PIC24FJ128GA310 FAMILY 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers with LCD Controller and XLP Technology Extreme Low-Power Features: Peripheral Features (Continued): • Multiple Power Management Options for Extreme • Seven Input Capture modules, each with a Power Reduction: Dedicated 16-Bit Timer - VBAT allows the device to transition to a backup • Seven Output Compare/PWM modules, each with a battery for the lowest power consumption with Dedicated 16-Bit Timer RTCC • Enhanced Parallel Master/Slave Port (EPMP/EPSP) - Deep Sleep allows near total power-down with the • Hardware Real-Time Clock/Calendar (RTCC): ability to wake-up on external triggers - Runs in Deep Sleep and VBAT modes - Sleep and Idle modes selectively shut down • Two 3-Wire/4-Wire SPI modules (support 4 Frame peripherals and/or core for substantial power modes) with 8-Level FIFO Buffer reduction and fast wake-up • Two I2C™ modules Support Multi-Master/Slave - Doze mode allows CPU to run at a lower clock mode and 7-Bit/10-Bit Addressing speed than peripherals • Four UART modules: • Alternate Clock modes Allow On-the-Fly Switching to - Support RS-485, RS-232 and LIN/J2602 a Lower Clock Speed for Selective Power Reduction - On-chip hardware encoder/decoder for IrDA® • Extreme Low-Power Current Consumption for - Auto-wake-up on Auto-Baud Detect Deep Sleep: - 4-level deep FIFO buffer - WDT: 270nA @ 3.3V typical • Programmable 32-Bit Cyclic Redundancy Check - RTCC: 400nA @ 32 kHz, 3.3V typical (CRC) Generator - Deep Sleep current, 40na, 3.3V typical • Digital Signal Modulator Provides On-Chip FSK and Peripheral Features: PSK Modulation for a Digital Signal Stream • Configurable Open-Drain Outputs on Digital I/O Pins • LCD Display Controller: • High-Current Sink/Source (18 mA/18 mA) on All I/O Pins - Up to 60 segments by 8 commons - Internal charge pump and low-power, internal Analog Features: resistor biasing • 10/12-Bit, 24-Channel Analog-to-Digital (A/D) Converter: - Operation in Sleep mode - Conversion rate of 500ksps (10-bit), 200ksps (12-bit) • Up to Five External Interrupt Sources - Conversion available during Sleep and Idle • Peripheral Pin Select (PPS): Allows Independent I/O • Three Rail-to-Rail Enhanced Analog Comparators Mapping of Many Peripherals with Programmable Input/Output Configuration • Five 16-Bit Timers/Counters with Prescaler: • On-Chip Programmable Voltage Reference - Can be paired as 32-bit timers/counters • Charge Time Measurement Unit (CTMU): • Six-Channel DMA supports All Peripheral modules: - Used for capacitive touch sensing, up to 24 channels - Minimizes CPU overhead and increases data - Time measurement down to 1ns resolution throughput - CTMU temperature sensing Memory Remappable Peripherals T A Device Pins Flash Program(bytes) Data SRAM(bytes) 16-Bit Timers Capture Input Compare/PWMOutput ®UART w/IrDA SPI 2IC™ 10/12-Bit ADC(ch) Comparators CTMU (ch) EPMP/EPSP LCD (pixels) JTAG Deep Sleep w/VB PIC24FJ128GA310 100 128K 8K 5 7 7 4 2 2 24 3 24 Y 480 Y Y PIC24FJ128GA308 80 128K 8K 5 7 7 4 2 2 16 3 16 Y 368 Y Y PIC24FJ128GA306 64 128K 8K 5 7 7 4 2 2 16 3 16 Y 240 Y Y PIC24FJ64GA310 100 64K 8K 5 7 7 4 2 2 24 3 24 Y 480 Y Y PIC24FJ64GA308 80 64K 8K 5 7 7 4 2 2 16 3 16 Y 368 Y Y PIC24FJ64GA306 64 64K 8K 5 7 7 4 2 2 16 3 16 Y 240 Y Y  2010-2014 Microchip Technology Inc. DS30009996G-page 1

PIC24FJ128GA310 FAMILY High-Performance CPU: Special Microcontroller Features: • Modified Harvard Architecture • Operating Voltage Range of 2.0V to 3.6V • Up to 16 MIPS Operation @ 32MHz • Two On-Chip Voltage Regulators (1.8V and 1.2V) for • 8MHz Internal Oscillator: Regular and Extreme Low-Power Operation - 4x PLL option • 20,000 Erase/Write Cycle Endurance Flash Program - Multiple clock divide options Memory, Typical - Fast start-up • Flash Data Retention: 20 Years Minimum • 17-Bit x 17-Bit Single-Cycle Hardware • Self-Programmable under Software Control Fractional/Integer Multiplier • Programmable Reference Clock Output • 32-Bit by 16-Bit Hardware Divider • In-Circuit Serial Programming™ (ICSP™) and • 16 x 16-Bit Working Register Array In-Circuit Emulation (ICE) via 2 Pins • C Compiler Optimized Instruction Set Architecture • JTAG Boundary Scan Support • Two Address Generation Units for Separate Read • Fail-Safe Clock Monitor Operation: and Write Addressing of Data Memory - Detects clock failure and switches to on-chip, low-power RC oscillator • Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Brown-out Reset (BOR) with Operation Below VBOR • High/Low-Voltage Detect (HLVD) • Flexible Watchdog Timer (WDT) with its Own RC Oscillator for Reliable Operation • Standard and Ultra Low-Power Watchdog Timers (ULPW) for Reliable Operation in Standard and Deep Sleep modes DS30009996G-page 2  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY Pin Diagrams 64-Pin TQFP, QFN(1) HLVDIN/CTED8/PMD4/CN62/RE4COM0/CTED9/PMD3/CN61/RE3COM1/PMD2/CN60/RE2COM2/PMD1/CN59/RE1COM3/PMD0/CN58/RE0COM4/SEG48/CN69/RF1SEG27/CN68/RF0VBATV/VCAPDDCOREC3INA/SEG26/CN16/RD7C3INB/SEG25/CN15/RD6RP20/SEG24/PMRD/CN14/RD5RP25/SEG23/PMWR/CN13/RD4RP22/SEG22/PMBE0/CN52/RD3RP23/SEG21/PMACK1/CN51/RD2RP24/SEG20/CN50/RD1 4321098765432109 6666655555555554 PMD5/CTED4/LCDBIAS2/CN63/RE5 1 48 SOSCO/RPI37/SCKLI/RC14 PMD6/LCDBIAS1/CN64/RE6 2 47 SOSCI/RC13 PMD7/LCDBIAS0/CN65/RE7 3 46 RP11/SEG17/CN49/RD0 C1IND/RP21/SEG0/PMA5/CN8/RG6 4 45 RP12/C3INC/SEG16/PMA14/CS1/CN56/RD11 VLCAP1/C1INC/RP26/PMA4/CN9/RG7 5 44 RP3/SEG15/PMA15/C3IND/CS2/CN55/RD10 VLCAP2/C2IND/RP19/PMA3/CN10/RG8 6 43 RP4/SEG14/PMACK2/CN54/RD9 MCLR 7 42 RP2/SEG13/RTCC/CN53/RD8 C2INC/RP27/SEG1/PMA2/CN11/RG9 8 PIC24FJXXXGA306 41 VSS VSS 9 40 OSCO/CLKO/CN22/RC15 VDD 10 39 OSCI/CLKI/CN23/RC12 PGEC3/AN5/C1INA/RP18/SEG2/CN7/RB5 11 38 VDD PGED3/AN4/C1INB/RP28/SEG3/CN6/RB4 12 37 SEG28/CN72/SCL1/RG2 AN3/C2INA/SEG4/CN5/RB3 13 36 SEG47/CN73/SDA1/RG3 AN2/C2INB/CTCMP/CTED13/RP13/SEG5/CN4/RB2 14 35 INT0/CN84/RF6 PGEC1/CVREF-/AN1/RP1/SEG6/CTED12/CN3/RB1 15 34 RP30/CN70/RF2 PGED1/CVREF+/AN0/RP0/SEG7/PMA6/CN2/RB0 16 33 RP16/SEG12/CN71/RF3 7890123456789012 1112222222222333 CN24/RB6CN25/RB7AVDDAVSSCN26/RB8CN27/RB9N28/RB10N29/RB11VSSVDD N30/RB12N31/RB13N32/RB14N12/RB15CN17/RF4CN18/RF5 PGEC2/AN6/RP6/LCDBIAS3/PGED2/AN7/RP7/ AN8/RP8/SEG31/COM7/AN9/RP9/SEG30/COM6/PMA7/TMS/CV/AN10/SEG29/COM5/PMA13/CREFTDO/AN11/PMA12/C TCK/AN12/CTED2/PMA11/SEG18/CTDI/AN13/SEG19/CTED1/PMA10/CRP14/SEG8/CTED5/CTPLS/PMA1/CAN14/AN15/RP29/SEG9/CTED6/REFO/PMA0/CRP10/SDA2/SEG10/PMA9/PMA8/RP17/SCL2/SEG11/ Legend: RPn and RPIn represent remappable pins for the Peripheral Pin Select feature. Shaded pins indicate pins that are tolerant up to +5.5V. Note1: Refer to Table4-22 for the list of analog ports.  2010-2014 Microchip Technology Inc. DS30009996G-page 3

PIC24FJ128GA310 FAMILY Pin Diagrams (Continued) 80-Pin TQFP(1) HLVDIN/CTED8/PMD4/CN62/RE4CTED9/COM0/PMD3/CN61/RE3COM1/PMD2/CN60/RE2COM2/PMD1/CN59/RE1COM3/PMD0/CN58/RE0SEG50/PMD8/CN77/RG0SEG46/PMD9/CN78/RG1COM4/SEG48/PMD10/CN69/RF1SEG27/PMD11/CN68/RF0VBAT/VVCAPDDCOREC3INA/SEG26/PMD15/CN16/RD7C3INB/SEG25/PMD14/CN15/RD6RP20/SEG24/PMRD/CN14/RD5RP25/SEG23/PMWR/CN13/RD4SEG45/PMD13/CN19/RD13RPI42/SEG44/PMD12/CN57/RD12RP22/SEG22/PMBE0/CN52/RD3RP23/SEG21/PMACK1/CN51/RD2RP24/SEG20/CN50/RD1 09876543210987654321 87777777777666666666 PMD5/CTED4/LCDBIAS2/CN63/RE5 1 60 RPI37/SOSCO/SCKLI/RC14 PMD6/LCDBIAS1/CN64/RE6 2 59 SOSCI/RC13 PMD7/LCDBIAS0/CN65/RE7 3 58 RP11/SEG17/CN49/RD0 RPI38/SEG32/CN45/RC1 4 57 RP12/C3INC/SEG16/PMA14/CS1/CN56/RD11 RPI40/SEG33/CN47/RC3 5 56 RP3/SEG15/C3IND/PMA15/CS2/CN55/RD10 C1IND/RP21/SEG0/PMA5/CN8/RG6 6 55 RP4/SEG14/PMACK2/CN54/RD9 VLCAP1/C1INC/RP26/PMA4/CN9/RG7 7 54 RP2/SEG13/RTCC/CN53/RD8 VLCAP2/C2IND/RP19/PMA3/CN10/RG8 8 53 RPI35/SEG43/PMBE1/CN44/RA15 MCLR 9 52 RPI36/SEG42/PMA22/CN43/RA14 C2INC/RP27/SEG1/PMA2/CN11/RG9 10 PIC24FJXXXGA308 51 VSS VSS 11 50 OSCO/CLKO/CN22/RC15 VDD 12 49 OSCI/CLKI/CN23/RC12 TMS/RPI33/SEG34/PMCS1/CN66/RE8 13 48 VDD TDO/RPI34/SEG35/PMA19/CN67/RE9 14 47 SEG28/SCL1/CN72/RG2 PGEC3/AN5/C1INA/RP18/SEG2/CN7/RB5 15 46 SEG47/SDA1/CN73/RG3 PGED3/AN4/C1INB/RP28/SEG3/CN6/RB4 16 45 INT0/CN84/RF6 AN3/C2INA/SEG4/CN5/RB3 17 44 CN83/RF7 AN2/C2INB/RP13/CTCMP/SEG5/CTED13/CN4/RB2 18 43 RP15/SEG41/CN74/RF8 PGEC1/CVREF-/AN1/RP1/SEG6/CTED12/CN3/RB1 19 42 RP30/SEG40/CN70/RF2 PGED1/CVREF+/AN0/RP0/SEG7/CN2/RB0 20 41 RP16/SEG12/CN71/RF3 12345678901234567890 22222222233333333334 PGEC2/AN6/RP6/LCDBIAS3/CN24/RB6PGED2/AN7/RP7/CN25/RB7-/SEG36/PMA7/CN41/RA9VREFV+/SEG37/PMA6/CN42/RA10REFAVDDAVSSAN8/RP8/SEG31/COM7/CN26/RB8RP9/SEG30/COM6/CN27/RB9AN9//AN10/SEG29/COM5/PMA13/CN28/RB10CVREFAN11/PMA12/CN29/RB11VssVDD TCK/AN12/CTED2/SEG18/PMA11/CN30/RB12TDI/AN13/CTED1/SEG19/PMA10/CN31/RB13AN14/RP14/SEG8/CTPLS/CTED5/PMA1/CN32/RB14RP29/SEG9/CTED6/REFO/PMA0/CN12/RB15AN15/RPI43/SEG38/CN20/RD14RP5/SEG39/CN21/RD15RP10/SEG10/SDA2/PMA9/CN17/RF4RP17/SEG11/SCL2/PMA8/CN18/RF5 Legend: RPn and RPIn represent remappable pins for the Peripheral Pin Select feature. Shaded pins indicate pins that are tolerant up to +5.5V. Note1: Refer to Table4-22 for the list of analog ports. DS30009996G-page 4  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY Pin Diagrams (Continued) 100-Pin TQFP(1) 4 E R 2/ 4 SEG63/PMD4/HLVDIN/CTED8/CN6COM0/PMD3/CTED9/CN61/RE3COM1/PMD2/CN60/RE2SEG62/CTED10/CN80/RG13SEG61/CN79/RG12SEG60/PMA16/CTED11/CN81/RG1COM2/PMD1/CN59/RE1COM3/PMD0/CN58/RE0AN22/SEG59/PMA17/CN40/RA7AN23/SEG58/CN39/RA6SEG50/PMD8/CN77/RG0SEG46/PMD9/CN78/RG1COM4/SEG48/PMD10/CN69/RF1SEG27/PMD11/CN68/RF0VBATV/VCAPDDCOREC3INA/SEG26/PMD15/CN16/RD7C3INB/SEG25/PMD14/CN15/RD6RP20/SEG24/PMRD/CN14/RD5RP25/SEG23/PMWR/CN13/RD4SEG45/PMD13/CN19/RD13RPI42/SEG44/PMD12/CN57/RD12RP22/SEG22/PMBE0/CN52/RD3RP23/SEG21/PMACK1/CN51/RD2RP24/SEG20/CN50/RD1 0987654321098765432109876 0999999999988888888887777 SEG51/CTED3/CN82/RG15 1 1 75 VSS VDD 2 74 RPI37/SOSCO/SCLKI/RC14 CTED4/PMD5/LCDBIAS2/CN63/RE5 3 73 SOSCI/RC13 PMD6/LCDBIAS1/CN64/RE6 4 72 RP11/SEG17/CN49/RD0 PMD7/LCDBIAS0/CN65/RE7 5 71 RP12/SEG16/C3INC/PMA14/CS1/CN56/RD11 RPI38/SEG32/CN45/RC1 6 70 RP3/SEG15/C3IND/PMA15/CS2/CN55/RD10 RPI39/SEG52/CN46/RC2 7 69 RP4/SEG14/PMACK2/CN54/RD9 RPI40/SEG33/CN47/RC3 8 68 RP2/SEG13/RTCC/CN53/RD8 AN16/RPI41/SEG53/PMCS2/CN48/RC4 9 67 RPI35/SEG43/PMBE1/CN44/RA15 AN17/C1IND/RP21/SEG0/PMA5/CN8/RG6 10 66 RPI36/SEG42/PMA22/CN43/RA14 VLCAP1/AN18/C1INC/RP26/PMA4/CN9/RG7 11 65 VSS VLCAP2/AN19/C2IND/RP19/PMA3/CN10/RG8 12 PIC24FJXXXGA310 64 OSCO/CLKO/CN22/RC15 MCLR 13 63 OSCI/CLKI/CN23/RC12 AN20/C2INC/RP27/SEG1/PMA2/CN11/RG9 14 62 VDD VSS 15 61 TDO/CN38/RA5 VDD 16 60 TDI/PMA21/CN37/RA4 TMS/CTED0/SEG49/CN33/RA0 17 59 SDA2/SEG57/PMA20/CN36/RA3 RPI33/SEG34/PMCS1/CN66/RE8 18 58 SCL2/SEG56/CN35/RA2 AN21/RPI34/SEG35/PMA19/CN67/RE9 19 57 SCL1/SEG28/CN72/RG2 PGEC3/AN5/C1INA/RP18/SEG2/CN7/RB5 20 56 SDA1/SEG47/CN73/RG3 PGED3/AN4/C1INB/RP28/SEG3/CN6/RB4 21 55 INT0/CN84/RF6 AN3/C2INA/SEG4/CN5/RB3 22 54 CN83/RF7 AN2/C2INB/RP13/SEG5/CTED13/CTCMP/CN4/RB2 23 53 RP15/SEG41/CN74/RF8 PGEC1/CVREF-/AN1/RP1/SEG6/CTED12/CN3/RB1 24 52 RP30/SEG40/CN70/RF2 PGED1/CVREF+/AN0/RP0/SEG7/CN2/RB0 25 51 RP16/SEG12/CN71/RF3 6789012345678901234567890 2222333333333344444444445 PGEC2/AN6/RP6/LCDBIAS3/CN24/RB6PGED2/AN7/RP7/CN25/RB7V-/SEG36/PMA7/CN41/RA9REFV+/SEG37/PMA6/CN42/RA10REFAVDDAVSSAN8/RP8/SEG31/COM7/CN26/RB8AN9/RP9/SEG30/COM6/CN27/RB9CV/AN10/SEG29/COM5/PMA13/CN28/RB10REFAN11/PMA12/CN29/RB11VSSVDDTCK/CN34/RA1RP31/SEG54/CN76/RF13RPI32/SEG55/CTED7/PMA18/CN75/RF12AN12/CTED2/SEG18/PMA11/CN30/RB12AN13/CTED1/PMA10/SEG19/CN31/RB13AN14/RP14/SEG8/CTPLS/CTED5/PMA1/CN32/RB14AN15/RP29/SEG9/REFO/CTED6/PMA0/CN12/RB15VSSVDDRPI43/SEG38/CN20/RD14RP5/SEG39/CN21/RD15RP10/SEG10/PMA9/CN17/RF4RP17/SEG11/PMA8/CN18/RF5 Legend: RPn and RPIn represent remappable pins for the Peripheral Pin Select feature. Shaded pins indicate pins that are tolerant up to +5.5V. Note1: Refer to Table4-22 for the list of analog ports.  2010-2014 Microchip Technology Inc. DS30009996G-page 5

PIC24FJ128GA310 FAMILY Pin Diagrams (Continued) 121-Pin BGA (Top View)(1,2) 1 2 3 4 5 6 7 8 9 10 11 A RE4 RE3 RG13 RE0 RG0 RF1 VBAT N/C RD12 RD2 RD1 B N/C RG15 RE2 RE1 RA7 RF0 VCAP/ RD5 RD3 VSS RC14 VDDCORE C RE6 VDD RG12 RG14 RA6 N/C RD7 RD4 N/C RC13 RD11 D RC1 RE7 RE5 N/C N/C N/C RD6 RD13 RD0 N/C RD10 E RC4 RC3 RG6 RC2 N/C RG1 N/C RA15 RD8 RD9 RA14 F MCLR RG8 RG9 RG7 VSS N/C N/C VDD OSCI/ VSS OSCO/ RC12 RC15 G RE8 RE9 RA0 N/C VDD VSS VSS N/C RA5 RA3 RA4 H RB5 RB4 N/C N/C N/C VDD N/C RF7 RF6 RG2 RA2 J RB3 RB2 RB7 AVDD RB11 RA1 RB12 N/C N/C RF8 RG3 K RB1 RB0 RA10 RB8 N/C RF12 RB14 VDD RD15 RF3 RF2 L RB6 RA9 AVSS RB9 RB10 RF13 RB13 RB15 RD14 RF4 RF5 Legend: Shaded pins indicate pins that are tolerant up to +5.5V. Note1: See Table1 for complete pinout descriptions. 2: Refer to Table4-22 for the list of analog ports. DS30009996G-page 6  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 1: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN DEVICES Pin Function Pin Function A1 SEG63/PMD4/HLVDIN/CTED8/CN62/RE4 E1 AN16/RPI41/SEG53/PMCS2/CN48/RC4 A2 COM0/PMD3/CTED9/CN61/RE3 E2 RPI40/SEG33/CN47/RC3 A3 SEG62/CTED10/CN80/RG13 E3 AN17/C1IND/RP21/SEG0/PMA5/CN8/RG6 A4 COM3/PMD0/CN58/RE0 E4 RPI39/SEG52/CN46/RC2 A5 SEG50/PMD8/CN77/RG0 E5 N/C A6 SEG48/COM4/PMD10/CN69/RF1 E6 SEG46/PMD9/CN78/RG1 A7 VBAT E7 N/C A8 N/C E8 RPI35/SEG43/PMBE1/CN44/RA15 A9 RPI42/SEG44/PMD12/CN57/RD12 E9 RP2/SEG13/RTCC/CN53/RD8 A10 RP23/SEG21/PMACK1/CN51/RD2 E10 RP4/SEG14/PMACK2/CN54/RD9 A11 RP24/SEG20/CN50/RD1 E11 RPI36/SEG42/PMA22/CN43/RA14 B1 N/C F1 MCLR B2 SEG51/CTED3/CN82/RG15 F2 VLCAP2/AN19/C2IND/RP19/PMA3/CN10/RG8 B3 COM1/PMD2/CN60/RE2 F3 AN20/C2INC/RP27/SEG1/PMA2/CN11/RG9 B4 COM2/PMD1/CN59/RE1 F4 VLCAP1/AN18/C1INC/RP26/PMA4/CN9/RG7 B5 AN22/SEG59/PMA17/CN40/RA7 F5 VSS B6 SEG27/PMD11/CN68/RF0 F6 N/C B7 VCAP F7 N/C B8 RP20/SEG24/PMRD/CN14/RD5 F8 VDD B9 RP22/SEG22/PMBE0/CN52/RD3 F9 OSCI/CLKI/CN23/RC12 B10 VSS F10 VSS B11 RPI37/SOSCO/SCLKI/RC14 F11 OSCO/CLKO/CN22/RC15 C1 PMD6/LCDBIAS1/CN64/RE6 G1 RPI33/SEG34/PMCS1/CN66/RE8 C2 VDD G2 AN21/RPI34/SEG35/PMPA19/CN67/RE9 C3 SEG61/CN79/RG12 G3 TMS/SEG49/CTED0/CN33/RA0 C4 SEG60/PMA16/CTED11/CN81/RG14 G4 N/C C5 AN23/SEG58/CN39/RA6 G5 VDD C6 N/C G6 VSS C7 C3INA/SEG26/PMD15/CN16/RD7 G7 VSS C8 RP25/SEG23/PMWR/CN13/RD4 G8 N/C C9 N/C G9 TDO/CN38/RA5 C10 SOSCI/RC13 G10 SDA2/SEG57/PMA20/CN36/RA3 C11 RP12/SEG16/C3INC/PMA14/CS1/CN56/RD11 G11 TDI/PMA21/CN37/RA4 D1 RPI38/SEG32/CN45/RC1 H1 PGEC3/AN5/C1INA/RP18/SEG2/CN7/RB5 D2 PMD7/LCDBIAS0/CN65/RE7 H2 PGED3/AN4/C1INB/RP28/SEG3/CN6/RB4 D3 PMD5/CTED4/LCDBIAS2/CN63/RE5 H3 N/C D4 N/C H4 N/C D5 N/C H5 N/C D6 N/C H6 VDD D7 C3INB/SEG25/PMD14/CN15/RD6 H7 N/C D8 SEG45/PMD13/CN19/RD13 H8 CN83/RF7 D9 RP11/SEG17/CN49/RD0 H9 INT0/CN84/RF6 D10 N/C H10 SCL1/SEG28/CN72/RG2 D11 RP3/SEG15/C3IND/PMA15/CS2/CN55/RD10 H11 SCL2/SEG56/CN35/RA2 Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select functions.  2010-2014 Microchip Technology Inc. DS30009996G-page 7

PIC24FJ128GA310 FAMILY TABLE 1: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN DEVICES (CONTINUED) Pin Function Pin Function J1 AN3/C2INA/SEG4/CN5/RB3 K7 AN14/RP14/SEG8/CTPLS/CTED5/PMA1/CN32/RB14 J2 AN2/C2INB/RP13/SEG5/CTCMP/CTED13/CN4/RB2 K8 VDD J3 PGED2/AN7/RP7/CN25/RB7 K9 RP5/SEG39/CN21/RD15 J4 AVDD K10 RP16/SEG12/CN71/RF3 J5 AN11/PMA12/CN29/RB11 K11 RP30/SEG40/CN70/RF2 J6 TCK/CN34/RA1 L1 PGEC2/AN6/RP6/LCDBIAS3/CN24/RB6 J7 AN12/SEG18/CTED2/PMA11/CN30/RB12 L2 VREF-/SEG36/PMA7/CN41/RA9 J8 N/C L3 AVSS J9 N/C L4 AN9/RP9/COM6/SEG30/CN27/RB9 J10 RP15/SEG41/CN74/RF8 L5 CVREF/AN10/COM5/SEG29/PMA13/CN28/RB10 J11 SDA1/SEG47/CN73/RG3 L6 RP31/SEG54/CN76/RF13 K1 PGEC1/CVREF-/AN1/RP1/SEG6/CTED12/CN3/RB1 L7 AN13/SEG19/CTED1/PMA10/CN31/RB13 K2 PGD1/CVREF+/AN0/RP0/SEG7/CN2/RB0 L8 AN15/RP29/SEG9/CTED6/REFO/PMA0/CN12/RB15 K3 VREF+/SEG37/PMA6/CN42/RA10 L9 RPI43/SEG38/CN20/RD14 K4 AN8/RP8/COM7/SEG31/CN26/RB8 L10 RP10/SEG10/PMA9/CN17/RF4 K5 N/C L11 RP17/SEG11/PMA8/CN18/RF5 K6 RPI32/SEG55/CTED7/PMA18/CN75/RF12 Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select functions. DS30009996G-page 8  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY Table of Contents 1.0 Device Overview........................................................................................................................................................................11 2.0 Guidelines for Getting Started with 16-bit Microcontrollers........................................................................................................29 3.0 CPU ...........................................................................................................................................................................................35 4.0 Memory Organization.................................................................................................................................................................41 5.0 Direct Memory Access Controller (DMA)...................................................................................................................................75 6.0 Flash Program Memory..............................................................................................................................................................83 7.0 Resets........................................................................................................................................................................................89 8.0 Interrupt Controller.....................................................................................................................................................................95 9.0 Oscillator Configuration............................................................................................................................................................145 10.0 Power-Saving Features............................................................................................................................................................155 11.0 I/O Ports...................................................................................................................................................................................167 12.0 Timer1......................................................................................................................................................................................197 13.0 Timer2/3 and Timer4/5 ............................................................................................................................................................199 14.0 Input Capture with Dedicated Timers.......................................................................................................................................205 15.0 Output Compare with Dedicated Timers..................................................................................................................................211 16.0 Serial Peripheral Interface (SPI)...............................................................................................................................................221 17.0 Inter-Integrated Circuit™ (I2C™)..............................................................................................................................................233 18.0 Universal Asynchronous Receiver Transmitter (UART)...........................................................................................................241 19.0 Data Signal Modulator..............................................................................................................................................................249 20.0 Enhanced Parallel Master Port (EPMP)...................................................................................................................................253 21.0 Liquid Crystal Display (LCD) Controller....................................................................................................................................265 22.0 Real-Time Clock and Calendar (RTCC) ..................................................................................................................................275 23.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator........................................................................................289 24.0 12-Bit A/D Converter (ADC) with Threshold Scan....................................................................................................................295 25.0 Triple Comparator Module........................................................................................................................................................315 26.0 Comparator Voltage Reference................................................................................................................................................321 27.0 Charge Time Measurement Unit (CTMU)................................................................................................................................323 28.0 High/Low-Voltage Detect (HLVD).............................................................................................................................................331 29.0 Special Features......................................................................................................................................................................333 30.0 Development Support...............................................................................................................................................................347 31.0 Instruction Set Summary..........................................................................................................................................................351 32.0 Electrical Characteristics..........................................................................................................................................................359 33.0 Packaging Information..............................................................................................................................................................389 Appendix A: Revision History.............................................................................................................................................................407 Index................................................................................................................................................................................................. 409 The Microchip Web Site.....................................................................................................................................................................415 Customer Change Notification Service..............................................................................................................................................415 Customer Support..............................................................................................................................................................................415 Product Identification System............................................................................................................................................................417  2010-2014 Microchip Technology Inc. DS30009996G-page 9

PIC24FJ128GA310 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS30009996G-page 10  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 1.0 DEVICE OVERVIEW Aside from these new features, PIC24FJ128GA310 family devices also include all of the legacy power-saving This document contains device-specific information for features of previous PIC24F microcontrollers, such as: the following devices: • On-the-Fly Clock Switching, allowing the selection • PIC24FJ64GA306 • PIC24FJ128GA306 of a lower power clock during run time • PIC24FJ64GA308 • PIC24FJ128GA308 • Doze Mode Operation, for maintaining peripheral clock speed while slowing the CPU clock • PIC24FJ64GA310 • PIC24FJ128GA310 • Instruction-Based Power-Saving Modes, for quick The PIC24FJ128GA310 family adds many new features invocation of Idle and the many Sleep modes. to Microchip‘s 16-bit microcontrollers, including new ultra low-power features, Direct Memory Access (DMA) 1.1.3 OSCILLATOR OPTIONS AND for peripherals, and a built-in LCD Controller and Driver. FEATURES Together, these provide a wide range of powerful features in one economical and power-saving package. All of the devices in the PIC24FJ128GA310 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These 1.1 Core Features include: 1.1.1 16-BIT ARCHITECTURE • Two Crystal modes Central to all PIC24F devices is the 16-bit modified • Two External Clock modes Harvard architecture, first introduced with Microchip’s • A Phase Lock Loop (PLL) frequency multiplier, dsPIC® Digital Signal Controllers (DSCs). The PIC24F which allows clock speeds of up to 32MHz CPU core offers a wide range of enhancements, such as: • A Fast Internal Oscillator (FRC) (nominal 8MHz output) with multiple frequency divider options • 16-bit data and 24-bit address paths with the ability to move information between data and • A separate Low-Power Internal RC Oscillator memory spaces (LPRC) (31 kHz nominal) for low-power, timing-insensitive applications. • Linear addressing of up to 12 Mbytes (program space) and 32 Kbytes (data) The internal oscillator block also provides a stable • A 16-element Working register array with built-in reference source for the Fail-Safe Clock Monitor software stack support (FSCM). This option constantly monitors the main clock source against a reference signal provided by the inter- • A 17 x 17 hardware multiplier with support for nal oscillator and enables the controller to switch to the integer math internal oscillator, allowing for continued low-speed • Hardware support for 32 by 16-bit division operation or a safe application shutdown. • An instruction set that supports multiple addressing modes and is optimized for high-level 1.1.4 EASY MIGRATION languages, such as ‘C’ Regardless of the memory size, all devices share the • Operational performance up to 16 MIPS same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The 1.1.2 XLP POWER-SAVING consistent pinout scheme used throughout the entire TECHNOLOGY family also aids in migrating from one device to the next The PIC24FJ128GA310 family of devices introduces a larger, or even in jumping from 64-pin to 100-pin greatly expanded range of power-saving operating devices. modes for the ultimate in power conservation. The new The PIC24F family is pin compatible with devices in the modes include: dsPIC33 family, and shares some compatibility with the • Retention Sleep with essential circuits being pinout schema for PIC18 and dsPIC30. This extends powered from a separate low-voltage regulator the ability of applications to grow from the relatively • Deep Sleep without RTCC for the lowest possible simple, to the powerful and complex, yet still selecting power consumption under software control a Microchip device. • VBAT mode (with or without RTCC) to continue limited operation from a backup battery when VDD is removed Many of these new low-power modes also support the continuous operation of the low-power, on-chip Real-Time Clock/Calendar (RTCC), making it possible for an application to keep time while the device is otherwise asleep.  2010-2014 Microchip Technology Inc. DS30009996G-page 11

PIC24FJ128GA310 FAMILY 1.2 DMA Controller • Enhanced Parallel Master/Parallel Slave Port: This module allows rapid and transparent access PIC24FJ128GA310 family devices also introduce a to the microcontroller data bus, and enables the new Direct Memory Access Controller (DMA) to the CPU to directly address external data memory. The PIC24F architecture. This module acts in concert with parallel port can function in Master or Slave mode, the CPU, allowing data to move between data memory accommodating data widths of 4, 8 or 16 bits, and and peripherals without the intervention of the CPU, address widths up to 23 bits in Master modes. increasing data throughput and decreasing execution • Real-Time Clock and Calendar (RTCC): This time overhead. Six independently programmable chan- module implements a full-featured clock and nels make it possible to service multiple peripherals at calendar with alarm functions in hardware, freeing virtually the same time, with each channel peripheral up timer resources and program memory space performing a different operation. Many types of data for use of the core application. transfer operations are supported. • Data Signal Modulator (DSM): The Data Signal Modulator (DSM) allows the user to mix a digital 1.3 LCD Controller data stream (the “modulator signal”) with a carrier With the PIC24FJ128GA310 family of devices, signal to produce a modulated output. Microchip introduces its versatile Liquid Crystal Display (LCD) controller and driver to the PIC24F family. The 1.5 Details on Individual Family on-chip LCD driver includes many features that make Members the integration of displays in low-power applications easier. These include an integrated voltage regulator Devices in the PIC24FJ128GA310 family are available with charge pump, and an integrated internal resistor in 64-pin, 80-pin and 100-pin packages. The general ladder that allows contrast control in software and block diagram for all devices is shown in Figure1-1. display operation above device VDD. The devices are differentiated from each other in sixways: 1.4 Other Special Features 1. Flash program memory (64 Kbytes for • Peripheral Pin Select: The Peripheral Pin Select PIC24FJ64GA3XX devices and 128 Kbytes for (PPS) feature allows most digital peripherals to be PIC24FJ128GA3XX devices). mapped over a fixed set of digital I/O pins. Users 2. Available I/O pins and ports (53 pins on 6 ports may independently map the input and/or output of for 64-pin devices, 69 pins on 7 ports for 80-pin any one of the many digital peripherals to any one devices and 85 pins on 7 ports for 100-pin of the I/O pins. devices). • Communications: The PIC24FJ128GA310 family 3. Available Interrupt-on-Change Notification (ICN) incorporates a range of serial communication inputs (52 on 64-pin devices, 66 on 80-pin peripherals to handle a range of application devices and 82 on 100-pin devices). requirements. There are two independent I2C™ 4. Available remappable pins (29 pins on 64-pin modules that support both Master and Slave devices, 40 on 80-pin devices and 44 pins on modes of operation. Devices also have, through 100-pin devices). the PPS feature, four independent UARTs with 5. Maximum available drivable LCD pixels (272 on built-in IrDA® encoders/decoders and two SPI 64-pin devices, 368 on 80-pin devices and modules. 480on 100-pin devices). • Analog Features: All members of the 6. Analog input channels (16 channels for 64-pin PIC24FJ128GA310 family include the new 12-bit and 80-pin devices, and 24 channels for 100-pin A/D Converter (ADC) module and a triple compar- devices). ator module. The ADC module incorporates a All other features for devices in this family are identical. range of new features that allow the converter to These are summarized in Table1-1, Table1-2 and assess and make decisions on incoming data, Table1-3. reducing CPU overhead for routine ADC conver- sions. The comparator module includes three A list of the pin features available on the analog comparators that are configurable for a PIC24FJ128GA310 family devices, sorted by function, wide range of operations. is shown in Table1-4. Note that this table shows the pin • CTMU Interface: In addition to their other analog location of individual peripheral features and not how features, members of the PIC24FJ128GA310 they are multiplexed on the same pin. This information is family include the CTMU interface module. This provided in the pinout diagrams in the beginning of this provides a convenient method for precision time data sheet. Multiplexed features are sorted by the priority measurement and pulse generation, and can given to a feature, with the highest priority peripheral serve as an interface for capacitive sensors. being listed first. DS30009996G-page 12  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ128GA310 FAMILY: 64-PIN Features PIC24FJ64GA306 PIC24FJ128GA306 Operating Frequency DC – 32 MHz Program Memory (bytes) 64K 128K Program Memory (instructions) 22,016 44,032 Data Memory (bytes) 8K Interrupt Sources (soft vectors/ 65 (61/4) NMI traps) I/O Ports Ports B, C, D, E, F, G Total I/O Pins 53 Remappable Pins 30 (29 I/Os, 1 input only) Timers: Total Number (16-bit) 5(1) 32-Bit (from paired 16-bit timers) 2 Input Capture Channels 7(1) Output Compare/PWM Channels 7(1) Input Change Notification Interrupt 52 Serial Communications: UART 4(1) SPI (3-wire/4-wire) 2(1) I2C™ 2 Digital Signal Modulator Yes Parallel Communications (EPMP/PSP) Yes JTAG Boundary Scan Yes 12/10-Bit Analog-to-Digital Converter 16 (ADC) Module (input channels) Analog Comparators 3 CTMU Interface Yes LCD Controller (available pixels) 240 (30 SEG x 8 COM) Resets (and Delays) Core POR, VDD POR, VBAT POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (OST, PLL Lock) Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations Packages 64-Pin TQFP and QFN Note 1: Peripherals are accessible through remappable pins.  2010-2014 Microchip Technology Inc. DS30009996G-page 13

PIC24FJ128GA310 FAMILY TABLE 1-2: DEVICE FEATURES FOR THE PIC24FJ128GA310 FAMILY: 80-PIN Features PIC24FJ64GA308 PIC24FJ128GA308 Operating Frequency DC – 32 MHz Program Memory (bytes) 64K 128K Program Memory (instructions) 22,016 44,032 Data Memory (bytes) 8K Interrupt Sources (soft vectors/ 65 (61/4) NMI traps) I/O Ports Ports A, B, C, D, E, F, G Total I/O Pins 69 Remappable Pins 40 (31 I/Os, 9 input only) Timers: Total Number (16-bit) 5(1) 32-Bit (from paired 16-bit timers) 2 Input Capture Channels 7(1) Output Compare/PWM Channels 7(1) Input Change Notification Interrupt 66 Serial Communications: UART 4(1) SPI (3-wire/4-wire) 2(1) I2C™ 2 Digital Signal Modulator Yes Parallel Communications (EPMP/PSP) Yes JTAG Boundary Scan Yes 12/10-Bit Analog-to-Digital Converter 16 (ADC) Module (input channels) Analog Comparators 3 CTMU Interface Yes LCD Controller (available pixels) 368 (46 SEG x 8 COM) Resets (and Delays) Core POR, VDD POR, VBAT POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (OST, PLL Lock) Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations Packages 80-Pin TQFP and QFN Note 1: Peripherals are accessible through remappable pins. DS30009996G-page 14  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 1-3: DEVICE FEATURES FOR THE PIC24FJ128GA310 FAMILY: 100-PIN DEVICES Features PIC24FJ64GA310 PIC24FJ128GA310 Operating Frequency DC – 32 MHz Program Memory (bytes) 64K 128K Program Memory (instructions) 22,016 44,032 Data Memory (bytes) 8K Interrupt Sources (soft vectors/NMI 66 (62/4) traps) I/O Ports Ports A, B, C, D, E, F, G Total I/O Pins 85 Remappable Pins 44 (32 I/Os, 12 input only) Timers: Total Number (16-bit) 5(1) 32-Bit (from paired 16-bit timers) 2 Input Capture Channels 7(1) Output Compare/PWM Channels 7(1) Input Change Notification Interrupt 82 Serial Communications: UART 4(1) SPI (3-wire/4-wire) 2(1) I2C™ 2 Digital Signal Modulator Yes Parallel Communications Yes (EPMP/PSP) JTAG Boundary Scan Yes 12/10-Bit Analog-to-Digital Converter 24 (ADC) Module (input channels) Analog Comparators 3 CTMU Interface Yes LCD Controller (available pixels) 480 (60 SEG x 8 COM) Resets (and delays) Core POR, VDD POR, VBAT POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (OST, PLL Lock) Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations Packages 100-Pin TQFP and 121-Pin BGA Note 1: Peripherals are accessible through remappable pins.  2010-2014 Microchip Technology Inc. DS30009996G-page 15

PIC24FJ128GA310 FAMILY FIGURE 1-1: PIC24FJ128GA310 FAMILY GENERAL BLOCK DIAGRAM Data Bus Interrupt Controller PORTA(1) 16 8 16 16 (12 I/O) EDS and Data Latch Table Data DMA Access Control PCH PCL DataRAM Controller 23 Program Counter Address Stack Repeat Latch PORTB Control Control Logic Logic (16 I/O) 16 23 16 16 Address Latch Read AGU Write AGU Program Memory/ PORTC(1) Extended Data Space (8 I/O) Data Latch Address Bus EA MUX 16 24 16 16 Inst Latch PORTD(1) Literal Data (16 I/O) Inst Register DMA Data Bus Instruction Control Signals Decode and Control PORTE(1) Divide OSCO/CLKO Support 16 x 16 (10 I/O) OSCI/CLKI 17x17 W Reg Array Timing Power-up Multiplier Generation Timer Oscillator REFO FRC/LPRC Start-up Timer PORTF(1) Oscillators Power-on 16-Bit ALU Reset (10 I/O) 16 Precision Band Gap Watchdog Reference Timer HLVD & Voltage BOR(2) Regulators PORTG(1) (12 I/O) VCAP VBAT VDD, VSS MCLR 12-Bit Digital Timer1 Timer2/3(3) Timer4/5(3) RTCC Comparators(3) ADC Modulator EPMP/PSP 1-I7C(3) OC1-/P7(W3)M ICNs(1) 1S/2P(3I) I21C/2™ 1/U2A/3R/4T(3) CTMU DLrCivDer Note1: Not all I/O pins or features are implemented on all device pinout configurations. See Table1-4 for specific implementations by pin count. 2: BOR functionality is provided when the on-board voltage regulator is enabled. 3: These peripheral I/Os are only accessible through remappable pins. DS30009996G-page 16  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS Pin Number/Grid Locater Pin Input I/O Description Function 64-Pin 80-Pin 100-Pin 121-Pin Buffer TQFP TQFP TQFP BGA AN0 16 20 25 K2 I ANA ADC Analog Inputs. AN1 15 19 24 K1 I ANA AN2 14 18 23 J2 I ANA AN3 13 17 22 J1 I ANA AN4 12 16 21 H2 I ANA AN5 11 15 20 H1 I ANA AN6 17 21 26 L1 I ANA AN7 18 22 27 J3 I ANA AN8 21 27 32 K4 I ANA AN9 22 28 33 L4 I ANA AN10 23 29 34 L5 I ANA AN11 24 30 35 J5 I ANA AN12 27 33 41 J7 I ANA AN13 28 34 42 L7 I ANA AN14 29 35 43 K7 I ANA AN15 30 36 44 L8 I ANA AN16 — — 9 E1 I ANA AN17 — — 10 E3 I ANA AN18 — — 11 F4 I ANA AN19 — — 12 F2 I ANA AN20 — — 14 F3 I ANA AN21 — — 19 G2 I ANA AN22 — — 92 B5 I ANA AN23 — — 91 C5 I ANA AVDD 19 25 30 J4 P — Positive Supply for Analog modules. AVSS 20 26 31 L3 P — Ground Reference for Analog modules. C1INA 11 15 20 H1 I ANA Comparator 1 Input A. C1INB 12 16 21 H2 I ANA Comparator 1 Input B. C1INC 5 7 11 F4 I ANA Comparator 1 Input C. C1IND 4 6 10 E3 I ANA Comparator 1 Input D. C2INA 13 17 22 J1 I ANA Comparator 2 Input A. C2INB 14 18 23 J2 I ANA Comparator 2 Input B. C2INC 8 10 14 F3 I ANA Comparator 2 Input C. C2IND 6 8 12 F2 I ANA Comparator 2 Input D. C3INA 55 69 84 C7 I ANA Comparator 3 Input A. C3INB 54 68 83 D7 I ANA Comparator 3 Input B. C3INC 45 57 71 C11 I ANA Comparator 3 Input C. C3IND 44 56 70 D11 I ANA Comparator 3 Input D. CLKI 39 49 63 F9 I ANA Main Clock Input Connection. CLKO 40 50 64 F11 O — System Clock Output. Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer  2010-2014 Microchip Technology Inc. DS30009996G-page 17

PIC24FJ128GA310 FAMILY TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locater Pin Input I/O Description Function 64-Pin 80-Pin 100-Pin 121-Pin Buffer TQFP TQFP TQFP BGA CN2 16 20 25 K2 I ST Interrupt-on-Change Inputs. CN3 15 19 24 K1 I ST CN4 14 18 23 J2 I ST CN5 13 17 22 J1 I ST CN6 12 16 21 H2 I ST CN7 11 15 20 H1 I ST CN8 4 6 10 E3 I ST CN9 5 7 11 F4 I ST CN10 6 8 12 F2 I ST CN11 8 10 14 F3 I ST CN12 30 36 44 L8 I ST CN13 52 66 81 C8 I ST CN14 53 67 82 B8 I ST CN15 54 68 83 D7 I ST CN16 55 69 84 C7 I ST CN17 31 39 49 L10 I ST CN18 32 40 50 L11 I ST CN19 — 65 80 D8 I ST CN20 — 37 47 L9 I ST CN21 — 38 48 K9 I ST CN22 40 50 64 F11 I ST CN23 39 49 63 F9 I ST CN24 17 21 26 L1 I ST CN25 18 22 27 J3 I ST CN26 21 27 32 K4 I ST CN27 22 28 33 L4 I ST CN28 23 29 34 L5 I ST CN29 24 30 35 J5 I ST CN30 27 33 41 J7 I ST CN31 28 34 42 L7 I ST CN32 29 35 43 K7 I ST CN33 — — 17 G3 I ST CN34 — — 38 J6 I ST CN35 — — 58 H11 I ST CN36 — — 59 G10 I ST CN37 — — 60 G11 I ST CN38 — — 61 G9 I ST CN39 — — 91 C5 I ST CN40 — — 92 B5 I ST CN41 — 23 28 L2 I ST CN42 — 24 29 K3 I ST CN43 — 52 66 E11 I ST Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer DS30009996G-page 18  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locater Pin Input I/O Description Function 64-Pin 80-Pin 100-Pin 121-Pin Buffer TQFP TQFP TQFP BGA CN44 — 53 67 E8 I ST Interrupt-on-Change Inputs. CN45 — 4 6 D1 I ST CN46 — — 7 E4 I ST CN47 — 5 8 E2 I ST CN48 — — 9 E1 I ST CN49 46 58 72 D9 I ST CN50 49 61 76 A11 I ST CN51 50 62 77 A10 I ST CN52 51 63 78 B9 I ST CN53 42 54 68 E9 I ST CN54 43 55 69 E10 I ST CN55 44 56 70 D11 I ST CN56 45 57 71 C11 I ST CN57 — 64 79 A9 I ST CN58 60 76 93 A4 I ST CN59 61 77 94 B4 I ST CN60 62 78 98 119 I ST CN61 63 79 99 A2 I ST CN62 64 80 100 A1 I ST CN63 1 1 3 D3 I ST CN64 2 2 4 C1 I ST CN65 3 3 5 D2 I ST CN66 — 13 18 G1 I ST CN67 — 14 19 G2 I ST CN68 58 72 87 B6 I ST CN69 59 73 88 A6 I ST CN70 34 42 52 K11 I ST CN71 33 41 51 K10 I ST CN72 37 47 57 H10 I ST CN73 36 46 56 J11 I ST CN74 — 43 53 J10 I ST CN75 — — 40 K6 I ST CN76 — — 39 L6 I ST CN77 — 75 90 A5 I ST CN78 — 74 89 E6 I ST CN79 — — 96 C3 I ST CN80 — — 97 A3 I ST CN81 — — 95 C4 I ST CN82 — — 1 B2 I ST CN83 — 44 54 H8 I ST CN84 35 45 55 H9 I ST Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer  2010-2014 Microchip Technology Inc. DS30009996G-page 19

PIC24FJ128GA310 FAMILY TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locater Pin Input I/O Description Function 64-Pin 80-Pin 100-Pin 121-Pin Buffer TQFP TQFP TQFP BGA COM0 63 79 99 A2 O — LCD Driver Common Outputs. COM1 62 78 98 B3 O — COM2 61 77 94 B4 O — COM3 60 76 93 A4 O — COM4 59 73 88 A6 O — COM5 23 29 34 L5 O — COM6 22 28 33 L4 O — COM7 21 27 32 K4 O — CS1 45 57 71 C11 I/O ST/TTL Parallel Master Port Chip Select 1 Strobe (shared with PMA14). CS2 44 56 70 D11 O — Parallel Master Port Chip Select 2 Strobe (shared with PMA15). CTCMP 14 18 23 J2 I ANA CTMU Comparator 2 Input (Pulse mode). CTED0 — — 17 G3 I DIG CTMU External Edge Inputs. CTED1 28 34 42 L7 I DIG CTED2 27 33 41 J7 I DIG CTED3 — — 1 B2 I DIG CTED4 1 1 3 D3 I DIG CTED5 29 35 43 K7 I DIG CTED6 30 36 44 L8 I DIG CTED7 — — 40 47 I DIG CTED8 64 80 100 A1 I DIG CTED9 63 79 99 A2 I DIG CTED10 — — 97 A3 I DIG CTED11 — — 95 C4 I DIG CTED12 15 19 24 K1 I DIG CTED13 14 18 23 J2 I DIG CTPLS 29 35 43 K7 O — CTMU Pulse Output. CVREF 23 29 34 L5 O — Comparator Voltage Reference Output. CVREF+ 16 20 25 K2 I ANA Comparator/ADC Reference Voltage (high) Input. CVREF- 15 19 24 K1 I ANA Comparator/ADC Reference Voltage (low) Input. INT0 35 45 55 H9 I ST External Interrupt Input 0. LCDBIAS0 3 3 5 D2 I ANA Bias Inputs for LCD Driver Charge Pump. LCDBIAS1 2 2 4 C1 I ANA LCDBIAS2 1 1 3 D3 I ANA LCDBIAS3 17 21 26 L1 I ANA HLVDIN 64 80 100 A1 I ANA High/Low-Voltage Detect Input. MCLR 7 9 13 F1 I ST Master Clear (device Reset) Input. This line is brought low to cause a Reset. OSCI 39 49 63 F9 I ANA Main Oscillator Input Connection. OSCO 40 50 64 F11 O — Main Oscillator Output Connection. Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer DS30009996G-page 20  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locater Pin Input I/O Description Function 64-Pin 80-Pin 100-Pin 121-Pin Buffer TQFP TQFP TQFP BGA PGEC1 15 19 24 K1 I/O ST In-Circuit Debugger/Emulator/ICSP™ Programming Clock 1. PGED1 16 20 25 K2 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data 1. PGEC2 17 21 26 L1 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Clock 2. PGED2 18 22 27 J3 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data 2. PGEC3 11 15 20 H1 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Clock 3. PGED3 12 16 21 H2 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data 3. PMA0 30 36 44 L8 I/O ST Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). PMA1 29 35 43 K7 I/O ST Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). PMA2 8 10 14 F3 O — Parallel Master Port Address (bits<22:2>). PMA3 6 8 12 F2 O — PMA4 5 7 11 F4 O — PMA5 4 6 10 E3 O — PMA6 16 24 29 K3 O — PMA7 22 23 28 L2 O — PMA8 32 40 50 L11 O — PMA9 31 39 49 L10 O — PMA10 28 34 42 L7 O — PMA11 27 33 41 J7 O — PMA12 24 30 35 J5 O — PMA13 23 29 34 L5 O — PMA14 45 57 71 C11 O — PMA15 44 56 70 D11 O — PMA16 — — 95 C4 O — PMA17 — — 92 B5 O — PMA18 — — 40 K6 O — PMA19 — 14 19 G2 O — PMA20 — — 59 G10 O — PMA21 — — 60 G11 O — PMA22 — 52 66 E11 O — PMACK1 50 62 77 A10 I ST/TTL Parallel Master Port Acknowledge Input 1. PMACK2 43 55 69 E10 I ST/TTL Parallel Master Port Acknowledge Input 2. PMBE0 51 63 78 B9 O — Parallel Master Port Byte Enable 0 Strobe. PMBE1 — 53 67 E8 O — Parallel Master Port Byte Enable 1 Strobe. PMCS1 — 13 18 G1 I/O ST/TTL Parallel Master Port Chip Select 1 Strobe. PMCS2 — — 9 E1 O — Parallel Master Port Chip Select 2 Strobe. Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer  2010-2014 Microchip Technology Inc. DS30009996G-page 21

PIC24FJ128GA310 FAMILY TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locater Pin Input I/O Description Function 64-Pin 80-Pin 100-Pin 121-Pin Buffer TQFP TQFP TQFP BGA PMD0 60 76 93 A4 I/O ST/TTL Parallel Master Port Data (Demultiplexed Master PMD1 61 77 94 B4 I/O ST/TTL mode) or Address/Data (Multiplexed Master modes). PMD2 62 78 98 B3 I/O ST/TTL PMD3 63 79 99 A2 I/O ST/TTL PMD4 64 80 100 A1 I/O ST/TTL PMD5 1 1 3 D3 I/O ST/TTL PMD6 2 2 4 C1 I/O ST/TTL PMD7 3 3 5 D2 I/O ST/TTL PMD8 — 75 90 A5 I/O ST/TTL PMD9 — 74 89 E6 I/O ST/TTL PMD10 — 73 88 A6 I/O ST/TTL PMD11 — 72 87 B6 I/O ST/TTL PMD12 — 64 79 A9 I/O ST/TTL PMD13 — 65 80 D8 I/O ST/TTL PMD14 — 68 83 D7 I/O ST/TTL PMD15 — 69 84 C7 I/O ST/TTL PMRD 53 67 82 B8 O — Parallel Master Port Read Strobe. PMWR 52 66 81 C8 O — Parallel Master Port Write Strobe. RA0 — — 17 G3 I/O ST PORTA Digital I/O. RA1 — — 38 J6 I/O ST RA2 — — 58 H11 I/O ST RA3 — — 59 G10 I/O ST RA4 — — 60 G11 I/O ST RA5 — — 61 G9 I/O ST RA6 — — 91 C5 I/O ST RA7 — — 92 B5 I/O ST RA9 — 23 28 L2 I/O ST RA10 — 24 29 K3 I/O ST RA14 — 52 66 E11 I/O ST RA15 — 53 67 E8 I/O ST Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer DS30009996G-page 22  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locater Pin Input I/O Description Function 64-Pin 80-Pin 100-Pin 121-Pin Buffer TQFP TQFP TQFP BGA RB0 16 20 25 K2 I/O ST PORTB Digital I/O. RB1 15 19 24 K1 I/O ST RB2 14 18 23 J2 I/O ST RB3 13 17 22 J1 I/O ST RB4 12 16 21 H2 I/O ST RB5 11 15 20 H1 I/O ST RB6 17 21 26 L1 I/O ST RB7 18 22 27 J3 I/O ST RB8 21 27 32 K4 I/O ST RB9 22 28 33 L4 I/O ST RB10 23 29 34 L5 I/O ST RB11 24 30 35 J5 I/O ST RB12 27 33 41 J7 I/O ST RB13 28 34 42 L7 I/O ST RB14 29 35 43 K7 I/O ST RB15 30 36 44 L8 I/O ST RC1 — 4 6 D1 I/O ST PORTC Digital I/O. RC2 — — 7 E4 I/O ST RC3 — 5 8 E2 I/O ST RC4 — — 9 E1 I/O ST RC12 39 49 63 F9 I/O ST RC13 47 59 73 C10 I ST RC14 48 60 74 B11 I ST RC15 40 50 64 F11 I/O ST RD0 46 58 72 D9 I/O ST PORTD Digital I/O. RD1 49 61 76 A11 I/O ST RD2 50 62 77 A10 I/O ST RD3 51 63 78 B9 I/O ST RD4 52 66 81 C8 I/O ST RD5 53 67 82 B8 I/O ST RD6 54 68 83 D7 I/O ST RD7 55 69 84 C7 I/O ST RD8 42 54 68 E9 I/O ST RD9 43 55 69 E10 I/O ST RD10 44 56 70 D11 I/O ST RD11 45 57 71 C11 I/O ST RD12 — 64 79 A9 I/O ST RD13 — 65 80 D8 I/O ST RD14 — 37 47 L9 I/O ST RD15 — 38 48 K9 I/O ST Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer  2010-2014 Microchip Technology Inc. DS30009996G-page 23

PIC24FJ128GA310 FAMILY TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locater Pin Input I/O Description Function 64-Pin 80-Pin 100-Pin 121-Pin Buffer TQFP TQFP TQFP BGA RE0 60 76 93 A4 I/O ST PORTE Digital I/O. RE1 61 77 94 B4 I/O ST RE2 62 78 98 B3 I/O ST RE3 63 79 99 A2 I/O ST RE4 64 80 100 A1 I/O ST RE5 1 1 3 D3 I/O ST RE6 2 2 4 C1 I/O ST RE7 3 3 5 D2 I/O ST RE8 — 13 18 G1 I/O ST RE9 — 14 19 G2 I/O ST REFO 30 36 44 L8 O — Reference Clock Output. RF0 58 72 87 B6 I/O ST PORTF Digital I/O. RF1 59 73 88 A6 I/O ST RF2 34 42 52 K11 I/O ST RF3 33 41 51 K10 I/O ST RF4 31 39 49 L10 I/O ST RF5 32 40 50 L11 I/O ST RF6 35 45 55 H9 I/O ST RF7 — 44 54 H8 I/O ST RF8 — 43 53 J10 I/O ST RF12 — — 40 K6 I/O ST RF13 — — 39 L6 I/O ST RG0 — 75 90 A5 I/O ST PORTG Digital I/O. RG1 — 74 89 E6 I/O ST RG2 37 47 57 H10 I/O ST RG3 36 46 56 J11 I/O ST RG6 4 6 10 E3 I/O ST RG7 5 7 11 F4 I/O ST RG8 6 8 12 F2 I/O ST RG9 8 10 14 F3 I/O ST RG12 — — 96 C3 I/O ST RG13 — — 97 A3 I/O ST RG14 — — 95 C4 I/O ST RG15 — — 1 B2 I/O ST Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer DS30009996G-page 24  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locater Pin Input I/O Description Function 64-Pin 80-Pin 100-Pin 121-Pin Buffer TQFP TQFP TQFP BGA RP0 16 20 25 K2 I/O ST Remappable Peripheral (input or output). RP1 15 19 24 K1 I/O ST RP2 42 54 68 E9 I/O ST RP3 44 56 70 D11 I/O ST RP4 43 55 69 E10 I/O ST RP5 — 38 48 K9 I/O ST RP6 17 21 26 L1 I/O ST RP7 18 22 27 J3 I/O ST RP8 21 27 32 K4 I/O ST RP9 22 28 33 L4 I/O ST RP10 31 39 49 L10 I/O ST RP11 46 58 72 D9 I/O ST RP12 45 57 71 C11 I/O ST RP13 14 18 23 J2 I/O ST RP14 29 35 43 K7 I/O ST RP15 — 43 53 J10 I/O ST RP16 33 41 51 K10 I/O ST RP17 32 40 50 L11 I/O ST RP18 11 15 20 H1 I/O ST RP19 6 8 12 F2 I/O ST RP20 53 67 82 B8 I/O ST RP21 4 6 10 E3 I/O ST RP22 51 63 78 B9 I/O ST RP23 50 62 77 A10 I/O ST RP24 49 61 76 A11 I/O ST RP25 52 66 81 C8 I/O ST RP26 5 7 11 F4 I/O ST RP27 8 10 14 F3 I/O ST RP28 12 16 21 H2 I/O ST RP29 30 36 44 L8 I/O ST RP30 34 42 52 K11 I/O ST RP31 — — 39 L6 I/O ST RPI32 — — 40 K6 I ST Remappable Peripheral (input only). RPI33 — 13 18 G1 I ST RPI34 — 14 19 G2 I ST RPI35 — 53 67 E8 I ST RPI36 — 52 66 E11 I ST RPI37 48 60 74 B11 I ST RPI38 — 4 6 D1 I ST RPI39 — — 7 E4 I ST RPI40 — 5 8 E2 I ST RPI41 — — 9 E1 I ST RPI42 — 64 79 A9 I ST RPI43 — 37 47 L9 I ST Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer  2010-2014 Microchip Technology Inc. DS30009996G-page 25

PIC24FJ128GA310 FAMILY TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locater Pin Input I/O Description Function 64-Pin 80-Pin 100-Pin 121-Pin Buffer TQFP TQFP TQFP BGA RTCC 42 54 68 E9 O — Real-Time Clock/Calendar Alarm/Seconds Pulse Output. SCL1 37 47 57 H10 I/O I2C I2C1 Synchronous Serial Clock Input/Output. SCL2 32 40 58 H11 I/O I2C I2C2 Synchronous Serial Clock Input/Output. SCLKI 48 60 74 B11 I ST Digital Secondary Clock Input. SDA1 36 46 56 J11 I/O I2C I2C1 Data Input/Output. SDA2 31 39 59 G10 I/O I2C I2C2 Data Input/Output. SEG0 4 6 10 E3 O — LCD Driver Segment Outputs. SEG1 8 10 14 F3 O — SEG2 11 15 20 H1 O — SEG3 12 16 21 H2 O — SEG4 13 17 22 J1 O — SEG5 14 18 23 J2 O — SEG6 15 19 24 K1 O — SEG7 16 20 25 K2 O — SEG8 29 35 43 K7 O — SEG9 30 36 44 L8 O — SEG10 31 39 49 L10 O — SEG11 32 40 50 L11 O — SEG12 33 41 51 K10 O — SEG13 42 54 68 E9 O — SEG14 43 55 69 E10 O — SEG15 44 56 70 D11 O — SEG16 45 57 71 C11 O — SEG17 46 58 72 D9 O — SEG18 27 33 41 J7 O — SEG19 28 34 42 L7 O — SEG20 49 61 76 A11 O — SEG21 50 62 77 A10 O — SEG22 51 63 78 B9 O — SEG23 52 66 81 C8 O — SEG24 53 67 82 B8 O — SEG25 54 68 83 D7 O — SEG26 55 69 84 C7 O — SEG27 58 72 87 B6 O — SEG28 37 47 57 H10 O — SEG29 23 29 34 L5 O — SEG30 22 28 33 L4 O — SEG31 21 27 32 K4 O — SEG32 — 4 6 D1 O — SEG33 — 5 8 E2 O — SEG34 — 13 18 G1 O — Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer DS30009996G-page 26  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locater Pin Input I/O Description Function 64-Pin 80-Pin 100-Pin 121-Pin Buffer TQFP TQFP TQFP BGA SEG35 — 14 19 G2 O — LCD Driver Segment Outputs. SEG36 — 23 28 L2 O — SEG37 — 24 29 K3 O — SEG38 — 37 47 L9 O — SEG39 — 38 48 K9 O — SEG40 — 42 52 K11 O — SEG41 — 43 53 J10 O — SEG42 — 52 66 E11 O — SEG43 — 53 67 E8 O — SEG44 — 64 79 A9 O — SEG45 — 65 80 D8 O — SEG46 — 74 89 E6 O — SEG47 36 46 56 J11 O — SEG48 59 73 88 A6 O — SEG49 — — 17 G3 O — SEG50 — 75 90 A5 O — SEG51 — — 1 B2 O — SEG52 — — 7 E4 O — SEG53 — — 9 E1 O — SEG54 — — 39 L6 O — SEG55 — — 40 K6 O — SEG56 — — 58 H11 O — SEG57 — — 59 G10 O — SEG58 — — 91 C5 O — SEG59 — — 92 B5 O — SEG60 — — 95 C4 O — SEG61 — — 96 C3 O — SEG62 — — 97 A3 O — SEG63 — — 100 A1 O — SOSCI 47 59 73 C10 I ANA Secondary Oscillator/Timer1 Clock Input. SOSCO 48 60 74 B11 O ANA Secondary Oscillator/Timer1 Clock Output. TCK 27 33 38 J6 I ST JTAG Test Clock/Programming Clock Input. TDI 28 34 60 G11 I ST JTAG Test Data/Programming Data Input. TDO 24 14 61 G9 O — JTAG Test Data Output. TMS 23 13 17 G3 I ST JTAG Test Mode Select Input. Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer  2010-2014 Microchip Technology Inc. DS30009996G-page 27

PIC24FJ128GA310 FAMILY TABLE 1-4: PIC24FJ128GA310 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locater Pin Input I/O Description Function 64-Pin 80-Pin 100-Pin 121-Pin Buffer TQFP TQFP TQFP BGA VBAT 57 71 86 A7 P — Backup Battery. VCAP 56 70 85 B7 P — External Filter Capacitor Connection (regulator enabled). VDD 10, 26, 12, 32, 2, 16, C2, F8, P — Positive Supply for Peripheral Digital Logic and I/O 38 48 37, 46, G5, H6, Pins. 62 K8 VLCAP1 5 7 11 F4 I ANA LCD Drive Charge Pump Capacitor Inputs. VLCAP2 6 8 12 F2 I ANA VREF+ — 24 29 K3 I ANA Comparator/ADC Reference Voltage (low) Input (default). VREF- — 23 28 L2 I ANA Comparator/ADC Reference Voltage (high) Input (default). Vss 9, 25, 41 11, 31, 15, 36, B10, F5, P — Ground Reference for Logic and I/O Pins. 51 45, 65, F10, G6, 75 G7 Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer DS30009996G-page 28  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 2.0 GUIDELINES FOR GETTING FIGURE 2-1: RECOMMENDED STARTED WITH 16-BIT MINIMUM CONNECTIONS MICROCONTROLLERS C2(2) 2.1 Basic Connection Requirements VDD Getting started with the PIC24FJ128GA310 family R1 DD SS family of 16-bit microcontrollers requires attention to a V V R2 minimal set of device pin connections before MCLR VCAP proceeding with development. The following pins must always be connected: C1 C7(1) PIC24FJXXX • All VDD and VSS pins (see Section2.2 “Power Supply Pins”) VSS VDD C6(2) C3(2) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used VDD D S VSS D S D S (see Section2.2 “Power Supply Pins”) V V D S A A V V • MCLR pin (see Section2.3 “Master Clear (MCLR) Pin”) C5(2) C4(2) • VCAP pin (see Section2.4 “Voltage Regulator Pin (VCAP)”) These pins must also be connected if they are being Key (all values are recommendations): used in the end application: C1 through C6: 0.1 F, 20V ceramic • PGECx/PGEDx pins used for In-Circuit Serial C7: 10 F, 6.3V or greater, tantalum or ceramic Programming™ (ICSP™) and debugging purposes R1: 10 kΩ (see Section2.5 “ICSP Pins”) R2: 100Ω to 470Ω • OSCI and OSCO pins when an external oscillator Note 1: See Section2.4 “Voltage Regulator Pin source is used (VCAP)” for details on selecting the proper (see Section2.6 “External Oscillator Pins”) capacitor for Vcap. Additionally, the following pins may be required: 2: The example shown is for a PIC24F device with five VDD/VSS and AVDD/AVSS pairs. • VREF+/VREF- pins used when external voltage Other devices may have more or less pairs; reference for analog modules is implemented adjust the number of decoupling capacitors Note: The AVDD and AVSS pins must always be appropriately. connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure2-1.  2010-2014 Microchip Technology Inc. DS30009996G-page 29

PIC24FJ128GA310 FAMILY 2.2 Power Supply Pins 2.3 Master Clear (MCLR) Pin 2.2.1 DECOUPLING CAPACITORS The MCLR pin provides two specific device functions: device Reset, and device programming The use of decoupling capacitors on every pair of and debugging. If programming and debugging are power supply pins, such as VDD, VSS, AVDD and not required in the end application, a direct AVSS, is required. connection to VDD may be all that is required. The Consider the following criteria when using decoupling addition of other components, to help increase the capacitors: application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical • Value and type of capacitor: A 0.1 F (100 nF), configuration is shown in Figure2-1. Other circuit 10-20V capacitor is recommended. The capacitor designs may be implemented, depending on the should be a low-ESR device with a resonance application’s requirements. frequency in the range of 200MHz and higher. Ceramic capacitors are recommended. During programming and debugging, the resistance • Placement on the printed circuit board: The and capacitance that can be added to the pin must decoupling capacitors should be placed as close be considered. Device programmers and debuggers to the pins as possible. It is recommended to drive the MCLR pin. Consequently, specific voltage place the capacitors on the same side of the levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values board as the device. If space is constricted, the of R1 and C1 will need to be adjusted based on the capacitor can be placed on another layer on the application and PCB requirements. For example, it is PCB using a via; however, ensure that the trace recommended that the capacitor, C1, be isolated length from the pin to the capacitor is no greater from the MCLR pin during programming and than 0.25inch (6mm). debugging operations by using a jumper (Figure2-2). • Handling high-frequency noise: If the board is The jumper is replaced for normal run-time experiencing high-frequency noise (upward of operations. tens of MHz), add a second ceramic type capaci- tor in parallel to the above described decoupling Any components associated with the MCLR pin capacitor. The value of the second capacitor can should be placed within 0.25 inch (6mm) of the pin. be in the range of 0.01F to 0.001F. Place this second capacitor next to each primary decoupling FIGURE 2-2: EXAMPLE OF MCLR PIN capacitor. In high-speed circuit designs, consider CONNECTIONS implementing a decade pair of capacitances as close to the power and ground pins as possible VDD (e.g., 0.1F in parallel with 0.001F). • Maximizing performance: On the board layout R1 from the power supply circuit, run the power and R2 return traces to the decoupling capacitors first, MCLR and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. JP PIC24FJXXX Equally important is to keep the trace length C1 between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. Note 1: R1  10 k is recommended. A suggested 2.2.2 TANK CAPACITORS starting value is 10 k. Ensure that the On boards with power traces running longer than six MCLR pin VIH and VIL specifications are met. inches in length, it is suggested to use a tank capacitor 2: R2  470 will limit any current flowing into for integrated circuits including microcontrollers to MCLR from the external capacitor, C, in the supply a local power source. The value of the tank event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical capacitor should be determined based on the trace Overstress (EOS). Ensure that the MCLR resistance that connects the power supply source to pin VIH and VIL specifications are met. the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7F to 47F. DS30009996G-page 30  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 2.4 Voltage Regulator Pin (VCAP) FIGURE 2-3: FREQUENCY vs. ESR PERFORMANCE FOR A low-ESR (<5Ω) capacitor is required on the VCAP pin SUGGESTED VCAP to stabilize the output voltage of the on-chip voltage regulator. The VCAP pin must not be connected to VDD 10 and must use a capacitor of 10 µF connected to ground. The type can be ceramic or tantalum. Suitable examples 1 of capacitors are shown in Table2-1. Capacitors with equivalent specification can be used. ) The placement of this capacitor should be close to R ( 0.1 S VCAP. It is recommended that the trace length not E exceed 0.25inch (6mm). Refer to Section32.0 0.01 “Electrical Characteristics” for additional information. 0.001 Designers may use Figure2-3 to evaluate ESR 0.01 0.1 1 10 100 1000 10,000 equivalence of candidate devices. Frequency (MHz) Refer to Section29.2 “On-Chip Voltage Regulator” Note: Typical data measurement at +25°C, 0V DC bias. for details on connecting and using the on-chip regulator. . TABLE 2-1: SUITABLE CAPACITOR EQUIVALENTS Nominal Make Part # Base Tolerance Rated Voltage Temp. Range Capacitance TDK C3216X7R1C106K 10 µF ±10% 16V -55 to +125ºC TDK C3216X5R1C106K 10 µF ±10% 16V -55 to +85ºC Panasonic ECJ-3YX1C106K 10 µF ±10% 16V -55 to +125ºC Panasonic ECJ-4YB1C106K 10 µF ±10% 16V -55 to +85ºC Murata GRM32DR71C106KA01L 10 µF ±10% 16V -55 to +125ºC Murata GRM31CR61C106KC31L 10 µF ±10% 16V -55 to +85ºC  2010-2014 Microchip Technology Inc. DS30009996G-page 31

PIC24FJ128GA310 FAMILY 2.4.1 CONSIDERATIONS FOR CERAMIC FIGURE 2-4: DC BIAS VOLTAGE vs. CAPACITORS CAPACITANCE CHARACTERISTICS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic %) 10 e ( 0 capacitors very attractive in many types of applications. ng-10 16V Capacitor ha-20 Ceramic capacitors are suitable for use with the inter- C-30 nal voltage regulator of this microcontroller. However, ance --5400 10V Capacitor some care is needed in selecting the capacitor to cit-60 ensure that it maintains sufficient capacitance over the Capa--8700 6.3V Capacitor intended operating range of the application. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DC Bias Voltage (VDC) Typical low-cost, 10 F ceramic capacitors are available in X5R, X7R and Y5V dielectric ratings (other types are also available, but are less common). The initial toler- When selecting a ceramic capacitor to be used with the ance specifications for these types of capacitors are internal voltage regulator, it is suggested to select a often specified as ±10% to ±20% (X5R and X7R), or high-voltage rating, so that the operating voltage is a -20%/+80% (Y5V). However, the effective capacitance small percentage of the maximum rated capacitor volt- that these capacitors provide in an application circuit will age. For example, choose a ceramic capacitor rated at also vary based on additional factors, such as the 16V for the 2.5V or 1.8V core voltage. Suggested applied DC bias voltage and the temperature. The total capacitors are shown in Table2-1. in-circuit tolerance is, therefore, much wider than the initial tolerance specification. 2.5 ICSP Pins The X5R and X7R capacitors typically exhibit satisfac- The PGECx and PGEDx pins are used for In-Circuit tory temperature stability (ex: ±15% over a wide Serial Programming (ICSP) and debugging purposes. temperature range, but consult the manufacturer’s data It is recommended to keep the trace length between sheets for exact specifications). However, Y5V capaci- the ICSP connector and the ICSP pins on the device as tors typically have extreme temperature tolerance short as possible. If the ICSP connector is expected to specifications of +22%/-82%. Due to the extreme experience an ESD event, a series resistor is temperature tolerance, a 10 F nominal rated Y5V type recommended, with the value in the range of a few tens capacitor may not deliver enough total capacitance to of Ohms, not to exceed 100Ω. meet minimum internal voltage regulator stability and Pull-up resistors, series diodes and capacitors on the transient response requirements. Therefore, Y5V PGECx and PGEDx pins are not recommended as they capacitors are not recommended for use with the will interfere with the programmer/debugger communi- internal regulator if the application must operate over a cations to the device. If such discrete components are wide temperature range. an application requirement, they should be removed In addition to temperature tolerance, the effective from the circuit during programming and debugging. capacitance of large value ceramic capacitors can vary Alternatively, refer to the AC/DC characteristics and substantially, based on the amount of DC voltage timing requirements information in the respective applied to the capacitor. This effect can be very signifi- device Flash programming specification for information cant, but is often overlooked or is not always on capacitive loading limits and pin Voltage Input High documented. (VIH) and Voltage Input Low (VIL) requirements. Typical DC bias voltage vs. capacitance graph for X7R For device emulation, ensure that the “Communication type capacitors is shown in Figure2-4. Channel Select” (i.e., PGECx/PGEDx pins), programmed into the device, matches the physical connections for the ICSP to the Microchip debugger/emulator tool. For more information on available Microchip development tools connection requirements, refer to Section30.0 “Development Support”. DS30009996G-page 32  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 2.6 External Oscillator Pins FIGURE 2-5: SUGGESTED PLACEMENT OF THE Many microcontrollers have options for at least two OSCILLATOR CIRCUIT oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Single-Sided and In-Line Layouts: Section9.0 “Oscillator Configuration” for details). Copper Pour Primary Oscillator The oscillator circuit should be placed on the same (tied to ground) Crystal side of the board as the device. Place the oscillator DEVICE PINS circuit close to the respective oscillator pins with no more than 0.5 inch (12mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side Primary OSCI Oscillator of the board. C1 ` OSCO Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The C2 GND grounded copper pour should be routed directly to the ` MCU ground. Do not run any signal traces or power SOSCO traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board Secondary SOSC I where the crystal is placed. Oscillator Crystal ` Layout suggestions are shown in Figure2-5. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With Sec Oscillator: C1 Sec Oscillator: C2 fine-pitch packages, it is not always possible to com- pletely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored Fine-Pitch (Dual-Sided) Layouts: ground layer. In all cases, the guard trace(s) must be returned to ground. Top Layer Copper Pour (tied to ground) In planning the application’s routing and I/O assign- ments, ensure that adjacent port pins, and other Bottom Layer signals in close proximity to the oscillator, are benign Copper Pour (i.e., free of high frequencies, short rise and fall times (tied to ground) and other similar noise). OSCO For additional information and design guidance on oscillator circuits, please refer to these Microchip C2 Application Notes, available at the corporate web site Oscillator (www.microchip.com): GND Crystal • AN826, “Crystal Oscillator Basics and Crystal C1 Selection for rfPIC™ and PICmicro® Devices” • AN849, “Basic PICmicro® Oscillator Design” OSCI • AN943, “Practical PICmicro® Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” DEVICE PINS  2010-2014 Microchip Technology Inc. DS30009996G-page 33

PIC24FJ128GA310 FAMILY 2.7 Configuration of Analog and If your application needs to use certain ADC pins as Digital Pins During ICSP analog input pins during the debug session, the user application must modify the appropriate bits during Operations initialization of the ADC module, as follows: If an ICSP compliant emulator is selected as a debug- • For devices with an ADxPCFG register, clear the ger, it automatically initializes all of the ADC input pins bits corresponding to the pin(s) to be configured (ANx) as “digital” pins. Depending on the particular as analog. Do not change any other bits, particu- device, this is done by setting all bits in the ADnPCFG larly those corresponding to the PGECx/PGEDx register(s), or clearing all bit in the ANSx registers. pair, at any time. All PIC24F devices will have either one or more • For devices with ANSx registers, set the bits ADxPCFG registers or several ANSx registers (one for corresponding to the pin(s) to be configured as each port); no device will have both. Refer to analog. Do not change any other bits, particularly Section11.2 “Configuring Analog Port Pins those corresponding to the PGECx/PGEDx pair, (ANSx)” for more specific information. at any time. The bits in these registers that correspond to the ADC When a Microchip debugger/emulator is used as a pins that initialized the emulator must not be changed programmer, the user application firmware must by the user application firmware; otherwise, correctly configure the ADxPCFG or ANSx registers. communication errors will result between the debugger Automatic initialization of these registers is only done and the device. during debugger operation. Failure to correctly configure the register(s) will result in all ADC pins being recognized as analog input pins, resulting in the port value being read as a logic ‘0’, which may affect user application functionality. 2.8 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1kΩ to 10kΩ resistor to VSS on unused pins and drive the output to logic low. DS30009996G-page 34  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 3.0 CPU The core supports Inherent (no operand), Relative, Literal and Memory Direct Addressing modes, along Note: This data sheet summarizes the features of with three other groups of addressing modes. All this group of PIC24F devices. It is not modes support Register Direct and various Register intended to be a comprehensive reference Indirect modes. Each group offers up to seven source. For more information, refer to addressing modes. Instructions are associated with “CPU with Extended Data Space (EDS)” predefined addressing modes depending upon their (DS39732) in the “dsPIC33/PIC24 Family functional requirements. Reference Manual”. The information in this For most instructions, the core is capable of executing data sheet supersedes the information in a data (or program data) memory read, a Working reg- the FRM. ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a The PIC24F CPU has a 16-bit (data) modified Harvard result, three parameter instructions can be supported, architecture with an enhanced instruction set and a allowing trinary operations (that is, A + B = C) to be 24-bit instruction word with a variable length opcode executed in a single cycle. field. The Program Counter (PC) is 23 bits wide and addresses up to 4M instructions of user program A high-speed, 17-bit x 17-bit multiplier has been memory space. A single-cycle instruction prefetch included to significantly enhance the core arithmetic mechanism is used to help maintain throughput and capability and throughput. The multiplier supports provides predictable execution. All instructions execute Signed, Unsigned and Mixed mode, 16-bit x 16-bit or in a single cycle, with the exception of instructions that 8-bit x 8-bit, integer multiplication. All multiply change the program flow, the double-word move instructions execute in a single cycle. (MOV.D) instruction and the table instructions. The 16-bit ALU has been enhanced with integer divide Overhead-free program loop constructs are supported assist hardware that supports an iterative non-restoring using the REPEAT instructions, which are interruptible divide algorithm. It operates in conjunction with the at any point. REPEAT instruction looping mechanism and a selection PIC24F devices have sixteen, 16-bit Working registers of iterative divide instructions to support 32-bit (or in the programmer’s model. Each of the Working 16-bit), divided by 16-bit, integer signed and unsigned registers can act as a data, address or address offset division. All divide operations require 19 cycles to register. The 16th Working register (W15) operates as complete but are interruptible at any cycle boundary. a Software Stack Pointer for interrupts and calls. The PIC24F has a vectored exception scheme with up The lower 32 Kbytes of the Data Space can be to 8 sources of non-maskable traps and up to 118 inter- accessed linearly. The upper 32Kbytes of the Data rupt sources. Each interrupt source can be assigned to Space are referred to as Extended Data Space (EDS) one of seven priority levels. to which the extended data RAM, EPMP memory A block diagram of the CPU is shown in Figure3-1. space or program memory can be mapped. The Instruction Set Architecture (ISA) has been 3.1 Programmer’s Model significantly enhanced beyond that of the PIC18, but maintains an acceptable level of backward compatibil- The programmer’s model for the PIC24F is shown in ity. All PIC18 instructions and addressing modes are Figure3-2. All registers in the programmer’s model are supported, either directly, or through simple macros. memory-mapped and can be manipulated directly by Many of the ISA enhancements have been driven by instructions. A description of each register is provided compiler efficiency needs. in Table3-1. All registers associated with the programmer’s model are memory-mapped.  2010-2014 Microchip Technology Inc. DS30009996G-page 35

PIC24FJ128GA310 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM EDS and Table Data Access Control Block Data Bus Interrupt Controller 16 8 16 16 Data Latch 23 Data RAM PCH PCL 16 23 Up to 0x7FFF Program Counter Stack Loop Address Control Control Latch Logic Logic 23 16 RAGU Address Latch WAGU Program Memory/ Extended Data Space Address Bus EA MUX Data Latch ROM Latch 24 16 16 Instruction a Decode and at D Control Instruction Reg al er Lit Control Signals to Various Blocks Hardware Multiplier 16 x 16 W Register Array Divide Support 16 16-Bit ALU 16 To Peripheral Modules TABLE 3-1: CPU CORE REGISTERS Register(s) Name Description W0 through W15 Working Register Array PC 23-Bit Program Counter SR ALU STATUS Register SPLIM Stack Pointer Limit Value Register TBLPAG Table Memory Page Address Register RCOUNT Repeat Loop Counter Register CORCON CPU Control Register DISICNT Disable Interrupt Count Register DSRPAG Data Space Read Page Register DSWPAG Data Space Write Page Register DS30009996G-page 36  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY FIGURE 3-2: PROGRAMMER’S MODEL 15 0 W0 (WREG) Divider Working Registers W1 W2 Multiplier Registers W3 W4 W5 W6 W7 Working/Address W8 Registers W9 W10 W11 W12 W13 W14 Frame Pointer W15 Stack Pointer 0 Stack Pointer Limit SPLIM 0 Value Register 22 0 PC 0 Program Counter 7 0 Table Memory Page TBLPAG Address Register 9 0 DSRPAG Data Space Read Page Register 8 0 DSWPAG Data Space Write Page Register 15 0 Repeat Loop Counter RCOUNT Register 15 SRH SRL 0 ———————DC 2IP1L0RA N OV Z C ALU STATUS Register (SR) 15 0 ———————————— IPL3 ——— CPU Control Register (CORCON) 13 0 DISICNT Disable Interrupt Count Register Registers or bits are shadowed for PUSH.S and POP.S instructions.  2010-2014 Microchip Technology Inc. DS30009996G-page 37

PIC24FJ128GA310 FAMILY 3.2 CPU Control Registers REGISTER 3-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — DC bit 15 bit 8 R/W-0(1) R/W-0(1) R/W-0(1) R-0 R/W-0 R/W-0 R/W-0, R/W-0 IPL2(2) IPL1(2) IPL0(2) RA N OV Z C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 DC: ALU Half Carry/Borrow bit 1 = A carry out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry out from the 4th or 8th low-order bit of the result has occurred bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(1,2) 111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop is in progress 0 = REPEAT loop is not in progress bit 3 N: ALU Negative bit 1 = Result was negative 0 = Result was not negative (zero or positive) bit 2 OV: ALU Overflow bit 1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation 0 = No overflow has occurred bit 1 Z: ALU Zero bit 1 = An operation, which affects the Z bit, has set it at some time in the past 0 = The most recent operation, which affects the Z bit, has cleared it (i.e., a non-zero result) bit 0 C: ALU Carry/Borrow bit 1 = A carry out from the Most Significant bit of the result occurred 0 = No carry out from the Most Significant bit of the result occurred Note 1: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1. 2: The IPL Status bits are concatenated with the IPL3 (CORCON<3>) bit to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. DS30009996G-page 38  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 3-2: CORCON: CPU CORE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0 r-1 U-0 U-0 — — — — IPL3(1) r — — bit 7 bit 0 Legend: C = Clearable bit r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less bit 2 Reserved: Read as ‘1’ bit 1-0 Unimplemented: Read as ‘0’ Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level; see Register3-1 for bit description.  2010-2014 Microchip Technology Inc. DS30009996G-page 39

PIC24FJ128GA310 FAMILY 3.3 Arithmetic Logic Unit (ALU) 3.3.2 DIVIDER The PIC24F ALU is 16 bits wide and is capable of addi- The divide block supports signed and unsigned integer tion, subtraction, bit shifts and logic operations. Unless divide operations with the following data sizes: otherwise mentioned, arithmetic operations are 2’s 1. 32-bit signed/16-bit signed divide complement in nature. Depending on the operation, the 2. 32-bit unsigned/16-bit unsigned divide ALU may affect the values of the Carry (C), Zero (Z), 3. 16-bit signed/16-bit signed divide Negative (N), Overflow (OV) and Digit Carry (DC) 4. 16-bit unsigned/16-bit unsigned divide Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, The quotient for all divide instructions ends up in W0 for subtraction operations. and the remainder in W1. Sixteen-bit signed and unsigned DIV instructions can specify any W register The ALU can perform 8-bit or 16-bit operations, for both the 16-bit divisor (Wn), and any W register depending on the mode of the instruction that is used. (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. Data for the ALU operation can come from the W The divide algorithm takes one cycle per bit of divisor, register array, or data memory, depending on the so both 32-bit/16-bit and 16-bit/16-bit instructions take addressing mode of the instruction. Likewise, output the same number of cycles to execute. data from the ALU can be written to the W register array or a data memory location. 3.3.3 MULTI-BIT SHIFT SUPPORT The PIC24F CPU incorporates hardware support for The PIC24F ALU supports both single bit and both multiplication and division. This includes a single-cycle, multi-bit arithmetic and logic shifts. dedicated hardware multiplier and support hardware Multi-bit shifts are implemented using a shifter block, for 16-bit divisor division. capable of performing up to a 15-bit arithmetic right 3.3.1 MULTIPLIER shift, or up to a 15-bit left shift, in a single cycle. All multi-bit shift instructions only support Register Direct The ALU contains a high-speed, 17-bit x 17-bit Addressing for both the operand source and result multiplier. It supports unsigned, signed or mixed sign destination. operation in several multiplication modes: A full summary of instructions that use the shift 1. 16-bit x 16-bit signed operation is provided in Table3-2. 2. 16-bit x 16-bit unsigned 3. 16-bit signed x 5-bit (literal) unsigned 4. 16-bit unsigned x 16-bit unsigned 5. 16-bit unsigned x 5-bit (literal) unsigned 6. 16-bit unsigned x 16-bit signed 7. 8-bit unsigned x 8-bit unsigned TABLE 3-2: INSTRUCTIONS THAT USE THE SINGLE BIT AND MULTI-BIT SHIFT OPERATION Instruction Description ASR Arithmetic shift right source register by one or more bits. SL Shift left source register by one or more bits. LSR Logical shift right source register by one or more bits. DS30009996G-page 40  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 4.0 MEMORY ORGANIZATION from either the 23-bit Program Counter (PC) during pro- gram execution, or from table operation or Data Space As Harvard architecture devices, PIC24F micro- remapping, as described in Section4.3 “Interfacing controllers feature separate program and data memory Program and Data Memory Spaces”. spaces and buses. This architecture also allows direct User access to the program memory space is restricted access of program memory from the Data Space during to the lower half of the address range (000000h to code execution. 7FFFFFh). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to 4.1 Program Memory Space the Configuration bits and Device ID sections of the The program address memory space of the configuration memory space. PIC24FJ128GA310 family devices is 4M instructions. Memory maps for the PIC24FJ128GA310 family of The space is addressable by a 24-bit value derived devices are shown in Figure4-1. FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ128GA310 FAMILY DEVICES PIC24FJ64GA3XX PIC24F128GA3XX 000000h GOTO Instruction GOTO Instruction 000002h Reset Address Reset Address 000004h Interrupt Vector Table Interrupt Vector Table 0000FEh 000100h Reserved Reserved 000104h Alternate Vector Table Alternate Vector Table 0001FEh 000200h User Flash Program Memory User Flash (22K instructions) Program Memory Flash Config Words (44K instructions) 00ABFEh 00AC00h e c a p 0157FEh S Flash Config Words y 015800h or m e M er s U Unimplemented Unimplemented Read ‘0’ Read ‘0’ 7FFFFEh 800000h Reserved Reserved e c a p S y F7FFFEh mor F80000h Me Device Config Registers Device Config Registers F8000Eh n F80010h o ati ur g nfi Reserved Reserved o C FEFFFEh FF0000h DEVID (2) DEVID (2) FFFFFEh Note: Memory areas are not shown to scale.  2010-2014 Microchip Technology Inc. DS30009996G-page 41

PIC24FJ128GA310 FAMILY 4.1.1 PROGRAM MEMORY 4.1.3 FLASH CONFIGURATION WORDS ORGANIZATION In PIC24FJ128GA310 family devices, the top four words The program memory space is organized in of on-chip program memory are reserved for configura- word-addressable blocks. Although it is treated as tion information. On device Reset, the configuration 24bits wide, it is more appropriate to think of each information is copied into the appropriate Configuration address of the program memory as a lower and upper register. The addresses of the Flash Configuration Word word, with the upper byte of the upper word being for devices in the PIC24FJ128GA310 family are shown unimplemented. The lower word always has an even in Table4-1. Their location in the memory map is shown address, while the upper word has an odd address with the other memory vectors in Figure4-1. (Figure4-2). The Configuration Words in program memory are a Program memory addresses are always word-aligned compact format. The actual Configuration bits are on the lower word and addresses are incremented or mapped in several different registers in the configuration decremented by two during code execution. This memory space. Their order in the Flash Configuration arrangement also provides compatibility with data Words does not reflect a corresponding arrangement in memory space addressing and makes it possible to the configuration space. Additional details on the device access data in the program memory space. Configuration Words are provided in Section29.0 “Special Features”. 4.1.2 HARD MEMORY VECTORS TABLE 4-1: FLASH CONFIGURATION All PIC24F devices reserve the addresses between 000000h and 000200h for hard-coded program execu- WORDS FOR tion vectors. A hardware Reset vector is provided to PIC24FJ128GA310 FAMILY redirect code execution from the default value of the DEVICES PC on device Reset to the actual start of code. A GOTO Program instruction is programmed by the user at 000000h with Configuration Word Device Memory the actual address for the start of code at 000002h. Addresses (Words) PIC24F devices also have two interrupt vector tables, PIC24FJ64GA3XX 22,016 00ABF8h:00ABFEh located from 000004h to 0000FFh and 000100h to 0001FFh. These vector tables allow each of the many PIC24FJ128GA3XX 44,032 0157F8h:0157FEh device interrupt sources to be handled by separate ISRs. A more detailed discussion of the interrupt vector tables is provided in Section8.1 “Interrupt Vector Table”. FIGURE 4-2: PROGRAM MEMORY ORGANIZATION msw most significant word least significant word PC Address Address (lsw Address) 23 16 8 0 0x000001 00000000 0x000000 0x000003 00000000 0x000002 0x000005 00000000 0x000004 0x000007 00000000 0x000006 Program Memory Instruction Width ‘Phantom’ Byte (read as ‘0’) DS30009996G-page 42  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 4.2 Data Memory Space The upper half of data memory address space (8000h to FFFFh) is used as a window into the Extended Data Note: This data sheet summarizes the features of Space (EDS). This allows the microcontroller to directly this group of PIC24F devices. It is not access a greater range of data beyond the standard intended to be a comprehensive reference 16-bit address range. EDS is discussed in detail in source. For more information, refer to Section4.2.5 “Extended Data Space (EDS)”. “Data Memory with Extended Data The lower half of DS is compatible with previous PIC24F Space (EDS)” (DS39733) in the microcontrollers without EDS. All PIC24FJ128GA310 “dsPIC33/PIC24 Family Reference Man- family devices implement 8 Kbytes of data RAM in the ual”. The information in this data sheet lower half of DS, from 0800h to 27FFh. supersedes the information in the FRM. 4.2.1 DATA SPACE WIDTH The PIC24F core has a 16-bit-wide data memory space, addressable as a single linear range. The Data Space is The data memory space is organized in accessed using two Address Generation Units (AGUs), byte-addressable, 16-bit wide blocks. Data is aligned one each for read and write operations. The Data Space in data memory and registers as 16-bit words, but all memory map is shown in Figure4-3. Data Space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while The 16-bit wide data addresses in the data memory the Most Significant Bytes (MSBs) have odd space point to bytes within the Data Space (DS). This addresses. gives a DS address range of 64 Kbytes or 32K words. The lower half (0000h to 7FFFh) is used for implemented (on-chip) memory addresses. FIGURE 4-3: DATA SPACE MEMORY MAP FOR PIC24FJ128GA310 FAMILY DEVICES MSB LSB Address MSB LSB Address 0001h SFR Space 0000h SFR 07FFh 07FEh Space Near 0801h 0800h Data Space 1FFFh 1FFEh 8 Kbytes Data RAM 2001h 2000h 2801h(1) 2800h Lower 32 Kbytes EDS Page 0x1 Data Space (32 Kbytes) Internal Extended Unimplemented Data RAM (66 Kbytes) EDS Page 0x2 (32 Kbytes) 7FFFh 7FFEh EPMP Memory Space 8001h 8000h EDS Page 0x3 (2 Kbytes) EDS Page 0x4 EDS Window Upper 32 Kbytes Data Space EDS Page 0x1FF EDS Page 0x200 Program Space Visibility Area to Access Lower Word of Program Memory EDS Page 0x2FF FFFFh FFFEh EDS Page 0x300 Program Space Visibility Area to Access Upper Word of Program Memory EDS Page 0x3FF Note: Memory areas not shown to scale.  2010-2014 Microchip Technology Inc. DS30009996G-page 43

PIC24FJ128GA310 FAMILY 4.2.2 DATA MEMORY ORGANIZATION A Sign-Extend (SE) instruction is provided to allow AND ALIGNMENT users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users To maintain backward compatibility with PIC® MCUs and can clear the MSB of any W register by executing a improve Data Space memory usage efficiency, the Zero-Extend (ZE) instruction on the appropriate PIC24F instruction set supports both word and byte address. operations. As a consequence of byte accessibility, all EA calculations are internally scaled to step through Although most instructions are capable of operating on word-aligned memory. For example, the core recognizes word or byte data sizes, it should be noted that some that Post-Modified Register Indirect Addressing mode instructions operate only on words. [Ws++] will result in a value of Ws + 1 for byte operations 4.2.3 NEAR DATA SPACE and Ws + 2 for word operations. The 8-Kbyte area between 0000h and 1FFFh is Data byte reads will read the complete word, which referred to as the Near Data Space. Locations in this contains the byte, using the LSB of any EA to deter- space are directly addressable via a 13-bit absolute mine which byte to select. The selected byte is placed address field within all memory direct instructions. The onto the LSB of the data path. That is, data memory remainder of the Data Space is addressable indirectly. and registers are organized as two parallel, byte-wide Additionally, the whole Data Space is addressable entities with shared (word) address decode but separate write lines. Data byte writes only write to the using MOV instructions, which support Memory Direct Addressing with a 16-bit address field. corresponding side of the array or register which matches the byte address. 4.2.4 SPECIAL FUNCTION REGISTER All word accesses must be aligned to an even address. (SFR) SPACE Misaligned word data fetches are not supported, so The first 2 Kbytes of the Near Data Space, from 0000h care must be taken when mixing byte and word to 07FFh, are primarily occupied with Special Function operations or translating from 8-bit MCU code. If a Registers (SFRs). These are used by the PIC24F core misaligned read or write is attempted, an address error and peripheral modules for controlling the operation of trap will be generated. If the error occurred on a read, the device. the instruction underway is completed; if it occurred on a write, the instruction will be executed but the write will SFRs are distributed among the modules that they con- not occur. In either case, a trap is then executed, allow- trol and are generally grouped together by module. ing the system and/or user to examine the machine Much of the SFR space contains unused addresses; state prior to execution of the address Fault. these are read as ‘0’. A diagram of the SFR space, showing where the SFRs are actually implemented, is All byte loads into any W register are loaded into the shown in Table4-2. Each implemented area indicates LSB. The Most Significant Byte (MSB) is not modified. a 32-byte region where at least one address is imple- mented as an SFR. A complete list of implemented SFRs, including their addresses, is shown in Tables4-3 through4-34. TABLE 4-2: IMPLEMENTED REGIONS OF SFR DATA SPACE SFR Space Address xx00 xx20 xx40 xx60 xx80 xxA0 xxC0 xxE0 000h Core ICN Interrupts — 100h Timers Capture — Compare — 200h I2C™ UART SPI/UART — — UART I/O 300h ADC/CTMU — DMA — 400h — — — — — — ANA — 500h — — — — LCD — LCD 600h EPMP RTC/CMP CRC — PPS — 700h — — System NVM/PMD — — — — Legend: — = No implemented SFRs in this block DS30009996G-page 44  2010-2014 Microchip Technology Inc.

 TABLE 4-3: CPU CORE REGISTERS MAP 2 0 1 0 All -2 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 0 1 4 M WREG0 0000 Working Register 0 0000 ic WREG1 0002 Working Register 1 0000 ro c WREG2 0004 Working Register 2 0000 h ip T WREG3 0006 Working Register 3 0000 ec WREG4 0008 Working Register 4 0000 h no WREG5 000A Working Register 5 0000 log WREG6 000C Working Register 6 0000 y In WREG7 000E Working Register 7 0000 c . WREG8 0010 Working Register 8 0000 WREG9 0012 Working Register 9 0000 WREG10 0014 Working Register 10 0000 WREG11 0016 Working Register 11 0000 WREG12 0018 Working Register 12 0000 P WREG13 001A Working Register 13 0000 I C WREG14 001C Working Register 14 0000 WREG15 001E Working Register 15 0800 2 SPLIM 0020 Stack Pointer Limit Value Register xxxx 4 PCL 002E Program Counter Low Word Register 0000 F PCH 0030 — — — — — — — — Program Counter High Word Register 0000 J DSRPAG 0032 — — — — — — Extended Data Space Read Page Address Register 0001 1 DSWPAG 0034 — — — — — — — Extended Data Space Write Page Address Register 0001 2 RCOUNT 0036 Repeat Loop Counter Register xxxx 8 SR 0042 — — — — — — — DC IPL2 IPL1 IPL0 RA N OV Z C 0000 G CORCON 0044 — — — — — — — — — — — — IPL3 r — — 0004 A DISICNT 0052 — — Disable Interrupts Counter Register xxxx TBLPAG 0054 — — — — — — — — Table Memory Page Address Register 0000 3 Legend: — = unimplemented, read as ‘0’; r = reserved, do not modify. Reset values are shown in hexadecimal. 1 0 D S F 3 0 A 0 0 9 9 M 9 6 G -p IL a g e 4 Y 5

DS TABLE 4-4: ICN REGISTER MAP P 3 0 I 0 File All C 0 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 Name Resets 9 9 2 6 CNPD1 0056 CN15PDE CN14PDE CN13PDE CN12PDE CN11PDE CN10PDE CN9PDE CN8PDE CN7PDE CN6PDE CN5PDE CN4PDE CN3PDE CN2PDE — — 0000 G 4 -p CNPD2 0058 CN31PDE CN30PDE CN29PDE CN28PDE CN27PDE CN26PDE CN25PDE CN24PDE CN23PDE CN22PDE CN21PDE(1) CN20PDE(1) CN19PDE(1) CN18PDE CN17PDE CN16PDE 0000 ag CNPD3 005A CN47PDE(1) CN46PDE(2) CN45PDE(1) CN44PDE(1) CN43PDE(1) CN42PDE(1) CN41PDE(1) CN40PDE(2) CN39PDE(2) CN38PDE(2) CN37PDE(2) CN36PDE(2) CN35PDE(2) CN34PDE(2) CN33PDE(2) CN32PDE 0000 F e 4 CNPD4 005C CN63PDE CN62PDE CN61PDE CN60PDE CN59PDE CN58PDE CN57PDE CN56PDE CN55PDE CN54PDE CN53PDE CN52PDE CN51PDE CN50PDE CN49PDE CN48PDE(2) 0000 J 6 CNPD5 005E CN79PDE(2) CN78PDE(1) CN77PDE(1) CN76PDE(2) CN75PDE(2) CN74PDE(1) CN73PDE CN72PDE CN71PDE CN70PDE CN69PDE CN68PDE CN67PDE(1) CN66PDE(1) CN65PDE CN64PDE 0000 1 CNPD6 0060 — — — — — — — — — — — CN84PDE CN83PDE(1) CN82PDE(2) CN81PDE(2) CN80PDE(2) 0000 2 CNEN1 0062 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE — — 0000 8 CNEN2 0064 CN31IE CN30IE CN29IE CN28IE CN27IE CN26IE CN25IE CN24IE CN23IE CN22IE CN21IE(1) CN20IE(1) CN19IE(1) CN18IE CN17IE CN16IE 0000 G CNEN3 0066 CN47IE(1) CN46IE(1) CN45IE(1) CN44IE(1) CN43IE(1) CN42IE(1) CN41IE(1) CN40IE(2) CN39IE(2) CN38IE(2) CN37IE(2) CN36IE(2) CN35IE(2) CN34IE(2) CN33IE(2) CN32IE 0000 CNEN4 0068 CN63IE CN62IE CN61IE CN60IE CN59IE CN58IE CN57IE CN56IE CN55IE CN54IE CN53IE CN52IE CN51IE CN50IE CN49IE CN48IE(2) 0000 A CNEN5 006A CN79IE(2) CN78IE(1) CN77IE(1) CN76IE(2) CN75IE(2) CN74IE(1) CN73IE CN72IE CN71IE CN70IE CN69IE CN68IE CN67IE(1) CN66IE(1) CN65IE CN64IE 0000 3 CNEN6 006C — — — — — — — — — — — CN84IE CN83IE(1) CN82IE(2) CN81IE(2) CN80IE(2) 0000 1 CNPU1 006E CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE — — 0000 0 CNPU2 0070 CN31PUE CN30PUE CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE(1) CN20PUE(1) CN19PUE(1) CN18PUE CN17PUE CN16PUE 0000 CNPU3 0072 CN47PUE(1) CN46PUE(1) CN45PUE(1) CN44PUE(1) CN43PUE(1) CN42PUE(1) CN41PUE(1) CN40PUE(2) CN39PUE(2) CN38PUE(2) CN37PUE(2) CN36PUE(2) CN35PUE(2) CN34PUE(2) CN33PUE(2) CN32PUE 0000 F CNPU4 0074 CN63PUE CN62PUE CN61PUE CN60PUE CN59PUE CN58PUE CN57PUE CN56PUE CN55PUE CN54PUE CN53PUE CN52PUE CN51PUE CN50PUE CN49PUE CN48PUE(2) 0000 A CNPU5 0076 CN79PUE(2) CN78PUE(1) CN77PUE(1) CN76PUE(2) CN75PUE(2) CN74PUE(1) CN73PUE CN72PUE CN71PUE CN70PUE CN69PUE CN68PUE CN67PUE(1) CN66PUE(1) CN65PUE CN64PUE 0000 M CNPU6 0078 — — — — — — — — — — — CN84PUE CN83PUE(1) CN82PUE(2) CN81PUE(2) CN80PUE(2) 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. I Note 1: These bits are unimplemented in 64-pin devices, read as ‘0’. L 2: These bits are unimplemented in 64-pin and 80-pin devices, read as ‘0’. Y  2 0 1 0 -2 0 1 4 M ic ro c h ip T e c h n o lo g y In c .

 TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP 2 0 1 0 File All -2 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 0 1 4 M INTCON1 0080 NSTDIS — — — — — — — — — — MATHERR ADDRERR STKERR OSCFAIL — 0000 ic INTCON2 0082 ALTIVT DISI — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 ro c IFS0 0084 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000 h ip T IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF — IC7IF — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000 ec IFS2 0088 — DMA4IF PMPIF — OC7IF OC6IF OC5IF IC6IF IC5IF IC4IF IC3IF DMA3IF — — SPI2IF SPF2IF 0000 h no IFS3 008A — RTCIF DMA5IF — — — — — — INT4IF INT3IF — — MI2C2IF SI2C2IF — 0000 log IFS4 008C — — CTMUIF — — — — HLVDIF — — — — CRCIF U2ERIF U1ERIF — 0000 y In IFS5 008E — — — — — — U4TXIF U4RXIF U4ERIF — — — U3TXIF U3RXIF U3ERIF — 0000 c . IFS6 0090 — — — — — — — — — — — LCDIF — — — — 0000 IFS7 0092 — — — — — — — — — — JTAGIF — — — — — 0000 IEC0 0094 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000 IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE — IC7IE — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000 IEC2 0098 — DMA4IE PMPIE — OC7IE OC6IE OC5IE IC6IE IC5IE IC4IE IC3IE DMA3IE — — SPI2IE SPF2IE 0000 P IEC3 009A — RTCIE DMA5IE — — — — — — INT4IE INT3IE — — MI2C2IE SI2C2IE — 0000 I C IEC4 009C — — CTMUIE — — — — HLVDIE — — — — CRCIE U2ERIE U1ERIE — 0000 IEC5 009E — — — — — — U4TXIE U4RXIE U4ERIE — — — U3TXIE U3RXIE U3ERIE — 0000 2 IEC6 00A0 — — — — — — — — — — — LCDIE — — — — 0000 4 IEC7 00A2 — — — — — — — — — — JTAGIE — — — — — 0000 F IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 4444 J IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — DMA0IP2 DMA0IP1 DMA0IP0 4444 1 IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 4444 2 IPC3 00AA — — — — — DMA1IP2 DMA1IP1 DMA1IP0 — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 0444 8 IPC4 00AC — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 4444 G IPC5 00AE — — — — — IC7IP2 IC7IP1 IC7IP0 — — — — — INT1IP2 INT1IP1 INT1IP0 0404 A IPC6 00B0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 — OC3IP2 OC3IP1 OC3IP0 — DMA2IP2 DMA2IP1 DMA2IP0 4444 IPC7 00B2 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 4444 3 IPC8 00B4 — — — — — — — — — SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0 0044 1 IPC9 00B6 — IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0 — IC3IP2 IC3IP1 IC3IP0 — DMA3IP2 DMA3IP1 DMA3IP0 4444 0 D IPC10 00B8 — OC7IP2 OC7IP1 OC7IP0 — OC6IP2 OC6IP1 OC6IP0 — OC5IP2 OC5IP1 OC5IP0 — IC6IP2 IC6IP1 IC6IP0 4444 S F 3 IPC11 00BA — — — — — DMA4IP2 DMA4IP1 DMA4IP0 — PMPIP2 PMPIP1 PMPIP0 — — — — 0440 0 A 00 IPC12 00BC — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — 0440 9 9 IPC13 00BE — — — — — INT4IP2 INT4IP1 INT4IP0 — INT3IP2 INT3IP1 INT3IP0 — — — — 0440 M 9 6 G IPC15 00C2 — — — — — RTCIP2 RTCIP1 RTCIP0 — DMA5IP2 DMA5IP1 DMA5IP0 — — — — 0440 -pa Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. IL g e 4 Y 7

D TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP (CONTINUED) P S 3 0 I 009 NFaimlee Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts C 9 9 2 6 IPC16 00C4 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — 4440 G 4 -p IPC18 00C8 — — — — — — — — — — — — — HLVDIP2 HLVDIP1 HLVDIP0 0004 a F ge IPC19 00CA — — — — — — — — — CTMUIP2 CTMUIP1 CTMUIP0 — — — — 0040 48 IPC20 00CC — U3TXIP2 U3TXIP1 U3TXIP0 — U3RXIP2 U3RXIP1 U3RXIP0 — U3ERIP2 U3ERIP1 U3ERIP0 — — — — 4440 J IPC21 00CE — U4ERIP2 U4ERIP1 U4ERIP0 — — — — — — — — — — — — 4000 1 IPC22 00D0 — — — — — — — — — U4TXIP2 U4TXIP1 U4TXIP0 — U4RXIP2 U4RXIP1 U4RXIP0 0044 2 IPC25 00D6 — — — — — — — — — — — — — LCDIP2 LCDIP1 LCDIP0 0004 8 IPC29 00DE — — — — — — — — — JTAGIP2 JTAGIP1 JTAGIP0 — — — — 0040 G INTTREG 00E0 CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000 A Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 3 1 TABLE 4-6: TIMER REGISTER MAP 0 All F File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets A TMR1 0100 Timer1 Register 0000 M PR1 0102 Timer1 Period Register FFFF T1CON 0104 TON — TSIDL — — — TIECS1 TIECS0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000 I L TMR2 0106 Timer2 Register 0000 Y TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) 0000 TMR3 010A Timer3 Register 0000 PR2 010C Timer2 Period Register FFFF PR3 010E Timer3 Period Register FFFF T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000  2 T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 0 1 TMR4 0114 Timer4 Register 0000 0 -2 TMR5HLD 0116 Timer5 Holding Register (for 32-bit operations only) 0000 0 1 4 TMR5 0118 Timer5 Register 0000 M ic PR4 011A Timer4 Period Register FFFF roc PR5 011C Timer5 Period Register FFFF h ip T4CON 011E TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T45 — TCS — 0000 T e T5CON 0120 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 c hn Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. o lo g y In c .

 TABLE 4-7: INPUT CAPTURE REGISTER MAP 2 0 1 File All 0 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -2 Name Resets 0 14 IC1CON1 0140 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 M ic IC1CON2 0142 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D ro IC1BUF 0144 Input Capture 1 Buffer Register 0000 c hip IC1TMR 0146 Timer Value 1 Register xxxx Te IC2CON1 0148 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 c h IC2CON2 014A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D n olo IC2BUF 014C Input Capture 2 Buffer Register 0000 gy IC2TMR 014E Timer Value 2 Register xxxx Inc IC3CON1 0150 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 . IC3CON2 0152 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D IC3BUF 0154 Input Capture 3 Buffer Register 0000 IC3TMR 0156 Timer Value 3 Register xxxx IC4CON1 0158 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 P IC4CON2 015A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D IC4BUF 015C Input Capture 4 Buffer Register 0000 I C IC4TMR 015E Timer Value 4 Register xxxx IC5CON1 0160 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 2 IC5CON2 0162 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D 4 IC5BUF 0164 Input Capture 5 Buffer Register 0000 F IC5TMR 0166 Timer Value 5 Register xxxx J IC6CON1 0168 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 1 IC6CON2 016A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D 2 IC6BUF 016C Input Capture 6 Buffer Register 0000 8 IC6TMR 016E Timer Value 6 Register xxxx G IC7CON1 0170 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 IC7CON2 0172 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D A IC7BUF 0174 Input Capture 7 Buffer Register 0000 3 IC7TMR 0176 Timer Value 7 Register xxxx 1 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 D S F 3 0 A 0 0 9 9 M 9 6 G -p IL a g e 4 Y 9

DS TABLE 4-8: OUTPUT COMPARE REGISTER MAP P 3 0 I 0 All C 0 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 Resets 9 9 2 6G OC1CON1 0190 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 4 -p OC1CON2 0192 FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C a F ge OC1RS 0194 Output Compare 1 Secondary Register 0000 50 OC1R 0196 Output Compare 1 Register 0000 J OC1TMR 0198 Timer Value 1 Register xxxx 1 OC2CON1 019A — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 2 OC2CON2 019C FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C 8 OC2RS 019E Output Compare 2 Secondary Register 0000 G OC2R 01A0 Output Compare 2 Register 0000 A OC2TMR 01A2 Timer Value 2 Register xxxx OC3CON1 01A4 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 3 OC3CON2 01A6 FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C 1 OC3RS 01A8 Output Compare 3 Secondary Register 0000 0 OC3R 01AA Output Compare 3 Register 0000 F OC3TMR 01AC Timer Value 3 Register xxxx A OC4CON1 01AE — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 OC4CON2 01B0 FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C M OC4RS 01B2 Output Compare 4 Secondary Register 0000 I OC4R 01B4 Output Compare 4 Register 0000 L OC4TMR 01B6 Timer Value 4 Register xxxx Y OC5CON1 01B8 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT1 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 OC5CON2 01BA FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C OC5RS 01BC Output Compare 5 Secondary Register 0000 OC5R 01BE Output Compare 5 Register 0000 OC5TMR 01C0 Timer Value 5 Register xxxx  2 OC6CON1 01C2 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 0 1 OC6CON2 01C4 FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C 0 -2 OC6RS 01C6 Output Compare 6 Secondary Register 0000 0 14 OC6R 01C8 Output Compare 6 Register 0000 M OC6TMR 01CA Timer Value 6 Register xxxx ic ro Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. c h ip T e c h n o lo g y In c .

 TABLE 4-8: OUTPUT COMPARE REGISTER MAP (CONTINUED) 2 0 1 All 0-2 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 0 14 OC7CON1 01CC — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 M OC7CON2 01CE FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C ic ro OC7RS 01D0 Output Compare 7 Secondary Register 0000 c hip OC7R 01D2 Output Compare 7 Register 0000 T OC7TMR 01D4 Timer Value 7 Register xxxx e ch Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. n o lo g y In TABLE 4-9: I2C™ REGISTER MAP c . All File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets I2C1RCV 0200 — — — — — — — — I2C1 Receive Register 0000 I2C1TRN 0202 — — — — — — — — I2C1 Transmit Register 00FF P I2C1BRG 0204 — — — — — — — Baud Rate Generator Register 0000 I I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 C I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 2 I2C1ADD 020A — — — — — — I2C1 Address Register 0000 4 I2C1MSK 020C — — — — — — I2C1 Address Mask Register 0000 F I2C2RCV 0210 — — — — — — — — I2C2 Receive Register 0000 J I2C2TRN 0212 — — — — — — — — I2C2 Transmit Register 00FF 1 I2C2BRG 0214 — — — — — — — Baud Rate Generator Register 0000 2 I2C2CON 0216 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 8 I2C2STAT 0218 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 G I2C2ADD 021A — — — — — — I2C2 Address Register 0000 I2C2MSK 021C — — — — — — I2C2 Address Mask Register 0000 A Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 3 1 0 D S F 3 0 A 0 0 9 9 M 9 6 G -p IL a g e 5 Y 1

D TABLE 4-10: UART REGISTER MAPS P S 3 0009 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts IC 9 9 2 6 U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000 G 4 -p U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110 a F ge U1TXREG 0224 — — — — — — — UART1 Transmit Register xxxx 52 U1RXREG 0226 — — — — — — — UART1 Receive Register 0000 J U1BRG 0228 Baud Rate Generator Prescaler Register 0000 1 U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000 2 U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110 8 U2TXREG 0234 — — — — — — — UART2 Transmit Register xxxx G U2RXREG 0236 — — — — — — — UART2 Receive Register 0000 A U2BRG 0238 Baud Rate Generator Prescaler Register 0000 3 U3MODE 0250 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000 1 U3STA 0252 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110 0 U3TXREG 0254 — — — — — — — UART3 Transmit Register xxxx U3RXREG 0256 — — — — — — — UART3 Receive Register 0000 F U3BRG 0258 Baud Rate Generator Prescaler Register 0000 A U4MODE 02B0 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000 M U4STA 02B2 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110 U4TXREG 02B4 — — — — — — — UART4 Transmit Register xxxx I L U4RXREG 02B6 — — — — — — — UART4 Receive Register 0000 U4BRG 02B8 Baud Rate Generator Prescaler Register 0000 Y Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.  2 0 1 0 -2 0 1 4 M ic ro c h ip T e c h n o lo g y In c .

 T ABLE 4-11: SPI REGISTER MAP 2 0 1 0 All -2 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 0 1 4 M SPI1STAT 0240 SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000 ic SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 ro c SPI1CON2 0244 FRMEN SPIFSD SPIFPOL — — — — — — — — — — — SPIFE SPIBEN 0000 h ip T SPI1BUF 0248 SPI1 Transmit and Receive Buffer 0000 ec SPI2STAT 0260 SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000 h no SPI2CON1 0262 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 log SPI2CON2 0264 FRMEN SPIFSD SPIFPOL — — — — — — — — — — — SPIFE SPIBEN 0000 y In SPI2BUF 0268 SPI2 Transmit and Receive Buffer 0000 c . Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-12: PORTA REGISTER MAP(1) File Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7(2) Bit 6(2) Bit 5(2) Bit 4(2) Bit 3(2) Bit2(2) Bit 1(2) Bit 0(2) All P Name Resets I TRISA 02C0 TRISA<15:14> — — — TRISA<10:9> — TRISA<7:0> C6FF C PORTA 02C2 RA<15:14> — — — RA<10:9> — RA<7:0> xxxx 2 LATA 02C4 LATA<15:14> — — — LATA<10:9> — LATA<7:0> xxxx 4 ODCA 02C6 ODA<15:14> — — — ODA<10:9> — ODA<7:0> 0000 F Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. J Note 1: PORTA and all associated bits are unimplemented in 64-pin devices and read as ‘0’. 2: These bits are also unimplemented in 80-pin devices, read as ‘0’. 1 2 8 TABLE 4-13: PORTB REGISTER MAP G File Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All A Name Resets 3 TRISB 02C8 TRISB<15:0> FFFF 1 PORTB 02CA RB<15:0> xxxx 0 LATB 02CC LATB<15:0> xxxx DS ODCB 02CE ODB<15:0> 0000 F 30 Legend: Reset values are shown in hexadecimal. A 0 0 9 9 M 9 6 G -p IL a g e 5 Y 3

DS TABLE 4-14: PORTC REGISTER MAP P 3 0 I 00 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4(1) Bit 3(2) Bit 2(1) Bit 1(2) Bit 0 All C 9 Name Resets 9 9 2 6G TRISC 02D0 TRISC15 — — TRISC12 — — — — — — — TRISC<4:1> — 901E 4 -p PORTC 02D2 RC<15:12>(3,4,5) — — — — — — — RC<4:1> — xxxx a F g e LATC 02D4 LATC15 — — LATC12 — — — — — — — LATC<4:1) — xxxx 5 J 4 ODCC 02D6 ODC<15:12> — — — — — — — ODC<4:1> — 0000 1 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Note 1: These bits are unimplemented in 64-pin and 80-pin devices, read as ‘0’. 2 2: These bits are unimplemented in 64-pin devices, read as ‘0’. 8 3: RC12 and RC15 are only available when the primary oscillator is disabled or when EC mode is selected (POSCMD<1:0> Configuration bits= 11 or 00); otherwise read as ‘0’. G 4: RC15 is only available when the POSCMD<1:0> Configuration bits= 11 or 00 and the OSCIOFN Configuration bit = 1. 5: RC13 and RC14 are input ports only and cannot be used as output ports. A 3 TABLE 4-15: PORTD REGISTER MAP 1 0 File Addr Bit 15(1) Bit 14(1) Bit 13(1) Bit 12(1) Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Name Resets F TRISD 02D8 TRISD<15:0> FFFF A PORTD 02DA RD<15:0> xxxx M LATD 02DC LATD<15:0> xxxx ODCD 02DE ODD<15:0> 0000 I L Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Note 1: These bits are unimplemented in 64-pin devices, read as ‘0’. Y TABLE 4-16: PORTE REGISTER MAP  NFaimlee Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9(1) Bit 8(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts 2 0 1 TRISE 02E0 — — — — — — TRISE<9:0> 03FF 0 -2 PORTE 02E2 — — — — — — RE<9:0> xxxx 0 14 LATE 02E4 — — — — — — LATE<9:0> xxxx M ODCE 02E6 — — — — — — ODE<9:0> 0000 ic ro Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. c h Note 1: These bits are unimplemented in 64-pin devices, read as ‘0’. ip T e c h n o lo g y In c .

 TABLE 4-17: PORTF REGISTER MAP 2 0 1 0-2 NFaimlee Addr Bit 15 Bit 14 Bit 13(1) Bit 12(1) Bit 11 Bit 10 Bit 9 Bit 8(2) Bit 7(2) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts 0 1 4 M TRISF 02E8 — — TRISF<13:12> — — — TRISF<8:0> 31FF ic PORTF 02EA — — RF<13:12> — — — RF<8:0> xxxx ro c LATF 02EC — — LATF<13:12> — — — LATF<8:0> xxxx h ip T ODCF 02EE — — ODF<13:12> — — — ODF<8:0> 0000 ec Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. hn Note 1: These bits are unimplemented in 64-pin and 80-pin devices, read as ‘0’. olo 2: These bits are unimplemented in 64-pin devices, read as ‘0’. g y In c . TABLE 4-18: PORTG REGISTER MAP File Addr Bit 15(1) Bit 14(1) Bit 13(1) Bit 12(1) Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1(2) Bit 0(2) All Name Resets P TRISG 02F0 TRISG<15:12> — — TRISG<9:6> — — TRISG<3:0> F3CF PORTG 02F2 RG<15:12> — — RG<9:6> — — RG<3:0> xxxx I C LATG 02F4 LATG<15:12> — — LATG<9:6> — — LATG<3:0> xxxx ODCG 02F6 ODG<15:12> — — ODG<9:6> — — ODG<3:0> 0000 2 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. 4 Note 1: These bits are unimplemented in 64-pin and 80-pin devices, read as ‘0’. F 2: These bits are unimplemented in 64-pin devices, read as ‘0’. J 1 TABLE 4-19: PAD CONFIGURATION REGISTER MAP (PADCFG1) 2 8 All File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 G Resets PADCFG1 02FC — — — — — — — — — — — — — — — PMPTTL 0000 A Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 3 1 0 D S F 3 0 A 0 0 9 9 M 9 6 G -p IL a g e 5 Y 5

DS TABLE 4-20: ADC REGISTER MAP P 3 0 I 0 All C 0 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 Resets 9 9 2 6G ADC1BUF0 0300 ADC Data Buffer 0/Threshold for Channel 0 xxxx 4 -p ADC1BUF1 0302 ADC Data Buffer 1/Threshold for Channel 1 xxxx a F g e ADC1BUF2 0304 ADC Data Buffer 2/Threshold for Channel 2 xxxx 5 J 6 ADC1BUF3 0306 ADC Data Buffer 3/Threshold for Channel 3 xxxx 1 ADC1BUF4 0308 ADC Data Buffer 4/Threshold for Channel 4 xxxx 2 ADC1BUF5 030A ADC Data Buffer 5/Threshold for Channel 5 xxxx 8 ADC1BUF6 030C ADC Data Buffer 6/Threshold for Channel 6 xxxx G ADC1BUF7 030E ADC Data Buffer 7/Threshold for Channel 7 xxxx ADC1BUF8 0310 ADC Data Buffer 8/Threshold for Channel 8 xxxx A ADC1BUF9 0312 ADC Data Buffer 9/Threshold for Channel 9 xxxx 3 ADC1BUF10 0314 ADC Data Buffer 10/Threshold for Channel 10 xxxx 1 ADC1BUF11 0316 ADC Data Buffer 11/Threshold for Channel 11 xxxx 0 ADC1BUF12 0318 ADC Data Buffer 12/Threshold for Channel 12 xxxx ADC1BUF13 031A ADC Data Buffer 13/Threshold for Channel 13/Threshold for Channel 0 in Windowed Compare xxxx F ADC1BUF14 031C ADC Data Buffer 14/Threshold for Channel 14/Threshold for Channel 1 in Windowed Compare xxxx A ADC1BUF15 031E ADC Data Buffer 15/Threshold for Channel 15/Threshold for Channel 2 in Windowed Compare xxxx M ADC1BUF16 0320 ADC Data Buffer 16/Threshold for Channel 16/Threshold for Channel 3 in Windowed Compare(1) xxxx ADC1BUF17 0322 ADC Data Buffer 17/Threshold for Channel 17/Threshold for Channel 4 in Windowed Compare(1) xxxx I L ADC1BUF18 0324 ADC Data Buffer 18/Threshold for Channel 18/Threshold for Channel 5 in Windowed Compare(1) xxxx Y ADC1BUF19 0326 ADC Data Buffer 19/Threshold for Channel 19/Threshold for Channel 6 in Windowed Compare(1) xxxx ADC1BUF20 0328 ADC Data Buffer 20/Threshold for Channel 20/Threshold for Channel 7 in Windowed Compare(1) xxxx ADC1BUF21 032A ADC Data Buffer 21/Threshold for Channel 21/Threshold for Channel 8 in Windowed Compare(1) xxxx ADC1BUF22 032C ADC Data Buffer 22/Threshold for Channel 22/Threshold for Channel 9 in Windowed Compare(1) xxxx ADC1BUF23 032E ADC Data Buffer 23/Threshold for Channel 23/Threshold for Channel 10 in Windowed Compare(1) xxxx  2 ADC1BUF24 0330 ADC Data Buffer 24/Threshold for Channel 24/Threshold for Channel 11 in Windowed Compare xxxx 0 1 ADC1BUF25 0332 ADC Data Buffer 25/Threshold for Channel 25/Threshold for Channel 12 in Windowed Compare xxxx 0 -20 AD1CON1 0340 ADON — ADSIDL DMABM DMAEN MODE12 FORM1 FORM0 SSRC3 SSRC2 SSRC1 SSRC0 — ASAM SAMP DONE 0000 1 4 AD1CON2 0342 PVCFG1 PVCFG0 NVCFG0 OFFCAL BUFREGEN CSCNA — — BUFS SMPI4 SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS 0000 M ic AD1CON3 0344 ADRC EXTSAM PUMPEN SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 0000 roc AD1CHS 0348 CH0NB2 CH0NB1 CH0NB0 CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA2 CH0NA1 CH0NA0 CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 0000 h ip AD1CSSH 034E — CSS<30:16> 0000 T e AD1CSSL 0350 CSS<15:0> 0000 c h n Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. o lo Note 1: These bits are unimplemented in 64-pin and 80-pin devices, read as ‘0’. g y In c .

 TABLE 4-20: ADC REGISTER MAP (CONTINUED) 2 0 1 All 0 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -2 Resets 0 14 AD1CON4 0352 — — — — — — — — — — — — — DMABL2 DMABL1 DMABL0 0000 M ic AD1CON5 0354 ASEN LPEN CTMREQ BGREQ — — ASINT1 ASINT0 — — — — WM1 WM0 CM1 CM0 0000 ro AD1CHITH 0356 — — — — — — CHH<25:16>(1) 0000 c h ip AD1CHITL 0358 CHH<15:0> 0000 Te AD1CTMENH 0360 — CTMEN<30:16> 0000 c hn AD1CTMENL 0362 CTMEN<15:0> 0000 o lo AD1DMBUF 0364 Conversion Data Buffer (Extended Buffer mode) xxxx g y Inc LNeogteend1:: —Th e=s uen bimitsp alerme eunntimedp, leremaedn ates d‘0 in’. R64e-speint vaanlude 8s0 a-prein s dheovwicne isn, hreeaxda daesc ‘i0m’.al. . TABLE 4-21: CTMU REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All P Resets I CTMUCON1 035A CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG — — — — — — — — 0000 C CTMUCON2 035C EDG1MOD EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT EDG2MOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0 — — 0000 2 CTMUICON 035E ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 — — — — — — — — 0000 4 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. F J TABLE 4-22: ANALOG CONFIGURATION REGISTER MAP(4) 1 2 All File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 8 Resets G ANCFG 04DE — — — — — — — — — — — — — VBG6EN VBG2EN VBGEN 0000 ANSA 04E0 — — — — — ANSA<10:9>(3) — ANSA<7:6>(1) — — — — — — 00C0 A ANSB 04E2 ANSB<15:0> FFFF 3 ANSC 04E4 — — — — — — — — — — — ANSC4(1) — — — — 0010 1 ANSD 04E6 — — — — ANSD<11:10> — — ANSD<7:6> — — — — — — 0CC0 0 D ANSE 04E8 — — — — — — ANSE9(2) — ANSE<7:4> — — — — 02F0 S ANSG 04EC — — — — — — ANSG<9:6> — — — — — — 03C0 F 3 00 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. A 09 Note 1: These bits are unimplemented in 64-pin and 80-pin devices, read as ‘0’. 99 2: This bit is unimplemented in 64-pin devices. In 80-pin devices, this bit needs to be cleared to get digital functionality on RE9. M 6 G 3: These bits are unimplemented in 64-pin devices. -p 4: ANSA, ANSB, ANSC, ANSD, ANSE and ANSG registers are used to configure the pins as analog or digital. Implemented bits in these registers indicate the analog pins on these ports. IL a g e 5 Y 7

DS TABLE 4-23: DMA REGISTER MAP P 3 0 I 00 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All C 9 Resets 9 9 2 6 DMACON 0380 DMAEN — — — — — — — — — — — — — — PRSSEL 0000 G 4 -p DMABUF 0382 DMA Transfer Data Buffer 0000 ag DMAL 0384 DMA High Address Limit 0000 F e 5 DMAH 0386 DMA Low Address Limit 0000 J 8 DMACH0 0388 — — — — — NULLW RELOAD CHREQ SAMODE1 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 SIZE CHEN 0000 1 DMAINT0 038A DBUFWF — CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 HIGHIF LOWIF DONEIF HALFIF OVRUNIF — — HALFEN 0000 2 DMASRC0 038C DMA Channel 0 Source Address 0000 8 DMADST0 038E DMA Channel 0 Destination Address 0000 G DMACNT0 0390 DMA Channel 0 Transaction Count 0001 DMACH1 0392 — — — — — NULLW RELOAD CHREQ SAMODE1 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 SIZE CHEN 0000 A DMAINT1 0394 DBUFWF — CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 HIGHIF LOWIF DONEIF HALFIF OVRUNIF — — HALFEN 0000 3 DMASRC1 0396 DMA Channel 1 Source Address 0000 1 DMADST1 0398 DMA Channel 1 Destination Address 0000 0 DMACNT1 039A DMA Channel 1 Transaction Count 0001 DMACH2 039C — — — — — NULLW RELOAD CHREQ SAMODE1 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 SIZE CHEN 0000 F DMAINT2 039E DBUFWF — CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 HIGHIF LOWIF DONEIF HALFIF OVRUNIF — — HALFEN 0000 A DMASRC2 03A0 DMA Channel 2 Source Address 0000 DMADST2 03A2 DMA Channel 2 Destination Address 0000 M DMACNT2 03A4 DMA Channel 2 Transaction Count 0001 I DMACH3 03A6 — — — — — NULLW RELOAD CHREQ SAMODE1 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 SIZE CHEN 0000 L DMAINT3 03A8 DBUFWF — CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 HIGHIF LOWIF DONEIF HALFIF OVRUNIF — — HALFEN 0000 Y DMASRC3 03AA DMA Channel 3 Source Address 0000 DMADST3 03AC DMA Channel 3 Destination Address 0000 DMACNT3 03AE DMA Channel 3 Transaction Count 0001 DMACH4 03B0 — — — — — NULLW RELOAD CHREQ SAMODE1 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 SIZE CHEN 0000 DMAINT4 03B2 DBUFWF — CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 HIGHIF LOWIF DONEIF HALFIF OVRUNIF — — HALFEN 0000  DMASRC4 03B4 DMA Channel 4 Source Address 0000 2 0 DMADST4 03B6 DMA Channel 4 Destination Address 0000 1 0-2 DMACNT4 03B8 DMA Channel 4 Transaction Count 0001 01 DMACH5 03BA — — — — — NULLW RELOAD CHREQ SAMODE1 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 SIZE CHEN 0000 4 M DMAINT5 03BC DBUFWF — — CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 HIGHIF LOWIF DONEIF HALFIF OVRUNIF — — HALFEN 0000 ic DMASRC5 03BE DMA Channel 5 Source Address 0000 ro c DMADST5 03C0 DMA Channel 5 Destination Address 0000 h ip DMACNT5 03C2 DMA Channel 5 Transaction Count 0001 T e Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. c h n o lo g y In c .

 TABLE 4-24: LCD REGISTER MAP 2 0 10-2 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts 0 1 4 LCDREG 0580 CPEN — — — — — — — — — BIAS2 BIAS1 BIAS0 MODE13 CKSEL1 CKSEL0 0000 M ic LCDREF 0582 LCDIRE — LCDCST2 LCDCST1 LCDCST0 VLCD3PE VLCD2PE VLCD1PE LRLAP1 LRLAP0 LRLBP1 LRLBP0 — LRLAT2 LRLAT1 LRLAT0 0000 ro c LCDCON 0584 LCDEN — LCDSIDL — — — — — — SLPEN WERR CS1 CS0 LMUX2 LMUX1 LMUX0 0000 h ip LCDPS 0586 — — — — — — — — WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 0000 T ec LCDDATA0 0590 S15C0 S14C0 S13C0 S12C0 S11C0 S10C0 S09C0 S08C0 S07C0 S06C0 S05C0 S04C0 S03C0 S02C0 S01C0 S00C0 0000 h n LCDDATA1 0592 S31C0 S30C0 S29C0 S28C0 S27C0 S26C0 S25C0 S24C0 S23C0 S22C0 S21C0 S20C0 S19C0 S18C0 S17C0 S16C0 0000 o log LCDDATA2 0594 S47C0 S46C0(1) S45C0(1) S44C0(1) S43C0(1) S42C0(1) S41C0(1) S40C0(1) S39C0(1) S38C0(1) S37C0(1) S36C0(1) S35C0(1) S34C0(1) S33C0(1) S32C0(1) 0000 y In LCDDATA3 0596 S63C0(2) S62C0(2) S61C0(2) S60C0(2) S59C0(2) S58C0(2) S57C0(2) S56C0(2) S55C0(2) S54C0(2) S53C0(2) S52C0(2) S51C0(2) S50C0(1) S49C0(2) S48C0 0000 c . LCDDATA4 0598 S15C1 S14C1 S13C1 S12C1 S11C1 S10C1 S09C1 S08C1 S07C1 S06C1 S05C1 S04C1 S03C1 S02C1 S01C1 S00C1 0000 LCDDATA5 059A S31C1 S30C1 S29C1 S28C1 S27C1 S26C1 S25C1 S24C1 S23C1 S22C1 S21C1 S20C1 S19C1 S18C1 S17C1 S16C1 0000 LCDDATA6 059C S47C1 S46C1(1) S45C1(1) S44C1(1) S43C1(1) S42C1(1) S41C1(1) S40C1(1) S39C1(1) S38C1(1) S37C1(1) S36C1(1) S35C1(1) S34C1(1) S33C1(1) S32C1(1) 0000 LCDDATA7 059E S63C1(2) S62C1(2) S61C1(2) S60C1(2) S59C1(2) S58C1(2) S57C1(2) S56C1(2) S55C1(2) S54C1(2) S53C1(2) S52C1(2) S51C1(2) S50C1(1) S49C1(2) S48C1 0000 LCDDATA8 05A0 S15C2 S14C2 S13C2 S12C2 S11C2 S10C2 S09C2 S08C2 S07C2 S06C2 S05C2 S04C2 S03C2 S02C2 S01C2 S00C2 0000 P LCDDATA9 05A2 S31C2 S30C2 S29C2 S28C2 S27C2 S26C2 S25C2 S24C2 S23C2 S22C2 S21C2 S20C2 S19C2 S18C2 S17C2 S16C2 0000 I LCDDATA10 05A4 S47C2 S46C2(1) S45C2(1) S44C2(1) S43C2(1) S42C2(1) S41C2(1) S40C2(1) S39C2(1) S38C2(1) S37C2(1) S36C2(1) S35C2(1) S34C2(1) S33C2(1) S32C2(1) 0000 C LCDDATA11 05A6 S63C2(2) S62C2(2) S61C2(2) S60C2(2) S59C2(2) S58C2(2) S57C2(2) S56C2(2) S55C2(2) S54C2(2) S53C2(2) S52C2(2) S51C2(2) S50C2(1) S49C2(2) S48C2 0000 2 LCDDATA12 05A8 S15C3 S14C3 S13C3 S12C3 S11C3 S10C3 S09C3 S08C3 S07C3 S06C3 S05C3 S04C3 S03C3 S02C3 S01C3 S00C3 0000 4 LCDDATA13 05AA S31C3 S30C3 S29C3 S28C3 S27C3 S26C3 S25C3 S24C3 S23C3 S22C3 S21C3 S20C3 S19C3 S18C3 S17C3 S16C3 0000 F LCDDATA14 05AC S47C3 S46C3(1) S45C3(1) S44C3(1) S43C3(1) S42C3(1) S41C3(1) S40C3(1) S39C3(1) S38C3(1) S37C3(1) S36C3(1) S35C3(1) S34C3(1) S33C3(1) S32C3(1) 0000 J LCDDATA15 05AE S63C3(2) S62C3(2) S61C3(2) S60C3(2) S59C3(2) S58C3(2) S57C3(2) S56C3(2) S55C3(2) S54C3(2) S53C3(2) S52C3(2) S51C3(2) S50C3(1) S49C3(2) S48C3 0000 1 LCDSE3 058E SE63(2) SE62(2) SE61(2) SE60(2) SE59(2) SE58(2) SE57(2) SE56(2) SE55(2) SE54(2) SE53(2) SE52(2) SE51(2) SE50(1) SE49(2) SE48 0000 2 LCDSE2 058C SE47 SE46(1) SE45(1) SE44(1) SE43(1) SE42(1) SE41(1) SE40(1) SE39(1) SE38(1) SE37(1) SE36(1) SE35(1) SE34(1) SE33(1) SE32(1) 0000 8 LCDSE1 058A SE<31:16> 0000 G LCDSE0 0588 SE<15:0> 0000 A LCDDATA16 05B0 S15C4 S14C4 S13C4 S12C4 S11C4 S10C4 S09C4 S08C4 S07C4 S06C4 S05C4 S04C4 S03C4 S02C4 S01C4 S00C4 0000 LCDDATA17 05B2 S31C4 S30C4 S29C4 S28C4 S27C4 S26C4 S25C4 S24C4 S23C4 S22C4 S21C4 S20C4 S19C4 S18C4 S17C4 S16C4 0000 3 LCDDATA18 05B4 S47C4 S46C4(1) S45C4(1) S44C4(1) S43C4(1) S42C4(1) S41C4(1) S40C4(1) S39C4(1) S38C4(1) S37C4(1) S36C4(1) S35C4(1) S34C4(1) S33C4(1) S32C4(1) 0000 1 LCDDATA19 05B6 S63C4(2) S62C4(2) S61C4(2) S60C4(2) S59C4(2) S58C4(2) S57C4(2) S56C4(2) S55C4(2) S54C4(2) S53C4(2) S52C4(2) S51C4(2) S50C4(1) S49C4(2) S48C4 0000 0 D LCDDATA20 05B8 S15C5 S14C5 S13C5 S12C5 S11C5 S10C5 S09C5 S08C5 S07C5 S06C5 S05C5 S04C5 S03C5 S02C5 S01C5 S00C5 0000 S3 LCDDATA21 05BA S31C5 S30C5 S29C5 S28C5 S27C5 S26C5 S25C5 S24C5 S23C5 S22C5 S21C5 S20C5 S19C5 S18C5 S17C5 S16C5 0000 F 00 LCDDATA22 05BC S47C5 S46C5(1) S45C5(1) S44C5(1) S43C5(1) S42C5(1) S41C5(1) S40C5(1) S39C5(1) S38C5(1) S37C5(1) S36C5(1) S35C5(1) S34C5(1) S33C5(1) S32C5(1) 0000 A 0 99 LCDDATA23 05BE S63C5(2) S62C5(2) S61C5(2) S60C5(2) S59C5(2) S58C5(2) S57C5(2) S56C5(2) S55C5(2) S54C5(2) S53C5(2) S52C5(2) S51C5(2) S50C5(1) S49C5(2) S48C5 0000 M 9 6G Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. -p Note 1: These bits are unimplemented in 64-pin devices, read as ‘0’. IL ag 2: These bits are unimplemented in 64-pin and 80-pin devices, devices, read as ‘0’. e 5 Y 9

D TABLE 4-24: LCD REGISTER MAP (CONTINUED) P S 3 0 All I 0 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C 0 Resets 9 9 96 LCDDATA24 05C0 S15C6 S14C6 S13C6 S12C6 S11C6 S10C6 S09C6 S08C6 S07C6 S06C6 S05C6 S04C6 S03C6 S02C6 S01C6 S00C6 0000 2 G-p LCDDATA25 05C2 S31C6 S30C6 S29C6 S28C6 S27C6 S26C6 S25C6 S24C6 S23C6 S22C6 S21C6 S20C6 S19C6 S18C6 S17C6 S16C6 0000 4 ag LCDDATA26 05C4 S47C6 S46C6(1) S45C6(1) S44C6(1) S43C6(1) S42C6(1) S41C6(1) S40C6(1) S39C6(1) S38C6(1) S37C6(1) S36C6(1) S35C6(1) S34C6(1) S33C6(1) S32C6(1) 0000 F e 6 LCDDATA27 05C6 S63C6(2) S62C6(2) S61C6(2) S60C6(2) S59C6(2) S58C6(2) S57C6(2) S56C6(2) S55C6(2) S54C6(2) S53C6(2) S52C6(2) S51C6(2) S50C6(1) S49C6(2) S48C6 0000 J 0 LCDDATA28 05C8 S15C7 S14C7 S13C7 S12C7 S11C7 S10C7 S09C7 S08C7 S07C7 S06C7 S05C7 S04C7 S03C7 S02C7 S01C7 S00C7 0000 1 LCDDATA29 05CA S31C7 S30C7 S29C7 S28C7 S27C7 S26C7 S25C7 S24C7 S23C7 S22C7 S21C7 S20C7 S19C7 S18C7 S17C7 S16C7 0000 2 LCDDATA30 05CC S47C7 S46C7(1) S45C7(1) S44C7(1) S43C7(1) S42C7(1) S41C7(1) S40C7(1) S39C7(1) S38C7(1) S37C7(1) S36C7(1) S35C7(1) S34C7(1) S33C7(1) S32C7(1) 0000 8 LCDDATA31 05CE S63C7(2) S62C7(2) S61C7(2) S60C7(2) S59C7(2) S58C7(2) S57C7(2) S56C7(2) S55C7(2) S54C7(2) S53C7(2) S52C7(2) S51C7(2) S50C7(1) S49C7(2) S48C7 0000 G Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. A Note 1: These bits are unimplemented in 64-pin devices, read as ‘0’. 2: These bits are unimplemented in 64-pin and 80-pin devices, devices, read as ‘0’. 3 1 0 TABLE 4-25: PARALLEL MASTER/SLAVE PORT REGISTER MAP F All File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets A PMCON1 0600 PMPEN — PSIDL ADRMUX1 ADRMUX0 — MODE1 MODE0 CSF1 CSF0 ALP ALMODE — BUSKEEP IRQM1 IRQM0 0000 M PMCON2 0602 BUSY — ERROR TIMEOUT — — — — RADDR23 RADDR22 RADDR21 RADDR20 RADDR19 RADDR18 RADDR17 RADDR16 0000 I PMCON3 0604 PTWREN PTRDEN PTBE1EN PTBE0EN — AWAITM1 AWAITM0 AWAITE — PTEN22 PTEN21 PTEN20 PTEN19 PTEN18 PTEN17 PTEN16 0000 L PMCON4 0606 PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 0000 Y PMCS1CF 0608 CSDIS CSP CSPTEN BEP — WRSP RDSP SM ACKP PTSZ1 PTSZ0 — — — — — 0000 PMCS1BS 060A BASE23 BASE22 BASE21 BASE20 BASE19 BASE18 BASE17 BASE16 BASE15 — — — BASE11 — — — 0200 PMCS1MD 060C ACKM1 ACKM0 AMWAIT2 AMWAIT1 AMWAIT0 — — — DWAITB1 DWAITB0 DWAITM3 DWAITM2 DWAITM1 DWAITM0 DWAITE1 DWAITE0 0000 PMCS2CF 060E CSDIS CSP CSPTEN BEP — WRSP RDSP SM ACKP PTSZ1 PTSZ0 — — — — — 0000  PMCS2BS 0610 BASE23 BASE22 BASE21 BASE20 BASE19 BASE18 BASE17 BASE16 BASE15 — — — BASE11 — — — 0600 2 PMCS2MD 0612 ACKM1 ACKM0 AMWAIT2 AMWAIT1 AMWAIT0 — — — DWAITB1 DWAITB0 DWAITM3 DWAITM2 DWAITM1 DWAITM0 DWAITE1 DWAITE0 0000 0 1 0 PMDOUT1 0614 Data Out Register 1<15:8> Data Out Register 1<7:0> xxxx -2 0 PMDOUT2 0616 Data Out Register 2<15:8> Data Out Register 2<7:0> xxxx 1 4 M PMDIN1 0618 Data In Register 1<15:8> Data In Register 1<7:0> xxxx ic PMDIN2 061A Data In Register 2<15:8> Data In Register 2<7:0> xxxx ro ch PMSTAT 061C IBF IBOV — — IB3F IB2F IB1F IB0F OBE OBUF — — OB3E OB2E OB1E OB0E 008F ip T Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. e c h n o lo g y In c .

 TABLE 4-26: REAL-TIME CLOCK AND CALENDAR (RTCC) REGISTER MAP 2 0 1 0 All -2 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 0 1 4 M ALRMVAL 0620 Alarm Value Register Window Based on ALRMPTR<1:0> xxxx ic ALCFGRPT 0622 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000 ro c RTCVAL 0624 RTCC Value Register Window Based on RTCPTR<1:0> xxxx h ip T RCFGCAL 0626 RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 Note 1 ec RTCPWC 0628 PWCEN PWCPOL PWCPRE PWSPRE RTCLK1 RTCLK0 RTCOUT1 RTCOUT0 — — — — — — — — Note 1 h no Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. lo Note 1: The status of the RCFGCAL and RTCPWR registers on POR is ‘0000’, and on other Resets, it is unchanged. g y In c . TABLE 4-27: DATA SIGNAL MODULATOR (DSM) REGISTER MAP All File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets MDCON 062A MDEN — MDSIDL — — — — — — MDOE MDSLR MDOPOL — — — MDBIT 0020 P MDSRC 062C — — — — — — — — SODIS — — — MS3 MS2 MS1 MS0 000x I MDCAR 062E CHODIS CHPOL CHSYNC — CH3 CH2 CH1 CH0 CLODIS CLPOL CLSYNC — CL3 CL2 CL1 CL0 0000 C Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 4 F TABLE 4-28: COMPARATORS REGISTER MAP J All 1 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 2 CMSTAT 0630 CMIDL — — — C3EVT C2EVT C1EVT — — — — — C3OUT C2OUT C1OUT 0000 8 CVRCON 0632 — — — — — CVREFP CVREFM1 CVREFM0 CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 G CM1CON 0634 CON COE CPOL — — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000 A CM2CON 0636 CON COE CPOL — — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000 CM3CON 0638 CON COE CPOL — — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000 3 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1 0 D S F 3 0 A 0 0 9 9 M 9 6 G -p IL a g e 6 Y 1

D TABLE 4-29: CRC REGISTER MAP P S 3 0 All I 0 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C 0 Resets 9 9 96 CRCCON1 0640 CRCEN — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN — — — 0040 2 G-p CRCCON2 0642 — — — DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0 — — — PLEN4 PLEN3 PLEN2 PLEN1 PLEN0 0000 4 ag CRCXORL 0644 X<15:1> — 0000 F e 6 CRCXORH 0646 X<31:16> 0000 J 2 CRCDATL 0648 CRC Data Input Register Low 0000 1 CRCDATH 064A CRC Data Input Register High 0000 2 CRCWDATL 064C CRC Result Register Low 0000 8 CRCWDATH 064E CRC Result Register High 0000 G Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. A 3 TABLE 4-30: PERIPHERAL PIN SELECT REGISTER MAP 1 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All 0 Resets RPINR0 0680 — — INT1R5 INT1R4 INT1R3 INT1R2 INT1R1 INT1R0 — — — — — — — — 3F3F F RPINR1 0682 — — INT3R5 INT3R4 INT3R3 INT3R2 INT3R1 INT3R0 — — INT2R5 INT2R4 INT2R3 INT2R2 INT2R1 INT2R0 3F3F A RPINR2 0684 — — — — — — — — — — INT4R5 INT4R4 INT4R3 INT4R2 INT4R1 INT4R0 3F3F M RPINR3 0686 — — T3CKR5 T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0 — — T2CKR5 T2CKR4 T2CKR3 T2CKR2 T2CKR1 T2CKR0 3F3F RPINR4 0688 — — T5CKR5 T5CKR4 T5CKR3 T5CKR2 T5CKR1 T5CKR0 — — T4CKR5 T4CKR4 T4CKR3 T4CKR2 T4CKR1 T4CKR0 3F3F IL RPINR7 068E — — IC2R5 IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 — — IC1R5 IC1R4 IC1R3 IC1R2 IC1R1 IC1R0 3F3F Y RPINR8 0690 — — IC4R5 IC4R4 IC4R3 IC4R2 IC4R1 IC4R0 — — IC3R5 IC3R4 IC3R3 IC3R2 IC3R1 IC3R0 3F3F RPINR9 0692 — — IC6R5 IC6R4 IC6R3 IC6R2 IC6R1 IC6R0 — — IC5R5 IC5R4 IC5R3 IC5R2 IC5R1 IC5R0 3F3F RPINR10 0694 — — — — — — — — — — IC7R5 IC7R4 IC7R3 IC7R2 IC7R1 IC7R0 003F RPINR11 0696 — — OCFBR5 OCFBR4 OCFBR3 OCFBR2 OCFBR1 OCFBR0 — — OCFAR5 OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0 3F3F RPINR17 06A2 — — U3RXR5 U3RXR4 U3RXR3 U3RXR2 U3RXR1 U3RXR0 — — — — — — — — 3F00  2 RPINR18 06A4 — — U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 — — U1RXR5 U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0 3F3F 0 10 RPINR19 06A6 — — U2CTSR5 U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0 — — U2RXR5 U2RXR4 U2RXR3 U2RXR2 U2RXR1 U2RXR0 3F3F -20 RPINR20 06A8 — — SCK1R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 — — SDI1R5 SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0 3F3F 1 4 M RPINR21 06AA — — U3CTSR5 U3CTSR4 U3CTSR3 U3CTSR2 U3CTSR1 U3CTSR0 — — SS1R5 SS1R4 SS1R3 SS1R2 SS1R1 SS1R0 3F3F ic RPINR22 06AC — — SCK2R5 SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 — — SDI2R5 SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0 3F3F ro c RPINR23 06AE — — T1CKR5 T1CKR4 T1CKR3 T1CKR2 T1CKR1 T1CKR0 — — SS2R5 SS2R4 SS2R3 SS2R2 SS2R1 SS2R0 003F h ip RPINR27 06B6 — — U4CTSR5 U4CTSR4 U4CTSR3 U4CTSR2 U4CTSR1 U4CTSR0 — — U4RXR5 U4RXR4 U4RXR3 U4RXR2 U4RXR1 U4RXR0 3F3F T ec RPINR30 06BC — — — — — — — — — — MDMIR5 MDMIR4 MDMIR3 MDMIR2 MDMIR1 MDMIR0 003F h n RPINR31 06BE — — MDC2R5 MDC2R4 MDC2R3 MDC2R2 MDC2R1 MDC2R0 — — MDC1R5 MDC1R4 MDC1R3 MDC1R2 MDC1R1 MDC1R0 3F3F o log Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. y Inc Note 12:: TThheessee bbiittss aarree uunniimmpplleemmeenntteedd iinn 6644--ppiinn adnedvi c8e0s-p, rine adde vaisc e‘0s’,. read as ‘0’. .

 TABLE 4-30: PERIPHERAL PIN SELECT REGISTER MAP (CONTINUED) 2 0 1 All 0 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -2 Resets 0 14 RPOR0 06C0 — — RP1R5 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 — — RP0R5 RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 0000 M ic RPOR1 06C2 — — RP3R5 RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 — — RP2R5 RP2R4 RP2R3 RP2R2 RP2R1 RP2R0 0000 ro RPOR2 06C4 — — RP5R5(1) RP5R4(1) RP5R3(1) RP5R2(1) RP5R1(1) RP5R0(1) — — RP4R5 RP4R4 RP4R3 RP4R2 RP4R1 RP4R0 0000 c h ip RPOR3 06C6 — — RP7R5 RP7R4 RP7R3 RP7R2 RP7R1 RP7R0 — — RP6R5 RP6R4 RP6R3 RP6R2 RP6R1 RP6R0 0000 Te RPOR4 06C8 — — RP9R5 RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 — — RP8R5 RP8R4 RP8R3 RP8R2 RP8R1 RP8R0 0000 c hn RPOR5 06CA — — RP11R5 RP11R4 RP11R3 RP11R2 RP11R1 RP11R0 — — RP10R5 RP10R4 RP10R3 RP10R2 RP10R1 RP10R0 0000 o lo RPOR6 06CC — — RP13R5 RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 — — RP12R5 RP12R4 RP12R3 RP12R2 RP12R1 RP12R0 0000 g y In RPOR7 06CE — — RP15R5(1) RP15R4(1) RP15R3(1) RP15R2(1) RP15R1(1) RP15R0(1) — — RP14R5 RP14R4 RP14R3 RP14R2 RP14R1 RP14R0 0000 c. RPOR8 06D0 — — RP17R5 RP17R4 RP17R3 RP17R2 RP17R1 RP17R0 — — RP16R5 RP16R4 RP16R3 RP16R2 RP16R1 RP16R0 0000 RPOR9 06D2 — — RP19R5 RP19R4 RP19R3 RP19R2 RP19R1 RP19R0 — — RP18R5 RP18R4 RP18R3 RP18R2 RP18R1 RP18R0 0000 RPOR10 06D4 — — RP21R5 RP21R4 RP21R3 RP21R2 RP21R1 RP21R0 — — RP20R5 RP20R4 RP20R3 RP20R2 RP20R1 RP20R0 0000 RPOR11 06D6 — — RP23R5 RP23R4 RP23R3 RP23R2 RP23R1 RP23R0 — — RP22R5 RP22R4 RP22R3 RP22R2 RP22R1 RP22R0 0000 RPOR12 06D8 — — RP25R5 RP25R4 RP25R3 RP25R2 RP25R1 RP25R0 — — RP24R5 RP24R4 RP24R3 RP24R2 RP24R1 RP24R0 0000 P RPOR13 06DA — — RP27R5 RP27R4 RP27R3 RP27R2 RP27R1 RP27R0 — — RP26R5 RP26R4 RP26R3 RP26R2 RP26R1 RP26R0 0000 I RPOR14 06DC — — RP29R5 RP29R4 RP29R3 RP29R2 RP29R1 RP29R0 — — RP28R5 RP28R4 RP28R3 RP28R2 RP28R1 RP28R0 0000 C RPOR15 06DE — — RP31R5(2) RP31R4(2) RP31R3(2) RP31R2(2) RP31R1(2) RP31R0(2) — — RP30R5 RP30R4 RP30R3 RP30R2 RP30R1 RP30R0 0000 2 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 4 Note 1: These bits are unimplemented in 64-pin devices, read as ‘0’. 2: These bits are unimplemented in 64-pin and 80-pin devices, read as ‘0’. F J 1 TABLE 4-31: SYSTEM CONTROL (CLOCK AND RESET) REGISTER MAP 2 All 8 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets G RCON 0740 TRAPR IOPUWR — RETEN — DPSLP CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Note 1 A OSCCON 0742 — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK IOLOCK LOCK — CF POSCEN SOSCEN OSWEN Note 2 3 CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0 — — — — — — — — 3100 1 OSCTUN 0748 — — — — — — — — — — TUN<5:0> 0000 0 REFOCON 074E ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 — — — — — — — — 0000 DS HLVDCON 0756 HLVDEN — HLSIDL — — — — — VDIR BGVST IRVST — HLVDL3 HLVDL2 HLVDL1 HLVDL0 0000 F 3 RCON2 0762 — — — — — — — — — — — r VDDBOR VDDPOR VBPOR VBAT Note 1 0 A 0 0 Legend: — = unimplemented, read as ‘0’; r = reserved. Reset values are shown in hexadecimal. 9 9 Note 1: The Reset value of the RCON register is dependent on the type of Reset event. See Section7.0 “Resets” for more information. M 9 6 2: The Reset value of the OSCCON register is dependent on both the type of Reset event and the device configuration. See Section9.0 “Oscillator Configuration” for more information. G -p IL a g e 6 Y 3

DS TABLE 4-32: DEEP SLEEP REGISTER MAP P 3 0 I 0 All C 0 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 Resets 9 9 2 6G DSCON 0758 DSEN — — — — — — — — — — — — r DSBOR RELEASE 0000(1) 4 -p DSWAKE 075A — — — — — — — DSINT0 DSFLT — — DSWDT DSRTCC DSMCLR — — 0000(1) a F ge DSGPR0 075C Deep Sleep Semaphore Data 0 0000(1) 64 DSGPR1 075E Deep Sleep Semaphore Data 1 0000(1) J 1 Legend: — = unimplemented, read as ‘0’; r = reserved. Reset values are shown in hexadecimal. Note 1: These registers are only reset on a VDD POR event. 2 8 G TABLE 4-33: NVM REGISTER MAP A All File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 3 1 NVMCON 0760 WR WREN WRERR — — — — — — ERASE — — NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1) 0 NVMKEY 0766 — — — — — — — — NVMKEY Register<7:0> 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. F Note 1: The Reset value shown is for POR only. The value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset. A M TABLE 4-34: PMD REGISTER MAP I L All File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets Y PMD1 0770 T5MD T4MD T3MD T2MD T1MD — — — I2C1MD U2MD U1MD SPI2MD SPI1MD — — ADC1MD 0000 PMD2 0772 — IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD — OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD 0000 PMD3 0774 — — — — DSMMD CMPMD RTCCMD PMPMD CRCMD — — — U3MD — I2C2MD — 0000 PMD4 0776 — — — — — — — — — UPWMMD U4MD — REFOMD CTMUMD LVDMD — 0000  2 PMD6 077A — — — — — — — — — LCDMD — — — — — SPI3MD 0000 01 PMD7 077C — — — — — — — — — — DMA1MD DMA0MD — — — — 0000 0 -2 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 1 4 M ic ro c h ip T e c h n o lo g y In c .

PIC24FJ128GA310 FAMILY 4.2.5 EXTENDED DATA SPACE (EDS) The data addressing range of PIC24FJ128GA310 family devices depends on the version of the Enhanced The Extended Data Space (EDS) allows PIC24F Parallel Master Port implemented on a particular devices to address a much larger range of data than device; this is in turn a function of device pin count. would otherwise be possible with a 16-bit address Table4-35 lists the total memory accessible by each of range. EDS includes any additional internal data mem- the devices in this family. For more details on accessing ory not directly accessible by the lower 32-Kbyte data external memory using EPMP, refer to “Enhanced address space, and any external memory through Parallel Master Port (EPMP)” (DS39730) in the EPMP. “dsPIC33/PIC24 Family Reference Manual”. In addition, EDS also allows read access to the . program memory space. This feature is called Program TABLE 4-35: TOTAL ACCESSIBLE DATA Space Visibility (PSV) and is discussed in detail in MEMORY Section4.3.3 “Reading Data from Program Memory External RAM Using EDS”. Internal Family Access Using RAM Figure4-4 displays the entire EDS space. The EDS is EPMP organized as pages, called EDS pages, with one page PIC24FJXXXGA310 8K Up to 16 MB equal to size of the EDS window (32 Kbytes). A partic- ular EDS page is selected through the Data Space PIC24FJXXXGA308 8K Up to 64K Read register (DSRPAG) or Data Space Write register PIC24FJXXXGA306 8K Up to 64K (DSWPAG). For PSV, only the DSRPAG register is used. The combination of the DSRPAG register value and the 16-bit wide data address forms a 24-bit Note: Accessing Page 0 in the EDS window will Effective Address (EA). generate an address error trap as Page 0 is the base data memory (data locations, 0800h to 7FFFh, in the lower Data Space). FIGURE 4-4: EXTENDED DATA SPACE Special 0000h Function Registers 0800h Internal Data Memory Space (up to 30 Kbytes) EDS Pages 8000h 008000h FF8000h 000000h 7F8000h 000001h 7F8001h 32-Kbyte External External Program Program Program Program EDS Memory Memory Space Space Space Space Window Access Access Access Access Access Access Using Using (Lower (Lower (Upper (Upper EPMP(1) EPMP(1) Word) Word) Word) Word) FFFEh 00FFFEh FFFFFEh 007FFEh 7FFFFEh 007FFFh 7FFFFFh DSxPAG DSx PAG DSRPAG DSRPAG DSRPAG DSRPAG = 001h = 1FFh = 200h = 2FFh = 300h = 3FFh EPMP Memory Space(1) Program Memory Note1: The range of addressable memory available is dependent on the device pin count and EPMP implementation.  2010-2014 Microchip Technology Inc. DS30009996G-page 65

PIC24FJ128GA310 FAMILY 4.2.5.1 Data Read from EDS Example4-1 shows how to read a byte, word and double-word from EDS. In order to read the data from the EDS space, first, an Address Pointer is set up by loading the required EDS Note: All read operations from EDS space have page number into the DSRPAG register and assigning an overhead of one instruction cycle. the offset address to one of the W registers. Once the Therefore, a minimum of two instruction above assignment is done, the EDS window is enabled cycles are required to complete an EDS by setting bit 15 of the Working register assigned with read. EDS reads under the REPEAT the offset address; then, the contents of the pointed instruction: the first two accesses take EDS location can be read. three cycles and the subsequent Figure4-5 illustrates how the EDS space address is accesses take one cycle. generated for read operations. When the Most Significant bit (MSb) of EA is ‘1’ and DSRPAG<9> = 0, the lower 9 bits of DSRPAG are con- catenated to the lower 15 bits of EA to form a 24-bit EDS space address for read operations. FIGURE 4-5: EDS ADDRESS GENERATION FOR READ OPERATIONS Select 1 Wn 9 8 0 DSRPAG Reg 9 Bits 15 Bits 24-Bit EA 0 = Extended SRAM and EPMP Wn<0> is Byte Select EXAMPLE 4-1: EDS READ CODE IN ASSEMBLY ; Set the EDS page from where the data to be read mov #0x0002, w0 mov w0, DSRPAG ;page 2 is selected for read mov #0x0800, w1 ;select the location (0x800) to be read bset w1, #15 ;set the MSB of the base address, enable EDS mode ;Read a byte from the selected location mov.b [w1++], w2 ;read Low byte mov.b [w1++], w3 ;read High byte ;Read a word from the selected location mov [w1], w2 ; ;Read Double - word from the selected location mov.d [w1], w2 ;two word read, stored in w2 and w3 DS30009996G-page 66  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 4.2.5.2 Data Write into EDS While developing code in assembly, care must be taken to update the Page registers when an Address Pointer In order to write data to EDS space, such as in EDS crosses the page boundary. The ‘C’ compiler keeps reads, an Address Pointer is set up by loading the track of the addressing and increments or decrements required EDS page number into the DSWPAG register, the Page registers accordingly while accessing and assigning the offset address to one of the W regis- contiguous data memory locations. ters. Once the above assignment is done, then the EDS window is enabled by setting bit 15 of the Working Note1: All write operations to EDS are executed register assigned with the offset address and the in a single cycle. accessed location can be written. 2: Use of Read/Modify/Write operation on Figure4-2 illustrates how the EDS space address is any EDS location under a REPEAT generated for write operations. instruction is not supported. For example, When the MSbs of EA are ‘1’, the lower 9 bits of BCLR, BSW, BTG, RLC f, RLNC f, DSWPAG are concatenated to the lower 15 bits of EA RRC f, RRNC f, ADD f, SUB f, to form a 24-bit EDS address for write operations. SUBR f, AND f, IOR f, XOR f, Example4-2 shows how to write a byte, word and ASR f, ASL f. double-word to EDS. 3: Use the DSRPAG register while The Page registers (DSRPAG/DSWPAG) do not performing Read/Modify/Write operations. update automatically while crossing a page boundary, when the rollover happens from 0xFFFF to 0x8000. FIGURE 4-6: EDS ADDRESS GENERATION FOR WRITE OPERATIONS Select 1 Wn 8 0 DSWPAG Reg 9 Bits 15 Bits 24-Bit EA Wn<0> is Byte Select EXAMPLE 4-2: EDS WRITE CODE IN ASSEMBLY ; Set the EDS page where the data to be written mov #0x0002, w0 mov w0, DSWPAG ;page 2 is selected for write mov #0x0800, w1 ;select the location (0x800) to be written bset w1, #15 ;set the MSB of the base address, enable EDS mode ;Write a byte to the selected location mov #0x00A5, w2 mov #0x003C, w3 mov.b w2, [w1++] ;write Low byte mov.b w3, [w1++] ;write High byte ;Write a word to the selected location mov #0x1234, w2 ; mov w2, [w1] ; ;Write a Double - word to the selected location mov #0x1122, w2 mov #0x4455, w3 mov.d w2, [w1] ;2 EDS writes  2010-2014 Microchip Technology Inc. DS30009996G-page 67

PIC24FJ128GA310 FAMILY TABLE 4-36: EDS MEMORY ADDRESS WITH DIFFERENT PAGES AND ADDRESSES Source/Destination DSRPAG DSWPAG Address while 24-Bit EA (Data Space Read (Data Space Write Comment Indirect Pointing to EDS Register) Register) Addressing x(1) x(1) 0000h to 1FFFh 000000h to Near Data Space(2) 001FFFh 2000h to 7FFFh 002000h to 007FFFh 001h 001h 008000h to 00FFFEh 002h 002h 010000h to 017FFEh 003h 003h 018000h to • • 0187FEh EPMP Memory Space • • 8000h to FFFFh • • • • • • • • • • 1FFh 1FFh FF8000h to FFFFFEh 000h 000h Invalid Address Address Error Trap(3) Note 1: If the source/destination address is below 8000h, the DSRPAG and DSWPAG registers are not considered. 2: This Data Space can also be accessed by Direct Addressing. 3: When the source/destination address is above 8000h and DSRPAG/DSWPAG are ‘0’, an address error trap will occur. 4.2.6 SOFTWARE STACK example, if it is desirable to cause a stack error trap when the stack grows beyond address 2000h in RAM, Apart from its use as a Working register, the W15 initialize the SPLIM with the value, 1FFEh. register in PIC24F devices is also used as a Software Stack Pointer (SSP). The pointer always points to the Similarly, a Stack Pointer underflow (stack error) trap is first available free word and grows from lower to higher generated when the Stack Pointer address is found to addresses. It pre-decrements for stack pops and be less than 0800h. This prevents the stack from post-increments for stack pushes, as shown in interfering with the SFR space. Figure4-7. Note that for a PC push during any CALL A write to the SPLIM register should not be immediately instruction, the MSB of the PC is zero-extended before followed by an indirect read operation using W15. the push, ensuring that the MSB is always clear. Note: A PC push during exception processing FIGURE 4-7: CALL STACK FRAME will concatenate the SRL register to the 0000h 15 0 MSB of the PC prior to the push. The Stack Pointer Limit Value register (SPLIM), associ- ated with the Stack Pointer, sets an upper address s d boundary for the stack. SPLIM is uninitialized at Reset. arss we Afosrc eisd thteo c‘a0s’ e afosr tahlle sSttaacckk Poopienrtaetri,o nSsP LmIMu<s0t > bies ows Toer Addr PC<15:0> W15 (before CALL) word-aligned. Whenever an EA is generated using Grgh 000000000 PC<22:16> W15 as a source or destination pointer, the resulting ack Hi <Free Word> W15 (after CALL) St address is compared with the value in SPLIM. If the POP : [--W15] contents of the Stack Pointer (W15) and the SPLIM reg- PUSH: [W15++] ister are equal, and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. Thus, for DS30009996G-page 68  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 4.3 Interfacing Program and Data 4.3.1 ADDRESSING PROGRAM SPACE Memory Spaces Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is The PIC24F architecture uses a 24-bit-wide program needed to create a 23-bit or 24-bit program address space and 16-bit-wide Data Space. The architecture is from 16-bit data registers. The solution depends on the also a modified Harvard scheme, meaning that data interface method to be used. can also be present in the program space. To use this data successfully, it must be accessed in a way that For table operations, the 8-bit Table Memory Page preserves the alignment of information in both spaces. Address register (TBLPAG) is used to define a 32Kword region within the program space. This is concatenated Aside from normal execution, the PIC24F architecture with a 16-bit EA to arrive at a full 24-bit program space provides two methods by which program space can be address. In this format, the MSBs of TBLPAG is used to accessed during operation: determine if the operation occurs in the user memory • Using table instructions to access individual bytes (TBLPAG<7> = 0) or the configuration memory or words anywhere in the program space (TBLPAG<7> = 1). • Remapping a portion of the program space into For remapping operations, the 10-bit Extended Data the Data Space (Program Space Visibility) Space Read register (DSRPAG) is used to define a Table instructions allow an application to read or write 16Kword page in the program space. When the Most to small areas of the program memory. This makes the Significant bit (MSb) of the EA is ‘1’, and the MSb (bit9) method ideal for accessing data tables that need to be of DSRPAG is ‘1’, the lower 8 bits of DSRPAG are con- updated from time to time. It also allows access to all catenated with the lower 15 bits of the EA to form a bytes of the program word. The remapping method 23-bit program space address. The DSRPAG<8> bit allows an application to access a large block of data on decides whether the lower word (when bit is ‘0’) or the a read-only basis, which is ideal for look ups from a higher word (when bit is ‘1’) of program memory is large table of static data. It can only access the least mapped. Unlike table operations, this strictly limits significant word of the program word. remapping operations to the user memory area. Table4-37 and Figure4-8 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P<23:0> refers to a program space word, whereas D<15:0> refers to a Data Space word. TABLE 4-37: PROGRAM SPACE ADDRESS CONSTRUCTION Access Program Space Address Access Type Space <23> <22:16> <15> <14:1> <0> Instruction Access User 0 PC<22:1> 0 (Code Execution) 0xx xxxx xxxx xxxx xxxx xxx0 TBLRD/TBLWT User TBLPAG<7:0> Data EA<15:0> (Byte/Word Read/Write) 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx Program Space Visibility User 0 DSRPAG<7:0>(2) Data EA<14:0>(1) (Block Remap/Read) 0 xxxx xxxx xxx xxxx xxxx xxxx Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is DSRPAG<0>. 2: DSRPAG<9> is always ‘1’ in this case. DSRPAG<8> decides whether the lower word or higher word of program memory is read. When DSRPAG<8> is ‘0’, the lower word is read and when it is ‘1’, the higher word is read.  2010-2014 Microchip Technology Inc. DS30009996G-page 69

PIC24FJ128GA310 FAMILY FIGURE 4-8: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter 0 Program Counter 0 23 Bits EA 1/0 Table Operations(2) 1/0 TBLPAG 8 Bits 16 Bits 24 Bits Select 1 EA 1/0 Program Space Visibility(1) 0 DSRPAG<7:0> (Remapping) 1-Bit 8 Bits 15 Bits 23 Bits User/Configuration Byte Select Space Select Note 1: DSRPAG<8> acts as word select. DSRPAG<9> should always be ‘1’ to map program memory to data memory. 2: The instructions, TBLRDH/TBLWTH/TBLRDL/TBLWTL, decide if the higher or lower word of program memory is accessed. TBLRDH/TBLWTH instructions access the higher word and TBLRDL/TBLWTL instructions access the lower word. Table Read operations are permitted in the configuration memory space. DS30009996G-page 70  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 4.3.2 DATA ACCESS FROM PROGRAM 2. TBLRDH (Table Read High): In Word mode, it MEMORY USING TABLE maps the entire upper word of a program address INSTRUCTIONS (P<23:16>) to a data address. Note that D<15:8>, the ‘phantom’ byte, will always be ‘0’. The TBLRDL and TBLWTL instructions offer a direct In Byte mode, it maps the upper or lower byte of method of reading or writing the lower word of any the program word to D<7:0> of the data address within the program space without going through address, as above. Note that the data will Data Space. The TBLRDH and TBLWTH instructions are always be ‘0’ when the upper ‘phantom’ byte is the only method to read or write the upper 8 bits of a selected (byte select = 1). program space word as data. In a similar fashion, two table instructions, TBLWTH The PC is incremented by two for each successive and TBLWTL, are used to write individual bytes or 24-bit program word. This allows program memory words to a program space address. The details of addresses to directly map to Data Space addresses. their operation are described in Section6.0 “Flash Program memory can thus be regarded as two, 16-bit Program Memory”. word-wide address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL For all table operations, the area of program memory access the space which contains the least significant space to be accessed is determined by the Table data word, and TBLRDH and TBLWTH access the space Memory Page Address register (TBLPAG). TBLPAG which contains the upper data byte. covers the entire program memory space of the device, including user and configuration spaces. When Two table instructions are provided to move byte or TBLPAG<7> = 0, the table page is located in the user word-sized (16-bit) data to and from program space. memory space. When TBLPAG<7> = 1, the page is Both function as either byte or word operations. located in configuration space. 1. TBLRDL (Table Read Low): In Word mode, it Note: Only Table Read operations will execute maps the lower word of the program space in the configuration memory space where location (P<15:0>) to a data address (D<15:0>). Device IDs are located. Table Write In Byte mode, either the upper or lower byte of operations are not allowed. the lower program word is mapped to the lower byte of a data address. The upper byte is selected when byte select is ‘1’; the lower byte is selected when it is ‘0’. FIGURE 4-9: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space TBLPAG Data EA<15:0> 02 23 15 0 000000h 23 16 8 0 00000000 00000000 020000h 00000000 030000h 00000000 ‘Phantom’ Byte TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. 800000h Only read operations are shown; write operations are also valid in the user memory area.  2010-2014 Microchip Technology Inc. DS30009996G-page 71

PIC24FJ128GA310 FAMILY 4.3.3 READING DATA FROM PROGRAM Table4-38 provides the corresponding 23-bit EDS MEMORY USING EDS address for program memory with EDS page and source addresses. The upper 32 Kbytes of Data Space may optionally be mapped into any 16K word page of the program space. For operations that use PSV and are executed outside This provides transparent access of stored constant a REPEAT loop, the MOV and MOV.D instructions will data from the Data Space without the need to use require one instruction cycle in addition to the specified special instructions (i.e., TBLRDL/H). execution time. All other instructions will require two instruction cycles in addition to the specified execution Program space access through the Data Space occurs time. when the MSb of EA is ‘1’ and the DSRPAG<9> is also ‘1’. The lower 8 bits of DSRPAG are concatenated to the For operations that use PSV, which are executed inside Wn<14:0> bits to form a 23-bit EA to access program a REPEAT loop, there will be some instances that memory. The DSRPAG<8> decides which word should require two instruction cycles in addition to the be addressed; when the bit is ‘0’, the lower word and specified execution time of the instruction: when ‘1’, the upper word of the program memory is • Execution in the first iteration accessed. • Execution in the last iteration The entire program memory is divided into 512 EDS • Execution prior to exiting the loop due to an pages, from 200h to 3FFh, each consisting of 16K words interrupt of data. Pages, 200h to 2FFh, correspond to the lower • Execution upon re-entering the loop after an words of the program memory, while 300h to 3FFh interrupt is serviced correspond to the upper words of the program memory. Any other iteration of the REPEAT loop will allow the Using this EDS technique, the entire program memory instruction accessing data, using PSV, to execute in a can be accessed. Previously, the access to the upper single cycle. word of the program memory was not supported. TABLE 4-38: EDS PROGRAM ADDRESS WITH DIFFERENT PAGES AND ADDRESSES DSRPAG Source Address while 23-Bit EA Pointing to (Data Space Read Comment Indirect Addressing EDS Register) 200h 000000h to 007FFEh Lower words of 4M program • • instructions; (8 Mbytes) for • • read operations only. • • 2FFh 7F8000h to 7FFFFEh 300h 8000h to FFFFh 000001h to 007FFFh Upper words of 4M program • • instructions (4 Mbytes remaining; • • 4Mbytes are phantom bytes) for • • read operations only. 3FFh 7F8001h to 7FFFFFh 000h Invalid Address Address error trap(1) Note 1: When the source/destination address is above 8000h and DSRPAG/DSWPAG is ‘0’, an address error trap will occur. EXAMPLE 4-3: EDS READ CODE FROM PROGRAM MEMORY IN ASSEMBLY ; Set the EDS page from where the data to be read mov #0x0202, w0 mov w0, DSRPAG ;page 0x202, consisting lower words, is selected for read mov #0x000A, w1 ;select the location (0x0A) to be read bset w1, #15 ;set the MSB of the base address, enable EDS mode ;Read a byte from the selected location mov.b [w1++], w2 ;read Low byte mov.b [w1++], w3 ;read High byte ;Read a word from the selected location mov [w1], w2 ; ;Read Double - word from the selected location mov.d [w1], w2 ;two word read, stored in w2 and w3 DS30009996G-page 72  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY FIGURE 4-10: PROGRAM SPACE VISIBILITY OPERATION TO ACCESS LOWER WORD When DSRPAG<9:8> = 10 and EA<15> = 1: Program Space Data Space DSRPAG 23 15 0 000000h 0000h 202h Data EA<14:0> 010000h 017FFEh The data in the page designated by DSRPAG is mapped into the upper half of the data memory space.... 8000h EDS Window ...while the lower 15bits of the EA specify an exact FFFFh address within the EDS area. This corre- sponds exactly to the same lower 15 bits of the actual program 7FFFFEh space address. FIGURE 4-11: PROGRAM SPACE VISIBILITY OPERATION TO ACCESS UPPER WORD When DSRPAG<9:8> = 11 and EA<15> = 1: Program Space Data Space DSRPAG 23 15 0 000000h 0000h 302h Data EA<14:0> 010001h 017FFFh The data in the page designated by DSRPAG is mapped into the upper half of the data memory space.... 8000h EDS Window ...while the lower 15bits of the EA specify an exact FFFFh address within the EDS area. This corre- sponds exactly to the same lower 15 bits of the actual program 7FFFFEh space address.  2010-2014 Microchip Technology Inc. DS30009996G-page 73

PIC24FJ128GA310 FAMILY NOTES: DS30009996G-page 74  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 5.0 DIRECT MEMORY ACCESS The controller also monitors CPU instruction process- CONTROLLER (DMA) ing directly, allowing it to be aware of when the CPU requires access to peripherals on the DMA bus, and Note: This data sheet summarizes the features automatically relinquishing control to the CPU as of the PIC24FJ128GA310 family of needed. This increases the effective bandwidth for devices. It is not intended to be a compre- handling data without DMA operations, causing a hensive reference source. To complement processor stall. This makes the controller essentially the information in this data sheet, refer to transparent to the user. “Direct Memory Access Controller The DMA controller has these features: (DMA)” (DS39742) in the “dsPIC33/PIC24 • Six multiple independent and independently Family Reference Manual”. The informa- programmable channels tion in this data sheet supersedes the • Concurrent operation with the CPU (no DMA information in the FRM. caused Wait states) The Direct Memory Access (DMA) controller is • DMA bus arbitration designed to service high data throughput peripherals • Five Programmable Address modes operating on the SFR bus, allowing them to access • Four Programmable Transfer modes data memory directly and alleviating the need for CPU • Four Flexible Internal Data Transfer modes intensive management. By allowing these data inten- sive peripherals to share their own data path, the main • Byte or word support for data transfer data bus is also deloaded, resulting in additional power • 16-Bit Source and Destination Address register savings. for each channel, dynamically updated and reloadable The DMA controller functions both as a peripheral and a direct extension of the CPU. It is located on the micro- • 16-Bit Transaction Count register, dynamically controller data bus, between the CPU and DMA updated and reloadable enabled peripherals, with direct access to SRAM. This • Upper and Lower Address Limit registers partitions the SFR bus into two buses, allowing the • Counter half-full level interrupt DMA controller access to the DMA capable peripherals • Software triggered transfer located on the new DMA SFR bus. The controller • Null Write mode for symmetric buffer operations serves as a master device on the DMA SFR bus, controlling data flow from DMA capable peripherals. A simplified block diagram of the DMA controller is shown if Figure5-1. FIGURE 5-1: DMA FUNCTIONAL BLOCK DIAGRAM CPU Execution Monitoring To DMA-Enabled To I/O Ports Peripherals and Peripherals DMACON Control DMAH Logic DMAL DMABUF Data Bus DMACH0 DMACH1 DMACH2 DMACHn DMAINT0 DMAINT1 DMAINT2 DMAINTn DMASRC0 DMASRC1 DMASRC2 DMASRCn DMADST0 DMADST1 DMADST2 DMADSTn DMACNT0 DMACNT1 DMACNT2 DMACNTn Channel 0 Channel 1 Channel 4 Channel 5 Data RAM Data RAM Address Generation  2010-2014 Microchip Technology Inc. DS30009996G-page 75

PIC24FJ128GA310 FAMILY 5.1 Summary of DMA Operations Since the source and destination addresses for any transaction can be programmed independently of the The DMA controller is capable of moving data between trigger source, the DMA controller can use any trigger addresses according to a number of different parame- to perform an operation on any peripheral. This also ters. Each of these parameters can be independently allows DMA channels to be cascaded to perform more configured for any transaction; in addition, any or all of complex transfer operations. the DMA channels can independently perform a differ- ent transaction at the same time. Transactions are 5.1.4 TRANSFER MODE classified by these parameters: The DMA controller supports four types of data trans- • Source and destination (SFRs and data RAM) fers, based on the volume of data to be moved for each • Data size (byte or word) trigger. • Trigger source • One-Shot: A single transaction occurs for each • Transfer mode (One-Shot, Repeated or trigger. Continuous) • Continuous: A series of back-to-back transactions • Addressing modes (fixed address or address occur for each trigger; the number of transactions blocks, with or without address increment/ is determined by the DMACNTx transaction decrement) counter. In addition, the DMA controller provides channel priority • Repeated One-Shot: A single transaction is per- arbitration for all channels. formed repeatedly, once per trigger, until the DMA channel is disabled. 5.1.1 SOURCE AND DESTINATION • Repeated Continuous: A series of transactions Using the DMA controller, data may be moved between are performed repeatedly, one cycle per trigger, any two addresses in the Data Space. The SFR space until the DMA channel is disabled. (0000h to 07FFh) or the data RAM space (0800h to All Transfer modes allow the option to have the source FFFFh) can serve as either the source or the destina- and destination addresses, and counter value automat- tion. Data can be moved between these areas in either ically reloaded after the completion of a transaction. direction, or between addresses in either area. The four Repeated mode transfers do this automatically. different combinations are shown in Figure5-2. 5.1.5 ADDRESSING MODES If it is necessary to protect areas of data RAM, the DMA controller allows the user to set upper and lower address The DMA controller also supports transfers between boundaries for operations in the Data Space above the single addresses or address ranges. The four basic SFR space. The boundaries are set by the DMAH and options are: DMAL Limit registers. If a DMA channel attempts an • Fixed-to-Fixed: Between two constant addresses operation outside of the address boundaries, the • Fixed-to-Block: From a constant source address transaction is terminated and an interrupt is generated. to a range of destination addresses 5.1.2 DATA SIZE • Block-to-Fixed: From a range of source addresses to a single, constant destination The DMA controller can handle both 8-bit and 16-bit address transactions. Size is user-selectable using the SIZE bit • Block-to-Block: From a range to source (DMACHx<1>). By default, each channel is configured addresses to a range of destination addresses for word-size transactions. When byte-size transac- tions are chosen, the LSb of the source and/or The option to select auto-increment or auto-decrement destination address determines if the data represents of source and/or destination addresses is available for the upper or lower byte of the data RAM location. Block Addressing modes. In addition to the four basic modes, the DMA controller 5.1.3 TRIGGER SOURCE also supports Peripheral Indirect Addressing (PIA) The DMA controller can use any one of the device’s mode, where the source or destination address is gen- 60interrupt sources to initiate a transaction. The DMA erated jointly by the DMA controller and a PIA capable trigger sources are listed in reverse order of their peripheral. When enabled, the DMA channel provides natural interrupt priority and are shown in Table5-1. a base source and/or destination address, while the peripheral provides a fixed-range offset address. For PIC24FJ128GA310 family devices, the 12-bit ADC module is the only PIA capable peripheral. Details for its use in PIA mode are provided in Section24.0 “12-Bit A/D Converter (ADC) with Threshold Scan”. DS30009996G-page 76  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY FIGURE 5-2: TYPES OF DMA DATA TRANSFERS Peripheral to Memory Memory to Peripheral SFR Area SFR Area DMASRCx DMADSTx 07FFh 07FFh 0800h 0800h Data RAM Data RAM DMAL DMAL DMA RAM Area DMA RAM Area DMADSTx DMASRCx DMAH DMAH Peripheral to Peripheral Memory to Memory SFR Area SFR Area DMASRCx DMADSTx 07FFh 07FFh 0800h 0800h Data RAM Data RAM DMAL DMAL DMA RAM Area DMA RAM Area DMASRCx DMADSTx DMAH DMAH Note: Relative sizes of memory areas are not shown to scale.  2010-2014 Microchip Technology Inc. DS30009996G-page 77

PIC24FJ128GA310 FAMILY 5.1.6 CHANNEL PRIORITY 5.3 Peripheral Module Disable Each DMA channel functions independently of the Unlike other peripheral modules, the channels of the others, but also competes with the others for access to DMA controller cannot be individually powered down the data and DMA buses. When access collisions using the Peripheral Module Disable (PMD) registers. occur, the DMA controller arbitrates between the chan- Instead, the channels are controlled as two groups. nels using a user-selectable priority scheme. Two The DMA0MD bit (PMD7<4>) selectively controls schemes are available: DMACH0 through DMACH3. The DMA1MD bit • Round-Robin: When two or more channels col- (PMD7<5>) controls DMACH4 and DMACH5. Setting lide, the lower numbered channel receives priority both bits effectively disables the DMA controller. on the first collision. On subsequent collisions, the higher numbered channels each receive priority, 5.4 Registers based on their channel number. The DMA controller uses a number of registers to con- • Fixed: When two or more channels collide, the trol its operation. The number of registers depends on lowest numbered channel always receives the number of channels implemented for a particular priority, regardless of past history. device. 5.2 Typical Setup There are always four module level registers (one control and three buffer/address): To set up a DMA channel for a basic data transfer: • DMACON: DMA Control Register (Register5-1) 1. Enable the DMA controller (DMAEN = 1) and • DMAH and DMAL: DMA High and Low Address select an appropriate channel priority scheme Limit Registers by setting or clearing PRSSEL. • DMABUF: DMA Transfer Data Buffer Register 2. Program DMAH and DMAL with the appropriate Each of the DMA channels implements five registers upper and lower address boundaries for data (two control and three buffer/address): RAM operations. 3. Select the DMA channel to be used and disable • DMACHx: DMA Channel x Control Register its operation (CHEN = 0). (Register5-2) 4. Program the appropriate source and destination • DMAINTx: DMA Channel x Interrupt Register addresses for the transaction into the channel’s (Register5-3) DMASRCx and DMADSTx registers. For PIA • DMASRCx: DMA Channel x Source Address mode addressing, use the base address value. Register 5. Program the DMACNTx register for the number • DMADSTx: DMA Channel x Destination Address of triggers per transfer (One-Shot or Continuous Register modes), or the number of words (bytes) to be • DMACNTx: DMA Channel x Transaction Count transferred (Repeated modes). Register 6. Set or clear the SIZE bit to select the data size. For PIC24FJ128GA310 family devices, there are a 7. Program the TRMODE<1:0> bits to select the total of 34 registers. Data Transfer mode. 8. Program the SAMODE<1:0> and DAMODE<1:0> bits to select the addressing mode. 9. Enable the DMA channel by setting CHEN. 10. Enable the trigger source interrupt. DS30009996G-page 78  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 5-1: DMACON: DMA ENGINE CONTROL REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 DMAEN — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PRSSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DMAEN: DMA Module Enable bit 1 = Enables module 0 = Disables module and terminates all active DMA operation(s) bit 14-1 Unimplemented: Read as ‘0’ bit 0 PRSSEL: Channel Priority Scheme Selection bit 1 = Round-robin scheme 0 = Fixed priority scheme  2010-2014 Microchip Technology Inc. DS30009996G-page 79

PIC24FJ128GA310 FAMILY REGISTER 5-2: DMACHx: DMA CHANNEL x CONTROL REGISTER U-0 U-0 U-0 r-0 U-0 R/W-0 R/W-0 R/W-0 — — — r — NULLW RELOAD(1) CHREQ(3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SAMODE1 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 SIZE CHEN bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 Reserved: Maintain as ‘0’ bit 11 Unimplemented: Read as ‘0’ bit 10 NULLW: Null Write Mode bit 1 = A dummy write is initiated to DMASRCx for every write to DMADSTx 0 = No dummy write is initiated bit 9 RELOAD: Address and Count Reload bit(1) 1 = DMASRCx, DMADSTx and DMACNTx registers are reloaded to their previous values upon the start of the next operation 0 = DMASRCx, DMADSTx and DMACNTx are not reloaded on the start of the next operation(2) bit 8 CHREQ: DMA Channel Software Request bit(3) 1 = A DMA request is initiated by software; automatically cleared upon completion of a DMA transfer 0 = No DMA request is pending bit 7-6 SAMODE<1:0>: Source Address Mode Selection bits 11 = DMASRCx is used in Peripheral Indirect Addressing and remains unchanged 10 = DMASRCx is decremented based on the SIZE bit after a transfer completion 01 = DMASRCx is incremented based on the SIZE bit after a transfer completion 00 = DMASRCx remains unchanged after a transfer completion bit 5-4 DAMODE<1:0>: Destination Address Mode Selection bits 11 = DMADSTx is used in Peripheral Indirect Addressing and remains unchanged 10 = DMADSTx is decremented based on the SIZE bit after a transfer completion 01 = DMADSTx is incremented based on the SIZE bit after a transfer completion 00 = DMADSTx remains unchanged after a transfer completion bit 3-2 TRMODE<1:0>: Transfer Mode Selection bits 11 = Repeated Continuous 10 = Continuous 01 = Repeated One-Shot 00 = One-Shot bit 1 SIZE: Data Size Selection bit 1 = Byte (8-bit) 0 = Word (16-bit) bit 0 CHEN: DMA Channel Enable bit 1 = The corresponding channel is enabled 0 = The corresponding channel is disabled Note 1: Only the original DMACNTx is required to be stored to recover the original DMASRCx and DMADSTx. 2: DMASRCx, DMADSTx and DMACNTx are always reloaded in Repeated mode transfers (DMACHx<2> = 1), regardless of the state of the RELOAD bit. 3: The number of transfers executed while CHREQ is set depends on the configuration of TRMODE<1:0>. DS30009996G-page 80  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 5-3: DMAINTx: DMA CHANNEL x INTERRUPT REGISTER R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DBUFWF(1) — CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 HIGHIF(1,2) LOWIF(1,2) DONEIF(1) HALFIF(1) OVRUNIF(1) — — HALFEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DBUFWF: Buffered Data Write Flag bit(1) 1 = The contents of the DMA buffer have not been written to the location specified in DMADSTx or DMASRCx in Null Write mode 0 = The contents of the DMA buffer have been written to the location specified in DMADSTx or DMASRCx in Null Write mode bit 14 Unimplemented: Read as ‘0’ bit 13-8 CHSEL<5:0>: DMA Channel Trigger Selection bits See Table5-1 for a complete list. bit 7 HIGHIF: DMA High Address Limit Interrupt Flag bit(1,2) 1 = The DMA channel has attempted to access an address higher than DMAH or the upper limit of the data RAM space 0 = The DMA channel has not invoked the high address limit interrupt bit 6 LOWIF: DMA Low Address Limit Interrupt Flag bit(1,2) 1 = The DMA channel has attempted to access the DMA SFR address lower than DMAL, but above the SFR range (07FFh) 0 = The DMA channel has not invoked the low address limit interrupt bit 5 DONEIF: DMA Complete Operation Interrupt Flag bit(1) If CHEN = 1: 1 = The previous DMA session has ended with completion 0 = The current DMA session has not yet completed If CHEN = 0: 1 = The previous DMA session has ended with completion 0 = The previous DMA session has ended without completion bit 4 HALFIF: DMA 50% Watermark Level Interrupt Flag bit(1) 1 = DMACNTx has reached the halfway point to 0000h 0 = DMACNTx has not reached the halfway point bit 3 OVRUNIF: DMA Channel Overrun Flag bit(1) 1 = The DMA channel is triggered while it is still completing the operation based on the previous trigger 0 = The overrun condition has not occurred bit 2-1 Unimplemented: Read as ‘0’ bit 0 HALFEN: Halfway Completion Watermark bit 1 = Interrupts are invoked when DMACNTx has reached its halfway point and is at completion 0 = An interrupt is invoked only at the completion of the transfer Note 1: Setting these flags in software does not generate an interrupt. 2: Testing for address limit violations (DMASRCx or DMADSTx is either greater than DMAH or less than DMAL) is NOT done before the actual access.  2010-2014 Microchip Technology Inc. DS30009996G-page 81

PIC24FJ128GA310 FAMILY TABLE 5-1: DMA TRIGGER SOURCES CHSEL<5:0> Trigger (Interrupt) CHSEL<5:0> Trigger (Interrupt) 000000 (Unimplemented) 100000 UART2 Transmit 000001 JTAG 100001 UART2 Receive 000010 LCD 100010 External Interrupt 2 000011 UART4 Transmit 100011 Timer5 000100 UART4 Receive 100100 Timer4 000101 UART4 Error 100101 Output Compare 4 000110 UART3 Transmit 100110 Output Compare 3 000111 UART3 Receive 100111 DMA Channel 2 001000 UART3 Error 101000 Input Capture 7 001001 CTMU Event 101001 External Interrupt 1 001010 HLVD 101010 Interrupt-on-Change 001011 CRC Done 101011 Comparators Event 001100 UART2 Error 101100 I2C1 Master Event 001101 UART1 Error 101101 I2C1 Slave Event 001110 RTCC 101110 DMA Channel 1 001111 DMA Channel 5 101111 A/D Converter 010000 External Interrupt 4 110000 UART1 Transmit 010001 External Interrupt 3 110001 UART1 Receive 010010 I2C2 Master Event 110010 SPI1 Event 010011 I2C2 Slave Event 110011 SPI1 Error 010100 DMA Channel 4 110100 Timer3 010101 EPMP 110101 Timer2 010110 Output Compare 7 110110 Output Compare 2 010111 Output Compare 6 110111 Input Capture 2 011000 Output Compare 5 111000 DMA Channel 0 011001 Input Capture 6 111001 Timer1 011010 Input Capture 5 111010 Output Compare 1 011011 Input Capture 4 111011 Input Capture 1 011100 Input Capture 3 111100 External Interrupt 0 011101 DMA Channel 3 111101 (Unimplemented) 011110 SPI2 Event 111110 (Unimplemented) 011111 SPI2 Error 111111 (Unimplemented) DS30009996G-page 82  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 6.0 FLASH PROGRAM MEMORY microcontroller just before shipping the product. This also allows the most recent firmware or a custom Note: This data sheet summarizes the features of firmware to be programmed. this group of PIC24F devices. It is not RTSP is accomplished using TBLRD (Table Read) and intended to be a comprehensive reference TBLWT (Table Write) instructions. With RTSP, the user source. For more information, refer to may write program memory data in blocks of 64 instruc- “Program Memory” (DS39715) in the tions (192 bytes) at a time and erase program memory “dsPIC33/PIC24 Family Reference Man- in blocks of 512 instructions (1536 bytes) at a time. ual”. The information in this data sheet supersedes the information in the FRM. 6.1 Table Instructions and Flash The PIC24FJ128GA310 family of devices contains Programming internal Flash program memory for storing and execut- Regardless of the method used, all programming of ing application code. The program memory is readable, Flash memory is done with the Table Read and Table writable and erasable. The Flash can be programmed Write instructions. These allow direct read and write in four ways: access to the program memory space from the data • In-Circuit Serial Programming™ (ICSP™) memory while the device is in normal operating mode. • Run-Time Self-Programming (RTSP) The 24-bit target address in the program memory is • JTAG formed using the TBLPAG<7:0> bits and the Effective • Enhanced In-Circuit Serial Programming Address (EA) from a W register, specified in the table (Enhanced ICSP) instruction, as shown in Figure6-1. ICSP allows a PIC24FJ128GA310 family device to be The TBLRDL and the TBLWTL instructions are used to serially programmed while in the end application circuit. read or write to bits<15:0> of program memory. This is simply done with two lines for the programming TBLRDL and TBLWTL can access program memory in clock and programming data (named PGECx and both Word and Byte modes. PGEDx, respectively), and three other lines for power The TBLRDH and TBLWTH instructions are used to read (VDD), ground (VSS) and Master Clear (MCLR). This or write to bits<23:16> of program memory. TBLRDH allows customers to manufacture boards with and TBLWTH can also access program memory in Word unprogrammed devices and then program the or Byte mode. FIGURE 6-1: ADDRESSING FOR TABLE REGISTERS 24 Bits Using Program 0 Program Counter 0 Counter Working Reg EA Using 1/0 TBLPAG Reg Table Instruction 8 Bits 16 Bits User/Configuration Byte Space Select 24-Bit EA Select  2010-2014 Microchip Technology Inc. DS30009996G-page 83

PIC24FJ128GA310 FAMILY 6.2 RTSP Operation 6.3 JTAG Operation The PIC24F Flash program memory array is organized The PIC24F family supports JTAG boundary scan. into rows of 64 instructions or 192 bytes. RTSP allows Boundary scan can improve the manufacturing the user to erase blocks of eight rows (512 instructions) process by verifying pin to PCB connectivity. at a time and to program one row at a time. It is also possible to program single words. 6.4 Enhanced In-Circuit Serial The 8-row erase blocks and single row write blocks are Programming edge-aligned, from the beginning of program memory, on Enhanced In-Circuit Serial Programming uses an boundaries of 1536 bytes and 192 bytes, respectively. on-board bootloader, known as the Program Executive When data is written to program memory using TBLWT (PE), to manage the programming process. Using an instructions, the data is not written directly to memory. SPI data frame format, the Program Executive can Instead, data written using Table Writes is stored in erase, program and verify program memory. For more holding latches until the programming sequence is information on Enhanced ICSP, see the device executed. programming specification. Any number of TBLWT instructions can be executed and a write will be successfully performed. However, 6.5 Control Registers 64TBLWT instructions are required to write the full row There are two SFRs used to read and write the of memory. program Flash memory: NVMCON and NVMKEY. To ensure that no data is corrupted during a write, any The NVMCON register (Register6-1) controls which unused address should be programmed with blocks are to be erased, which memory type is to be FFFFFFh. This is because the holding latches reset to programmed and when the programming cycle starts. an unknown state, so if the addresses are left in the Reset state, they may overwrite the locations on rows NVMKEY is a write-only register that is used for write which were not rewritten. protection. To start a programming or erase sequence, the user must consecutively write 55h and AAh to the The basic sequence for RTSP programming is to set up NVMKEY register. Refer to Section6.6 “Programming a Table Pointer, then do a series of TBLWT instructions Operations” for further details. to load the buffers. Programming is performed by setting the control bits in the NVMCON register. 6.6 Programming Operations Data can be loaded in any order and the holding regis- ters can be written to multiple times before performing A complete programming sequence is necessary for a write operation. Subsequent writes, however, will programming or erasing the internal Flash in RTSP wipe out any previous writes. mode. During a programming or erase operation, the processor stalls (Waits) until the operation is finished. Note: Writing to a location multiple times without Setting the WR bit (NVMCON<15>) starts the opera- erasing is not recommended. tion and the WR bit is automatically cleared when the All of the Table Write operations are single-word writes operation is finished. (2 instruction cycles), because only the buffers are writ- ten. A programming cycle is required for programming each row. DS30009996G-page 84  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 6-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/S-0, HC(1) R/W-0(1) R-0, HSC(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 bit 8 U-0 R/W-0(1) U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) — ERASE — — NVMOP3(2) NVMOP2(2) NVMOP1(2) NVMOP0(2) bit 7 bit 0 Legend: S = Settable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown HSC = Hardware Settable/Clearable bit bit 15 WR: Write Control bit(1) 1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is cleared by hardware once the operation is complete 0 = Program or erase operation is complete and inactive bit 14 WREN: Write Enable bit(1) 1 = Enables Flash program/erase operations 0 = Inhibits Flash program/erase operations bit 13 WRERR: Write Sequence Error Flag bit(1) 1 = An improper program or erase sequence attempt, or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally bit 12-7 Unimplemented: Read as ‘0’ bit 6 ERASE: Erase/Program Enable bit(1) 1 = Performs the erase operation specified by NVMOP<3:0> on the next WR command 0 = Performs the program operation specified by NVMOP<3:0> on the next WR command bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 NVMOP<3:0>: NVM Operation Select bits(1,2) 1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)(3) 0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1) 0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0) 0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1) Note 1: These bits can only be reset on a Power-on Reset. 2: All other combinations of NVMOP<3:0> are unimplemented. 3: Available in ICSP™ mode only; refer to the device programming specification.  2010-2014 Microchip Technology Inc. DS30009996G-page 85

PIC24FJ128GA310 FAMILY 6.6.1 PROGRAMMING ALGORITHM FOR 4. Write the first 64 instructions from data RAM into FLASH PROGRAM MEMORY the program memory buffers (see Example6-3). 5. Write the program block to Flash memory: The user can program one row of Flash program memory at a time. To do this, it is necessary to erase the 8-row a) Set the NVMOPx bits to ‘0001’ to configure erase block containing the desired row. The general for row programming. Clear the ERASE bit process is: and set the WREN bit. b) Write 55h to NVMKEY. 1. Read eight rows of program memory (512instructions) and store in data RAM. c) Write AAh to NVMKEY. 2. Update the program data in RAM with the d) Set the WR bit. The programming cycle desired new data. begins and the CPU stalls for the duration of the write cycle. When the write to Flash 3. Erase the block (see Example6-1): memory is done, the WR bit is cleared a) Set the NVMOPx bits (NVMCON<3:0>) to automatically. ‘0010’ to configure for block erase. Set the 6. Repeat Steps 4 and 5, using the next available ERASE (NVMCON<6>) and WREN 64instructions from the block in data RAM by (NVMCON<14>) bits. incrementing the value in TBLPAG, until all b) Write the starting address of the block to be 512instructions are written back to Flash erased into the TBLPAG and W registers. memory. c) Write 55h to NVMKEY. For protection against accidental operations, the write d) Write AAh to NVMKEY. initiate sequence for NVMKEY must be used to allow e) Set the WR bit (NVMCON<15>). The erase any erase or program operation to proceed. After the cycle begins and the CPU stalls for the dura- programming command has been executed, the user tion of the erase cycle. When the erase is must wait for the programming time until programming done, the WR bit is cleared automatically. is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example6-4. EXAMPLE 6-1: ERASING A PROGRAM MEMORY BLOCK (ASSEMBLY LANGUAGE CODE) ; Set up NVMCON for block erase operation MOV #0x4042, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ; Initialize Program Memory (PM) Page Boundary SFR MOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA<15:0> pointer TBLWTL W0, [W0] ; Set base address of erase block DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV.B #0x55, W0 MOV W0, NVMKEY ; Write the 0x55 key MOV.B #0xAA, W1 ; MOV W1, NVMKEY ; Write the 0xAA key BSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted DS30009996G-page 86  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY EXAMPLE 6-2: ERASING A PROGRAM MEMORY BLOCK (‘C’ LANGUAGE CODE) // C example using MPLAB C30 unsigned long progAddr = 0xXXXXXX; // Address of row to write unsigned int offset; //Set up pointer to the first memory location to be written TBLPAG = progAddr>>16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address __builtin_tblwtl(offset, 0x0000); // Set base address of erase block // with dummy latch write NVMCON = 0x4042; // Initialize NVMCON asm("DISI #5"); // Block all interrupts with priority <7 // for next 5 instructions __builtin_write_NVM(); // check function to perform unlock // sequence and set WR EXAMPLE 6-3: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 1st_program_word MOV #LOW_WORD_1, W2 ; MOV #HIGH_BYTE_1, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 2nd_program_word MOV #LOW_WORD_2, W2 ; MOV #HIGH_BYTE_2, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch • • • ; 63rd_program_word MOV #LOW_WORD_63, W2 ; MOV #HIGH_BYTE_63, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0] ; Write PM high byte into program latch EXAMPLE 6-4: INITIATING A PROGRAMMING SEQUENCE DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV.B #0x55, W0 MOV W0, NVMKEY ; Write the 0x55 key MOV.B #0xAA, W1 ; MOV W1, NVMKEY ; Write the 0xAA key BSET NVMCON, #WR ; Start the programming sequence NOP ; Required delays NOP BTSC NVMCON, #15 ; and wait for it to be BRA $-2 ; completed  2010-2014 Microchip Technology Inc. DS30009996G-page 87

PIC24FJ128GA310 FAMILY 6.6.2 PROGRAMMING A SINGLE WORD write latches and specify the lower 16 bits of the pro- OF FLASH PROGRAM MEMORY gram memory address to write to. To configure the NVMCON register for a word write, set the NVMOPx If a Flash location has been erased, it can be pro- bits (NVMCON<3:0>) to ‘0011’. The write is performed grammed using Table Write instructions to write an by executing the unlock sequence and setting the WR instruction word (24-bit) into the write latch. The bit (see Example6-5). An equivalent procedure in ‘C’ TBLPAG register is loaded with the 8 Most Significant compiler, using the MPLAB® C30 compiler and built-in Bytes (MSBs) of the Flash address. The TBLWTL and hardware functions, is shown in Example6-6. TBLWTH instructions write the desired data into the EXAMPLE 6-5: PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY ; Setup a pointer to data Program Memory MOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ;Initialize PM Page Boundary SFR MOV #tbloffset(PROG_ADDR), W0 ;Initialize a register with program memory address MOV #LOW_WORD_N, W2 ; MOV #HIGH_BYTE_N, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; Setup NVMCON for programming one word to data Program Memory MOV #0x4003, W0 ; MOV W0, NVMCON ; Set NVMOP bits to 0011 DISI #5 ; Disable interrupts while the KEY sequence is written MOV.B #0x55, W0 ; Write the key sequence MOV W0, NVMKEY MOV.B #0xAA, W0 MOV W0, NVMKEY BSET NVMCON, #WR ; Start the write cycle NOP ; Required delays NOP EXAMPLE 6-6: PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY (‘C’ LANGUAGE CODE) // C example using MPLAB C30 unsigned int offset; unsigned long progAddr = 0xXXXXXX; // Address of word to program unsigned int progDataL = 0xXXXX; // Data to program lower word unsigned char progDataH = 0xXX; // Data to program upper byte //Set up NVMCON for word programming NVMCON = 0x4003; // Initialize NVMCON //Set up pointer to the first memory location to be written TBLPAG = progAddr>>16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address //Perform TBLWT instructions to write latches __builtin_tblwtl(offset, progDataL); // Write to address low word __builtin_tblwth(offset, progDataH); // Write to upper byte asm(“DISI #5”); // Block interrupts with priority <7 // for next 5 instructions __builtin_write_NVM(); // C30 function to perform unlock // sequence and set WR DS30009996G-page 88  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 7.0 RESETS Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU Note: This data sheet summarizes the features of and peripherals are forced to a known Reset state. this group of PIC24F devices. It is not Most registers are unaffected by a Reset; their status is intended to be a comprehensive reference unknown on POR and unchanged by all other Resets. source. For more information, refer to Note: Refer to the specific peripheral or CPU “Reset” (DS39712) in the “dsPIC33/PIC24 section of this manual for register Reset Family Reference Manual”, . The informa- states. tion in this data sheet supersedes the information in the FRM. All types of device Reset will set a corresponding status The Reset module combines all Reset sources and bit in the RCON register to indicate the type of Reset controls the device Master Reset Signal, SYSRST. The (see Register7-1). In addition, Reset events occurring following is a list of device Reset sources: while an extreme power-saving feature is in use (such as VBAT) will set one or more status bits in the RCON2 • POR: Power-on Reset register (Register7-2). A POR will clear all bits, except • MCLR: Pin Reset for the BOR and POR (RCON<1:0>) bits, which are • SWR: RESET Instruction set. The user may set or clear any bit at any time during • WDT: Watchdog Timer Reset code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software will • BOR: Brown-out Reset not cause a device Reset to occur. • CM: Configuration Mismatch Reset The RCON register also has other bits associated with • TRAPR: Trap Conflict Reset the Watchdog Timer and device power-saving states. • IOPUWR: Illegal Opcode Reset The function of these bits is discussed in other sections • UWR: Uninitialized W Register Reset of this data sheet. A simplified block diagram of the Reset module is Note: The status bits in the RCON registers shown in Figure7-1. should be cleared after they are read so that the next RCON register values after a device Reset will be meaningful. FIGURE 7-1: RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle VDD Rise POR Detect SYSRST VDD Brown-out BOR Reset Enable Voltage Regulator Trap Conflict Illegal Opcode Configuration Mismatch Uninitialized W Register  2010-2014 Microchip Technology Inc. DS30009996G-page 89

PIC24FJ128GA310 FAMILY REGISTER 7-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 TRAPR(1) IOPUWR(1) — RETEN(2) — DPSLP(1) CM(1) VREGS(3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 EXTR(1) SWR(1) SWDTEN(4) WDTO(1) SLEEP(1) IDLE(1) BOR(1) POR(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit(1) 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit(1) 1 = An illegal opcode detection, an illegal address mode or Uninitialized W register is used as an Address Pointer and caused a Reset 0 = An illegal opcode or Uninitialized W Reset has not occurred bit 13 Unimplemented: Read as ‘0’ bit 12 RETEN: Retention Mode Enable bit(2) 1 = Retention mode is enabled while device is in Sleep modes (1.2V regulator supplies to the core) 0 = Retention mode is disabled; normal voltage levels are present bit 11 Unimplemented: Read as ‘0’ bit 10 DPSLP: Deep Sleep Flag bit(1) 1 = Device has been in Deep Sleep mode 0 = Device has not been in Deep Sleep mode bit 9 CM: Configuration Word Mismatch Reset Flag bit(1) 1 = A Configuration Word Mismatch Reset has occurred 0 = A Configuration Word Mismatch Reset has not occurred bit 8 VREGS: Program Memory Power During Sleep bit(3) 1 = Program memory bias voltage remains powered during Sleep 0 = Program memory bias voltage is powered down during Sleep bit 7 EXTR: External Reset (MCLR) Pin bit(1) 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred bit 6 SWR: Software Reset (Instruction) Flag bit(1) 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the LPCFG Configuration bit is 1’ (unprogrammed), the retention regulator is disabled and the RETEN bit has no effect. 3: Re-enabling the regulator after it enters Standby mode will add a delay, TVREG, when waking up from Sleep. Applications that do not use the voltage regulator should set this bit to prevent this delay from occurring. 4: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS30009996G-page 90  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 7-1: RCON: RESET CONTROL REGISTER (CONTINUED) bit 5 SWDTEN: Software Enable/Disable of WDT bit(4) 1 = WDT is enabled 0 = WDT is disabled bit 4 WDTO: Watchdog Timer Time-out Flag bit(1) 1 = WDT time-out has occurred 0 = WDT time-out has not occurred bit 3 SLEEP: Wake from Sleep Flag bit(1) 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode bit 2 IDLE: Wake-up from Idle Flag bit(1) 1 = Device has been in Idle mode 0 = Device has not been in Idle mode bit 1 BOR: Brown-out Reset Flag bit(1) 1 = A Brown-out Reset has occurred (also set after a Power-on Reset). 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit(1) 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the LPCFG Configuration bit is 1’ (unprogrammed), the retention regulator is disabled and the RETEN bit has no effect. 3: Re-enabling the regulator after it enters Standby mode will add a delay, TVREG, when waking up from Sleep. Applications that do not use the voltage regulator should set this bit to prevent this delay from occurring. 4: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting.  2010-2014 Microchip Technology Inc. DS30009996G-page 91

PIC24FJ128GA310 FAMILY REGISTER 7-2: RCON2: RESET AND SYSTEM CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 r-0 R/CO-1 R/CO-1 R/CO-1 R/CO-0 — — — r VDDBOR(1) VDDPOR(1,2) VBPOR(1,3) VBAT(1) bit 7 bit 0 Legend: CO = Clearable Only bit r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4 Reserved: Maintain as ‘0’ bit 3 VDDBOR: VDD Brown-out Reset Flag bit(1) 1 = A VDD Brown-out Reset has occurred (set by hardware) 0 = A VDD Brown-out Reset has not occurred bit 2 VDDPOR: VDD Power-On Reset Flag bit(1,2) 1 = A VDD Power-up Reset has occurred (set by hardware) 0 = A VDD Power-up Reset has not occurred bit 1 VBPOR: VBPOR Flag bit(1,3) 1 = A VBAT POR has occurred (no battery connected to VBAT pin, or VBAT power below Deep Sleep Semaphore retention level, set by hardware) 0 = A VBAT POR has not occurred bit 0 VBAT: VBAT Flag bit(1) 1 = A POR exit has occurred while power was applied to VBAT pin (set by hardware) 0 = A POR exit from VBAT has not occurred Note 1: This bit is set in hardware only; it can only be cleared in software. 2: Indicates a VDD POR. Setting the POR bit (RCON<0>) indicates a VCORE POR. 3: This bit is set when the device is originally powered up, even if power is present on VBAT. DS30009996G-page 92  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 7-1: RESET FLAG BIT OPERATION Flag Bit Setting Event Clearing Event TRAPR (RCON<15>) Trap Conflict Event POR IOPUWR (RCON<14>) Illegal Opcode or Uninitialized W Register Access POR CM (RCON<9>) Configuration Mismatch Reset POR EXTR (RCON<7>) MCLR Reset POR SWR (RCON<6>) RESET Instruction POR WDTO (RCON<4>) WDT Time-out CLRWDT, PWRSAV Instruction, POR SLEEP (RCON<3>) PWRSAV #0 Instruction POR DPSLP (RCON<10>) PWRSAV #0 Instruction while DSEN bit is Set POR IDLE (RCON<2>) PWRSAV #1 Instruction POR BOR (RCON<1>) POR, BOR — POR (RCON<0>) POR — Note: All Reset flag bits may be set or cleared by the user software. 7.1 Special Function Register Reset 7.3 Brown-out Reset (BOR) States PIC24FJ128GA310 family devices implement a BOR Most of the Special Function Registers (SFRs) associ- circuit that provides the user with several configuration ated with the PIC24F CPU and peripherals are reset to a and power-saving options. The BOR is controlled by particular value at a device Reset. The SFRs are the BOREN (CW3<12>) Configuration bit. grouped by their peripheral or CPU function and their When BOR is enabled, any drop of VDD below the BOR Reset values are specified in each section of this manual. threshold results in a device BOR. Threshold levels are The Reset value for each SFR does not depend on the described in Section32.1 “DC Characteristics” type of Reset, with the exception of four registers. The (Parameter DC17). Reset value for the Reset Control register, RCON, will depend on the type of device Reset. The Reset value 7.4 Clock Source Selection at Reset for the Oscillator Control register, OSCCON, will If clock switching is enabled, the system clock source depend on the type of Reset and the programmed at device Reset is chosen, as shown in Table7-2. If values of the FNOSC<2:0> bits in Flash Configuration clock switching is disabled, the system clock source is Word2 (CW2) (see Table7-2). The RCFGCAL and always selected according to the Oscillator Configura- NVMCON registers are only affected by a POR. tion bits. Refer to “Oscillator” (DS39700) in the “dsPIC33/PIC24 Family Reference Manual” for further 7.2 Device Reset Times details. The Reset times for various types of device Reset are summarized in Table7-3. Note that the system Reset TABLE 7-2: OSCILLATOR SELECTION vs. signal, SYSRST, is released after the POR delay time TYPE OF RESET (CLOCK expires. SWITCHING ENABLED) The time at which the device actually begins to execute Reset Type Clock Source Determinant code will also depend on the system oscillator delays, which include the Oscillator Start-up Timer (OST) and POR FNOSC<2:0> Configuration bits the PLL lock time. The OST and PLL lock times occur BOR (CW2<10:8>) in parallel with the applicable SYSRST delay times. MCLR The Fail-Safe Clock Monitor (FSCM) delay determines COSC2:0> Control bits WDTO the time at which the FSCM begins to monitor the (OSCCON<14:12>) SWR system clock source after the SYSRST signal is released.  2010-2014 Microchip Technology Inc. DS30009996G-page 93

PIC24FJ128GA310 FAMILY TABLE 7-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS System Clock Reset Type Clock Source SYSRST Delay Notes Delay POR EC TPOR + TSTARTUP + TRST — 1, 2, 3 ECPLL TPOR + TSTARTUP + TRST TLOCK 1, 2, 3, 5 XT, HS, SOSC TPOR + TSTARTUP + TRST TOST 1, 2, 3, 4, 8 XTPLL, HSPLL TPOR + TSTARTUP + TRST TOST + TLOCK 1, 2, 3, 4, 5, 8 FRC, FRCDIV TPOR + TSTARTUP + TRST TFRC 1, 2, 3, 6, 7 FRCPLL TPOR + TSTARTUP + TRST TFRC + TLOCK 1, 2, 3, 5, 6 LPRC TPOR + TSTARTUP + TRST TLPRC 1, 2, 3, 6 BOR EC TSTARTUP + TRST — 2, 3 ECPLL TSTARTUP + TRST TLOCK 2, 3, 5 XT, HS, SOSC TSTARTUP + TRST TOST 2, 3, 4, 8 XTPLL, HSPLL TSTARTUP + TRST TOST + TLOCK 2, 3, 4, 5, 8 FRC, FRCDIV TSTARTUP + TRST TFRC 2, 3, 6, 7 FRCPLL TSTARTUP + TRST TFRC + TLOCK 2, 3, 5, 6 LPRC TSTARTUP + TRST TLPRC 2, 3, 6 MCLR Any Clock TRST — 3 WDT Any Clock TRST — 3 Software Any clock TRST — 3 Illegal Opcode Any Clock TRST — 3 Uninitialized W Any Clock TRST — 3 Trap Conflict Any Clock TRST — 3 Note 1: TPOR = Power-on Reset delay (10 s nominal). 2: TSTARTUP = TVREG (10 s nominal when VREGS = 1 and when VREGS = 0; depends upon WDTWIN<1:0> bits setting). 3: TRST = Internal State Reset time (2s nominal). 4: TOST = Oscillator Start-up Timer (OST). A 10-bit counter counts 1024 oscillator periods before releasing the oscillator clock to the system. 5: TLOCK = PLL lock time. 6: TFRC and TLPRC = RC oscillator start-up times. 7: If Two-speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC so the system clock delay is just TFRC, and in such cases, FRC start-up time is valid. It switches to the primary oscillator after its respective clock delay. 8: TOST = Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing the oscillator clock to the system. 7.4.1 POR AND LONG OSCILLATOR The device will not begin to execute code until a valid START-UP TIMES clock source has been released to the system. There- fore, the oscillator and PLL start-up delays must be The oscillator start-up circuitry and its associated delay considered when the Reset delay time must be known. timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially 7.4.2 FAIL-SAFE CLOCK MONITOR low-frequency crystals) will have a relatively long (FSCM) AND DEVICE RESETS start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: If the FSCM is enabled, it will begin to monitor the system clock source when SYSRST is released. If a • The oscillator circuit has not begun to oscillate. valid clock source is not available at this time, the • The Oscillator Start-up Timer has not expired (if a device will automatically switch to the FRC oscillator crystal oscillator is used). and the user can switch to the desired crystal oscillator • The PLL has not achieved a lock (if PLL is used). in the Trap Service Routine (TSR). DS30009996G-page 94  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 8.0 INTERRUPT CONTROLLER 8.1.1 ALTERNATE INTERRUPT VECTOR TABLE Note: This data sheet summarizes the features The Alternate Interrupt Vector Table (AIVT) is located of this group of PIC24F devices. It is not after the IVT, as shown in Figure8-1. The ALTIVT intended to be a comprehensive refer- (INTCON2<15>) control bit provides access to the ence source. For more information, refer AIVT. If the ALTIVT bit is set, all interrupt and exception to “Interrupts” (DS39707) in the processes will use the alternate vectors instead of the “dsPIC33/PIC24 Family Reference Man- default vectors. The alternate vectors are organized in ual”. The information in this data sheet the same manner as the default vectors. supersedes the information in the FRM. The AIVT supports emulation and debugging efforts by The PIC24F interrupt controller reduces the numerous providing a means to switch between an application peripheral interrupt request signals to a single interrupt and a support environment without requiring the inter- request signal to the PIC24F CPU. It has the following rupt vectors to be reprogrammed. This feature also features: enables switching between applications for evaluation • Up to 8 processor exceptions and software traps of different software algorithms at run time. If the AIVT is not needed, the AIVT should be programmed with • Seven user-selectable priority levels the same addresses used in the IVT. • Interrupt Vector Table (IVT) with up to 118 vectors • Unique vector for each interrupt or exception 8.2 Reset Sequence source • Fixed priority within a specified user priority level A device Reset is not a true exception because the • Alternate Interrupt Vector Table (AIVT) for debug interrupt controller is not involved in the Reset process. support The PIC24F devices clear their registers in response to a Reset, which forces the PC to zero. The micro- • Fixed interrupt entry and return latencies controller then begins program execution at location, 000000h. The user programs a GOTO instruction at the 8.1 Interrupt Vector Table Reset address, which redirects program execution to The Interrupt Vector Table (IVT) is shown in Figure8-1. the appropriate start-up routine. The IVT resides in program memory, starting at location, Note: Any unimplemented or unused vector 000004h. The IVT contains 126 vectors, consisting of locations in the IVT and AIVT should be 8non-maskable trap vectors, plus up to 118 sources of programmed with the address of a default interrupt. In general, each interrupt source has its own interrupt handler routine that contains a vector. Each interrupt vector contains a 24-bit wide RESET instruction. address. The value programmed into each interrupt vec- tor location is the starting address of the associated Interrupt Service Routine (ISR). Interrupt vectors are prioritized in terms of their natural priority; this is linked to their position in the vector table. All other things being equal, lower addresses have a higher natural priority. For example, the interrupt asso- ciated with Vector 0 will take priority over interrupts at any other vector address. PIC24FJ128GA310 family devices implement non-maskable traps and unique interrupts. These are summarized in Table8-1 and Table8-2.  2010-2014 Microchip Technology Inc. DS30009996G-page 95

PIC24FJ128GA310 FAMILY FIGURE 8-1: PIC24F INTERRUPT VECTOR TABLE Reset – GOTO Instruction 000000h Reset – GOTO Address 000002h Reserved 000004h Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 000014h Interrupt Vector 1 — — — Interrupt Vector 52 00007Ch y orit Interrupt Vector 53 00007Eh Interrupt Vector Table (IVT)(1) Pri Interrupt Vector 54 000080h er — d — Or — ural Interrupt Vector 116 0000FCh at Interrupt Vector 117 0000FEh N g Reserved 000100h n Reserved 000102h si a Reserved e cr Oscillator Fail Trap Vector e D Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 000114h Interrupt Vector 1 — — — Interrupt Vector 52 00017Ch Interrupt Vector 53 00017Eh Alternate Interrupt Vector Table (AIVT)(1) Interrupt Vector 54 000180h — — — Interrupt Vector 116 Interrupt Vector 117 0001FEh Start of Code 000200h Note 1: See Table8-2 for the interrupt vector list. TABLE 8-1: TRAP VECTOR DETAILS Vector Number IVT Address AIVT Address Trap Source 0 000004h 000104h Reserved 1 000006h 000106h Oscillator Failure 2 000008h 000108h Address Error 3 00000Ah 00010Ah Stack Error 4 00000Ch 00010Ch Math Error 5 00000Eh 00010Eh Reserved 6 000010h 000110h Reserved 7 000012h 000112h Reserved DS30009996G-page 96  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 8-2: IMPLEMENTED INTERRUPT VECTORS Interrupt Bit Locations Vector IVT AIVT Interrupt Source Number Address Address Flag Enable Priority ADC1 Conversion Done 13 00002Eh 00012Eh IFS0<13> IEC0<13> IPC3<6:4> Comparator Event 18 000038h 000138h IFS1<2> IEC1<2> IPC4<10:8> CRC Generator 67 00009Ah 00019Ah IFS4<3> IEC4<3> IPC16<14:12> CTMU Event 77 0000AEh 0001AEh IFS4<13> IEC4<13> IPC19<6:4> DMA Channel 0 4 00001Ch 00011Ch IFS0<4> IEC0<4> IPC1<2:0> DMA Channel 1 14 000030h 000130h IFS0<14> IEC0<14> IPC3<10:8> DMA Channel 2 24 000044h 000144h IFS1<8> IEC1<8> IPC6<2:0> DMA Channel 3 36 00005Ch 00015Ch IFS2<4> IEC2<4> IPC9<2:0> DMA Channel 4 46 000070h 000170h IFS2<14> IEC2<14> IPC11<10:8> DMA Channel 5 61 00008Eh 00018Eh IFS3<13> IEC3<13> IPC15<6:4> External Interrupt 0 0 000014h 000114h IFS0<0> IEC0<0> IPC0<2:0> External Interrupt 1 20 00003Ch 00013Ch IFS1<4> IEC1<4> IPC5<2:0> External Interrupt 2 29 00004Eh 00014Eh IFS1<13> IEC1<13> IPC7<6:4> External Interrupt 3 53 00007Eh 00017Eh IFS3<5> IEC3<5> IPC13<6:4> External Interrupt 4 54 000080h 000180h IFS3<6> IEC3<6> IPC13<10:8> I2C1 Master Event 17 000036h 000136h IFS1<1> IEC1<1> IPC4<6:4> I2C1 Slave Event 16 000034h 000134h IFS1<0> IEC1<0> IPC4<2:0> I2C2 Master Event 50 000078h 000178h IFS3<2> IEC3<2> IPC12<10:8> I2C2 Slave Event 49 000076h 000176h IFS3<1> IEC3<1> IPC12<6:4> Input Capture 1 1 000016h 000116h IFS0<1> IEC0<1> IPC0<6:4> Input Capture 2 5 00001Eh 00011Eh IFS0<5> IEC0<5> IPC1<6:4> Input Capture 3 37 00005Eh 00015Eh IFS2<5> IEC2<5> IPC9<6:4> Input Capture 4 38 000060h 000160h IFS2<6> IEC2<6> IPC9<10:8> Input Capture 5 39 000062h 000162h IFS2<7> IEC2<7> IPC9<14:12> Input Capture 6 40 000064h 000164h IFS2<8> IEC2<8> IPC10<2:0> Input Capture 7 22 000040h 000140h IFS1<6> IEC1<6> IPC5<10:8> JTAG 117 0000FEh 0001FEh IFS7<5> IEC7<5> IPC29<6:4> Input Change Notification (ICN) 19 00003Ah 00013Ah IFS1<3> IEC1<3> IPC4<14:12> LCD Controller 100 0000DCh 0001DCh IFS6<4> IEC6<4> IPC25<2:0> High/Low-Voltage Detect (HLVD) 72 0000A4h 0001A4h IFS4<8> IEC4<8> IPC18<2:0> Output Compare 1 2 000018h 000118h IFS0<2> IEC0<2> IPC0<10:8> Output Compare 2 6 000020h 000120h IFS0<6> IEC0<6> IPC1<10:8> Output Compare 3 25 000046h 000146h IFS1<9> IEC1<9> IPC6<6:4> Output Compare 4 26 000048h 000148h IFS1<10> IEC1<10> IPC6<10:8> Output Compare 5 41 000066h 000166h IFS2<9> IEC2<9> IPC10<6:4> Output Compare 6 42 000068h 000168h IFS2<10> IEC2<10> IPC10<10:8> Output Compare 7 43 00006Ah 00016Ah IFS2<11> IEC2<11> IPC10<14:12> Enhanced Parallel Master Port (EPMP) 45 00006Eh 00016Eh IFS2<13> IEC2<13> IPC11<6:4> Real-Time Clock and Calendar (RTCC) 62 000090h 000190h IFS3<14> IEC3<14> IPC15<10:8> SPI1 Error 9 000026h 000126h IFS0<9> IEC0<9> IPC2<6:4> SPI1 Event 10 000028h 000128h IFS0<10> IEC0<10> IPC2<10:8> SPI2 Error 32 000054h 000154h IFS2<0> IEC2<0> IPC8<2:0> SPI2 Event 33 000056h 000156h IFS2<1> IEC2<1> IPC8<6:4>  2010-2014 Microchip Technology Inc. DS30009996G-page 97

PIC24FJ128GA310 FAMILY TABLE 8-2: IMPLEMENTED INTERRUPT VECTORS (CONTINUED) Interrupt Bit Locations Vector IVT AIVT Interrupt Source Number Address Address Flag Enable Priority Timer1 3 00001Ah 00011Ah IFS0<3> IEC0<3> IPC0<14:12> Timer2 7 000022h 000122h IFS0<7> IEC0<7> IPC1<14:12> Timer3 8 000024h 000124h IFS0<8> IEC0<8> IPC2<2:0> Timer4 27 00004Ah 00014Ah IFS1<11> IEC1<11> IPC6<14:12> Timer5 28 00004Ch 00014Ch IFS1<12> IEC1<12> IPC7<2:0> UART1 Error 65 000096h 000196h IFS4<1> IEC4<1> IPC16<6:4> UART1 Receiver 11 00002Ah 00012Ah IFS0<11> IEC0<11> IPC2<14:12> UART1 Transmitter 12 00002Ch 00012Ch IFS0<12> IEC0<12> IPC3<2:0> UART2 Error 66 000098h 000198h IFS4<2> IEC4<2> IPC16<10:8> UART2 Receiver 30 000050h 000150h IFS1<14> IEC1<14> IPC7<10:8> UART2 Transmitter 31 000052h 000152h IFS1<15> IEC1<15> IPC7<14:12> UART3 Error 81 0000B6h 0001B6h IFS5<1> IEC5<1> IPC20<6:4> UART3 Receiver 82 0000B8h 0001B8h IFS5<2> IEC5<2> IPC20<10:8> UART3 Transmitter 83 0000BAh 0001BAh IFS5<3> IEC5<3> IPC20<14:12> UART4 Error 87 0000C2h 0001C2h IFS5<7> IEC5<7> IPC21<14:12> UART4 Receiver 88 0000C4h 0001C4h IFS5<8> IEC5<8> IPC22<2:0> UART4 Transmitter 89 0000C6h 0001C6h IFS5<9> IEC5<9> IPC22<6:4> 8.3 Interrupt Control and Status The IPCx registers are used to set the Interrupt Priority Registers Level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels. The PIC24FJ128GA310 family of devices implements The INTTREG register contains the associated a total of 43 registers for the interrupt controller: interrupt vector number and the new CPU Interrupt • INTCON1 Priority Level, which are latched into the Vector • INTCON2 Number (VECNUM<6:0>) and the Interrupt Level • IFS0 through IFS7 (ILR<3:0>) bit fields in the INTTREG register. The new Interrupt Priority Level is the priority of the • IEC0 through IEC7 pending interrupt. • IPC0 through IPC13, ICP15 and ICP16, ICP18 through ICP23, ICP25 and ICP29 The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the order of their vector numbers, • INTTREG as shown in Table8-2. For example, the INT0 (External Global interrupt control functions are controlled from Interrupt 0) is shown as having a vector number and a INTCON1 and INTCON2. INTCON1 contains the Inter- natural order priority of 0. Thus, the INT0IF status bit is rupt Nesting Disable (NSTDIS) bit, as well as the found in IFS0<0>, the INT0IE enable bit in IEC0<0> control and status flags for the processor trap sources. and the INT0IP<2:0> priority bits in the first position of The INTCON2 register controls the external interrupt IPC0 (IPC0<2:0>). request signal behavior and the use of the Alternate Although they are not specifically part of the interrupt Interrupt Vector Table (AIVT). control hardware, two of the CPU Control registers con- The IFSx registers maintain all of the interrupt request tain bits that control interrupt functionality. The ALU flags. Each source of interrupt has a status bit, which is STATUS Register (SR) contains the IPL<2:0> bits set by the respective peripherals or an external signal (SR<7:5>). These indicate the current CPU Interrupt and is cleared via software. Priority Level. The user can change the current CPU The IECx registers maintain all of the interrupt enable priority level by writing to the IPLx bits. bits. These control bits are used to individually enable interrupts from the peripherals or external signals. DS30009996G-page 98  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY The CORCON register contains the IPL3 bit, which ority Level are latched into INTTREG. This information together with the IPL<2:0> bits, indicate the current can be used to determine a specific interrupt source if CPU priority level. IPL3 is a read-only bit so that trap a generic ISR is used for multiple vectors (such as events cannot be masked by the user software. when ISR remapping is used in bootloader applica- tions) or to check if another interrupt is pending while in The interrupt controller has the Interrupt Controller Test an ISR. register, INTTREG, which displays the status of the interrupt controller. When an interrupt request occurs, All interrupt registers are described in Register8-1 it’s associated vector number and the new Interrupt Pri- through Register8-44 in the succeeding pages. REGISTER 8-1: SR: ALU STATUS REGISTER (IN CPU) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — DC(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL2(2,3) IPL1(2,3) IPL0(2,3) RA(1) N(1) OV(1) Z(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) Note 1: See Register3-1 for the description of the remaining bits (bits 8, 4, 3, 2, 1 and 0) that are not dedicated to interrupt control functions. 2: The IPLx bits are concatenated with the IPL3 (CORCON<3>) bit to form the CPU Interrupt Priority Level. The value in parentheses indicates the Interrupt Priority Level if IPL3 = 1. 3: The IPLx Status bits are read-only when NSTDIS (INTCON1<15>) = 1.  2010-2014 Microchip Technology Inc. DS30009996G-page 99

PIC24FJ128GA310 FAMILY REGISTER 8-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0 r-1 U-0 U-0 — — — — IPL3(1) r — — bit 7 bit 0 Legend: r = Reserved bit C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less bit 2 Reserved: Read as ‘1’ bit 1-0 Unimplemented: Read as ‘0’ Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level; see Register3-2 for bit description. DS30009996G-page 100  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 8-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 NSTDIS — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — — — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled bit 14-5 Unimplemented: Read as ‘0’ bit 4 MATHERR: Arithmetic Error Trap Status bit 1 = Overflow trap has occurred 0 = Overflow trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’  2010-2014 Microchip Technology Inc. DS30009996G-page 101

PIC24FJ128GA310 FAMILY REGISTER 8-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0, HSC U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use Alternate Interrupt Vector Table 0 = Use standard (default) Interrupt Vector Table bit 14 DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active bit 13-5 Unimplemented: Read as ‘0’ bit 4 INT4EP: External Interrupt 4 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 3 INT3EP: External Interrupt 3 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge DS30009996G-page 102  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 8-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0, R/W-0 R/W-0 T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 DMA1IF: DMA Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 SPF1IF: SPI1 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 DMA0IF: DMA Channel 0 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2010-2014 Microchip Technology Inc. DS30009996G-page 103

PIC24FJ128GA310 FAMILY REGISTER 8-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS30009996G-page 104  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 8-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF bit 15 bit 8 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC7IF — INT1IF CNIF CMIF MI2C1IF SI2C1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 U2TXIF: UART2 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 U2RXIF: UART2 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 T5IF: Timer5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 T4IF: Timer4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 OC4IF: Output Compare Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 OC3IF: Output Compare Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 DMA2IF: DMA Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 Unimplemented: Read as ‘0’ bit 6 IC7IF: Input Capture Channel 7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 Unimplemented: Read as ‘0’ bit 4 INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2010-2014 Microchip Technology Inc. DS30009996G-page 105

PIC24FJ128GA310 FAMILY REGISTER 8-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED) bit 2 CMIF: Comparator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS30009996G-page 106  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 8-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA4IF PMPIF — OC7IF OC6IF OC5IF IC6IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 IC5IF IC4IF IC3IF DMA3IF — — SPI2IF SPF2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 DMA4IF: DMA Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 PMPIF: Parallel Master Port Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 Unimplemented: Read as ‘0’ bit 11 OC7IF: Output Compare Channel 7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 OC6IF: Output Compare Channel 6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 OC5IF: Output Compare Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 IC6IF: Input Capture Channel 6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 IC5IF: Input Capture Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 IC4IF: Input Capture Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 IC3IF: Input Capture Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 DMA3IF: DMA Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3-2 Unimplemented: Read as ‘0’ bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2010-2014 Microchip Technology Inc. DS30009996G-page 107

PIC24FJ128GA310 FAMILY REGISTER 8-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 (CONTINUED) bit 0 SPF2IF: SPI2 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred REGISTER 8-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — RTCIF DMA5IF — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 — INT4IF INT3IF — — MI2C2IF SI2C2IF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 DMA5IF: DMA Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12-7 Unimplemented: Read as ‘0’ bit 6 INT4IF: External Interrupt 4 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 INT3IF: External Interrupt 3 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4-3 Unimplemented: Read as ‘0’ bit 2 MI2C2IF: Master I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ DS30009996G-page 108  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 8-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 — — CTMUIF — — — — HLVDIF bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 — — — — CRCIF U2ERIF U1ERIF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIF: CTMU Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12-9 Unimplemented: Read as ‘0’ bit 8 HLVDIF: High/Low-Voltage Detect Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7-4 Unimplemented: Read as ‘0’ bit 3 CRCIF: CRC Generator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 U2ERIF: UART2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U1ERIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’  2010-2014 Microchip Technology Inc. DS30009996G-page 109

PIC24FJ128GA310 FAMILY REGISTER 8-10: IFS5: INTERRUPT FLAG STATUS REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — U4TXIF U4RXIF bit 15 bit 8 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U4ERIF — — — U3TXIF U3RXIF U3ERIF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9 U4TXIF: UART4 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 U4RXIF: UART4 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 U4ERIF: UART4 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6-4 Unimplemented: Read as ‘0’ bit 3 U3TXIF: UART3 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 U3RXIF: UART3 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U3ERIF: UART3 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ DS30009996G-page 110  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 8-11: IFS6: INTERRUPT FLAG STATUS REGISTER 6 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 — — — LCDIF — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4 LCDIF: LCD Controller Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3-0 Unimplemented: Read as ‘0’ REGISTER 8-12: IFS7: INTERRUPT FLAG STATUS REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — JTAGIF — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5 JTAGIF: JTAG Controller Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4-0 Unimplemented: Read as ‘0’  2010-2014 Microchip Technology Inc. DS30009996G-page 111

PIC24FJ128GA310 FAMILY REGISTER 8-13: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 DMA1IE: DMA Channel 1 Interrupt Flag Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13 AD1IE: ADC1 Conversion Complete Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 10 SPI1IE: SPI1 Transfer Complete Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 9 SPF1IE: SPI1 Fault Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8 T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7 T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4 DMA0IE: DMA Channel 0 Interrupt Flag Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled DS30009996G-page 112  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 8-13: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled  2010-2014 Microchip Technology Inc. DS30009996G-page 113

PIC24FJ128GA310 FAMILY REGISTER 8-14: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U2TXIE U2RXIE INT2IE(1) T5IE T4IE OC4IE OC3IE DMA2IE bit 15 bit 8 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC7IE — INT1IE(1) CNIE CMIE MI2C1IE SI2C1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 14 U2RXIE: UART2 Receiver Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13 INT2IE: External Interrupt 2 Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12 T5IE: Timer5 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 11 T4IE: Timer4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 10 OC4IE: Output Compare Channel 4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 9 OC3IE: Output Compare Channel 3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8 DMA2IE: DMA Channel 2 Interrupt Flag Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7 Unimplemented: Read as ‘0’ bit 6 IC7IE: Input Capture Channel 7 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 5 Unimplemented: Read as ‘0’ bit 4 INT1IE: External Interrupt 1 Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Note 1: If an external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn pin. See Section11.4 “Peripheral Pin Select (PPS)” for more information. DS30009996G-page 114  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 8-14: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED) bit 3 CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 CMIE: Comparator Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 MI2C1IE: Master I2C1 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 SI2C1IE: Slave I2C1 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Note 1: If an external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn pin. See Section11.4 “Peripheral Pin Select (PPS)” for more information.  2010-2014 Microchip Technology Inc. DS30009996G-page 115

PIC24FJ128GA310 FAMILY REGISTER 8-15: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA4IE PMPIE — OC7IE OC6IE OC5IE IC6IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 IC5IE IC4IE IC3IE DMA3IE — — SPI2IE SPF2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 DMA4IE: DMA Channel 4 Interrupt Flag Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13 PMPIE: Parallel Master Port Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12 Unimplemented: Read as ‘0’ bit 11 OC7IE: Output Compare Channel 7 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 10 OC6IE: Output Compare Channel 6 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 9 OC5IE: Output Compare Channel 5 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8 IC6IE: Input Capture Channel 6 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7 IC5IE: Input Capture Channel 5 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 6 IC4IE: Input Capture Channel 4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 5 IC3IE: Input Capture Channel 3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4 DMA3IF: DMA Channel 3 Interrupt Flag Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 3-2 Unimplemented: Read as ‘0’ DS30009996G-page 116  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 8-15: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled REGISTER 8-16: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — RTCIE DMA5IE — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 — INT4IE(1) INT3IE(1) — — MI2C2IE SI2C2IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13 DMA5IE: DMA Channel 5 Interrupt Flag Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12-7 Unimplemented: Read as ‘0’ bit 6 INT4IE: External Interrupt 4 Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 5 INT3IE: External Interrupt 3 Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4-3 Unimplemented: Read as ‘0’ bit 2 MI2C2IE: Master I2C2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 SI2C2IE: Slave I2C2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’ Note 1: If an external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn pin. See Section11.4 “Peripheral Pin Select (PPS)” for more information.  2010-2014 Microchip Technology Inc. DS30009996G-page 117

PIC24FJ128GA310 FAMILY REGISTER 8-17: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 — — CTMUIE — — — — HLVDIE bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 — — — — CRCIE U2ERIE U1ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIE: CTMU Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12-9 Unimplemented: Read as ‘0’ bit 8 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7-4 Unimplemented: Read as ‘0’ bit 3 CRCIE: CRC Generator Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 U2ERIE: UART2 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’ DS30009996G-page 118  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 8-18: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — U4TXIE U4RXIE bit 15 bit 8 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U4ERIE — — — U3TXIE U3RXIE U3ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9 U4TXIE: UART4 Transmitter Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8 U4RXIE: UART4 Receiver Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7 U4ERIE: UART4 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 6-4 Unimplemented: Read as ‘0’ bit 3 U3TXIE: UART3 Transmitter Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 U3RXIE: UART3 Receiver Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 U3ERIE: UART3 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’  2010-2014 Microchip Technology Inc. DS30009996G-page 119

PIC24FJ128GA310 FAMILY REGISTER 8-19: IEC6: INTERRUPT ENABLE CONTROL REGISTER 6 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 — — — LCDIE — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4 LCDIE: LCD Controller Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 3-0 Unimplemented: Read as ‘0’ REGISTER 8-20: IEC7: INTERRUPT ENABLE CONTROL REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — JTAGIE — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5 JTAGIE: JTAG Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4-0 Unimplemented: Read as ‘0’ DS30009996G-page 120  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 8-21: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2010-2014 Microchip Technology Inc. DS30009996G-page 121

PIC24FJ128GA310 FAMILY REGISTER 8-22: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC2IP2 IC2IP1 IC2IP0 — DMA0IP2 DMA0IP1 DMA0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 DMA0IP<2:0>: DMA Channel 0 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS30009996G-page 122  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 8-23: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SPF1IP<2:0>: SPI1 Fault Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2010-2014 Microchip Technology Inc. DS30009996G-page 123

PIC24FJ128GA310 FAMILY REGISTER 8-24: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — DMA1IP2 DMA1IP1 DMA1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 DMA1IP<2:0>: DMA Channel 1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS30009996G-page 124  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 8-25: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Input Change Notification Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 CMIP<2:0>: Comparator Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 MI2C1IP<2:0>: Master I2C1 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SI2C1IP<2:0>: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2010-2014 Microchip Technology Inc. DS30009996G-page 125

PIC24FJ128GA310 FAMILY REGISTER 8-26: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — IC7IP2 IC7IP1 IC7IP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP2 INT1IP1 INT1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 IC7IP<2:0>: Input Capture Channel 7 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS30009996G-page 126  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 8-27: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC3IP2 OC3IP1 OC3IP0 — DMA2IP2 DMA2IP1 DMA2IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP<2:0>: Timer4 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 DMA2IP<2:0>: DMA Channel 2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2010-2014 Microchip Technology Inc. DS30009996G-page 127

PIC24FJ128GA310 FAMILY REGISTER 8-28: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS30009996G-page 128  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 8-29: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 SPI2IP<2:0>: SPI2 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SPF2IP<2:0>: SPI2 Fault Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2010-2014 Microchip Technology Inc. DS30009996G-page 129

PIC24FJ128GA310 FAMILY REGISTER 8-30: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC3IP2 IC3IP1 IC3IP0 — DMA3IP2 DMA3IP1 DMA3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC5IP<2:0>: Input Capture Channel 5 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 IC4IP<2:0>: Input Capture Channel 4 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC3IP<2:0>: Input Capture Channel 3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 DMA3IP<2:0>: DMA Channel 3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS30009996G-page 130  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 8-31: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC7IP2 OC7IP1 OC7IP0 — OC6IP2 OC6IP1 OC6IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC5IP2 OC5IP1 OC5IP0 — IC6IP2 IC6IP1 IC6IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 OC7IP<2:0>: Output Compare Channel 7 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC6IP<2:0>: Output Compare Channel 6 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 OC5IP<2:0>: Output Compare Channel 5 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 IC6IP<2:0>: Input Capture Channel 6 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2010-2014 Microchip Technology Inc. DS30009996G-page 131

PIC24FJ128GA310 FAMILY REGISTER 8-32: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — DMA4IP2 DMA4IP1 DMA4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — PMPIP2 PMPIP1 PMPIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 DMA4IP<2:0>: DMA Channel 4 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 PMPIP<2:0>: Parallel Master Port Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS30009996G-page 132  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 8-33: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 MI2C2IP<2:0>: Master I2C2 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SI2C2IP<2:0>: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010-2014 Microchip Technology Inc. DS30009996G-page 133

PIC24FJ128GA310 FAMILY REGISTER 8-34: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT4IP2 INT4IP1 INT4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — INT3IP2 INT3IP1 INT3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 INT4IP<2:0>: External Interrupt 4 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 INT3IP<2:0>: External Interrupt 3 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS30009996G-page 134  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 8-35: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — RTCIP2 RTCIP1 RTCIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — DMA5IP2 DMA5IP1 DMA5IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 RTCIP<2:0>: Real-Time Clock and Calendar Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 DMA5IP<2:0>: DMA Channel 5 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010-2014 Microchip Technology Inc. DS30009996G-page 135

PIC24FJ128GA310 FAMILY REGISTER 8-36: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 CRCIP<2:0>: CRC Generator Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U2ERIP<2:0>: UART2 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 U1ERIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS30009996G-page 136  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 8-37: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — HLVDIP2 HLVDIP1 HLVDIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 HLVDIP<2:0>: High/Low-Voltage Detect Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled REGISTER 8-38: IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — CTMUIP2 CTMUIP1 CTMUIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 CTMUIP<2:0>: CTMU Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010-2014 Microchip Technology Inc. DS30009996G-page 137

PIC24FJ128GA310 FAMILY REGISTER 8-39: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U3TXIP2 U3TXIP1 U3TXIP0 — U3RXIP2 U3RXIP1 U3RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U3ERIP2 U3ERIP1 U3ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U3TXIP<2:0>: UART3 Transmitter Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U3RXIP<2:0>: UART3 Receiver Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 U3ERIP<2:0>: UART3 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS30009996G-page 138  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 8-40: IPC21: INTERRUPT PRIORITY CONTROL REGISTER 21 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U4ERIP2 U4ERIP1 U4ERIP0 — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U4ERIP<2:0>: UART4 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11-0 Unimplemented: Read as ‘0’  2010-2014 Microchip Technology Inc. DS30009996G-page 139

PIC24FJ128GA310 FAMILY REGISTER 8-41: IPC22: INTERRUPT PRIORITY CONTROL REGISTER 22 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U4TXIP2 U4TXIP1 U4TXIP0 — U4RXIP2 U4RXIP1 U4RXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 U4TXIP<2:0>: UART4 Transmitter Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U4RXIP<2:0>: UART4 Receiver Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS30009996G-page 140  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 8-42: IPC25: INTERRUPT PRIORITY CONTROL REGISTER 25 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — LCDIP2 LCDIP1 LCDIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 LCDIP<2:0>: LCD Controller Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled REGISTER 8-43: IPC29: INTERRUPT PRIORITY CONTROL REGISTER 29 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — JTAGIP2 JTAGIP1 JTAGIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 JTAGIP<2:0>: JTAG Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2010-2014 Microchip Technology Inc. DS30009996G-page 141

PIC24FJ128GA310 FAMILY REGISTER 8-44: INTTREG: INTERRUPT CONTROLLER TEST REGISTER R-0, HSC U-0 R/W-0 U-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 U-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CPUIRQ: Interrupt Request from Interrupt Controller CPU bit 1 = An interrupt request has occurred but has not yet been Acknowledged by the CPU; this happens when the CPU priority is higher than the interrupt priority 0 = No interrupt request is unacknowledged bit 14 Unimplemented: Read as ‘0’ bit 13 VHOLD: Vector Number Capture Configuration bit 1 = The VECNUMx bits contain the value of the highest priority pending interrupt 0 = The VECNUMx bits contain the value of the last Acknowledged interrupt (i.e., the last interrupt that has occurred with higher priority than the CPU, even if other interrupts are pending) bit 12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • • • 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 bit 7 Unimplemented: Read as ‘0’ bit 6-0 VECNUM<5:0>: Vector Number of Pending Interrupt or Last Acknowledged Interrupt bits VHOLD = 1: The VECNUMx bits indicate the vector number (from 0 to 118) of the last interrupt to occur VHOLD = 0: The VECNUMx bits indicate the vector number (from 0 to 118) of the interrupt request currently being handled DS30009996G-page 142  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 8.4 Interrupt Setup Procedures 8.4.3 TRAP SERVICE ROUTINE (TSR) A Trap Service Routine (TSR) is coded like an ISR, 8.4.1 INITIALIZATION except that the appropriate trap status flag in the To configure an interrupt source: INTCON1 register must be cleared to avoid re-entry into the TSR. 1. Set the NSTDIS (INTCON1<15>) control bit if nested interrupts are not desired. 8.4.4 INTERRUPT DISABLE 2. Select the user-assigned priority level for the interrupt source by writing the control bits in the All user interrupts can be disabled using the following appropriate IPCx register. The priority level will procedure: depend on the specific application and type of 1. Push the current SR value onto the software interrupt source. If multiple priority levels are not stack using the PUSH instruction. desired, the IPCx register control bits for all 2. Force the CPU to Priority Level 7 by inclusive enabled interrupt sources may be programmed ORing the value 0Eh with SRL. to the same non-zero value. To enable user interrupts, the POP instruction may be Note: At a device Reset, the IPCx registers are used to restore the previous SR value. initialized, such that all user interrupt Note that only user interrupts with a priority level of 7 or sources are assigned to Priority Level 4. less can be disabled. Trap sources (Levels8-15) 3. Clear the interrupt flag status bit associated with cannot be disabled. the peripheral in the associated IFSx register. The DISI instruction provides a convenient way to 4. Enable the interrupt source by setting the disable interrupts of Priority Levels 1-6 for a fixed interrupt enable control bit associated with the period of time. Level 7 interrupt sources are not source in the appropriate IECx register. disabled by the DISI instruction. 8.4.2 INTERRUPT SERVICE ROUTINE (ISR) The method that is used to declare an Interrupt Service Routine (ISR) and initialize the IVT with the correct vec- tor address will depend on the programming language (i.e., ‘C’ or assembler) and the language development toolsuite that is used to develop the application. In general, the user must clear the interrupt flag in the appropriate IFSx register for the source of the interrupt that the ISR handles; otherwise, the ISR will be re-entered immediately after exiting the routine. If the ISR is coded in assembly language, it must be termi- nated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level.  2010-2014 Microchip Technology Inc. DS30009996G-page 143

PIC24FJ128GA310 FAMILY NOTES: DS30009996G-page 144  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 9.0 OSCILLATOR • Software-controllable switching between various CONFIGURATION clock sources • Software-controllable postscaler for selective Note: This data sheet summarizes the features of clocking of CPU for system power savings this group of PIC24F devices. It is not • A Fail-Safe Clock Monitor (FSCM) that detects intended to be a comprehensive refer- clock failure and permits safe application recovery ence source. For more information, refer or shutdown to “Oscillator” (DS39700) in the • A separate and independently configurable system “dsPIC33/PIC24 Family Reference Man- clock output for synchronizing external hardware ual”. The information in this data sheet A simplified diagram of the oscillator system is shown supersedes the information in the FRM. in Figure9-1. The oscillator system for PIC24FJ128GA310 family devices has the following features: • A total of four external and internal oscillator options as clock sources, providing 11 different clock modes • On-chip 4x PLL to boost internal operating frequency on select internal and external oscillator sources FIGURE 9-1: PIC24FJ128GA310 FAMILY CLOCK DIAGRAM Primary Oscillator REFOCON<15:8> XT, HS, EC OSCO Reference Clock Generator XTPLL, HSPLL, OSCI ECPLL, FRCPLL 4 x PLL REFO 8 MHz er 4 MHz FRC al FRCDIV c Oscillator 8 MHz sts (nominal) Po Peripherals CLKDIV<10:8> FRC CLKO LPRC LPRC er Oscillator 31 kHz (nominal) al CPU c s st Secondary Oscillator o P SOSC SOSCO CLKDIV<14:12> SOSCEN Enable SOSCI Oscillator Clock Control Logic Fail-Safe Clock Monitor WDT, PWRT Clock Source Option for Other Modules  2010-2014 Microchip Technology Inc. DS30009996G-page 145

PIC24FJ128GA310 FAMILY 9.1 CPU Clocking Scheme 9.2 Initial Configuration on POR The system clock source can be provided by one of The oscillator source (and operating mode) that is four sources: used at a device Power-on Reset event is selected using Configuration bit settings. The Oscillator • Primary Oscillator (POSC) on the OSCI and Configuration bit settings are located in the OSCO pins Configuration registers in the program memory (refer • Secondary Oscillator (SOSC) on the SOSCI and to Section29.0 “Special Features” for further SOSCO pins details). The Primary Oscillator Configuration bits, • Fast Internal RC (FRC) Oscillator POSCMD<1:0> (Configuration Word 2<1:0>), and the • Low-Power Internal RC (LPRC) Oscillator Initial Oscillator Select Configuration bits, FNOSC<2:0> (Configuration Word 2<10:8>), select The primary oscillator and FRC sources have the the oscillator source that is used at a Power-on Reset. option of using the internal 4x PLL. The frequency of the FRC clock source can optionally be reduced by the The FRC Primary Oscillator with Postscaler (FRCDIV) is the default (unprogrammed) selection. The Second- programmable clock divider. The selected clock source generates the processor and peripheral clock sources. ary Oscillator (SOSC), or one of the internal oscillators, may be chosen by programming these bit locations. The processor clock source is divided by two to pro- duce the internal instruction cycle clock, FCY. In this The Configuration bits allow users to choose between document, the instruction cycle clock is also denoted the various clock modes, shown in Table9-1. by FOSC/2. The internal instruction cycle clock, FOSC/2, 9.2.1 CLOCK SWITCHING MODE can be provided on the OSCO I/O pin for some CONFIGURATION BITS operating modes of the primary oscillator. The FCKSM<1:0> Configuration bits (Configuration Word2<7:6>) are used to jointly configure device clock switching and the Fail-Safe Clock Monitor (FSCM). Clock switching is enabled only when FCKSM1 is programmed (‘0’). The FSCM is enabled only when the FCKSM<1:0> bits are both programmed (‘00’). TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0> Note Fast RC Oscillator with Postscaler Internal 11 111 1, 2 (FRCDIV) (Reserved) Internal xx 110 1 Low-Power RC Oscillator (LPRC) Internal 11 101 1 Secondary (Timer1) Oscillator Secondary 11 100 1 (SOSC) Primary Oscillator (XT) with PLL Primary 01 011 Module (XTPLL) Primary Oscillator (EC) with PLL Primary 00 011 Module (ECPLL) Primary Oscillator (HS) Primary 10 010 Primary Oscillator (XT) Primary 01 010 Primary Oscillator (EC) Primary 00 010 Fast RC Oscillator with PLL Module Internal 11 001 1 (FRCPLL) Fast RC Oscillator (FRC) Internal 11 000 1 Note 1: OSCO pin function is determined by the OSCIOFCN Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. DS30009996G-page 146  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 9.3 Control Registers The CLKDIV register (Register9-2) controls the features associated with Doze mode, as well as the The operation of the oscillator is controlled by three postscaler for the FRC oscillator. Special Function Registers: The OSCTUN register (Register9-3) allows the user to • OSCCON fine tune the FRC oscillator over a range of approxi- • CLKDIV mately ±1.5%. Each bit increment or decrement • OSCTUN changes the factory calibrated frequency of the FRC oscillator by a fixed amount. The OSCCON register (Register9-1) is the main con- trol register for the oscillator. It controls clock source switching and allows the monitoring of clock sources. REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-0 R-0 R-0 U-0 R/W-x(1) R/W-x(1) R/W-x(1) — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 bit 15 bit 8 R/SO-0 R/W-0 R-0(3) U-0 R/CO-0 R/W-0 R/W-0 R/W-0 CLKLOCK IOLOCK(2) LOCK — CF POSCEN SOSCEN OSWEN bit 7 bit 0 Legend: CO = Clearable Only bit SO = Settable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Selection bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC<2:0>: New Oscillator Selection bits(1) 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) Note 1: Reset values for these bits are determined by the FNOSCx Configuration bits. 2: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is ‘1’ once the IOLOCK bit is set, it cannot be cleared. 3: This bit also resets to ‘0’ during any valid clock switch or whenever a Non-PLL Clock mode is selected.  2010-2014 Microchip Technology Inc. DS30009996G-page 147

PIC24FJ128GA310 FAMILY REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is Enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is Disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit. bit 6 IOLOCK: I/O Lock Enable bit(2) 1 = I/O lock is active 0 = I/O lock is not active bit 5 LOCK: PLL Lock Status bit(3) 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected bit 2 POSCEN: Primary Oscillator Sleep Enable bit 1 = Primary oscillator continues to operate during Sleep mode 0 = Primary oscillator is disabled during Sleep mode bit 1 SOSCEN: 32kHz Secondary Oscillator (SOSC) Enable bit 1 = Enables Secondary Oscillator 0 = Disables Secondary Oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Initiates an oscillator switch to a clock source specified by the NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: Reset values for these bits are determined by the FNOSCx Configuration bits. 2: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is ‘1’ once the IOLOCK bit is set, it cannot be cleared. 3: This bit also resets to ‘0’ during any valid clock switch or whenever a Non-PLL Clock mode is selected. DS30009996G-page 148  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 9-2: CLKDIV: CLOCK DIVIDER REGISTER R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 ROI DOZE2 DOZE1 DOZE0 DOZEN(1) RCDIV2 RCDIV1 RCDIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1 0 = Interrupts have no effect on the DOZEN bit bit 14-12 DOZE<2:0>: CPU Peripheral Clock Ratio Select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 bit 11 DOZEN: DOZE Enable bit(1) 1 = DOZE<2:0> bits specify the CPU peripheral clock ratio 0 = CPU peripheral clock ratio set to 1:1 bit 10-8 RCDIV<2:0>: FRC Postscaler Select bits 111 = 31.25kHz (divide-by-256) 110 = 125kHz (divide-by-64) 101 = 250kHz (divide-by-32) 100 = 500kHz (divide-by-16) 011 = 1MHz (divide-by-8) 010 = 2MHz (divide-by-4) 001 = 4MHz (divide-by-2) 000 = 8MHz (divide-by-1) bit 7-0 Unimplemented: Read as ‘0’ Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.  2010-2014 Microchip Technology Inc. DS30009996G-page 149

PIC24FJ128GA310 FAMILY REGISTER 9-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN<5:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1) 011111 = Maximum frequency deviation 011110 =    000001 = 000000 = Center frequency, oscillator is running at factory calibrated frequency 111111 =    100001 = 100000 = Minimum frequency deviation Note 1: Increments or decrements of TUN<5:0> may not change the FRC frequency in equal steps over the FRC tuning range and may not be monotonic. 9.4 Clock Switching Operation 9.4.1 ENABLING CLOCK SWITCHING With few limitations, applications are free to switch To enable clock switching, the FCKSMx Configuration between any of the four clock sources (POSC, SOSC, bits in CW2 must be programmed to ‘00’. (Refer to FRC and LPRC) under software control and at any Section29.1 “Configuration Bits” for further details.) time. To limit the possible side effects that could result If the FCKSMx Configuration bits are unprogrammed from this flexibility, PIC24F devices have a safeguard (‘1x’), the clock switching function and Fail-Safe Clock lock built into the switching process. Monitor function are disabled. This is the default setting. The NOSCx control bits (OSCCON<10:8>) do not Note: The Primary Oscillator mode has three control the clock selection when clock switching is dis- different submodes (XT, HS and EC) abled. However, the COSCx bits (OSCCON<14:12>) which are determined by the POSCMDx will reflect the clock source selected by the FNOSCx Configuration bits. While an application Configuration bits. can switch to and from Primary Oscillator mode in software, it cannot switch The OSWEN control bit (OSCCON<0>) has no effect between the different primary submodes when clock switching is disabled. It is held at ‘0’ at all without reprogramming the device. times. DS30009996G-page 150  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 9.4.2 OSCILLATOR SWITCHING A recommended code sequence for a clock switch SEQUENCE includes the following: At a minimum, performing a clock switch requires this 1. Disable interrupts during the OSCCON register basic sequence: unlock and write sequence. 2. Execute the unlock sequence for the OSCCON 1. If desired, read the COSCx bits high byte by writing 78h and 9Ah to (OSCCON<14:12>) to determine the current OSCCON<15:8> in two back-to-back oscillator source. instructions. 2. Perform the unlock sequence to allow a write to 3. Write new oscillator source to the NOSCx bits in the OSCCON register high byte. the instruction immediately following the unlock 3. Write the appropriate value to the NOSCx bits sequence. (OSCCON<10:8>) for the new oscillator source. 4. Execute the unlock sequence for the OSCCON 4. Perform the unlock sequence to allow a write to low byte by writing 46h and 57h to the OSCCON register low byte. OSCCON<7:0> in two back-to-back instructions. 5. Set the OSWEN bit to initiate the oscillator 5. Set the OSWEN bit in the instruction immediately switch. following the unlock sequence. Once the basic sequence is completed, the system 6. Continue to execute code that is not clock hardware responds automatically as follows: clock-sensitive (optional). 1. The clock switching hardware compares the 7. Invoke an appropriate amount of software delay COSCx bits with the new value of the NOSCx (cycle counting) to allow the selected oscillator bits. If they are the same, then the clock switch and/or PLL to start and stabilize. is a redundant operation. In this case, the 8. Check to see if OSWEN is ‘0’. If it is, the switch OSWEN bit is cleared automatically and the was successful. If OSWEN is still set, then clock switch is aborted. check the LOCK bit to determine the cause of 2. If a valid clock switch has been initiated, the failure. LOCK (OSCCON<5>) and CF (OSCCON<3>) The core sequence for unlocking the OSCCON register bits are cleared. and initiating a clock switch is shown in Example9-1. 3. The new oscillator is turned on by the hardware if it is not currently running. If a crystal oscillator EXAMPLE 9-1: BASIC CODE SEQUENCE must be turned on, the hardware will wait until FOR CLOCK SWITCHING the OST expires. If the new source is using the PLL, then the hardware waits until a PLL lock is ;Place the new oscillator selection in W0 detected (LOCK = 1). ;OSCCONH (high byte) Unlock Sequence MOV #OSCCONH, w1 4. The hardware waits for 10 clock cycles from the MOV #0x78, w2 new clock source and then performs the clock MOV #0x9A, w3 switch. MOV.b w2, [w1] 5. The hardware clears the OSWEN bit to indicate a MOV.b w3, [w1] successful clock transition. In addition, the ;Set new oscillator selection NOSCx bits values are transferred to the COSCx MOV.b WREG, OSCCONH bits. ;OSCCONL (low byte) unlock sequence MOV #OSCCONL, w1 6. The old clock source is turned off at this time, with MOV #0x46, w2 the exception of LPRC (if WDT or FSCM are MOV #0x57, w3 enabled) or SOSC (if SOSCEN remains set). MOV.b w2, [w1] MOV.b w3, [w1] Note1: The processor will continue to execute ;Start oscillator switch operation code throughout the clock switching BSET OSCCON,#0 sequence. Timing-sensitive code should not be executed during this time. 2: Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direc- tion. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes.  2010-2014 Microchip Technology Inc. DS30009996G-page 151

PIC24FJ128GA310 FAMILY 9.5 Secondary Oscillator (SOSC) In general, the crystal circuit connections should be as short as possible. It is also good practice to surround 9.5.1 BASIC SOSC OPERATION the crystal circuit with a ground loop or ground plane. For more information on crystal circuit design, please PIC24FJ128GA310 family devices do not have to set the refer to “Oscillator” (DS39700) in the “dsPIC33/PIC24 SOSCEN bit to use the Secondary Oscillator. Any Family Reference Manual”. Additional information is module requiring the SOSC (such as RTCC, Timer1 or also available in these Microchip Application Notes: DSWDT) will automatically turn on the SOSC when the clock signal is needed. The SOSC, however, has a long • AN826, “Crystal Oscillator Basics and Crystal start-up time. To avoid delays for peripheral start-up, the Selection for rfPIC® and PICmicro® Devices” SOSC can be manually started using the SOSCEN bit. (DS00826) • AN849, “Basic PICmicro® Oscillator Design” To use the Secondary Oscillator, the SOSCSEL bit (DS00849). (CW3<8>) must be set (= 1). Programming SOSCSEL (= 0) configures the SOSC pins for Digital mode, 9.6 Reference Clock Output enabling digital input functionality on the pins. In addition to the CLKO output (FOSC/2) available in 9.5.2 EXTERNAL (DIGITAL) CLOCK certain oscillator modes, the device clock in the MODE (SCLKI) PIC24FJ128GA310 family devices can also be config- The SOSC can also be configured to run from an ured to provide a reference clock output signal to a port external 32 kHz clock source, rather than the internal pin. This feature is available in all oscillator configura- oscillator. In this mode, also referred to as Digital mode, tions and allows the user to select a greater range of the clock source provided on the SCLKI pin is used to clock submultiples to drive external devices in the clock any modules that are configured to use the application. Secondary Oscillator. In this mode, the crystal driving This reference clock output is controlled by the circuit is disabled and the SOSCEN bit (OSCCON<1>) REFOCON register (Register9-4). Setting the ROEN has no effect. bit (REFOCON<15>) makes the clock signal available on the REFO pin. The RODIVx bits (REFOCON<11:8>) 9.5.3 SOSC LAYOUT CONSIDERATIONS enable the selection of 16 different clock divider The pinout limitations on low pin count devices, such as options. those in the PIC24FJ128GA310 family, may make the The ROSSLP and ROSEL bits (REFOCON<13:12>) SOSC more susceptible to noise than other PIC24FJ control the availability of the reference output during devices. Unless proper care is taken in the design and Sleep mode. The ROSEL bit determines if the oscillator layout of the SOSC circuit, this external noise may on OSC1 and OSC2, or the current system clock source, introduce inaccuracies into the oscillator’s period. is used for the reference clock output. The ROSSLP bit Note: A typical 50K ESR (65K-70K Max) crystal determines if the reference source is available on REFO is recommended for the reliable operation when the device is in Sleep mode. of the SOSC. The duty cycle of the SOSC To use the reference clock output in Sleep mode, both output can be measured on the REFO pin the ROSSLP and ROSEL bits must be set. The device and is recommended to be within ±15% clock must also be configured for one of the primary from a 50% duty cycle. modes (EC, HS or XT). Otherwise, if the POSCEN bit is also not set, the oscillator on OSC1 and OSC2 will be powered down when the device enters Sleep mode. Clearing the ROSEL bit allows the reference output frequency to change as the system clock changes during any clock switches. DS30009996G-page 152  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 9-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROEN: Reference Oscillator Output Enable bit 1 = Reference oscillator is enabled on the REFO pin 0 = Reference oscillator is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 ROSSLP: Reference Oscillator Output Stop in Sleep bit 1 = Reference oscillator continues to run in Sleep 0 = Reference oscillator is disabled in Sleep bit 12 ROSEL: Reference Oscillator Source Select bit 1 = Primary oscillator is used as the base clock. Note that the crystal oscillator must be enabled using the FOSC<2:0> bits; the crystal maintains the operation in Sleep mode. 0 = System clock is used as the base clock; base clock reflects any clock switching of the device bit 11-8 RODIV<3:0>: Reference Oscillator Divisor Select bits 1111 = Base clock value divided by 32,768 1110 = Base clock value divided by 16,384 1101 = Base clock value divided by 8,192 1100 = Base clock value divided by 4,096 1011 = Base clock value divided by 2,048 1010 = Base clock value divided by 1,024 1001 = Base clock value divided by 512 1000 = Base clock value divided by 256 0111 = Base clock value divided by 128 0110 = Base clock value divided by 64 0101 = Base clock value divided by 32 0100 = Base clock value divided by 16 0011 = Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value bit 7-0 Unimplemented: Read as ‘0’  2010-2014 Microchip Technology Inc. DS30009996G-page 153

PIC24FJ128GA310 FAMILY NOTES: DS30009996G-page 154  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 10.0 POWER-SAVING FEATURES 10.1 Overview of Power-Saving Modes Note: This data sheet summarizes the features In addition to full-power operation, otherwise known as of this group of PIC24FJ devices. It is not Run mode, the PIC24FJ128GA310 family of devices intended to be a comprehensive offers three Instruction-Based, Power-Saving modes reference source. For more information, and one Hardware-Based mode: refer to “Power-Saving Features with • Idle VBAT” (DS30622) in the “dsPIC33/PIC24 • Sleep (Sleep and Low-Voltage Sleep) Family Reference Manual”. The • Deep Sleep information in this data sheet supersedes the information in the FRM. • VBAT (with and without RTCC) All four modes can be activated by powering down dif- The PIC24FJ128GA310 family of devices provides the ferent functional areas of the microcontroller, allowing ability to manage power consumption by selectively progressive reductions of operating and Idle power managing clocking to the CPU and the peripherals. In consumption. In addition, three of the modes can be general, a lower clock frequency and a reduction in the tailored for more power reduction, at a trade-off of number of circuits being clocked reduces consumed some operating features. Table10-1 lists all of the power. operating modes, in order of increasing power savings. PIC24FJ128GA310 family devices manage power Table10-2 summarizes how the microcontroller exits consumption with five strategies: the different modes. Specific information is provided in the following sections. • Instruction-Based Power Reduction Modes • Hardware-Based Power Reduction Features • Clock Frequency Control • Software Controlled Doze Mode • Selective Peripheral Control in Software Combinations of these methods can be used to selectively tailor an application’s power consumption, while still maintaining critical application features, such as timing-sensitive communications. TABLE 10-1: OPERATING MODES FOR PIC24FJ128GA310 FAMILY DEVICES Active Systems Mode Entry DSGPR0/ Data RAM Core Peripherals RTCC(1) DSGPR1 Retention Retention Run (default) N/A Y Y Y Y Y Idle Instruction N Y Y Y Y Sleep: Sleep Instruction N S(2) Y Y Y Low-Voltage Sleep Instruction + N S(2) Y Y Y RETEN bit Deep Sleep: Deep Sleep Instruction + N N N Y Y DSEN bit VBAT: with RTCC Hardware N N N Y Y Note 1: If RTCC is otherwise enabled in firmware. 2: A select peripheral can operate during this mode from LPRC or some external clock.  2010-2014 Microchip Technology Inc. DS30009996G-page 155

PIC24FJ128GA310 FAMILY TABLE 10-2: EXITING POWER SAVING MODES Exit Conditions Code Mode Interrupts Resets Execution RTCC VDD WDT Resumes(2) Alarm Restore All INT0 All POR MCLR Idle Y Y Y Y Y Y Y N/A Next Instruction Sleep (all modes) Y Y Y Y Y Y Y N/A Deep Sleep N Y N Y Y Y Y(1) N/A Reset Vector VBAT N N N N N N N Y Reset Vector Note 1: Deep Sleep WDT. 2: Code execution resumption is also valid for all the exit conditions; for example, a MCLR and POR exit will cause code execution from the Reset vector. 10.1.1 INSTRUCTION-BASED Sleep and Idle modes can be exited as a result of an POWER-SAVING MODES enabled interrupt, WDT time-out or a device Reset. When the device exits these modes, it is said to Three of the power-saving modes are entered through “wake-up”. the execution of the PWRSAV instruction. Sleep mode stops clock operation and halts all code execution. Idle The features enabled with the low-voltage/retention mode halts the CPU and code execution, but allows regulator results in some changes to the way that Sleep peripheral modules to continue operation. Deep Sleep mode behaves. See Section10.3 “Sleep Mode”. mode stops clock operation, code execution and all 10.1.1.1 Interrupts Coincident with Power peripherals, except RTCC and DSWDT. It also freezes Save Instructions I/O states and removes power to Flash memory and may remove power to SRAM. Any interrupt that coincides with the execution of a The assembly syntax of the PWRSAV instruction is shown PWRSAV instruction will be held off until entry into in Example10-1. Sleep and Idle modes are entered Sleep/Deep Sleep or Idle mode has completed. The directly with a single assembler command. Deep Sleep device will then wake-up from Sleep/Deep Sleep or Idle requires an additional sequence to unlock and enable mode. the entry into Deep Sleep, which is described in Section10.4.1 “Entering Deep Sleep Mode”. Note: SLEEP_MODE and IDLE_MODE are constants defined in the assembler include file for the selected device. To enter Deep Sleep, the DSCON<0> bit should be cleared before setting the DSEN bit, EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX // Syntax to enter Sleep mode: PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode // //Synatx to enter Idle mode: PWRSAV #IDLE_MODE ; Put the device into IDLE mode // // Syntax to enter Deep Sleep mode: // First use the unlock sequence to set the DSEN bit (see Example 10-2) CLR DSCON CLR DSCON ; (repeat the command) BSET DSCON, #DSEN ; Enable Deep Sleep BSET DSCON, #DSEN ; Enable Deep Sleep (repeat the command) PWRSAV #SLEEP_MODE ; Put the device into Deep SLEEP mode DS30009996G-page 156  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 10.1.2 HARDWARE-BASED 10.3 Sleep Mode POWER-SAVING MODE Sleep mode includes these features: The hardware-based VBAT mode does not require any • The system clock source is shut down. If an action by the user during code development. Instead, it on-chip oscillator is used, it is turned off. is a hardware design feature that allows the micro- controller to retain critical data (using the DSGPRx • The device current consumption will be reduced registers) and maintain the RTCC when VDD is removed to a minimum provided that no I/O pin is sourcing from the application. This is accomplished by supplying current. a backup power source to a specific power pin. VBAT • The I/O pin directions and states are frozen. mode is described in more detail in Section10.5 “Vbat • The Fail-Safe Clock Monitor does not operate Mode”. during Sleep mode since the system clock source is disabled. 10.1.3 LOW-VOLTAGE/RETENTION • The LPRC clock will continue to run in Sleep REGULATOR mode if the WDT or RTCC, with LPRC as clock PIC24FJ128GA310 family devices incorporate a source, is enabled. second on-chip voltage regulator, designed to provide • The WDT, if enabled, is automatically cleared power to select microcontroller features at 1.2V nomi- prior to entering Sleep mode. nal. This regulator allows features, such as data RAM • Some device features or peripherals may and the WDT, to be maintained in power-saving modes continue to operate in Sleep mode. This includes where they would otherwise be inactive, or maintain items, such as the Input Change Notification on them at a lower power than would otherwise be the the I/O ports, or peripherals that use an external case. clock input. Any peripheral that requires the sys- The low-voltage/retention regulator is only available tem clock source for its operation will be disabled when Sleep or Deep Sleep modes are invoked. It is in Sleep mode. controlled by the LPCFG Configuration bit (CW1<10>) The device will wake-up from Sleep mode on any of and in firmware by the RETEN bit (RCON<12>). these events: LPCFG must be programmed (= 0) and the RETEN bit • On any interrupt source that is individually must be set (= 1) for the regulator to be enabled. enabled 10.2 Idle Mode • On any form of device Reset • On a WDT time-out Idle mode has these features: On wake-up from Sleep, the processor will restart with • The CPU will stop executing instructions. the same clock source that was active when Sleep • The WDT is automatically cleared. mode was entered. • The system clock source remains active. By 10.3.1 LOW-VOLTAGE/RETENTION SLEEP default, all peripheral modules continue to operate MODE normally from the system clock source, but can also be selectively disabled (see Section10.8 Low-Voltage/Retention Sleep mode functions as Sleep “Selective Peripheral Module Control”). mode with the same features and wake-up triggers. • If the WDT or FSCM is enabled, the LPRC will The difference is that the low-voltage/retention regula- also remain active. tor allows core digital logic voltage (VCORE) to drop to 1.2V nominal. This permits an incremental reduction of The device will wake from Idle mode on any of these power consumption over what would be required if events: VCORE was maintained at a 1.8V (minimum) level. • Any interrupt that is individually enabled Low-Voltage Sleep mode requires a longer wake-up • Any device Reset time than Sleep mode, due to the additional time • A WDT time-out required to bring VCORE back to 1.8V (known as TREG). On wake-up from Idle, the clock is reapplied to the CPU In addition, the use of the low-voltage/retention regula- and instruction execution begins immediately, starting tor limits the amount of current that can be sourced to with the instruction following the PWRSAV instruction or any active peripherals, such as the RTCC/LCD, etc. the first instruction in the ISR.  2010-2014 Microchip Technology Inc. DS30009996G-page 157

PIC24FJ128GA310 FAMILY 10.4 Deep Sleep Mode The sequence to enter Deep Sleep mode is: 1. If the application requires the Deep Sleep WDT, Deep Sleep mode provides the lowest levels of power enable it and configure its clock source. For consumption available from the Instruction-Based more information on Deep Sleep WDT, see modes. Section10.4.5 “Deep Sleep WDT”. Deep Sleep modes have these features: 2. If the application requires Deep Sleep BOR, • The system clock source is shut down. If an enable it by programming the DSBOREN on-chip oscillator is used, it is turned off. Configuration bit (FDS<6>). • The device current consumption will be reduced 3. If the application requires wake-up from Deep to a minimum. Sleep on RTCC alarm, enable and configure the • The I/O pin directions and states are frozen. RTCC module. For more information on RTCC, • The Fail-Safe Clock Monitor does not operate see Section22.0 “Real-Time Clock and during Sleep mode since the system clock source Calendar (RTCC)”. is disabled. 4. If needed, save any critical application context • The LPRC clock will continue to run in Deep data by writing it to the DSGPR0 and DSGPR1 Sleep mode if the WDT or RTCC with LPRC as registers (optional). clock source is enabled. 5. Enable Deep Sleep mode by setting the DSEN • The dedicated Deep Sleep WDT and BOR bit (DSCON<15>). systems, if enabled, are used. Note: A repeat sequence is required to set the • The RTCC and its clock source continue to run, if DSEN bit. The repeat sequence (repeating enabled. All other peripherals are disabled. the instruction twice) is required to write Entry into Deep Sleep mode is completely under into any of the Deep Sleep registers software control. Exit from the Deep Sleep modes can (DSCON, DSWAKE, DSGPR0, DSGPR1). be triggered from any of the following events: This is required to avoid the user from entering Deep Sleep by mistake. Any write • POR event to these registers has to be done twice to • MCLR event actually complete the write (see • RTCC alarm (If the RTCC is present) Example10-2). • External Interrupt 0 6. Enter Deep Sleep mode by issuing three NOP • Deep Sleep Watchdog Timer (DSWDT) time-out commands and then a PWRSAV #0 instruction. 10.4.1 ENTERING DEEP SLEEP MODE Any time the DSEN bit is set, all bits in the DSWAKE Deep Sleep mode is entered by setting the DSEN bit in register will be automatically cleared. the DSCON register, and then executing a Sleep command (PWRSAV #SLEEP_MODE) within one instruc- EXAMPLE 10-2: THE REPEAT SEQUENCE tion cycle, to minimize the chance that Deep Sleep will Example 1: be spuriously entered. mov #8000, w2 ; enable DS If the PWRSAV command is not given within one mov w2, DSCON instruction cycle, the DSEN bit will be cleared by the mov w2, DSCON ; second write required to hardware and must be set again by the software before actually write to DSCON entering Deep Sleep mode. The DSEN bit is also Example 2: automatically cleared when exiting Deep Sleep mode. bset DSCON, #15 Note: To re-enter Deep Sleep after a Deep Sleep nop wake-up, allow a delay of at least 3 TCY nop after clearing the RELEASE bit. nop bset DSCON, #15 ; enable DS (two writes required) DS30009996G-page 158  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 10.4.2 EXITING DEEP SLEEP MODES 10.4.3 SAVING CONTEXT DATA WITH THE DSGPRx REGISTERS Deep Sleep modes exit on any one of the following events: • POR event on VDD supply. If there is no DSBOR As exiting Deep Sleep mode causes a POR, most circuit to re-arm the VDD supply POR circuit, the Special Function Registers reset to their default POR external VDD supply must be lowered to the values. In addition, because VCORE power is not sup- natural arming voltage of the POR circuit. plied in Deep Sleep mode, information in data RAM may be lost when exiting this mode. • DSWDT time-out. When the DSWDT timer times out, the device exits Deep Sleep. Applications which require critical data to be saved • RTCC alarm (if RTCEN = 1). prior to Deep Sleep may use the Deep Sleep General Purpose registers, DSGPR0 and DSGPR1, or data • Assertion (‘0’) of the MCLR pin. EEPROM (if available). Unlike other SFRs, the • Assertion of the INT0 pin (if the interrupt was contents of these registers are preserved while the enabled before Deep Sleep mode was entered). device is in Deep Sleep mode. After exiting Deep The polarity configuration is used to determine the Sleep, software can restore the data by reading the assertion level (‘0’ or ‘1’) of the pin that will cause an exit from Deep Sleep mode. Exiting from Deep registers and clearing the RELEASE bit (DSCON<0>). Sleep mode requires a change on the INT0 pin 10.4.4 I/O PINS IN DEEP SLEEP MODES while in Deep Sleep mode. During Deep Sleep, the general purpose I/O pins retain Note: Any interrupt pending, when entering their previous states and the Secondary Oscillator Deep Sleep mode, is cleared. (SOSC) will remain running, if enabled. Pins that are Exiting Deep Sleep generally does not retain the state configured as inputs (TRISx bit set), prior to entry into of the device and is equivalent to a Power-on Reset Deep Sleep, remain high-impedance during Deep (POR) of the device. Exceptions to this include the Sleep. Pins that are configured as outputs (TRISx bit RTCC (if present), which remains operational through clear), prior to entry into Deep Sleep, remain as output the wake-up, the DSGPRx registers and DSWDT. pins during Deep Sleep. While in this mode, they continue to drive the output level determined by their Wake-up events that occur from the time Deep Sleep corresponding LATx bit at the time of entry into Deep exits, until the time the POR sequence completes, are Sleep. not ignored. The DSWAKE register will capture ALL wake-up events, from DSEN set to RELEASE clear. Once the device wakes back up, all I/O pins continue to maintain their previous states, even after the device The sequence for exiting Deep Sleep mode is: has finished the POR sequence and is executing 1. After a wake-up event, the device exits Deep application code again. Pins configured as inputs Sleep and performs a POR. The DSEN bit is during Deep Sleep remain high-impedance, and pins cleared automatically. Code execution resumes configured as outputs continue to drive their previous at the Reset vector. value. After waking up, the TRISx and LATx registers, 2. To determine if the device exited Deep Sleep, and the SOSCEN bit (OSCCON<1>) are reset. If read the Deep Sleep bit, DPSLP (RCON<10>). firmware modifies any of these bits or registers, the This bit will be set if there was an exit from Deep I/Os will not immediately go to the newly configured Sleep mode. If the bit is set, clear it. states. Once the firmware clears the RELEASE bit 3. Determine the wake-up source by reading the (DSCON<0>), the I/O pins are “released”. This causes DSWAKE register. the I/O pins to take the states configured by their respective TRISx and LATx bit values. 4. Determine if a DSBOR event occurred during Deep Sleep mode by reading the DSBOR bit This means that keeping the SOSC running after (DSCON<1>). waking up requires the SOSCEN bit to be set before 5. If application context data has been saved, read clearing RELEASE. it back from the DSGPR0 and DSGPR1 registers. If the Deep Sleep BOR (DSBOR) is enabled, and a 6. Clear the RELEASE bit (DSCON<0>). DSBOR or a true POR event occurs during Deep Sleep, the I/O pins will be immediately released, similar to clearing the RELEASE bit. All previous state information will be lost, including the general purpose DSGPR0 and DSGPR1 contents.  2010-2014 Microchip Technology Inc. DS30009996G-page 159

PIC24FJ128GA310 FAMILY If a MCLR Reset event occurs during Deep Sleep, the 10.4.6 CHECKING AND CLEARING THE DSGPRx, DSCON and DSWAKE registers will remain STATUS OF DEEP SLEEP valid, and the RELEASE bit will remain set. The state Upon entry into Deep Sleep mode, the status bit, of the SOSC will also be retained. The I/O pins, DPSLP (RCON<10>), becomes set and must be however, will be reset to their MCLR Reset state. Since cleared by the software. RELEASE is still set, changes to the SOSCEN bit (OSCCON<1>) cannot take effect until the RELEASE On power-up, the software should read this status bit to bit is cleared. determine if the Reset was due to an exit from Deep Sleep mode, and clear the bit if it is set. Of the four In all other Deep Sleep wake-up cases, application possible combinations of DPSLP and POR bit states, firmware must clear the RELEASE bit in order to three cases can be considered: reconfigure the I/O pins. • Both the DPSLP and POR bits are cleared. In this 10.4.5 DEEP SLEEP WDT case, the Reset was due to some event other than a Deep Sleep mode exit. To enable the DSWDT in Deep Sleep mode, program the Configuration bit, DSWDTEN (CW4<7>). The • The DPSLP bit is clear, but the POR bit is set; this device WDT need not be enabled for the DSWDT to is a normal POR. function. Entry into Deep Sleep modes automatically • Both the DPSLP and POR bits are set. This reset the DSWDT. means that Deep Sleep mode was entered, the device was powered down and Deep Sleep mode The DSWDT clock source is selected by the was exited. DSWDTOSC Configuration bit (CW4<5>). The postscaler options are programmed by the 10.4.7 POWER-ON RESETS (PORs) DSWDPS<4:0> Configuration bits (CW4<4:0>). The minimum time-out period that can be achieved is 1ms VDD voltage is monitored to produce PORs. Since and the maximum is 25.7 days. For more details on the exiting from Deep Sleep mode functionally looks like a CW4 Configuration register and DSWDT configuration POR, the technique described in Section10.4.6 options, refer to Section29.0 “Special Features”. “Checking and Clearing the Status of Deep Sleep” should be used to distinguish between Deep Sleep and 10.4.5.1 Switching Clocks in Deep Sleep a true POR event. When a true POR occurs, the entire Mode device, including all Deep Sleep logic (Deep Sleep registers, RTCC, DSWDT, etc.) are reset. Both the RTCC and the DSWDT may run from either SOSC or the LPRC clock source. This allows both the RTCC and DSWDT to run without requiring both the 10.5 VBAT Mode LPRC and SOSC to be enabled together, reducing This mode represents the lowest power state that the power consumption. microcontroller can achieve and still resume operation. Running the RTCC from LPRC will result in a loss of VBAT mode is automatically triggered when the micro- accuracy in the RTCC, of approximately 5 to 10%. If a controller’s main power supply on VDD fails. When this more accurate RTCC is required, it must be run from the happens, the microcontroller’s on-chip power switch SOSC clock source. The RTCC clock source is selected connects to a backup power source, such as a battery, with the RTCLK<1:0> bits (RTCPWC<11:10>). supplied to the VBAT pin. This maintains a few key Under certain circumstances, it is possible for the systems at an extremely low-power draw until VDD is restored. DSWDT clock source to be off when entering Deep Sleep mode. In this case, the clock source is turned on The power supplied on VBAT only runs two systems: the automatically (if DSWDT is enabled), without the need RTCC and the Deep Sleep Semaphore registers for software intervention. However, this can cause a (DSGPR0 and DSGPR1). To maintain these systems delay in the start of the DSWDT counters. In order to during a sudden loss of VDD, it is essential to connect a avoid this delay when using SOSC as a clock source, power source, other than VDD or AVDD, to the VBAT pin. the application can activate SOSC prior to entering Deep Sleep mode. DS30009996G-page 160  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY When the RTCC is enabled, it continues to operate with With VBPOR set, the user should clear it, and the next the same clock source (SOSC or LPRC) that was time, this bit will only set when VDD = 0 and the VBAT selected prior to entering VBAT mode. There is no pro- pin has gone below level VBTRST. vision to switch to a lower power clock source after the mode switch. 10.5.3 I/O PINS DURING VBAT MODES Since the loss of VDD is usually an unforeseen event, it All I/O pins should be maintained at VSS level; no I/O is recommended that the contents of the Deep Sleep pins should be given VDD (refer to “Absolute Maximum Semaphore registers be loaded with the data to be Ratings” in Section32.0 “Electrical Characteris- retained at an early point in code execution. tics”) during VBAT mode. The only exceptions are the SOSCI and SOSCO pins, which maintain their states if 10.5.1 VBAT MODE WITH NO RTCC the Secondary Oscillator is being used as the RTCC clock source. It is the user’s responsibility to restore the By disabling RTCC operation during VBAT mode, power I/O pins to their proper states, using the TRISx and LATx consumption is reduced to the lowest of all power-saving modes. In this mode, only the Deep bits, once VDD has been restored. Sleep Semaphore registers are maintained. 10.5.4 SAVING CONTEXT DATA WITH THE 10.5.2 WAKE-UP FROM VBAT MODES DSGPRx REGISTERS When VDD is restored to a device in VBAT mode, it auto- As with Deep Sleep mode, all SFRs are reset to their matically wakes. Wake-up occurs with a POR, after POR values after VDD has been restored. Only the which the device starts executing code from the Reset Deep Sleep Semaphore registers are preserved. Appli- vector. All SFRs, except the Deep Sleep Semaphores cations which require critical data to be saved should and RTCC registers are reset to their POR values. If save it in DSGPR0 and DSGPR1. the RTCC was not configured to run during VBAT mode, Note: If the VBAT mode is not used, the it will remain disabled and RTCC will not run. Wake-up recommendation is to connect the VBAT timing is similar to that for a normal POR. pin to VDD and connect a 0.1 μF capacitor To differentiate a wake-up from VBAT mode from other close to the VBAT pin to ground. POR states, check the VBAT status bit (RCON2<0>). If When the VBAT mode is used (connected this bit is set while the device is starting to execute the to the battery), it is suggested to connect code from Reset vector, it indicates that there has been a 0.1 μF capacitor from the VBAT pin to an exit from VBAT mode. The application must clear the ground. The capacitor should be located VBAT bit to ensure that future VBAT wake-up events are very close to the VBAT pin. captured. The BOR should be enabled for the reliable operation If a POR occurs without a power source connected to of the VBAT. the VBAT pin, the VBPOR bit (RCON2<1>) is set. If this bit is set on a POR, it indicates that a battery needs to be connected to the VBAT pin. In addition, if the VBAT power source falls below the level needed for Deep Sleep Semaphore operation while in VBAT mode (e.g., the battery has been drained), the VBPOR bit will be set. VBPOR is also set when the microcontroller is powered up the very first time, even if power is supplied to VBAT.  2010-2014 Microchip Technology Inc. DS30009996G-page 161

PIC24FJ128GA310 FAMILY REGISTER 10-1: DSCON: DEEP SLEEP CONTROL REGISTER(1) R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 DSEN — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 r-0 R/W-0 R/C-0, HS — — — — — r DSBOR(2) RELEASE bit 7 bit 0 Legend: C = Clearable bit U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HS = Hardware Settable bit r = Reserved bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DSEN: Deep Sleep Enable bit 1 = Enters Deep Sleep on execution of PWRSAV #0 0 = Enters normal Sleep on execution of PWRSAV #0 bit 14-3 Unimplemented: Read as ‘0’ bit 2 Reserved: Maintain as ‘0’ bit 1 DSBOR: Deep Sleep BOR Event bit(2) 1 = The DSBOR was active and a BOR event was detected during Deep Sleep 0 = The DSBOR was not active or was active but did not detect a BOR event during Deep Sleep bit 0 RELEASE: I/O Pin State Release bit 1 = Upon waking from Deep Sleep, I/O pins maintain their states previous to Deep Sleep entry 0 = Releases I/O pins from their state previous to Deep Sleep entry, and allows their respective TRISx and LATx bits to control their states Note 1: All register bits are reset only in the case of a POR event outside of Deep Sleep mode. 2: Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this re-arms POR. DS30009996G-page 162  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 10-2: DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS — — — — — — — DSINT0 bit 15 bit 8 R/W-0, HS U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS U-0 U-0 DSFLT — — DSWDT DSRTCC DSMCLR — — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 DSINT0: Deep Sleep Interrupt-on-Change bit 1 = Interrupt-on-change was asserted during Deep Sleep 0 = Interrupt-on-change was not asserted during Deep Sleep bit 7 DSFLT: Deep Sleep Fault Detected bit 1 = A Fault occurred during Deep Sleep and some Deep Sleep configuration settings may have been corrupted 0 = No Fault was detected during Deep Sleep bit 6-5 Unimplemented: Read as ‘0’ bit 4 DSWDT: Deep Sleep Watchdog Timer Time-out bit 1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep 0 = The Deep Sleep Watchdog Timer did not time out during Deep Sleep bit 3 DSRTCC: Real-Time Clock and Calendar Alarm bit 1 = The Real-Time Clock and Calendar triggered an alarm during Deep Sleep 0 = The Real-Time Clock and Calendar did not trigger an alarm during Deep Sleep bit 2 DSMCLR: MCLR Event bit 1 = The MCLR pin was active and was asserted during Deep Sleep 0 = The MCLR pin was not active, or was active, but not asserted during Deep Sleep bit 1-0 Unimplemented: Read as ‘0’ Note 1: All register bits are cleared when the DSEN (DSCON<15>) bit is set.  2010-2014 Microchip Technology Inc. DS30009996G-page 163

PIC24FJ128GA310 FAMILY REGISTER 10-3: RCON2: RESET AND SYSTEM CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 r-0 R/CO-1 R/CO-1 R/CO-1 R/CO-0 — — — r VDDBOR(1) VDDPOR(1,2) VBPOR(1,3) VBAT(1) bit 7 bit 0 Legend: CO = Clearable Only bit r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4 Reserved: Maintain as ‘0’ bit 3 VDDBOR: VDD Brown-out Reset Flag bit(1) 1 = A VDD Brown-out Reset has occurred (set by hardware) 0 = A VDD Brown-out Reset has not occurred bit 2 VDDPOR: VDD Power-On Reset Flag bit(1,2) 1 = A VDD Power-on Reset has occurred (set by hardware) 0 = A VDD Power-on Reset has not occurred bit 1 VBPOR: VBPOR Flag bit(1,3) 1 = A VBAT POR has occurred (no battery connected to the VBAT pin, or VBAT power below Deep Sleep Semaphore retention level, set by hardware) 0 = A VBAT POR has not occurred bit 0 VBAT: VBAT Flag bit(1) 1 = A POR exit has occurred while power was applied to the VBAT pin (set by hardware) 0 = A POR exit from VBAT has not occurred Note 1: This bit is set in hardware only; it can only be cleared in software. 2: Indicates a VDD POR. Setting the POR bit (RCON<0>) indicates a VCORE POR. 3: This bit is set when the device is originally powered up, even if power is present on VBAT. It is recom- mended that the user clear this flag, and the next time, this bit will only set when the VBAT voltage goes below 0.4-0.6V with VDD = 0. DS30009996G-page 164  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 10.6 Clock Frequency and Clock 10.8 Selective Peripheral Module Switching Control In Run and Idle modes, all PIC24FJ devices allow for a Idle and Doze modes allow users to substantially wide range of clock frequencies to be selected under reduce power consumption by slowing or stopping the application control. If the system clock configuration is CPU clock. Even so, peripheral modules still remain not locked, users can choose low-power or clocked, and thus, consume power. There may be high-precision oscillators by simply changing the cases where the application needs what these modes NOSCx bits. The process of changing a system clock do not provide: the allocation of power resources to during operation, as well as limitations to the pro- CPU processing with minimal power consumption from cess, are discussed in more detail in Section9.0 the peripherals. “Oscillator Configuration”. PIC24F devices address this requirement by allowing peripheral modules to be selectively disabled, reducing 10.7 Doze Mode or eliminating their power consumption. This can be done with two control bits: Generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies • The Peripheral Enable bit, generically named, for reducing power consumption. There may be “XXXEN”, located in the module’s main control circumstances, however, where this is not practical. For SFR. example, it may be necessary for an application to • The Peripheral Module Disable (PMD) bit, maintain uninterrupted synchronous communication, generically named, “XXXMD”, located in one of even while it is doing nothing else. Reducing system the PMD Control registers (XXXMD bits are in clock speed may introduce communication errors, PMD1, PMD2, PMD3, PMD4, PMD6, PMD7 while using a power-saving mode may stop registers). communications completely. Both bits have similar functions in enabling or disabling Doze mode is a simple and effective alternative method its associated module. Setting the PMD bit for a module to reduce power consumption while the device is still disables all clock sources to that module, reducing its executing code. In this mode, the system clock power consumption to an absolute minimum. In this continues to operate from the same source and at the state, the control and status registers associated with same speed. Peripheral modules continue to be the peripheral will also be disabled, so writes to those clocked at the same speed while the CPU clock speed registers will have no effect and read values will be is reduced. Synchronization between the two clock invalid. Many peripheral modules have a corresponding domains is maintained, allowing the peripherals to PMD bit. access the SFRs while the CPU executes code at a In contrast, disabling a module by clearing its XXXEN slower rate. bit disables its functionality, but leaves its registers Doze mode is enabled by setting the DOZEN bit available to be read and written to. Power consumption (CLKDIV<11>). The ratio between peripheral and core is reduced, but not by as much as the PMD bits are clock speed is determined by the DOZE<2:0> bits used. Most peripheral modules have an enable bit; (CLKDIV<14:12>). There are eight possible exceptions include capture, compare and RTCC. configurations, from 1:1 to 1:128, with 1:1 being the To achieve more selective power savings, peripheral default. modules can also be selectively disabled when the It is also possible to use Doze mode to selectively reduce device enters Idle mode. This is done through the control power consumption in event driven applications. This bit of the generic name format, “XXXIDL”. By default, all allows clock-sensitive functions, such as synchronous modules that can operate during Idle mode will do so. communications, to continue without interruption while Using the disable on Idle feature disables the module the CPU Idles, waiting for something to invoke an while in Idle mode, allowing further reduction of power interrupt routine. Enabling the automatic return to consumption during Idle mode, enhancing power full-speed CPU operation on interrupts is enabled by set- savings for extremely critical power applications. ting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation.  2010-2014 Microchip Technology Inc. DS30009996G-page 165

PIC24FJ128GA310 FAMILY NOTES: DS30009996G-page 166  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 11.0 I/O PORTS When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as Note: This data sheet summarizes the features of a general purpose output pin is disabled. The I/O pin this group of PIC24F devices. It is not may be read, but the output driver for the parallel port intended to be a comprehensive reference bit will be disabled. If a peripheral is enabled, but the source. For more information, refer to “I/O peripheral is not actively driving a pin, that pin may be Ports with Peripheral Pin Select (PPS)” driven by a port. (DS39711) in the “dsPIC33/PIC24 Family All port pins have three registers directly associated Reference Manual”. The information in this with their operation as digital I/Os and one register data sheet supersedes the information in associated with their operation as analog inputs. The the FRM. Data Direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a All of the device pins (except VDD, VSS, MCLR and ‘1’, then the pin is an input. All port pins are defined as OSCI/CLKI) are shared between the peripherals and inputs after a Reset. Reads from the Output Latch reg- the parallel I/O ports. All I/O input ports feature Schmitt ister (LATx), read the latch; writes to the latch, write the Trigger (ST) inputs for improved noise immunity. latch. Reads from the port (PORTx), read the port pins; writes to the port pins, write the latch. 11.1 Parallel I/O (PIO) Ports Any bit and its associated data and control registers A Parallel I/O port that shares a pin with a peripheral is, that are not valid for a particular device will be in general, subservient to the peripheral. The peripheral’s disabled. That means the corresponding LATx and output buffer data and control signals are provided to a TRISx registers, and the port pin will read as zeros. pair of multiplexers. The multiplexers select whether the When a pin is shared with another peripheral or func- peripheral or the associated port has ownership of the tion that is defined as an input only, it is regarded as a output data and control signals of the I/O pin. The logic dedicated port because there is no other competing also prevents “loop through”, in which a port’s digital out- source of inputs. RC13 and RC14 can be input ports put can drive the input of a peripheral that shares the only; they cannot be configured as outputs. same pin. Figure11-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. FIGURE 11-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable I/O Peripheral Output Enable 1 Output Enable Peripheral Output Data 0 PIO Module 1 Output Data Read TRIS 0 Data Bus D Q I/O Pin WR TRIS CK TRIS Latch D Q WR LAT + CK WR PORT Data Latch Read LAT Input Data Read PORT  2010-2014 Microchip Technology Inc. DS30009996G-page 167

PIC24FJ128GA310 FAMILY 11.1.1 I/O PORT WRITE/READ TIMING 11.2 Configuring Analog Port Pins (ANSx) One instruction cycle is required between a port direction change or port write operation and a read operation of The ANSx and TRISx registers control the operation of the same port. Typically, this instruction would be a NOP. the pins with analog function. Each port pin with analog function is associated with one of the ANSx bits (see 11.1.2 OPEN-DRAIN CONFIGURATION Register11-1 through Register11-6), which decides if In addition to the PORTx, LATx and TRISx registers for the pin function should be analog or digital. Refer to data control, each port pin can also be individually Table11-1 for detailed behavior of the pin for different configured for either a digital or open-drain output. This ANSx and TRISx bit settings. is controlled by the Open-Drain Control register, ODCx, When reading the PORTx register, all pins configured as associated with each port. Setting any of the bits config- analog input channels will read as cleared (a low level). ures the corresponding pin to act as an open-drain output. 11.2.1 ANALOG INPUT PINS AND The open-drain feature allows the generation of VOLTAGE CONSIDERATIONS outputs higher than VDD (e.g., 5V) on any desired The voltage tolerance of pins used as device inputs is digital only pins by using external pull-up resistors. The dependent on the pin’s input function. Most input pins are maximum open-drain voltage allowed is the same as able to handle DC voltages of up to 5.5V, a level typical the maximum VIH specification. for digital logic circuits. However, several pins can only tolerate voltages up to VDD. Voltage excursions beyond VDD on these pins should always be avoided. Table11-2 summarizes the different voltage tolerances. Refer to Section32.0 “Electrical Characteristics” for more details. TABLE 11-1: CONFIGURING ANALOG/DIGITAL FUNCTION OF AN I/O PIN Pin Function ANSx Setting TRISx Setting Comments Analog Input 1 1 It is recommended to keep ANSx = 1. Analog Output 1 1 It is recommended to keep ANSx = 1. Digital Input 0 1 Firmware must wait at least one instruction cycle after configuring a pin as a digital input before a valid input value can be read. Digital Output 0 0 Make sure to disable the analog output function on the pin if any is present. TABLE 11-2: INPUT VOLTAGE LEVELS FOR PORT OR PIN TOLERATED DESCRIPTION INPUT Port or Pin Tolerated Input Description PORTA<15:14, 7:0>(1) PORTB<15:7, 5:2> PORTC<3:1>(1) PORTD<15:8, 5:0>(1) 5.5V Tolerates input levels above VDD; useful for most standard logic. PORTE<9:8, 4:0>(1) PORTF<13:12, 8:0>(1) PORTG<15:12, 9, 6:0>(1) PORTA<10:9>(1) PORTB<6, 1:0> PORTC<15:12, 4>(1) VDD Only VDD input levels are tolerated. PORTD<7:6> PORTE<7:5>(1) PORTG<8:7> Note 1: Not all of these pins are implemented on 64-pin or 80-pin devices. Refer to Section1.0 “Device Overview” for a complete description of port pin implementation. DS30009996G-page 168  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 11-1: ANSA: PORTA ANALOG FUNCTION SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 U-0 — — — — — ANSA<10:9>(2) — bit 15 bit 8 R/W-1 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0 ANSA<7:6>(1) — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 ANSA<10:9>: Analog Function Selection bits(2) 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled bit 7-6 ANSA<7:6>: Analog Function Selection bits(1) 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled bit 5-0 Unimplemented: Read as ‘0’ Note 1: These bits are not available in 64-pin and 80-pin devices. 2: These bits are not available in 64-pin devices. REGISTER 11-2: ANSB: PORTB ANALOG FUNCTION SELECTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANSB<15:8> bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANSB<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 ANSB<15:0>: Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled  2010-2014 Microchip Technology Inc. DS30009996G-page 169

PIC24FJ128GA310 FAMILY REGISTER 11-3: ANSC: PORTC ANALOG FUNCTION SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 U-0 U-0 U-0 U-0 — — — ANSC4(1) — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4 ANSC4: Analog Function Selection bit(1) 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled bit 3-0 Unimplemented: Read as ‘0’ Note 1: This bit is not available in 64-pin and 80-pin devices. REGISTER 11-4: ANSD: PORTD ANALOG FUNCTION SELECTION REGISTER U-0 U-0 U-0 U-0 R/W-1 R/W-1 U-0 U-0 — — — — ANSD<11:10> — — bit 15 bit 8 R/W-1 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0 ANSD<7:6> — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11 ANSD<11:10>: Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled bit 9-8 Unimplemented: Read as ‘0’ bit 7-6 ANSD<7:6>: Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled bit 5-0 Unimplemented: Read as ‘0’ DS30009996G-page 170  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 11-5: ANSE: PORTE ANALOG FUNCTION SELECTION REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 U-0 — — — — — — ANSE9(2) — bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0 ANSE<7:4> — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9 ANSE9: Analog Function Selection bit(2) 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled bit 8 Unimplemented: Read as ‘0’ bit 7-4 ANSE<7:4>: Analog Function Selection bits(1) 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled bit 3-0 Unimplemented: Read as ‘0’ Note 1: This register is not available in 64-pin and 80-pin devices. 2: This bit is unimplemented on 64-pin devices. In 80-pin devices, this bit needs to be cleared to get digital functionality on RE9. REGISTER 11-6: ANSG: PORTG ANALOG FUNCTION SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 — — — — — — ANSG<9:8> bit 15 bit 8 R/W-1 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0 ANSG<7:6> — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-6 ANSG<9:6>: Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled bit 5-0 Unimplemented: Read as ‘0’  2010-2014 Microchip Technology Inc. DS30009996G-page 171

PIC24FJ128GA310 FAMILY 11.3 Input Change Notification Each CN pin has both a weak pull-up and a weak pull-down connected to it. The pull-ups act as a current The Input Change Notification (ICN) function of the I/O source that is connected to the pin, while the ports allows the PIC24FJ128GA310 family of devices pull-downs act as a current sink that is connected to the to generate interrupt requests to the processor in pin. These eliminate the need for external resistors response to a Change-of-State (COS) on selected when push button or keypad devices are connected. input pins. This feature is capable of detecting input The pull-ups and pull-downs are separately enabled Change-of-States, even in Sleep mode when the using the CNPU1 through CNPU6 registers (for clocks are disabled. Depending on the device pin pull-ups) and the CNPD1 through CNPD6 registers (for count, there are up to 82 external inputs that may be pull-downs). Each CN pin has individual control bits for selected (enabled) for generating an interrupt request its pull-up and pull-down. Setting a control bit enables on a Change-of-State. the weak pull-up or pull-down for the corresponding Registers, CNEN1 through CNEN6, contain the pin. interrupt enable control bits for each of the Change When the internal pull-up is selected, the pin pulls up to Notification (CN) input pins. Setting any of these bits VDD – 1.1V (typical). When the internal pull-down is enables a CN interrupt for the corresponding pins. selected, the pin pulls down to VSS. Note: Pull-ups on Change Notification pins should always be disabled whenever the port pin is configured as a digital output. EXAMPLE 11-1: PORT WRITE/READ IN ASSEMBLY MOV 0xFF00, W0 ; Configure PORTB<15:8> as inputs MOV W0, TRISB ; and PORTB<7:0> as outputs NOP ; Delay 1 cycle BTSS PORTB, #13 ; Next Instruction EXAMPLE 11-2: PORT WRITE/READ IN ‘C’ TRISB = 0xFF00; // Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs Nop(); // Delay 1 cycle If (PORTBbits.RB13){ }; // Next Instruction DS30009996G-page 172  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 11.4 Peripheral Pin Select (PPS) PPS is not available for these peripherals: • I2C™ (input and output) A major challenge in general purpose devices is provid- ing the largest possible set of peripheral features while • Change Notification inputs minimizing the conflict of features on I/O pins. In an • RTCC alarm output(s) application that needs to use more than one peripheral • EPMP signals (input and output) multiplexed on a single pin, inconvenient work arounds • LCD signals in application code, or a complete redesign, may be the • Analog inputs only option. • INT0 The Peripheral Pin Select (PPS) feature provides an A key difference between pin select and non-pin select alternative to these choices by enabling the user’s peripherals is that pin select peripherals are not asso- peripheral set selection and its placement on a wide ciated with a default I/O pin. The peripheral must range of I/O pins. By increasing the pinout options always be assigned to a specific I/O pin before it can be available on a particular device, users can better tailor used. In contrast, non-pin select peripherals are always the microcontroller to their entire application, rather available on a default pin, assuming that the peripheral than trimming the application to fit the device. is active and not conflicting with another peripheral. The Peripheral Pin Select feature operates over a fixed subset of digital I/O pins. Users may independently 11.4.2.1 Peripheral Pin Select Function map the input and/or output of any one of many digital Priority peripherals to any one of these I/O pins. PPS is per- Pin-selectable peripheral outputs (e.g., OCx, UARTx formed in software and generally does not require the transmit) will take priority over general purpose digital device to be reprogrammed. Hardware safeguards are functions on a pin, such as EPMP and port I/O. Special- included that prevent accidental or spurious changes to ized digital outputs (e.g., USB on USB-enabled the peripheral mapping once it has been established. devices) will take priority over PPS outputs on the same 11.4.1 AVAILABLE PINS pin. The pin diagrams list peripheral outputs in the order of priority. Refer to them for priority concerns on The PPS feature is used with a range of up to 44 pins, a particular pin. depending on the particular device and its pin count. Pins that support the Peripheral Pin Select feature Unlike PIC24F devices with fixed peripherals, include the designation, “RPn” or “RPIn”, in their full pin pin-selectable peripheral inputs will never take owner- designation, where “n” is the remappable pin number. ship of a pin. The pin’s output buffer will be controlled “RP” is used to designate pins that support both remap- by the TRISx setting or by a fixed peripheral on the pin. pable input and output functions, while “RPI” indicates If the pin is configured in Digital mode then the PPS pins that support remappable input functions only. input will operate correctly. If an analog function is enabled on the pin, the PPS input will be disabled. PIC24FJ128GA310 family devices support a larger number of remappable input only pins than remappable 11.4.3 CONTROLLING PERIPHERAL PIN input/output pins. In this device family, there are up to SELECT 32 remappable input/output pins, depending on the pin count of the particular device selected. These pins are PPS features are controlled through two sets of Special numbered, RP0 through RP31. Remappable input only Function Registers (SFRs): one to map peripheral pins are numbered above this range, from RPI32 to inputs and one to map outputs. Because they are RPI43 (or the upper limit for that particular device). separately controlled, a particular peripheral’s input and output (if the peripheral has both) can be placed on See Table1-4 for a summary of pinout options in each any selectable function pin without constraint. package offering. The association of a peripheral to a peripheral-selectable 11.4.2 AVAILABLE PERIPHERALS pin is handled in two different ways, depending on if an input or an output is being mapped. The peripherals managed by the PPS are all digital only peripherals. These include general serial commu- nications (UART and SPI), general purpose timer clock inputs, timer related peripherals (input capture and out- put compare) and external interrupt inputs. Also included are the outputs of the comparator module, since these are discrete digital signals.  2010-2014 Microchip Technology Inc. DS30009996G-page 173

PIC24FJ128GA310 FAMILY 11.4.3.1 Input Mapping Each register contains two sets of 6-bit fields, with each set associated with one of the pin-selectable peripher- The inputs of the Peripheral Pin Select options are als. Programming a given peripheral’s bit field, with an mapped on the basis of the peripheral; that is, a control appropriate 6-bit value, maps the RPn/RPIn pin with register associated with a peripheral dictates the pin it that value to that peripheral. For any given device, the will be mapped to. The RPINRx registers are used to valid range of values for any of the bit fields corre- configure peripheral input mapping (see Register11-7 sponds to the maximum number of Peripheral Pin through Register11-26). Selections supported by the device. TABLE 11-3: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1) Function Mapping Input Name Function Name Register Bits DSM Modulation Input MDMIN RPINR30 MDMIR<5:0> DSM Carrier 1 Input MDCIN1 RPINR31 MDC1R<5:0> DSM Carrier 2 Input MDCIN2 RPINR31 MDC2R<5:0> External Interrupt 1 INT1 RPINR0 INT1R<5:0> External Interrupt 2 INT2 RPINR1 INT2R<5:0> External Interrupt 3 INT3 RPINR1 INT3R<5:0> External Interrupt 4 INT4 RPINR2 INT4R<5:0> Input Capture 1 IC1 RPINR7 IC1R<5:0> Input Capture 2 IC2 RPINR7 IC2R<5:0> Input Capture 3 IC3 RPINR8 IC3R<5:0> Input Capture 4 IC4 RPINR8 IC4R<5:0> Input Capture 5 IC5 RPINR9 IC5R<5:0> Input Capture 6 IC6 RPINR9 IC6R<5:0> Input Capture 7 IC7 RPINR10 IC7R<5:0> Output Compare Fault A OCFA RPINR11 OCFAR<5:0> Output Compare Fault B OCFB RPINR11 OCFBR<5:0> SPI1 Clock Input SCK1IN RPINR20 SCK1R<5:0> SPI1 Data Input SDI1 RPINR20 SDI1R<5:0> SPI1 Slave Select Input SS1IN RPINR21 SS1R<5:0> SPI2 Clock Input SCK2IN RPINR22 SCK2R<5:0> SPI2 Data Input SDI2 RPINR22 SDI2R<5:0> SPI2 Slave Select Input SS2IN RPINR23 SS2R<5:0> Timer1 External Clock T1CK RPINR23 T1CKR<5:0> Timer2 External Clock T2CK RPINR3 T2CKR<5:0> Timer3 External Clock T3CK RPINR3 T3CKR<5:0> Timer4 External Clock T4CK RPINR4 T4CKR<5:0> Timer5 External Clock T5CK RPINR4 T5CKR<5:0> UART1 Clear-to-Send U1CTS RPINR18 U1CTSR<5:0> UART1 Receive U1RX RPINR18 U1RXR<5:0> UART2 Clear-to-Send U2CTS RPINR19 U2CTSR<5:0> UART2 Receive U2RX RPINR19 U2RXR<5:0> UART3 Clear-to-Send U3CTS RPINR21 U3CTSR<5:0> UART3 Receive U3RX RPINR17 U3RXR<5:0> UART4 Clear-to-Send U4CTS RPINR27 U4CTSR<5:0> UART4 Receive U4RX RPINR27 U4RXR<5:0> Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger (ST) input buffers. DS30009996G-page 174  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 11.4.3.2 Output Mapping corresponds to one of the peripherals and that peripheral’s output is mapped to the pin (see In contrast to inputs, the outputs of the Peripheral Pin Table11-4). Select options are mapped on the basis of the pin. In this case, a control register associated with a particular Because of the mapping technique, the list of peripher- pin dictates the peripheral output to be mapped. The als for output mapping also includes a null value of RPORx registers are used to control output mapping. ‘000000’. This permits any given pin to remain discon- Each register contains two 6-bit fields, with each field nected from the output of any of the pin-selectable being associated with one RPn pin (see Register11-27 peripherals. through Register11-42). The value of the bit field TABLE 11-4: SELECTABLE OUTPUT SOURCES (MAPS FUNCTION TO OUTPUT) Output Function Number(1) Function Output Name 0 NULL(2) Null 1 C1OUT Comparator 1 Output 2 C2OUT Comparator 2 Output 3 U1TX UART1 Transmit 4 U1RTS(3) UART1 Request-to-Send 5 U2TX UART2 Transmit 6 U2RTS(3) UART2 Request-to-Send 7 SDO1 SPI1 Data Output 8 SCK1OUT SPI1 Clock Output 9 SS1OUT SPI1 Slave Select Output 10 SDO2 SPI2 Data Output 11 SCK2OUT SPI2 Clock Output 12 SS2OUT SPI2 Slave Select Output 18 OC1 Output Compare 1 19 OC2 Output Compare 2 20 OC3 Output Compare 3 21 OC4 Output Compare 4 22 OC5 Output Compare 5 23 OC6 Output Compare 6 24 OC7 Output Compare 7 28 U3TX UART3 Transmit 29 U3RTS(3) UART3 Request-to-Send 30 U4TX UART4 Transmit 31 U4RTS(3) UART4 Request-to-Send 36 C3OUT Comparator 3 Output 37 MDOUT DSM Modulator Output 38-63 (unused) NC Note 1: Setting the RPORx register with the listed value assigns that output function to the associated RPn pin. 2: The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function. 3: IrDA® BCLK functionality uses this output.  2010-2014 Microchip Technology Inc. DS30009996G-page 175

PIC24FJ128GA310 FAMILY 11.4.3.3 Mapping Limitations 11.4.4.1 Control Register Lock The control schema of the Peripheral Pin Select is Under normal operation, writes to the RPINRx and extremely flexible. Other than systematic blocks that RPORx registers are not allowed. Attempted writes will prevent signal contention, caused by two physical pins appear to execute normally, but the contents of the being configured as the same functional input or two registers will remain unchanged. To change these reg- functional outputs configured as the same pin, there isters, they must be unlocked in hardware. The register are no hardware enforced lock outs. The flexibility lock is controlled by the IOLOCK bit (OSCCON<6>). extends to the point of allowing a single input to drive Setting IOLOCK prevents writes to the control multiple peripherals or a single functional output to registers; clearing IOLOCK allows writes. drive multiple output pins. To set or clear IOLOCK, a specific command sequence must be executed: 11.4.3.4 Mapping Exceptions for PIC24FJ128GA310 Family Devices 1. Write 46h to OSCCON<7:0>. 2. Write 57h to OSCCON<7:0>. Although the PPS registers theoretically allow for up to 64 remappable I/O pins, not all of these are imple- 3. Clear (or set) IOLOCK as a single operation. mented in all devices. For PIC24FJ128GA310 family Unlike the similar sequence with the oscillator’s LOCK devices, the maximum number of remappable pins bit, IOLOCK remains in one state until changed. This available is 44, which includes 12 input only pins. In allows all of the Peripheral Pin Selects to be configured addition, some pins in the RPn and RPIn sequences with a single unlock sequence, followed by an update are unimplemented in lower pin count devices. The to all control registers, then locked with a second lock differences in available remappable pins are sequence. summarized in Table11-5. 11.4.4.2 Continuous State Monitoring When developing applications that use remappable pins, users should also keep these things in mind: In addition to being protected from direct writes, the contents of the RPINRx and RPORx registers are • For the RPINRx registers, bit combinations corre- constantly monitored in hardware by shadow registers. sponding to an unimplemented pin for a particular If an unexpected change in any of the registers occurs device are treated as invalid; the corresponding (such as cell disturbances caused by ESD or other module will not have an input mapped to it. For all external events), a Configuration Mismatch Reset will PIC24FJ128GA310 family devices, this includes be triggered. all values greater than 43 (‘101011’). • For RPORx registers, the bit fields corresponding 11.4.4.3 Configuration Bit Pin Select Lock to an unimplemented pin will also be As an additional level of safety, the device can be con- unimplemented. Writing to these fields will have figured to prevent more than one write session to the no effect. RPINRx and RPORx registers. The IOL1WAY 11.4.4 CONTROLLING CONFIGURATION (CW2<4>) Configuration bit blocks the IOLOCK bit CHANGES from being cleared after it has been set once. If IOLOCK remains set, the register unlock procedure will Because peripheral remapping can be changed during not execute and the Peripheral Pin Select Control reg- run time, some restrictions on peripheral remapping isters cannot be written to. The only way to clear the bit are needed to prevent accidental configuration and re-enable peripheral remapping is to perform a changes. PIC24F devices include three features to device Reset. prevent alterations to the peripheral map: In the default (unprogrammed) state, IOL1WAY is set, • Control register lock sequence restricting users to one write session. Programming • Continuous state monitoring IOL1WAY allows users unlimited access (with the • Configuration bit remapping lock proper use of the unlock sequence) to the Peripheral Pin Select registers. TABLE 11-5: REMAPPABLE PIN EXCEPTIONS FOR PIC24FJ128GA310 FAMILY DEVICES RP Pins (I/O) RPI Pins Device Total Unimplemented Total Unimplemented PIC24FJXXXGA306 29 RP5, RP15, RP31 1 RPI32-36, RPI38-43 PIC24FJXXXGA308 31 — 9 RPI32, RPI39, RPI41 PIC24FJXXXGA310 32 — 12 — DS30009996G-page 176  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 11.4.5 CONSIDERATIONS FOR Along these lines, configuring a remappable pin for a PERIPHERAL PIN SELECTION specific peripheral does not automatically turn that feature on. The peripheral must be specifically config- The ability to control Peripheral Pin Selection intro- ured for operation, and enabled as if it were tied to a duces several considerations into application design fixed pin. Where this happens in the application code that could be overlooked. This is particularly true for (immediately following device Reset and peripheral con- several common peripherals that are available only as figuration, or inside the main application routine) remappable peripherals. depends on the peripheral and its use in the application. The main consideration is that the Peripheral Pin A final consideration is that Peripheral Pin Select func- Selects are not available on default pins in the device’s tions neither override analog inputs nor reconfigure default (Reset) state. Since all RPINRx registers reset pins with analog functions for digital I/O. If a pin is to ‘111111’ and all RPORx registers reset to ‘000000’, configured as an analog input on device Reset, it must all Peripheral Pin Select inputs are tied to VSS and all be explicitly reconfigured as digital I/O when used with Peripheral Pin Select outputs are disconnected. a Peripheral Pin Select. Note: In tying Peripheral Pin Select inputs to Example11-3 shows a configuration for bidirectional RP63, RP63 need not exist on a device for communication with flow control using UART1. The the registers to be reset to it. following input and output functions are used: This situation requires the user to initialize the device • Input Functions: U1RX, U1CTS with the proper peripheral configuration before any • Output Functions: U1TX, U1RTS other application code is executed. Since the IOLOCK bit resets in the unlocked state, it is not necessary to EXAMPLE 11-3: CONFIGURING UART1 execute the unlock sequence after the device has INPUT AND OUTPUT come out of Reset. For application safety, however, it is FUNCTIONS best to set IOLOCK and lock the configuration after writing to the control registers. // Unlock Registers asm volatile( "MOV #OSCCON, w1 \n" Because the unlock sequence is timing-critical, it must "MOV #0x46, w2 \n" be executed as an assembly language routine in the "MOV #0x57, w3 \n" same manner as changes to the oscillator configura- "MOV.b w2, [w1] \n" tion. If the bulk of the application is written in ‘C’, or "MOV.b w3, [w1] \n" another high-level language, the unlock sequence "BCLR OSCCON,#6") ; should be performed by writing in-line assembly. // or use C30 built-in macro: Choosing the configuration requires the review of all // __builtin_write_OSCCONL(OSCCON & 0xbf); Peripheral Pin Selects and their pin assignments, especially those that will not be used in the application. // Configure Input Functions (Table11-2)) In all cases, unused pin-selectable peripherals should // Assign U1RX To Pin RP0 be disabled completely. Unused peripherals should RPINR18bits.U1RXR = 0; have their inputs assigned to an unused RPn/RPIn pin function. I/O pins with unused RPn functions should be // Assign U1CTS To Pin RP1 configured with the null peripheral output. RPINR18bits.U1CTSR = 1; The assignment of a peripheral to a particular pin does // Configure Output Functions (Table11-4) not automatically perform any other configuration of the // Assign U1TX To Pin RP2 pin’s I/O circuitry. In theory, this means adding a RPOR1bits.RP2R = 3; pin-selectable output to a pin may mean inadvertently driving an existing peripheral input when the output is // Assign U1RTS To Pin RP3 driven. Users must be familiar with the behavior of RPOR1bits.RP3R = 4; other fixed peripherals that share a remappable pin and // Lock Registers know when to enable or disable them. To be safe, fixed asm volatile ("MOV #OSCCON, w1 \n" digital peripherals that share the same pin should be "MOV #0x46, w2 \n" disabled when not in use. "MOV #0x57, w3 \n" "MOV.b w2, [w1]\n" "MOV.b w3, [w1]\n" "BSET OSCCON, #6" ; // or use C30 built-in macro: // __builtin_write_OSCCONL(OSCCON | 0x40);  2010-2014 Microchip Technology Inc. DS30009996G-page 177

PIC24FJ128GA310 FAMILY 11.4.6 PERIPHERAL PIN SELECT Note: Input and output register values can only REGISTERS be changed if IOLOCK (OSCCON<6>) = 0. The PIC24FJ128GA310 family of devices implements See Section11.4.4.1 “Control Register a total of 35 registers for remappable peripheral Lock” for a specific command sequence. configuration: • Input Remappable Peripheral Registers (20) • Output Remappable Peripheral Registers (16) REGISTER 11-7: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — INT1R5 INT1R4 INT1R3 INT1R2 INT1R1 INT1R0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 INT1R<5:0>: Assign External Interrupt 1 (INT1) to Corresponding RPn or RPIn Pin bits bit 7-0 Unimplemented: Read as ‘0’ REGISTER 11-8: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — INT3R5 INT3R4 INT3R3 INT3R2 INT3R1 INT3R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — INT2R5 INT2R4 INT2R3 INT2R2 INT2R1 INT2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 INT3R<5:0>: Assign External Interrupt 3 (INT3) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 INT2R<5:0>: Assign External Interrupt 2 (INT2) to Corresponding RPn or RPIn Pin bits DS30009996G-page 178  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 11-9: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — INT4R5 INT4R4 INT4R3 INT4R2 INT4R1 INT4R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 INT4R<5:0>: Assign External Interrupt 4 (INT4) to Corresponding RPn or RPIn Pin bits REGISTER 11-10: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T3CKR5 T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T2CKR5 T2CKR4 T2CKR3 T2CKR2 T2CKR1 T2CKR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 T3CKR<5:0>: Assign Timer3 External Clock (T3CK) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 T2CKR<5:0>: Assign Timer2 External Clock (T2CK) to Corresponding RPn or RPIn Pin bits  2010-2014 Microchip Technology Inc. DS30009996G-page 179

PIC24FJ128GA310 FAMILY REGISTER 11-11: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T5CKR5 T5CKR4 T5CKR3 T5CKR2 T5CKR1 T5CKR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T4CKR5 T4CKR4 T4CKR3 T4CKR2 T4CKR1 T4CKR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 T5CKR<5:0>: Assign Timer5 External Clock (T5CK) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 T4CKR<5:0>: Assign Timer4 External Clock (T4CK) to Corresponding RPn or RPIn Pin bits REGISTER 11-12: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC2R5 IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC1R5 IC1R4 IC1R3 IC1R2 IC1R1 IC1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 IC2R<5:0>: Assign Input Capture 2 (IC2) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IC1R<5:0>: Assign Input Capture 1 (IC1) to Corresponding RPn or RPIn Pin bits DS30009996G-page 180  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 11-13: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC4R5 IC4R4 IC4R3 IC4R2 IC4R1 IC4R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC3R5 IC3R4 IC3R3 IC3R2 IC3R1 IC3R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 IC4R<5:0>: Assign Input Capture 4 (IC4) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IC3R<5:0>: Assign Input Capture 3 (IC3) to Corresponding RPn or RPIn Pin bits REGISTER 11-14: RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC6R5 IC6R4 IC6R3 IC6R2 IC6R1 IC6R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC5R5 IC5R4 IC5R3 IC5R2 IC5R1 IC5R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 IC6R<5:0>: Assign Input Capture 6 (IC6) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IC5R<5:0>: Assign Input Capture 5 (IC5) to Corresponding RPn or RPIn Pin bits  2010-2014 Microchip Technology Inc. DS30009996G-page 181

PIC24FJ128GA310 FAMILY REGISTER 11-15: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC7R5 IC7R4 IC7R3 IC7R2 IC7R1 IC7R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 IC7R<5:0>: Assign Input Capture 7 (IC7) to Corresponding RPn or RPIn Pin bits REGISTER 11-16: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — OCFBR5 OCFBR4 OCFBR3 OCFBR2 OCFBR1 OCFBR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — OCFAR5 OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 OCFBR<5:0>: Assign Output Compare Fault B (OCFB) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 OCFAR<5:0>: Assign Output Compare Fault A (OCFA) to Corresponding RPn or RPIn Pin bits DS30009996G-page 182  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 11-17: RPINR17: PERIPHERAL PIN SELECT INPUT REGISTER 17 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U3RXR5 U3RXR4 U3RXR3 U3RXR2 U3RXR1 U3RXR0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U3RXR<5:0>: Assign UART3 Receive (U3RX) to Corresponding RPn or RPIn Pin bits bit 7-0 Unimplemented: Read as ‘0’ REGISTER 11-18: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U1RXR5 U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U1CTSR<5:0>: Assign UART1 Clear-to-Send (U1CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 U1RXR<5:0>: Assign UART1 Receive (U1RX) to Corresponding RPn or RPIn Pin bits  2010-2014 Microchip Technology Inc. DS30009996G-page 183

PIC24FJ128GA310 FAMILY REGISTER 11-19: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U2CTSR5 U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U2RXR5 U2RXR4 U2RXR3 U2RXR2 U2RXR1 U2RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U2CTSR<5:0>: Assign UART2 Clear-to-Send (U2CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 U2RXR<5:0>: Assign UART2 Receive (U2RX) to Corresponding RPn or RPIn Pin bits REGISTER 11-20: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SCK1R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SDI1R5 SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SCK1R<5:0>: Assign SPI1 Clock Input (SCK1IN) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SDI1R<5:0>: Assign SPI1 Data Input (SDI1) to Corresponding RPn or RPIn Pin bits DS30009996G-page 184  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 11-21: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U3CTSR5 U3CTSR4 U3CTSR3 U3CTSR2 U3CTSR1 U3CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SS1R5 SS1R4 SS1R3 SS1R2 SS1R1 SS1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U3CTSR<5:0>: Assign UART3 Clear-to-Send (U3CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SS1R<5:0>: Assign SPI1 Slave Select Input (SS1IN) to Corresponding RPn or RPIn Pin bits REGISTER 11-22: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SCK2R5 SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SDI2R5 SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SCK2R<5:0>: Assign SPI2 Clock Input (SCK2IN) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SDI2R<5:0>: Assign SPI2 Data Input (SDI2) to Corresponding RPn or RPIn Pin bits  2010-2014 Microchip Technology Inc. DS30009996G-page 185

PIC24FJ128GA310 FAMILY REGISTER 11-23: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T1CKR5 T1CKR4 T1CKR3 T1CKR2 T1CKR1 T1CKR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SS2R5 SS2R4 SS2R3 SS2R2 SS2R1 SS2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 T1CKR<5:0>: Assign Timer1 External Clock (T1CK) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SS2R<5:0>: Assign SPI2 Slave Select Input (SS2IN) to Corresponding RPn or RPIn Pin bits REGISTER 11-24: RPINR27: PERIPHERAL PIN SELECT INPUT REGISTER 27 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U4CTSR5 U4CTSR4 U4CTSR3 U4CTSR2 U4CTSR1 U4CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U4RXR5 U4RXR4 U4RXR3 U4RXR2 U4RXR1 U4RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U4CTSR<5:0>: Assign UART4 Clear-to-Send Input (U4CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 U4RXR<5:0>: Assign UART4 Receive Input (U4RX) to Corresponding RPn or RPIn Pin bits DS30009996G-page 186  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 11-25: RPINR30: PERIPHERAL PIN SELECT INPUT REGISTER 30 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — MDMIR5 MDMIR4 MDMIR3 MDMIR2 MDMIR1 MDMIR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 MDMIR<5:0>: Assign TX Modulation Input (MDMI) to Corresponding RPn or RPIn Pin bits REGISTER 11-26: RPINR31: PERIPHERAL PIN SELECT INPUT REGISTER 31 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — MDC2R5 MDC2R4 MDC2R3 MDC2R2 MDC2R1 MDC2R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — MDC1R5 MDC1R4 MDC1R3 MDC1R2 MDC21R1 MDC1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 MDC2R<5:0>: Assign TX Carrier 2 Input (MDCIN2) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 MDC1R<5:0>: Assign TX Carrier 1 Input (MDCIN1) to Corresponding RPn or RPIn Pin bits  2010-2014 Microchip Technology Inc. DS30009996G-page 187

PIC24FJ128GA310 FAMILY REGISTER 11-27: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP1R5 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP0R5 RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP1R<5:0>: RP1 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP1 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP0R<5:0>: RP0 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP0 (see Table11-4 for peripheral function numbers). REGISTER 11-28: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP3R5 RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP2R5 RP2R4 RP2R3 RP2R2 RP2R1 RP2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP3R<5:0>: RP3 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP3 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP2R<5:0>: RP2 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP2 (see Table11-4 for peripheral function numbers). DS30009996G-page 188  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 11-29: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP5R5(1) RP5R4(1) RP5R3(1) RP5R2(1) RP5R1(1) RP5R0(1) bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP4R5 RP4R4 RP4R3 RP4R2 RP4R1 RP4R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP5R<5:0>: RP5 Output Pin Mapping bits(1) Peripheral Output Number n is assigned to pin, RP5 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP4R<5:0>: RP4 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP4 (see Table11-4 for peripheral function numbers). Note 1: These bits are unimplemented in 64-pin devices; read as ‘0’. REGISTER 11-30: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP7R5 RP7R4 RP7R3 RP7R2 RP7R1 RP7R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP6R5 RP6R4 RP6R3 RP6R2 RP6R1 RP6R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP7R<5:0>: RP7 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP7 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP6R<5:0>: RP6 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP6 (see Table11-4 for peripheral function numbers).  2010-2014 Microchip Technology Inc. DS30009996G-page 189

PIC24FJ128GA310 FAMILY REGISTER 11-31: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP9R5 RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP8R5 RP8R4 RP8R3 RP8R2 RP8R1 RP8R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP9R<5:0>: RP9 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP9 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP8R<5:0>: RP8 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP8 (see Table11-4 for peripheral function numbers). REGISTER 11-32: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP11R5 RP11R4 RP11R3 RP11R2 RP11R1 RP11R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP10R5 RP10R4 RP10R3 RP10R2 RP10R1 RP10R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP11R<5:0>: RP11 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP11 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP10R<5:0>: RP10 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP10 (see Table11-4 for peripheral function numbers). DS30009996G-page 190  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 11-33: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP13R5 RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP12R5 RP12R4 RP12R3 RP12R2 RP12R1 RP12R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP13R<5:0>: RP13 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP13 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP12R<5:0>: RP12 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP12 (see Table11-4 for peripheral function numbers). REGISTER 11-34: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP15R5(1) RP15R4(1) RP15R3(1) RP15R2(1) RP15R1(1) RP15R0(1) bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP14R5 RP14R4 RP14R3 RP14R2 RP14R1 RP14R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP15R<5:0>: RP15 Output Pin Mapping bits(1) Peripheral Output Number n is assigned to pin, RP15 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP14R<5:0>: RP14 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP14 (see Table11-4 for peripheral function numbers). Note 1: These bits are unimplemented in 64-pin devices; read as ‘0’.  2010-2014 Microchip Technology Inc. DS30009996G-page 191

PIC24FJ128GA310 FAMILY REGISTER 11-35: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP17R5 RP17R4 RP17R3 RP17R2 RP17R1 RP17R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP16R5 RP16R4 RP16R3 RP16R2 RP16R1 RP16R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP17R<5:0>: RP17 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP17 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP16R<5:0>: RP16 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP16 (see Table11-4 for peripheral function numbers). REGISTER 11-36: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP19R5 RP19R4 RP19R3 RP19R2 RP19R1 RP19R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP18R5 RP18R4 RP18R3 RP18R2 RP18R1 RP18R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP19R<5:0>: RP19 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP19 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP18R<5:0>: RP18 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP18 (see Table11-4 for peripheral function numbers). DS30009996G-page 192  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 11-37: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP21R5 RP21R4 RP21R3 RP21R2 RP21R1 RP21R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP20R5 RP20R4 RP20R3 RP20R2 RP20R1 RP20R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP21R<5:0>: RP21 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP21 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP20R<5:0>: RP20 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP20 (see Table11-4 for peripheral function numbers). REGISTER 11-38: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP23R5 RP23R4 RP23R3 RP23R2 RP23R1 RP23R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP22R5 RP22R4 RP22R3 RP22R2 RP22R1 RP22R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP23R<5:0>: RP23 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP23 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP22R<5:0>: RP22 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP22 (see Table11-4 for peripheral function numbers).  2010-2014 Microchip Technology Inc. DS30009996G-page 193

PIC24FJ128GA310 FAMILY REGISTER 11-39: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP25R5 RP25R4 RP25R3 RP25R2 RP25R1 RP25R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP24R5 RP24R4 RP24R3 RP24R2 RP24R1 RP24R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP25R<5:0>: RP25 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP25 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP24R<5:0>: RP24 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP24 (see Table11-4 for peripheral function numbers). REGISTER 11-40: RPOR13: PERIPHERAL PIN SELECT OUTPUT REGISTER 13 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP27R5 RP27R4 RP27R3 RP27R2 RP27R1 RP27R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP26R5 RP26R4 RP26R3 RP26R2 RP26R1 RP26R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP27R<5:0>: RP27 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP27 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP26R<5:0>: RP26 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP26 (see Table11-4 for peripheral function numbers). DS30009996G-page 194  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 11-41: RPOR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP29R5 RP29R4 RP29R3 RP29R2 RP29R1 RP29R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP28R5 RP28R4 RP28R3 RP28R2 RP28R1 RP28R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP29R<5:0>: RP29 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP29 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP28R<5:0>: RP28 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP28 (see Table11-4 for peripheral function numbers). REGISTER 11-42: RPOR15: PERIPHERAL PIN SELECT OUTPUT REGISTER 15 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP31R5(1) RP31R4(1) RP31R3(1) RP31R2(1) RP31R1(1) RP31R0(1) bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP30R5 RP30R4 RP30R3 RP30R2 RP30R1 RP30R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP31R<5:0>: RP31 Output Pin Mapping bits(1) Peripheral Output Number n is assigned to pin, RP31 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP30R<5:0>: RP30 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP30 (see Table11-4 for peripheral function numbers). Note 1: These bits are unimplemented in 64-pin and 80-pin devices; read as ‘0’.  2010-2014 Microchip Technology Inc. DS30009996G-page 195

PIC24FJ128GA310 FAMILY NOTES: DS30009996G-page 196  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 12.0 TIMER1 Figure12-1 presents a block diagram of the 16-bit Timer1 module. Note: This data sheet summarizes the features of To configure Timer1 for operation: this group of PIC24F devices. It is not intended to be a comprehensive reference 1. Set the TON bit (= 1). source. For more information, refer to 2. Select the timer prescaler ratio using the “Timers” (DS39704) in the TCKPS<1:0> bits. “dsPIC33/PIC24 Family Reference 3. Set the Clock and Gating modes using the TCS, Manual”. The information in this data sheet TECS and TGATE bits. supersedes the information in the FRM. 4. Set or clear the TSYNC bit to configure synchronous or asynchronous operation. The Timer1 module is a 16-bit timer that can operate as a free-running, interval timer/counter. Timer1 can 5. Load the timer period value into the PR1 operate in three modes: register. 6. If interrupts are required, set the Timer1 Interrupt • 16-Bit Timer Enable bit, T1IE. Use the Timer1 Interrupt Priority • 16-Bit Synchronous Counter bits, T1IP<2:0>, to set the interrupt priority. • 16-Bit Asynchronous Counter Timer1 also supports these features: • Timer Gate Operation • Selectable Prescaler Settings • Timer Operation during CPU Idle and Sleep modes • Interrupt on 16-Bit Period Register Match or Falling Edge of External Gate Signal FIGURE 12-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM TGATE LPRC Clock D Q 1 SOSCO Input Select Set T1IF CK Q 0 Reset SOSCI TMR1 Comparator Equal SOSCEN PR1 Clock Input Select Detail T1ECS<1:0> Gate 2 Output SOSC TCKPS<1:0> Input TON 2 T1CK Input Gate Prescaler 0 Sync 1, 8, 64, 256 Clock LPRC Input Output to TMR1 Sync 1 TCY TSYNC TGATE TCS  2010-2014 Microchip Technology Inc. DS30009996G-page 197

PIC24FJ128GA310 FAMILY REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER(1) R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 TON — TSIDL — — — TIECS1 TIECS0 bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timer1 Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-10 Unimplemented: Read as ‘0’ bit 9-8 TIECS<1:0>: Timer1 Extended Clock Source Select bits (selected when TCS = 1) 11 = Unimplemented, do not use 10 = LPRC oscillator 01 = T1CK external clock input 00 = SOSC bit 7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 Unimplemented: Read as ‘0’ bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronizes external clock input 0 = Does not synchronize external clock input When TCS = 0: This bit is ignored. bit 1 TCS: Timer1 Clock Source Select bit 1 = Extended clock is selected by the timer 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: Changing the value of T1CON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. DS30009996G-page 198  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 13.0 TIMER2/3 AND TIMER4/5 To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 or T45 bit (T2CON<3> or Note: This data sheet summarizes the features T4CON<3> = 1). of this group of PIC24F devices. It is not 2. Select the prescaler ratio for Timer2 or Timer4 intended to be a comprehensive refer- using the TCKPS<1:0> bits. ence source. For more information, refer 3. Set the Clock and Gating modes using the TCS to “Timers” (DS39704) in the and TGATE bits. If TCS is set to an external “dsPIC33/PIC24 Family Reference Man- clock, RPINRx (TxCK) must be configured to ual”. The information in this data sheet an available RPn/RPIn pin. For more informa- supersedes the information in the FRM. tion, see Section 11.4“Peripheral Pin Select The Timer2/3 and Timer4/5 modules are 32-bit timers, (PPS)”. which can also be configured as four independent, 16-bit 4. Load the timer period value. PR3 (or PR5) will timers with selectable operating modes. contain the most significant word (msw) of the As 32-bit timers, Timer2/3 and Timer4/5 can each value, while PR2 (or PR4) contains the least operate in three modes: significant word (lsw). 5. If interrupts are required, set the interrupt enable • Two independent 16-bit timers with all 16-bit bit, T3IE or T5IE. Use the priority bits, T3IP<2:0> operating modes (except Asynchronous Counter or T5IP<2:0>, to set the interrupt priority. Note mode) that while Timer2 or Timer4 controls the timer, the • Single 32-bit timer interrupt appears as a Timer3 or Timer5 interrupt. • Single 32-bit synchronous counter 6. Set the TON bit (= 1). They also support these features: The timer value, at any point, is stored in the register • Timer Gate Operation pair, TMR<3:2> (or TMR<5:4>). TMR3 (TMR5) always • Selectable Prescaler Settings contains the most significant word of the count, while • Timer Operation during Idle and Sleep modes TMR2 (TMR4) contains the least significant word. • Interrupt on a 32-Bit Period Register Match To configure any of the timers for individual 16-bit • ADC Event Trigger (only on Timer2/3 in 32-bit operation: mode and Timer3 in 16-bit mode) 1. Clear the T32 bit corresponding to that timer Individually, all four of the 16-bit timers can function as (T2CON<3> for Timer2 and Timer3 or synchronous timers or counters. They also offer the T4CON<3> for Timer4 and Timer5). features listed above, except for the ADC event trigger. 2. Select the timer prescaler ratio using the This trigger is implemented only on Timer2/3 in 32-bit TCKPS<1:0> bits. mode and Timer3 in 16-bit mode. The operating modes 3. Set the Clock and Gating modes using the TCS and enabled features are determined by setting the and TGATE bits. See Section 11.4“Peripheral appropriate bit(s) in the T2CON, T3CON, T4CON and Pin Select (PPS)” for more information. T5CON registers. T2CON and T4CON are shown in 4. Load the timer period value into the PRx register. generic form in Register13-1; T3CON and T5CON are 5. If interrupts are required, set the interrupt enable shown in Register13-2. bit, TxIE. Use the priority bits, TxIP<2:0>, to set For 32-bit timer/counter operation, Timer2 and Timer4 the interrupt priority. are the least significant word; Timer3 and Timer4 are 6. Set the TON (TxCON<15> = 1) bit. the most significant word of the 32-bit timers. Note: For 32-bit operation, T3CON and T5CON control bits are ignored. Only T2CON and T4CON control bits are used for setup and control. Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags.  2010-2014 Microchip Technology Inc. DS30009996G-page 199

PIC24FJ128GA310 FAMILY FIGURE 13-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM TCKPS<1:0> T2CK TON 2 1x (T4CK) Gate Prescaler Sync 01 1, 8, 64, 256 TCY 00 TGATE TGATE(2) TCS(2) 1 Q D Set T3IF (T5IF) Q CK 0 PR3 PR2 (PR5) (PR4) ADC Event Trigger(3) Equal Comparator MSB LSB TMR3 TMR2 Sync Reset (TMR5) (TMR4) 16 Read TMR2 (TMR4)(1) Write TMR2 (TMR4)(1) 16 TMR3HLD 16 (TMR5HLD) Data Bus<15:0> Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON and T4CON registers. 2: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.4“Peripheral Pin Select (PPS)” for more information. 3: The ADC event trigger is available only on Timer 2/3 in 32-bit mode and Timer 3 in 16-bit mode. DS30009996G-page 200  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY FIGURE 13-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM TCKPS<1:0> TON 2 T2CK 1x (T4CK) Gate Prescaler Sync 01 1, 8, 64, 256 TGATE 00 TCY TCS(1) 1 Q D TGATE(1) Set T2IF (T4IF) Q CK 0 Reset TMR2 (TMR4) Sync Comparator Equal PR2 (PR4) Note 1: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.4“Peripheral Pin Select (PPS)” for more information. FIGURE 13-3: TIMER3 AND TIMER5 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM TCKPS<1:0> T3CK TON 2 Sync 1x (T5CK) Prescaler 01 1, 8, 64, 256 TGATE 00 TCY TCS(1) 1 Q D TGATE(1) Set T3IF (T5IF) Q CK 0 Reset TMR3 (TMR5) ADC Event Trigger(2) Comparator Equal PR3 (PR5) Note 1: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.4“Peripheral Pin Select (PPS)” for more information. 2: The ADC event trigger is available only on Timer3.  2010-2014 Microchip Technology Inc. DS30009996G-page 201

PIC24FJ128GA310 FAMILY REGISTER 13-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER(3) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 T32(1) — TCS(2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timerx On bit When TxCON<3> = 1: 1 = Starts 32-bit Timerx/y 0 = Stops 32-bit Timerx/y When TxCON<3> = 0: 1 = Starts 16-bit Timerx 0 = Stops 16-bit Timerx bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timerx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timerx Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timerx Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 T32: 32-Bit Timer Mode Select bit(1) 1 = Timerx and Timery form a single 32-bit timer 0 = Timerx and Timery act as two 16-bit timers In 32-bit mode, T3CON control bits do not affect 32-bit timer operation. bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timerx Clock Source Select bit(2) 1 = External clock is from pin, TxCK (on the rising edge) 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: In T4CON, the T45 bit is implemented instead of T32 to select 32-bit mode. In 32-bit mode, the T3CON or T5CON control bits do not affect 32-bit timer operation. 2: If TCS = 1, RPINRx (TxCK) must be configured to an available RPn/RPIn pin. For more information, see Section 11.4“Peripheral Pin Select (PPS)”. 3: Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. DS30009996G-page 202  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 13-2: TyCON: TIMER3 AND TIMER5 CONTROL REGISTER(3) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(1) — TSIDL(1) — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — TGATE(1) TCKPS1(1) TCKPS0(1) — — TCS(1,2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timery On bit(1) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timery bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timery Stop in Idle Mode bit(1) 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timery Gated Time Accumulation Enable bit(1) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timery Input Clock Prescale Select bits(1) 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3-2 Unimplemented: Read as ‘0’ bit 1 TCS: Timery Clock Source Select bit(1,2) 1 = External clock from pin, TyCK (on the rising edge) 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit operation is enabled (T2CON<3> or T4CON<3> = 1), these bits have no effect on Timery operation; all timer functions are set through T2CON and T4CON. 2: If TCS = 1, RPINRx (TxCK) must be configured to an available RPn/RPIn pin. See Section 11.4“Peripheral Pin Select (PPS)” for more information. 3: Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended.  2010-2014 Microchip Technology Inc. DS30009996G-page 203

PIC24FJ128GA310 FAMILY NOTES: DS30009996G-page 204  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 14.0 INPUT CAPTURE WITH 14.1 General Operating Modes DEDICATED TIMERS 14.1.1 SYNCHRONOUS AND TRIGGER Note: This data sheet summarizes the features of MODES this group of PIC24F devices. It is not When the input capture module operates in a intended to be a comprehensive reference Free-Running mode, the internal 16-bit counter, source. For more information, refer to ICxTMR, counts up continuously, wrapping around “Input Capture with Dedicated Timer” from FFFFh to 0000h on each overflow. Its period is (DS39722) in the “dsPIC33/PIC24 Family synchronized to the selected external clock source. Reference Manual”. The information in this When a capture event occurs, the current 16-bit value data sheet supersedes the information in of the internal counter is written to the FIFO buffer. the FRM. In Synchronous mode, the module begins capturing Devices in the PIC24FJ128GA310 family contain events on the ICx pin as soon as its selected clock seven independent input capture modules. Each of the source is enabled. Whenever an event occurs on the modules offers a wide range of configuration and selected sync source, the internal counter is reset. In operating options for capturing external pulse events Trigger mode, the module waits for a Sync event from and generating interrupts. another internal module to occur before allowing the internal counter to run. Key features of the input capture module include: Standard, free-running operation is selected by setting • Hardware-configurable for 32-bit operation in all the SYNCSELx bits (ICxCON2<4:0>) to ‘00000’ and modes by cascading two adjacent modules clearing the ICTRIG bit (ICxCON2<7>). Synchronous • Synchronous and Trigger modes of output and Trigger modes are selected any time the compare operation, with up to 30 user-selectable SYNCSELx bits are set to any value except ‘00000’. sync/trigger sources available The ICTRIG bit selects either Synchronous or Trigger • A 4-level FIFO buffer for capturing and holding mode; setting the bit selects Trigger mode operation. In timer values for several events both modes, the SYNCSELx bits determine the • Configurable interrupt generation sync/trigger source. • Up to 6 clock sources available for each module, When the SYNCSELx bits are set to ‘00000’ and driving a separate internal 16-bit counter ICTRIG is set, the module operates in Software Trigger The module is controlled through two registers: ICxCON1 mode. In this case, capture operations are started by (Register14-1) and ICxCON2 (Register14-2). A general manually setting the TRIGSTAT bit (ICxCON2<6>). block diagram of the module is shown in Figure14-1. FIGURE 14-1: INPUT CAPTURE x BLOCK DIAGRAM ICM<2:0> ICI<1:0> Prescaler Edge Detect Logic Event and Set ICxIF Counter and Interrupt 1:1/4/16 Clock Synchronizer Logic ICx Pin(1) ICTSEL<2:0> Increment 16 ICx Clock Clock ICxTMR 4-Level FIFO Buffer Sources Select 16 16 Sync and Reset ICxBUF Sync and Trigger Trigger Sources Logic SYNCSEL<4:0> Trigger ICOV, ICBNE System Bus Note 1: The ICx inputs must be assigned to an available RPn/RPIn pin before use. See Section11.4 “Peripheral Pin Select (PPS)” for more information.  2010-2014 Microchip Technology Inc. DS30009996G-page 205

PIC24FJ128GA310 FAMILY 14.1.2 CASCADED (32-BIT) MODE For 32-bit cascaded operations, the setup procedure is slightly different: By default, each module operates independently with its own 16-bit timer. To increase resolution, adjacent 1. Set the IC32 bits for both modules even and odd modules can be configured to function as (ICyCON2<8>) and (ICxCON2<8>), enabling a single 32-bit module. (For example, Modules 1 and 2 the even numbered module first. This ensures are paired, as are Modules 3 and 4, and so on.) The the modules will start functioning in unison. odd numbered module (ICx) provides the Least Signif- 2. Set the ICTSELx and SYNCSELx bits for both icant 16 bits of the 32-bit register pairs and the even modules to select the same sync/trigger and time module (ICy) provides the Most Significant 16 bits. base source. Set the even module first, then the Wraparounds of the ICx registers cause an increment odd module. Both modules must use the same of their corresponding ICy registers. ICTSELx and SYNCSELx bits settings. Cascaded operation is configured in hardware by 3. Clear the ICTRIG bit of the even module setting the IC32 bits (ICxCON2<8>) for both modules. (ICyCON2<7>). This forces the module to run in Synchronous mode with the odd module, 14.2 Capture Operations regardless of its trigger setting. 4. Use the odd module’s ICIx bits (ICxCON1<6:5>) The input capture module can be configured to capture to set the desired interrupt frequency. timer values and generate interrupts on rising edges on 5. Use the ICTRIG bit of the odd module ICx or all transitions on ICx. Captures can be config- (ICxCON2<7>) to configure Trigger or ured to occur on all rising edges or just some (every 4th Synchronous mode operation. or 16th). Interrupts can be independently configured to generate on each event or a subset of events. Note: For Synchronous mode operation, enable the sync source as the last step. Both To set up the module for capture operations: input capture modules are held in Reset 1. Configure the ICx input for one of the available until the sync source is enabled. Peripheral Pin Select pins. 6. Use the ICMx bits of the odd module 2. If Synchronous mode is to be used, disable the (ICxCON1<2:0>) to set the desired Capture sync source before proceeding. mode. 3. Make sure that any previous data has been removed from the FIFO by reading ICxBUF until The module is ready to capture events when the time the ICBNE bit (ICxCON1<3>) is cleared. base and the sync/trigger source are enabled. When the ICBNE bit (ICxCON1<3>) becomes set, at least 4. Set the SYNCSELx bits (ICxCON2<4:0>) to the one capture value is available in the FIFO. Read input desired sync/trigger source. capture values from the FIFO until the ICBNE clears 5. Set the ICTSELx bits (ICxCON1<12:10>) for the to‘0’. desired clock source. For 32-bit operation, read both the ICxBUF and 6. Set the ICIx bits (ICxCON1<6:5>) to the desired ICyBUF for the full 32-bit timer value (ICxBUF for the interrupt frequency lsw, ICyBUF for the msw). At least one capture value is 7. Select Synchronous or Trigger mode operation: available in the FIFO buffer when the odd module’s a) Check that the SYNCSELx bits are not set ICBNE bit (ICxCON1<3>) becomes set. Continue to to ‘00000’. read the buffer registers until ICBNE is cleared b) For Synchronous mode, clear the ICTRIG (performed automatically by hardware). bit (ICxCON2<7>). c) For Trigger mode, set ICTRIG, and clear the TRIGSTAT bit (ICxCON2<6>). 8. Set the ICMx bits (ICxCON1<2:0>) to the desired operational mode. 9. Enable the selected sync/trigger source. DS30009996G-page 206  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 14-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — bit 15 bit 8 U-0 R/W-0 R/W-0 R-0, HSC R-0, HSC R/W-0 R/W-0 R/W-0 — ICI1 ICI0 ICOV ICBNE ICM2(1) ICM1(1) ICM0(1) bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 ICSIDL: Input Capture x Module Stop in Idle Control bit 1 = Input capture module halts in CPU Idle mode 0 = Input capture module continues to operate in CPU Idle mode bit 12-10 ICTSEL<2:0>: Input Capture x Timer Select bits 111 = System clock (FOSC/2) 110 = Reserved 101 = Reserved 100 = Timer1 011 = Timer5 010 = Timer4 001 = Timer2 000 = Timer3 bit 9-7 Unimplemented: Read as ‘0’ bit 6-5 ICI<1:0>: Select Number of Captures per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event bit 4 ICOV: Input Capture x Overflow Status Flag bit (read-only) 1 = Input capture overflow has occurred 0 = No input capture overflow has occurred bit 3 ICBNE: Input Capture x Buffer Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty bit 2-0 ICM<2:0>: Input Capture x Mode Select bits(1) 111 = Interrupt mode: Input capture functions as an interrupt pin only when the device is in Sleep or Idle mode (rising edge detect only, all other control bits are not applicable) 110 = Unused (module is disabled) 101 = Prescaler Capture mode: Capture on every 16th rising edge 100 = Prescaler Capture mode: Capture on every 4th rising edge 011 = Simple Capture mode: Capture on every rising edge 010 = Simple Capture mode: Capture on every falling edge 001 = Edge Detect Capture mode: Capture on every edge (rising and falling); ICI<1:0> bits do not control interrupt generation for this mode 000 = Input capture module is turned off Note 1: The ICx input must also be configured to an available RPn/RPIn pin. For more information, see Section11.4 “Peripheral Pin Select (PPS)”.  2010-2014 Microchip Technology Inc. DS30009996G-page 207

PIC24FJ128GA310 FAMILY REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — IC32 bit 15 bit 8 R/W-0 R/W-0, HS U-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 IC32: Cascade Two IC Modules Enable bit (32-bit operation) 1 = ICx and ICy operate in cascade as a 32-bit module (this bit must be set in both modules) 0 = ICx functions independently as a 16-bit module bit 7 ICTRIG: ICx Sync/Trigger Select bit 1 = Trigger ICx from the source designated by the SYNCSELx bits 0 = Synchronize ICx with the source designated by the SYNCSELx bits bit 6 TRIGSTAT: Timer Trigger Status bit 1 = Timer source has been triggered and is running (set in hardware, can be set in software) 0 = Timer source has not been triggered and is being held clear bit 5 Unimplemented: Read as ‘0’ Note 1: Use these inputs as trigger sources only and never as sync sources. 2: Never use an IC module as its own trigger source, by selecting this mode. DS30009996G-page 208  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 (CONTINUED) bit 4-0 SYNCSEL<4:0>: Synchronization/Trigger Source Selection bits 11111 =Reserved 11110 =Reserved(2) 11101 =Reserved(2) 11100 =CTMU(1) 11011 =ADC(1) 11010 =Comparator 3(1) 11001 =Comparator 2(1) 11000 =Comparator 1(1) 10111 =Reserved(2) 10110 =Input Capture 7(2) 10101 =Input Capture 6(2) 10100 =Input Capture 5(2) 10011 =Input Capture 4(2) 10010 =Input Capture 3(2) 10001 =Input Capture 2(2) 10000 =Input Capture 1(2) 01111 =Timer5 01110 =Timer4 01101 =Timer3 01100 =Timer2 01011 =Timer1 01010 =Reserved 01001 =Reserved 01000 =Reserved 00111 =Output Compare 7 • • • 00010 =Output Compare 2 00001 =Output Compare 1 00000 =Not synchronized to any other module Note 1: Use these inputs as trigger sources only and never as sync sources. 2: Never use an IC module as its own trigger source, by selecting this mode.  2010-2014 Microchip Technology Inc. DS30009996G-page 209

PIC24FJ128GA310 FAMILY NOTES: DS30009996G-page 210  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 15.0 OUTPUT COMPARE WITH In Synchronous mode, the module begins performing DEDICATED TIMERS its compare or PWM operation as soon as its selected clock source is enabled. Whenever an event occurs on the selected sync source, the module’s internal counter Note: This data sheet summarizes the features of is reset. In Trigger mode, the module waits for a sync this group of PIC24F devices. It is not event from another internal module to occur before intended to be a comprehensive reference allowing the counter to run. source. For more information, refer to “Out- put Compare with Dedicated Timer” Free-Running mode is selected by default or any time (DS39723) in the “dsPIC33/PIC24 Family that the SYNCSELx bits (OCxCON2<4:0>) are set to Reference Manual”. The information in this ‘00000’. Synchronous or Trigger modes are selected data sheet supersedes the information in any time the SYNCSELx bits are set to any value the FRM. except ‘00000’. The OCTRIG bit (OCxCON2<7>) selects either Synchronous or Trigger mode; setting the Devices in the PIC24FJ128GA310 family all feature bit selects Trigger mode operation. In both modes, the seven independent output compare modules. Each of SYNCSELx bits determine the sync/trigger source. these modules offers a wide range of configuration and operating options for generating pulse trains on internal 15.1.2 CASCADED (32-BIT) MODE device events, and can produce Pulse-Width By default, each module operates independently with Modulated waveforms for driving power applications. its own set of 16-Bit Timer and Duty Cycle registers. To Key features of the output compare module include: increase resolution, adjacent even and odd modules • Hardware-configurable for 32-bit operation in all can be configured to function as a single 32-bit module. modes by cascading two adjacent modules (For example, Modules 1 and 2 are paired, as are Modules 3 and 4, and so on.) The odd numbered • Synchronous and Trigger modes of output compare operation, with up to 31 user-selectable module (OCx) provides the Least Significant 16 bits of the 32-bit register pairs and the even module (OCy) trigger/sync sources available provides the Most Significant 16 bits. Wraparounds of • Two separate Period registers (a main register, the OCx registers cause an increment of their OCxR, and a secondary register, OCxRS) for corresponding OCy registers. greater flexibility in generating pulses of varying widths Cascaded operation is configured in hardware by set- • Configurable for single pulse or continuous pulse ting the OC32 bit (OCxCON2<8>) for both modules. generation on an output event, or continuous For more details on cascading, refer to “Output PWM waveform generation Compare with Dedicated Timer” (DS39723) in the “dsPIC33/PIC24 Family Reference Manual”. • Up to 6 clock sources available for each module, driving a separate internal 16-bit counter 15.1 General Operating Modes 15.1.1 SYNCHRONOUS AND TRIGGER MODES When the output compare module operates in a Free-Running mode, the internal 16-bit counter, OCxTMR, counts up continuously, wrapping around from 0xFFFF to 0x0000 on each overflow. Its period is synchronized to the selected external clock source. Compare or PWM events are generated each time a match between the internal counter and one of the Period registers occurs.  2010-2014 Microchip Technology Inc. DS30009996G-page 211

PIC24FJ128GA310 FAMILY FIGURE 15-1: OUTPUT COMPARE x BLOCK DIAGRAM (16-BIT MODE) OCMx OCINV OCxCON1 OCTRIS OCTSELx OCxCON2 FLTOUT SYNCSELx FLTTRIEN TRIGSTAT FLTMD TRIGMODE ENFLT<2:0> OCTRIG OCxR and OCFLT<2:0> DCB<1:0> DCB<1:0> OCx Pin(1) Match Event Comparator Increment OCx Clock Clock Sources Select OCx Output and OCxTMR Reset Fault Logic Match Event OCFA/OCFB(2) Comparator Match Event Trigger and Trigger and Sync Logic OCxRS Sync Sources Reset OCx Interrupt Note 1: The OCx outputs must be assigned to an available RPn pin before use. See Section11.4 “Peripheral Pin Select (PPS)” for more information. 2: The OCFA/OCFB Fault inputs must be assigned to an available RPn/RPIn pin before use. See Section11.4 “Peripheral Pin Select (PPS)” for more information. 15.2 Compare Operations 3. Write the rising edge value to OCxR and the falling edge value to OCxRS. In Compare mode (Figure15-1), the output compare 4. Set the Timer Period register, PRy, to a value module can be configured for single-shot or continuous equal to or greater than the value in OCxRS. pulse generation. It can also repeatedly toggle an 5. Set the OCM<2:0> bits for the appropriate output pin on each timer event. compare operation (= 0xx). To set up the module for compare operations: 6. For Trigger mode operations, set OCTRIG to 1. Configure the OCx output for one of the enable Trigger mode. Set or clear TRIGMODE available Peripheral Pin Select pins. to configure trigger operation and TRIGSTAT to 2. Calculate the required values for the OCxR and select a hardware or software trigger. For (for Double Compare modes) OCxRS Duty Synchronous mode, clear OCTRIG. Cycle registers: 7. Set the SYNCSEL<4:0> bits to configure the a) Determine the instruction clock cycle time. trigger or synchronization source. If free-running Take into account the frequency of the timer operation is required, set the SYNCSELx external clock to the timer source (if one is bits to ‘00000’ (no sync/trigger source). used) and the timer prescaler settings. 8. Select the time base source with the b) Calculate time to the rising edge of the OCTSEL<2:0> bits. If necessary, set the TON bit output pulse relative to the timer start value for the selected timer, which enables the com- (0000h). pare time base to count. Synchronous mode c) Calculate the time to the falling edge of the operation starts as soon as the time base is pulse based on the desired pulse width and enabled; Trigger mode operation starts after a the time to the rising edge of the pulse. trigger source event occurs. DS30009996G-page 212  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY For 32-bit cascaded operation, these steps are also 15.3 Pulse-Width Modulation (PWM) necessary: Mode 1. Set the OC32 bits for both registers In PWM mode, the output compare module can be (OCyCON2<8>) and (OCxCON2<8>). Enable configured for edge-aligned or center-aligned pulse the even numbered module first to ensure the waveform generation. All PWM operations are modules will start functioning in unison. double-buffered (buffer registers are internal to the 2. Clear the OCTRIG bit of the even module module and are not mapped into SFR space). (OCyCON2<7>), so the module will run in To configure the output compare module for PWM Synchronous mode. operation: 3. Configure the desired output and Fault settings for OCy. 1. Configure the OCx output for one of the 4. Force the output pin for OCx to the output state available Peripheral Pin Select pins. by clearing the OCTRIS bit. 2. Calculate the desired duty cycles and load them 5. If Trigger mode operation is required, configure into the OCxR register. the trigger options in OCx by using the OCTRIG 3. Calculate the desired period and load it into the (OCxCON2<7>), TRIGMODE (OCxCON1<3>) OCxRS register. and SYNCSELx (OCxCON2<4:0>) bits. 4. Select the current OCx as the synchronization 6. Configure the desired Compare or PWM mode source by writing 0x1F to the SYNCSEL<4:0> of operation (OCM<2:0>) for OCy first, then for bits (OCxCON2<4:0>) and ‘0’ to the OCTRIG bit OCx. (OCxCON2<7>). Depending on the output mode selected, the module 5. Select a clock source by writing to the holds the OCx pin in its default state and forces a tran- OCTSEL<2:0> bits (OCxCON<12:10>). sition to the opposite state when OCxR matches the 6. Enable interrupts, if required, for the timer and timer. In Double Compare modes, OCx is forced back output compare modules. The output compare to its default state when a match with OCxRS occurs. interrupt is required for PWM Fault pin The OCxIF interrupt flag is set after an OCxR match in utilization. Single Compare modes and after each OCxRS match 7. Select the desired PWM mode with the in Double Compare modes. OCM<2:0> bits (OCxCON1<2:0>). Single-shot pulse events only occur once, but may be 8. Appropriate Fault inputs may be enabled by repeated by simply rewriting the value of the using the ENFLT<2:0> bits as described in OCxCON1 register. Continuous pulse events continue Register15-1. indefinitely until terminated. 9. If a timer is selected as a clock source, set the selected timer prescale value. The selected timer’s prescaler output is used as the clock input for the OCx timer and not the selected timer output. Note: This peripheral contains input and output functions that may need to be configured by the Peripheral Pin Select. See Section11.4 “Peripheral Pin Select (PPS)” for more information.  2010-2014 Microchip Technology Inc. DS30009996G-page 213

PIC24FJ128GA310 FAMILY FIGURE 15-2: OUTPUT COMPARE x BLOCK DIAGRAM (DOUBLE-BUFFERED, 16-BIT PWM MODE) OCxCON1 OCMx OCxCON2 OCINV OCTSELx OCTRIS SYNCSELx OCxR and FLTOUT DCB<1:0> TRIGSTAT FLTTRIEN TRIGMODE FLTMD OCTRIG Rollover/Reset ENFLT<2:0> OCFLT<2:0> OCxR and DCB<1:0> DCB<1:0> Buffers OCx Pin(1) Comparator Increment Match OC Clock Clock Event Sources Select OCxTMR OCx Output and Rollover Fault Logic Reset OCFA/OCFB(2) Comparator Match Event Match Trigger and Trigger and Event Sync Sources Sync Logic OCxRS Buffer Rollover/Reset OCxRS OCx Interrupt Reset Note 1: The OCx outputs must be assigned to an available RPn pin before use. See Section11.4 “Peripheral Pin Select (PPS)” for more information. 2: The OCFA/OCFB Fault inputs must be assigned to an available RPn/RPIn pin before use. See Section11.4 “Peripheral Pin Select (PPS)” for more information. 15.3.1 PWM PERIOD The PWM period is specified by writing to PRy, the Timer Period register. The PWM period can be calculated using Equation15-1. EQUATION 15-1: CALCULATING THE PWM PERIOD(1) PWM Period = [(PRy) + 1 • TCY • (Timer Prescale Value) where: PWM Frequency = 1/[PWM Period] Note 1: Based on TCY = TOSC * 2; Doze mode and PLL are disabled. Note: A PRy value of N will produce a PWM period of N + 1 time base count cycles. For example, a value of 7,written into the PRy register, will yield a period consisting of 8 time base cycles. DS30009996G-page 214  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 15.3.2 PWM DUTY CYCLE Some important boundary parameters of the PWM duty cycle include: The PWM duty cycle is specified by writing to the OCxRS and OCxR registers. The OCxRS and OCxR • If OCxR, OCxRS, and PRy are all loaded with registers can be written to at any time, but the duty 0000h, the OCx pin will remain low (0% duty cycle value is not latched until a match between PRy cycle). and TMRy occurs (i.e., the period is complete). This • If OCxRS is greater than PRy, the pin will remain provides a double buffer for the PWM duty cycle and is high (100% duty cycle). essential for glitchless PWM operation. See Example15-1 for PWM mode timing details. Table15-1 and Table15-2 show example PWM frequencies and resolutions for a device operating at 4 MIPS and 10 MIPS, respectively. EQUATION 15-2: CALCULATION FOR MAXIMUM PWM RESOLUTION(1) log10( FCY ) FPWM • (Timer Prescale Value) Maximum PWM Resolution (bits) = bits log (2) 10 Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. EXAMPLE 15-1: PWM PERIOD AND DUTY CYCLE CALCULATIONS(1) 1. Find the Timer Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL (32 MHz device clock rate) and a Timer2 prescaler setting of 1:1. TCY = 2 • TOSC = 62.5 ns PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2ms PWM Period = (PR2 + 1) • TCY • (Timer2 Prescale Value) 19.2ms = (PR2 + 1) • 62.5 ns • 1 PR2 = 306 2. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32MHz device clock rate: PWM Resolution = log10(FCY/FPWM)/log102) bits = (log (16 MHz/52.08 kHz)/log 2) bits 10 10 = 8.3 bits Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled. TABLE 15-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)(1) PWM Frequency 7.6 Hz 61 Hz 122 Hz 977 Hz 3.9 kHz 31.3 kHz 125 kHz Timer Prescaler Ratio 8 1 1 1 1 1 1 Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh Resolution (bits) 16 16 15 12 10 7 5 Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. TABLE 15-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)(1) PWM Frequency 30.5 Hz 244 Hz 488 Hz 3.9 kHz 15.6 kHz 125 kHz 500 kHz Timer Prescaler Ratio 8 1 1 1 1 1 1 Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh Resolution (bits) 16 16 15 12 10 7 5 Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.  2010-2014 Microchip Technology Inc. DS30009996G-page 215

PIC24FJ128GA310 FAMILY REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2(2) ENFLT1(2) bit 15 bit 8 R/W-0 R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0 R/W-0 R/W-0 R/W-0 ENFLT0(2) OCFLT2(2,3) OCFLT1(2,4) OCFLT0(2,4) TRIGMODE OCM2(1) OCM1(1) OCM0(1) bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 OCSIDL: Output Compare x Stop in Idle Mode Control bit 1 = Output Compare x halts in CPU Idle mode 0 = Output Compare x continues to operate in CPU Idle mode bit 12-10 OCTSEL<2:0>: Output Compare x Timer Select bits 111 =Peripheral clock (FCY) 110 =Reserved 101 =Reserved 100 =Timer1 clock (only synchronous clock is supported) 011 =Timer5 clock 010 =Timer4 clock 001 = Timer3 clock 000 =Timer2 clock bit 9 ENFLT2: Fault Input 2 Enable bit(2) 1 = Fault 2 (Comparator 1/2/3 out) is enabled(3) 0 = Fault 2 is disabled bit 8 ENFLT1: Fault Input 1 Enable bit(2) 1 = Fault 1 (OCFB pin) is enabled(4) 0 = Fault 1 is disabled bit 7 ENFLT0: Fault Input 0 Enable bit(2) 1 = Fault 0 (OCFA pin) is enabled(4) 0 = Fault 0 is disabled bit 6 OCFLT2: PWM Fault 2 (Comparator 1/2/3) Condition Status bit(2,3) 1 = PWM Fault 2 has occurred 0 = No PWM Fault 2 has occurred bit 5 OCFLT1: PWM Fault 1 (OCFB pin) Condition Status bit(2,4) 1 = PWM Fault 1 has occurred 0 = No PWM Fault 1 has occurred Note 1: The OCx output must also be configured to an available RPn pin. For more information, see Section11.4 “Peripheral Pin Select (PPS)”. 2: The Fault input enable and Fault status bits are valid when OCM<2:0> = 111 or 110. 3: The Comparator 1 output controls the OC1-OC3 channels; Comparator 2 output controls the OC4-OC6 channels; Comparator 3 output controls the OC7-OC9 channels. 4: The OCFA/OCFB Fault input must also be configured to an available RPn/RPIn pin. For more information, see Section11.4 “Peripheral Pin Select (PPS)”. DS30009996G-page 216  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED) bit 4 OCFLT0: PWM Fault 0 (OCFA pin) Condition Status bit(2,4) 1 = PWM Fault 0 has occurred 0 = No PWM Fault 0 has occurred bit 3 TRIGMODE: Trigger Status Mode Select bit 1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software 0 = TRIGSTAT is only cleared by software bit 2-0 OCM<2:0>: Output Compare x Mode Select bits(1) 111 = Center-Aligned PWM mode on OCx(2) 110 = Edge-Aligned PWM mode on OCx(2) 101 = Double Compare Continuous Pulse mode: Initialize the OCx pin low; toggle the OCx state continuously on alternate matches of OCxR and OCxRS 100 = Double Compare Single-Shot mode: Initialize the OCx pin low; toggle the OCx state on matches of OCxR and OCxRS for one cycle 011 = Single Compare Continuous Pulse mode: Compare events continuously toggle the OCx pin 010 = Single Compare Single-Shot mode: Initialize OCx pin high; compare event forces the OCx pin low 001 = Single Compare Single-Shot mode: Initialize OCx pin low; compare event forces the OCx pin high 000 = Output compare channel is disabled Note 1: The OCx output must also be configured to an available RPn pin. For more information, see Section11.4 “Peripheral Pin Select (PPS)”. 2: The Fault input enable and Fault status bits are valid when OCM<2:0> = 111 or 110. 3: The Comparator 1 output controls the OC1-OC3 channels; Comparator 2 output controls the OC4-OC6 channels; Comparator 3 output controls the OC7-OC9 channels. 4: The OCFA/OCFB Fault input must also be configured to an available RPn/RPIn pin. For more information, see Section11.4 “Peripheral Pin Select (PPS)”.  2010-2014 Microchip Technology Inc. DS30009996G-page 217

PIC24FJ128GA310 FAMILY REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 FLTMD FLTOUT FLTTRIEN OCINV — DCB1(3) DCB0(3) OC32 bit 15 bit 8 R/W-0 R/W-0, HS R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FLTMD: Fault Mode Select bit 1 = Fault mode is maintained until the Fault source is removed and the corresponding OCFLT0 bit is cleared in software 0 = Fault mode is maintained until the Fault source is removed and a new PWM period starts bit 14 FLTOUT: Fault Out bit 1 = PWM output is driven high on a Fault 0 = PWM output is driven low on a Fault bit 13 FLTTRIEN: Fault Output State Select bit 1 = Pin is forced to an output on a Fault condition 0 = Pin I/O condition is unaffected by a Fault bit 12 OCINV: OCMP Invert bit 1 = OCx output is inverted 0 = OCx output is not inverted bit 11 Unimplemented: Read as ‘0’ bit 10-9 DCB<1:0>: PWM Duty Cycle Least Significant bits(3) 11 = Delay OCx falling edge by ¾ of the instruction cycle 10 = Delay OCx falling edge by ½ of the instruction cycle 01 = Delay OCx falling edge by ¼ of the instruction cycle 00 = OCx falling edge occurs at the start of the instruction cycle bit 8 OC32: Cascade Two OC Modules Enable bit (32-bit operation) 1 = Cascade module operation is enabled 0 = Cascade module operation is disabled bit 7 OCTRIG: OCx Trigger/Sync Select bit 1 = Trigger OCx from the source designated by the SYNCSELx bits 0 = Synchronize OCx with the source designated by the SYNCSELx bits bit 6 TRIGSTAT: Timer Trigger Status bit 1 = Timer source has been triggered and is running 0 = Timer source has not been triggered and is being held clear bit 5 OCTRIS: OCx Output Pin Direction Select bit 1 = OCx pin is tri-stated 0 = Output Compare Peripheral x is connected to an OCx pin Note 1: Never use an OCx module as its own trigger source, either by selecting this mode or another equivalent SYNCSELx setting. 2: Use these inputs as trigger sources only and never as sync sources. 3: The DCB<1:0> bits are double-buffered in PWM modes only (OCM<2:0> (OCxCON1<2:0>) = 111, 110). DS30009996G-page 218  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED) bit 4-0 SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits 11111 = This OC module(1) 11110 = Input Capture 9(2) 11101 = Input Capture 6(2) 11100 = CTMU(2) 11011 = ADC(2) 11010 = Comparator 3(2) 11001 = Comparator 2(2) 11000 = Comparator 1(2) 10111 = Input Capture 4(2) 10110 = Input Capture 3(2) 10101 = Input Capture 2(2) 10100 = Input Capture 1(2) 10011 = Input Capture 8(2) 10010 = Input Capture 7(2) 1000x = Reserved 01111 = Timer5 01110 = Timer4 01101 = Timer3 01100 = Timer2 01011 = Timer1 01010 = Input Capture 5(2) 01001 = Output Compare 9(1) 01000 = Output Compare 8(1) 00111 = Output Compare 7(1) 00110 = Output Compare 6(1) 00101 = Output Compare 5(1) 00100 = Output Compare 4(1) 00011 = Output Compare 3(1) 00010 = Output Compare 2(1) 00001 = Output Compare 1(1) 00000 = Not synchronized to any other module Note 1: Never use an OCx module as its own trigger source, either by selecting this mode or another equivalent SYNCSELx setting. 2: Use these inputs as trigger sources only and never as sync sources. 3: The DCB<1:0> bits are double-buffered in PWM modes only (OCM<2:0> (OCxCON1<2:0>) = 111, 110).  2010-2014 Microchip Technology Inc. DS30009996G-page 219

PIC24FJ128GA310 FAMILY NOTES: DS30009996G-page 220  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 16.0 SERIAL PERIPHERAL The module also supports a basic framed SPI protocol INTERFACE (SPI) while operating in either Master or Slave mode. A total of four framed SPI configurations are supported. Note: This data sheet summarizes the features of The SPI serial interface consists of four pins: this group of PIC24F devices. It is not • SDIx: Serial Data Input intended to be a comprehensive reference • SDOx: Serial Data Output source. For more information, refer to “Serial Peripheral Interface (SPI)” • SCKx: Shift Clock Input or Output (DS39699) in the “dsPIC33/PIC24 Family • SSx: Active-Low Slave Select or Frame Reference Manual”. The information in this Synchronization I/O Pulse data sheet supersedes the information in The SPI module can be configured to operate using 2, the FRM. 3 or 4 pins. In the 3-pin mode, SSx is not used. In the 2-pin mode, both SDOx and SSx are not used. The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating Block diagrams of the module in Standard and with other peripheral or microcontroller devices. These Enhanced modes are shown in Figure16-1 and peripheral devices may be serial EEPROMs, shift Figure16-2. registers, display drivers, ADC Converters, etc. The Note: In this section, the SPI modules are SPI module is compatible with the SPI and SIOP Motorola® interfaces. All PIC24FJ128GA310 family referred to together as SPIx or separately as SPI1 or SPI2. Special Function Regis- devices include two SPI modules. ters will follow a similar notation. For The module supports operation in two buffer modes. In example, SPIxCON1 and SPIxCON2 Standard mode, data is shifted through a single serial refer to the control registers for any of the buffer. In Enhanced Buffer mode, data is shifted 2 SPI modules. through an 8-level FIFO buffer. Note: Do not perform Read-Modify-Write opera- tions (such as bit-oriented instructions) on the SPIxBUF register in either Standard or Enhanced Buffer mode.  2010-2014 Microchip Technology Inc. DS30009996G-page 221

PIC24FJ128GA310 FAMILY To set up the SPI module for the Standard Master mode To set up the SPI module for the Standard Slave mode of operation: of operation: 1. If using interrupts: 1. Clear the SPIxBUF register. a) Clear the SPIxIF bit in the respective IFSx 2. If using interrupts: register. a) Clear the SPIxIF bit in the respective IFSx b) Set the SPIxIE bit in the respective IECx register. register. b) Set the SPIxIE bit in the respective IECx c) Write the SPIxIP bits in the respective IPCx register. register to set the interrupt priority. c) Write the SPIxIP bits in the respective IPCx 2. Write the desired settings to the SPIxCON1 register to set the interrupt priority. and SPIxCON2 registers with MSTEN 3. Write the desired settings to the SPIxCON1 (SPIxCON1<5>) = 1. and SPIxCON2 registers with MSTEN 3. Clear the SPIROV bit (SPIxSTAT<6>). (SPIxCON1<5>) = 0. 4. Enable SPI operation by setting the SPIEN bit 4. Clear the SMP bit. (SPIxSTAT<15>). 5. If the CKE bit (SPIxCON1<8>) is set, then the 5. Write the data to be transmitted to the SPIxBUF SSEN bit (SPIxCON1<7>) must be set to enable register. Transmission (and reception) will start the SSx pin. as soon as data is written to the SPIxBUF 6. Clear the SPIROV bit (SPIxSTAT<6>). register. 7. Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). FIGURE 16-1: SPIx MODULE BLOCK DIAGRAM (STANDARD MODE) SCKx 1:1 to 1:8 1:1/4/16/64 Secondary Primary FCY Prescaler Prescaler SSx/FSYNCx Sync Control Select Control Clock Edge SPIxCON1<1:0> Shift Control SPIxCON1<4:2> SDOx Enable SDIx bit 0 Master Clock SPIxSR Transfer Transfer SPIxBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus DS30009996G-page 222  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY To set up the SPI module for the Enhanced Buffer To set up the SPI module for the Enhanced Buffer Master mode of operation: Slave mode of operation: 1. If using interrupts: 1. Clear the SPIxBUF register. a) Clear the SPIxIF bit in the respective IFSx 2. If using interrupts: register. a) Clear the SPIxIF bit in the respective IFSx b) Set the SPIxIE bit in the respective IECx register. register. b) Set the SPIxIE bit in the respective IECx c) Write the SPIxIP bits in the respective IPCx register. register. c) Write the SPIxIP bits in the respective IPCx 2. Write the desired settings to the SPIxCON1 register to set the interrupt priority. and SPIxCON2 registers with MSTEN 3. Write the desired settings to the SPIxCON1 (SPIxCON1<5>) = 1. and SPIxCON2 registers with MSTEN 3. Clear the SPIROV bit (SPIxSTAT<6>). (SPIxCON1<5>) = 0. 4. Select Enhanced Buffer mode by setting the 4. Clear the SMP bit. SPIBEN bit (SPIxCON2<0>). 5. If the CKE bit is set, then the SSEN bit must be 5. Enable SPI operation by setting the SPIEN bit set, thus enabling the SSx pin. (SPIxSTAT<15>). 6. Clear the SPIROV bit (SPIxSTAT<6>). 6. Write the data to be transmitted to the SPIxBUF 7. Select Enhanced Buffer mode by setting the register. Transmission (and reception) will start SPIBEN bit (SPIxCON2<0>). as soon as data is written to the SPIxBUF 8. Enable SPI operation by setting the SPIEN bit register. (SPIxSTAT<15>). FIGURE 16-2: SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE) SCKx 1:1 to 1:8 1:1/4/16/64 Secondary Primary FCY Prescaler Prescaler SSx/FSYNCx Sync Control Select Control Clock Edge SPIxCON1<1:0> Shift Control SPIxCON1<4:2> SDOx Enable SDIx bit 0 Master Clock SPIxSR Transfer Transfer 8-Level FIFO 8-Level FIFO Receive Buffer Transmit Buffer SPIXBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus  2010-2014 Microchip Technology Inc. DS30009996G-page 223

PIC24FJ128GA310 FAMILY REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC SPIEN(1) — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 bit 15 bit 8 R-0, HSC R/C-0, HS R-0, HSC R/W-0 R/W-0 R/W-0 R-0, HSC R-0, HSC SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown HSC = Hardware Settable/Clearable bit bit 15 SPIEN: SPIx Enable bit(1) 1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables module bit 14 Unimplemented: Read as ‘0’ bit 13 SPISIDL: SPIx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-11 Unimplemented: Read as ‘0’ bit 10-8 SPIBEC<2:0>: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode) Master mode: Number of SPI transfers pending. Slave mode: Number of SPI transfers unread. bit 7 SRMPT: SPIx Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode) 1 = SPIx Shift register is empty and ready to send or receive 0 = SPIx Shift register is not empty bit 6 SPIROV: SPIx Receive Overflow Flag bit 1 = A new byte/word is completely received and discarded; the user software has not read the previous data in the SPIxBUF register 0 = No overflow has occurred bit 5 SRXMPT: SPIx Receive FIFO Empty bit (valid in Enhanced Buffer mode) 1 = Receive FIFO is empty 0 = Receive FIFO is not empty bit 4-2 SISEL<2:0>: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode) 111 = Interrupt when the SPIx transmit buffer is full (SPITBF bit is set) 110 = Interrupt when the last bit is shifted into SPIxSR; as a result, the TX FIFO is empty 101 = Interrupt when the last bit is shifted out of SPIxSR; now the transmit is complete 100 = Interrupt when one data is shifted into the SPIxSR; as a result, the TX FIFO has one open spot 011 = Interrupt when the SPIx receive buffer is full (SPIRBF bit is set) 010 = Interrupt when the SPIx receive buffer is 3/4 or more full 001 = Interrupt when data is available in the receive buffer (SRMPT bit is set) 000 = Interrupt when the last data in the receive buffer is read; as a result, the buffer is empty (SRXMPT bit is set) Note 1: If SPIEN = 1, these functions must be assigned to available RPn/RPIn pins before use. See Section11.4 “Peripheral Pin Select (PPS)” for more information. DS30009996G-page 224  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED) bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit has not yet started, SPIxTXB is full 0 = Transmit has started, SPIxTXB is empty In Standard Buffer mode: Automatically set in hardware when the CPU writes to the SPIxBUF location, loading the SPIxTXB. Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR. In Enhanced Buffer mode: Automatically set in hardware when the CPU writes to the SPIxBUF location, loading the last available buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write. bit 0 SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive is complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty In Standard Buffer mode: Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB. In Enhanced Buffer mode: Automatically set in hardware when SPIx transfers data from the SPIxSR to the buffer, filling the last unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. Note 1: If SPIEN = 1, these functions must be assigned to available RPn/RPIn pins before use. See Section11.4 “Peripheral Pin Select (PPS)” for more information.  2010-2014 Microchip Technology Inc. DS30009996G-page 225

PIC24FJ128GA310 FAMILY REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK(1) DISSDO(2) MODE16 SMP CKE(3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEN(4) CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 DISSCK: Disable SCKx Pin bit (SPI Master modes only)(1) 1 = Internal SPI clock is disabled; pin functions as I/O 0 = Internal SPI clock is enabled bit 11 DISSDO: Disable SDOx Pin bit(2) 1 = SDOx pin is not used by the module; pin functions as I/O 0 = SDOx pin is controlled by the module bit 10 MODE16: Word/Byte Communication Select bit 1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits) bit 9 SMP: SPIx Data Input Sample Phase bit Master mode: 1 = Input data is sampled at the end of data output time 0 = Input data is sampled at the middle of data output time Slave mode: SMP must be cleared when SPIx is used in Slave mode. bit 8 CKE: SPIx Clock Edge Select bit(3) 1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6) 0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6) bit 7 SSEN: Slave Select Enable (Slave mode) bit(4) 1 = SSx pin is used for Slave mode 0 = SSx pin is not used by the module; pin is controlled by the port function bit 6 CKP: Clock Polarity Select bit 1 = Idle state for the clock is a high level; active state is a low level 0 = Idle state for the clock is a low level; active state is a high level bit 5 MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode Note 1: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section11.4 “Peripheral Pin Select (PPS)” for more information. 2: If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section11.4 “Peripheral Pin Select (PPS)” for more information. 3: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 4: If SSEN = 1, SSx must be configured to an available RPn/PRIn pin. See Section11.4 “Peripheral Pin Select (PPS)” for more information. DS30009996G-page 226  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 . . . 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section11.4 “Peripheral Pin Select (PPS)” for more information. 2: If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section11.4 “Peripheral Pin Select (PPS)” for more information. 3: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 4: If SSEN = 1, SSx must be configured to an available RPn/PRIn pin. See Section11.4 “Peripheral Pin Select (PPS)” for more information.  2010-2014 Microchip Technology Inc. DS30009996G-page 227

PIC24FJ128GA310 FAMILY REGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD SPIFPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — SPIFE SPIBEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support is enabled 0 = Framed SPIx support is disabled bit 14 SPIFSD: Frame Sync Pulse Direction Control on SSx Pin bit 1 = Frame sync pulse input (slave) 0 = Frame sync pulse output (master) bit 13 SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only) 1 = Frame sync pulse is active-high 0 = Frame sync pulse is active-low bit 12-2 Unimplemented: Read as ‘0’ bit 1 SPIFE: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with the first bit clock 0 = Frame sync pulse precedes the first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced buffer is enabled 0 = Enhanced buffer is disabled (Legacy mode) DS30009996G-page 228  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY FIGURE 16-3: SPIx MASTER/SLAVE CONNECTION (STANDARD MODE) Processor 1 (SPI Master) Processor 2 (SPI Slave) SDOx SDIx Serial Receive Buffer Serial Receive Buffer (SPIxRXB) (SPIxRXB)(2) Shift Register SDIx SDOx Shift Register (SPIxSR) (SPIxSR)(2) MSb LSb MSb LSb Serial Transmit Buffer Serial Transmit Buffer (SPIxTXB) (SPIxTXB)(2) Serial Clock SPIx Buffer SCKx SCKx SPIx Buffer (SPIxBUF)(2) (SPIxBUF)(2) SSx(1) MSTEN (SPIxCON1<5>) = 1) SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0 Note 1: Using the SSx pin in Slave mode of operation is optional. 2: User must write transmit data to read the received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory-mapped to SPIxBUF. FIGURE 16-4: SPIx MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES) Processor 1 (SPI Enhanced Buffer Master) Processor 2 (SPI Enhanced Buffer Slave) SDOx SDIx Shift Register SDIx SDOx Shift Register (SPIxSR) (SPIxSR) MSb LSb MSb LSb 8-Level FIFO Buffer 8-Level FIFO Buffer SPIx Buffer Serial Clock SPIx Buffer (SPIxBUF)(2) SCKx SCKx (SPIxBUF)(2) SSx SSx(1) MSTEN (SPIxCON1<5>) = 1 and SSEN (SPIxCON1<7>) = 1, SPIBEN (SPIxCON2<0>) = 1 MSTEN (SPIxCON1<5>) = 0 and SPIBEN (SPIxCON2<0>) = 1 Note 1: Using the SSx pin in Slave mode of operation is optional. 2: User must write transmit data to read the received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory-mapped to SPIxBUF.  2010-2014 Microchip Technology Inc. DS30009996G-page 229

PIC24FJ128GA310 FAMILY FIGURE 16-5: SPIx MASTER, FRAME MASTER CONNECTION DIAGRAM PIC24F Processor 2 (SPI Master, Frame Master) SDOx SDIx SDIx SDOx Serial Clock SCKx SCKx SSx SSx Frame Sync Pulse FIGURE 16-6: SPIx MASTER, FRAME SLAVE CONNECTION DIAGRAM PIC24F Processor 2 SPI Master, Frame Slave) SDOx SDIx SDIx SDOx Serial Clock SCKx SCKx SSx SSx Frame Sync Pulse FIGURE 16-7: SPIx SLAVE, FRAME MASTER CONNECTION DIAGRAM PIC24F Processor 2 (SPI Slave, Frame Master) SDOx SDIx SDIx SDOx Serial Clock SCKx SCKx SSx SSx Frame Sync. Pulse FIGURE 16-8: SPIx SLAVE, FRAME SLAVE CONNECTION DIAGRAM PIC24F Processor 2 (SPI Slave, Frame Slave) SDOx SDIx SDIx SDOx Serial Clock SCKx SCKx SSx SSx Frame Sync Pulse DS30009996G-page 230  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY EQUATION 16-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED(1) FCY FSCK = Primary Prescaler x Secondary Prescaler Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. TABLE 16-1: SAMPLE SCKx FREQUENCIES(1,2) Secondary Prescaler Settings FCY = 16 MHz 1:1 2:1 4:1 6:1 8:1 1:1 Invalid 8000 4000 2667 2000 4:1 4000 2000 1000 667 500 Primary Prescaler Settings 16:1 1000 500 250 167 125 64:1 250 125 63 42 31 FCY = 5 MHz 1:1 5000 2500 1250 833 625 4:1 1250 625 313 208 156 Primary Prescaler Settings 16:1 313 156 78 52 39 64:1 78 39 20 13 10 Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. 2: SCKx frequencies are shown in kHz.  2010-2014 Microchip Technology Inc. DS30009996G-page 231

PIC24FJ128GA310 FAMILY NOTES: DS30009996G-page 232  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 17.0 INTER-INTEGRATED 17.1 Communicating as a Master in a CIRCUIT™ (I2C™) Single Master Environment The details of sending a message in Master mode Note: This data sheet summarizes the features of depends on the communications protocol for the device this group of PIC24F devices. It is not being communicated with. Typically, the sequence of intended to be a comprehensive reference events is as follows: source. For more information, refer to “Inter-Integrated Circuit™ (I2C™)” 1. Assert a Start condition on SDAx and SCLx. (DS70000195) in the “dsPIC33/PIC24 Fam- 2. Send the I2C device address byte to the slave ily Reference Manual”. The information in with a write indication. this data sheet supersedes the information 3. Wait for and verify an Acknowledge from the in the FRM. slave. The Inter-Integrated Circuit™ (I2C™) module is a serial 4. Send the first data byte (sometimes known as interface useful for communicating with other periph- the command) to the slave. eral or microcontroller devices. These peripheral 5. Wait for and verify an Acknowledge from the devices may be serial EEPROMs, display drivers, ADC slave. Converters, etc. 6. Send the serial memory address low byte to the The I2C module supports these features: slave. 7. Repeat Steps 4 and 5 until all data bytes are • Independent master and slave logic sent. • 7-bit and 10-bit device addresses 8. Assert a Repeated Start condition on SDAx and • General call address as defined in the I2C protocol SCLx. • Clock stretching to provide delays for the 9. Send the device address byte to the slave with processor to respond to a slave data request a read indication. • Both 100kHz and 400kHz bus specifications 10. Wait for and verify an Acknowledge from the • Configurable address masking slave. • Multi-Master modes to prevent loss of messages 11. Enable master reception to receive serial in arbitration memory data. • Bus Repeater mode, allowing the acceptance of 12. Generate an ACK or NACK condition at the end all messages as a slave regardless of the address of a received byte of data. • Automatic SCL 13. Generate a Stop condition on SDAx and SCLx. A block diagram of the module is shown in Figure17-1.  2010-2014 Microchip Technology Inc. DS30009996G-page 233

PIC24FJ128GA310 FAMILY FIGURE 17-1: I2C™ BLOCK DIAGRAM Internal Data Bus I2CxRCV Read Shift SCLx Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation I2CxSTAT c ogi Read Collision ol L Write Detect ntr o C I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read Shift Clock Reload Control Write BRG Down Counter I2CxBRG Read TCY/2 DS30009996G-page 234  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 17.2 Setting Baud Rate When 17.3 Slave Address Masking Operating as a Bus Master The I2CxMSK register (Register17-3) designates To compute the Baud Rate Generator reload value, use address bit positions as “don’t care” for both 7-Bit and Equation17-1. 10-Bit Addressing modes. Setting a particular bit loca- tion (= 1) in the I2CxMSK register causes the slave EQUATION 17-1: COMPUTING BAUD RATE module to respond whether the corresponding address RELOAD VALUE(1,2) bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK is set to ‘00100000’, the slave module will detect both FSCL = FCY addresses, ‘0000000’ and ‘0100000’. FCY I2CxBRG + 1 + To enable address masking, the Intelligent Peripheral 10,000,000 or: Management Interface (IPMI) must be disabled by ( FCY FCY ) clearing the IPMIEN bit (I2CxCON<11>). I2CxBRG = – – 1 FSCL 10,000,000 Note: As a result of changes in the I2C™ proto- Note1: Based on FCY = FOSC/2; Doze mode and col, the addresses in Table17-2 are PLL are disabled. reserved and will not be Acknowledged in Slave mode. This includes any address 2: These clock rate values are for guidance mask settings that include any of these only. The actual clock rate can be affected addresses. by various system level parameters. The actual clock rate should be measured in its intended application. TABLE 17-1: I2C™ CLOCK RATES(1,2) I2CxBRG Value Required System FSCL FCY Actual FSCL (Decimal) (Hexadecimal) 100 kHz 16MHz 157 9D 100kHz 100kHz 8MHz 78 4E 100kHz 100kHz 4MHz 39 27 99kHz 400kHz 16MHz 37 25 404kHz 400kHz 8MHz 18 12 404kHz 400kHz 4MHz 9 9 385kHz 400kHz 2MHz 4 4 385kHz 1MHz 16MHz 13 D 1.026MHz 1MHz 8MHz 6 6 1.026MHz 1MHz 4MHz 3 3 0.909MHz Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. 2: These clock rate values are for guidance only. The actual clock rate can be affected by various system level parameters. The actual clock rate should be measured in its intended application. TABLE 17-2: I2C™ RESERVED ADDRESSES(1) Slave Address R/W Bit Description 0000 000 0 General Call Address(2) 0000 000 1 Start Byte 0000 001 x CBus Address 0000 01x x Reserved 0000 1xx x HS Mode Master Code 1111 0xx x 10-Bit Slave Upper Byte(3) 1111 1xx x Reserved Note 1: The address bits listed here will never cause an address match, independent of address mask settings. 2: The address will be Acknowledged only if GCEN=1. 3: A match on this address can only occur on the upper byte in 10-Bit Addressing mode.  2010-2014 Microchip Technology Inc. DS30009996G-page 235

PIC24FJ128GA310 FAMILY REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module; all I2C™ pins are controlled by port functions bit 14 Unimplemented: Read as ‘0’ bit 13 I2CSIDL: I2Cx Stop in Idle Mode bit 1 = Discontinues module operation when device enters an Idle mode 0 = Continues module operation in Idle mode bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Releases SCLx clock 0 = Holds SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear at the beginning of slave transmission. Hardware is clear at the end of slave reception. If STREN = 0: Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware is clear at the beginning of slave transmission. bit 11 IPMIEN: Intelligent Platform Management Interface (IPMI) Enable bit 1 = IPMI Support mode is enabled; all addresses are Acknowledged 0 = IPMI mode is disabled bit 10 A10M: 10-Bit Slave Addressing bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address bit 9 DISSLW: Disable Slew Rate Control bit 1 = Slew rate control is disabled 0 = Slew rate control is enabled bit 8 SMEN: SMBus Input Levels bit 1 = Enables I/O pin thresholds compliant with SMBus specifications 0 = Disables the SMBus input thresholds bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address is disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with the SCLREL bit. 1 = Enables software or receive clock stretching 0 = Disables software or receive clock stretching DS30009996G-page 236  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master; applicable during master receive) Value that will be transmitted when the software initiates an Acknowledge sequence. 1 = Sends NACK during Acknowledge 0 = Sends ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master; applicable during master receive) 1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits the ACKDT data bit. Hardware is clear at the end of the master Acknowledge sequence. 0 = Acknowledge sequence is not in progress bit 3 RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware is clear at the end of the eighth bit of the master receive data byte. 0 = Receive sequence is not in progress bit 2 PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiates Stop condition on the SDAx and SCLx pins. Hardware is clear at the end of the master Stop sequence. 0 = Stop condition is not in progress bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master) 1 = Initiates Repeated Start condition on the SDAx and SCLx pins. Hardware is clear at the end of the master Repeated Start sequence. 0 = Repeated Start condition is not in progress bit 0 SEN: Start Condition Enable bit (when operating as I2C master) 1 = Initiates Start condition on SDAx and SCLx pins. Hardware is clear at the end of the master Start sequence. 0 = Start condition is not in progress  2010-2014 Microchip Technology Inc. DS30009996G-page 237

PIC24FJ128GA310 FAMILY REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC IWCOL I2COV D/A P S R/W RBF TBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown HSC = Hardware Settable/Clearable bit bit 15 ACKSTAT: Acknowledge Status bit 1 = NACK was detected last 0 = ACK was detected last Hardware is set or cleared at the end of Acknowledge. bit 14 TRSTAT: Transmit Status bit (when operating as I2C™ master; applicable to master transmit operation.) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware is set at the beginning of master transmission; hardware is clear at the end of slave Acknowledge. bit 13-11 Unimplemented: Read as ‘0’ bit 10 BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware is set at the detection of a bus collision. bit 9 GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware is set when the address matches the general call address; hardware is clear at Stop detection. bit 8 ADD10: 10-Bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware is set at the match of the 2nd byte of the matched 10-bit address; hardware is clear at Stop detection. bit 7 IWCOL: Write Collision Detect bit 1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware is set at an occurrence of write to I2CxTRN while busy (cleared by software). bit 6 I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware is set at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software). bit 5 D/A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was a device address Hardware is clear at the device address match. Hardware is set after a transmission finishes or by reception of a slave byte. DS30009996G-page 238  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected. bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected. bit 2 R/W: Read/Write Information bit (when operating as I2C slave) 1 = Read: Indicates the data transfer is output from the slave 0 = Write: Indicates the data transfer is input to the slave Hardware is set or clear after the reception of an I2C device address byte. bit 1 RBF: Receive Buffer Full Status bit 1 = Receive is complete, I2CxRCV is full 0 = Receive is not complete, I2CxRCV is empty Hardware is set when I2CxRCV is written with the received byte; hardware is clear when the software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit is in progress, I2CxTRN is full 0 = Transmit is complete, I2CxTRN is empty Hardware is set when software writes to I2CxTRN; hardware is clear at the completion of data transmission. REGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK<9:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AMSK<9:0>: Mask for Address Bit x Select bits 1 = Enables masking for bit x of the incoming message address; bit match is not required in this position 0 = Disables masking for bit x; bit match is required in this position  2010-2014 Microchip Technology Inc. DS30009996G-page 239

PIC24FJ128GA310 FAMILY NOTES: DS30009996G-page 240  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 18.0 UNIVERSAL ASYNCHRONOUS • Fully Integrated Baud Rate Generator with 16-Bit RECEIVER TRANSMITTER Prescaler • Baud Rates Ranging from 15 bps to 1Mbps at (UART) 16MIPS Note: This data sheet summarizes the features of • 4-Deep, First-In-First-Out (FIFO) Transmit Data this group of PIC24F devices. It is not Buffer intended to be a comprehensive reference • 4-Deep FIFO Receive Data Buffer source. For more information, refer to • Parity, Framing and Buffer Overrun Error Detection “UART” (DS39708) in the “dsPIC33/PIC24 • Support for 9-bit mode with Address Detect Family Reference Manual”. The informa- (9th bit = 1) tion in this data sheet supersedes the • Transmit and Receive Interrupts information in the FRM. • Loopback mode for Diagnostic Support The Universal Asynchronous Receiver Transmitter • Support for Sync and Break Characters (UART) module is one of the serial I/O modules available • Supports Automatic Baud Rate Detection in the PIC24F device family. The UART is a full-duplex, • IrDA® Encoder and Decoder Logic asynchronous system that can communicate with peripheral devices, such as personal computers, • 16x Baud Clock Output for IrDA Support LIN/J2602, RS-232 and RS-485 interfaces. The module A simplified block diagram of the UART is shown in also supports a hardware flow control option with the Figure18-1. The UART module consists of these key UxCTS and UxRTS pins, and includes an IrDA® encoder important hardware elements: and decoder. • Baud Rate Generator The primary features of the UART module are: • Asynchronous Transmitter • Full-Duplex, 8 or 9-Bit Data Transmission through • Asynchronous Receiver the UxTX and UxRX Pins • Even, Odd or No Parity Options (for 8-bit data) • One or Two Stop bits • Hardware Flow Control Option with the UxCTS and UxRTS Pins FIGURE 18-1: UARTx SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA® Hardware Flow Control UxRTS/BCLKx UxCTS UARTx Receiver UxRX UARTx Transmitter UxTX Note: The UART inputs and outputs must all be assigned to available RPn/RPIn pins before use. See Section11.4 “Peripheral Pin Select (PPS)” for more information.  2010-2014 Microchip Technology Inc. DS30009996G-page 241

PIC24FJ128GA310 FAMILY 18.1 UART Baud Rate Generator (BRG) The maximum baud rate (BRGH = 0) possible is FCY/16 (for UxBRG=0) and the minimum baud rate The UART module includes a dedicated, 16-bit Baud possible is FCY/(16 * 65536). Rate Generator. The UxBRG register controls the Equation18-2 shows the formula for computation of period of a free-running, 16-bit timer. Equation18-1 the baud rate with BRGH = 1. shows the formula for computation of the baud rate with BRGH=0. EQUATION 18-2: UARTx BAUD RATE WITH EQUATION 18-1: UARTx BAUD RATE WITH BRGH = 1(1,2) BRGH = 0(1,2) FCY Baud Rate = FCY 4 • (UxBRG + 1) Baud Rate = 16 • (UxBRG + 1) FCY UxBRG = – 1 FCY 4 • Baud Rate UxBRG = – 1 16 • Baud Rate Note 1: FCY denotes the instruction cycle clock Note 1: FCY denotes the instruction cycle clock frequency. frequency (FOSC/2). 2: Based on FCY = FOSC/2; Doze mode 2: Based on FCY = FOSC/2; Doze mode and PLL are disabled. and PLL are disabled. Example18-1 shows the calculation of the baud rate The maximum baud rate (BRGH = 1) possible is FCY/4 error for the following conditions: (for UxBRG = 0) and the minimum baud rate possible is FCY/(4 * 65536). • FCY = 4 MHz Writing a new value to the UxBRG register causes the • Desired Baud Rate = 9600 BRG timer to be reset (cleared). This ensures the BRG does not wait for a timer overflow before generating the new baud rate. EXAMPLE 18-1: BAUD RATE ERROR CALCULATION (BRGH = 0)(1) Desired Baud Rate = FCY/(16 (BRGx + 1)) Solving for BRGx Value: BRGx = ((FCY/Desired Baud Rate)/16) – 1 BRGx = ((4000000/9600)/16) – 1 BRGx = 25 Calculated Baud Rate = 4000000/(16 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate) Desired Baud Rate = (9615 – 9600)/9600 = 0.16% Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. DS30009996G-page 242  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 18.2 Transmitting in 8-Bit Data Mode 18.5 Receiving in 8-Bit or 9-Bit Data Mode 1. Set up the UART: a) Write appropriate values for data, parity and 1. Set up the UART (as described in Section18.2 Stop bits. “Transmitting in 8-Bit Data Mode”). b) Write appropriate baud rate value to the 2. Enable the UART. UxBRG register. 3. A receive interrupt will be generated when one c) Set up transmit and receive interrupt enable or more data characters have been received as and priority bits. per interrupt control bit, URXISELx. 2. Enable the UART. 4. Read the OERR bit to determine if an overrun 3. Set the UTXEN bit (causes a transmit interrupt, error has occurred. The OERR bit must be reset two cycles after being set). in software. 4. Write a data byte to the lower byte of the 5. Read UxRXREG. UxTXREG word. The value will be immediately The act of reading the UxRXREG character will move transferred to the Transmit Shift Register (TSR) the next character to the top of the receive FIFO, and the serial bit stream will start shifting out including a new set of PERR and FERR values. with the next rising edge of the baud clock. 5. Alternatively, the data byte may be transferred 18.6 Operation of UxCTS and UxRTS while UTXEN = 0 and then the user may set Control Pins UTXEN. This will cause the serial bit stream to begin immediately because the baud clock will UARTx Clear-to-Send (UxCTS) and Request-to-Send start from a cleared state. (UxRTS) are the two hardware controlled pins that are 6. A transmit interrupt will be generated as per associated with the UART module. These two pins interrupt control bit, UTXISELx. allow the UART to operate in Simplex and Flow Control mode. They are implemented to control the transmis- 18.3 Transmitting in 9-Bit Data Mode sion and reception between the Data Terminal Equipment (DTE). The UEN<1:0> bits in the UxMODE 1. Set up the UART (as described in Section18.2 register configure these pins. “Transmitting in 8-Bit Data Mode”). 2. Enable the UART. 18.7 Infrared Support 3. Set the UTXEN bit (causes a transmit interrupt). The UART module provides two types of infrared UART 4. Write UxTXREG as a 16-bit value only. support: one is the IrDA clock output to support an 5. A word write to UxTXREG triggers the transfer external IrDA encoder and decoder device (legacy of the 9-bit data to the TSR. The serial bit stream module support), and the other is the full implementa- will start shifting out with the first rising edge of tion of the IrDA encoder and decoder. Note that the baud clock. because the IrDA modes require a 16x baud clock, they 6. A transmit interrupt will be generated as per the will only work when the BRGH bit (UxMODE<3>) is ‘0’. setting of control bit, UTXISELx. 18.7.1 IrDA CLOCK OUTPUT FOR 18.4 Break and Sync Transmit EXTERNAL IrDA SUPPORT Sequence To support external IrDA encoder and decoder devices, the BCLKx pin (same as the UxRTS pin) can be The following sequence will send a message frame configured to generate the 16x baud clock. With header, made up of a Break, followed by an auto-baud UEN<1:0> = 11, the BCLKx pin will output the 16x Sync byte. baud clock if the UART module is enabled. It can be 1. Configure the UART for the desired mode. used to support the IrDA codec chip. 2. Set UTXEN and UTXBRK to set up the Break 18.7.2 BUILT-IN IrDA ENCODER AND character. DECODER 3. Load the UxTXREG with a dummy character to initiate transmission (value is ignored). The UART has full implementation of the IrDA encoder 4. Write ‘55h’ to UxTXREG; this loads the Sync and decoder as part of the UART module. The built-in character into the transmit FIFO. IrDA encoder and decoder functionality is enabled using the IREN bit (UxMODE<12>). When enabled 5. After the Break has been sent, the UTXBRK bit (IREN = 1), the receive pin (UxRX) acts as the input is reset by hardware. The Sync character now from the infrared receiver. The transmit pin (UxTX) acts transmits. as the output to the infrared transmitter.  2010-2014 Microchip Technology Inc. DS30009996G-page 243

PIC24FJ128GA310 FAMILY REGISTER 18-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 UARTEN(1) — USIDL IREN(2) RTSMD — UEN1 UEN0 bit 15 bit 8 R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 UARTEN: UARTx Enable bit(1) 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> 0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption is minimal bit 14 Unimplemented: Read as ‘0’ bit 13 USIDL: UARTx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2) 1 = IrDA encoder and decoder are enabled 0 = IrDA encoder and decoder are disabled bit 11 RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin is in Simplex mode 0 = UxRTS pin is in Flow Control mode bit 10 Unimplemented: Read as ‘0’ bit 9-8 UEN<1:0>: UARTx Enable bits 11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin is controlled by port latches 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins are controlled by port latches bit 7 WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit 1 = UARTx will continue to sample the UxRX pin; interrupt is generated on the falling edge, bit is cleared in hardware on the following rising edge 0 = No wake-up is enabled bit 6 LPBACK: UARTx Loopback Mode Select bit 1 = Enables Loopback mode 0 = Loopback mode is disabled bit 5 ABAUD: Auto-Baud Enable bit 1 = Enables baud rate measurement on the next character – requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement is disabled or completed Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See Section11.4 “Peripheral Pin Select (PPS)” for more information. 2: This feature is only available for the 16x BRG mode (BRGH=0). DS30009996G-page 244  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 4 RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = High-Speed mode (4 BRG clock cycles per bit) 0 = Standard Speed mode (16 BRG clock cycles per bit) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See Section11.4 “Peripheral Pin Select (PPS)” for more information. 2: This feature is only available for the 16x BRG mode (BRGH=0).  2010-2014 Microchip Technology Inc. DS30009996G-page 245

PIC24FJ128GA310 FAMILY REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0, HSC R-1, HSC UTXISEL1 UTXINV(1) UTXISEL0 — UTXBRK UTXEN(2) UTXBF TRMT(3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1, HSC R-0, HSC R-0, HSC R/C-0, HS R-0, HSC URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown HS = Hardware Settable bit HC = Hardware Clearable bit bit 15,13 UTXISEL<1:0>: UARTx Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least one character open in the transmit buffer) bit 14 UTXINV: IrDA® Encoder Transmit Polarity Inversion bit(1) IREN = 0: 1 = UxTX is Idle ‘0’ 0 = UxTX is Idle ‘1’ IREN = 1: 1 = UxTX is Idle ‘1’ 0 = UxTX is Idle ‘0’ bit 12 Unimplemented: Read as ‘0’ bit 11 UTXBRK: UARTx Transmit Break bit 1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission is disabled or completed bit 10 UTXEN: UARTx Transmit Enable bit(2) 1 = Transmit is enabled, UxTX pin is controlled by UARTx 0 = Transmit is disabled, any pending transmission is aborted and the buffer is reset; UxTX pin is controlled by the port. bit 9 UTXBF: UARTx Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written bit 8 TRMT: Transmit Shift Register Empty bit (read-only)(3) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued Note 1: The value of the bit only affects the transmit properties of the module when the IrDA® encoder is enabled (IREN=1). 2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See Section11.4 “Peripheral Pin Select (PPS)” for more information. 3: The TRMT bit will be active only after two instruction cycles once the UTXREG is loaded. DS30009996G-page 246  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 7-6 URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits 11 = Interrupt is set on an RSR transfer, making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on an RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer; receive buffer has one or more characters bit 5 ADDEN: Address Character Detect bit (bit 8 of received data=1) 1 = Address Detect mode is enabled (if 9-bit mode is not selected, this does not take effect) 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed (clearing a previously set OERR bit (10 transition); will reset the receiver buffer and the RSR to the empty state bit 0 URXDA: UARTx Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: The value of the bit only affects the transmit properties of the module when the IrDA® encoder is enabled (IREN=1). 2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See Section11.4 “Peripheral Pin Select (PPS)” for more information. 3: The TRMT bit will be active only after two instruction cycles once the UTXREG is loaded.  2010-2014 Microchip Technology Inc. DS30009996G-page 247

PIC24FJ128GA310 FAMILY NOTES: DS30009996G-page 248  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 19.0 DATA SIGNAL MODULATOR The modulated output signal is generated by perform- ing a logical AND operation of both the carrier and Note: This data sheet summarizes the features of modulator signals and then it is provided to the MDOUT this group of PIC24F devices. It is not pin. Using this method, the DSM can generate the intended to be a comprehensive reference following types of key modulation schemes: source. For more information, refer to • Frequency Shift Keying (FSK) “Data Signal Modulator (DSM)” • Phase Shift Keying (PSK) (DS39744) in the “dsPIC33/PIC24 Family Reference Manual”. The information in this • On-Off Keying (OOK) data sheet supersedes the information in Figure19-1 shows a simplified block diagram of the the FRM. Data Signal Modulator peripheral. The Data Signal Modulator (DSM) allows the user to mix a digital data stream (the “modulator signal”) with a carrier signal to produce a modulated output. Both the carrier and the modulator signals are supplied to the DSM module, either internally from the output of a peripheral, or externally through an input pin. FIGURE 19-1: SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR MDCH<3:0> MDEN VSS MDCIN1 EN MDCIN2 Data Signal REFO Clock Modulator OC/PWM1 CARH OC/PWM2 OC/PWM3 OC/PWM4 CHPOL OC/PWM5 OC/PWM6 D OC/PWM7 SYNC MDMS<3:0> Q 1 MDBIT MDMIN SSP1 (SDO) 0 SSP2 (SDO) UART1 (TX) CHSYNC UART2 (TX) UART3 (TX) MOD UART4 (TX) MDOUT OC/PWM1 OC/PWM2 MDOE OC/PWM3 MDOPOL OC/PWM4 OC/PWM5 OC/PWM6 OC/PWM7 D MDCL<3:0> SYNC VSS Q 1 MDCIN1 MDCIN2 REFO Clock 0 OC/PWM1 OC/PWM2 CARL CLSYNC OC/PWM3 OC/PWM4 OC/PWM5 CLPOL OC/PWM6 OC/PWM7  2010-2014 Microchip Technology Inc. DS30009996G-page 249

PIC24FJ128GA310 FAMILY REGISTER 19-1: MDCON: MODULATOR CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 MDEN — MSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 — MDOE MDSLR MDOPOL — — — MDBIT(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 MDEN: Modulator Module Enable bit 1 = Modulator module is enabled and mixing input signals 0 = Modulator module is disabled and has no output bit 14 Unimplemented: Read as ‘0’ bit 13 MSIDL: Modulator Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 MDOE: Modulator Module Pin Output Enable bit 1 = Modulator pin output is enabled 0 = Modulator pin output is disabled bit 5 MDSLR: MDOUT Pin Slew Rate Limiting bit 1 = MDOUT pin slew rate limiting is enabled 0 = MDOUT pin slew rate limiting is disabled bit 4 MDOPOL: Modulator Output Polarity Select bit 1 = Modulator output signal is inverted 0 = Modulator output signal is not inverted bit 3-1 Unimplemented: Read as ‘0’ bit 0 MDBIT: Manual Modulation Input bit(1) 1 = Carrier is modulated 0 = Carrier is not modulated Note 1: The MDBIT must be selected as the modulation source (MDSRC<3:0> = 0000). DS30009996G-page 250  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 19-2: MDSRC: MODULATOR SOURCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-x U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x SODIS(1) — — — MS3(2) MS2(2) MS1(2) MS0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 SODIS: Modulation Source Output Disable bit(1) 1 = Output signal driving the peripheral output pin (selected by MDMS<3:0>) is disabled 0 = Output signal driving the peripheral output pin (selected by MDMS<3:0>) is enabled bit 6-4 Unimplemented: Read as ‘0’ bit 3-0 MS<3:0> Modulation Source Selection bits(2) 1111 = Unimplemented 1110 = Output Compare/PWM Module 7 output 1101 = Output Compare/PWM Module 6 output 1100 = Output Compare/PWM Module 5 output 1011 = Output Compare/PWM Module 4 output 1010 = Output Compare/PWM Module 3 output 1001 = Output Compare/PWM Module 2 output 1000 = Output Compare/PWM Module 1 output 0111 = UART4 TX output 0110 = UART3 TX output 0101 = UART2 TX output 0100 = UART1 TX output 0011 = SPI2 module output (SDO2) 0010 = SPI1 module output (SDO1) 0001 = Input on MDMIN pin 0000 = Manual modulation using MDBIT (MDCON<0>) Note 1: This bit is only affected by a POR. 2: These bits are not affected by a POR.  2010-2014 Microchip Technology Inc. DS30009996G-page 251

PIC24FJ128GA310 FAMILY REGISTER 19-3: MDCAR: MODULATOR CARRIER CONTROL REGISTER R/W-x R/W-x R/W-x U-0 R/W-x R/W-x R/W-x R/W-x CHODIS CHPOL CHSYNC — CH3(1) CH2(1) CH1(1) CH0(1) bit 15 bit 8 R/W-0 R/W-x R/W-x U-0 R/W-x R/W-x R/W-x R/W-x CLODIS CLPOL CLSYNC — CL3(1) CL2(1) CL1(1) CL0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CHODIS: Modulator High Carrier Output Disable bit 1 = Output signal driving the peripheral output pin (selected by CH<3:0>) is disabled 0 = Output signal driving the peripheral output pin is enabled bit 14 CHPOL: Modulator High Carrier Polarity Select bit 1 = Selected high carrier signal is inverted 0 = Selected high carrier signal is not inverted bit 13 CHSYNC: Modulator High Carrier Synchronization Enable bit 1 = Modulator waits for a falling edge on the high carrier before allowing a switch to the low carrier 0 = Modulator output is not synchronized to the high time carrier signal(1) bit 12 Unimplemented: Read as ‘0’ bit 11-8 CH<3:0> Modulator Data High Carrier Selection bits(1) 1111 . . . = Reserved 1011 1010 = Output Compare/PWM Module 7 output 1001 = Output Compare/PWM Module 6 output 1000 = Output Compare/PWM Module 5 output 0111 = Output Compare/PWM Module 4 output 0110 = Output Compare/PWM Module 3 output 0101 = Output Compare/PWM Module 2 output 0100 = Output Compare/PWM Module 1 output 0011 = Reference clock (REFO) output 0010 = Input on MDCIN2 pin 0001 = Input on MDCIN1 pin 0000 = VSS bit 7 CLODIS: Modulator Low Carrier Output Disable bit 1 = Output signal driving the peripheral output pin (selected by CL<3:0>) is disabled 0 = Output signal driving the peripheral output pin is enabled bit 6 CLPOL: Modulator Low Carrier Polarity Select bit 1 = Selected low carrier signal is inverted 0 = Selected low carrier signal is not inverted bit 5 CLSYNC: Modulator Low Carrier Synchronization Enable bit 1 = Modulator waits for a falling edge on the low carrier before allowing a switch to the high carrier 0 = Modulator output is not synchronized to the low time carrier signal(1) bit 4 Unimplemented: Read as ‘0’ bit 3-0 CL<3:0> Modulator Data Low Carrier Selection bits(1) Bit settings are identical to those for CH<3:0>. Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. DS30009996G-page 252  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 20.0 ENHANCED PARALLEL • Programmable Address/Data Multiplexing MASTER PORT (EPMP) • Programmable Address Wait States • Programmable Data Wait States (per Chip Select) Note: This data sheet summarizes the features of • Programmable Polarity on Control Signals this group of PIC24F devices. It is not (per Chip Select) intended to be a comprehensive reference • Legacy Parallel Slave Port Support source. For more information, refer to • Enhanced Parallel Slave Support: “Enhanced Parallel Master Port (EPMP)” (DS39730) in the “dsPIC33/PIC24 Family - Address Support Reference Manual”. The information in this - 4-Byte Deep Auto-Incrementing Buffer data sheet supersedes the information in the FRM. 20.1 Specific Package Variations The Enhanced Parallel Master Port (EPMP) module While all PIC24FJ128GA310 family devices implement provides a parallel, 4-bit (Master mode only), 8-bit the EPMP, I/O pin constraints place some limits on (Master and Slave modes) or 16-bit (Master mode only) 16-Bit Master mode operations in some package types. data bus interface to communicate with off-chip This is reflected in the number of dedicated Chip Select modules, such as memories, FIFOs, LCD controllers pins implemented and the number of dedicated and other microcontrollers. This module can serve as address lines that are available. The differences are either the master or the slave on the communication summarized in Table20-1. All available EPMP pin bus. functions are summarized in Table20-2. For EPMP Master modes, all external addresses are For 64-pin devices, the dedicated Chip Select pins mapped into the internal Extended Data Space (EDS). (PMCS1 and PMCS2) are not implemented. In addi- This is done by allocating a region of the EDS for each tion, only 16 address lines (PMA<15:0>) are available. Chip Select, and then assigning each Chip Select to a If required, PMA14 and PMA15 can be remapped to particular external resource, such as a memory or function as PMCS1 and PMCS2, respectively. external controller. This region should not be assigned For 80-pin devices, the dedicated PMCS2 pin is not to another device resource, such as RAM or SFRs. To implemented. It also only implements 16 address lines perform a write or read on an external resource, the (PMA<15:0>). If required, PMA15 can be remapped to CPU simply performs a write or read within the address function as PMCS2. range assigned for the EPMP. The memory space addressable by the device Key features of the EPMP module are: depends on the number of address lines available, as • Extended Data Space (EDS) Interface allows well as the number of Chip Select signals required for Direct Access from the CPU the application. Devices with lower pin counts are more • Up to 23 Programmable Address Lines affected by Chip Select requirements, as these take • Up to 2 Chip Select Lines away address lines. Table20-1 shows the maximum addressable range for each pin count. • Up to 2 Acknowledgment Lines (one per Chip Select) • 4-Bit, 8-Bit or 16-Bit-Wide Data Bus • Programmable Strobe Options (per Chip Select): - Individual Read and Write Strobes or; - Read/Write Strobe with Enable Strobe TABLE 20-1: EPMP FEATURE DIFFERENCES BY DEVICE PIN COUNT Dedicated Chip Select Address Range (bytes) Address Device Lines CS1 CS2 No CS 1 CS 2 CS PIC24FJXXXGA306 (64-pin) — — 16 64K 32K 16K PIC24FJXXXGA308 (80-pin) X — 16 64K 32K PIC24FJXXXGA310 (100-pin) X X 23 16M  2010-2014 Microchip Technology Inc. DS30009996G-page 253

PIC24FJ128GA310 FAMILY TABLE 20-2: ENHANCED PARALLEL MASTER PORT PIN DESCRIPTIONS Pin Name Type Description (Alternate Function) PMA<22:16> O Address Bus bits<22:16> O Address Bus bit 15 PMA<15> I/O Data Bus bit 15 (16-bit port with multiplexed addressing) (PMCS2) O Chip Select 2 (alternate location) O Address Bus bit 14 PMA<14> I/O Data Bus bit 14 (16-bit port with multiplexed addressing) (PMCS1) O Chip Select 1 (alternate location) O Address Bus bits<13:8> PMA<13:8> I/O Data Bus bits<13:8> (16-bit port with multiplexed addressing) PMA<7:3> O Address Bus bits<7:3> PMA<2> O Address Bus bit 2 (PMALU) O Address Latch Upper Strobe for Multiplexed Address PMA<1> I/O Address Bus bit 1 (PMALH) O Address Latch High Strobe for Multiplexed Address PMA<0> I/O Address Bus bit 0 (PMALL) O Address Latch Low Strobe for Multiplexed Address PMD<15:8> I/O Data Bus bits<15:8> (demultiplexed addressing) I/O Data Bus bits<7:4> PMD<7:4> O Address Bus bits<7:4> (4-bit port with 1-phase multiplexed addressing) PMD<3:0> I/O Data Bus bits<3:0> PMCS1(1) I/O Chip Select 1 PMCS2(2) O Chip Select 2 PMWR I/O Write Strobe(3) (PMENB) I/O Enable Signal(3) PMRD I/O Read Strobe(3) (PMRD/PMWR) I/O Read/Write Signal(3) PMBE1 O Byte Indicator PMBE0 O Nibble or Byte Indicator PMACK1 I Acknowledgment Signal 1 PMACK2 I Acknowledgment Signal 2 Note 1: These pins are implemented in 80-pin and 100-pin devices only. 2: These pins are implemented in 100-pin devices only. 3: Signal function depends on the setting of the MODE<1:0> and SM bits (PMCON1<9:8> and PMCSxCF<8>). DS30009996G-page 254  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 20-1: PMCON1: EPMP CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 PMPEN — PSIDL ADRMUX1 ADRMUX0 — MODE1 MODE0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 CSF1 CSF0 ALP ALMODE — BUSKEEP IRQM1 IRQM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PMPEN: Parallel Master Port Enable bit 1 = EPMP is enabled 0 = EPMP is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 PSIDL: Parallel Master Port Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits 11 = Lower address bits are multiplexed with data bits using 3 address phases 10 = Lower address bits are multiplexed with data bits using 2 address phases 01 = Lower address bits are multiplexed with data bits using 1 address phase 00 = Address and data appear on separate pins bit 10 Unimplemented: Read as ‘0’ bit 9-8 MODE<1:0>: Parallel Port Mode Select bits 11 = Master mode 10 = Enhanced PSP; pins used are PMRD, PMWR, PMCS, PMD<7:0> and PMA<1:0> 01 = Buffered PSP; pins used are PMRD, PMWR, PMCS and PMD<7:0> 00 = Legacy Parallel Slave Port; PMRD, PMWR, PMCS and PMD<7:0> pins are used bit 7-6 CSF<1:0>: Chip Select Function bits 11 = Reserved 10 = PMA<15> is used for Chip Select 2, PMA<14> is used for Chip Select 1 01 = PMA<15> is used for Chip Select 2, PMCS1 is used for Chip Select 1 00 = PMCS2 is used for Chip Select 2, PMCS1 is used for Chip Select 1 bit 5 ALP: Address Latch Polarity bit 1 = Active-high (PMALL, PMALH and PMALU) 0 = Active-low (PMALL, PMALH and PMALU) bit 4 ALMODE: Address Latch Strobe Mode bit 1 = Enables “smart” address strobes (each address phase is only present if the current access would cause a different address in the latch than the previous address) 0 = Disables “smart” address strobes bit 3 Unimplemented: Read as ‘0’ bit 2 BUSKEEP: Bus Keeper bit 1 = Data bus keeps its last value when not actively being driven 0 = Data bus is in a high-impedance state when not actively being driven bit 1-0 IRQM<1:0>: Interrupt Request Mode bits 11 = Interrupt is generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode), or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only) 10 = Reserved 01 = Interrupt is generated at the end of a read/write cycle 00 = No interrupt is generated  2010-2014 Microchip Technology Inc. DS30009996G-page 255

PIC24FJ128GA310 FAMILY REGISTER 20-2: PMCON2: EPMP CONTROL REGISTER 2 R-0, HSC U-0 R/C-0, HS R/C-0, HS U-0 U-0 U-0 U-0 BUSY — ERROR TIMEOUT — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RADDR23(1) RADDR22(1) RADDR21(1) RADDR20(1) RADDR19(1) RADDR18(1) RADDR17(1) RADDR16(1) bit 7 bit 0 Legend: HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown C = Clearable bit bit 15 BUSY: Busy bit (Master mode only) 1 = Port is busy 0 = Port is not busy bit 14 Unimplemented: Read as ‘0’ bit 13 ERROR: Error bit 1 = Transaction error (illegal transaction was requested) 0 = Transaction completed successfully bit 12 TIMEOUT: Time-out bit 1 = Transaction timed out 0 = Transaction completed successfully bit 11-8 Unimplemented: Read as ‘0’ bit 7-0 RADDR<23:16>: Parallel Master Port Reserved Address Space bits(1) Note 1: If RADDR<23:16> = 00000000, then the last EDS address for Chip Select 2 will be FFFFFFh. DS30009996G-page 256  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 20-3: PMCON3: EPMP CONTROL REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 PTWREN PTRDEN PTBE1EN PTBE0EN — AWAITM1 AWAITM0 AWAITE bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — PTEN22(1) PTEN21(1) PTEN20(1) PTEN19(1) PTEN18(1) PTEN17(1) PTEN16(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTWREN: Parallel Master Port Write/Enable Strobe Port Enable bit 1 = PMWR/PMENB port is enabled 0 = PMWR/PMENB port is disabled bit 14 PTRDEN: Parallel Master Port Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port is enabled 0 = PMRD/PMWR port is disabled bit 13 PTBE1EN: Parallel Master Port High Nibble/Byte Enable Port Enable bit 1 = PMBE1 port is enabled 0 = PMBE1 port is disabled bit 12 PTBE0EN: Parallel Master Port Low Nibble/Byte Enable Port Enable bit 1 = PMBE0 port is enabled 0 = PMBE0 port is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-9 AWAITM<1:0>: Address Latch Strobe Wait States bits 11 = Wait of 3½ TCY 10 = Wait of 2½ TCY 01 = Wait of 1½ TCY 00 = Wait of ½ TCY bit bit 8 AWAITE: Address Hold After Address Latch Strobe Wait States bits 1 = Wait of 1¼ TCY 0 = Wait of ¼ TCY bit 7 Unimplemented: Read as ‘0’ bit 6-0 PTEN<22:16>: EPMP Address Port Enable bits(1) 1 = PMA<22:16> function as EPMP address lines 0 = PMA<22:16> function as port I/Os Note 1: These bits are not available in 80 and 64-pin devices (PIC24FJXXXGA306, PIC24FJXXXGA308).  2010-2014 Microchip Technology Inc. DS30009996G-page 257

PIC24FJ128GA310 FAMILY REGISTER 20-4: PMCON4: EPMP CONTROL REGISTER 4 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTEN15: PMA15 Port Enable bit 1 = PMA15 functions as either Address Line 15 or Chip Select 2 0 = PMA15 functions as port I/O bit 14 PTEN14: PMA14 Port Enable bit 1 = PMA14 functions as either Address Line 14 or Chip Select 1 0 = PMA14 functions as port I/O bit 13-3 PTEN<13:3>: EPMP Address Port Enable bits 1 = PMA<13:3> function as EPMP address lines 0 = PMA<13:3> function as port I/Os bit 2-0 PTEN<2:0>: PMALU/PMALH/PMALL Strobe Enable bits 1 = PMA<2:0> function as either address lines or address latch strobes 0 = PMA<2:0> function as port I/Os DS30009996G-page 258  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 20-5: PMCSxCF: CHIP SELECT x CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 CSDIS CSP CSPTEN BEP — WRSP RDSP SM bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ACKP PTSZ1 PTSZ0 — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CSDIS: Chip Select x Disable bit 1 = Disables the Chip Select x functionality 0 = Enables the Chip Select x functionality bit 14 CSP: Chip Select x Polarity bit 1 = Active-high (PMCSx) 0 = Active-low (PMCSx) bit 13 CSPTEN: PMCSx Port Enable bit 1 = PMCSx port is enabled 0 = PMCSx port is disabled bit 12 BEP: Chip Select x Nibble/Byte Enable Polarity bit 1 = Nibble/byte enable is active-high (PMBE0, PMBE1) 0 = Nibble/byte enable is active-low (PMBE0, PMBE1) bit 11 Unimplemented: Read as ‘0’ bit 10 WRSP: Chip Select x Write Strobe Polarity bit For Slave modes and Master mode when SM = 0: 1 = Write strobe is active-high (PMWR) 0 = Write strobe is active-low (PMWR) For Master mode when SM = 1: 1 = Enable strobe is active-high (PMENB) 0 = Enable strobe is active-low (PMENB) bit 9 RDSP: Chip Select x Read Strobe Polarity bit For Slave modes and Master mode when SM = 0: 1 = Read strobe is active-high (PMRD) 0 = Read strobe is active-low (PMRD) For Master mode when SM = 1: 1 = Read/write strobe is active-high (PMRD/PMWR) 0 = Read/Write strobe is active-low (PMRD/PMWR) bit 8 SM: Chip Select x Strobe Mode bit 1 = Read/write and enable strobes (PMRD/PMWR and PMENB) 0 = Read and write strobes (PMRD and PMWR) bit 7 ACKP: Chip Select x Acknowledge Polarity bit 1 = ACK is active-high (PMACK1) 0 = ACK is active-low (PMACK1)  2010-2014 Microchip Technology Inc. DS30009996G-page 259

PIC24FJ128GA310 FAMILY REGISTER 20-5: PMCSxCF: CHIP SELECT x CONFIGURATION REGISTER (CONTINUED) bit 6-5 PTSZ<1:0>: Chip Select x Port Size bits 11 = Reserved 10 = 16-bit port size (PMD<15:0>) 01 = 4-bit port size (PMD<3:0>) 00 = 8-bit port size (PMD<7:0>) bit 4-0 Unimplemented: Read as ‘0’ REGISTER 20-6: PMCSxBS: CHIP SELECT x BASE ADDRESS REGISTER(2) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) BASE<23:16> bit 15 bit 8 R/W(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 BASE15 — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 BASE<23:15>: Chip Select x Base Address bits(1) bit 6-0 Unimplemented: Read as ‘0’ Note 1: The value at POR is 0080h for PMCS1BS and 0880h for PMCS2BS. 2: If the whole PMCS2BS register is written together as 0x0000, then the last EDS address for Chip Select 1 will be FFFFFFh. In this case, Chip Select 2 should not be used. PMCS1BS has no such feature. DS30009996G-page 260  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 20-7: PMCSxMD: CHIP SELECT x MODE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 ACKM1 ACKM0 AMWAIT2 AMWAIT1 AMWAIT0 — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DWAITB1 DWAITB0 DWAITM3 DWAITM2 DWAITM1 DWAITM0 DWAITE1 DWAITE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 ACKM<1:0>: Chip Select x Acknowledge Mode bits 11 = Reserved 10 = PMACKx is used to determine when a read/write operation is complete 01 = PMACKx is used to determine when a read/write operation is complete with time-out (If DWAITM<3:0> = 0000, the maximum time-out is 255 TCY or else it is DWAITM<3:0> cycles.) 00 = PMACKx is not used bit 13-11 AMWAIT<2:0>: Chip Select x Alternate Master Wait States bits 111 = Wait of 10 alternate master cycles . . . 001 = Wait of 4 alternate master cycles 000 = Wait of 3 alternate master cycles bit 10-8 Unimplemented: Read as ‘0’ bit 7-6 DWAITB<1:0>: Chip Select x Data Setup Before Read/Write Strobe Wait States bits 11 = Wait of 3¼ TCY 10 = Wait of 2¼ TCY 01 = Wait of 1¼ TCY 00 = Wait of ¼ TCY bit 5-2 DWAITM<3:0>: Chip Select x Data Read/Write Strobe Wait States bits For Write Operations: 1111 = Wait of 15½ TCY . . . 0001 = Wait of 1½ TCY 0000 = Wait of ½ TCY For Read Operations: 1111 = Wait of 15¾ TCY . . . 0001 = Wait of 1¾ TCY 0000 = Wait of ¾ TCY bit 1-0 DWAITE<1:0>: Chip Select x Data Hold After Read/Write Strobe Wait States bits For Write Operations: 11 = Wait of 3¼ TCY 10 = Wait of 2¼ TCY 01 = Wait of 1¼ TCY 00 = Wait of ¼ TCY For Read Operations: 11 = Wait of 3 TCY 10 = Wait of 2 TCY 01 = Wait of 1 TCY 00 = Wait of 0 TCY  2010-2014 Microchip Technology Inc. DS30009996G-page 261

PIC24FJ128GA310 FAMILY REGISTER 20-8: PMSTAT: EPMP STATUS REGISTER (SLAVE MODE ONLY) R-0, HSC R/W-0, HS U-0 U-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC IBF IBOV — — IB3F(1) IB2F(1) IB1F(1) IB0F(1) bit 15 bit 8 R-1, HSC R/W-0, HS U-0 U-0 R-1, HSC R-1, HSC R-1, HSC R-1, HSC OBE OBUF — — OB3E OB2E OB1E OB0E bit 7 bit 0 Legend: HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IBF: Input Buffer Full Status bit 1 = All writable Input Buffer registers are full 0 = Some or all of the writable Input Buffer registers are empty bit 14 IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full Input register occurred (must be cleared in software) 0 = No overflow occurred bit 13-12 Unimplemented: Read as ‘0’ bit 11-8 IB3F:IB0F: Input Buffer x Status Full bits(1) 1 = Input buffer contains unread data (reading the buffer will clear this bit) 0 = Input buffer does not contain unread data bit 7 OBE: Output Buffer Empty Status bit 1 = All readable Output Buffer registers are empty 0 = Some or all of the readable Output Buffer registers are full bit 6 OBUF: Output Buffer Underflow Status bit 1 = A read occurred from an empty Output register (must be cleared in software) 0 = No underflow occurred bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 OB3E:OB0E: Output Buffer x Status Empty bits 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains untransmitted data Note 1: Even though an individual bit represents the byte in the buffer, the bits corresponding to the word (Byte 0 and 1, or Byte 2 and 3) get cleared, even on byte reading. DS30009996G-page 262  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 20-9: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 Unimplemented: Read as ‘0’ bit 0 PMPTTL: EPMP Module TTL Input Buffer Select bit 1 = EPMP module inputs (PMDx, PMCS1) use TTL input buffers 0 = EPMP module inputs use Schmitt Trigger input buffers  2010-2014 Microchip Technology Inc. DS30009996G-page 263

PIC24FJ128GA310 FAMILY NOTES: DS30009996G-page 264  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 21.0 LIQUID CRYSTAL DISPLAY The module has these features: (LCD) CONTROLLER • Direct driving of LCD panel • Three LCD clock sources with selectable prescaler Note: This data sheet summarizes the features of • Up to eight commons: this group of PIC24F devices. It is not - Static (One common) intended to be a comprehensive reference source. For more information, refer to “Liq- - 1/2 multiplex (two commons) uid Crystal Display (LCD)” (DS30009740) - 1/3 multiplex (three commons) in the “dsPIC33/PIC24 Family Reference - 1/8 multiplex (eight commons) Manual”. The information in this data sheet • Ability to drive from 30 (in 64-pin devices) to supersedes the information in the FRM. 64(100-pin) segments, depending on the Multiplexing mode selected The Liquid Crystal Display (LCD) Controller generates the data and timing control required to directly drive a • Static, 1/2 or 1/3 LCD bias static or multiplexed LCD panel. In 100-pin devices • On-chip bias generator with dedicated charge (PIC24FJXXXGA310), the module can drive panels of pump to support a range of fixed and variable bias up to eight commons and up to 60 segments when 5 to options 8 commons are used, or up to 64 segments when 1 to • Internal resistors for bias voltage generation 4 commons are used. • Software contrast control for LCD using internal biasing A simplified block diagram of the module is shown in Figure21-1. FIGURE 21-1: LCD CONTROLLER MODULE BLOCK DIAGRAM Data Bus LCD DATA 32 x 16 (= 8 x 64) LCDDATA31 512 64 LCDDATA30 to . . 64 . SEG<63:0> LCDDATA1 MUX 16 LCDDATA0 Bias Voltage To I/O Pins Timing Control 8 LCDCON LCDPS LCDSEx COM<7:0> LCD Bias Generation LCDREG LCDREF Resistor Ladder FRC Oscillator LCD Clock LCD LPRC Oscillator SOSC Source Select Charge Pump (Secondary Oscillator)  2010-2014 Microchip Technology Inc. DS30009996G-page 265

PIC24FJ128GA310 FAMILY 21.1 Registers The LCD controller has up to 40 registers: • LCD Control Register (LCDCON) • LCD Charge Pump Control Register (LCDREG) • LCD Phase Register (LCDPS) • LCD Voltage Ladder Control Register (LCDREF) • Four LCD Segment Enable Registers (LCDSE3:LCDSE0) • Up to 32 LCD Data Registers (LCDDATA31:LCDDATA0) REGISTER 21-1: LCDCON: LCD CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 LCDEN — LCDSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SLPEN WERR CS1 CS0 LMUX2 LMUX1 LMUX0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 LCDEN: LCD Driver Enable bit 1 = LCD driver module is enabled 0 = LCD driver module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 LCDSIDL: Stop LCD Drive in CPU Idle Mode Control bit 1 = LCD driver halts in CPU Idle mode 0 = LCD driver continues to operate in CPU Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 SLPEN: LCD Driver Enable in Sleep mode bit 1 = LCD driver module is disabled in Sleep mode 0 = LCD driver module is enabled in Sleep mode bit 5 WERR: LCD Write Failed Error bit 1 = LCDDATAx register is written while WA bit (LCDPS<4>) = 0 (must be cleared in software) 0 = No LCD write error bit 4-3 CS<1:0>: Clock Source Select bits 00 = FRC 01 = LPRC 1x = SOSC DS30009996G-page 266  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 21-1: LCDCON: LCD CONTROL REGISTER (CONTINUED) bit 2-0 LMUX<2:0>: LCD Commons Select bits LMUX<2:0> Multiplex Bias 111 1/8 MUX (COM<7:0>) 1/3 110 1/7 MUX (COM<6:0>) 1/3 101 1/6 MUX (COM<5:0>) 1/3 100 1/5 MUX (COM<4:0>) 1/3 011 1/4 MUX (COM<3:0>) 1/3 010 1/3 MUX (COM<2:0>) 1/2 or 1/3 001 1/2 MUX (COM<1:0>) 1/2 or 1/3 000 Static (COM0) Static Note: For multiplex above 4 commons, COM4, COM5, COM6 and COM7 also have segment functionality. Therefore, if the COM is enabled in multiplexing, the segment will not be available on that pin.  2010-2014 Microchip Technology Inc. DS30009996G-page 267

PIC24FJ128GA310 FAMILY REGISTER 21-2: LCDREG: LCD CHARGE PUMP CONTROL REGISTER RW-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 CPEN(1) — — — — — — — bit 15 bit 8 U-0 U-0 RW-1 RW-1 RW-1 RW-1 RW-0 RW-0 — — BIAS2 BIAS1 BIAS0 MODE13 CKSEL1 CKSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CPEN: 3.6V Charge Pump Enable bit(1) 1 = The regulator generates the highest (3.6V) voltage 0 = Highest voltage in the system is supplied externally (AVDD) bit 14-6 Unimplemented: Read as ‘0’ bit 5-3 BIAS<2:0>: Regulator Voltage Output Control bits 111 = 3.60V peak (offset on LCDBIAS0 of 0V) 110 = 3.47V peak (offset on LCDBIAS0 of 0.13V) 101 = 3.34V peak (offset on LCDBIAS0 of 0.26V) 100 = 3.21V peak (offset on LCDBIAS0 of 0.39V) 011 = 3.08V peak (offset on LCDBIAS0 of 0.52V) 010 = 2.95V peak (offset on LCDBIAS0 of 0.65V) 001 = 2.82V peak (offset on LCDBIAS0 of 0.78V) 000 = 2.69V peak (offset on LCDBIAS0 of 0.91V) bit 2 MODE13: 1/3 LCD Bias Enable bit 1 = Regulator output supports 1/3 LCD Bias mode 0 = Regulator output supports Static LCD Bias mode bit 1-0 CLKSEL<1:0>: Regulator Clock Select Control bits 11 = LPRC 31 kHz 10 = 8 MHz FRC 01 = SOSC 00 = Disables regulator and floats regulator voltage output Note 1: When using the charge pump, the LCDBIASx pins and the VLCAP1/VLCAP2 pins should be made analog, and the respective TRISx bits should be set as inputs. DS30009996G-page 268  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 21-3: LCDPS: LCD PHASE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 WFT: Waveform Type Select bit 1 = Type-B waveform (phase changes on each frame boundary) 0 = Type-A waveform (phase changes within each common type) bit 6 BIASMD: Bias Mode Select bit When LMUX<2:0> = 000 or 011 through 111: 0 = Static Bias mode (do not set this bit to ‘1’) When LMUX<2:0> = 001 or 010: 1 = 1/2 Bias mode 0 = 1/3 Bias mode bit 5 LCDA: LCD Active Status bit 1 = LCD driver module is active 0 = LCD driver module is inactive bit 4 WA: LCD Write Allow Status bit 1 = Writes into the LCDDATAx registers are allowed 0 = Writes into the LCDDATAx registers are not allowed bit 3-0 LP<3:0>: LCD Prescaler Select bits 1111 = 1:16 1110 = 1:15 1101 = 1:14 1100 = 1:13 1011 = 1:12 1010 = 1:11 1001 = 1:10 1000 = 1:9 0111 = 1:8 0110 = 1:7 0101 = 1:6 0100 = 1:5 0011 = 1:4 0010 = 1:3 0001 = 1:2 0000 = 1:1  2010-2014 Microchip Technology Inc. DS30009996G-page 269

PIC24FJ128GA310 FAMILY REGISTER 21-4: LCDSEx: LCD SEGMENT x ENABLE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SE(n+15) SE(n+14) SE(n+13) SE(n+12) SE(n+11) SE(n+10) SE(n+9) SE(n+8) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SE(n+7) SE(n+6) SE(n+5) SE(n+4) SE(n+3) SE(n+2) SE(n+1) SE(n) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 SE(n + 15):SE(n): Segment Enable bits For LCDSE0: n = 0 For LCDSE1: n = 16 For LCDSE2: n = 32 For LCDSE3: n = 48(1) 1 = Segment function of the pin is enabled, digital I/O is disabled 0 = Segment function of the pin is disabled, digital I/O is enabled Note 1: For the SEG49 to work correctly, the JTAG needs to be disabled. REGISTER 21-5: LCDDATAx: LCD DATA x REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 S(n+15)Cy S(n+14)Cy S(n+13)Cy S(n+12)Cy S(n+11)Cy S(n+10)Cy S(n+9)Cy S(n+8)Cy bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 S(n+7)Cy S(n+6)Cy S(n+5)Cy S(n+4)Cy S(n+3)Cy S(n+2)Cy S(n+1)Cy S(n)Cy bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 S(n + 15)Cy:S(n)Cy: Pixel On bits For registers, LCDDATA0 through LCDDATA3: n = (16x), y = 0 For registers, LCDDATA4 through LCDDATA7: n = (16(x – 4)), y = 1 For registers, LCDDATA8 through LCDDATA11: n = (16(x – 8)), y = 2 For registers, LCDDATA12 through LCDDATA15: n = (16(x – 12)), y = 3 For registers, LCDDATA16 through LCDDATA19: n = (16(x – 16)), y = 4 For registers, LCDDATA20 through LCDDATA23: n = (16(x – 20)), y = 5 For registers, LCDDATA24 through LCDDATA27: n = (16(x – 24)), y = 6 For registers, LCDDATA28 through LCDDATA31: n = (16(x – 28)), y = 7 1 = Pixel is on 0 = Pixel is off DS30009996G-page 270  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 21-1: LCDDATA REGISTERS AND BITS FOR SEGMENT AND COM COMBINATIONS Segments COM Lines 0 to 15 16 to 31 32 to 47 48 to 64 LCDDATA0 LCDDATA1 LCDDATA2 LCDDATA3 0 S00C0:S15C0 S16C0:S31C0 S32C0:S47C0 S48C0:S63C0 LCDDATA4 LCDDATA5 LCDDATA6 LCDDATA7 1 S00C1:S15C1 S16C1:S31C1 S32C1:S47C1 S48C1:S63C1 LCDDATA8 LCDDATA9 LCDDATA10 LCDDATA11 2 S00C2:S15C2 S16C2:S31C2 S32C2:S47C2 S48C2:S63C2 LCDDATA12 LCDDATA13 LCDDATA14 LCDDATA15 3 S00C3:S15C3 S16C3:S31C3 S32C3:S47C3 S48C3:S63C3 LCDDATA16 LCDDATA17 LCDDATA18 LCDDATA19 4 S00C4:S15C4 S16C4:S31C4 S32C4:S47C4 S48C4:S59C4 LCDDATA20 LCDDATA21 LCDDATA22 LCDDATA23 5 S00C5:S15C5 S16C5:S31C5 S32C5:S47C5 S48C5:S69C5 LCDDATA24 LCDDATA25 LCDDATA26 LCDDATA27 6 S00C6:S15C6 S16C6:S31C6 S32C6:S47C6 S48C6:S59C6 LCDDATA28 LCDDATA29 LCDDATA30 LCDDATA31 7 S00C7:S15C7 S16C7:S31C7 S32C7:S47C7 S48C7:S59C7  2010-2014 Microchip Technology Inc. DS30009996G-page 271

PIC24FJ128GA310 FAMILY REGISTER 21-6: LCDREF: LCD REFERENCE LADDER CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LCDIRE — LCDCST2 LCDCST1 LCDCST0 VLCD3PE(1) VLCD2PE(1) VLCD1PE(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 LRLAP1 LRLAP0 LRLBP1 LRLBP0 — LRLAT2 LRLAT1 LRLAT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 LCDIRE: LCD Internal Reference Enable bit 1 = Internal LCD reference is enabled and connected to the internal contrast control circuit 0 = Internal LCD reference is disabled bit 14 Unimplemented: Read as ‘0’ bit 13-11 LCDCST<2:0>: LCD Contrast Control bits Selects the resistance of the LCD contrast control resistor ladder: 111 = Resistor ladder is at maximum resistance (minimum contrast) 110 = Resistor ladder is at 6/7th of maximum resistance 101 = Resistor ladder is at 5/7th of maximum resistance 100 = Resistor ladder is at 4/7th of maximum resistance 011 = Resistor ladder is at 3/7th of maximum resistance 010 = Resistor ladder is at 2/7th of maximum resistance 001 = Resistor ladder is at 1/7th of maximum resistance 000 = Minimum resistance (maximum contrast); resistor ladder is shorted bit 10 VLCD3PE: Bias 3 Pin Enable bit(1) 1 = Bias 3 level is connected to the external pin, LCDBIAS3 0 = Bias 3 level is internal (internal resistor ladder) bit 9 VLCD2PE: Bias 2 Pin Enable bit(1) 1 = Bias 2 level is connected to the external pin, LCDBIAS2 0 = Bias 2 level is internal (internal resistor ladder) bit 8 VLCD1PE: Bias 1 Pin Enable bit(1) 1 = Bias 1 level is connected to the external pin, LCDBIAS1 0 = Bias 1 level is internal (internal resistor ladder) bit 7-6 LRLAP<1:0>: LCD Reference Ladder A Time Power Control bits During Time Interval A: 11 = Internal LCD reference ladder is powered in High-Power mode 10 = Internal LCD reference ladder is powered in Medium Power mode 01 = Internal LCD reference ladder is powered in Low-Power mode 00 = Internal LCD reference ladder is powered down and unconnected bit 5-4 LRLBP<1:0>: LCD Reference Ladder B Time Power Control bits During Time Interval B: 11 = Internal LCD reference ladder is powered in High-Power mode 10 = Internal LCD reference ladder is powered in Medium Power mode 01 = Internal LCD reference ladder is powered in Low-Power mode 00 = Internal LCD reference ladder is powered down and unconnected bit 3 Unimplemented: Read as ‘0’ Note 1: When using the external resistor ladder biasing, the LCDBIASx pins should be made analog and the respective TRISx bits should be set as inputs. DS30009996G-page 272  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 21-6: LCDREF: LCD REFERENCE LADDER CONTROL REGISTER (CONTINUED) bit 2-0 LRLAT<2:0>: LCD Reference Ladder A Time Interval Control bits Sets the number of 32 clock counts when the A Time Interval Power mode is active. For Type-A Waveforms (WFT = 0): 111 = Internal LCD reference ladder is in A Power mode for 7 clocks and B Power mode for 9 clocks 110 = Internal LCD reference ladder is in A Power mode for 6 clocks and B Power mode for 10 clocks 101 = Internal LCD reference ladder is in A Power mode for 5 clocks and B Power mode for 11 clocks 100 = Internal LCD reference ladder is in A Power mode for 4 clocks and B Power mode for 12 clocks 011 = Internal LCD reference ladder is in A Power mode for 3 clocks and B Power mode for 13 clocks 010 = Internal LCD reference ladder is in A Power mode for 2 clocks and B Power mode for 14 clocks 001 = Internal LCD reference ladder is in A Power mode for 1 clock and B Power mode for 15 clocks 000 = Internal LCD reference ladder is always in B Power mode For Type-B Waveforms (WFT = 1): 111 = Internal LCD reference ladder is in A Power mode for 7 clocks and B Power mode for 25 clocks 110 = Internal LCD reference ladder is in A Power mode for 6 clocks and B Power mode for 26 clocks 101 = Internal LCD reference ladder is in A Power mode for 5 clocks and B Power mode for 27 clocks 100 = Internal LCD reference ladder is in A Power mode for 4 clocks and B Power mode for 28 clocks 011 = Internal LCD reference ladder is in A Power mode for 3 clocks and B Power mode for 29 clocks 010 = Internal LCD reference ladder is in A Power mode for 2 clocks and B Power mode for 30 clocks 001 = Internal LCD reference ladder is in A Power mode for 1 clock and B Power mode for 31 clocks 000 = Internal LCD reference ladder is always in B Power mode Note 1: When using the external resistor ladder biasing, the LCDBIASx pins should be made analog and the respective TRISx bits should be set as inputs.  2010-2014 Microchip Technology Inc. DS30009996G-page 273

PIC24FJ128GA310 FAMILY NOTES: DS30009996G-page 274  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 22.0 REAL-TIME CLOCK AND 22.1 RTCC Source Clock CALENDAR (RTCC) The user can select between the SOSC crystal oscillator, LPRC internal oscillator or an external Note: This data sheet summarizes the features of 50Hz/60Hz power line input as the clock reference for this group of PIC24F devices. It is not the RTCC module. This gives the user an option to intended to be a comprehensive reference trade off system cost, accuracy and power source. For more information on the consumption, based on the overall system needs. If Real-Time Clock and Calendar, refer to using SOSC for a time-sensitive application, do not “RTCC with External Power Control” enable the LCD pin (SEG17) adjacent to the SOSCI (DS39745) in the “dsPIC33/PIC24 Family pin. Reference Manual”. The information in this data sheet supersedes the information in Note: Do not enable the LCD segment pin, the FRM. SEG17 on RD0, if the SOSC is used for time-sensitive applications. Avoid The RTCC provides the user with a Real-Time Clock high-frequency switching adjacent to the and Calendar (RTCC) function that can be calibrated. SOSCO and SOSCI pins. Key features of the RTCC module are: • Operates in Deep Sleep mode • Selectable clock source • Provides hours, minutes and seconds using 24-hour format • Visibility of one half second period • Provides calendar – weekday, date, month and year • Alarm-configurable for half a second, one second, 10 seconds, one minute, 10 minutes, one hour, one day, one week, one month or one year • Alarm repeat with decrementing counter • Alarm with indefinite repeat chime • Year 2000 to 2099 leap year correction • BCD format for smaller software overhead • Optimized for long-term battery operation • User calibration of the 32.768 kHz clock crystal/ 32K INTRC frequency with periodic auto-adjust • Optimized for long term battery operation • Fractional second synchronization • Calibration to within ±2.64 seconds error per month • Calibrates up to 260 ppm of crystal error • Ability to periodically wake up external devices without CPU intervention (external power control) • Power control output for external circuit control • Calibration takes effect every 15 seconds • Runs from any one of the following: - External Real-Time Clock (RTC) of 32.768 kHz - Internal 31.25 kHz LPRC clock - 50 Hz or 60 Hz external input  2010-2014 Microchip Technology Inc. DS30009996G-page 275

PIC24FJ128GA310 FAMILY FIGURE 22-1: RTCC BLOCK DIAGRAM Input from SOSC/LPRC Oscillator or RTCC Clock Domain CPU Clock Domain External Source RCFGCAL RTCC Prescalers ALCFGRPT 0.5 Sec YEAR MTHDY RTCC Timer RTCVAL WKDYHR Alarm MINSEC Event Comparator ALMTHDY Alarm Registers with Masks ALRMVAL ALWDHR ALMINSEC Repeat Counter RTCOE RTCC Interrupt RTCOUT<1:0> RTCC Interrupt Logic Alarm Pulse 00 1s 01 Clock Source 10 RTCC Pin DS30009996G-page 276  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 22.2 RTCC Module Registers TABLE 22-2: ALRMVAL REGISTER MAPPING The RTCC module registers are organized into three categories: ALRMPTR Alarm Value Register Window • RTCC Control Registers <1:0> ALRMVAL<15:8> ALRMVAL<7:0> • RTCC Value Registers 00 ALRMMIN ALRMSEC • Alarm Value Registers 01 ALRMWD ALRMHR 22.2.1 REGISTER MAPPING 10 ALRMMNTH ALRMDAY To limit the register interface, the RTCC Timer and 11 — — Alarm Time registers are accessed through Considering that the 16-bit core does not distinguish corresponding register pointers. The RTCC Value between 8-bit and 16-bit read operations, the user must register window (RTCVALH and RTCVALL) uses the be aware that when reading either the ALRMVALH or RTCPTR bits (RCFGCAL<9:8>) to select the desired ALRMVALL bytes, the ALRMPTR<1:0> value will be Timer register pair (see Table22-1). decremented. The same applies to the RTCVALH or By writing the RTCVALH byte, the RTCC Pointer value, RTCVALL bytes with the RTCPTR<1:0> being the RTCPTR<1:0> bits decrement by one until they decremented. reach ‘00’. Once they reach ‘00’, the MINUTES and Note: This only applies to read operations and SECONDS value will be accessible through RTCVALH not write operations. and RTCVALL until the pointer value is manually changed. 22.2.2 WRITE LOCK TABLE 22-1: RTCVAL REGISTER MAPPING In order to perform a write to any of the RTCC Timer registers, the RTCWREN bit (RCFGCAL1<13>) must RTCC Value Register Window RTCPTR<1:0> be set (see Example22-1). RTCVAL<15:8> RTCVAL<7:0> Note: To avoid accidental writes to the timer, it is 00 MINUTES SECONDS recommended that the RTCWREN bit 01 WEEKDAY HOURS (RCFGCAL1<13>) is kept clear at any other time. For the RTCWREN bit to be 10 MONTH DAY set, there is only one instruction cycle time 11 — YEAR window allowed between the 55h/AA The Alarm Value register window (ALRMVALH and sequence and the setting of RTCWREN; ALRMVALL) uses the ALRMPTR bits (ALCFGRPT<9:8>) therefore, it is recommended that code to select the desired Alarm register pair (see Table22-2). follow the procedure in Example22-1. By writing the ALRMVALH byte, the Alarm Pointer 22.2.3 SELECTING RTCC CLOCK SOURCE value, ALRMPTR<1:0> bits, decrement by one until they reach ‘00’. Once they reach ‘00’, the ALRMMIN The clock source for the RTCC module can be selected and ALRMSEC value will be accessible through using the RTCLK<1:0> bits in the RTCPWC register. ALRMVALH and ALRMVALL until the pointer value is When the bits are set to ‘00’, the Secondary Oscillator manually changed. (SOSC) is used as the reference clock and when the bits are ‘01’, LPRC is used as the reference clock. When RTCLK<1:0> = 10 and 11, the external power line (50Hz and 60Hz) is used as the clock source. EXAMPLE 22-1: SETTING THE RTCWREN BIT asm volatile(“push w7”); asm volatile(“push w8”); asm volatile(“disi #5”); asm volatile(“mov #0x55, w7”); asm volatile(“mov w7, _NVMKEY”); asm volatile(“mov #0xAA, w8”); asm volatile(“mov w8, _NVMKEY”); asm volatile(“bset _RCFGCAL1, #13”); //set the RTCWREN bit asm volatile(“pop w8”); asm volatile(“pop w7”);  2010-2014 Microchip Technology Inc. DS30009996G-page 277

PIC24FJ128GA310 FAMILY 22.3 RTCC Control Registers REGISTER 22-1: RCFGCAL: RTCC CALIBRATION/CONFIGURATION REGISTER(1) R/W-0 U-0 R/W-0 R-0, HSC R-0, HSC R/W-0 R/W-0 R/W-0 RTCEN(2) — RTCWREN RTCSYNC HALFSEC(3) RTCOE RTCPTR1 RTCPTR0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 RTCEN: RTCC Enable bit(2) 1 = RTCC module is enabled 0 = RTCC module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 RTCWREN: RTCC Value Registers Write Enable bit 1 = RTCVALH and RTCVALL registers can be written to by the user 0 = RTCVALH and RTCVALL registers are locked out from being written to by the user bit 12 RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple resulting in an invalid data read. If the register is read twice and results in the same data, the data can be assumed to be valid. 0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple bit 11 HALFSEC: Half Second Status bit(3) 1 = Second half period of a second 0 = First half period of a second bit 10 RTCOE: RTCC Output Enable bit 1 = RTCC output is enabled 0 = RTCC output is disabled bit 9-8 RTCPTR<1:0>: RTCC Value Register Window Pointer bits Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers. The RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’. RTCVAL<15:8>: 11 = Reserved 10 = MONTH 01 = WEEKDAY 00 = MINUTES RTCVAL<7:0>: 11 = YEAR 10 = DAY 01 = HOURS 00 = SECONDS Note 1: The RCFGCAL register is only affected by a POR. 2: A write to the RTCEN bit is only allowed when RTCWREN=1. 3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register. DS30009996G-page 278  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 22-1: RCFGCAL: RTCC CALIBRATION/CONFIGURATION REGISTER(1) (CONTINUED) bit 7-0 CAL<7:0>: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 127 RTC clock pulses every 15 seconds . . . 01111111 = Minimum positive adjustment; adds 1 RTC clock pulse every 15 seconds 00000000 = No adjustment 11111111 = Minimum negative adjustment; subtracts 1 RTC clock pulse every 15 seconds . . . 10000000 = Maximum negative adjustment; subtracts 128 RTC clock pulses every 15 seconds Note 1: The RCFGCAL register is only affected by a POR. 2: A write to the RTCEN bit is only allowed when RTCWREN=1. 3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.  2010-2014 Microchip Technology Inc. DS30009996G-page 279

PIC24FJ128GA310 FAMILY REGISTER 22-2: RTCPWC: RTCC POWER CONTROL REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PWCEN PWCPOL PWCPRE PWSPRE RTCLK1(2) RTCLK0(2) RTCOUT1 RTCOUT0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PWCEN: Power Control Enable bit 1 = Power control is enabled 0 = Power control is disabled bit 14 PWCPOL: Power Control Enable bit 1 = Power control is enabled 0 = Power control is disabled bit 13 PWCPRE: Power Control/Stability Prescaler bits 1 = PWC stability window clock is divide-by-2 of the source RTCC clock 0 = PWC stability window clock is divide-by-1 of the source RTCC clock bit 12 PWSPRE: Power Control Sample Prescaler bits 1 = PWC sample window clock is divide-by-2 of the source RTCC clock 0 = PWC sample window clock is divide-by-1 of the source RTCC clock bit 11-10 RTCLK<1:0>: RTCC Clock Source Select bits(2) 11 = External power line (60 Hz) 10 = External power line source (50 Hz) 01 = Internal LPRC Oscillator 00 = External Secondary Oscillator (SOSC) bit 9-8 RTCOUT<1:0>: RTCC Output Source Select bits 11 = Power control 10 = RTCC clock 01 = RTCC seconds clock 00 = RTCC alarm pulse bit 7-0 Unimplemented: Read as ‘0’ Note 1: The RTCPWC register is only affected by a POR. 2: When a new value is written to these register bits, the lower half of the MINSEC register should also be written to properly reset the clock prescalers in the RTCC. DS30009996G-page 280  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 22-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0>=00h and CHIME=0) 0 = Alarm is disabled bit 14 CHIME: Chime Enable bit 1 = Chime is enabled; ARPT<7:0> bits are allowed to roll over from 00h to FFh 0 = Chime is disabled; ARPT<7:0> bits stop once they reach 00h bit 13-10 AMASK<3:0>: Alarm Mask Configuration bits 0000 = Every half second 0001 = Every second 0010 = Every 10 seconds 0011 = Every minute 0100 = Every 10 minutes 0101 = Every hour 0110 = Once a day 0111 = Once a week 1000 = Once a month 1001 = Once a year (except when configured for February 29th, once every 4 years) 101x = Reserved – do not use 11xx = Reserved – do not use bit 9-8 ALRMPTR<1:0>: Alarm Value Register Window Pointer bits Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL registers. The ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’. ALRMVAL<15:8>: 00 = ALRMMIN 01 = ALRMWD 10 = ALRMMNTH 11 = PWCSTAB ALRMVAL<7:0>: 00 = ALRMSEC 01 = ALRMHR 10 = ALRMDAY 11 = PWCSAMP bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times . . . 00000000 = Alarm will not repeat The counter decrements on any alarm event; it is prevented from rolling over from 00h to FFh unless CHIME=1.  2010-2014 Microchip Technology Inc. DS30009996G-page 281

PIC24FJ128GA310 FAMILY 22.3.1 RTCVAL REGISTER MAPPINGS REGISTER 22-4: YEAR: YEAR VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YRTEN3 YRTEN2 YRTEN2 YRTEN1 YRONE3 YRONE2 YRONE1 YRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-4 YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit bits Contains a value from 0 to 9. bit 3-0 YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to the YEAR register is only allowed when RTCWREN=1. REGISTER 22-5: MTHDY: MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of ‘0’ or ‘1’. bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from 0 to 3. bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. DS30009996G-page 282  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 22-6: WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. REGISTER 22-7: MINSEC: MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9.  2010-2014 Microchip Technology Inc. DS30009996G-page 283

PIC24FJ128GA310 FAMILY 22.3.2 ALRMVAL REGISTER MAPPINGS REGISTER 22-8: ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of ‘0’ or ‘1’. bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from 0 to 3. bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. REGISTER 22-9: ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. DS30009996G-page 284  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 22-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9.  2010-2014 Microchip Technology Inc. DS30009996G-page 285

PIC24FJ128GA310 FAMILY REGISTER 22-11: RTCCSWT: POWER CONTROL AND SAMPLE WINDOW TIMER REGISTER(1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x PWCSTAB7 PWCSTAB6 PWCSTAB5 PWCSTAB4 PWCSTAB3 PWCSTAB2 PWCSTAB1 PWCSTAB0 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x PWCSAMP7(2) PWCSAMP6(2) PWCSAMP5(2) PWCSAMP4(2) PWCSAMP3(2) PWCSAMP2(2) PWCSAMP1(2) PWCSAMP0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 PWCSTAB<7:0>: Power Control Stability Window Timer bits 11111111 = Stability Window is 255 TPWCCLK clock periods 11111110 = Stability Window is 254 TPWCCLK clock periods ... 00000001 = Stability Window is 1 TPWCCLK clock period 00000000 = No Stability Window; Sample Window starts when the alarm event triggers bit 7-0 PWCSAMP<7:0>: Power Control Sample Window Timer bits(2) 11111111 = Sample Window is always enabled, even when PWCEN = 0 11111110 = Sample Window is 254 TPWCCLK clock periods ... 00000001 = Sample Window is 1 TPWCCLK clock period 00000000 = No Sample Window Note 1: A write to this register is only allowed when RTCWREN=1. 2: The Sample Window always starts when the Stability Window timer expires, except when its initial value is 00h. DS30009996G-page 286  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 22.4 Calibration 22.5.1 CONFIGURING THE ALARM The real-time crystal input can be calibrated using the The alarm feature is enabled using the ALRMEN bit. periodic auto-adjust feature. When properly calibrated, This bit is cleared when an alarm is issued. Writes to the RTCC can provide an error of less than 3 seconds ALRMVAL should only take place when ALRMEN = 0. per month. This is accomplished by finding the number As shown in Figure22-2, the interval selection of the of error clock pulses and storing the value into the alarm is configured through the AMASKx bits lower half of the RCFGCAL register. The 8-bit signed (ALCFGRPT<13:10>). These bits determine which and value loaded into the lower half of RCFGCAL is how many digits of the alarm must match the clock multiplied by four and will either be added or subtracted value for the alarm to occur. from the RTCC timer, once every minute. Refer to the The alarm can also be configured to repeat based on a steps below for RTCC calibration: preconfigured interval. The amount of times this 1. Using another timer resource on the device, the occurs, once the alarm is enabled, is stored in the user must find the error of the 32.768kHz crystal. ARPT<7:0> bits (ALCFGRPT<7:0>). When the value 2. Once the error is known, it must be converted to of the ARPTx bits equals 00h and the CHIME bit the number of error clock pulses per minute. (ALCFGRPT<14>) is cleared, the repeat function is 3. a) If the oscillator is faster than ideal (negative disabled and only a single alarm will occur. The alarm result form Step 2), the RCFGCAL register value can be repeated, up to 255 times, by loading must be negative. This causes the specified ARPT<7:0> with FFh. number of clock pulses to be subtracted from After each alarm is issued, the value of the ARPTx bits the timer counter, once every minute. is decremented by one. Once the value has reached b) If the oscillator is slower than ideal (positive 00h, the alarm will be issued one last time, after which, result from Step 2), the RCFGCAL register value the ALRMEN bit will be cleared automatically and the must be positive. This causes the specified alarm will turn off. number of clock pulses to be subtracted from Indefinite repetition of the alarm can occur if the the timer counter, once every minute. CHIME bit = 1. Instead of the alarm being disabled when the value of the ARPTx bits reaches 00h, it rolls EQUATION 22-1: over to FFh and continues counting indefinitely while (Ideal Frequency† – Measured Frequency) * 60 = CHIME is set. Clocks per Minute 22.5.2 ALARM INTERRUPT † Ideal Frequency = 32,768 Hz At every alarm event, an interrupt is generated. In Writes to the lower half of the RCFGCAL register addition, an alarm pulse output is provided that should only occur when the timer is turned off, or operates at half the frequency of the alarm. This output immediately after the rising edge of the seconds pulse, is completely synchronous to the RTCC clock and can except when SECONDS = 00, 15, 30 or 45. This is due be used as a trigger clock to other peripherals. to the auto-adjust of the RTCC at 15 second intervals. Note: Changing any of the registers, other than Note: It is up to the user to include, in the error the RCFGCAL and ALCFGRPT registers, value, the initial error of the crystal: drift and the CHIME bit while the alarm is due to temperature and drift due to crystal enabled (ALRMEN = 1), can result in a aging. false alarm event leading to a false alarm interrupt. To avoid a false alarm event, the 22.5 Alarm timer and alarm values should only be changed while the alarm is disabled • Configurable from half second to one year (ALRMEN = 0). It is recommended that • Enabled using the ALRMEN bit the ALCFGRPT register and CHIME bit be (ALCFGRPT<15>) changed when RTCSYNC = 0. • One-time alarm and repeat alarm options available  2010-2014 Microchip Technology Inc. DS30009996G-page 287

PIC24FJ128GA310 FAMILY FIGURE 22-2: ALARM MASK SETTINGS Day of Alarm Mask Setting the (AMASK<3:0>) Week Month Day Hours Minutes Seconds 0000 - Every half second 0001 - Every second 0010 - Every 10 seconds s 0011 - Every minute s s 0100 - Every 10 minutes m s s 0101 - Every hour m m s s 0110 - Every day h h m m s s 0111 - Every week d h h m m s s 1000 - Every month d d h h m m s s 1001 - Every year(1) m m d d h h m m s s Note 1: Annually, except when configured for February 29. 22.6 Power Control 22.7 RTCC VBAT Operation The RTCC includes a power control feature that allows The RTCC can operate in VBAT mode when there is a the device to periodically wake-up an external device, power loss on the VDD pin. The RTCC will continue to wait for the device to be stable before sampling operate if the VBAT pin is powered on (it is usually wake-up events from that device, and then shut down connected to the battery). the external device. This can be done completely Note: It is recommended to connect the VBAT autonomously by the RTCC, without the need to wake pin to VDD if the VBAT mode is not used from the current lower power mode (Sleep, Deep (not connected to the battery). Sleep, etc.). To use this feature: The VBAT BOR can be enabled/disabled using the VBTBOR bit in the CW3 Configuration register 1. Enable the RTCC (RTCEN = 1). (CW3<7>). If the VBTBOR enable bit is cleared, the 2. Set the PWCEN bit (RTCPWC<15>). VBAT BOR is always disabled and there will be no indi- 3. Configure the RTCC pin to drive the PWC control cation of a VBAT BOR. If the VBTBOR bit is set, the signal (RTCOE = 1 and RTCOUT<1:0>=11). RTCC can receive a Reset and the RTCEN bit will get The polarity of the PWC control signal may be chosen cleared when the voltage reaches VBTRTC. using the PWCPOL bit (RTCPWC<14>). An active-low or active-high signal may be used with the appropriate external switch to turn on or off the power to one or more external devices. The active-low setting may also be used in conjunction with an open-drain setting on the RTCC pin, in order to drive the ground pin(s) of the external device directly (with the appropriate external VDD pull-up device), without the need for external switches. Finally, the CHIME bit should be set to enable the PWC periodicity. DS30009996G-page 288  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 23.0 32-BIT PROGRAMMABLE The 32-bit programmable CRC generator provides a CYCLIC REDUNDANCY CHECK hardware implemented method of quickly generating checksums for various networking and security (CRC) GENERATOR applications. It offers the following features: Note: This data sheet summarizes the features of • User-programmable CRC polynomial equation, this group of PIC24F devices. It is not up to 32 bits intended to be a comprehensive reference • Programmable shift direction (little or big-endian) source. For more information, refer to • Independent data and polynomial lengths “32-Bit Programmable Cyclic Redun- • Configurable interrupt output dancy Check (CRC)” (DS30009729) in • Data FIFO the “dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet Figure23-1 displays a simplified block diagram of the supersedes the information in the FRM. CRC generator. A simple version of the CRC shift engine is displayed in Figure23-2. FIGURE 23-1: CRC BLOCK DIAGRAM CRCDATH CRCDATL Variable FIFO FIFO Empty (4x32, 8x16 or 16x8) Event CRCISEL CRCWDATH CRCWDATL 1 CRC LENDIAN Interrupt 0 Shift Buffer 1 CRC Shift Engine 0 Shift Complete Event Shifter Clock 2 * FCY FIGURE 23-2: CRC SHIFT ENGINE DETAIL CRC Shift Engine CRCWDATH CRCWDATL Read/Write Bus X0 X1 Xn(1) Shift Buffer Data Bit 0 Bit 1 Bit n(1) Note 1: n = PLEN<4:1> + 1.  2010-2014 Microchip Technology Inc. DS30009996G-page 289

PIC24FJ128GA310 FAMILY 23.1 User Interface 23.1.2 DATA INTERFACE The module incorporates a FIFO that works with a 23.1.1 POLYNOMIAL INTERFACE variable data width. Input data width can be configured The CRC module can be programmed for CRC to any value between 1 and 32 bits using the polynomials of up to the 32nd order, using up to 32 bits. DWIDTH<4:0> bits (CRCCON2<12:8>). When the data width is greater than 15, the FIFO is 4 words deep. Polynomial length, which reflects the highest exponent When the DWIDTHx bits are between 15 and 8, the in the equation, is selected by the PLEN<4:0> bits FIFO is 8 words deep. When the DWIDTHx bits are (CRCCON2<4:0>). less than 8, the FIFO is 16 words deep. The CRCXORL and CRCXORH registers control which The data for which the CRC is to be calculated must exponent terms are included in the equation. Setting a first be written into the FIFO. Even if the data width is particular bit includes that exponent term in the equa- less than 8, the smallest data element that can be tion. Functionally, this includes an XOR operation on written into the FIFO is 1 byte. For example, if the the corresponding bit in the CRC engine. Clearing the DWIDTHx bits are 5, then the size of the data is bit disables the XOR. DWIDTH<4:0>+1 or 6. The data is written as a whole For example, consider two CRC polynomials, one a byte; the two unused upper bits are ignored by the 16-bit and the other a 32-bit equation. module. Once data is written into the MSb of the CRCDAT reg- EQUATION 23-1: 16-BIT, 32-BIT CRC isters (that is, the MSb as defined by the data width), POLYNOMIALS the value of the VWORD<4:0> bits (CRCCON1<12:8>) increments by one. For example, if the DWIDTHx bits X16 + X12 + X5 + 1 are 24, the VWORDx bits will increment when bit 7 of and CRCDATH is written. Therefore, CRCDATL must always be written to before CRCDATH. X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1 The CRC engine starts shifting data when the CRCGO bit is set and the value of the VWORDx bits is greater than zero. To program these polynomial into the CRC generator, Each word is copied out of the FIFO into a buffer regis- set the register bits, as shown in Table23-1. ter, which decrements the VWORDx bits. The data is then shifted out of the buffer. The CRC engine contin- Note that the appropriate positions are set to ‘1’ to indi- ues shifting at a rate of two bits per instruction cycle, cate that they are used in the equation (for example, until the VWORDx bits reach zero. This means that for X26 and X23). The ‘0’ bit required by the equation is a given data width, it takes half that number of instruc- always XORed; thus, X0 is a don’t care. For a poly- nomial of length 32, it is assumed that the 32nd bit will tions for each word to complete the calculation. For example, it takes 16 cycles to calculate the CRC for a be used. Therefore, the X<31:1> bits do not have the 32nd bit. single word of 32-bit data. When the VWORDx bits reach the maximum value for the configured value of the DWIDTHx bits (4, 8 or 16), the CRCFUL bit becomes set. When the VWORD bits reach zero, the CRCMPT bit becomes set. The FIFO is emptied and the VWORD<4:0> bits are set to ‘00000’ whenever CRCEN is ‘0’. At least one instruction cycle must pass after a write to CRCWDAT before a read of the VWORDx bits is done. TABLE 23-1: CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIALS Bit Values CRC Control Bits 16-Bit Polynomial 32-Bit Polynomial PLEN<4:0> 01111 11111 X<31:16> 0000 0000 0000 0001 0000 0100 1100 0001 X<15:0> 0001 0000 0010 000X 0001 1101 1011 011x DS30009996G-page 290  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 23.1.3 DATA SHIFT DIRECTION 3. Preload the FIFO by writing to the CRCDATL and CRCDATH registers until the CRCFUL bit is The LENDIAN bit (CRCCON1<3>) is used to control set or no data is left. the shift direction. By default, the CRC will shift data through the engine, MSb first. Setting LENDIAN (= 1) 4. Clear old results by writing 00h to CRCWDATL causes the CRC to shift data, LSb first. This setting and CRCWDATH. The CRCWDAT registers can allows better integration with various communication also be left unchanged to resume a previously schemes and removes the overhead of reversing the halted calculation. bit order in software. Note that this only changes the 5. Set the CRCGO bit to start calculation. direction the data is shifted into the engine. The result 6. Write remaining data into the FIFO as space of the CRC calculation will still be a normal CRC result, becomes available. not a reverse CRC result. 7. When the calculation completes, CRCGO is automatically cleared. An interrupt will be 23.1.4 INTERRUPT OPERATION generated if CRCISEL = 1. The module generates an interrupt that is configurable 8. Read CRCWDATL and CRCWDATH for the by the user for either of two conditions. result of the calculation. If CRCISEL is ‘0’, an interrupt is generated when the There are eight registers used to control programmable VWORD<4:0> bits make a transition from a value of ‘1’ CRC operation: to ‘0’. If CRCISEL is ‘1’, an interrupt will be generated • CRCCON1 after the CRC operation finishes and the module sets the CRCGO bit to ‘0’. Manually setting CRCGO to ‘0’ • CRCCON2 will not generate an interrupt. Note that when an • CRCXORL interrupt occurs, the CRC calculation would not yet be • CRCXORH complete. The module will still need (PLEN + 1)/2 clock • CRCDATL cycles after the interrupt is generated until the CRC • CRCDATH calculation is finished. • CRCWDATL 23.1.5 TYPICAL OPERATION • CRCWDATH To use the module for a typical CRC calculation: The CRCCON1 and CRCCON2 registers (Register23-1 and Register23-2) control the operation 1. Set the CRCEN bit to enable the module. of the module and configure the various settings. 2. Configure the module for desired operation: a) Program the desired polynomial using the The CRCXOR registers (Register23-3 and CRCXORL and CRCXORH registers, and the Register23-4) select the polynomial terms to be used PLEN<4:0> bits. in the CRC equation. The CRCDAT and CRCWDAT b) Configure the data width and shift direction registers are each register pairs that serve as buffers using the DWIDTHx and LENDIAN bits. for the double-word input data and CRC processed c) Select the desired Interrupt mode using the output, respectively. CRCISEL bit.  2010-2014 Microchip Technology Inc. DS30009996G-page 291

PIC24FJ128GA310 FAMILY REGISTER 23-1: CRCCON1: CRC CONTROL 1 REGISTER R/W-0 U-0 R/W-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC CRCEN — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 bit 15 bit 8 R-0, HSC R-1, HSC R/W-0 R/W-0, HC R/W-0 U-0 U-0 U-0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN — — — bit 7 bit 0 Legend: HC = Hardware Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CRCEN: CRC Enable bit 1 = Enables module 0 = Disables module; all state machines, pointers and CRCWDAT/CRCDATH registers reset; other SFRs are NOT reset bit 14 Unimplemented: Read as ‘0’ bit 13 CSIDL: CRC Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-8 VWORD<4:0>: Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN<4:0>  7 or 16 when PLEN<4:0> 7. bit 7 CRCFUL: CRC FIFO Full bit 1 = FIFO is full 0 = FIFO is not full bit 6 CRCMPT: CRC FIFO Empty bit 1 = FIFO is empty 0 = FIFO is not empty bit 5 CRCISEL: CRC Interrupt Selection bit 1 = Interrupt on FIFO is empty; the final word of data is still shifting through the CRC 0 = Interrupt on shift is complete and results are ready bit 4 CRCGO: Start CRC bit 1 = Starts CRC serial shifter 0 = CRC serial shifter is turned off bit 3 LENDIAN: Data Shift Direction Select bit 1 = Data word is shifted into the CRC, starting with the LSb (little endian) 0 = Data word is shifted into the CRC, starting with the MSb (big endian) bit 2-0 Unimplemented: Read as ‘0’ DS30009996G-page 292  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 23-2: CRCCON2: CRC CONTROL 2 REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — PLEN4 PLEN3 PLEN2 PLEN1 PLEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 DWIDTH<4:0>: Data Word Width Configuration bits Configures the width of the data word (Data Word Width – 1). bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 PLEN<4:0>: Polynomial Length Configuration bits Configures the length of the polynomial (Polynomial Length – 1). REGISTER 23-3: CRCXORL: CRC XOR POLYNOMIAL REGISTER, LOW BYTE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 X<7:1> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 X<15:1>: XOR of Polynomial Term xn Enable bits bit 0 Unimplemented: Read as ‘0’  2010-2014 Microchip Technology Inc. DS30009996G-page 293

PIC24FJ128GA310 FAMILY REGISTER 23-4: CRCXORH: CRC XOR POLYNOMIAL REGISTER, HIGH BYTE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 X<31:16>: XOR of Polynomial Term xn Enable bits DS30009996G-page 294  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 24.0 12-BIT A/D CONVERTER (ADC) 24.1 Basic Operation WITH THRESHOLD SCAN To perform a standard ADC conversion: Note: This data sheet summarizes the features 1. Configure the module: of this group of PIC24F devices. It is not a) Configure port pins as analog inputs by intended to be a comprehensive refer- setting the appropriate bits in the ANSx ence source. For more information on the registers (see Section11.2 “Configuring 12-Bit ADC, refer to “12-Bit A/D Analog Port Pins (ANSx)” for more Converter with Threshold Detect” information). (DS39739) in the “dsPIC33/PIC24 Family b) Select the voltage reference source to Reference Manual”. The information in this match expected range on analog inputs data sheet supersedes the information in (AD1CON2<15:13>). the FRM. c) Select the positive and negative multiplexer inputs for each channel (AD1CHS<15:0>). The 12-bit A/D Converter (ADC) has the following key features: d) Select the analog conversion clock to match the desired data rate with the processor • Successive Approximation Register (SAR) clock (AD1CON3<7:0>). Conversion e) Select the appropriate sample/conversion • Conversion Speeds of up to 200ksps sequence (AD1CON1<7:5> and • Up to 32 Analog Input Channels (internal and AD1CON3<12:8>). external) f) For Channel A scanning operations, select • Selectable 10-Bit (default) or 12-Bit Conversion the positive channels to be included Resolution (AD1CSSH and AD1CSSL registers). • Multiple Internal Reference Input Channels g) Select how conversion results are presented • External Voltage Reference Input Pins in the buffer (AD1CON1<9:8> bits and • Unipolar Differential Sample-and-Hold (S/H) AD1CON5 register). Amplifier h) Select the interrupt rate (AD1CON2<5:2>). • Automated Threshold Scan and Compare i) Turn on ADC module (AD1CON1<15>). Operation to Pre-Evaluate Conversion Results 2. Configure the ADC interrupt (if required): • Selectable Conversion Trigger Source a) Clear the AD1IF bit (IFS0<13>). • Fixed Length (one word per channel), b) Enable the AD1IE interrupt (IEC0<13>). Configurable Conversion Result Buffer c) Select the ADC interrupt priority • Four Options for Results Alignment (IPC3<6:4>). • Configurable Interrupt Generation 3. If the module is configured for manual sampling, • Enhanced DMA Operations with Indirect Address set the SAMP bit (AD1CON1<1>) to begin Generation sampling. • Operation During CPU Sleep and Idle modes The 12-bit ADC module is an enhanced version of the 10-bit module offered in earlier PIC24 devices. It is a Successive Approximation Register (SAR) Converter, enhanced with 12-bit resolution, a wide range of auto- matic sampling options, tighter integration with other analog modules and a configurable results buffer. It also includes a unique Threshold Detect feature that allows the module itself to make simple decisions based on the conversion results, and enhanced opera- tion with the DMA controller through Peripheral Indirect Addressing (PIA). A simplified block diagram for the module is shown in Figure24-1.  2010-2014 Microchip Technology Inc. DS30009996G-page 295

PIC24FJ128GA310 FAMILY FIGURE 24-1: 12-BIT ADC1 BLOCK DIAGRAM (PIC24FJ128GA310 FAMILY) Internal Data Bus AVDD VR+ AVSS ct e 16 el VREF+ SR VR- V VREF- Comparator VINH VR- VR+ S/H DAC AN0 VINL AN1 12-Bit SAR Conversion Logic AN2 Data Formatting VINH Extended DMA data AN14 A X AN15 U M ADC1BUF0: AN16(1) ADC1BUF25 VINL AD1CON1 AD1CON2 AD1CON3 AD1CON4 AN21(1) AD1CON5 AN22(1) AD1CHS AN23(1) UX B VINH AADD11CCHHIITTHL M VBG AD1CSSL VINL AD1CSSH VBG/2 AD1DMBUF VBG/6 VBAT/2 AVDD Sample Control Control Logic Conversion Control 16 AVSS Input MUX Control CTMU DMA Data Bus Note 1: AN16 through AN23 are implemented on 100-pin devices only. DS30009996G-page 296  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 24.2 Extended DMA Operations The IA is created by combining the base address within a channel buffer with three to five bits (depending on In addition to the standard features available on all the buffer size) to identify the channel. The base 12-bit ADC modules, PIC24FJ128GA310 family address ranges from zero to seven bits wide, depend- devices implement a limited extension of DMA func- ing on the buffer size. The address is right-padded with tionality. This extension adds features that work with a ‘0’ in order to maintain address alignment in the Data the device’s DMA controller to expand the ADC Space. The concatenated channel and base address module’s data storage abilities beyond the module’s bits are then left-padded with zeros, as necessary, to built-in buffer. complete the 11-bit IA. The Extended DMA functionality is controlled by the The IA is configured to auto-increment during write DMAEN bit (AD1CON1<11>); setting this bit enables operations by using the SMPIx bits (AD1CON2<6:2>). the functionality. The DMABM bit (AD1CON1<12>) As with PIA operations for any DMA-enabled module, configures how the DMA feature operates. the base destination address in the DMADST register 24.2.1 EXTENDED BUFFER MODE must be masked properly to accommodate the IA. Table24-1 shows how complete addresses are Extended Buffer mode (DMABM = 1) is useful for stor- formed. Note that the address masking varies for each ing the results of conversions on the upper channels buffer size option. Because of masking requirements, (i.e., 26 and above), which do not have their own some address ranges may not be available for certain memory-mapped buffers inside the ADC module. It can buffer sizes. Users should verify that the DMA base also be used to store the conversion results on any address is compatible with the buffer size selected. ADC channel in any implemented address in data RAM. Figure24-2 shows how the parts of the address define the buffer locations in data memory. In this case, the In Extended Buffer mode, all data from the ADC Buffer module “allocates” 256 bytes of data RAM (1000h to register, and channels above 26, is mapped into data 1100h) for 32 buffers of four words each. However, this RAM. Conversion data is written to a destination is not a hard allocation and nothing prevents these specified by the DMA controller, specifically by the locations from being used for other purposes. For DMADST register. This allows users to read the con- example, in the current case, if Analog Channels 1, 3 version results of channels above 26, which do not and 8 are being sampled and converted, conversion have their own memory-mapped ADC buffer locations, data will only be written to the channel buffers, starting from data memory. at 1008h, 1018h and 1040h. The holes in PIA buffer When using Extended Buffer mode, always set the space can be used for any other purpose. It is the BUFREGEN bit to disable FIFO operation. In addition, user’s responsibility to keep track of buffer locations disable the Split Buffer mode by clearing the BUFM bit. and preventing data overwrites. 24.2.2 PIA MODE 24.3 ADC Operation with VBAT When DMABM = 0, the ADC module is configured to One of the ADC channels is connected to the VBAT pin function with the DMA controller for Peripheral Indirect to monitor the VBAT voltage. This allows monitoring the Addressing (PIA) mode operations. In this mode, the VBAT pin voltage (battery voltage) with no external con- ADC module generates an 11-bit Indirect Address (IA). nection. The voltage measured, using the ADC VBAT This is ORed with the destination address in the DMA monitor, is VBAT/2. The voltage can be calculated by controller to define where the ADC conversion data will reading ADC = ((VBAT/2)/VDD) * 1024 for 10-bit ADC be stored. and ((VBAT/2)/VDD) * 4096 for 12-bit ADC. In PIA mode, the buffer space is created as a series of When using the VBAT ADC monitor: contiguous smaller buffers, one per analog channel. The size of the channel buffer determines how many analog • Connect the ADC channel to ground to discharge channels can be accommodated. The size of the buffer the sample capacitor. is selected by the DMABLx bits (AD1CON4<2:0>). The • Because of the high-impedance of VBAT, select size options range from a single word per buffer to higher sampling time to get an accurate reading. 128words. Each channel is allocated a buffer of this Since the VBAT pin is connected to the ADC during size, regardless of whether or not the channel will sampling, to prolong the VBAT battery life, the actually have conversion data. recommendation is to select the VBAT channel when needed.  2010-2014 Microchip Technology Inc. DS30009996G-page 297

PIC24FJ128GA310 FAMILY 24.4 Control Registers • AD1CSSH and AD1CSSL (Register24-10 and Register24-11) The 12-bit ADC is controlled through a total of • AD1CTMENH and AD1CTMENL (Register24-12 13registers: and Register24-13) • AD1CON1 through AD1CON5 (Register24-1 • AD1DMBUF (not shown) – The 16-bit conversion through Register24-5) buffer for Extended Buffer mode • AD1CS (Register24-6) • AD1CHITH and AD1CHITL (Register24-8 and Register24-9) TABLE 24-1: INDIRECT ADDRESS GENERATION IN PIA MODE Available Buffer Size per Generated Offset Allowable DMADST DMABL<2:0> Input Channel (words) Address (lower 11 bits) Addresses Channels 000 1 000 00cc ccc0 32 xxxx xxxx xx00 0000 001 2 000 0ccc ccn0 32 xxxx xxxx x000 0000 010 4 000 cccc cnn0 32 xxxx xxxx 0000 0000 011 8 00c cccc nnn0 32 xxxx xxx0 0000 0000 100 16 0cc cccn nnn0 32 xxxx xx00 0000 0000 101 32 ccc ccnn nnn0 32 xxxx x000 0000 0000 110 64 ccc cnnn nnn0 16 xxxx x000 0000 0000 111 128 ccc nnnn nnn0 8 xxxx x000 0000 0000 Legend: ccc = Channel number (three to five bits), n = Base buffer address (zero to seven bits), x = User-definable range of DMADST for base address, 0 = Masked bits of DMADST for IA. DS30009996G-page 298  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY FIGURE 24-2: EXAMPLE OF BUFFER ADDRESS GENERATION IN PIA MODE (4-WORD BUFFERS PER CHANNEL) ADC Module DMABL<2:0> = 010 (16-Word Buffer Size) Data RAM (PIA Mode) BBA Channel Ch 0 Buffer (4 Words) 1000h ccccc (0-31) Ch 1 Buffer (4 Words) 1008h 000 cccc cnn0 (IA) Ch 2 Buffer (4 Words) 1010h Ch 3 Buffer (4 Words) 1018h nn (0-3) Destination (Buffer Base Address) Range Ch 7 Buffer (4 Words) 1038h 1000h (DMA Base Address) Ch 8 Buffer (4 Words) 1040h Ch 29 Buffer (4 Words) 10F0h Ch 29 Buffer (4 Words) 10F8h DMADST Ch 31 Buffer (4 Words) 1100h DMA Channel Buffer Address Channel Address Address Mask DMA Base Address Ch 0, Word 0 1000h 0001 0000 0000 0000 Ch 0, Word 1 1002h 0001 0000 0000 0010 Ch 0, Word 2 1004h 0001 0000 0000 0100 Ch 0, Word 3 1006h 0001 0000 0000 0110 Ch 1, Word 0 1008h 0001 0000 0000 1000 Ch 1, Word 1 100Ah 0001 0000 0000 1010 Ch 1, Word 2 100Ch 0001 0000 0000 1100 Ch 1, Word 3 100Eh 0001 0000 0000 1110  2010-2014 Microchip Technology Inc. DS30009996G-page 299

PIC24FJ128GA310 FAMILY REGISTER 24-1: AD1CON1: ADC1 CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADON — ADSIDL DMABM(1) DMAEN MODE12 FORM1 FORM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0, HSC R/C-0, HSC SSRC3 SSRC2 SSRC1 SSRC0 — ASAM SAMP DONE bit 7 bit 0 Legend: C = Clearable bit U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: ADC Operating Mode bit 1 = ADC module is operating 0 = ADC module is off bit 14 Unimplemented: Read as ‘0’ bit 13 ADSIDL: ADC Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 DMABM: Extended DMA Buffer Mode Select bit(1) 1 = Extended Buffer mode: Buffer address is defined by the DMAnDST register 0 = PIA mode: Buffer addresses are defined by the DMA controller and AD1CON4<2:0> bit 11 DMAEN: Extended DMA/Buffer Enable bit 1 = Extended DMA and buffer features are enabled 0 = Extended features are disabled bit 10 MODE12: 12-Bit Operation Mode bit 1 = 12-bit ADC operation 0 = 10-bit ADC operation bit 9-8 FORM<1:0>: Data Output Format bits (see formats following) 11 = Fractional result, signed, left justified 10 = Absolute fractional result, unsigned, left justified 01 = Decimal result, signed, right justified 00 = Absolute decimal result, unsigned, right justified bit 7-4 SSRC<3:0>: Sample Clock Source Select bits 1xxx = Unimplemented, do not use 0111 = Internal counter ends sampling and starts conversion (auto-convert); do not use in Auto-Scan mode 0110 = Timer1 in Sleep (for Auto-Scan mode) 0101 = TMR1 0100 = CTMU 0011 = TMR5 0010 = TMR3 0001 = INT0 0000 = The SAMP bit must be cleared by software to start conversion bit 3 Unimplemented: Read as ‘0’ bit 2 ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately after last conversion; SAMP bit is auto-set 0 = Sampling begins when SAMP bit is manually set Note 1: This bit is only available when extended DMA/buffer features are available (DMAEN=1). DS30009996G-page 300  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 24-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED) bit 1 SAMP: ADC Sample Enable bit 1 = ADC Sample-and-Hold amplifiers are sampling 0 = ADC Sample-and-Hold amplifiers are holding bit 0 DONE: ADC Conversion Status bit 1 = ADC conversion cycle has completed 0 = ADC conversion has not started or is in progress Note 1: This bit is only available when extended DMA/buffer features are available (DMAEN=1).  2010-2014 Microchip Technology Inc. DS30009996G-page 301

PIC24FJ128GA310 FAMILY REGISTER 24-2: AD1CON2: ADC1 CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 PVCFG1 PVCFG0 NVCFG0 OFFCAL BUFREGEN CSCNA — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS(1) SMPI4 SMPI3 SMPI2 SMPI1 SMPI0 BUFM(1) ALTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 PVCFG<1:0>: ADC Converter Positive Voltage Reference Configuration bits 1x = Unimplemented, do not use 01 = External VREF+ 00 = AVDD bit 13 NVCFG0: ADC Converter Negative Voltage Reference Configuration bits 1 = External VREF- 0 = AVSS bit 12 OFFCAL: Offset Calibration Mode Select bit 1 = Inverting and non-inverting inputs of channel Sample-and-Hold are connected to AVSS 0 = Inverting and non-inverting inputs of channel Sample-and-Hold are connected to normal inputs bit 11 BUFREGEN: ADC Buffer Register Enable bit 1 = Conversion result is loaded into the buffer location determined by the converted channel 0 = ADC result buffer is treated as a FIFO bit 10 CSCNA: Scan Input Selections for CH0+ During Sample A bit 1 = Scans inputs 0 = Does not scan inputs bit 9-8 Unimplemented: Read as ‘0’ bit 7 BUFS: Buffer Fill Status bit(1) 1 = ADC is filling the upper half of the buffer; user should access data in the lower half 0 = ADC is filling the lower half of the buffer; user should access data in the upper half bit 6-2 SMPI<4:0>: Interrupt Sample/DMA Increment Rate Select bits When DMAEN = 1: 0001 = For 2-channel DMA ADC operation 0000 = For 1-channel DMA ADC operation When DMAEN = 0: Selects the number of sample/conversions per each interrupt. 11111 = Interrupt/address increment at the completion of conversion for each 32nd sample 11110 = Interrupt/address increment at the completion of conversion for each 31st sample  00001 = Interrupt/address increment at the completion of conversion for every other sample 00000 = Interrupt/address increment at the completion of conversion for each sample Note 1: These bits are only applicable when the buffer is used in FIFO mode (BUFREGEN=0). In addition, BUFS is only used when BUFM=1. DS30009996G-page 302  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 24-2: AD1CON2: ADC1 CONTROL REGISTER 2 (CONTINUED) bit 1 BUFM: Buffer Fill Mode Select bit(1) 1 = ADC buffer is two, 13-word buffers, starting at ADC1BUF0 and ADC1BUF12, and sequential conversions fill the buffers alternately (Split mode) 0 = ADC buffer is a single, 26-word buffer and fills sequentially from ADC1BUF0 (FIFO mode) bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A Note 1: These bits are only applicable when the buffer is used in FIFO mode (BUFREGEN=0). In addition, BUFS is only used when BUFM=1. REGISTER 24-3: AD1CON3: ADC1 CONTROL REGISTER 3 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC EXTSAM PUMPEN SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADRC: ADC Conversion Clock Source bit 1 = RC Clock 0 = Clock derived from system clock bit 14 EXTSAM: Extended Sampling Time bit 1 = ADC is still sampling after SAMP=0 0 = ADC is finished sampling bit 13 PUMPEN: Charge Pump Enable bit 1 = Charge pump for switches is enabled 0 = Charge pump for switches is disabled bit 12-8 SAMC<4:0>: Auto-Sample Time Select bits 11111 = 31 TAD  00001 = 1 TAD 00000 = 0 TAD bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits 11111111  = Reserved 01000000 00111111 = 64·TCY=TAD  00000001 = 2·TCY=TAD 00000000 = TCY=TAD  2010-2014 Microchip Technology Inc. DS30009996G-page 303

PIC24FJ128GA310 FAMILY REGISTER 24-4: AD1CON4: ADC1 CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — DMABL2(1) DMABL1(1) DMABL0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 DMABL<2:0>: DMA Buffer Size Select bits(1) 111 = Allocates 128 words of buffer to each analog input 110 = Allocates 64 words of buffer to each analog input 101 = Allocates 32 words of buffer to each analog input 100 = Allocates 16 words of buffer to each analog input 011 = Allocates 8 words of buffer to each analog input 010 = Allocates 4 words of buffer to each analog input 001 = Allocates 2 words of buffer to each analog input 000 = Allocates 1 word of buffer to each analog input Note 1: The DMABL<2:0> bits are only used when AD1CON1<11> = 1 and AD1CON<12> = 0; otherwise, their value is ignored. DS30009996G-page 304  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 24-5: AD1CON5: ADC1 CONTROL REGISTER 5 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 ASEN LPEN CTMREQ BGREQ — — ASINT1 ASINT0 bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — WM1 WM0 CM1 CM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ASEN: Auto-Scan Enable bit 1 = Auto-scan is enabled 0 = Auto-scan is disabled bit 14 LPEN: Low-Power Enable bit 1 = Low power is enabled after scan 0 = Full power is enabled after scan bit 13 CTMREQ: CTMU Request bit 1 = CTMU is enabled when the ADC is enabled and active 0 = CTMU is not enabled by the ADC bit 12 BGREQ: Band Gap Request bit 1 = Band gap is enabled when the ADC is enabled and active 0 = Band gap is not enabled by the ADC bit 11-10 Unimplemented: Read as ‘0’ bit 9-8 ASINT<1:0>: Auto-Scan (Threshold Detect) Interrupt Mode bits 11 = Interrupt after Threshold Detect sequence completed and valid compare has occurred 10 = Interrupt after valid compare has occurred 01 = Interrupt after Threshold Detect sequence completed 00 = No interrupt bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 WM<1:0>: Write Mode bits 11 = Reserved 10 = Auto-compare only (conversion results are not saved, but interrupts are generated when a valid match occurs, as defined by the CMx and ASINTx bits) 01 = Convert and save (conversion results are saved to locations as determined by the register bits when a match occurs, as defined by the CMx bits) 00 = Legacy operation (conversion data is saved to a location determined by the buffer register bits) bit 1-0 CM<1:0>: Compare Mode bits 11 = Outside Window mode (valid match occurs if the conversion result is outside of the window defined by the corresponding buffer pair) 10 = Inside Window mode (valid match occurs if the conversion result is inside the window defined by the corresponding buffer pair) 01 = Greater Than mode (valid match occurs if the result is greater than the value in the corresponding buffer register) 00 = Less Than mode (valid match occurs if the result is less than the value in the corresponding buffer register)  2010-2014 Microchip Technology Inc. DS30009996G-page 305

PIC24FJ128GA310 FAMILY REGISTER 24-6: AD1CHS: ADC1 SAMPLE SELECT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NB2 CH0NB1 CH0NB0 CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA2 CH0NA1 CH0NA0 CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 CH0NB<2:0>: Sample B Channel 0 Negative Input Select bits 1xx = Unimplemented 011 = Unimplemented 010 = AN1 001 = Unimplemented 000 = VREF-/AVSS bit 12-8 CH0SB<4:0>: Sample B Channel 0 Positive Input Select bits 11111 = VBAT/2(1) 11110 = AVDD(1) 11101 = AVSS(1) 11100 = Band gap reference (VBG)(1) 11011 = VBG/2(1) 11010 = VBG/6(1) 11001 = CTMU 11000 = CTMU temperature sensor input (does not require AD1CTMENH<8> to be set) 10111 = AN23(2) 10110 = AN22(2) 10101 = AN21(2) 10100 = AN20(2) 10011 = AN19(2) 10010 = AN18(2) 10001 = AN17(2) 10000 = AN16(2) 01111 = AN15 01110 = AN14 01101 = AN13 01100 = AN12 01011 = AN11 01010 = AN10 01001 = AN9 01000 = AN8 00111 = AN7 00110 = AN6 00101 = AN5 00100 = AN4 00011 = AN3 00010 = AN2 00001 = AN1 00000 = AN0 Note 1: These input channels do not have corresponding memory-mapped result buffers. 2: These channels are implemented in 100-pin devices only. DS30009996G-page 306  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 24-6: AD1CHS: ADC1 SAMPLE SELECT REGISTER (CONTINUED) bit 7-5 CH0NA<2:0>: Sample A Channel 0 Negative Input Select bits Same definitions as for CHONB<2:0>. bit 4-0 CH0SA<4:0>: Sample A Channel 0 Positive Input Select bits Same definitions as for CHOSB<4:0>. Note 1: These input channels do not have corresponding memory-mapped result buffers. 2: These channels are implemented in 100-pin devices only. REGISTER 24-7: ANCFG: ADC BAND GAP REFERENCE CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — VBG6EN VBG2EN VBGEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2 VBG6EN: ADC Input VBG/6 Enable bit 1 = Band gap voltage, divided by six reference (VBG/6), is enabled 0 = Band gap, divided by six reference (VBG/6), is disabled bit 1 VBG2EN: ADC Input VBG/2 Enable bit 1 = Band gap voltage, divided by two reference (VBG/2), is enabled 0 = Band gap, divided by two reference (VBG/2), is disabled bit 0 VBGEN: ADC Input VBG Enable bit 1 = Band gap voltage reference (VBG) is enabled 0 = Band gap reference (VBG) is disabled  2010-2014 Microchip Technology Inc. DS30009996G-page 307

PIC24FJ128GA310 FAMILY REGISTER 24-8: AD1CHITH: ADC1 SCAN COMPARE HIT REGISTER (HIGH WORD) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — CHH<25:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHH<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 CHH<25:16>: ADC Compare Hit bits If CM<1:0>=11: 1 = ADC Result Buffer n has been written with data or a match has occurred 0 = ADC Result Buffer n has not been written with data For All Other Values of CM<1:0>: 1 = A match has occurred on ADC Result Channel n 0 = No match has occurred on ADC Result Channel n REGISTER 24-9: AD1CHITL: ADC1 SCAN COMPARE HIT REGISTER (LOW WORD) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHH<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHH<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 CHH<15:0>: ADC Compare Hit bits If CM<1:0>=11: 1 = ADC Result Buffer n has been written with data or a match has occurred 0 = ADC Result Buffer n has not been written with data For All Other Values of CM<1:0>: 1 = A match has occurred on ADC Result Channel n 0 = No match has occurred on ADC Result Channel n DS30009996G-page 308  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 24-10: AD1CSSH: ADC1 INPUT SCAN SELECT REGISTER (HIGH WORD) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CSS<30:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-0 CSS<30:16>: ADC Input Scan Selection bits 1 = Includes corresponding channel for input scan 0 = Skips channel for input scan REGISTER 24-11: AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER (LOW WORD) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 CSS<15:0>: ADC Input Scan Selection bits 1 = Includes corresponding channel for input scan 0 = Skips channel for input scan  2010-2014 Microchip Technology Inc. DS30009996G-page 309

PIC24FJ128GA310 FAMILY REGISTER 24-12: AD1CTMENH: ADC1 CTMU ENABLE REGISTER (HIGH WORD)(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CTMEN<30:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMEN<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 CTMEN<31:16>: CTMU Enabled During Conversion bits 1 = CTMU is enabled and connected to the selected channel during conversion 0 = CTMU is not connected to this channel Note 1: The actual number of channels available depends on which channels are implemented on a specific device; refer to the device data sheet for details. Unimplemented channels are read as ‘0’. REGISTER 24-13: AD1CTMENL: ADC1 CTMU ENABL E REGISTER (LOW WORD)(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMEN<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMEN<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 CTMEN<15:0>: CTMU Enabled During Conversion bits 1 = CTMU is enabled and connected to the selected channel during conversion 0 = CTMU is not connected to this channel Note 1: The actual number of channels available depends on which channels are implemented on a specific device; refer to the device data sheet for details. Unimplemented channels are read as ‘0’. DS30009996G-page 310  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY FIGURE 24-3: 10-BIT ADC MODULE ANALOG INPUT MODEL RIC  250 Sampling Switch Rs ANx RSS RSS  3 k VA CPIN ILEAKAGE C= H4O.4L DpF 500 nA VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RSS = Sampling Switch Resistance CHOLD = Sample/Hold Capacitance (from DAC) Note: The CPIN value depends on the device package and is not tested. The effect of CPIN is negligible if Rs  5 k. EQUATION 24-1: ADC CONVERSION CLOCK PERIOD TAD = TCY (ADCS + 1) TAD ADCS = – 1 TCY Note: Based on TCY = 2/FOSC; Doze mode and PLL are disabled.  2010-2014 Microchip Technology Inc. DS30009996G-page 311

PIC24FJ128GA310 FAMILY FIGURE 24-4: 12-BIT ADC TRANSFER FUNCTION Output Code (Binary (Decimal)) 1111 1111 1111 (4095) 1111 1111 1110 (4094) 0010 0000 0011 (2051) 0010 0000 0010 (2050) 0010 0000 0001 (2049) 0010 0000 0000 (2048) 0001 1111 1111 (2047) 0001 1111 1110 (2046) 0001 1111 1101 (2045) 0000 0000 0001 (1) 0000 0000 0000 (0) Voltage Level 0 VR-V– VR+ R-V+R- 4096 2048 * (V– V)R+ R-V+R-4096 4095 * (V– V)R+ R-+R- 4096VR+ (V – V)INHINL V DS30009996G-page 312  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY FIGURE 24-5: 10-BIT ADC TRANSFER FUNCTION Output Code (Binary (Decimal)) 11 1111 1111 (1023) 11 1111 1110 (1022) 10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509) 00 0000 0001 (1) 00 0000 0000 (0) Voltage Level 0 VR-V– VR+ R-1024 V– V)R+ R-024 V– V)R+ R-024VR+ – V)NHINL V+R- 512 * (V+R-1 1023 * (+R- 1 (VI V  2010-2014 Microchip Technology Inc. DS30009996G-page 313

PIC24FJ128GA310 FAMILY NOTES: DS30009996G-page 314  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 25.0 TRIPLE COMPARATOR voltage reference input from one of the internal band MODULE gap references or the comparator voltage reference generator (VBG, VBG/2, VBG/6 and CVREF). Note: This data sheet summarizes the features of The comparator outputs may be directly connected to this group ofPIC24F devices. It is not the CxOUT pins. When the respective COE equals ‘1’, intended to be a comprehensive reference the I/O pad logic makes the unsynchronized output of source. For more information, refer to the comparator available on the pin. “Scalable Comparator Module” A simplified block diagram of the module in shown in (DS39734) in the “dsPIC33/PIC24 Family Figure25-1. Diagrams of the possible individual Reference Manual”. The information in this comparator configurations are shown in Figure25-2. data sheet supersedes the information in the FRM. Each comparator has its own control register, CMxCON (Register25-1), for enabling and configuring The triple comparator module provides three dual input its operation. The output and event status of all three comparators. The inputs to the comparator can be comparators is provided in the CMSTAT register configured to use any one of five external analog inputs (Register25-2). (CxINA, CxINB, CxINC, CxIND and VREF+) and a FIGURE 25-1: TRIPLE COMPARATOR MODULE BLOCK DIAGRAM EVPOL<1:0> CCH<1:0> Trigger/Interrupt CEVT Input CPOL Logic COE Select VIN- Logic C1 CXINB 00 VIN+ C1OUT Pin CXINC 01 COUT - 10 CXIND VBG 00 11 EVPOL<1:0> VBG/2 01 Trigger/Interrupt CEVT VBG/6 10 CPOL Logic COE 11 VIN- VREF+ C2 VIN+ C2OUT CVREFM<1:0>(1) COUT Pin EVPOL<1:0> 0 CXINA + 0 1 Trigger/Interrupt CEVT VREF+ Logic CPOL COE CVREF 1 VIN- C3 CVREFP(1) VIN+ C3OUT COUT Pin CREF Note 1: Refer to the CVRCON register (Register26-1) for bit details.  2010-2014 Microchip Technology Inc. DS30009996G-page 315

PIC24FJ128GA310 FAMILY FIGURE 25-2: INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 0 Comparator Off CEN=0, CREF=x, CCH<1:0>=xx COE VIN- Cx VIN+ Off (Read as ‘0’) CxOUT Pin Comparator CxINB > CxINA Compare Comparator CxINC > CxINA Compare CEN=1, CCH<1:0>=00, CVREFM<1:0> = xx CEN=1, CCH<1:0> =01, CVREFM<1:0> = xx COE COE CXINB VIN- CXINC VIN- Cx Cx VIN+ VIN+ CXINA CxOUT CXINA CxOUT Pin Pin Comparator CxIND > CxINA Compare Comparator VBG > CxINA Compare CEN=1, CCH<1:0> =10, CVREFM<1:0> = xx CEN=1, CCH<1:0> =11, CVREFM<1:0> = 00 COE COE CXIND VIN- VBG VIN- Cx Cx VIN+ VIN+ CXINA CxOUT CXINA CxOUT Pin Pin Comparator VBG > CxINA Compare Comparator VBG > CxINA Compare CEN=1, CCH<1:0> =11, CVREFM<1:0> = 01 CEN=1, CCH<1:0> =11, CVREFM<1:0> = 10 COE COE VBG/2 VIN- VBG/6 VIN- CXINA VIN+ Cx CxOUT CXINA VIN+ Cx CxOUT Pin Pin Comparator CxIND > CxINA Compare CEN=1, CCH<1:0> =11, CVREFM<1:0> = 11 COE VREF+ VIN- Cx VIN+ CXINA CxOUT Pin DS30009996G-page 316  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY FIGURE 25-3: INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 1 AND CVREFP = 0 Comparator CxINB > CVREF Compare Comparator CxINC > CVREF Compare CEN=1, CCH<1:0> =00, CVREFM<1 :0> = xx CEN=1, CCH<1:0> =01, CVREFM<1:0> = xx COE COE CXINB VIN- CXINC VIN- Cx Cx CVREF VIN+ CxOUT CVREF VIN+ CxOUT Pin Pin Comparator CxIND > CVREF Compare Comparator VBG > CVREF Compare CEN=1, CCH<1:0> =10, CVREFM<1:0> = xx CEN=1, CCH<1:0> =11, CVREFM<1:0> = 00 COE COE CXIND VIN- VBG VIN- CVREF VIN+ Cx CxOUT CVREF VIN+ Cx CxOUT Pin Pin Comparator VBG > CVREF Compare Comparator VBG > CVREF Compare CEN=1, CCH<1:0> =11, CVREFM<1:0> = 01 CEN=1, CCH<1:0> =11, CVREFM<1:0> = 10 COE COE VBG/2 VIN- VBG/6 VIN- CVREF VIN+ Cx CxOUT CVREF VIN+ Cx CxOUT Pin Pin Comparator CxIND > CVREF Compare CEN=1, CCH<1:0> =11, CVREFM<1:0> = 11 COE VREF+ VIN- Cx VIN+ CVREF CxOUT Pin FIGURE 25-4: INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 1 AND CVREFP = 1 Comparator CxINB > CVREF Compare Comparator CxINC > CVREF Compare CEN=1, CCH<1:0> =00, CVREFM<1:0> = xx CEN=1, CCH<1:0>=01, CVREFM<1:0> = xx COE COE CXINB VIN- CXINC VIN- Cx Cx VREF+ VIN+ CxOUT VREF+ VIN+ CxOUT Pin Pin Comparator CxIND > CVREF Compare Comparator VBG > CVREF Compare CEN=1, CCH<1:>=10, CVREFM<1:0> = xx CEN=1, CCH<1:0>=11, CVREFM<1:0> = 00 COE COE CXIND VIN- VBG VIN- VREF+ VIN+ Cx CxOUT VREF+ VIN+ Cx CxOUT Pin Pin Comparator VBG > CVREF Compare Comparator VBG > CVREF Compare CEN=1, CCH<1:0>=11, CVREFM<1:0> = 01 CEN=1, CCH<1:0> =11, CVREFM<1:0> = 10 COE COE VBG/2 VIN- VBG/6 VIN- VREF+ VIN+ Cx CxOUT VREF+ VIN+ Cx CxOUT Pin Pin  2010-2014 Microchip Technology Inc. DS30009996G-page 317

PIC24FJ128GA310 FAMILY R EGISTER 25-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0, HS R-0, HSC CEN COE CPOL — — — CEVT COUT bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 bit 7 bit 0 Legend: HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CEN: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 14 COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin 0 = Comparator output is internal only bit 13 CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 12-10 Unimplemented: Read as ‘0’ bit 9 CEVT: Comparator Event bit 1 = Comparator event that is defined by EVPOL<1:0> has occurred; subsequent triggers and interrupts are disabled until the bit is cleared 0 = Comparator event has not occurred bit 8 COUT: Comparator Output bit When CPOL = 0: 1 = VIN+ > VIN- 0 = VIN+ < VIN- When CPOL = 1: 1 = VIN+ < VIN- 0 = VIN+ > VIN- bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits 11 = Trigger/event/interrupt is generated on any change of the comparator output (while CEVT=0) 10 = Trigger/event/interrupt is generated on transition of the comparator output: If CPOL = 0 (non-inverted polarity): High-to-low transition only. If CPOL = 1 (inverted polarity): Low-to-high transition only. 01 = Trigger/event/interrupt is generated on transition of comparator output: If CPOL = 0 (non-inverted polarity): Low-to-high transition only. If CPOL = 1 (inverted polarity): High-to-low transition only. 00 = Trigger/event/interrupt generation is disabled bit 5 Unimplemented: Read as ‘0’ DS30009996G-page 318  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 25-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) (CONTINUED) bit 4 CREF: Comparator Reference Select bits (non-inverting input) 1 = Non-inverting input connects to the internal CVREF voltage 0 = Non-inverting input connects to the CxINA pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CCH<1:0>: Comparator Channel Select bits 11 = Inverting input of the comparator connects to the internal selectable reference voltage specified by the CVREFM<1:0> bits in the CVRCON register 10 = Inverting input of the comparator connects to the CxIND pin 01 = Inverting input of the comparator connects to the CxINC pin 00 = Inverting input of the comparator connects to the CxINB pin REGISTER 25-2: CMSTAT: COMPARATOR MODULE STATUS REGISTER R/W-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC CMIDL — — — — C3EVT C2EVT C1EVT bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC — — — — — C3OUT C2OUT C1OUT bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CMIDL: Comparator Stop in Idle Mode bit 1 = Discontinues operation of all comparators when device enters Idle mode 0 = Continues operation of all enabled comparators in Idle mode bit 14-11 Unimplemented: Read as ‘0’ bit 10 C3EVT: Comparator 3 Event Status bit (read-only) Shows the current event status of Comparator 3 (CM3CON<9>). bit 9 C2EVT: Comparator 2 Event Status bit (read-only) Shows the current event status of Comparator 2 (CM2CON<9>). bit 8 C1EVT: Comparator 1 Event Status bit (read-only) Shows the current event status of Comparator 1 (CM1CON<9>). bit 7-3 Unimplemented: Read as ‘0’ bit 2 C3OUT: Comparator 3 Output Status bit (read-only) Shows the current output of Comparator 3 (CM3CON<8>). bit 1 C2OUT: Comparator 2 Output Status bit (read-only) Shows the current output of Comparator 2 (CM2CON<8>). bit 0 C1OUT: Comparator 1 Output Status bit (read-only) Shows the current output of Comparator 1 (CM1CON<8>).  2010-2014 Microchip Technology Inc. DS30009996G-page 319

PIC24FJ128GA310 FAMILY NOTES: DS30009996G-page 320  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 26.0 COMPARATOR VOLTAGE 26.1 Configuring the Comparator REFERENCE Voltage Reference The voltage reference module is controlled through the Note: This data sheet summarizes the features of CVRCON register (Register26-1). The comparator this group of PIC24F devices. It is not voltage reference provides two ranges of output intended to be a comprehensive reference voltage, each with 16 distinct levels. The range to be source. For more information, refer to used is selected by the CVRR bit (CVRCON<5>). The “Dual Comparator Module” (DS39710) primary difference between the ranges is the size of the in the “dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet steps selected by the CVREF Selection bits (CVR<3:0>), with one range offering finer resolution. supersedes the information in the FRM. The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF-. The voltage source is selected by the CVRSS bit (CVRCON<4>). The settling time of the comparator voltage reference must be considered when changing the CVREF output. FIGURE 26-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 VREF+ AVDD CVRSS = 0 8R CVR<3:0> R CVREN R R R X U 16 Steps M 1 CVREF o- 6-t CVROE 1 R R CVREF Pin R CVRR 8R CVRSS = 1 VREF- CVRSS = 0 AVSS  2010-2014 Microchip Technology Inc. DS30009996G-page 321

PIC24FJ128GA310 FAMILY REGISTER 26-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CVREFP CVREFM1 CVREFM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 CVREFP: Comparator Voltage Reference Select bit (valid only when CREF is ‘1’) 1 = VREF+ is used as a reference voltage to the comparators 0 = The CVR (4-bit DAC) within this module provides the reference voltage to the comparators bit 9-8 CVREFM<1:0>: Band Gap Reference Source Select bits (valid only when CCH<1:0> = 11) 00 = Band gap voltage is provided as an input to the comparators 01 = Band gap voltage, divided by two, is provided as an input to the comparators 10 = Band gap voltage, divided by six, is provided as an input to the comparators 11 = VREF+ pin is provided as an input to the comparators bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit is powered on 0 = CVREF circuit is powered down bit 6 CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on the CVREF pin 0 = CVREF voltage level is disconnected from the CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step-size 0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step-size bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = VREF+ – VREF- 0 = Comparator reference source, CVRSRC = AVDD – AVSS bit 3-0 CVR<3:0>: Comparator VREF Value Selection 0  CVR<3:0>  15 bits When CVRR = 1: CVREF = (CVR<3:0>/24)  (CVRSRC) When CVRR = 0: CVREF = 1/4  (CVRSRC) + (CVR<3:0>/32)  (CVRSRC) DS30009996G-page 322  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 27.0 CHARGE TIME 27.1 Measuring Capacitance MEASUREMENT UNIT (CTMU) The CTMU module measures capacitance by generating an output pulse with a width equal to the Note: This data sheet summarizes the features of time between edge events on two separate input this group of PIC24F devices. It is not channels. The pulse edge events to both input intended to be a comprehensive reference channels can be selected from four sources: two source. For more information on the internal peripheral modules (OC1 and Timer1) and up Charge Measurement Unit, refer to to 13 external pins (CTEDG1 through CTEDG13). This “Charge Time Measurement Unit pulse is used with the module’s precision current (CTMU) with Threshold Detect” source to calculate capacitance according to the (DS39743) in the “dsPIC33/PIC24 Family relationship: Reference Manual”. The information in this data sheet supersedes the information in EQUATION 27-1: the FRM. dV The Charge Time Measurement Unit (CTMU) is a I = C------- dT flexible analog module that provides charge measurement, accurate differential time measurement For capacitance measurements, the ADC samples an between pulse sources and asynchronous pulse external capacitor (CAPP) on one of its input channels generation. Its key features include: after the CTMU output’s pulse. A precision resistor • Thirteen external edge input trigger sources (RPR) provides current source calibration on a second ADC channel. After the pulse ends, the converter • Polarity control for each edge source determines the voltage on the capacitor. The actual • Control of edge sequence calculation of capacitance is performed in software by • Control of response to edge levels or edge the application. transitions Figure27-1 illustrates the external connections used • Time measurement resolution of onenanosecond for capacitance measurements, and how the CTMU • Accurate current source suitable for capacitive and ADC modules are related in this application. This measurement example also shows the edge events coming from Together with other on-chip analog modules, the CTMU Timer1, but other configurations using external edge can be used to precisely measure time, measure sources are possible. A detailed discussion on capacitance, measure relative changes in capacitance measuring capacitance and time with the CTMU or generate output pulses that are independent of the module is provided in “Charge Time Measurement system clock. The CTMU module is ideal for interfacing Unit (CTMU)” (DS39724) in the “dsPIC33/PIC24 with capacitive-based touch sensors. Family Reference Manual”. The CTMU is controlled through three registers: CTMUCON1, CTMUCON2 and CTMUICON. CTMUCON1 enables the module and controls the mode of operation of the CTMU, as well as controlling edge sequencing. CTMUCON2 controls edge source selec- tion and edge source polarity selection. The CTMUICON register selects the current range of current source and trims the current.  2010-2014 Microchip Technology Inc. DS30009996G-page 323

PIC24FJ128GA310 FAMILY FIGURE 27-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT PIC24F Device Timer1 CTMU EDG1 Current Source EDG2 Output Pulse ADC Module ANx ANY CAPP RPR 27.2 Measuring Time When the module is configured for pulse generation delay by setting the TGEN bit (CTMUCON1<12>), the Time measurements on the pulse width can be similarly internal current source is connected to the B input of performed using the ADC module’s internal capacitor Comparator 2. A capacitor (CDELAY) is connected to (CAD) and a precision resistor for current calibration. the Comparator 2 pin, C2INB, and the comparator Figure27-2 displays the external connections used for voltage reference, CVREF, is connected to C2INA. time measurements, and how the CTMU and ADC CVREF is then configured for a specific trip point. The modules are related in this application. This example module begins to charge CDELAY when an edge event also shows both edge events coming from the external is detected. When CDELAY charges above the CVREF CTEDG pins, but other configurations using internal trip point, a pulse is output on CTPLS. The length of the edge sources are possible. pulse delay is determined by the value of CDELAY and the CVREF trip point. 27.3 Pulse Generation and Delay Figure27-3 illustrates the external connections for The CTMU module can also generate an output pulse pulse generation, as well as the relationship of the with edges that are not synchronous with the device’s different analog modules required. While CTED1 is system clock. More specifically, it can generate a pulse shown as the input pulse source, other options are with a programmable delay from an edge event input to available. A detailed discussion on pulse generation the module. with the CTMU module is provided in the “dsPIC33/ PIC24 Family Reference Manual”. DS30009996G-page 324  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY FIGURE 27-2: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT PIC24F Device CTMU CTEDX EDG1 Current Source CTEDX EDG2 Output Pulse ADC Module ANx CAD RPR FIGURE 27-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION PIC24F Device CTMU CTEDX EDG1 CTPLS Current Source Comparator C2INB - C2 CDELAY CVREF  2010-2014 Microchip Technology Inc. DS30009996G-page 325

PIC24FJ128GA310 FAMILY REGISTER 27-1: CTMUCON1: CTMU CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 CTMUSIDL: CTMU Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 TGEN: Time Generation Enable bit 1 = Enables edge delay generation 0 = Disables edge delay generation bit 11 EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked bit 10 EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed bit 9 IDISSEN: Analog Current Source Control bit 1 = Analog current source output is grounded 0 = Analog current source output is not grounded bit 8 CTTRIG: CTMU Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled bit 7-0 Unimplemented: Read as ‘0’ DS30009996G-page 326  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 27-2: CTMUCON2: CTMU CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG1MOD EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 EDG2MOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 EDG1MOD: Edge 1 Edge-Sensitive Select bit 1 = Input is edge-sensitive 0 = Input is level-sensitive bit 14 EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 is programmed for a positive edge response 0 = Edge 1 is programmed for a negative edge response bit 13-10 EDG1SEL<3:0>: Edge 1 Source Select bits 1111 = Edge 1 source is Comparator 3 output 1110 = Edge 1 source is Comparator 2 output 1101 = Edge 1 source is Comparator 1 output 1100 = Edge 1 source is IC3 1011 = Edge 1 source is IC2 1010 = Edge 1 source is IC1 1001 = Edge 1 source is CTED8 1000 = Edge 1 source is CTED7(1) 0111 = Edge 1 source is CTED6 0110 = Edge 1 source is CTED5 0101 = Edge 1 source is CTED4 0100 = Edge 1 source is CTED3(1) 0011 = Edge 1 source is CTED1 0010 = Edge 1 source is CTED2 0001 = Edge 1 source is OC1 0000 = Edge 1 source is Timer1 bit 9 EDG2STAT: Edge 2 Status bit Indicates the status of Edge 2 and can be written to control current source. 1 = Edge 2 has occurred 0 = Edge 2 has not occurred bit 8 EDG1STAT: Edge 1 Status bit Indicates the status of Edge 1 and can be written to control current source. 1 = Edge 1 has occurred 0 = Edge 1 has not occurred bit 7 EDG2MOD: Edge 2 Edge-Sensitive Select bit 1 = Input is edge-sensitive 0 = Input is level-sensitive bit 6 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 is programmed for a positive edge 0 = Edge 2 is programmed for a negative edge Note 1: Edge sources, CTED3, CTED7, CTED10 and CTED11, are available in 100-pin devices only.  2010-2014 Microchip Technology Inc. DS30009996G-page 327

PIC24FJ128GA310 FAMILY REGISTER 27-2: CTMUCON2: CTMU CONTROL REGISTER 2 (CONTINUED) bit 5-2 EDG2SEL<3:0>: Edge 2 Source Select bits 1111 = Edge 2 source is Comparator 3 output 1110 = Edge 2 source is Comparator 2 output 1101 = Edge 2 source is Comparator 1 output 1100 = Unimplemented Do not use 1011 = Edge 2 source is IC3 1010 = Edge 2 source is IC2 1001 = Edge 2 source is IC1 1000 = Edge 2 source is CTED13 0111 = Edge 2 source is CTED12 0110 = Edge 2 source is CTED11(1) 0101 = Edge 2 source is CTED10(1) 0100 = Edge 2 source is CTED9 0011 = Edge 2 source is CTED1 0010 = Edge 2 source is CTED2 0001 = Edge 2 source is OC1 0000 = Edge 2 source is Timer1 bit 1-0 Unimplemented: Read as ‘0’ Note 1: Edge sources, CTED3, CTED7, CTED10 and CTED11, are available in 100-pin devices only. DS30009996G-page 328  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 27-3: CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 . . . 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG<1:0> 111111 = Minimum negative change from nominal current . . . 100010 100001 = Maximum negative change from nominal current bit 9-8 IRNG<1:0>: Current Source Range Select bits 11 = 100 × Base Current 10 = 10 × Base Current 01 = Base current level (0.55 A nominal) 00 = 1000 × Base Current bit 7-0 Unimplemented: Read as ‘0’  2010-2014 Microchip Technology Inc. DS30009996G-page 329

PIC24FJ128GA310 FAMILY NOTES: DS30009996G-page 330  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 28.0 HIGH/LOW-VOLTAGE DETECT The High/Low-Voltage Detect (HLVD) module is a (HLVD) programmable circuit that allows the user to specify both the device voltage trip point and the direction of Note: This data sheet summarizes the features change. of this group of PIC24F devices. It is not An interrupt flag is set if the device experiences an intended to be a comprehensive excursion past the trip point in the direction of change. reference source. For more information If the interrupt is enabled, the program execution will on the High/Low-Voltage Detect, refer branch to the interrupt vector address and the software to “High-Level Integration with can then respond to the interrupt. Programmable High/Low-Voltage The HLVD Control register (see Register28-1) Detect (HLVD)” (DS39725) in the completely controls the operation of the HLVD module. “dsPIC33/PIC24 Family Reference This allows the circuitry to be “turned off” by the user Manual”. The information in this data sheet under software control, which minimizes the current supersedes the information in the FRM. consumption for the device. FIGURE 28-1: HIGH/LOW-VOLTAGE DETECT (HLVD) MODULE BLOCK DIAGRAM Externally Generated Trip Point VDD VDD HLVDIN HLVDL<3:0> HLVDEN VDIR X U Set M HLVDIF 1 o- 6-t 1 Band Gap 1.2V Typical HLVDEN  2010-2014 Microchip Technology Inc. DS30009996G-page 331

PIC24FJ128GA310 FAMILY REGISTER 28-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 HLVDEN — HLSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 VDIR BGVST IRVST — HLVDL3 HLVDL2 HLVDL1 HLVDL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD is enabled 0 = HLVD is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 HLSIDL: HLVD Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-8 Unimplemented: Read as ‘0’ bit 7 VDIR: Voltage Change Direction Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>) 0 = Event occurs when voltage equals or falls below trip point (HLVDL<3:0>) bit 6 BGVST: Band Gap Voltage Stable Flag bit 1 = Indicates that the band gap voltage is stable 0 = Indicates that the band gap voltage is unstable bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Internal reference voltage is stable; the High-Voltage Detect logic generates the interrupt flag at the specified voltage range 0 = Internal reference voltage is unstable; the High-Voltage Detect logic will not generate the interrupt flag at the specified voltage range and the HLVD interrupt should not be enabled bit 4 Unimplemented: Read as ‘0’ bit 3-0 HLVDL<3:0>: High/Low-Voltage Detection Limit bits 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = Trip Point 1(1) 1101 = Trip Point 2(1) 1100 = Trip Point 3(1) . . . 0100 = Trip Point 11(1) 00xx = Unused Note 1: For the actual trip point, see Section32.0 “Electrical Characteristics”. DS30009996G-page 332  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 29.0 SPECIAL FEATURES 29.1.1 CONSIDERATIONS FOR CONFIGURING PIC24FJ128GA310 Note: This data sheet summarizes the features of FAMILY DEVICES this group of PIC24F devices. It is not In PIC24FJ128GA310 family devices, the Configura- intended to be a comprehensive reference tion bytes are implemented as volatile memory. This source. For more information, refer to the means that configuration data must be programmed following sections of the “dsPIC33/PIC24 each time the device is powered up. Configuration data Family Reference Manual”. The informa- is stored in the three words at the top of the on-chip pro- tion in this data sheet supersedes the gram memory space, known as the Flash Configuration information in the FRMs. Words. Their specific locations are shown in • “Watchdog Timer (WDT)” Table29-1. These are packed representations of the (DS39697) actual device Configuration bits, whose actual • “High-Level Device Integration” locations are distributed among several locations in (DS39719) configuration space. The configuration data is automat- • “Programming and Diagnostics” ically loaded from the Flash Configuration Words to the (DS39716) proper Configuration registers during device Resets. PIC24FJ128GA310 family devices include several Note: Configuration data is reloaded on all types features intended to maximize application flexibility and of device Resets. reliability, and minimize cost through elimination of When creating applications for these devices, users external components. These are: should always specifically allocate the location of the • Flexible Configuration Flash Configuration Word for configuration data. This is • Watchdog Timer (WDT) to make certain that program code is not stored in this • Code Protection address when the code is compiled. • JTAG Boundary Scan Interface The upper byte of all Flash Configuration Words in • In-Circuit Serial Programming™ program memory should always be ‘0000 0000’. This • In-Circuit Emulation makes them appear to be NOP instructions in the remote event that their locations are ever executed by 29.1 Configuration Bits accident. Since Configuration bits are not implemented in the corresponding locations, writing ‘0’s to these The Configuration bits can be programmed (read as ‘0’), locations has no effect on device operation. or left unprogrammed (read as ‘1’), to select various Note: Performing a page erase operation on the device configurations. These bits are mapped starting at last page of program memory clears the program memory location, F80000h. A detailed explana- Flash Configuration Words, enabling code tion of the various bit functions is provided in protection as a result. Therefore, users Register29-1 through Register29-6. should avoid performing page erase Note that address, F80000h, is beyond the user program operations on the last page of program memory space. In fact, it belongs to the configuration memory. memory space (800000h-FFFFFFh) which can only be accessed using Table Reads and Table Writes. TABLE 29-1: FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJ128GA310 FAMILY DEVICES Configuration Word Addresses Device 1 2 3 4 PIC24FJ64GA3XX ABFEh ABFCh ABFAh ABF8h PIC24FJ128GA3XX 157FEh 157FCh 157FAh 157F8h  2010-2014 Microchip Technology Inc. DS30009996G-page 333

PIC24FJ128GA310 FAMILY REGISTER 29-1: CW1: FLASH CONFIGURATION WORD 1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 23 bit 16 r-x R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 r JTAGEN GCP GWRP DEBUG LPCFG ICS1 ICS0 bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 WINDIS FWDTEN1 FWDTEN0 FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: r = Reserved bit PO = Program once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘1’ bit 15 Reserved: The value is unknown; program as ‘0’ bit 14 JTAGEN: JTAG Port Enable bit 1 = JTAG port is enabled 0 = JTAG port is disabled bit 13 GCP: General Segment Program Memory Code Protection bit 1 = Code protection is disabled 0 = Code protection is enabled for the entire program memory space bit 12 GWRP: General Segment Code Flash Write Protection bit 1 = Writes to program memory are allowed 0 = Writes to program memory are not allowed bit 11 DEBUG: Background Debugger Enable bit 1 = Device resets into Operational mode 0 = Device resets into Debug mode bit 10 LPCFG: Low-Voltage/Retention Regulator Configuration bit 1 = Low-voltage/retention regulator is always disabled 0 = Low-power, low-voltage/retention regulator is enabled and controlled in firmware by the RETEN bit bit 9-8 ICS<1:0>: Emulator Pin Placement Select bits 11 = Emulator functions are shared with PGEC1/PGED1 10 = Emulator functions are shared with PGEC2/PGED2 01 = Emulator functions are shared with PGEC3/PGED3 00 = Reserved; do not use bit 7 WINDIS: Windowed Watchdog Timer Disable bit 1 = Standard Watchdog Timer is enabled 0 = Windowed Watchdog Timer is enabled; (FWDTEN<1:0> must not be ‘00’) bit 6-5 FWDTEN<1:0>: Watchdog Timer Configuration bits 11 = WDT is always enabled; SWDTEN bit has no effect 10 = WDT is enabled and controlled in firmware by the SWDTEN bit 01 = WDT is enabled only in Run mode and disabled in Sleep modes; SWDTEN bit is disabled 00 = WDT is disabled; SWDTEN bit is disabled DS30009996G-page 334  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 29-1: CW1: FLASH CONFIGURATION WORD 1 (CONTINUED) bit 4 FWPSA: WDT Prescaler Ratio Select bit 1 = Prescaler ratio of 1:128 0 = Prescaler ratio of 1:32 bit 3-0 WDTPS<3:0>: Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1  2010-2014 Microchip Technology Inc. DS30009996G-page 335

PIC24FJ128GA310 FAMILY REGISTER 29-2: CW2: FLASH CONFIGURATION WORD 2 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 23 bit 16 R/PO-1 r-1 r-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 IESO r r ALTVRF1 ALTVRF0 FNOSC2 FNOSC1 FNOSC0 bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-1 R/PO-1 R/PO-1 FCKSM1 FCKSM0 OSCIOFCN IOL1WAY BOREN1 r POSCMD1 POSCMD0 bit 7 bit 0 Legend: r = Reserved bit PO = Program once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘1’ bit 15 IESO: Internal External Switchover bit 1 = IESO mode (Two-Speed Start-up) is enabled 0 = IESO mode (Two-Speed Start-up) is disabled bit 14-13 Reserved: Always maintain as ‘1’ bit 12-11 ALTVRF<1:0>: Alternate VREF/CVREF Pins Selection bits 00 = Comparator Voltage reference input VREF+ is RB0, VREF- is RB1, ADC VREF+ is RB0 and ADCVREF- is RB1 01 = Comparator Voltage reference input VREF+ is RB0, VREF- is RB1, ADC VREF+ is RA10 and ADCVREF- is RA9 10 = Comparator Voltage reference input VREF+ is RA10, VREF- is RA9, ADC VREF+ is RB0 and ADCVREF- is RB1 11 = Comparator Voltage reference input VREF+ is RA10, VREF- is RA9, ADC VREF+ is RA10 and ADCVREF- is RA9 bit 10-8 FNOSC<2:0>: Initial Oscillator Select bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) bit 7-6 FCKSM<1:0>: Clock Switching and Fail-Safe Clock Monitor Configuration bits 1x = Clock switching and Fail-Safe Clock Monitor are disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled bit 5 OSCIOFCN: OSCO Pin Configuration bit If POSCMD<1:0> = 11 or 00: 1 = OSCO/CLKO/RC15 functions as CLKO (FOSC/2) 0 = OSCO/CLKO/RC15 functions as port I/O (RC15) If POSCMD<1:0> = 10 or 01: OSCIOFCN has no effect on OSCO/CLKO/RC15. DS30009996G-page 336  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 29-2: CW2: FLASH CONFIGURATION WORD 2 (CONTINUED) bit 4 IOL1WAY: IOLOCK One-Way Set Enable bit 1 = The IOLOCK bit (OSCCON<6>) can be set once, provided the unlock sequence has been completed. Once set, the Peripheral Pin Select registers cannot be written to a second time. 0 = The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been completed bit 3 BOREN1: BOR Override bit This bit should be set/cleared based on the BOREN (CW3<12>) setting. 1 = BOR is enabled (CW3<12>, BOREN = 1) 0 = BOR is disabled (CW3<12>, BOREN = 0) Allowed Combinations are Shown Below: BOREN (CW3<12>), BOREN1 (CW2<3>): 11 = BOR is enabled 10 = Reserved 01 = Reserved 00 = BOR is disabled bit 2 Reserved: Always maintain as ‘1’ bit 1-0 POSCMD<1:0>: Primary Oscillator Configuration bits 11 = Primary Oscillator mode is disabled 10 = HS Oscillator mode is selected 01 = XT Oscillator mode is selected 00 = EC Oscillator mode is selected  2010-2014 Microchip Technology Inc. DS30009996G-page 337

PIC24FJ128GA310 FAMILY REGISTER 29-3: CW3: FLASH CONFIGURATION WORD 3 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 23 bit 16 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-1 R/PO-1 WPEND WPCFG WPDIS BOREN WDTWIN1 WDTWIN0 r SOSCSEL bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 VBTBOR WPFP6(3) WPFP5 WPFP4 WPFP3 WPFP2 WPFP1 WPFP0 bit 7 bit 0 Legend: r = Reserved bit PO = Program once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘1’ bit 15 WPEND: Segment Write Protection End Page Select bit 1 = Protected code segment upper boundary is at the last page of program memory; the lower boundary is the code page specified by WPFP<6:0> 0 = Protected code segment lower boundary is at the bottom of the program memory (000000h); upper boundary is the code page specified by WPFP<6:0> bit 14 WPCFG: Configuration Word Code Page Write Protection Select bit 1 = Last page (at the top of program memory) and Flash Configuration Words are not write-protected(1) 0 = Last page and Flash Configuration Words are write-protected provided WPDIS = 0 bit 13 WPDIS: Segment Write Protection Disable bit 1 = Segmented code protection is disabled 0 = Segmented code protection is enabled; protected segment is defined by the WPEND, WPCFG and WPFPx Configuration bits bit 12 BOREN: Brown-out Reset Enable bit (also see CW2<3> BOREN1) 1 = BOR is enabled (all modes except Deep Sleep) (BOREN1 = 1) 0 = BOR is disabled Allowed Combinations are Shown Below: BOREN (CW3<12>), BOREN1 (CW2<3>): 11 = BOR is enabled 10 = Reserved 01 = Reserved 00 = BOR is disabled (BOREN1 = 0) bit 11-10 WDTWIN<1:0>: Watchdog Timer Window Width Select bits 11 = 25% 10 = 37.5% 01 = 50% 00 = 75% bit 9 Reserved: Always maintain as ‘1’ Note 1: Regardless of WPCFG status, if WPEND = 1 or if WPFPx corresponds to the Configuration Word page, the Configuration Word page is protected. 2: Ensure that the SCLKI pin is made a digital input while using this configuration (see Table11-1). 3: For the 62K devices: PIC24FJ64GA310, PIC24FJ64GA308 and PIC24FJ64GA306, bit 6 should be maintained as ‘0’. DS30009996G-page 338  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 29-3: CW3: FLASH CONFIGURATION WORD 3 (CONTINUED) bit 8 SOSCSEL: SOSC Selection bit 1 = SOSC circuit is selected 0 = Digital (SCLKI) mode(2) bit 7 VBTBOR: VBAT BOR Enable bit 1 = VBAT BOR is enabled 0 = VBAT BOR is disabled bit 6-0 WPFP<6:0>: Write-Protected Code Segment Boundary Page bits(3) Designates the 256 instruction words page boundary of the protected code segment. If WPEND = 1: Specifies the lower page boundary of the code-protected segment; the last page being the last implemented page in the device. If WPEND = 0: Specifies the upper page boundary of the code-protected segment; Page 0 being the lower boundary. Note 1: Regardless of WPCFG status, if WPEND = 1 or if WPFPx corresponds to the Configuration Word page, the Configuration Word page is protected. 2: Ensure that the SCLKI pin is made a digital input while using this configuration (see Table11-1). 3: For the 62K devices: PIC24FJ64GA310, PIC24FJ64GA308 and PIC24FJ64GA306, bit 6 should be maintained as ‘0’.  2010-2014 Microchip Technology Inc. DS30009996G-page 339

PIC24FJ128GA310 FAMILY REGISTER 29-4: CW4: FLASH CONFIGURATION WORD 4 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 23 bit 16 r-1 r-1 r-1 r-1 r-1 r-1 r-1 R/PO-1 r r r r r r r DSSWEN bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 DSWDTEN DSBOREN DSWDTOSC DSWDPS4 DSWDPS3 DSWDPS2 DSWDPS1 DSWDPS0 bit 7 bit 0 Legend: r = Reserved bit PO = Program once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘1’ bit 15-9 Reserved: Read as ‘1’ bit 8 DSSWEN: Deep Sleep Software Control Select bit 1 = Deep Sleep operation is enabled and controlled by the DSEN bit 0 = Deep Sleep operation is disabled bit 7 DSWDTEN: Deep Sleep Watchdog Timer Enable bit 1 = Deep Sleep WDT is enabled 0 = Deep Sleep WDT is disabled bit 6 DSBOREN: Deep Sleep Brown-out Reset Enable bit 1 = BOR is enabled in Deep Sleep mode 0 = BOR is disabled in Deep Sleep mode (remains active in other Sleep modes) bit 5 DSWDTOSC: Deep Sleep Watchdog Timer Clock Select bit 1 = Clock source is LPRC 0 = Clock source is SOSC DS30009996G-page 340  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY REGISTER 29-4: CW4: FLASH CONFIGURATION WORD 4 (CONTINUED) bit 4-0 DSWDPS<4:0>: Deep Sleep Watchdog Timer Postscaler Select bits 11111 = 1:68,719,476,736 (25.7 days) 11110 = 1:34,359,738,368(12.8 days) 11101 = 1:17,179,869,184 (6.4 days) 11100 = 1:8,589,934592 (77.0 hours) 11011 = 1:4,294,967,296 (38.5 hours) 11010 = 1:2,147,483,648 (19.2 hours) 11001 = 1:1,073,741,824 (9.6 hours) 11000 = 1:536,870,912 (4.8 hours) 10111 = 1:268,435,456 (2.4 hours) 10110 = 1:134,217,728 (72.2 minutes) 10101 = 1:67,108,864 (36.1 minutes) 10100 = 1:33,554,432 (18.0 minutes) 10011 = 1:16,777,216 (9.0 minutes) 10010 = 1:8,388,608 (4.5 minutes) 10001 = 1:4,194,304 (135.3 s) 10000 = 1:2,097,152 (67.7 s) 01111 = 1:1,048,576 (33.825 s) 01110 = 1:524,288 (16.912 s) 01101 = 1:262,114 (8.456 s) 01100 = 1:131,072 (4.228 s) 01011 = 1:65,536 (2.114 s) 01010 = 1:32,768 (1.057 s) 01001 = 1:16,384 (528.5 ms) 01000 = 1:8,192 (264.3 ms) 00111 = 1:4,096 (132.1 ms) 00110 = 1:2,048 (66.1 ms) 00101 = 1:1,024 (33 ms) 00100 = 1:512 (16.5 ms) 00011 = 1:256 (8.3 ms) 00010 = 1:128 (4.1 ms) 00001 = 1:64 (2.1 ms) 00000 = 1:32 (1 ms)  2010-2014 Microchip Technology Inc. DS30009996G-page 341

PIC24FJ128GA310 FAMILY REGISTER 29-5: DEVID: DEVICE ID REGISTER U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 23 bit 16 R R R R R R R R FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2 FAMID1 FAMID0 bit 15 bit 8 R R R R R R R R DEV7 DEV6 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit bit 23-16 Unimplemented: Read as ‘1’ bit 15-8 FAMID<7:0>: Device Family Identifier bits 0100 0110 = PIC24FJ128GA310 family bit 7-0 DEV<7:0>: Individual Device Identifier bits 1100 0000 = PIC24FJ64GA306 1100 0010 = PIC24FJ128GA306 1100 0100 = PIC24FJ64GA308 1100 0110 = PIC24FJ128GA308 1100 1000 = PIC24FJ64GA310 1100 1010 = PIC24FJ128GA310 REGISTER 29-6: DEVREV: DEVICE REVISION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R R R R — — — — REV<3:0> bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit bit 23-4 Unimplemented: Read as ‘0’ bit 3-0 REV<3:0>: Device revision identifier bits DS30009996G-page 342  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 29.2 On-Chip Voltage Regulator 29.2.1 ON-CHIP REGULATOR AND POR All PIC24FJ128GA310 family devices power their core The voltage regulator takes approximately 10s for it digital logic at a nominal 1.8V. This may create an issue to generate output. During this time, designated as for designs that are required to operate at a higher TVREG, code execution is disabled. TVREG is applied typical voltage, such as 3.3V. To simplify system every time the device resumes operation after any design, all devices in the PIC24FJ128GA310 family power-down, including Sleep mode. TVREG is deter- mined by the status of the VREGS bit (RCON<8>) and incorporate an on-chip regulator that allows the device to run its core logic from VDD. the WDTWINx Configuration bits (CW3<11:10>). Refer to Section32.0 “Electrical Characteristics” for more This regulator is always enabled. It provides a constant information on TVREG. voltage (1.8V nominal) to the digital core logic, from a VDD of about 2.1V all the way up to the device’s Note: For more information, see Section32.0 VDDMAX. It does not have the capability to boost VDD “Electrical Characteristics”. The infor- levels. In order to prevent “brown-out” conditions when mation in this data sheet supersedes the the voltage drops too low for the regulator, the information in the FRM. Brown-out Reset occurs. Then the regulator output follows VDD with a typical voltage drop of 300mV. 29.2.2 VOLTAGE REGULATOR STANDBY MODE A low-ESR capacitor (such as ceramic) must be connected to the VCAP pin (Figure29-1). This helps to The on-chip regulator always consumes a small incre- maintain the stability of the regulator. The recommended mental amount of current over IDD/IPD, including when value for the filter capacitor (CEFC) is provided in the device is in Sleep mode, even though the core Section32.1 “DC Characteristics”. digital logic does not require power. To provide addi- tional savings in applications where power resources FIGURE 29-1: CONNECTIONS FOR THE are critical, the regulator can be made to enter Standby ON-CHIP REGULATOR mode on its own whenever the device goes into Sleep mode. This feature is controlled by the VREGS bit (RCON<8>). Clearing the VREGS bit enables the 3.3V(1) Standby mode. When waking up from Standby mode, PIC24FJXXXGA3XX the regulator needs to wait for TVREG to expire before wake-up. VDD 29.2.3 LOW-VOLTAGE/RETENTION VCAP REGULATOR CEFC (10F typ) VSS When power-saving modes, such as Sleep and Deep Sleep are used, PIC24FJ128GA310 family devices may use a separate low-power, low-voltage/retention regulator to power critical circuits. This regulator, which Note 1: This is a typical operating voltage. Refer to Section32.0 “Electrical Characteristics” operates at 1.2V nominal, maintains power to data for the full operating ranges of VDD. RAM and the RTCC while all other core digital logic is powered down. It operates only in Sleep, Deep Sleep and VBAT modes. The low-voltage/retention regulator is described in more detail in Section10.1.3 “Low-Voltage/Retention Regulator”.  2010-2014 Microchip Technology Inc. DS30009996G-page 343

PIC24FJ128GA310 FAMILY 29.3 Watchdog Timer (WDT) The WDT Flag bit, WDTO (RCON<4>), is not auto- matically cleared following a WDT time-out. To detect For PIC24FJ128GA310 family devices, the WDT is subsequent WDT events, the flag must be cleared in driven by the LPRC oscillator. When the WDT is software. enabled, the clock source is also enabled. Note: The CLRWDT and PWRSAV instructions The nominal WDT clock source from LPRC is 31kHz. clear the prescaler and postscaler counts This feeds a prescaler that can be configured for either when executed. 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit. 29.3.1 WINDOWED OPERATION With a 31kHz input, the prescaler yields a nominal WDT Time-out period (TWDT) of 1ms in 5-bit mode or The Watchdog Timer has an optional Fixed Window 4ms in 7-bit mode. mode of operation. In this Windowed mode, CLRWDT instructions can only reset the WDT during the last 1/4 A variable postscaler divides down the WDT prescaler of the programmed WDT period. A CLRWDT instruction output and allows for a wide range of time-out periods. executed before that window causes a WDT Reset, The postscaler is controlled by the WDTPS<3:0> Con- similar to a WDT time-out. figuration bits (CW1<3:0>), which allows the selection of a total of 16 settings, from 1:1 to 1:32,768. Using the Windowed WDT mode is enabled by programming the prescaler and postscaler time-out periods, ranging WINDIS Configuration bit (CW1<7>) to ‘0’. from 1ms to 131 seconds, can be achieved. 29.3.2 CONTROL REGISTER The WDT, prescaler and postscaler are reset: • On any device Reset The WDT is enabled or disabled by the FWDTEN<1:0> • On the completion of a clock switch, whether Configuration bits. When the Configuration bits, invoked by software (i.e., setting the OSWEN bit FWDTEN<1:0> = 11, the WDT is always enabled. after changing the NOSC bits) or by hardware The WDT can be optionally controlled in software when (i.e., Fail-Safe Clock Monitor) the Configuration bits, FWDTEN<1:0> = 10. When • When a PWRSAV instruction is executed FWDTEN<1:0> = 00, the Watchdog Timer is always (i.e., Sleep or Idle mode is entered) disabled. The WDT is enabled in software by setting • When the device exits Sleep or Idle mode to the SWDTEN control bit (RCON<5>). The SWDTEN resume normal operation control bit is cleared on any device Reset. The software WDT option allows the user to enable the WDT for • By a CLRWDT instruction during normal execution critical code segments and disable the WDT during If the WDT is enabled, it will continue to run during non-critical segments for maximum power savings. Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE (RCON<3:2>) bits will need to be cleared in software after the device wakes up. FIGURE 29-2: WDT BLOCK DIAGRAM SWDTEN LPRC Control FWDTEN<1:0> Wake from Sleep FWPSA WDTPS<3:0> Prescaler WDT Postscaler WDT Overflow LPRC Input (5-bit/7-bit) Counter 1:1 to 1:32.768 Reset 31 kHz 1 ms/4 ms All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode CLRWDT Instr. PWRSAV Instr. Sleep or Idle Mode DS30009996G-page 344  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 29.4 Program Verification and Code segment protection provides an added level of Code Protection protection to a designated area of program memory by disabling the NVM safety interlock whenever a write or PIC24FJ128GA310 family devices provide two compli- erase address falls within a specified range. It does not mentary methods to protect application code from override General Segment protection controlled by the overwrites and erasures. These also help to protect the GCP or GWRP bits. For example, if GCP and GWRP device from inadvertent configuration changes during are enabled, enabling segmented code protection for run time. the bottom half of program memory does not undo General Segment protection for the top half. 29.4.1 GENERAL SEGMENT PROTECTION The size and type of protection for the segmented code For all devices in the PIC24FJ128GA310 family, the range are configured by the WPFPx, WPEND, WPCFG on-chip program memory space is treated as a single and WPDIS bits in Configuration Word 3. Code seg- block, known as the General Segment (GS). Code pro- ment protection is enabled by programming the WPDIS tection for this block is controlled by one Configuration bit (= 0). The WPFPx bits specify the size of the bit, GCP. This bit inhibits external reads and writes to segment to be protected by specifying the 512-word the program memory space. It has no direct effect in code page that is the start or end of the protected normal execution mode. segment. The specified region is inclusive, therefore, Write protection is controlled by the GWRP bit in the this page will also be protected. Configuration Word. When GWRP is programmed to The WPEND bit determines if the protected segment ‘0’, internal write and erase operations to program uses the top or bottom of the program space as a memory are blocked. boundary. Programming WPEND (= 0) sets the bottom of program memory (000000h) as the lower boundary 29.4.2 CODE SEGMENT PROTECTION of the protected segment. Leaving WPEND unpro- In addition to global General Segment protection, a grammed (= 1) protects the specified page through the separate subrange of the program memory space can last page of implemented program memory, including be individually protected against writes and erases. the Configuration Word locations. This area can be used for many purposes where a sep- A separate bit, WPCFG, is used to protect the last page arate block of write and erase-protected code is of program space, including the Flash Configuration needed, such as bootloader applications. Unlike Words. Programming WPCFG (=0) protects the last common boot block implementations, the specially page in addition to the pages selected by the WPEND protected segment in the PIC24FJ128GA310 family and WPFP<6:0> bits setting. This is useful in circum- devices can be located by the user anywhere in the stances where write protection is needed for both the program space and configured in a wide range of sizes. code segment in the bottom of the memory and the Flash Configuration Words. The various options for segment code protection are shown in Table29-2. TABLE 29-2: CODE SEGMENT PROTECTION CONFIGURATION OPTIONS Segment Configuration Bits Write/Erase Protection of Code Segment WPDIS WPEND WPCFG 1 x x No additional protection is enabled; all program memory protection is configured by GCP and GWRP. 0 1 x Addresses from the first address of the code page are defined by WPFP<6:0> through the end of implemented program memory (inclusive); erase/write-protected, including Flash Configuration Words. 0 0 1 Address, 000000h through the last address of the code page, is defined by WPFP<6:0> (inclusive); erase/write-protected. 0 0 0 Address, 000000h through the last address of the code page, is defined by WPFP<6:0> (inclusive); erase/write-protected and the last page, including Flash Configuration Words, are erase/write-protected.  2010-2014 Microchip Technology Inc. DS30009996G-page 345

PIC24FJ128GA310 FAMILY 29.4.3 CONFIGURATION REGISTER 29.6 In-Circuit Serial Programming PROTECTION PIC24FJ128GA310 family microcontrollers can be The Configuration registers are protected against serially programmed while in the end application circuit. inadvertent or unwanted changes or reads in two ways. This is simply done with two lines for clock (PGECx) The primary protection method is the same as that of and data (PGEDx), and three other lines for power the RP registers – shadow registers contain a compli- (VDD), ground (VSS) and MCLR. This allows customers mentary value which is constantly compared with the to manufacture boards with unprogrammed devices actual value. and then program the microcontroller just before To safeguard against unpredictable events, Configura- shipping the product. This also allows the most recent tion bit changes resulting from individual cell level firmware or a custom firmware to be programmed. disruptions (such as ESD events) will cause a parity error and trigger a device Reset. 29.7 In-Circuit Debugger The data for the Configuration registers is derived from When MPLAB® ICD 3 is selected as a debugger, the the Flash Configuration Words in program memory. in-circuit debugging functionality is enabled. This func- When the GCP bit is set, the source data for device tion allows simple debugging functions when used with configuration is also protected as a consequence. Even MPLAB IDE. Debugging functionality is controlled if General Segment protection is not enabled, the through the PGECx (Emulation/Debug Clock) and device configuration can be protected by using the PGEDx (Emulation/Debug Data) pins. appropriate code segment protection setting. To use the in-circuit debugger function of the device, the design must implement ICSP connections to 29.5 JTAG Interface MCLR, VDD, VSS and the PGECx/PGEDx pin pair des- PIC24FJ128GA310 family devices implement a JTAG ignated by the ICSx Configuration bits. In addition, interface, which supports boundary scan device when the feature is enabled, some of the resources are testing. not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins. DS30009996G-page 346  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 30.0 DEVELOPMENT SUPPORT 30.1 MPLAB X Integrated Development Environment Software The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user of software and hardware development tools: interface for Microchip and third-party software, and • Integrated Development Environment hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, - MPLAB® X IDE Software MPLAB X IDE is an entirely new IDE with a host of free • Compilers/Assemblers/Linkers software components and plug-ins for high- - MPLAB XC Compiler performance application development and debugging. - MPASMTM Assembler Moving between tools and upgrading from software - MPLINKTM Object Linker/ simulators to hardware debugging and programming MPLIBTM Object Librarian tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs, Various Device Families a configurable watch window and a feature-rich editor • Simulators that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new - MPLAB X SIM Software Simulator users. With the ability to support multiple tools on • Emulators multiple projects with simultaneous debugging, MPLAB - MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced • In-Circuit Debuggers/Programmers users. - MPLAB ICD 3 Feature-Rich Editor: - PICkit™ 3 • Color syntax highlighting • Device Programmers • Smart code completion makes suggestions and - MPLAB PM3 Device Programmer provides hints as you type • Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined Evaluation Kits and Starter Kits rules • Third-party development tools • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker  2010-2014 Microchip Technology Inc. DS30009996G-page 347

PIC24FJ128GA310 FAMILY 30.2 MPLAB XC Compilers 30.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other relo- related modules together catable object files and archives to create an execut- • Flexible creation of libraries with easy module able file. MPLAB XC Compiler uses the assembler to listing, replacement, deletion and extraction produce its object file. Notable features of the assem- bler include: 30.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, • Flexible macro language PIC32 and dsPIC DSC devices. MPLAB XC Compiler • MPLAB X IDE compatibility uses the assembler to produce its object file. The assembler generates relocatable object files that can 30.3 MPASM Assembler then be archived or linked with other relocatable object files and archives to create an executable file. Notable The MPASM Assembler is a full-featured, universal features of the assembler include: macro assembler for PIC10/12/16/18 MCUs. • Support for the entire device instruction set The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process DS30009996G-page 348  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 30.6 MPLAB X SIM Software Simulator 30.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful, logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB buffer and logic analyzer display extend the power of IDE. the simulator to record and track program execution, The MPLAB ICD 3 In-Circuit Debugger probe is actions on I/O, most peripherals and internal registers. connected to the design engineer’s PC using a high- The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target symbolic debugging using the MPLAB XCCompilers, with a connector compatible with the MPLAB ICD 2 or and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers. debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software 30.9 PICkit 3 In-Circuit Debugger/ development tool. Programmer 30.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program- Emulator System ming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full- Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar- programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati- with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The the MPLAB X IDE. connector uses two device I/O pins and the Reset line The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™). connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) 30.10 MPLAB PM3 Device Programmer or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal, Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable (CAT5). voltage verification at VDDMIN and VDDMAX for The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod- significant advantages over competitive emulators ular, detachable socket assembly to support various including full-speed emulation, run-time variable package types. The ICSP cable assembly is included watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program three meters) interconnection cables. PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications.  2010-2014 Microchip Technology Inc. DS30009996G-page 349

PIC24FJ128GA310 FAMILY 30.11 Demonstration/Development 30.12 Third-Party Development Tools Boards, Evaluation Kits, and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide applica- and Trace Systems tion firmware and source code for examination and • Protocol Analyzers from companies, such as modification. Saleae and Total Phase The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies, EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstra- tion software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS30009996G-page 350  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 31.0 INSTRUCTION SET SUMMARY The literal instructions that involve data movement may use some of the following operands: Note: This chapter is a brief summary of the • A literal value to be loaded into a W register or file PIC24F Instruction Set Architecture (ISA) register (specified by the value of ‘k’) and is not intended to be a comprehensive • The W register or file register where the literal reference source. value is to be loaded (specified by ‘Wb’ or ‘f’) The PIC24F instruction set adds many enhancements However, literal instructions that involve arithmetic or to the previous PIC® MCU instruction sets, while main- logical operations use some of the following operands: taining an easy migration from previous PIC MCU • The first source operand, which is a register, ‘Wb’, instruction sets. Most instructions are a single program without any address modifier memory word. Only three instructions require two program memory locations. • The second source operand, which is a literal value Each single-word instruction is a 24-bit word divided • The destination of the result (only if not the same into an 8-bit opcode, which specifies the instruction as the first source operand), which is typically a type and one or more operands, which further specify register, ‘Wd’, with or without an address modifier the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic The control instructions may use some of the following categories: operands: • Word or byte-oriented operations • A program memory address • Bit-oriented operations • The mode of the Table Read and Table Write • Literal operations instructions • Control operations All instructions are a single word, except for certain double-word instructions, which were made Table31-1 shows the general symbols used in double-word instructions so that all the required infor- describing the instructions. The PIC24F instruction set mation is available in these 48 bits. In the second word, summary in Table31-2 lists all the instructions, along the 8MSbs are ‘0’s. If this second word is executed as with the status flags affected by each instruction. an instruction (by itself), it will execute as a NOP. Most word or byte-oriented W register instructions Most single-word instructions are executed in a single (including barrel shift instructions) have three instruction cycle, unless a conditional test is true or the operands: Program Counter (PC) is changed as a result of the • The first source operand, which is typically a instruction. In these cases, the execution takes two register, ‘Wb’, without any address modifier instruction cycles, with the additional instruction cycle(s) • The second source operand, which is typically a executed as a NOP. Notable exceptions are the BRA register, ‘Ws’, with or without an address modifier (unconditional/computed branch), indirect CALL/GOTO, • The destination of the result, which is typically a all Table Reads and Table Writes, and RETURN/RETFIE register, ‘Wd’, with or without an address modifier instructions, which are single-word instructions but take two or three cycles. However, word or byte-oriented file register instructions have two operands: Certain instructions that involve skipping over the sub- sequent instruction require either two or three cycles if • The file register specified by the value, ‘f’ the skip is performed, depending on whether the • The destination, which could either be the file instruction being skipped is a single-word or two-word register, ‘f’, or the W0 register, which is denoted instruction. Moreover, double-word moves require two as ‘WREG’ cycles. The double-word instructions execute in two Most bit-oriented instructions (including simple instruction cycles. rotate/shift instructions) have two operands: • The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’) • The bit in the W register or file register (specified by a literal value or indirectly by the contents of register, ‘Wb’)  2010-2014 Microchip Technology Inc. DS30009996G-page 351

PIC24FJ128GA310 FAMILY TABLE 31-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation <n:m> Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) bit4 4-bit Bit Selection field (used in word addressed instructions) {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address {0000h...1FFFh} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal {0...16383} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388607}; LSB must be ‘0’ None Field does not require an entry, may be blank PC Program Counter Slit10 10-bit signed literal {-512...511} Slit16 16-bit signed literal {-32768...32767} Slit6 6-bit signed literal {-16...16} Wb Base W register {W0..W15} Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Wdo Destination W register  { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor Working register pair (direct addressing) Wn One of 16 Working registers {W0..W15} Wnd One of 16 Destination Working registers {W0..W15} Wns One of 16 Source Working registers {W0..W15} WREG W0 (Working register used in file register instructions) Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Wso Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } DS30009996G-page 352  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 31-2: INSTRUCTION SET OVERVIEW Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected ADD ADD f f = f + WREG 1 1 C, DC, N, OV, Z ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z ADDC ADDC f f = f + WREG + (C) 1 1 C, DC, N, OV, Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C, DC, N, OV, Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C, DC, N, OV, Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C, DC, N, OV, Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C, DC, N, OV, Z AND AND f f = f .AND. WREG 1 1 N, Z AND f,WREG WREG = f .AND. WREG 1 1 N, Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N, Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N, Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N, Z ASR ASR f f = Arithmetic Right Shift f 1 1 C, N, OV, Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C, N, OV, Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C, N, OV, Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N, Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N, Z BCLR BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None BRA BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if Greater than or Equal 1 1 (2) None BRA GEU,Expr Branch if Unsigned Greater than or Equal 1 1 (2) None BRA GT,Expr Branch if Greater than 1 1 (2) None BRA GTU,Expr Branch if Unsigned Greater than 1 1 (2) None BRA LE,Expr Branch if Less than or Equal 1 1 (2) None BRA LEU,Expr Branch if Unsigned Less than or Equal 1 1 (2) None BRA LT,Expr Branch if Less than 1 1 (2) None BRA LTU,Expr Branch if Unsigned Less than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None BSET BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None BTG BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None (2 or 3) BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None (2 or 3)  2010-2014 Microchip Technology Inc. DS30009996G-page 353

PIC24FJ128GA310 FAMILY TABLE 31-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) BTST BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z CALL CALL lit23 Call Subroutine 2 2 None CALL Wn Call Indirect Subroutine 1 2 None CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO, Sleep COM COM f f = f 1 1 N, Z COM f,WREG WREG = f 1 1 N, Z COM Ws,Wd Wd = Ws 1 1 N, Z CP CP f Compare f with WREG 1 1 C, DC, N, OV, Z CP Wb,#lit5 Compare Wb with lit5 1 1 C, DC, N, OV, Z CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C, DC, N, OV, Z CP0 CP0 f Compare f with 0x0000 1 1 C, DC, N, OV, Z CP0 Ws Compare Ws with 0x0000 1 1 C, DC, N, OV, Z CPB CPB f Compare f with WREG, with Borrow 1 1 C, DC, N, OV, Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C, DC, N, OV, Z CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C, DC, N, OV, Z (Wb – Ws – C) CPSEQ CPSEQ Wb,Wn Compare Wb with Wn, Skip if = 1 1 None (2 or 3) CPSGT CPSGT Wb,Wn Compare Wb with Wn, Skip if > 1 1 None (2 or 3) CPSLT CPSLT Wb,Wn Compare Wb with Wn, Skip if < 1 1 None (2 or 3) CPSNE CPSNE Wb,Wn Compare Wb with Wn, Skip if  1 1 None (2 or 3) DAW DAW.B Wn Wn = Decimal Adjust Wn 1 1 C DEC DEC f f = f –1 1 1 C, DC, N, OV, Z DEC f,WREG WREG = f –1 1 1 C, DC, N, OV, Z DEC Ws,Wd Wd = Ws – 1 1 1 C, DC, N, OV, Z DEC2 DEC2 f f = f – 2 1 1 C, DC, N, OV, Z DEC2 f,WREG WREG = f – 2 1 1 C, DC, N, OV, Z DEC2 Ws,Wd Wd = Ws – 2 1 1 C, DC, N, OV, Z DISI DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 None DIV DIV.SW Wm,Wn Signed 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N, Z, C, OV DIV.UW Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N, Z, C, OV EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C DS30009996G-page 354  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 31-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected GOTO GOTO Expr Go to Address 2 2 None GOTO Wn Go to Indirect 1 2 None INC INC f f = f + 1 1 1 C, DC, N, OV, Z INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z INC Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z INC2 INC2 f f = f + 2 1 1 C, DC, N, OV, Z INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z INC2 Ws,Wd Wd = Ws + 2 1 1 C, DC, N, OV, Z IOR IOR f f = f .IOR. WREG 1 1 N, Z IOR f,WREG WREG = f .IOR. WREG 1 1 N, Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N, Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N, Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N, Z LNK LNK #lit14 Link Frame Pointer 1 1 None LSR LSR f f = Logical Right Shift f 1 1 C, N, OV, Z LSR f,WREG WREG = Logical Right Shift f 1 1 C, N, OV, Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C, N, OV, Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N, Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N, Z MOV MOV f,Wn Move f to Wn 1 1 None MOV [Wns+Slit10],Wnd Move [Wns+Slit10] to Wnd 1 1 None MOV f Move f to f 1 1 N, Z MOV f,WREG Move f to WREG 1 1 N, Z MOV #lit16,Wn Move 16-bit Literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit Literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wns,[Wns+Slit10] Move Wns to [Wns+Slit10] 1 1 MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 N, Z MOV.D Wns,Wd Move Double from W(ns):W(ns+1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd+1):W(nd) 1 2 None MUL MUL.SS Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) 1 1 None MUL.SU Wb,#lit5,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) 1 1 None MUL f W3:W2 = f * WREG 1 1 None NEG NEG f f = f + 1 1 1 C, DC, N, OV, Z NEG f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z NEG Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z NOP NOP No Operation 1 1 None NOPR No Operation 1 1 None POP POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) 1 2 None POP.S Pop Shadow Registers 1 1 All PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns+1) to Top-of-Stack (TOS) 1 2 None PUSH.S Push Shadow Registers 1 1 None  2010-2014 Microchip Technology Inc. DS30009996G-page 355

PIC24FJ128GA310 FAMILY TABLE 31-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None RESET RESET Software Device Reset 1 1 None RETFIE RETFIE Return from Interrupt 1 3 (2) None RETLW RETLW #lit10,Wn Return with Literal in Wn 1 3 (2) None RETURN RETURN Return from Subroutine 1 3 (2) None RLC RLC f f = Rotate Left through Carry f 1 1 C, N, Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C, N, Z RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C, N, Z RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N, Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N, Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N, Z RRC RRC f f = Rotate Right through Carry f 1 1 C, N, Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C, N, Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C, N, Z RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N, Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N, Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N, Z SE SE Ws,Wnd Wnd = Sign-Extended Ws 1 1 C, N, Z SETM SETM f f = FFFFh 1 1 None SETM WREG WREG = FFFFh 1 1 None SETM Ws Ws = FFFFh 1 1 None SL SL f f = Left Shift f 1 1 C, N, OV, Z SL f,WREG WREG = Left Shift f 1 1 C, N, OV, Z SL Ws,Wd Wd = Left Shift Ws 1 1 C, N, OV, Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N, Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N, Z SUB SUB f f = f – WREG 1 1 C, DC, N, OV, Z SUB f,WREG WREG = f – WREG 1 1 C, DC, N, OV, Z SUB #lit10,Wn Wn = Wn – lit10 1 1 C, DC, N, OV, Z SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C, DC, N, OV, Z SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C, DC, N, OV, Z SUBB SUBB f f = f – WREG – (C) 1 1 C, DC, N, OV, Z SUBB f,WREG WREG = f – WREG – (C) 1 1 C, DC, N, OV, Z SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C, DC, N, OV, Z SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C, DC, N, OV, Z SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C, DC, N, OV, Z SUBR SUBR f f = WREG – f 1 1 C, DC, N, OV, Z SUBR f,WREG WREG = WREG – f 1 1 C, DC, N, OV, Z SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C, DC, N, OV, Z SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C, DC, N, OV, Z SUBBR SUBBR f f = WREG – f – (C) 1 1 C, DC, N, OV, Z SUBBR f,WREG WREG = WREG – f – (C) 1 1 C, DC, N, OV, Z SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C, DC, N, OV, Z SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C, DC, N, OV, Z SWAP SWAP.b Wn Wn = Nibble Swap Wn 1 1 None SWAP Wn Wn = Byte Swap Wn 1 1 None DS30009996G-page 356  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 31-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None ULNK ULNK Unlink Frame Pointer 1 1 None XOR XOR f f = f .XOR. WREG 1 1 N, Z XOR f,WREG WREG = f .XOR. WREG 1 1 N, Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N, Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N, Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N, Z ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C, Z, N  2010-2014 Microchip Technology Inc. DS30009996G-page 357

PIC24FJ128GA310 FAMILY NOTES: DS30009996G-page 358  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 32.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24FJ128GA310 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FJ128GA310 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +100°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS.......................................................................................................... -0.3V to +4.0V Voltage on any combined analog and digital pin, and MCLR with respect to VSS.........................-0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS when VDD < 3.0V............................................-0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS when VDD > 3.0V..................................................... -0.3V to (+5.5V) Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin (Note 1)................................................................................................................250 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................25 mA Maximum current sunk by all ports.......................................................................................................................200 mA Maximum current sourced by all ports (Note 1)....................................................................................................200 mA Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table32-1). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2010-2014 Microchip Technology Inc. DS30009996G-page 359

PIC24FJ128GA310 FAMILY 32.1 DC Characteristics FIGURE 32-1: PIC24FJ128GA310 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 3.6V 3.6V PIC24FJXXXGA3XX )D D V 2.2V 2.2V ( e 2.0V 2.0V g a t ol V 32 MHz Frequency Note: VCAP (nominal On-Chip Regulator output voltage) = 1.8V. TABLE 32-1: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit PIC24FJ128GA310 Family: Operating Junction Temperature Range TJ -40 — +125 °C Operating Ambient Temperature Range TA -40 — +85 °C Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD –  IOH) PD PINT + PI/O W I/O Pin Power Dissipation: PI/O =  ({VDD – VOH} x IOH) +  (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJMAX – TA)/JA W TABLE 32-2: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ Max Unit Note Package Thermal Resistance, 14x14x1 mm 100-pin TQFP JA 43.0 — °C/W (Note 1) Package Thermal Resistance, 12x12x1 mm 100-pin TQFP JA 45.0 — °C/W (Note 1) Package Thermal Resistance, 12x12x1 mm 80-pin TQFP JA 48.0 — °C/W (Note 1) Package Thermal Resistance, 10x10x1 mm 64-pin TQFP JA 48.3 — °C/W (Note 1) Package Thermal Resistance, 9x9x0.9 mm 64-pin QFN JA 28.0 — °C/W (Note 1) Package Thermal Resistance, 10x10x1.1 mm 121-pin BGA JA 40.2 — °C/W (Note 1) Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. DS30009996G-page 360  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 32-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Param Symbol Characteristic Min Typ Max Units Conditions No. Operating Voltage DC10 VDD Supply Voltage 2 — 3.6 V With BOR disabled DC12 VDR RAM Data Retention 1.9 — — V Voltage(1) DC16 VPOR VDD Start Voltage VSS — — V to Ensure Internal Power-on Reset Signal DC17 SVDD VDD Rise Rate 0.05 — — V/ms 0-3.3V in 66 ms to Ensure Internal 0-2.5V in 50ms Power-on Reset Signal VBOR Brown-out Reset Voltage 2 — 2.2 V on VDD Transition, High-to-Low Note 1: This is the limit to which the RAM data can be retained while the on-chip regulator output voltage starts following the VDD. TABLE 32-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Parameter Operating Typical(1) Max Units VDD Conditions No. Temperature Operating Current (IDD) DC19 0.15 — mA -40°C to +85°C 2.0V 0.5 MIPS, DC20A 0.15 — mA -40°C to +85°C 3.3V FOSC = 1 MHz DC20 0.31 — mA -40°C to +85°C 2.0V 1 MIPS, 0.32 — mA -40°C to +85°C 3.3V FOSC = 2 MHz DC23 1.2 — mA -40°C to +85°C 2.0V 4 MIPS, 1.25 — mA -40°C to +85°C 3.3V FOSC = 8 MHz DC24 4.8 6.8 mA -40°C to +85°C 2.0V 16 MIPS, 4.9 6.9 mA -40°C to +85°C 3.3V FOSC = 32 MHz DC31 26 78 A -40°C to +85°C 2.0V LPRC (15.5 KIPS), 26 80 A -40°C to +85°C 3.3V FOSC = 31 kHz Note 1: Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Typical parameters are for design guidance only and are not tested.  2010-2014 Microchip Technology Inc. DS30009996G-page 361

PIC24FJ128GA310 FAMILY TABLE 32-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Parameter Operating Typical(1) Max Units VDD Conditions No. Temperature Idle Current (IIDLE) DC40 81 — A -40°C to +85°C 2.0V 1 MIPS, 86 — A -40°C to +85°C 3.3V FOSC = 2 MHz DC43 0.27 — mA -40°C to +85°C 2.0V 4 MIPS, 0.28 — mA -40°C to +85°C 3.3V FOSC = 8 MHz DC47 1 1.35 mA -40°C to +85°C 2.0V 16 MIPS, 1.07 1.4 mA -40°C to +85°C 3.3V FOSC = 32 MHz DC50 0.47 — mA -40°C to +85°C 2.0V 4 MIPS (FRC), 0.48 — mA -40°C to +85°C 3.3V FOSC = 8 MHz DC51 21 76 A -40°C to +85°C 2.0V LPRC (15.5 KIPS), 21 78 A -40°C to +85°C 3.3V FOSC = 31 kHz Note 1: Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guid- ance only and are not tested. DS30009996G-page 362  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 32-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Parameter Operating Typical(1) Max Units VDD Conditions No. Temperature Power-Down Current (IPD) DC60 — — A -40°C 3.7 — A +25°C 2.0V 6.2 — A +60°C 13.6 27.5 A +85°C — — A -40° 3.8 — A +25°C 3.3V Sleep(2) 6.3 — A +60°C 13.7 28 A +85°C DC61 — — A -40° 0.33 — A +25°C 2.0V 2 — A +60°C 7.7 14.5 A +85°C Low-Voltage Sleep(3) — — A -40° 0.34 — A +25°C 3.3V 2 — A +60°C 7.9 15 A +85°C DC70 — — A -40° 0.01 — A +25°C 2.0V — — A +60°C — 1.1 A +85°C Deep Sleep — — A -40° 3.3V 0.04 — A +25°C — — A +60°C — 1.4 A +85°C 0.4 2.0 A -40°C to +85°C 0V RTCC with VBAT mode (LPRC/SOSC)(4) Note 1: Data in the Typical column is at 3.3V, +25°C unless otherwise stated. IPD is measured with all peripherals and clocks (PMD) shutdown; all the ports are made output and driven low. 2: The retention low-voltage regulator is disabled; RETEN (RCON<12>) = 0, LPCFG (CW1<10>) = 1. 3: The retention low-voltage regulator is enabled; RETEN (RCON<12>) = 1, LPCFG (CW1<10>) = 0. 4: The VBAT pin is connected to the battery and RTCC is running with VDD = 0.  2010-2014 Microchip Technology Inc. DS30009996G-page 363

PIC24FJ128GA310 FAMILY TABLE 32-7: DC CHARACTERISTICS: CURRENT (BOR, WDT, DSBOR, DSWDT, LCD) Standard Operating Conditions: 2V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Parameter Operating Typical(1) Max Units VDD Conditions No. Temperature Incremental Current Brown-out Reset (BOR)(2) DC20 3.1 5 A -40°C to +85°C 2.0V BOR(2) 4.3 6 A -40°C to +85°C 3.3V Incremental Current Watch Dog Timer (WDT)(2) DC71 0.8 1.5 A -40°C to +85°C 2.0V WDT(2) 0.8 1.5 A -40°C to +85°C 3.3V Incremental Current HLVD (HLVD)(2) DC75 5.7 15 A -40°C to +85°C 2.0V HLVD(2) 5.7 15 A -40°C to +85°C 3.3V Incremental Current Real-Time Clock and Calendar (RTCC)(2) DC77 0.4 1 A -40°C to +85°C 2.0V RTCC(2), 0.4 1 A -40°C to +85°C 3.3V RTCC with SOSC Incremental Current Real-Time Clock and Calendar (RTCC)(2) DC77a 0.4 1 A -40°C to +85°C 2.0V RTCC(2), 0.4 1 A -40°C to +85°C 3.3V RTCC with LPRC Incremental Current Deep Sleep BOR ( DSBOR)(2) DC81 0.07 0.3 A -40°C to +85°C 2.0V Deep Sleep BOR(2) 0.07 0.3 A -40°C to +85°C 3.3V Incremental Current Deep Sleep Watchdog Timer Reset ( DSWDT)(2) DC80 0.27 0.4 A -40°C to +85°C 2.0V Deep Sleep WDT(2) 0.27 0.4 A -40°C to +85°C 3.3V Incremental Current LCD ( LCD)(2) 0.8 3 A -40°C to +85°C LCD External/Internal(2,3), 3.3V 1/8 MUX, 1/3 Bias DC90 20 30 A -40°C to +85°C 2.0V LCD Charge Pump(2,4), 24 40 A -40°C to +85°C 3.3V 1/8 MUX, 1/3 Bias VBAT ADC Monitor(5) DC91 1.5 — A -40°C to +85°C 3.3V VBAT = 2V 4 — A -40°C to +85°C 3.3V VBAT = 3.3V Note 1: Data in the Typical column is at 3.3V, +25°C unless otherwise stated. IPD is measured with all peripherals and clocks (PMD) shut down; all the ports are made output and driven low. 2: Incremental current while the module is enabled and running. 3: LCD is enabled and running; no glass is connected; the resistor ladder current is not included. 4: LCD is enabled and running; no glass is connected. 5: The ADC channel is connected to the VBAT pin internally; this is the current during ADC VBAT operation. DS30009996G-page 364  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 32-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Param Symbol Characteristic Min Typ(1) Max Units Conditions No. VIL Input Low Voltage(3) DI10 I/O Pins with ST Buffer VSS — 0.2 VDD V DI11 I/O Pins with TTL Buffer VSS — 0.15 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSCI (XT mode) VSS — 0.2 VDD V DI17 OSCI (HS mode) VSS — 0.2 VDD V DI18 I/O Pins with I2C™ Buffer VSS — 0.3 VDD V DI19 I/O Pins with SMBus Buffer VSS — 0.8 V SMBus enabled VIH Input High Voltage(3) DI20 I/O Pins with ST Buffer: with Analog Functions, 0.8VDD — VDD V Digital Only 0.8VDD — 5.5 V DI21 I/O Pins with TTL Buffer: with Analog Functions, 0.25 VDD + 0.8 — VDD V Digital Only 0.25 VDD + 0.8 — 5.5 V DI25 MCLR 0.8 VDD — VDD V DI26 OSCI (XT mode) 0.7 VDD — VDD V DI27 OSCI (HS mode) 0.7 VDD — VDD V DI28 I/O Pins with I2C™ Buffer: with Analog Functions, 0.7 VDD — VDD V Digital Only 0.7 VDD — 5.5 V DI29 I/O Pins with SMBus Buffer: 2.5V  VPIN  VDD with Analog Functions, 2.1 VDD V Digital Only 2.1 5.5 V DI30 ICNPU CNxx Pull-up Current 150 290 550 A VDD = 3.3V, VPIN = VSS DI30A ICNPD CNxx Pull-down Current 150 260 550 A VDD = 3.3V, VPIN = VDD IIL Input Leakage Current(2) DI50 I/O Ports — — +1 A VSS  VPIN  VDD, pin at high-impedance — — +1 A VSS  VPIN  5.5, pin at high-impedance DI51 Analog Input Pins — — +1 A VSS  VPIN  VDD, pin at high-impedance DI55 MCLR — — +1 A VSS VPIN VDD DI56 OSCI/CLKI — — +1 A VSS VPIN VDD, EC, XT and HS modes Note 1: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Negative current is defined as current sourced by the pin. 3: Refer to Table1-4 for I/O pins buffer types.  2010-2014 Microchip Technology Inc. DS30009996G-page 365

PIC24FJ128GA310 FAMILY TABLE 32-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Param Symbol Characteristic Min Typ(1) Max Units Conditions No. VOL Output Low Voltage DO10 I/O Ports — — 0.4 V IOL = 6.6 mA, VDD = 3.6V — — 0.4 V IOL = 5.0 mA, VDD = 2V DO16 OSCO/CLKO — — 0.4 V IOL = 6.6 mA, VDD = 3.6V — — 0.4 V IOL = 5.0 mA, VDD = 2V VOH Output High Voltage DO20 I/O Ports 3.0 — — V IOH = -3.0 mA, VDD = 3.6V 2.4 — — V IOH = -6.0 mA, VDD = 3.6V 1.65 — — V IOH = -1.0 mA, VDD = 2V 1.4 — — V IOH = -3.0 mA, VDD = 2V DO26 OSCO/CLKO 2.4 — — V IOH = -6.0 mA, VDD = 3.6V 1.4 — — V IOH = -1.0 mA, VDD = 2V Note 1: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 32-10: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 2V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Param Symbol Characteristic Min Typ(1) Max Units Conditions No. Program Flash Memory D130 EP Cell Endurance 10000 — — E/W -40C to +85C D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage D132B VDD for Self-Timed Write VMIN — 3.6 V VMIN = Minimum operating voltage D133A TIW Self-Timed Word Write — 20 — s Cycle Time Self-Timed Row Write — 1.5 — ms Cycle Time D133B TIE Self-Timed Page Erase 20 — 40 ms Time D134 TRETD Characteristic Retention 20 — — Year If no other specifications are violated D135 IDDP Supply Current during — 16 — mA Programming Note 1: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. DS30009996G-page 366  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 32-11: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param Symbol Characteristics Min Typ Max Units Comments No. VRGOUT Regulator Output Voltage — 1.8 — V VBG Internal Band Gap Reference 1.14 1.2 1.26 V CEFC External Filter Capacitor Value 4.7 10 — F Series resistance < 3 Ohm recommended; < 5 Ohm required TVREG Voltage Regulator Start-up Time — 10 — s VREGS = 1 with any POR or BOR TBG Band Gap Reference Start-up — 1 — ms Time VLVR Low-Voltage Regulator Output — 1.2 — V RETEN = 1, LPCFG = 0 Voltage TABLE 32-12: VBAT OPERATING VOLTAGE SPECIFICATIONS Param Symbol Characteristic Min Typ Max Units Comments No. VBT Operating Voltage 1.6 — 3.6 V Battery connected to the VBAT pin VBTADC VBAT ADC Monitoring 1.6 — 3.6 V ADC monitoring the VBAT pin Voltage Specification(1) using the internal ADC channel VBTRTC — 1.65 — V RTCC Reset voltage with VBTBOR (CW3<7>) = 1 VBTRST — 0.65 — V VBPOR bit (RCON2<1>) Reset voltage Note 1: Measuring the ADC value, using the ADC, is represented by the equation: Measured Voltage = ((VBAT/2)/VDD) * 1024) for 10-bit ADC and Measured Voltage = ((VBAT/2)VDD) * 4096) for 12-bit ADC. TABLE 32-13: CTMU CURRENT SOURCE SPECIFICATIONS Standard Operating Conditions: 2V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Param Sym Characteristic Min Typ(1) Max Units Comments Conditions No. IOUT1 CTMU Current — 550 — nA CTMUICON<1:0> = 00 Source, Base Range IOUT2 CTMU Current — 5.5 — A CTMUICON<1:0> = 01 Source, 10x Range 2.5V < VDD < VDDMAX IOUT3 CTMU Current — 55 — A CTMUICON<1:0> = 10 Source, 100x Range IOUT4 CTMU Current — 550 — A CTMUICON<1:0>=11(2) Source, 1000x Range V Voltage Change per — 3 — mV/°C Degree Celsius Note 1: Nominal value at center point of current trim range (CTMUICON<7:2> = 000000). 2: Do not use this current range with temperature sensing diode.  2010-2014 Microchip Technology Inc. DS30009996G-page 367

PIC24FJ128GA310 FAMILY TABLE 32-14: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param Symbol Characteristic Min Typ Max Units Conditions No. DC18 VHLVD HLVD Voltage on VDD HLVDL<3:0> = 0100(1) 3.45 — 3.75 V Transition HLVDL<3:0> = 0101 3.30 — 3.6 V HLVDL<3:0> = 0110 3.00 — 3.3 V HLVDL<3:0> = 0111 2.80 — 3.1 V HLVDL<3:0> = 1000 2.70 — 2.95 V HLVDL<3:0> = 1001 2.50 — 2.75 V HLVDL<3:0> = 1010 2.40 — 2.60 V HLVDL<3:0> = 1011 2.30 — 2.5 V HLVDL<3:0> = 1100 2.20 — 2.4 V HLVDL<3:0> = 1101 2.10 — 2.3 V HLVDL<3:0> = 1110 2.00 — 2.2 V DC101 VTHL HLVD Voltage on HLVDL<3:0> = 1111 — 1.20 — V HLVDIN Pin Transition Note 1: Trip points for values of HLVD<3:0>, from ‘0000’ to ‘0011’, are not implemented. TABLE 32-15: COMPARATOR DC SPECIFICATIONS Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param Symbol Characteristic Min Typ Max Units Comments No. D300 VIOFF Input Offset Voltage — 20 40 mV D301 VICM Input Common-Mode Voltage) 0 — VDD V D302 CMRR Common-Mode Rejection Ratio 55 — — dB D306 IQCMP AVDD Quiescent Current per — 27 — A Comparator Comparator enabled D307 TRESP Response Time — 300 — ns (Note 1) D308 TMC2OV Comparator Mode Change to — — 10 S Valid Output Note 1: Measured with one input at VDD/2 and the other transitioning from VSS to VDD, 40 mV step, 15 mV overdrive. TABLE 32-16: COMPARATOR VOLTAGE REFERENCE DC SPECIFICATIONS Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param Symbol Characteristic Min Typ Max Units Comments No. VRD310 CVRES Resolution VDD/24 — VDD/32 LSb VRD311 CVRAA Absolute Accuracy — — AVDD – 1.5 LSb VRD312 CVRUR Unit Resistor Value (R) — 2K —  DS30009996G-page 368  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 32.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24FJ128GA310 family AC characteristics and timing parameters. TABLE 32-17: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 2V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Operating voltage VDD range as described in Section32.1 “DC Characteristics”. FIGURE 32-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSCO Load Condition 2 – for OSCO VDD/2 RL Pin CL VSS CL Pin RL = 464 CL = 50 pF for all pins except OSCO VSS 15 pF for OSCO output TABLE 32-18: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol Characteristic Min Typ(1) Max Units Conditions No. DO50 COSCO OSCO/CLKO Pin — — 15 pF In XT and HS modes when external clock is used to drive OSCI DO56 CIO All I/O Pins and OSCO — — 50 pF EC mode DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode Note 1: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.  2010-2014 Microchip Technology Inc. DS30009996G-page 369

PIC24FJ128GA310 FAMILY FIGURE 32-3: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 OSCI OS20 OS30 OS30 OS31 OS31 OS25 CLKO OS40 OS41 TABLE 32-19: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Param Symbol Characteristic Min Typ(1) Max Units Conditions No. OS10 FOSC External CLKI Frequency DC — 32 MHz EC (External clocks allowed 4 — 8 MHz ECPLL only in EC mode) Oscillator Frequency 3.5 — 10 MHz XT 4 — 8 MHz XTPLL 10 — 32 MHz HS 4 — 8 MHz HSPLL 31 — 33 kHz SOSC OS20 TOSC TOSC = 1/FOSC — — — — See Parameter OS10 for FOSC value OS25 TCY Instruction Cycle Time(2) 62.5 — DC ns OS30 TosL, External Clock in (OSCI) 0.45 x TOSC — — ns EC TosH High or Low Time OS31 TosR, External Clock in (OSCI) — — 20 ns EC TosF Rise or Fall Time OS40 TckR CLKO Rise Time(3) — 6 10 ns OS41 TckF CLKO Fall Time(3) — 6 10 ns Note 1: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type, under standard operating conditions, with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. 3: Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY). DS30009996G-page 370  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 32-20: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2V TO 3.6V) Standard Operating Conditions: 2V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Param Symbol Characteristic Min Typ(1) Max Units Conditions No. OS50 FPLLI PLL Input Frequency 4 — 8 MHz ECPLL mode Range(1) 4 — 8 MHz HSPLL mode 4 — 8 MHz XTPLL mode OS52 TLOCK PLL Start-up Time — — 128 s (Lock Time) OS53 DCLK CLKO Stability (Jitter) -0.25 — 0.25 % Note 1: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 32-21: INTERNAL RC ACCURACY Standard Operating Conditions: 2V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA +85°C for Industrial Param Characteristic Min Typ Max Units Conditions No. F20 FRC Accuracy @ -1 — 1 % -10°C  TA +85°C 2V  VDD 3.6V 8MHz(1,2) -1.5 — 1.5 % -40°C  TA -10°C 2V  VDD 3.6V F21 LPRC @ 31 kHz -20 — 20 % -40°C  TA +85°C VCAP (on-chip regulator output voltage) = 1.8V Note 1: Frequency is calibrated at +25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift. 2: To achieve this accuracy, physical stress applied to the microcontroller package (ex., by flexing the PCB) must be kept to a minimum. TABLE 32-22: RC OSCILLATOR START-UP TIME Standard Operating Conditions: 2V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Param Characteristic Min Typ Max Units Conditions No. TFRC — 15 — s TLPRC — 50 — s  2010-2014 Microchip Technology Inc. DS30009996G-page 371

PIC24FJ128GA310 FAMILY FIGURE 32-4: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin Old Value New Value (Output) DO31 DO32 Note: Refer to Figure32-2 for load conditions. TABLE 32-23: CLKO AND I/O TIMING REQUIREMENTS Standard Operating Conditions: 2V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Param Symbol Characteristic Min Typ(1) Max Units Conditions No. DO31 TIOR Port Output Rise Time — 10 25 ns DO32 TIOF Port Output Fall Time — 10 25 ns DI35 TINP INTx Pin High or Low 20 — — ns Time (input) DI40 TRBP CNx High or Low Time 2 — — TCY (input) Note 1: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. DS30009996G-page 372  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 32-24: RESET AND BROWN-OUT RESET REQUIREMENTS Standard Operating Conditions: 2V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Para Symbo m Characteristic Min Typ Max Units Conditions l No. SY10 TMCL MCLR Pulse Width (Low) 2 — — s SY12 TPOR Power-on Reset Delay — 2 — s SY13 TIOZ I/O High-Impedance from — — 100 ns MCLR Low or Watchdog Timer Reset SY25 TBOR Brown-out Reset Pulse 1 — — s VDD VBOR Width TRST Internal State Reset Time — 50 — s SY71 TPM Program Memory — 20 — s Sleep wake-up(1) with Wake-up Time VREGS = 0 — 1 — s Sleep wake-up(1) with VREGS = 1 SY72 TLVR Low-Voltage Regulator — 90 — s Sleep wake-up(1) with Wake-up Time VREGS = 0 — 70 — s Sleep wake-up(1) with VREGS = 1 TDSWU Deep Sleep Wake-up — 200 — s VCAP fully discharged before Time wake-up(1) Note 1: Wake-up times are based on the CPU running on the external EC clock.  2010-2014 Microchip Technology Inc. DS30009996G-page 373

PIC24FJ128GA310 FAMILY FIGURE 32-5: TIMER1/2/3/4/5 EXTERNAL CLOCK INPUT TIMING TxCK Pin TtL TtH TtP TABLE 32-25: TIMER1/2/3/4/5 EXTERNAL CLOCK INPUT REQUIREMENTS(1) Param. Symbol Characteristic Min Max Units Conditions No. TtH TxCK High Pulse Time Synchronous w/Prescaler TCY + 20 — ns Must also meet Asynchronous w/Prescaler 10 — ns Parameter Ttp Asynchronous Counter 20 — ns TtL TxCK Low Pulse Time Synchronous w/Prescaler TCY + 20 — ns Must also meet Asynchronous w/Prescaler 10 — ns Parameter Ttp Asynchronous Counter 20 — ns TtP TxCK External Input Synchronous w/Prescaler 2 * TCY + 40 — ns N = Prescale Value Period Asynchronous w/Prescaler Greater of: — ns (1, 4, 8, 16) 20 or 2 * TCY + 40 N Asynchronous Counter 40 — ns Delay for Input Edge Synchronous 1 2 TCY to Timer Increment Asynchronous — 20 ns Note 1: Asynchronous mode is available only on Timer1. FIGURE 32-6: INPUT CAPTURE x TIMINGS ICx Pin (Input Capture Mode) IC10 IC11 IC15 TABLE 32-26: INPUT CAPTURE x REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. IC10 TccL ICx Input Low Time – No Prescaler TCY + 20 — ns Must also meet Synchronous Timer With Prescaler 20 — ns Parameter IC15 IC11 TccH ICx Input Low Time – No Prescaler TCY + 20 — ns Must also meet Synchronous Timer With Prescaler 20 — ns Parameter IC15 IC15 TccP ICx Input Period – Synchronous Timer 2 * TCY + 40 — ns N = Prescale Value N (1, 4, 16) DS30009996G-page 374  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY FIGURE 32-7: INPUT CAPTURE x TIMINGS ICx Pin (Input Capture Mode) IC11 IC10 IC15 TABLE 32-27: INPUT CAPTURE x TIMINGS REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. IC10 TccL ICx Input Low Time – No Prescaler TCY + 20 — ns Must also meet Synchronous Timer With Prescaler 20 — ns Parameter IC15 IC11 TccH ICx Input Low Time – No Prescaler TCY + 20 — ns Must also meet Synchronous Timer With Prescaler 20 — ns Parameter IC15 IC15 TccP ICx Input Period – Synchronous Timer 2 * TCY + 40 — ns N = Prescale N Value (1, 4, 16) FIGURE 32-8: OUTPUT COMPARE x TIMINGS OCx (Output Compare or PWM Mode) OC11 OC10 TABLE 32-28: OUTPUT COMPARE 1 TIMINGS Param. Symbol Characteristic Min Max Unit Condition No. OC11 TCCR OC1 Output Rise Time — 10 ns — — ns OC10 TCCF OC1 Output Fall Time — 10 ns — — ns FIGURE 32-9: PWM MODULE TIMING REQUIREMENTS OC20 OCFx OC15 PWM  2010-2014 Microchip Technology Inc. DS30009996G-page 375

PIC24FJ128GA310 FAMILY TABLE 32-29: PWM TIMING REQUIREMENTS Param. Symbol Characteristic Min Typ(1) Max Unit Condition No. OC15 TFD Fault Input to PWM I/O — — 25 ns VDD = 3.0V, -40C to +85C Change OC20 TFH Fault Input Pulse Width 50 — — ns VDD = 3.0V, -40C to +85C Note1: Data in “Typ” column is at 3.3V, +25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 32-10: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Start Stop Condition Condition TABLE 32-30: I2Cx BUS START/STOP BITS TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C (Industrial) Param Symbol Characteristic Min(1) Max Units Conditions No. IM30 TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — s Only relevant for Setup Time 400 kHz mode TCY/2 (BRG + 1) — s Repeated Start condition 1 MHz mode(2) TCY/2 (BRG + 1) — s IM31 THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — s After this period, the Hold Time 400 kHz mode TCY/2 (BRG + 1) — s first clock pulse is generated 1 MHz mode(2) TCY/2 (BRG + 1) — s IM33 TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — s Setup Time 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — ns Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns 1 MHz mode(2) TCY/2 (BRG + 1) — ns Note 1: BRG is the value of the I2C™ Baud Rate Generator. Refer to Section 17.2 “Setting Baud Rate When Operating as a Bus Master” for details. 2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only). DS30009996G-page 376  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY FIGURE 32-11: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM11 IM21 SCLx IM10 IM25 IM26 IM20 SDAx In IM45 IM40 SDAx Out TABLE 32-31: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C (Industrial) Param Symbol Characteristic Min(1) Max Units Conditions No. IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s IM20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 100 ns IM21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 300 ns IM25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns 1 MHz mode(2) — — ns IM26 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 s 1 MHz mode(2) — — ns IM40 TAA:SCL Output Valid 100 kHz mode — 3500 ns From Clock 400 kHz mode — 1000 ns 1 MHz mode(2) — — ns IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be 400 kHz mode 1.3 — s free before a new transmission can start 1 MHz mode(2) — — s IM50 CB Bus Capacitive Loading — 400 pF Note 1: BRG is the value of the I2C™ Baud Rate Generator. Refer to Section 17.2 “Setting Baud Rate When Operating as a Bus Master” for details. 2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).  2010-2014 Microchip Technology Inc. DS30009996G-page 377

PIC24FJ128GA310 FAMILY FIGURE 32-12: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS31 IS34 IS30 IS33 SDAx Start Stop Condition Condition TABLE 32-32: I2Cx BUS START/STOP BITS TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C (Industrial) Param Symbol Characteristic Min Max Units Conditions No. IS30 TSU:STA Start Condition 100 kHz mode 4.7 — s Only relevant for Repeated Setup Time 400 kHz mode 0.6 — s Start condition 1 MHz mode(1) 0.25 — s IS31 THD:STA Start Condition 100 kHz mode 4.0 — s After this period, the first Hold Time 400 kHz mode 0.6 — s clock pulse is generated 1 MHz mode(1) 0.25 — s IS33 TSU:STO Stop Condition 100 kHz mode 4.7 — s Setup Time 400 kHz mode 0.6 — s 1 MHz mode(1) 0.6 — s IS34 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — ns 1 MHz mode(1) 250 — ns Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only). FIGURE 32-13: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS11 IS21 IS10 SCLx IS25 IS20 IS26 SDAx In IS45 IS40 SDAx Out DS30009996G-page 378  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 32-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C (Industrial) Param Symbol Characteristic Min Max Units Conditions No. IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — s — IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — s — IS20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns IS21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns IS25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns 1 MHz mode(1) 100 — ns IS26 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 s 1 MHz mode(1) 0 0.3 s IS40 TAA:SCL Output Valid From 100 kHz mode 0 3500 ns Clock 400 kHz mode 0 1000 ns 1 MHz mode(1) 0 350 ns IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start 1 MHz mode(1) 0.5 — s IS50 CB Bus Capacitive Loading — 400 pF Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only).  2010-2014 Microchip Technology Inc. DS30009996G-page 379

PIC24FJ128GA310 FAMILY FIGURE 32-14: SPIx MODULE MASTER MODE TIMING CHARACTERISTICS (CKE = 0) SCKx (CKP = 0) SP11 SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP31 SP30 SDIx MSb In Bit 14 - - - -1 LSb In SP40 SP41 TABLE 32-34: SPIx MASTER MODE TIMING REQUIREMENTS (CKE = 0) Standard Operating Conditions: 2.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Param Symbol Characteristic Min Typ(1) Max Units Conditions No. SP10 TscL SCKx Output Low Time(2) TCY/2 — — ns SP11 TscH SCKx Output High Time(2) TCY/2 — — ns SP20 TscF SCKx Output Fall Time(3) — 10 25 ns SP21 TscR SCKx Output Rise Time(3) — 10 25 ns SP30 TdoF SDOx Data Output Fall Time(3) — 10 25 ns SP31 TdoR SDOx Data Output Rise Time(3) — 10 25 ns SP35 TscH2doV, SDOx Data Output Valid after — — 30 ns TscL2doV SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 20 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 20 — — ns TscL2diL to SCKx Edge Note1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: The minimum clock period for SCKx is 100 ns; therefore, the clock generated in Master mode must not violate this specification. 3: Assumes 50 pF load on all SPIx pins. DS30009996G-page 380  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY FIGURE 32-15: SPIx MODULE MASTER MODE TIMING CHARACTERISTICS (CKE = 1) SP36 SCKx (CKP = 0) SP11 SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP40 SP30,SP31 SDIx MSb In Bit 14 - - - -1 LSb In SP41 TABLE 32-35: SPIx MODULE MASTER MODE TIMING REQUIREMENTS (CKE = 1) Standard Operating Conditions: 2.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Param Symbol Characteristic Min Typ(1) Max Units Conditions No. SP10 TscL SCKx Output Low Time(2) TCY/2 — — ns SP11 TscH SCKx Output High Time(2) TCY/2 — — ns SP20 TscF SCKx Output Fall Time(3) — 10 25 ns SP21 TscR SCKx Output Rise Time(3) — 10 25 ns SP30 TdoF SDOx Data Output Fall Time(3) — 10 25 ns SP31 TdoR SDOx Data Output Rise Time(3) — 10 25 ns SP35 TscH2doV, SDOx Data Output Valid after — — 30 ns TscL2doV SCKx Edge SP36 TdoV2sc, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 20 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 20 — — ns TscL2diL to SCKx Edge Note1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 3: Assumes 50 pF load on all SPIx pins.  2010-2014 Microchip Technology Inc. DS30009996G-page 381

PIC24FJ128GA310 FAMILY FIGURE 32-16: SPIx MODULE SLAVE MODE TIMING CHARACTERISTICS (CKE = 0) SSx SP50 SP52 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SCKx (CKP = 1) SP72 SP73 SP35 SDOx MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SSDDIIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 TABLE 32-36: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS (CKE = 0) Standard Operating Conditions: 2.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Param Symbol Characteristic Min Typ(1) Max Units Conditions No. SP70 TscL SCKx Input Low Time 30 — — ns SP71 TscH SCKx Input High Time 30 — — ns SP72 TscF SCKx Input Fall Time(2) — 10 25 ns SP73 TscR SCKx Input Rise Time(2) — 10 25 ns SP30 TdoF SDOx Data Output Fall Time(2) — 10 25 ns SP31 TdoR SDOx Data Output Rise Time(2) — 10 25 ns SP35 TscH2doV, SDOx Data Output Valid after — — 30 ns TscL2doV SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 20 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 20 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx to SCKx  or SCKx Input 120 — — ns TssL2scL SP51 TssH2doZ SSx  to SDOx Output 10 — 50 ns High-Impedance SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns TscL2ssH Note1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Assumes 50 pF load on all SPIx pins. DS30009996G-page 382  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY FIGURE 32-17: SPIx MODULE SLAVE MODE TIMING CHARACTERISTICS (CKE = 1) SP60 SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SCKx (CKP = 1) SP35 SP72 SP73 SP52 SDOx MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 TABLE 32-37: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS (CKE = 1) Standard Operating Conditions: 2.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Param Symbol Characteristic Min Typ(1) Max Units Conditions No. SP70 TscL SCKx Input Low Time 30 — — ns SP71 TscH SCKx Input High Time 30 — — ns SP72 TscF SCKx Input Fall Time(2) — 10 25 ns SP73 TscR SCKx Input Rise Time(2) — 10 25 ns SP30 TdoF SDOx Data Output Fall Time(2) — 10 25 ns SP31 TdoR SDOx Data Output Rise Time(2) — 10 25 ns SP35 TscH2doV, SDOx Data Output Valid after SCKx Edge — — 30 ns TscL2doV SP40 TdiV2scH, Setup Time of SDIx Data Input to 20 — — ns TdiV2scL SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input to 20 — — ns TscL2diL SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx  Input 120 — — ns TssL2scL SP51 TssH2doZ SSx  to SDOx Output 10 — 50 ns High-Impedance(3) Note1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 3: Assumes 50 pF load on all SPIx pins.  2010-2014 Microchip Technology Inc. DS30009996G-page 383

PIC24FJ128GA310 FAMILY TABLE 32-37: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS (CKE = 1) (CONTINUED) Standard Operating Conditions: 2.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Param Symbol Characteristic Min Typ(1) Max Units Conditions No. SP52 TscH2ssH SSx  after SCKx Edge 1.5 TCY + 40 — — ns TscL2ssH SP60 TssL2doV SDOx Data Output Valid after SSx Edge — — 50 ns Note1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 3: Assumes 50 pF load on all SPIx pins. FIGURE 32-18: UARTx BAUD RATE GENERATOR OUTPUT TIMING BRGx + 1 * TCY TLW THW BCLKx TBLD TBHD UxTX FIGURE 32-19: UARTx START BIT EDGE DETECTION BRGx Any Value TCY Start bit Detected, BRGx Started Cycle Clock TSETUP TSTDELAY UxRX DS30009996G-page 384  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 32-38: UARTx AC SPECIFICATIONS Symbol Characteristics Min Typ Max Units TLW BCLKx High Time 20 TCY/2 — ns THW BCLKx Low Time 20 (TCY * BRGx) + TCY/2 — ns TBLD BCLKx Falling Edge Delay from UxTX -50 — 50 ns TBHD BCLKx Rising Edge Delay from UxTX TCY/2 – 50 — TCY/2 + 50 ns TWAK Min. Low on UxRX Line to Cause Wake-up — 1 — s TCTS Min. Low on UxCTS Line to Start TCY — — ns Transmission TSETUP Start bit Falling Edge to System Clock Rising 3 — — ns Edge Setup Time TSTDELAY Maximum Delay in the Detection of the — — TCY + TSETUP ns Start bit Falling Edge  2010-2014 Microchip Technology Inc. DS30009996G-page 385

PIC24FJ128GA310 FAMILY TABLE 32-39: ADC MODULE SPECIFICATIONS Standard Operating Conditions: 2V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C Param Symbol Characteristic Min. Typ Max. Units Conditions No. Device Supply AD01 AVDD Module VDD Supply Greater of: — Lesser of: V VDD – 0.3 VDD + 0.3 or 2.2 or 3.6 AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.3 V Reference Inputs AD05 VREFH Reference Voltage High AVSS + 1.7 — AVDD V AD06 VREFL Reference Voltage Low AVSS — AVDD – 1.7 V AD07 VREF Absolute Reference AVSS – 0.3 — AVDD + 0.3 V Voltage Analog Input AD10 VINH-VINL Full-Scale Input Span VREFL — VREFH V (Note 2) AD11 VIN Absolute Input Voltage AVSS – 0.3 — AVDD + 0.3 V AD12 VINL Absolute VINL Input AVSS – 0.3 — AVDD/3 V Voltage AD13 Leakage Current — ±1.0 ±610 nA VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V, Source Impedance = 2.5k AD17 RIN Recommended Impedance — — 2.5K  10-bit of Analog Voltage Source ADC Accuracy AD20B Nr Resolution — 12 — bits AD21B INL Integral Nonlinearity — ±1 <±2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD22B DNL Differential Nonlinearity — — <±1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD23B GERR Gain Error — ±1 ±3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD24B EOFF Offset Error — ±1 ±2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD25B Monotonicity(1) — — — — Guaranteed Note 1: The ADC conversion result never decreases with an increase in the input voltage and has no missing codes. 2: Measurements are taken with the external VREF+ and VREF- used as the ADC voltage reference. DS30009996G-page 386  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY TABLE 32-40: ADC CONVERSION TIMING REQUIREMENTS(1) Standard Operating Conditions: 2V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C Param Symbol Characteristic Min. Typ Max. Units Conditions No. Clock Parameters AD50 TAD ADC Clock Period 312 — — ns AD51 tRC ADC Internal RC Oscillator — 250 — ns Period Conversion Rate AD55 tCONV Conversion Time — 14 — TAD AD56 FCNV Throughput Rate — — 200 ksps AVDD > 2.7V AD57 tSAMP Sample Time — 1 — TAD Clock Parameters AD61 tPSS Sample Start Delay from Setting 2 — 3 TAD Sample bit (SAMP) Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures.  2010-2014 Microchip Technology Inc. DS30009996G-page 387

PIC24FJ128GA310 FAMILY NOTES: DS30009996G-page 388  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 33.0 PACKAGING INFORMATION 33.1 Package Marking Information 64-Lead QFN (9x9x0.9 mm) Example XXXXXXXXXXX PIC24FJ128 XXXXXXXXXXX GA306-I/MRe3 XXXXXXXXXXX 1450017 YYWWNNN 64-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX PIC24FJ128 XXXXXXXXXX GA306-I/ XXXXXXXXXX PTe3 YYWWNNN 1420017 80-Lead TQFP (12x12x1mm) Example XXXXXXXXXXXX PIC24F128GA XXXXXXXXXXXX 308-I/PTe3 YYWWNNN 1450017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010-2014 Microchip Technology Inc. DS30009996G-page 389

PIC24FJ128GA310 FAMILY 33.2 Package Marking Information 100-Lead TQFP (12x12x1 mm) Example XXXXXXXXXXXX PIC24FJ128GA XXXXXXXXXXXX 310-I/PTe3 YYWWNNN 1410017 100-Lead TQFP (14x14x1mm) Example XXXXXXXXXXXX PIC24FJ128GA XXXXXXXXXXXX 310-I/PFe3 YYWWNNN 1450017 121-BGA (10x10x1.1 mm) Example XXXXXXXXXXX PIC24FJ128 XXXXXXXXXXX GA310-I/BGe3 XXXXXXXXXXX 1420017 YYWWNNN DS30009996G-page 390  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 33.3 Package Details The following sections give the technical details of the packages. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2014 Microchip Technology Inc. DS30009996G-page 391

PIC24FJ128GA310 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30009996G-page 392  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2014 Microchip Technology Inc. DS30009996G-page 393

PIC24FJ128GA310 FAMILY 64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 D1/2 D NOTE 2 E1/2 A B E1 E A A SEE DETAIL 1 N 4X N/4 TIPS 0.20 C A-B D 1 3 2 4X NOTE 1 0.20 H A-B D TOP VIEW A2 A C 0.05 SEATING PLANE A1 64 X b 0.08 C 0.08 C A-B D e SIDE VIEW Microchip Technology Drawing C04-085C Sheet 1 of 2 DS30009996G-page 394  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY 64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging H c (cid:69) L (cid:84) (L1) X=A—B OR D SECTION A-A X e/2 DETAIL 1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 64 Lead Pitch e 0.50 BSC Overall Height A - - 1.20 Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 - 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle (cid:73) 0° 3.5° 7° Overall Width E 12.00 BSC Overall Length D 12.00 BSC Molded Package Width E1 10.00 BSC Molded Package Length D1 10.00 BSC Lead Thickness c 0.09 - 0.20 Lead Width b 0.17 0.22 0.27 Mold Draft Angle Top (cid:68) 11° 12° 13° Notes: Mold Draft Angle Bottom (cid:69) 11° 12° 13° 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-085C Sheet 2 of 2  2010-2014 Microchip Technology Inc. DS30009996G-page 395

PIC24FJ128GA310 FAMILY 64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 E C2 G Y1 X1 RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 0.50 BSC Contact Pad Spacing C1 11.40 Contact Pad Spacing C2 11.40 Contact Pad Width (X28) X1 0.30 Contact Pad Length (X28) Y1 1.50 Distance Between Pads G 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2085B Sheet 1 of 1 DS30009996G-page 396  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)(cid:28)(cid:29)(cid:27)(cid:28)(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)(cid:28)#(cid:3)(cid:3)(cid:9)(cid:30)(cid:30)(cid:9)$(cid:16)(cid:19)(cid:21)(cid:10)% & (cid:13)(cid:6)’ 4(cid:24)(cid:23)(cid:14)’(cid:25)(cid:13)(cid:14)((cid:24)"’(cid:14)(cid:22)#(cid:23)(cid:23)(cid:13)(cid:27)’(cid:14)(cid:10)(cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)$(cid:23)(cid:11)+(cid:21)(cid:27)(cid:12)")(cid:14)(cid:10)(cid:28)(cid:13)(cid:11)"(cid:13)(cid:14)"(cid:13)(cid:13)(cid:14)’(cid:25)(cid:13)(cid:14)(cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:21)(cid:27)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:22)(cid:21)&(cid:21)(cid:22)(cid:11)’(cid:21)(cid:24)(cid:27)(cid:14)(cid:28)(cid:24)(cid:22)(cid:11)’(cid:13)$(cid:14)(cid:11)’(cid:14) (cid:25)’’(cid:10)366+++(cid:31)((cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:31)(cid:22)(cid:24)(6(cid:10)(cid:11)(cid:22)5(cid:11)(cid:12)(cid:21)(cid:27)(cid:12) D D1 E e E1 b N NOTE1 123 NOTE2 α A c φ β A1 A2 L L1 7(cid:27)(cid:21)’" (cid:20)(cid:30)88(cid:30)(cid:20)/(cid:26)/(cid:8)(cid:3) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:14)8(cid:21)((cid:21)’" (cid:20)(cid:30)9 9:(cid:20) (cid:20)(cid:7); 9#(*(cid:13)(cid:23)(cid:14)(cid:24)&(cid:14)8(cid:13)(cid:11)$" 9 (cid:17)(cid:4) 8(cid:13)(cid:11)$(cid:14) (cid:21)’(cid:22)(cid:25) (cid:13) (cid:4)(cid:31)0(cid:4)(cid:14)2(cid:3), :!(cid:13)(cid:23)(cid:11)(cid:28)(cid:28)(cid:14)<(cid:13)(cid:21)(cid:12)(cid:25)’ (cid:7) = = (cid:15)(cid:31)(cid:18)(cid:4) (cid:20)(cid:24)(cid:28)$(cid:13)$(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)(cid:26)(cid:25)(cid:21)(cid:22)5(cid:27)(cid:13)"" (cid:7)(cid:18) (cid:4)(cid:31)(cid:6)0 (cid:15)(cid:31)(cid:4)(cid:4) (cid:15)(cid:31)(cid:4)0 (cid:3)’(cid:11)(cid:27)$(cid:24)&&(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:31)(cid:4)0 = (cid:4)(cid:31)(cid:15)0 4(cid:24)(cid:24)’(cid:14)8(cid:13)(cid:27)(cid:12)’(cid:25) 8 (cid:4)(cid:31)(cid:5)0 (cid:4)(cid:31)>(cid:4) (cid:4)(cid:31)(cid:19)0 4(cid:24)(cid:24)’(cid:10)(cid:23)(cid:21)(cid:27)’ 8(cid:15) (cid:15)(cid:31)(cid:4)(cid:4)(cid:14)(cid:8)/4 4(cid:24)(cid:24)’(cid:14)(cid:7)(cid:27)(cid:12)(cid:28)(cid:13) (cid:3) (cid:4)? (cid:16)(cid:31)0? (cid:19)? :!(cid:13)(cid:23)(cid:11)(cid:28)(cid:28)(cid:14)@(cid:21)$’(cid:25) / (cid:15)(cid:5)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), :!(cid:13)(cid:23)(cid:11)(cid:28)(cid:28)(cid:14)8(cid:13)(cid:27)(cid:12)’(cid:25) (cid:2) (cid:15)(cid:5)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), (cid:20)(cid:24)(cid:28)$(cid:13)$(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)@(cid:21)$’(cid:25) /(cid:15) (cid:15)(cid:18)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), (cid:20)(cid:24)(cid:28)$(cid:13)$(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)8(cid:13)(cid:27)(cid:12)’(cid:25) (cid:2)(cid:15) (cid:15)(cid:18)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), 8(cid:13)(cid:11)$(cid:14)(cid:26)(cid:25)(cid:21)(cid:22)5(cid:27)(cid:13)"" (cid:22) (cid:4)(cid:31)(cid:4)(cid:6) = (cid:4)(cid:31)(cid:18)(cid:4) 8(cid:13)(cid:11)$(cid:14)@(cid:21)$’(cid:25) * (cid:4)(cid:31)(cid:15)(cid:19) (cid:4)(cid:31)(cid:18)(cid:18) (cid:4)(cid:31)(cid:18)(cid:19) (cid:20)(cid:24)(cid:28)$(cid:14)(cid:2)(cid:23)(cid:11)&’(cid:14)(cid:7)(cid:27)(cid:12)(cid:28)(cid:13)(cid:14)(cid:26)(cid:24)(cid:10) (cid:4) (cid:15)(cid:15)? (cid:15)(cid:18)? (cid:15)(cid:16)? (cid:20)(cid:24)(cid:28)$(cid:14)(cid:2)(cid:23)(cid:11)&’(cid:14)(cid:7)(cid:27)(cid:12)(cid:28)(cid:13)(cid:14)2(cid:24)’’(cid:24)( (cid:5) (cid:15)(cid:15)? (cid:15)(cid:18)? (cid:15)(cid:16)? & (cid:13)(cid:6)(cid:12)’ (cid:15)(cid:31) (cid:21)(cid:27)(cid:14)(cid:15)(cid:14)!(cid:21)"#(cid:11)(cid:28)(cid:14)(cid:21)(cid:27)$(cid:13)%(cid:14)&(cid:13)(cid:11)’#(cid:23)(cid:13)(cid:14)((cid:11)(cid:29)(cid:14)!(cid:11)(cid:23)(cid:29))(cid:14)*#’(cid:14)(#"’(cid:14)*(cid:13)(cid:14)(cid:28)(cid:24)(cid:22)(cid:11)’(cid:13)$(cid:14)+(cid:21)’(cid:25)(cid:21)(cid:27)(cid:14)’(cid:25)(cid:13)(cid:14)(cid:25)(cid:11)’(cid:22)(cid:25)(cid:13)$(cid:14)(cid:11)(cid:23)(cid:13)(cid:11)(cid:31) (cid:18)(cid:31) ,(cid:25)(cid:11)(&(cid:13)(cid:23)"(cid:14)(cid:11)’(cid:14)(cid:22)(cid:24)(cid:23)(cid:27)(cid:13)(cid:23)"(cid:14)(cid:11)(cid:23)(cid:13)(cid:14)(cid:24)(cid:10)’(cid:21)(cid:24)(cid:27)(cid:11)(cid:28)-(cid:14)"(cid:21).(cid:13)(cid:14)((cid:11)(cid:29)(cid:14)!(cid:11)(cid:23)(cid:29)(cid:31) (cid:16)(cid:31) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)"(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:27)$(cid:14)/(cid:15)(cid:14)$(cid:24)(cid:14)(cid:27)(cid:24)’(cid:14)(cid:21)(cid:27)(cid:22)(cid:28)#$(cid:13)(cid:14)((cid:24)(cid:28)$(cid:14)&(cid:28)(cid:11)"(cid:25)(cid:14)(cid:24)(cid:23)(cid:14)(cid:10)(cid:23)(cid:24)’(cid:23)#"(cid:21)(cid:24)(cid:27)"(cid:31)(cid:14)(cid:20)(cid:24)(cid:28)$(cid:14)&(cid:28)(cid:11)"(cid:25)(cid:14)(cid:24)(cid:23)(cid:14)(cid:10)(cid:23)(cid:24)’(cid:23)#"(cid:21)(cid:24)(cid:27)"(cid:14)"(cid:25)(cid:11)(cid:28)(cid:28)(cid:14)(cid:27)(cid:24)’(cid:14)(cid:13)%(cid:22)(cid:13)(cid:13)$(cid:14)(cid:4)(cid:31)(cid:18)0(cid:14)(((cid:14)(cid:10)(cid:13)(cid:23)(cid:14)"(cid:21)$(cid:13)(cid:31) (cid:5)(cid:31) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:21)(cid:27)(cid:12)(cid:14)(cid:11)(cid:27)$(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:21)(cid:27)(cid:12)(cid:14)(cid:10)(cid:13)(cid:23)(cid:14)(cid:7)(cid:3)(cid:20)/(cid:14)1(cid:15)(cid:5)(cid:31)0(cid:20)(cid:31) 2(cid:3),3 2(cid:11)"(cid:21)(cid:22)(cid:14)(cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:31)(cid:14)(cid:26)(cid:25)(cid:13)(cid:24)(cid:23)(cid:13)’(cid:21)(cid:22)(cid:11)(cid:28)(cid:28)(cid:29)(cid:14)(cid:13)%(cid:11)(cid:22)’(cid:14)!(cid:11)(cid:28)#(cid:13)(cid:14)"(cid:25)(cid:24)+(cid:27)(cid:14)+(cid:21)’(cid:25)(cid:24)#’(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:13)"(cid:31) (cid:8)/43 (cid:8)(cid:13)&(cid:13)(cid:23)(cid:13)(cid:27)(cid:22)(cid:13)(cid:14)(cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27))(cid:14)#"#(cid:11)(cid:28)(cid:28)(cid:29)(cid:14)+(cid:21)’(cid:25)(cid:24)#’(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:13))(cid:14)&(cid:24)(cid:23)(cid:14)(cid:21)(cid:27)&(cid:24)(cid:23)((cid:11)’(cid:21)(cid:24)(cid:27)(cid:14)(cid:10)#(cid:23)(cid:10)(cid:24)"(cid:13)"(cid:14)(cid:24)(cid:27)(cid:28)(cid:29)(cid:31) (cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:26)(cid:13)(cid:22)(cid:25)(cid:27)(cid:24)(cid:28)(cid:24)(cid:12)(cid:29)(cid:2)(cid:23)(cid:11)+(cid:21)(cid:27)(cid:12),(cid:4)(cid:5)(cid:9)(cid:4)(cid:6)(cid:18)2  2010-2014 Microchip Technology Inc. DS30009996G-page 397

PIC24FJ128GA310 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30009996G-page 398  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY (cid:27)(cid:3)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)(cid:28)(cid:29)(cid:27)(cid:28)(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)(cid:28)#(cid:3)(cid:3)(cid:9)(cid:30)(cid:30)(cid:9)$(cid:16)(cid:19)(cid:21)(cid:10)% & (cid:13)(cid:6)’ 4(cid:24)(cid:23)(cid:14)’(cid:25)(cid:13)(cid:14)((cid:24)"’(cid:14)(cid:22)#(cid:23)(cid:23)(cid:13)(cid:27)’(cid:14)(cid:10)(cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)$(cid:23)(cid:11)+(cid:21)(cid:27)(cid:12)")(cid:14)(cid:10)(cid:28)(cid:13)(cid:11)"(cid:13)(cid:14)"(cid:13)(cid:13)(cid:14)’(cid:25)(cid:13)(cid:14)(cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:21)(cid:27)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:22)(cid:21)&(cid:21)(cid:22)(cid:11)’(cid:21)(cid:24)(cid:27)(cid:14)(cid:28)(cid:24)(cid:22)(cid:11)’(cid:13)$(cid:14)(cid:11)’(cid:14) (cid:25)’’(cid:10)366+++(cid:31)((cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:31)(cid:22)(cid:24)(6(cid:10)(cid:11)(cid:22)5(cid:11)(cid:12)(cid:21)(cid:27)(cid:12) D D1 e E E1 N b NOTE1 123 NOTE2 α c A φ β L A1 L1 A2 7(cid:27)(cid:21)’" (cid:20)(cid:30)88(cid:30)(cid:20)/(cid:26)/(cid:8)(cid:3) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:14)8(cid:21)((cid:21)’" (cid:20)(cid:30)9 9:(cid:20) (cid:20)(cid:7); 9#(*(cid:13)(cid:23)(cid:14)(cid:24)&(cid:14)8(cid:13)(cid:11)$" 9 (cid:15)(cid:4)(cid:4) 8(cid:13)(cid:11)$(cid:14) (cid:21)’(cid:22)(cid:25) (cid:13) (cid:4)(cid:31)(cid:5)(cid:4)(cid:14)2(cid:3), :!(cid:13)(cid:23)(cid:11)(cid:28)(cid:28)(cid:14)<(cid:13)(cid:21)(cid:12)(cid:25)’ (cid:7) = = (cid:15)(cid:31)(cid:18)(cid:4) (cid:20)(cid:24)(cid:28)$(cid:13)$(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)(cid:26)(cid:25)(cid:21)(cid:22)5(cid:27)(cid:13)"" (cid:7)(cid:18) (cid:4)(cid:31)(cid:6)0 (cid:15)(cid:31)(cid:4)(cid:4) (cid:15)(cid:31)(cid:4)0 (cid:3)’(cid:11)(cid:27)$(cid:24)&&(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:31)(cid:4)0 = (cid:4)(cid:31)(cid:15)0 4(cid:24)(cid:24)’(cid:14)8(cid:13)(cid:27)(cid:12)’(cid:25) 8 (cid:4)(cid:31)(cid:5)0 (cid:4)(cid:31)>(cid:4) (cid:4)(cid:31)(cid:19)0 4(cid:24)(cid:24)’(cid:10)(cid:23)(cid:21)(cid:27)’ 8(cid:15) (cid:15)(cid:31)(cid:4)(cid:4)(cid:14)(cid:8)/4 4(cid:24)(cid:24)’(cid:14)(cid:7)(cid:27)(cid:12)(cid:28)(cid:13) (cid:3) (cid:4)? (cid:16)(cid:31)0? (cid:19)? :!(cid:13)(cid:23)(cid:11)(cid:28)(cid:28)(cid:14)@(cid:21)$’(cid:25) / (cid:15)(cid:5)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), :!(cid:13)(cid:23)(cid:11)(cid:28)(cid:28)(cid:14)8(cid:13)(cid:27)(cid:12)’(cid:25) (cid:2) (cid:15)(cid:5)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), (cid:20)(cid:24)(cid:28)$(cid:13)$(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)@(cid:21)$’(cid:25) /(cid:15) (cid:15)(cid:18)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), (cid:20)(cid:24)(cid:28)$(cid:13)$(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)8(cid:13)(cid:27)(cid:12)’(cid:25) (cid:2)(cid:15) (cid:15)(cid:18)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), 8(cid:13)(cid:11)$(cid:14)(cid:26)(cid:25)(cid:21)(cid:22)5(cid:27)(cid:13)"" (cid:22) (cid:4)(cid:31)(cid:4)(cid:6) = (cid:4)(cid:31)(cid:18)(cid:4) 8(cid:13)(cid:11)$(cid:14)@(cid:21)$’(cid:25) * (cid:4)(cid:31)(cid:15)(cid:16) (cid:4)(cid:31)(cid:15)(cid:17) (cid:4)(cid:31)(cid:18)(cid:16) (cid:20)(cid:24)(cid:28)$(cid:14)(cid:2)(cid:23)(cid:11)&’(cid:14)(cid:7)(cid:27)(cid:12)(cid:28)(cid:13)(cid:14)(cid:26)(cid:24)(cid:10) (cid:4) (cid:15)(cid:15)? (cid:15)(cid:18)? (cid:15)(cid:16)? (cid:20)(cid:24)(cid:28)$(cid:14)(cid:2)(cid:23)(cid:11)&’(cid:14)(cid:7)(cid:27)(cid:12)(cid:28)(cid:13)(cid:14)2(cid:24)’’(cid:24)( (cid:5) (cid:15)(cid:15)? (cid:15)(cid:18)? (cid:15)(cid:16)? & (cid:13)(cid:6)(cid:12)’ (cid:15)(cid:31) (cid:21)(cid:27)(cid:14)(cid:15)(cid:14)!(cid:21)"#(cid:11)(cid:28)(cid:14)(cid:21)(cid:27)$(cid:13)%(cid:14)&(cid:13)(cid:11)’#(cid:23)(cid:13)(cid:14)((cid:11)(cid:29)(cid:14)!(cid:11)(cid:23)(cid:29))(cid:14)*#’(cid:14)(#"’(cid:14)*(cid:13)(cid:14)(cid:28)(cid:24)(cid:22)(cid:11)’(cid:13)$(cid:14)+(cid:21)’(cid:25)(cid:21)(cid:27)(cid:14)’(cid:25)(cid:13)(cid:14)(cid:25)(cid:11)’(cid:22)(cid:25)(cid:13)$(cid:14)(cid:11)(cid:23)(cid:13)(cid:11)(cid:31) (cid:18)(cid:31) ,(cid:25)(cid:11)(&(cid:13)(cid:23)"(cid:14)(cid:11)’(cid:14)(cid:22)(cid:24)(cid:23)(cid:27)(cid:13)(cid:23)"(cid:14)(cid:11)(cid:23)(cid:13)(cid:14)(cid:24)(cid:10)’(cid:21)(cid:24)(cid:27)(cid:11)(cid:28)-(cid:14)"(cid:21).(cid:13)(cid:14)((cid:11)(cid:29)(cid:14)!(cid:11)(cid:23)(cid:29)(cid:31) (cid:16)(cid:31) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)"(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:27)$(cid:14)/(cid:15)(cid:14)$(cid:24)(cid:14)(cid:27)(cid:24)’(cid:14)(cid:21)(cid:27)(cid:22)(cid:28)#$(cid:13)(cid:14)((cid:24)(cid:28)$(cid:14)&(cid:28)(cid:11)"(cid:25)(cid:14)(cid:24)(cid:23)(cid:14)(cid:10)(cid:23)(cid:24)’(cid:23)#"(cid:21)(cid:24)(cid:27)"(cid:31)(cid:14)(cid:20)(cid:24)(cid:28)$(cid:14)&(cid:28)(cid:11)"(cid:25)(cid:14)(cid:24)(cid:23)(cid:14)(cid:10)(cid:23)(cid:24)’(cid:23)#"(cid:21)(cid:24)(cid:27)"(cid:14)"(cid:25)(cid:11)(cid:28)(cid:28)(cid:14)(cid:27)(cid:24)’(cid:14)(cid:13)%(cid:22)(cid:13)(cid:13)$(cid:14)(cid:4)(cid:31)(cid:18)0(cid:14)(((cid:14)(cid:10)(cid:13)(cid:23)(cid:14)"(cid:21)$(cid:13)(cid:31) (cid:5)(cid:31) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:21)(cid:27)(cid:12)(cid:14)(cid:11)(cid:27)$(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:21)(cid:27)(cid:12)(cid:14)(cid:10)(cid:13)(cid:23)(cid:14)(cid:7)(cid:3)(cid:20)/(cid:14)1(cid:15)(cid:5)(cid:31)0(cid:20)(cid:31) 2(cid:3),3 2(cid:11)"(cid:21)(cid:22)(cid:14)(cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:31)(cid:14)(cid:26)(cid:25)(cid:13)(cid:24)(cid:23)(cid:13)’(cid:21)(cid:22)(cid:11)(cid:28)(cid:28)(cid:29)(cid:14)(cid:13)%(cid:11)(cid:22)’(cid:14)!(cid:11)(cid:28)#(cid:13)(cid:14)"(cid:25)(cid:24)+(cid:27)(cid:14)+(cid:21)’(cid:25)(cid:24)#’(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:13)"(cid:31) (cid:8)/43 (cid:8)(cid:13)&(cid:13)(cid:23)(cid:13)(cid:27)(cid:22)(cid:13)(cid:14)(cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27))(cid:14)#"#(cid:11)(cid:28)(cid:28)(cid:29)(cid:14)+(cid:21)’(cid:25)(cid:24)#’(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:13))(cid:14)&(cid:24)(cid:23)(cid:14)(cid:21)(cid:27)&(cid:24)(cid:23)((cid:11)’(cid:21)(cid:24)(cid:27)(cid:14)(cid:10)#(cid:23)(cid:10)(cid:24)"(cid:13)"(cid:14)(cid:24)(cid:27)(cid:28)(cid:29)(cid:31) (cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:26)(cid:13)(cid:22)(cid:25)(cid:27)(cid:24)(cid:28)(cid:24)(cid:12)(cid:29)(cid:2)(cid:23)(cid:11)+(cid:21)(cid:27)(cid:12),(cid:4)(cid:5)(cid:9)(cid:15)(cid:4)(cid:4)2  2010-2014 Microchip Technology Inc. DS30009996G-page 399

PIC24FJ128GA310 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30009996G-page 400  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY (cid:27)(cid:3)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:21)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)((cid:29)(cid:27)((cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)(cid:28)#(cid:3)(cid:3)(cid:9)(cid:30)(cid:30)(cid:9)$(cid:16)(cid:19)(cid:21)(cid:10)% & (cid:13)(cid:6)’ 4(cid:24)(cid:23)(cid:14)’(cid:25)(cid:13)(cid:14)((cid:24)"’(cid:14)(cid:22)#(cid:23)(cid:23)(cid:13)(cid:27)’(cid:14)(cid:10)(cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)$(cid:23)(cid:11)+(cid:21)(cid:27)(cid:12)")(cid:14)(cid:10)(cid:28)(cid:13)(cid:11)"(cid:13)(cid:14)"(cid:13)(cid:13)(cid:14)’(cid:25)(cid:13)(cid:14)(cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:21)(cid:27)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:22)(cid:21)&(cid:21)(cid:22)(cid:11)’(cid:21)(cid:24)(cid:27)(cid:14)(cid:28)(cid:24)(cid:22)(cid:11)’(cid:13)$(cid:14)(cid:11)’(cid:14) (cid:25)’’(cid:10)366+++(cid:31)((cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:31)(cid:22)(cid:24)(6(cid:10)(cid:11)(cid:22)5(cid:11)(cid:12)(cid:21)(cid:27)(cid:12) D D1 e E1 E b N α NOTE1 123 NOTE2 A φ c A2 β A1 L L1 7(cid:27)(cid:21)’" (cid:20)(cid:30)88(cid:30)(cid:20)/(cid:26)/(cid:8)(cid:3) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:14)8(cid:21)((cid:21)’" (cid:20)(cid:30)9 9:(cid:20) (cid:20)(cid:7); 9#(*(cid:13)(cid:23)(cid:14)(cid:24)&(cid:14)8(cid:13)(cid:11)$" 9 (cid:15)(cid:4)(cid:4) 8(cid:13)(cid:11)$(cid:14) (cid:21)’(cid:22)(cid:25) (cid:13) (cid:4)(cid:31)0(cid:4)(cid:14)2(cid:3), :!(cid:13)(cid:23)(cid:11)(cid:28)(cid:28)(cid:14)<(cid:13)(cid:21)(cid:12)(cid:25)’ (cid:7) = = (cid:15)(cid:31)(cid:18)(cid:4) (cid:20)(cid:24)(cid:28)$(cid:13)$(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)(cid:26)(cid:25)(cid:21)(cid:22)5(cid:27)(cid:13)"" (cid:7)(cid:18) (cid:4)(cid:31)(cid:6)0 (cid:15)(cid:31)(cid:4)(cid:4) (cid:15)(cid:31)(cid:4)0 (cid:3)’(cid:11)(cid:27)$(cid:24)&&(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:31)(cid:4)0 = (cid:4)(cid:31)(cid:15)0 4(cid:24)(cid:24)’(cid:14)8(cid:13)(cid:27)(cid:12)’(cid:25) 8 (cid:4)(cid:31)(cid:5)0 (cid:4)(cid:31)>(cid:4) (cid:4)(cid:31)(cid:19)0 4(cid:24)(cid:24)’(cid:10)(cid:23)(cid:21)(cid:27)’ 8(cid:15) (cid:15)(cid:31)(cid:4)(cid:4)(cid:14)(cid:8)/4 4(cid:24)(cid:24)’(cid:14)(cid:7)(cid:27)(cid:12)(cid:28)(cid:13) (cid:3) (cid:4)? (cid:16)(cid:31)0? (cid:19)? :!(cid:13)(cid:23)(cid:11)(cid:28)(cid:28)(cid:14)@(cid:21)$’(cid:25) / (cid:15)>(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), :!(cid:13)(cid:23)(cid:11)(cid:28)(cid:28)(cid:14)8(cid:13)(cid:27)(cid:12)’(cid:25) (cid:2) (cid:15)>(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), (cid:20)(cid:24)(cid:28)$(cid:13)$(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)@(cid:21)$’(cid:25) /(cid:15) (cid:15)(cid:5)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), (cid:20)(cid:24)(cid:28)$(cid:13)$(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)8(cid:13)(cid:27)(cid:12)’(cid:25) (cid:2)(cid:15) (cid:15)(cid:5)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), 8(cid:13)(cid:11)$(cid:14)(cid:26)(cid:25)(cid:21)(cid:22)5(cid:27)(cid:13)"" (cid:22) (cid:4)(cid:31)(cid:4)(cid:6) = (cid:4)(cid:31)(cid:18)(cid:4) 8(cid:13)(cid:11)$(cid:14)@(cid:21)$’(cid:25) * (cid:4)(cid:31)(cid:15)(cid:19) (cid:4)(cid:31)(cid:18)(cid:18) (cid:4)(cid:31)(cid:18)(cid:19) (cid:20)(cid:24)(cid:28)$(cid:14)(cid:2)(cid:23)(cid:11)&’(cid:14)(cid:7)(cid:27)(cid:12)(cid:28)(cid:13)(cid:14)(cid:26)(cid:24)(cid:10) (cid:4) (cid:15)(cid:15)? (cid:15)(cid:18)? (cid:15)(cid:16)? (cid:20)(cid:24)(cid:28)$(cid:14)(cid:2)(cid:23)(cid:11)&’(cid:14)(cid:7)(cid:27)(cid:12)(cid:28)(cid:13)(cid:14)2(cid:24)’’(cid:24)( (cid:5) (cid:15)(cid:15)? (cid:15)(cid:18)? (cid:15)(cid:16)? & (cid:13)(cid:6)(cid:12)’ (cid:15)(cid:31) (cid:21)(cid:27)(cid:14)(cid:15)(cid:14)!(cid:21)"#(cid:11)(cid:28)(cid:14)(cid:21)(cid:27)$(cid:13)%(cid:14)&(cid:13)(cid:11)’#(cid:23)(cid:13)(cid:14)((cid:11)(cid:29)(cid:14)!(cid:11)(cid:23)(cid:29))(cid:14)*#’(cid:14)(#"’(cid:14)*(cid:13)(cid:14)(cid:28)(cid:24)(cid:22)(cid:11)’(cid:13)$(cid:14)+(cid:21)’(cid:25)(cid:21)(cid:27)(cid:14)’(cid:25)(cid:13)(cid:14)(cid:25)(cid:11)’(cid:22)(cid:25)(cid:13)$(cid:14)(cid:11)(cid:23)(cid:13)(cid:11)(cid:31) (cid:18)(cid:31) ,(cid:25)(cid:11)(&(cid:13)(cid:23)"(cid:14)(cid:11)’(cid:14)(cid:22)(cid:24)(cid:23)(cid:27)(cid:13)(cid:23)"(cid:14)(cid:11)(cid:23)(cid:13)(cid:14)(cid:24)(cid:10)’(cid:21)(cid:24)(cid:27)(cid:11)(cid:28)-(cid:14)"(cid:21).(cid:13)(cid:14)((cid:11)(cid:29)(cid:14)!(cid:11)(cid:23)(cid:29)(cid:31) (cid:16)(cid:31) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)"(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:27)$(cid:14)/(cid:15)(cid:14)$(cid:24)(cid:14)(cid:27)(cid:24)’(cid:14)(cid:21)(cid:27)(cid:22)(cid:28)#$(cid:13)(cid:14)((cid:24)(cid:28)$(cid:14)&(cid:28)(cid:11)"(cid:25)(cid:14)(cid:24)(cid:23)(cid:14)(cid:10)(cid:23)(cid:24)’(cid:23)#"(cid:21)(cid:24)(cid:27)"(cid:31)(cid:14)(cid:20)(cid:24)(cid:28)$(cid:14)&(cid:28)(cid:11)"(cid:25)(cid:14)(cid:24)(cid:23)(cid:14)(cid:10)(cid:23)(cid:24)’(cid:23)#"(cid:21)(cid:24)(cid:27)"(cid:14)"(cid:25)(cid:11)(cid:28)(cid:28)(cid:14)(cid:27)(cid:24)’(cid:14)(cid:13)%(cid:22)(cid:13)(cid:13)$(cid:14)(cid:4)(cid:31)(cid:18)0(cid:14)(((cid:14)(cid:10)(cid:13)(cid:23)(cid:14)"(cid:21)$(cid:13)(cid:31) (cid:5)(cid:31) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:21)(cid:27)(cid:12)(cid:14)(cid:11)(cid:27)$(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:21)(cid:27)(cid:12)(cid:14)(cid:10)(cid:13)(cid:23)(cid:14)(cid:7)(cid:3)(cid:20)/(cid:14)1(cid:15)(cid:5)(cid:31)0(cid:20)(cid:31) 2(cid:3),3 2(cid:11)"(cid:21)(cid:22)(cid:14)(cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:31)(cid:14)(cid:26)(cid:25)(cid:13)(cid:24)(cid:23)(cid:13)’(cid:21)(cid:22)(cid:11)(cid:28)(cid:28)(cid:29)(cid:14)(cid:13)%(cid:11)(cid:22)’(cid:14)!(cid:11)(cid:28)#(cid:13)(cid:14)"(cid:25)(cid:24)+(cid:27)(cid:14)+(cid:21)’(cid:25)(cid:24)#’(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:13)"(cid:31) (cid:8)/43 (cid:8)(cid:13)&(cid:13)(cid:23)(cid:13)(cid:27)(cid:22)(cid:13)(cid:14)(cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27))(cid:14)#"#(cid:11)(cid:28)(cid:28)(cid:29)(cid:14)+(cid:21)’(cid:25)(cid:24)#’(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:13))(cid:14)&(cid:24)(cid:23)(cid:14)(cid:21)(cid:27)&(cid:24)(cid:23)((cid:11)’(cid:21)(cid:24)(cid:27)(cid:14)(cid:10)#(cid:23)(cid:10)(cid:24)"(cid:13)"(cid:14)(cid:24)(cid:27)(cid:28)(cid:29)(cid:31) (cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:26)(cid:13)(cid:22)(cid:25)(cid:27)(cid:24)(cid:28)(cid:24)(cid:12)(cid:29)(cid:2)(cid:23)(cid:11)+(cid:21)(cid:27)(cid:12),(cid:4)(cid:5)(cid:9)(cid:15)(cid:15)(cid:4)2  2010-2014 Microchip Technology Inc. DS30009996G-page 401

PIC24FJ128GA310 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30009996G-page 402  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY  2010-2014 Microchip Technology Inc. DS30009996G-page 403

PIC24FJ128GA310 FAMILY DS30009996G-page 404  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY  2010-2014 Microchip Technology Inc. DS30009996G-page 405

PIC24FJ128GA310 FAMILY NOTES: DS30009996G-page 406  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY APPENDIX A: REVISION HISTORY Revision A (March 2010) Original data sheet for the PIC24FJ128GA310 family of devices. Revision B (May 2011) Changes in Reset values for TRISA in Table4-12. Edits to the “Special Microcontroller Features:” Revision C (July 2011) Updated the values in Section32.0 “Electrical Characteristics”. Special Function Register addresses have been changed. The OCTRIG1 and OCTRIG2 pins have been removed. Minor text edits throughout the document. Revision D (August 2011) Updated VBAT specification; updated maximum values for Section32.0 “Electrical Characteristics”. Revision E (October 2011) • Removed the RTCBAT bit from the CW4<9> register. • Added the IDD/IPD numbers in the Section32.0 “Electrical Characteristics”. • Added details on the VBAT pin capacitor. • Added Section24.3 “ADC Operation with Vbat”. Revision F (November 2011) Updated the values in Section32.0 “Electrical Characteristics”. Minor text edits throughout the document. Revision G (March 2014) • Updated Table1-4 (CTED1 through CTED13 are digital, not analog). Removed references to Timer1 clock. • Removed the Low-Power SOSC Operation section from Section9.0 “Oscillator Configura- tion”. • Added note to Section9.5.3 “SOSC Layout Considerations”. • Added BOREN1 bit to Register29-2. • Updated description of ALTVRF<1:0> in Register29-2. • Minor text edits throughout the document.  2010-2014 Microchip Technology Inc. DS30009996G-page 407

PIC24FJ128GA310 FAMILY NOTES: DS30009996G-page 408  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY INDEX A Output Compare x (Double-Buffered, 16-Bit PWM Mode)...........................................214 AC Characteristics PCI24FJ256GA310 Family (General).........................16 ADC Conversion Timing...........................................387 PIC24F CPU Core......................................................36 ADC Module..............................................................386 PSV Operation (Lower Word).....................................73 CLKO and I/O Timing................................................372 PSV Operation (Upper Word).....................................73 External Clock Timing...............................................370 Reset System.............................................................89 Internal RC Accuracy................................................371 RTCC........................................................................276 Load Conditions and Requirements Shared I/O Port Structure.........................................167 for Specifications..............................................369 SPIx Master, Frame Master Connection..................230 PLL Clock Timing Specifications...............................371 SPIx Master, Frame Slave Connection....................230 RC Oscillator Start-up Time......................................371 SPIx Master/Slave Connection Reset and Brown-out Reset Requirements..............373 (Enhanced Buffer Modes).................................229 UARTx Specifications...............................................385 SPIx Master/Slave Connection ADC (Standard Mode)...............................................229 Control Registers......................................................298 SPIx Module (Enhanced Mode)................................223 Extended DMA Operations.......................................297 SPIx Module (Standard Mode).................................222 Operation..................................................................295 SPIx Slave, Frame Master Connection....................230 Alternate Interrupt Vector Table (AIVT)..............................95 SPIx Slave, Frame Slave Connection......................230 Assembler System Clock............................................................145 MPASM Assembler...................................................348 Triple Comparator Module........................................315 B UARTx (Simplified)...................................................241 Block Diagrams Watchdog Timer (WDT)............................................344 10-Bit A/D Converter Analog Input Model.................311 C 12-Bit ADC1 Module.................................................296 C Compilers 16-Bit Synchronous Timer2 and Timer4...................201 MPLAB C18..............................................................348 16-Bit Synchronous Timer3 and Timer5...................201 Charge Time Measurement Unit. See CTMU. 16-Bit Timer1 Module................................................197 Code Examples 32-Bit Timer2/3 and Timer4/5...................................200 Basic Sequence for Clock Switching........................151 Accessing Program Memory Using Configuring UART1 Input/Output Table Instructions...............................................71 Functions (PPS)...............................................177 Addressing for Table Registers...................................83 EDS Read From Program Memory in Assembly........72 Buffer Address Generation in PIA Mode...................299 EDS Read in Assembly..............................................66 CALL Stack Frame......................................................68 EDS Write in Assembly..............................................67 Comparator Voltage Reference................................321 Erasing a Program Memory Block (Assembly)...........86 CPU Programmer’s Model..........................................37 Erasing a Program Memory Block (C Language).......87 CRC Module.............................................................289 Initiating a Programming Sequence...........................87 CRC Shift Engine Detail............................................289 Loading the Write Buffers...........................................87 CTMU Connections and Internal Configuration Port Read/Write in Assembly....................................172 for Capacitance Measurement..........................324 Port Read/Write in C.................................................172 CTMU Typical Connections and Internal PWRSAV Instruction Syntax....................................156 Configuration for Pulse Delay Generation........325 Setting the RTCWREN Bit........................................277 CTMU Typical Connections and Internal Single-Word Flash Programming...............................88 Configuration for Time Measurement...............325 Single-Word Flash Programming (C Language)........88 Data Access from Program Space Code Protection................................................................345 Address Generation............................................70 Code Segment Protection........................................345 Data Signal Modulator..............................................249 Configuration Options.......................................345 Direct Memory Access (DMA).....................................75 Configuration Register Protection.............................346 EDS Address Generation for Read Operations..........66 General Segment Protection....................................345 EDS Address Generation for Write Operations..........67 Comparator Voltage Reference........................................321 Extended Data Space.................................................65 Configuring...............................................................321 High/Low-Voltage Detect (HLVD).............................331 I2C Module................................................................234 Configuration Bits.............................................................333 Core Features.....................................................................11 Individual Comparator Configurations, CPU CREF = 0..........................................................316 Arithmetic Logic Unit (ALU)........................................40 Individual Comparator Configurations, Control Registers........................................................38 CREF = 1 and CVREFP = 0.............................317 Core Registers............................................................36 Individual Comparator Configurations, Programmer’s Model..................................................35 CREF = 1 and CVREFP = 1.............................317 CRC Input Capture x.........................................................205 Data Interface...........................................................290 LCD Controller..........................................................265 Polynomials..............................................................290 On-Chip Regulator Connections...............................343 Setup Examples for 16 and 32-Bit Polynomials.......290 Output Compare x (16-Bit Mode)..............................212 User Interface...........................................................290  2010-2014 Microchip Technology Inc. DS30009996G-page 409

PIC24FJ128GA310 FAMILY CTMU Equations Measuring Capacitance............................................323 16-Bit, 32-Bit CRC Polynomials................................290 Measuring Time........................................................324 ADC Conversion Clock Period..................................311 Pulse Delay and Generation.....................................324 Baud Rate Reload Calculation..................................235 Customer Change Notification Service.............................414 Calculating the PWM Period.....................................214 Customer Notification Service...........................................414 Calculation for Maximum PWM Resolution..............215 Customer Support.............................................................414 Relationship Between Device and SPI Clock Speed..............................................231 D UARTx Baud Rate with BRGH = 0...........................242 Data Memory UARTx Baud Rate with BRGH = 1...........................242 Address Space............................................................43 Errata..................................................................................10 Extended Data Space (EDS)......................................65 Extended Data Space (EDS)............................................253 Memory Map...............................................................43 F Near Data Space........................................................44 SFR Space..................................................................44 Flash Configuration Word Locations.................................333 Software Stack............................................................68 Flash Configuration Words.................................................42 Space Organization, Alignment..................................44 Flash Program Memory......................................................83 Data Signal Modulator.......................................................249 and Table Instructions................................................83 Data Signal Modulator (DSM)...........................................249 Enhanced ICSP Operation.........................................84 DC Characteristics JTAG Operation..........................................................84 Comparator...............................................................368 Programming Algorithm..............................................86 Comparator Voltage Reference................................368 Programming Operations............................................84 CTMU Current Source..............................................367 RTSP Operation.........................................................84 Delta Current (BOR, WDT, DSBOR, Single-Word Programming.........................................88 DSWDT, LCD)..................................................364 G I/O Pin Input Specifications.......................................365 I/O Pin Output Specifications....................................366 Getting Started with 16-Bit MCUs.......................................29 Idle Current (IIDLE)....................................................362 H Operating Current (IDD).............................................361 Power-Down Current (IPD)........................................363 High/Low-Voltage Detect (HLVD).....................................331 Program Memory......................................................366 I Temperature and Voltage Specifications..................361 Development Support.......................................................347 I/O Ports Device Features Analog Port Pins Configuration (ANSx)....................168 100-Pin........................................................................15 Analog/Digital Function of an I/O Pin........................168 64-Pin..........................................................................13 Input Change Notification.........................................172 Input Voltage Levels for Port or Pin 80-Pin..........................................................................14 Direct Memory Access Controller. See DMA. Tolerated Description Input..............................168 Open-Drain Configuration.........................................168 DMA....................................................................................75 Channel Trigger Sources............................................82 Parallel (PIO)............................................................167 Peripheral Module Disable (PMD) Registers..............78 Peripheral Pin Select................................................173 Summary of Operations..............................................76 Pull-ups and Pull-Downs...........................................172 Types of Transfers......................................................77 Selectable Input Sources..........................................174 Typical Setup..............................................................78 Selectable Output Sources.......................................175 DMA Controller....................................................................12 I2C Clock Rates..............................................................235 E Communicating as Master in Single Electrical Characteristics Master Environment.........................................233 Absolute Maximum Ratings......................................359 Reserved Addresses................................................235 Capacitive Loading on Output Pins...........................369 Setting Baud Rate as Bus Master.............................235 High/Low-Voltage Detect..........................................368 Slave Address Masking............................................235 Internal Voltage Regulator Specifications.................367 Input Capture Thermal Operating Conditions..................................360 32-Bit Cascaded Mode.............................................206 Thermal Packaging...................................................360 Operations................................................................206 V/F Graph.................................................................360 Synchronous and Trigger Modes..............................205 Vbat Operating Voltage Specifications.....................367 Input Capture with Dedicated Timers...............................205 Enhanced Parallel Master Port (EPMP)............................253 Instruction Set Enhanced Parallel Master Port. See EPMP......................253 Overview...................................................................353 EPMP Summary..................................................................351 Key Features.............................................................253 Symbols Used in Opcode Descriptions....................352 Package Variations...................................................253 Interfacing Program and Data Spaces................................69 Inter-Integrated Circuit. See I2C.......................................233 DS30009996G-page 410  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY Internet Address................................................................414 Pin Descriptions Interrupt Vector Table (IVT)................................................95 121-Pin Devices (BGA)................................................7 Interrupts Pinout Descriptions.............................................................17 Control and Status Registers......................................98 Power-Saving Features....................................................155 Implemented Vectors..................................................97 Clock Frequency and Clock Switching.....................165 Reset Sequence.........................................................95 Doze Mode...............................................................165 Setup and Service Procedures.................................143 Instruction-Based Modes..........................................156 Trap Vectors...............................................................96 Deep Sleep.......................................................158 Vector Table................................................................96 Idle....................................................................157 Sleep................................................................157 J Low-Voltage JTAG Interface..................................................................346 Retention Regulator..........................................157 Vbat Mode................................................................160 K Product Identification System...........................................416 Key Features.....................................................................333 Program Memory L Access Using Table Instructions................................71 Address Construction.................................................69 LCD Controller....................................................................12 Address Space...........................................................41 Liquid Crystal Display (LCD) Controller............................265 Flash Configuration Words.........................................42 M Hard Memory Vectors.................................................42 Memory Maps.............................................................41 Memory Organization..........................................................41 Organization...............................................................42 Microchip Internet Web Site..............................................414 Reading from Program Memory Using EDS...............72 Modulator. See Data Signal Modulator.............................249 Program Verification.........................................................345 MPLAB ASM30 Assembler, Linker, Librarian...................348 Pulse-Width Modulation (PWM) Mode..............................213 MPLAB Integrated Development Pulse-Width Modulation. See PWM. Environment Software...............................................347 PWM MPLAB PM3 Device Programmer....................................349 Duty Cycle and Period..............................................214 MPLAB REAL ICE In-Circuit Emulator System.................349 MPLINK Object Linker/MPLIB Object Librarian................348 R N Real-Time Clock and Calendar (RTCC)...........................275 Register Maps Near Data Space................................................................44 ADC............................................................................56 O Analog Configuration..................................................57 Comparators...............................................................61 On-Chip Voltage Regulator...............................................343 CPU Core...................................................................45 POR..........................................................................343 CRC............................................................................62 Standby Mode...........................................................343 CTMU.........................................................................57 Oscillator Configuration Data Signal Modulator (DSM).....................................61 Bit Values for Clock Selection...................................146 Deep Sleep.................................................................64 Clock Switching.........................................................150 DMA............................................................................58 Sequence..........................................................151 I2C..............................................................................51 Control Registers......................................................147 ICN.............................................................................46 CPU Clocking Scheme.............................................146 Input Capture..............................................................49 Initial Configuration on POR.....................................146 Interrupt Controller......................................................47 Reference Clock Output............................................152 LCD Controller............................................................59 Secondary Oscillator (SOSC)...................................152 NVM............................................................................64 Output Compare Output Compare.........................................................50 32-Bit Cascaded Mode.............................................211 Pad Configuration.......................................................55 Synchronous and Trigger Modes..............................211 Parallel Master/Slave Port..........................................60 Output Compare with Dedicated Timers...........................211 Peripheral Pin Select..................................................62 P PMD............................................................................64 PORTA.......................................................................53 Packaging.........................................................................389 PORTB.......................................................................53 Details.......................................................................391 PORTC.......................................................................54 Marking.....................................................................389 PORTD.......................................................................54 Peripheral Pin Select (PPS)..............................................173 PORTE.......................................................................54 Available Peripherals and Pins.................................173 PORTF.......................................................................55 Configuration Control................................................176 PORTG.......................................................................55 Considerations for Use.............................................177 RTCC..........................................................................61 Input Mapping...........................................................174 SPI..............................................................................53 Mapping Exceptions..................................................176 System Control...........................................................63 Output Mapping........................................................175 Timers.........................................................................48 Peripheral Priority.....................................................173 UART..........................................................................52 Registers...................................................................178  2010-2014 Microchip Technology Inc. DS30009996G-page 411

PIC24FJ128GA310 FAMILY Registers IEC3 (Interrupt Enable Control 3).............................117 AD1CHITH (ADC1 Scan Compare Hit, IEC4 (Interrupt Enable Control 4).............................118 High Word)........................................................308 IEC5 (Interrupt Enable Control 5).............................119 AD1CHITL (ADC1 Scan Compare Hit, IEC6 (Interrupt Enable Control 6).............................120 Low Word).........................................................308 IEC7 (Interrupt Enable Control 7).............................120 AD1CHS (ADC1 Sample Select)..............................306 IFS0 (Interrupt Flag Status 0)...................................103 AD1CON1 (ADC1 Control 1)....................................300 IFS1 (Interrupt Flag Status 1)...................................105 AD1CON2 (ADC1 Control 2)....................................302 IFS2 (Interrupt Flag Status 2)...................................107 AD1CON3 (ADC1 Control 3)....................................303 IFS3 (Interrupt Flag Status 3)...................................108 AD1CON4 (ADC1 Control 4)....................................304 IFS4 (Interrupt Flag Status 4)...................................109 AD1CON5 (ADC1 Control 5)....................................305 IFS5 (Interrupt Flag Status 5)...................................110 AD1CSSH (ADC1 Input Scan Select, IFS6 (Interrupt Flag Status 6)...................................111 High Word)........................................................309 IFS7 (Interrupt Flag Status 7)...................................111 AD1CSSL (ADC1 Input Scan Select, INTCON1 (Interrupt Control 1)..................................101 Low Word).........................................................309 INTCON2 (Interrupt Control 2)..................................102 AD1CTMENH (ADC1 CTMU Enable, INTTREG (Interrupt Controller Test).........................142 High Word)........................................................310 IPC0 (Interrupt Priority Control 0).............................121 AD1CTMENL (ADC1 CTMU Enable, IPC1 (Interrupt Priority Control 1).............................122 Low Word).........................................................310 IPC10 (Interrupt Priority Control 10).........................131 ALCFGRPT (Alarm Configuration)............................281 IPC11 (Interrupt Priority Control 11).........................132 ALMINSEC (Alarm Minutes and IPC12 (Interrupt Priority Control 12).........................133 Seconds Value).................................................285 IPC13 (Interrupt Priority Control 13).........................134 ALMTHDY (Alarm Month and Day Value)................284 IPC15 (Interrupt Priority Control 15).........................135 ALWDHR (Alarm Weekday and Hours Value)..........284 IPC16 (Interrupt Priority Control 16).........................136 ANCFG (ADC Band Gap Reference)........................307 IPC18 (Interrupt Priority Control 18).........................137 ANSA (PORTA Analog Function Selection)..............169 IPC19 (Interrupt Priority Control 19).........................137 ANSB (PORTB Analog Function Selection)..............169 IPC2 (Interrupt Priority Control 2).............................123 ANSC (PORTC Analog Function Selection).............170 IPC20 (Interrupt Priority Control 20).........................138 ANSD (PORTD Analog Function Selection).............170 IPC21 (Interrupt Priority Control 21).........................139 ANSE (PORTE Analog Function Selection)..............171 IPC22 (Interrupt Priority Control 22).........................140 ANSG (PORTG Analog Function Selection).............171 IPC25 (Interrupt Priority Control 25).........................141 CLKDIV (Clock Divider)............................................149 IPC29 (Interrupt Priority Control 29).........................141 CMSTAT (Comparator Status)..................................319 IPC3 (Interrupt Priority Control 3).............................124 CMxCON (Comparator x Control, IPC4 (Interrupt Priority Control 4).............................125 Comparators 1-3)..............................................318 IPC5 (Interrupt Priority Control 5).............................126 CORCON (CPU Core Control)............................39, 100 IPC6 (Interrupt Priority Control 6).............................127 CRCCON1 (CRC Control 1).....................................292 IPC7 (Interrupt Priority Control 7).............................128 CRCCON2 (CRC Control 2).....................................293 IPC8 (Interrupt Priority Control 8).............................129 CRCXORL (CRC XOR Polynomial, High Byte)........294 IPC9 (Interrupt Priority Control 9).............................130 CRCXORL (CRC XOR Polynomial, Low Byte).........293 LCDCON (LCD Control)...........................................266 CTMUCON1 (CTMU Control 1)................................326 LCDCREG (LCD Charge Pump Control)..................268 CTMUCON2 (CTMU Control 2)................................327 LCDDATAx (LCD Pixel Data x)................................270 CTMUICON (CTMU Current Control).......................329 LCDPS (LCD Phase)................................................269 CVRCON (Comparator Voltage LCDREF (LCD Reference Ladder Control)..............272 Reference Control)............................................322 LCDSEx (LCD Segment x Enable)...........................270 CW1 (Flash Configuration Word 1)...........................334 MDCAR (Modulator Carrier Control).........................252 CW2 (Flash Configuration Word 2)...........................336 MDCON (Modulator Control)....................................250 CW3 (Flash Configuration Word 3)...........................338 MDSRC (Modulator Source Control)........................251 CW4 (Flash Configuration Word 4)...........................340 MINSEC (RTCC Minutes and Seconds Value).........283 DEVID (Device ID)....................................................342 MTHDY (RTCC Month and Day Value)....................282 DEVREV (Device Revision)......................................342 NVMCON (Flash Memory Control).............................85 DMACHx (DMA Channel x Control)............................80 OCxCON1 (Output Compare x Control 1)................216 DMACON (DMA Engine Control)................................79 OCxCON2 (Output Compare x Control 2)................218 DMAINTx (DMA Channel x Interrupt).........................81 OSCCON (Oscillator Control)...................................147 DSCON (Deep Sleep Control)..................................162 OSCTUN (FRC Oscillator Tune)...............................150 DSWAKE (Deep Sleep Wake-up Source)................163 PADCFG1 (Pad Configuration Control)....................263 HLVDCON (High/Low-Voltage Detect Control).........332 PMCON1 (EPMP Control 1).....................................255 I2CxCON (I2Cx Control)...........................................236 PMCON2 (EPMP Control 2).....................................256 I2CxMSK (I2Cx Slave Mode Address Mask)............239 PMCON3 (EPMP Control 3).....................................257 I2CxSTAT (I2Cx Status)...........................................238 PMCON4 (EPMP Control 4).....................................258 ICxCON1 (Input Capture x Control 1).......................207 PMCSxBS (Chip Select x Base Address).................260 ICxCON2 (Input Capture x Control 2).......................208 PMCSxCF (Chip Select x Configuration)..................259 IEC0 (Interrupt Enable Control 0).............................112 PMCSxMD (Chip Select x Mode).............................261 IEC1 (Interrupt Enable Control 1).............................114 PMSTAT (EPMP Status, Slave Mode).....................262 IEC2 (Interrupt Enable Control 2).............................116 DS30009996G-page 412  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY RCFGCAL (RTCC Calibration POR (Power-on Reset)...............................................89 and Configuration)............................................278 RCON Flags, Operation.............................................93 RCON (Reset Control)................................................90 SFR States.................................................................93 RCON2 (Reset and System Control 2).....................164 SWR (RESET Instruction)..........................................89 RCON2 (Reset Control 2)...........................................92 TRAPR (Trap Conflict Reset).....................................89 REFOCON (Reference Oscillator Control)...............153 UWR (Uninitialized W Register Reset).......................89 RPINR0 (PPS Input 0)..............................................178 WDT (Watchdog Timer Reset)...................................89 RPINR1 (PPS Input 1)..............................................178 Revision History................................................................407 RPINR10 (PPS Input 10)..........................................182 RTCC RPINR11 (PPS Input 11)..........................................182 Alarm Configuration..................................................287 RPINR17 (PPS Input 17)..........................................183 Alarm Mask Settings (figure)....................................288 RPINR18 (PPS Input 18)..........................................183 Calibration................................................................287 RPINR19 (PPS Input 19)..........................................184 Clock Source Selection............................................277 RPINR2 (PPS Input 2)..............................................179 Control Registers......................................................278 RPINR20 (PPS Input 20)..........................................184 Power Control...........................................................288 RPINR21 (PPS Input 21)..........................................185 Register Mapping.....................................................277 RPINR22 (PPS Input 22)..........................................185 Source Clock............................................................275 RPINR23 (PPS Input 23)..........................................186 VBAT Operation.........................................................288 RPINR27 (PPS Input 27)..........................................186 Write Lock.................................................................277 RPINR3 (PPS Input 3)..............................................179 S RPINR30 (PPS Input 30)..........................................187 RPINR31 (PPS Input 31)..........................................187 Selective Peripheral Power Control..................................165 RPINR4 (PPS Input 4)..............................................180 Serial Peripheral Interface (SPI).......................................221 RPINR7 (PPS Input 7)..............................................180 Serial Peripheral Interface. See SPI. RPINR8 (PPS Input 8)..............................................181 SFR Space.........................................................................44 RPINR9 (PPS Input 9)..............................................181 Software Simulator (MPLAB SIM)....................................349 RPOR0 (PPS Output 0)............................................188 Software Stack...................................................................68 RPOR1 (PPS Output 1)............................................188 Special Features.................................................................12 RPOR10 (PPS Output 10)........................................193 SPI....................................................................................221 RPOR11 (PPS Output 11)........................................193 T RPOR12 (PPS Output 12)........................................194 RPOR13 (PPS Output 13)........................................194 Timer1..............................................................................197 RPOR14 (PPS Output 14)........................................195 Timer2/3 and Timer4/5.....................................................199 RPOR15 (PPS Output 15)........................................195 Timing Diagrams RPOR2 (PPS Output 2)............................................189 CLKO and I/O Timing...............................................372 RPOR3 (PPS Output 3)............................................189 External Clock..........................................................370 RPOR4 (PPS Output 4)............................................190 I2Cx Bus Data (Master Mode)..................................377 RPOR5 (PPS Output 5)............................................190 I2Cx Bus Data (Slave Mode)....................................378 RPOR6 (PPS Output 6)............................................191 I2Cx Bus Start/Stop Bits (Master Mode)...................376 RPOR7 (PPS Output 7)............................................191 I2Cx Bus Start/Stop Bits (Slave Mode).....................378 RPOR8 (PPS Output 8)............................................192 ICx (Input Capture Mode).........................................375 RPOR9 (PPS Output 9)............................................192 Input Capture x.........................................................374 RTCCSWT (Power Control and Sample Output Compare x....................................................375 Window Timer)..................................................286 PWM Requirements.................................................375 RTCPWC (RTCC Power Control).............................280 SPIx Master Mode (CKE = 0)...................................380 SPIxCON1 (SPIx Control 1)......................................226 SPIx Slave Mode (CKE = 0).....................................382 SPIxCON2 (SPIx Control 2)......................................228 SPIx Slave Mode (CKE = 1).....................................383 SPIxSTAT (SPIx Status and Control).......................224 Timer1/2/3/4/5 External Clock Input.........................374 SR (ALU STATUS)...............................................38, 99 UARTx Baud Rate Generator Output.......................384 T1CON (Timer1 Control)...........................................198 UARTx Start Bit Edge Detection...............................384 TxCON (Timer2 and Timer4 Control)........................202 Timing Requirements TyCON (Timer3 and Timer5 Control)........................203 I2Cx Bus Data (Master Mode)..................................377 UxMODE (UARTx Mode)..........................................244 I2Cx Bus Data (Slave Mode)....................................379 UxSTA (UARTx Status and Control).........................246 I2Cx Bus Start/Stop Bits (Master Mode)...................376 WKDYHR (RTCC Weekday and Hours Value).........283 I2Cx Bus Start/Stop Bits (Slave Mode).....................378 YEAR (RTCC Year Value)........................................282 Input Capture x.................................................374, 375 Resets Output Compare 1....................................................375 BOR (Brown-out Reset)..............................................89 PWM.........................................................................376 Brown-out Reset (BOR)..............................................93 SPIx Master Mode (CKE = 0)...................................380 Clock Source Selection...............................................93 SPIx Slave Mode (CKE = 0).....................................382 CM (Configuration Mismatch Reset)...........................89 SPIx Slave Mode (CKE = 1).....................................383 Delay Times................................................................94 Timer1/2/3/4/5 External Clock Input.........................374 Device Times..............................................................93 Triple Comparator.............................................................315 IOPUWR (Illegal Opcode Reset)................................89 Triple Comparator Module................................................315 MCLR (Pin Reset).......................................................89  2010-2014 Microchip Technology Inc. DS30009996G-page 413

PIC24FJ128GA310 FAMILY U W UART................................................................................241 Watchdog Timer (WDT)....................................................344 Baud Rate Generator (BRG).....................................242 Control Register........................................................344 Infrared Support........................................................243 Windowed Operation................................................344 Operation of UxCTS and UxRTS Pins......................243 WWW Address.................................................................414 Receiving WWW, On-Line Support.....................................................10 8-Bit or 9-Bit Data Mode...................................243 Transmitting 8-Bit Data Mode................................................243 9-Bit Data Mode................................................243 Break and Sync Sequence...............................243 Universal Asynchronous Receiver Transmitter. See UART. DS30009996G-page 414  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following information: • Field Application Engineer (FAE) • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is • General Technical Support – Frequently Asked included in the back of this document. Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2010-2014 Microchip Technology Inc. DS30009996G-page 415

PIC24FJ128GA310 FAMILY NOTES: DS30009996G-page 416  2010-2014 Microchip Technology Inc.

PIC24FJ128GA310 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 FJ 128 GA3 10 T - I / PT - XXX Examples: a) PIC24FJ64GA306-I/MR: Microchip Trademark PIC24F device with LCD Controller and XLP Technology, 64-Kbyte program memory, 64-pin, Architecture Industrial temp., QFN package. Flash Memory Family b) PIC24FJ128GA308-I/PT: Program Memory Size (KB) PIC24F device with LCD Controller and XLP Technology, 128-Kbyte program memory, Product Group 80-pin, Industrial temp., TQFP package. Pin Count c) PIC24FJ128GA210-I/BG: Tape and Reel Flag (if applicable) PIC24F device with LCD Controller and XLP Technology, 128-Kbyte program memory, Temperature Range 121-pin, Industrial temp., BGA package. Package Pattern Architecture 24 = 16-bit modified Harvard without DSP Flash Memory Family FJ = Flash program memory Product Group GA3= General purpose microcontrollers with LCD Controller and XLP Technology Pin Count 06 = 64-pin 08 = 80-pin 10 = 100-pin (TQFP) and 121-pin (BGA) Temperature Range I = -40C to +85C (Industrial) Package BG = 121-pin (10x10x1.4 mm) BGA package PT = 100-lead (12x12x1 mm) TQFP (Thin Quad Flatpack) PF = 100-lead (14x14x1 mm) TQFP (Thin Quad Flatpack) PT = 80-pin (12x12x1 mm) TQFP (Thin Quad Flatpack) PT = 64-lead (10x10x1 mm) TQFP (Thin Quad Flatpack) MR = 64-lead (9x9x0.9 mm) QFN (Quad Flatpack, No Lead) Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample  2010-2014 Microchip Technology Inc. DS30009996G-page 417

PIC24FJ128GA310 FAMILY NOTES: DS30009996G-page 418  2010-2014 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2010-2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62077-988-0 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2010-2014 Microchip Technology Inc. DS30009996G-page 419

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