PIC18F2458/2553/4458/4553 Data Sheet 28/40/44-Pin High-Performance, Enhanced Flash, USB Microcontrollers with 12-Bit A/D and nanoWatt Technology © 2009 Microchip Technology Inc. DS39887C

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. rfPIC and UNI/O are registered trademarks of Microchip MICROCHIP MAKES NO REPRESENTATIONS OR Technology Incorporated in the U.S.A. and other countries. WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, OTHERWISE, RELATED TO THE INFORMATION, MXDEV, MXLAB, SEEVAL and The Embedded Control INCLUDING BUT NOT LIMITED TO ITS CONDITION, Solutions Company are registered trademarks of Microchip QUALITY, PERFORMANCE, MERCHANTABILITY OR Technology Incorporated in the U.S.A. FITNESS FOR PURPOSE. Microchip disclaims all liability Analog-for-the-Digital Age, Application Maestro, CodeGuard, arising from this information and its use. Use of Microchip dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, devices in life support and/or safety applications is entirely at ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial the buyer’s risk, and the buyer agrees to defend, indemnify and Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified hold harmless Microchip from any and all damages, claims, logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code suits, or expenses resulting from such use. No licenses are Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, conveyed, implicitly or otherwise, under any Microchip PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total intellectual property rights. Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39887C-page 2 © 2009 Microchip Technology Inc.

PIC18F2458/2553/4458/4553 28/40/44-Pin High-Performance, Enhanced Flash, USB Microcontrollers with 12-Bit A/D and nanoWatt Technology Universal Serial Bus Features: Flexible Oscillator Structure: • USB V2.0 Compliant • Four Crystal modes, Including High-Precision PLL • Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s) for USB • Supports Control, Interrupt, Isochronous and Bulk • Two External Clock modes, up to 48 MHz Transfers • Internal Oscillator Block: • Supports up to 32 Endpoints (16 bidirectional) - 8 user-selectable frequencies, from 31kHz • 1-Kbyte Dual Access RAM for USB to 8MHz • On-Chip USB Transceiver with On-Chip Voltage - User-tunable to compensate for frequency drift Regulator • Secondary Oscillator using Timer1 @ 32 kHz • Interface for Off-Chip USB Transceiver • Dual Oscillator Options allow Microcontroller and • Streaming Parallel Port (SPP) for USB Streaming USB module to Run at Different Clock Speeds Transfers (40/44-pin devices only) • Fail-Safe Clock Monitor: Power-Managed Modes: - Allows for safe shutdown if any clock stops • Run: CPU On, Peripherals On Peripheral Highlights: • Idle: CPU Off, Peripherals On • High-Current Sink/Source: 25mA/25mA • Sleep: CPU Off, Peripherals Off • Three External Interrupts • Idle mode Currents Down to 5.8 μA Typical • Four Timer modules (Timer0 to Timer3) • Sleep mode Currents Down to 0.1 μA Typical • Up to 2 Capture/Compare/PWM (CCP) modules: • Timer1 Oscillator: 1.1 μA Typical, 32 kHz, 2V - Capture is 16-bit, max. resolution 5.2ns (TCY/16) • Watchdog Timer: 2.1 μA Typical - Compare is 16-bit, max. resolution 83.3ns (TCY) • Two-Speed Oscillator Start-up - PWM output: PWM resolution is 1 to 10-bits Special Microcontroller Features: • Enhanced Capture/Compare/PWM (ECCP) module: • C Compiler Optimized Architecture with Optional - Multiple output modes Extended Instruction Set - Selectable polarity • 100,000 Erase/Write Cycle Enhanced Flash - Programmable dead time Program Memory Typical - Auto-shutdown and auto-restart • 1,000,000 Erase/Write Cycle Data EEPROM • Enhanced USART module: Memory Typical - LIN bus support • Flash/Data EEPROM Retention: > 40 Years • Master Synchronous Serial Port (MSSP) module • Self-Programmable under Software Control supporting 3-wire SPI (all 4 modes) and I2C™ • Priority Levels for Interrupts Master and Slave modes • 8 x 8 Single-Cycle Hardware Multiplier • 12-Bit, up to 13-Channel Analog-to-Digital Converter • Extended Watchdog Timer (WDT): module (A/D) with Programmable Acquisition Time - Programmable period from 41ms to 131s • Dual Analog Comparators with Input Multiplexing • Programmable Code Protection Note: This document is supplemented by • Single-Supply 5V In-Circuit Serial the“PIC18F2455/2550/4455/4550 Data Programming™ (ICSP™) via Two Pins Sheet” (DS39632). See Section1.0 • In-Circuit Debug (ICD) via Two Pins “Device Overview”. • Optional Dedicated ICD/ICSP Port (44-pin TQFP package only) • Wide Operating Voltage Range (2.0V to 5.5V) Device (bFylaPtserhso)gra#mI nS siMntrgeulmec-toWiorynosrd (SbRyDtAaeMtsa) MEe(EbmPyoRterOys)M I/O A1/D2- B(ciht ) CC(PPW/EMCC)P SPP SPIMSMSI2PaCs™ter EUSART Comp. 8T/i1m6-eBrsit PIC18F2458 24K 12288 24 10 2/0 No PIC18F2553 32K 16384 2048 256 Y Y 1 2 1/3 PIC18F4458 24K 12288 35 13 1/1 Yes PIC18F4553 32K 16384 © 2009 Microchip Technology Inc. DS39887C-page 3

PIC18F2458/2553/4458/4553 Pin Diagrams 28-Pin SPDIP, SOIC MCLR/VPP/RE3 1 28 RB7/KBI3/PGD RA0/AN0 2 27 RB6/KBI2/PGC RA1/AN1 3 26 RB5/KBI1/PGM RA2/AN2/VREF-/CVREF 4 25 RB4/AN11/KBI0 RA3/AN3/VREF+ 5 83 24 RB3/AN9/CCP2(1)/VPO 55 RA4/T0CKI/C1OUT/RCV 6 45 23 RB2/AN8/INT2/VMO 22 RA5/AN4/SS/HLVDIN/C2OUT 7 FF 22 RB1/AN10/INT1/SCK/SCL 88 VSS 8 11 21 RB0/AN12/INT0/FLT0/SDI/SDA OSC1/CLKI 9 PICPIC 20 VDD OSC2/CLKO/RA6 10 19 VSS RC0/T1OSO/T13CKI 11 18 RC7/RX/DT/SDO RC1/T1OSI/CCP2(1)/UOE 12 17 RC6/TX/CK RC2/CCP1 13 16 RC5/D+/VP VUSB 14 15 RC4/D-/VM 40-Pin PDIP MCLR/VPP/RE3 1 40 RB7/KBI3/PGD RA0/AN0 2 39 RB6/KBI2/PGC RA1/AN1 3 38 RB5/KBI1/PGM RA2/AN2/VREF-/CVREF 4 37 RB4/AN11/KBI0/CSSPP RA3/AN3/VREF+ 5 36 RB3/AN9/CCP2(1)/VPO RA4/T0CKI/C1OUT/RCV 6 35 RB2/AN8/INT2/VMO RA5/AN4/SS/HLVDIN/C2OUT 7 34 RB1/AN10/INT1/SCK/SCL RE0/AN5/CK1SPP 8 83 33 RB0/AN12/INT0/FLT0/SDI/SDA 55 RE1/AN6/CK2SPP 9 45 32 VDD 44 RE2/AN7/OESPP 10 FF 31 VSS VDD 11 1818 30 RD7/SPP7/P1D VSS 12 CC 29 RD6/SPP6/P1C OSC1/CLKI 13 PIPI 28 RD5/SPP5/P1B OSC2/CLKO/RA6 14 27 RD4/SPP4 RC0/T1OSO/T13CKI 15 26 RC7/RX/DT/SDO RC1/T1OSI/CCP2(1)/UOE 16 25 RC6/TX/CK RC2/CCP1/P1A 17 24 RC5/D+/VP VUSB 18 23 RC4/D-/VM RD0/SPP0 19 22 RD3/SPP3 RD1/SPP1 20 21 RD2/SPP2 Note1: RB3 is the alternate pin for CCP2 multiplexing. DS39887C-page 4 © 2009 Microchip Technology Inc.

PIC18F2458/2553/4458/4553 Pin Diagrams (Continued) E O U (1)2/ 44-Pin TQFP TX/CKD+/VPD-/VMSPP3SPP2SPP1SPP0 CCP1/P1AT1OSI/CCP(2)CPORTS C6/C5/C4/D3/D2/D1/D0/USBC2/C1/C/I RRRRRRRVRRN 43210987654 RC7/RX/DT/SDO 1 4444433333333 NC/ICRST(2)/ICVPP(2) RD4/SPP4 2 32 RC0/T1OSO/T13CKI RD5/SPP5/P1B 3 31 OSC2/CLKO/RA6 RD6/SPP6/P1C 4 30 OSC1/CLKI RD7/SPP7/P1D 5 PIC18F4458 29 VSS VSS 6 PIC18F4553 28 VDD VDD 7 27 RE2/AN7/OESPP RB0/AN12/INT0/FLT0/SDI/SDA 8 26 RE1/AN6/CK2SPP RB1/AN10/INT1/SCK/SCL 9 25 RE0/AN5/CK1SPP RB2/AN8/INT2/VMO 10 24 RA5/AN4/SS/HLVDIN/C2OUT RB3/AN9/CCP2(1)/VPO 11 23 RA4/T0CKI/C1OUT/RCV 23456789012 11111111222 (2)(2)NC/ICCK/ICPGC(2)(2)NC/ICDT/ICPGDRB4/AN11/KBI0/CSSPPRB5/KBI1/PGMRB6/KBI2/PGCRB7/KBI3/PGDMCLR/V/RE3PPRA0/AN0RA1/AN1RA2/AN2/V-/CVREFREFRA3/AN3/V+REF (1)2/UOE3CKI AP1 1CT 44-Pin QFN TX/CKD+/VPD-/VMSPP3SPP2SPP1SPP0 CCP1/PT1OSI/CT1OSO/ C6/C5/C4/D3/D2/D1/D0/USBC2/C1/C0/ RRRRRRRVRRR 4443424140393837363534 RC7/RX/DT/SDO 1 33 OSC2/CLKO/RA6 RD4/SPP4 2 32 OSC1/CLKI RD5/SPP5/P1B 3 31 VSS RD6/SPP6/P1C 4 30 VSS RD7/SPP7/P1D 5 PIC18F4458 29 VDD VSS 6 PIC18F4553 28 VDD VDD 7 27 RE2/AN7/OESPP VDD 8 26 RE1/AN6/CK2SPP RB0/AN12/INT0/FLT0/SDI/SDA 9 25 RE0/AN5/CK1SPP RB1/AN10/INT1/SCK/SCL 10 24 RA5/AN4/SS/HLVDIN/C2OUT RB2/AN8/INT2/VMO 11 23 RA4/T0CKI/C1OUT/RCV 23456789012 11111111222 (1)AN9/CCP2/VPONCN11/KBI0/CSSPPRB5/KBI1/PGMRB6/KBI2/PGCRB7/KBI3/PGDMCLR/V/RE3PPRA0/AN0RA1/AN1AN2/V-/CVREFREFRA3/AN3/V+REF B3/ 4/A A2/ R B R R Note 1: RB3 is the alternate pin for CCP2 multiplexing. 2: Special ICPORT features are available only in 44-pin TQFP packages. See Section 25.9 “Special ICPORT Features” in the “PIC18F2455/2550/4455/4550 Data Sheet”’. © 2009 Microchip Technology Inc. DS39887C-page 5

PIC18F2458/2553/4458/4553 Table of Contents 1.0 Device Overview..........................................................................................................................................................................7 2.0 12-Bit Analog-to-Digital Converter (A/D) Module.......................................................................................................................21 3.0 Special Features of the CPU......................................................................................................................................................31 4.0 Electrical Characteristics............................................................................................................................................................33 5.0 Packaging Information................................................................................................................................................................37 Appendix A: Revision History...............................................................................................................................................................39 Appendix B: Device Differences...........................................................................................................................................................39 Appendix C: Migration From Mid-Range to Enhanced Devices...........................................................................................................40 Appendix D: Migration From High-End to Enhanced Devices.............................................................................................................40 Index....................................................................................................................................................................................................41 The Microchip Web Site.......................................................................................................................................................................43 Customer Change Notification Service................................................................................................................................................43 Customer Support................................................................................................................................................................................43 Reader Response................................................................................................................................................................................44 Product Identification System...............................................................................................................................................................45 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39887C-page 6 © 2009 Microchip Technology Inc.

PIC18F2458/2553/4458/4553 1.0 DEVICE OVERVIEW 1.2 Details on Individual Family Members This document contains device-specific information for the following devices: The PIC18F2458/2553/4458/4553 devices are available in 28-pin and 40/44-pin packages. Block • PIC18F2458 • PIC18F4458 diagrams for the two groups are shown in Figure1-1 • PIC18F2553 • PIC18F4553 and Figure1-2. The devices are differentiated from each other in the Note: This data sheet documents only the following ways: devices’ features and specifications that are 1. Flash program memory (24Kbytes for in addition to the features and specifica- PIC18FX458 devices, 32Kbytes for tions of the PIC18F2455/2550/4455/4550 PIC18FX553). devices. For information on the features and specifications shared by 2. A/D channels (10 for 28-pin devices, 13 for the PIC18F2458/2553/4458/4553 and 40-pin and 44-pin devices). PIC18F2455/2550/4455/4550 devices, 3. I/O ports (3 bidirectional ports and 1 input only see the “PIC18F2455/2550/4455/4550 port on 28-pin devices, 5 bidirectional ports on Data Sheet” (DS39632). 40-pin and 44-pin devices). 4. CCP and Enhanced CCP implementation The PIC18F4553 family of devices offers the advan- (28-pin devices have two standard CCP tages of all PIC18 microcontrollers – namely, high modules, 40-pin and 44-pin devices have one computational performance at an economical price – standard CCP module and one ECCP module). with the addition of high-endurance, Enhanced Flash 5. Streaming Parallel Port (present only on program memory. In addition to these features, the 40/44-pin devices). PIC18F4553 family introduces design enhancements that make these microcontrollers a logical choice for All other features for devices in this family are identical. many high-performance, power sensitive applications. These are summarized in Table1-1. The pinouts for all devices are listed in Table1-2 and 1.1 Special Features Table1-3. • 12-Bit A/D Converter: The PIC18F4553 family Members of the PIC18F4553 family are available as implements a 12-bit A/D Converter. The A/D both standard and low-voltage devices. Standard Converter incorporates programmable acquisi- devices with Enhanced Flash memory, designated with tion time. This allows for a channel to be selected an “F” in the part number (such as PIC18F2458), and a conversion to be initiated, without waiting accommodate an operating VDD range of 4.2V to 5.5V. for a sampling period and thus, reducing code Low-voltage parts, designated by “LF” (such as overhead. PIC18LF2458), function over an extended VDD range of 2.0V to 5.5V. © 2009 Microchip Technology Inc. DS39887C-page 7

PIC18F2458/2553/4458/4553 TABLE 1-1: DEVICE FEATURES Features PIC18F2458 PIC18F2553 PIC18F4458 PIC18F4553 Operating Frequency DC – 48 MHz DC – 48 MHz DC – 48 MHz DC – 48 MHz Program Memory (Bytes) 24576 32768 24576 32768 Program Memory 12288 16384 12288 16384 (Instructions) Data Memory (Bytes) 2048 2048 2048 2048 Data EEPROM Memory 256 256 256 256 (Bytes) Interrupt Sources 19 19 20 20 I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E Timers 4 4 4 4 Capture/Compare/PWM 2 2 1 1 Modules Enhanced Capture/ 0 0 1 1 Compare/PWM Modules Serial Communications MSSP, MSSP, MSSP, MSSP, Enhanced USART Enhanced USART Enhanced USART Enhanced USART Universal Serial Bus (USB) 1 1 1 1 Module Streaming Parallel Port (SPP) No No Yes Yes 12-Bit Analog-to-Digital 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels Converter Module Comparators 2 2 2 2 Resets (and Delays) POR, BOR, WDT, POR, BOR, WDT, POR, BOR, WDT, POR, BOR, WDT, RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction, Stack Full, Stack Stack Full, Stack Stack Full, Stack Stack Full, Stack Underflow, MCLR Underflow, MCLR Underflow, MCLR Underflow, MCLR (optional), (optional), (optional), (optional), (PWRT, OST) (PWRT, OST) (PWRT, OST) (PWRT, OST) Programmable High/ Yes Yes Yes Yes Low-Voltage Detect Programmable Brown-out Yes Yes Yes Yes Reset Instruction Set 75 Instructions; 75 Instructions; 75 Instructions; 75 Instructions; 83 with Extended 83 with Extended 83 with Extended 83 with Extended Instruction Set Instruction Set Instruction Set Instruction Set Enabled Enabled Enabled Enabled Packages 28-Pin SPDIP 28-Pin SPDIP 40-Pin PDIP 40-Pin PDIP 28-Pin SOIC 28-Pin SOIC 44-Pin QFN 44-Pin QFN 44-Pin TQFP 44-Pin TQFP Corresponding Devices with PIC18F2455 PIC18F2550 PIC18F4455 PIC18F4550 10-Bit A/D DS39887C-page 8 © 2009 Microchip Technology Inc.

PIC18F2458/2553/4458/4553 FIGURE 1-1: PIC18F2458/2553 (28-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> PORTA Data Latch RA0/AN0 inc/dec logic 8 8 RA1/AN1 Data Memory RA2/AN2/VREF-/CVREF 21 PCLAT U PCLATH (2Kbytes) RRAA43//TA0NC3K/VI/RCE1FO+UT/RCV 20 Address Latch RA5/AN4/SS/HLVDIN/C2OUT PCU PCH PCL OSC2/CLKO/RA6 Program Counter 12 Data Address<12> 31 Level Stack Address Latch 4 12 4 BSR Access Program Memory STKPTR FSR0 Bank (24/32Kbytes) FSR1 Data Latch FSR2 12 PORTB RB0/AN12/INT0/FLT0/SDI/SDA inc/dec RB1/AN10/INT1/SCK/SCL 8 Table Latch logic RB2/AN8/INT2/VMO RB3/AN9/CCP2(3)/VPO RB4/AN11/KBI0 ROM Latch Address RB5/KBI1/PGM Instruction Bus <16> Decode RB6/KBI2/PGC RB7/KBI3/PGD IR 8 Instruction State Machine Decode & Control Signals Control PRODH PRODL PORTC 8 x 8 Multiply RC0/T1OSO/T13CKI 3 8 RC1/T1OSI/CCP2(3)/UOE OSC1(2) Internal Power-up RC2/CCP1 OsBcloillcaktor Timer BITOP8 W8 8 RC4/D-/VM OSC2(2) Oscillator RC5/D+/VP INTRC Start-up Timer RC6/TX/CK T1OSI Oscillator Power-on 8 8 RC7/RX/DT/SDO Reset 8 MHz ALU<8> T1OSO Oscillator Watchdog Timer 8 MCLR(1) Single-Supply BrRowesne-otut Programming In-Circuit Fail-Safe VDD,VSS Debugger Clock Monitor PORTE USB Voltage Band Gap VUSB Regulator Reference MCLR/VPP/RE3(1) BOR Data HLVD EEPROM Timer0 Timer1 Timer2 Timer3 Comparator CCP1 CCP2 MSSP EUSART ADC USB 12-Bit Note1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. 3: RB3 is the alternate pin for CCP2 multiplexing. © 2009 Microchip Technology Inc. DS39887C-page 9

PIC18F2458/2553/4458/4553 FIGURE 1-2: PIC18F4458/4553(40/44-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> PORTA RA0/AN0 inc/dec logic 8 8 Data Latch RA1/AN1 RA2/AN2/VREF-/CVREF Data Memory RA3/AN3/VREF+ 21 PCLAT U PCLATH (2Kbytes) RA4/T0CKI/C1OUT/RCV RA5/AN4/SS/HLVDIN/C2OUT 20 Address Latch PCU PCH PCL OSC2/CLKO/RA6 Program Counter 12 Data Address<12> PORTB 31 Level Stack RB0/AN12/INT0/FLT0/SDI/SDA Address Latch 4 12 4 RB1/AN10/INT1/SCK/SCL BSR Access Program Memory STKPTR FSR0 Bank RB2/AN8/INT2/VMO (24/32Kbytes) FSR1 RB3/AN9/CCP2(4)/VPO Data Latch FSR2 12 RB4/AN11/KBI0/CSSPP RB5/KBI1/PGM RB6/KBI2/PGC inc/dec 8 logic RB7/KBI3/PGD Table Latch Address PORTC ROM Latch Instruction Bus <16> Decode RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(4)/UOE RC2/CCP1/P1A IR RC4/D-/VM RC5/D+/VP 8 RC6/TX/CK Instruction State Machine RC7/RX/DT/SDO Decode & Control Signals Control PRODH PRODL PORTD 8 x 8 Multiply VDD, VSS 3 8 Internal OSC1(2) OsBcloillcaktor PoTwimere-rup BITO8P W8 8 RRDD05//SSPPPP05:/RP1DB4/SPP4 OSC2(2) Oscillator RD6/SPP6/P1C INTRC Start-up Timer RD7/SPP7/P1D T1OSI Oscillator 8 8 Power-on T1OSO O8s cMillHatzor Reset ALU<8> Watchdog 8 ICPGC(3) Single-Supply Timer ICPGD(3) Programming BrRowesne-otut PORTE In-Circuit RE0/AN5/CK1SPP ICPORTS(3) Debugger Fail-Safe RE1/AN6/CK2SPP ICRST(3) Clock Monitor RBeafnedr eGnacpe MREC2L/RA/NV7P/PO/REES3P(P1) MCLR(1) USB Voltage Regulator VUSB BOR Data Timer0 Timer1 Timer2 Timer3 HLVD EEPROM Comparator ECCP1 CCP2 MSSP EUSART ADC USB 12-Bit Note1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. 3: These pins are only available on 44-pin TQFP packages under certain conditions. 4: RB3 is the alternate pin for CCP2 multiplexing. DS39887C-page 10 © 2009 Microchip Technology Inc.

PIC18F2458/2553/4458/4553 TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type SPDIP, SOIC MCLR/VPP/RE3 1 Master Clear (input) or programming voltage (input). MCLR I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. VPP P Programming voltage input. RE3 I ST Digital input. OSC1/CLKI 9 Oscillator crystal or external clock input. OSC1 I Analog Oscillator crystal input or external clock source input. CLKI I Analog External clock source input. Always associated with pin function OSC1. (See OSC2/CLKO pin.) OSC2/CLKO/RA6 10 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In select modes, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. © 2009 Microchip Technology Inc. DS39887C-page 11

PIC18F2458/2553/4458/4553 TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type SPDIP, SOIC PORTA is a bidirectional I/O port. RA0/AN0 2 RA0 I/O TTL Digital I/O. AN0 I Analog Analog input 0. RA1/AN1 3 RA1 I/O TTL Digital I/O. AN1 I Analog Analog input 1. RA2/AN2/VREF-/CVREF 4 RA2 I/O TTL Digital I/O. AN2 I Analog Analog input 2. VREF- I Analog A/D reference voltage (low) input. CVREF O Analog Analog comparator reference output. RA3/AN3/VREF+ 5 RA3 I/O TTL Digital I/O. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI/C1OUT/RCV 6 RA4 I/O ST Digital I/O. T0CKI I ST Timer0 external clock input. C1OUT O — Comparator 1 output. RCV I TTL External USB transceiver RCV input. RA5/AN4/SS/ 7 HLVDIN/C2OUT RA5 I/O TTL Digital I/O. AN4 I Analog Analog input 4. SS I TTL SPI slave select input. HLVDIN I Analog High/Low-Voltage Detect input. C2OUT O — Comparator 2 output. RA6 — — — See the OSC2/CLKO/RA6 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. DS39887C-page 12 © 2009 Microchip Technology Inc.

PIC18F2458/2553/4458/4553 TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type SPDIP, SOIC PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/AN12/INT0/FLT0/ 21 SDI/SDA RB0 I/O TTL Digital I/O. AN12 I Analog Analog input 12. INT0 I ST External interrupt 0. FLT0 I ST PWM Fault input (CCP1 module). SDI I ST SPI data in. SDA I/O ST I2C™ data I/O. RB1/AN10/INT1/SCK/ 22 SCL RB1 I/O TTL Digital I/O. AN10 I Analog Analog input 10. INT1 I ST External interrupt 1. SCK I/O ST Synchronous serial clock input/output for SPI mode. SCL I/O ST Synchronous serial clock input/output for I2C mode. RB2/AN8/INT2/VMO 23 RB2 I/O TTL Digital I/O. AN8 I Analog Analog input 8. INT2 I ST External interrupt 2. VMO O — External USB transceiver VMO output. RB3/AN9/CCP2/VPO 24 RB3 I/O TTL Digital I/O. AN9 I Analog Analog input 9. CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM 2 output. VPO O — External USB transceiver VPO output. RB4/AN11/KBI0 25 RB4 I/O TTL Digital I/O. AN11 I Analog Analog input 11. KBI0 I TTL Interrupt-on-change pin. RB5/KBI1/PGM 26 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. PGM I/O ST Low-Voltage ICSP™ Programming enable pin. RB6/KBI2/PGC 27 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP programming clock pin. RB7/KBI3/PGD 28 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. © 2009 Microchip Technology Inc. DS39887C-page 13

PIC18F2458/2553/4458/4553 TABLE 1-2: PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type SPDIP, SOIC PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 11 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/CCP2/UOE 12 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM2 output. UOE — — External USB transceiver OE output. RC2/CCP1 13 RC2 I/O ST Digital I/O. CCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. RC4/D-/VM 15 RC4 I TTL Digital input. D- I/O — USB differential minus line (input/output). VM I TTL External USB transceiver VM input. RC5/D+/VP 16 RC5 I TTL Digital input. D+ I/O — USB differential plus line (input/output). VP O TTL External USB transceiver VP input. RC6/TX/CK 17 RC6 I/O ST Digital I/O. TX O — EUSART asynchronous transmit. CK I/O ST EUSART synchronous clock (see RX/DT). RC7/RX/DT/SDO 18 RC7 I/O ST Digital I/O. RX I ST EUSART asynchronous receive. DT I/O ST EUSART synchronous data (see TX/CK). SDO O — SPI data out. RE3 — — — See MCLR/VPP/RE3 pin. VUSB 14 Internal USB transceiver power supply. O — When the internal USB regulator is enabled, VUSB is the regulator output. P — When the internal USB regulator is disabled, VUSB is the power input for the USB transceiver. VSS 8, 19 P — Ground reference for logic and I/O pins. VDD 20 P — Positive supply for logic and I/O pins. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. DS39887C-page 14 © 2009 Microchip Technology Inc.

PIC18F2458/2553/4458/4553 TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP MCLR/VPP/RE3 1 18 18 Master Clear (input) or programming voltage (input). MCLR I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. VPP P Programming voltage input. RE3 I ST Digital input. OSC1/CLKI 13 32 30 Oscillator crystal or external clock input. OSC1 I Analog Oscillator crystal input or external clock source input. CLKI I Analog External clock source input. Always associated with pin function OSC1. (See OSC2/CLKO pin.) OSC2/CLKO/RA6 14 33 31 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2009 Microchip Technology Inc. DS39887C-page 15

PIC18F2458/2553/4458/4553 TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP PORTA is a bidirectional I/O port. RA0/AN0 2 19 19 RA0 I/O TTL Digital I/O. AN0 I Analog Analog input 0. RA1/AN1 3 20 20 RA1 I/O TTL Digital I/O. AN1 I Analog Analog input 1. RA2/AN2/VREF-/ 4 21 21 CVREF RA2 I/O TTL Digital I/O. AN2 I Analog Analog input 2. VREF- I Analog A/D reference voltage (low) input. CVREF O Analog Analog comparator reference output. RA3/AN3/VREF+ 5 22 22 RA3 I/O TTL Digital I/O. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI/C1OUT/ 6 23 23 RCV RA4 I/O ST Digital I/O. T0CKI I ST Timer0 external clock input. C1OUT O — Comparator 1 output. RCV I TTL External USB transceiver RCV input. RA5/AN4/SS/ 7 24 24 HLVDIN/C2OUT RA5 I/O TTL Digital I/O. AN4 I Analog Analog input 4. SS I TTL SPI slave select input. HLVDIN I Analog High/Low-Voltage Detect input. C2OUT O — Comparator 2 output. RA6 — — — — — See the OSC2/CLKO/RA6 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. DS39887C-page 16 © 2009 Microchip Technology Inc.

PIC18F2458/2553/4458/4553 TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP PORTB is a bidirectional I/O port. PORTB can be soft- ware programmed for internal weak pull-ups on all inputs. RB0/AN12/INT0/ 33 9 8 FLT0/SDI/SDA RB0 I/O TTL Digital I/O. AN12 I Analog Analog input 12. INT0 I ST External interrupt 0. FLT0 I ST Enhanced PWM Fault input (ECCP1 module). SDI I ST SPI data in. SDA I/O ST I2C™ data I/O. RB1/AN10/INT1/SCK/ 34 10 9 SCL RB1 I/O TTL Digital I/O. AN10 I Analog Analog input 10. INT1 I ST External interrupt 1. SCK I/O ST Synchronous serial clock input/output for SPI mode. SCL I/O ST Synchronous serial clock input/output for I2C mode. RB2/AN8/INT2/VMO 35 11 10 RB2 I/O TTL Digital I/O. AN8 I Analog Analog input 8. INT2 I ST External interrupt 2. VMO O — External USB transceiver VMO output. RB3/AN9/CCP2/VPO 36 12 11 RB3 I/O TTL Digital I/O. AN9 I Analog Analog input 9. CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM 2 output. VPO O — External USB transceiver VPO output. RB4/AN11/KBI0/CSSPP 37 14 14 RB4 I/O TTL Digital I/O. AN11 I Analog Analog input 11. KBI0 I TTL Interrupt-on-change pin. CSSPP O — SPP chip select control output. RB5/KBI1/PGM 38 15 15 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. PGM I/O ST Low-Voltage ICSP™ Programming enable pin. RB6/KBI2/PGC 39 16 16 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP programming clock pin. RB7/KBI3/PGD 40 17 17 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2009 Microchip Technology Inc. DS39887C-page 17

PIC18F2458/2553/4458/4553 TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 15 34 32 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/CCP2/ 16 35 35 UOE RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM2 output. UOE O — External USB transceiver OE output. RC2/CCP1/P1A 17 36 36 RC2 I/O ST Digital I/O. CCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. P1A O TTL Enhanced CCP1 PWM output, channel A. RC4/D-/VM 23 42 42 RC4 I TTL Digital input. D- I/O — USB differential minus line (input/output). VM I TTL External USB transceiver VM input. RC5/D+/VP 24 43 43 RC5 I TTL Digital input. D+ I/O — USB differential plus line (input/output). VP I TTL External USB transceiver VP input. RC6/TX/CK 25 44 44 RC6 I/O ST Digital I/O. TX O — EUSART asynchronous transmit. CK I/O ST EUSART synchronous clock (see RX/DT). RC7/RX/DT/SDO 26 1 1 RC7 I/O ST Digital I/O. RX I ST EUSART asynchronous receive. DT I/O ST EUSART synchronous data (see TX/CK). SDO O — SPI data out. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. DS39887C-page 18 © 2009 Microchip Technology Inc.

PIC18F2458/2553/4458/4553 TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP PORTD is a bidirectional I/O port or a Streaming Parallel Port (SPP). PORTD can be software programmed for internal weak pull-ups on all inputs. These pins have TTL input buffers when the SPP module is enabled. RD0/SPP0 19 38 38 RD0 I/O ST Digital I/O. SPP0 I/O TTL Streaming Parallel Port data. RD1/SPP1 20 39 39 RD1 I/O ST Digital I/O. SPP1 I/O TTL Streaming Parallel Port data. RD2/SPP2 21 40 40 RD2 I/O ST Digital I/O. SPP2 I/O TTL Streaming Parallel Port data. RD3/SPP3 22 41 41 RD3 I/O ST Digital I/O. SPP3 I/O TTL Streaming Parallel Port data. RD4/SPP4 27 2 2 RD4 I/O ST Digital I/O. SPP4 I/O TTL Streaming Parallel Port data. RD5/SPP5/P1B 28 3 3 RD5 I/O ST Digital I/O. SPP5 I/O TTL Streaming Parallel Port data. P1B O — ECCP1 PWM output, channel B. RD6/SPP6/P1C 29 4 4 RD6 I/O ST Digital I/O. SPP6 I/O TTL Streaming Parallel Port data. P1C O — ECCP1 PWM output, channel C. RD7/SPP7/P1D 30 5 5 RD7 I/O ST Digital I/O. SPP7 I/O TTL Streaming Parallel Port data. P1D O — ECCP1 PWM output, channel D. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2009 Microchip Technology Inc. DS39887C-page 19

PIC18F2458/2553/4458/4553 TABLE 1-3: PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type PDIP QFN TQFP PORTE is a bidirectional I/O port. RE0/AN5/CK1SPP 8 25 25 RE0 I/O ST Digital I/O. AN5 I Analog Analog input 5. CK1SPP O — SPP clock 1 output. RE1/AN6/CK2SPP 9 26 26 RE1 I/O ST Digital I/O. AN6 I Analog Analog input 6. CK2SPP O — SPP clock 2 output. RE2/AN7/OESPP 10 27 27 RE2 I/O ST Digital I/O. AN7 I Analog Analog input 7. OESPP O — SPP output enable output. RE3 — — — — — See MCLR/VPP/RE3 pin. VSS 12, 6, 30, 6, 29 P — Ground reference for logic and I/O pins. 31 31 VDD 11, 32 7, 8, 7, 28 P — Positive supply for logic and I/O pins. 28, 29 VUSB 18 37 37 Internal USB transceiver power supply. O — When the internal USB regulator is enabled, VUSB is the regulator output. P — When the internal USB regulator is disabled, VUSB is the power input for the USB transceiver. NC/ICCK/ICPGC(3) — — 12 No Connect or dedicated ICD/ICSP™ port clock. ICCK I/O ST In-Circuit Debugger clock. ICPGC I/O ST ICSP programming clock. NC/ICDT/ICPGD(3) — — 13 No Connect or dedicated ICD/ICSP port clock. ICDT I/O ST In-Circuit Debugger data. ICPGD I/O ST ICSP programming data. NC/ICRST/ICVPP(3) — — 33 No Connect or dedicated ICD/ICSP port Reset. ICRST I — Master Clear (Reset) input. ICVPP P — Programming voltage input. NC/ICPORTS(3) — — 34 P — No Connect or 28-pin device emulation. ICPORTS Enable 28-pin device emulation when connected to VSS. NC — 13 — — — No Connect. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. DS39887C-page 20 © 2009 Microchip Technology Inc.

PIC18F2458/2553/4458/4553 2.0 12-BIT ANALOG-TO-DIGITAL The ADCON0 register, shown in Register2-1, controls CONVERTER (A/D) MODULE the operation of the A/D module. The ADCON1 register, shown in Register2-2, configures the The Analog-to-Digital (A/D) Converter module has functions of the port pins. The ADCON2 register, 10inputs for the 28-pin devices and 13 for the 40-pin shown in Register2-3, configures the A/D clock and 44-pin devices. This module allows conversion of an source, programmed acquisition time and justification. analog input signal to a corresponding 12-bit digital number. The module has five registers: • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) • A/D Control Register 0 (ADCON0) • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) REGISTER 2-1: ADCON0: A/D CONTROL REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-2 CHS3:CHS0: Analog Channel Select bits 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5)(1,2) 0110 = Channel 6 (AN6)(1,2) 0111 = Channel 7 (AN7)(1,2) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12 1101 = Unimplemented(2) 1110 = Unimplemented(2) 1111 = Unimplemented(2) bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress 0 = A/D Idle bit 0 ADON: A/D On bit 1 = A/D Converter module is enabled 0 = A/D Converter module is disabled Note 1: These channels are not implemented on 28-pin devices. 2: Performing a conversion on unimplemented channels will return a floating input measurement. © 2009 Microchip Technology Inc. DS39887C-page 21

PIC18F2458/2553/4458/4553 REGISTER 2-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W(1) R/W(1) R/W(1) — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 VCFG1: Voltage Reference Configuration bit (VREF- source) 1 = VREF- (AN2) 0 = VSS bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source) 1 = VREF+ (AN3) 0 = VDD bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits: PCFG3: 12 11 10 9 8 (2)7 (2)6 (2)5 4 3 2 1 0 PCFG0 N N N N N N N N N N N N N A A A A A A A A A A A A A 0000(1) A A A A A A A A A A A A A 0001 A A A A A A A A A A A A A 0010 A A A A A A A A A A A A A 0011 D A A A A A A A A A A A A 0100 D D A A A A A A A A A A A 0101 D D D A A A A A A A A A A 0110 D D D D A A A A A A A A A 0111(1) D D D D D A A A A A A A A 1000 D D D D D D A A A A A A A 1001 D D D D D D D A A A A A A 1010 D D D D D D D D A A A A A 1011 D D D D D D D D D A A A A 1100 D D D D D D D D D D A A A 1101 D D D D D D D D D D D A A 1110 D D D D D D D D D D D D A 1111 D D D D D D D D D D D D D A = Analog input D = Digital I/O Note 1: The Reset value of the PCFG bits depends on the value of the PBADEN Configuration bit. When PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111. 2: AN5 through AN7 are available only on 40-pin and 44-pin devices. DS39887C-page 22 © 2009 Microchip Technology Inc.

PIC18F2458/2553/4458/4553 REGISTER 2-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(1) bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(1) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. © 2009 Microchip Technology Inc. DS39887C-page 23

PIC18F2458/2553/4458/4553 The analog reference voltage is software selectable to A device Reset forces all registers to their Reset state. either the device’s positive and negative supply voltage This forces the A/D module to be turned off and any (VDD and VSS), or the voltage level on the RA3/AN3/ conversion in progress is aborted. VREF+ and RA2/AN2/VREF-/CVREF pins. Each port pin associated with the A/D Converter can be The A/D Converter has a unique feature of being able configured as an analog input or as a digital I/O. The to operate while the device is in Sleep mode. To oper- ADRESH and ADRESL registers contain the result of ate in Sleep, the A/D conversion clock must be derived the A/D conversion. When the A/D conversion is com- from the A/D’s internal RC oscillator. plete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit (ADCON0 register) is The output of the sample and hold is the input into the cleared and the A/D Interrupt Flag bit, ADIF, is set. The Converter, which generates the result via successive block diagram of the A/D module is shown in Figure2-1. approximation. FIGURE 2-1: A/D BLOCK DIAGRAM CHS3:CHS0 1100 AN12 1011 AN11 1010 AN10 1001 AN9 1000 AN8 0111 AN7(1) 0110 AN6(1) 0101 AN5(1) 0100 AN4 VAIN 12-Bit (Input Voltage) 0011 AN3 A/D Converter 0010 AN2 0001 VCFG1:VCFG0 AN1 VDD 0000 AN0 X0 VREF+ X1 Reference Voltage 1X VREF- 0X VSS Note 1: Channels AN5 through AN7 are not available on 28-pin devices. DS39887C-page 24 © 2009 Microchip Technology Inc.

PIC18F2458/2553/4458/4553 The value in the ADRESH:ADRESL registers is 5. Wait for A/D conversion to complete, by either: unknown following Power-on and Brown-out Resets, • Polling for the GO/DONE bit to be cleared and is not affected by any other Reset. OR After the A/D module has been configured as desired, • Waiting for the A/D interrupt the selected channel must be acquired before the 6. Read A/D Result registers (ADRESH:ADRESL); conversion is started. The analog input channels must have their corresponding TRIS bits selected as an clear bit ADIF, if required. input. To determine acquisition time, see Section2.1 7. For next conversion, go to step 1 or step 2, as “A/D Acquisition Requirements”. After this acquisi- required. The A/D conversion time per bit is tion time has elapsed, the A/D conversion can be defined as TAD. A minimum wait of 2 TAD is started. An acquisition time can be programmed to required before the next acquisition starts. occur between setting the GO/DONE bit and the actual start of the conversion. FIGURE 2-2: A/D TRANSFER FUNCTION The following steps should be followed to perform an A/D conversion: FFFh 1. Configure the A/D module: • Configure analog pins, voltage reference and FFEh digital I/O (ADCON1) ut • Select A/D input channel (ADCON0) utp O • Select A/D acquisition time (ADCON2) e d • Select A/D conversion clock (ADCON2) Co 003h al • Turn on A/D module (ADCON0) git Di 002h 2. Configure A/D interrupt (if desired): • Clear ADIF bit 001h • Set ADIE bit • Set GIE bit 000h B B B B B B B B B B 3. Wait the required acquisition time (if required). S S S S S S S S S S L L L L L L L L L L 4. S•taSret tc GonOv/eDrsOioNnE: bit (ADCON0 register) 0.5 1 1.5 2 2.5 3 4094 4094.5 4095 4095.5 Analog Input Voltage FIGURE 2-3: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V Rs ANx RIC ≤ 1k SS RSS VAIN CPIN ILEAKAGE CHOLD = 25 pF 5 pF VT = 0.6V ±100 nA VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage 6V ILEAKAGE = Leakage Current at the pin due to 5V various junctions VDD 4V 3V RIC = Interconnect Resistance 2V SS = Sampling Switch CHOLD = Sample/Hold Capacitance (from DAC) 1 2 3 4 RSS = Sampling Switch Resistance SamplingSwitch(kΩ) © 2009 Microchip Technology Inc. DS39887C-page 25

PIC18F2458/2553/4458/4553 2.1 A/D Acquisition Requirements To calculate the minimum acquisition time, Equation2-1 may be used. This equation assumes that 1/2 LSb error For the A/D Converter to meet its specified accuracy, is used (4096 steps for the 12-bit A/D). The 1/2 LSb error the charge holding capacitor (CHOLD) must be allowed is the maximum error allowed for the A/D to meet its to fully charge to the input channel voltage level. The specified resolution. analog input model is shown in Figure2-3. The source Example2-3 shows the calculation of the minimum impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge required acquisition time, TACQ. This calculation is based on the following application system the capacitor CHOLD. The sampling switch (RSS) assumptions: impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the ana- CHOLD = 25 pF log input (due to pin leakage current). The maximum Rs = 2.5 kΩ recommended impedance for analog sources is Conversion Error ≤ 1/2 LSb 2.5kΩ. After the analog input channel is selected VDD = 3V → Rss = 4 kΩ (changed), the channel must be sampled for at least Temperature = 85°C (system max.) the minimum acquisition time before starting a conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. EQUATION 2-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 2-2: A/D MINIMUM CHARGING TIME VHOLD = (VREF – (VREF/4096)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))) or TC = -(CHOLD)(RIC + RSS + RS) ln(1/4096) EQUATION 2-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF TAMP = 0.2 µs TCOFF = (Temp – 25°C)(0.02 µs/°C) (85°C – 25°C)(0.02 µs/°C) 1.2 µs Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 µs. TC = -(CHOLD)(RIC + RSS + RS) ln(1/4096) µs -(25 pF) (1 kΩ + 4 kΩ + 2.5 kΩ) ln(0.0002441) µs 1.56 µs TACQ = 0.2 µs + 1.56 μs + 1.2 µs 2.96 µs DS39887C-page 26 © 2009 Microchip Technology Inc.

PIC18F2458/2553/4458/4553 2.2 Selecting and Configuring 2.3 Selecting the A/D Conversion Acquisition Time Clock The ADCON2 register allows the user to select an The A/D conversion time per bit is defined as TAD. The acquisition time that occurs each time the GO/DONE A/D conversion requires 13 TAD per 12-bit conversion. bit is set. It also gives users the option to use an The source of the A/D conversion clock is software automatically determined acquisition time. selectable. There are seven possible options for TAD: Acquisition time may be set with the ACQT2:ACQT0 • 2 TOSC bits (ADCON2<5:3>), which provides a range of 2 to • 4 TOSC 20TAD. When the GO/DONE bit is set, the A/D module • 8 TOSC continues to sample the input for the selected acquisi- • 16 TOSC tion time, then automatically begins a conversion. Since the acquisition time is programmed, there may • 32 TOSC be no need to wait for an acquisition time between • 64 TOSC selecting a channel and setting the GO/DONE bit. • Internal RC Oscillator Manual acquisition is selected when For correct A/D conversions, the A/D conversion clock ACQT2:ACQT0=000. When the GO/DONE bit is set, (TAD) must be as short as possible, but greater than the sampling is stopped and a conversion begins. The user minimum TAD (see parameter 130 for more is responsible for ensuring the required acquisition time information). has passed between selecting the desired input Table2-1 shows the resultant TAD times derived from channel and setting the GO/DONE bit. This option is the device operating frequencies and the A/D clock also the default Reset state of the ACQT2:ACQT0 bits source selected. and is compatible with devices that do not offer programmable acquisition times. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. TABLE 2-1: TAD vs. DEVICE OPERATING FREQUENCIES A/D Clock Source (TAD) Assumes TAD Min. = 0.8 μs Operation ADCS2:ADCS0 Maximum FOSC 2 TOSC 000 2.50 MHz 4 TOSC 100 5.00 MHz 8 TOSC 001 10.00 MHz 16 TOSC 101 20.00 MHz 32 TOSC 010 40.00 MHz 64 TOSC 110 48.00 MHz RC(1) x11 1.00 MHz(2) Note 1: The RC source has a typical TAD time of 2.5 μs. 2: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or a FOSC divider should be used instead; otherwise, the A/D accuracy specification may not be met. © 2009 Microchip Technology Inc. DS39887C-page 27

PIC18F2458/2553/4458/4553 2.4 Operation in Power-Managed 2.5 Configuring Analog Port Pins Modes The ADCON1, TRISA, TRISB and TRISE registers all The selection of the automatic acquisition time and A/D configure the A/D port pins. The port pins needed as conversion clock is determined in part by the clock analog inputs must have their corresponding TRIS bits source and frequency while in a power-managed mode. set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. If the A/D is expected to operate while the device is in a power-managed mode, the ADCS2:ADCS0 bits in The A/D operation is independent of the state of the ADCON2 should be updated in accordance with the CHS3:CHS0 bits and the TRIS bits. clock source to be used. The ACQT2:ACQT0 bits do Note1: When reading the PORT register, all pins not need to be adjusted as the ADCS2:ADCS0 bits configured as analog input channels will adjust the TAD time for the new clock speed. After read as cleared (a low level). Analog con- entering the mode, an A/D acquisition or conversion version on pins configured as digital pins may be started. Once started, the device should can be performed. The voltage on the pin continue to be clocked by the same clock source until will be accurately converted. the conversion has been completed. 2: Analog levels on any pin defined as a dig- If desired, the device may be placed into the ital input may cause the digital input buffer corresponding Idle mode during the conversion. If the to consume current out of the device’s device clock frequency is less than 1MHz, the A/D RC specification limits. clock source should be selected. 3: The PBADEN bit in Configuration Operation in Sleep mode requires the A/D FRC clock to Register 3H configures PORTB pins to be selected. If bits ACQT2:ACQT0 are set to ‘000’ and reset as analog or digital pins by control- a conversion is started, the conversion will be delayed ling how the PCFG3:PCFG0 bits in one instruction cycle to allow execution of the SLEEP ADCON1 are reset. instruction and entry to Sleep mode. The IDLEN bit (OSCCON<7>) must have already been cleared prior to starting the conversion. DS39887C-page 28 © 2009 Microchip Technology Inc.

PIC18F2458/2553/4458/4553 2.6 A/D Conversions After the A/D conversion is completed or aborted, a 2TCY wait is required before the next acquisition can Figure2-4 shows the operation of the A/D Converter be started. After this wait, acquisition on the selected after the GO/DONE bit has been set and the channel is automatically started. ACQT2:ACQT0 bits are cleared. A conversion is started after the following instruction to allow entry into Note: The GO/DONE bit should NOT be set in Sleep mode before the conversion begins. the same instruction that turns on the A/D. Code should wait at least 2 μs after Figure2-5 shows the operation of the A/D Converter enabling the A/D before beginning an after the GO/DONE bit has been set and the acquisition and conversion cycle. ACQT2:ACQT0 bits are set to ‘010’, and selecting a 4TAD acquisition time before the conversion starts. 2.7 Discharge Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will The discharge phase is used to initialize the value of NOT be updated with the partially completed A/D the holding capacitor. The array is discharged before conversion sample. This means the ADRESH:ADRESL every sample. This feature helps to optimize the unity registers will continue to contain the value of the last gain amplifier, as the circuit always needs to charge the completed conversion (or the last value written to the capacitor array, rather than charge/discharge based on ADRESH:ADRESL registers). previous measure values. FIGURE 2-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY – TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11TAD12TAD13 TAD1 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Discharge (typically 200 ns) Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit On the following cycle: ADRESH:ADRESL are loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. FIGURE 2-5: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) TACQT Cycles TAD Cycles 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 TAD1 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Automatic Acquisition Time Conversion starts Discharge (Holding capacitor is disconnected) (typically 200 ns) Set GO/DONE bit (Holding capacitor continues On the following cycle: acquiring input) ADRESH:ADRESL are loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. © 2009 Microchip Technology Inc. DS39887C-page 29

PIC18F2458/2553/4458/4553 2.8 Use of the CCP2 Trigger the desired location). The appropriate analog input channel must be selected and the minimum acquisition An A/D conversion can be started by the Special Event period is either timed by the user, or an appropriate TACQ Trigger of the CCP2 module. This requires that the time selected before the Special Event Trigger sets the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro- GO/DONE bit (starts a conversion). grammed as ‘1011’ and that the A/D module is enabled If the A/D module is not enabled (ADON is cleared), the (ADON bit is set). When the trigger occurs, the GO/ Special Event Trigger will be ignored by the A/D DONE bit will be set, starting the A/D acquisition and module, but will still reset the Timer1 (or Timer3) conversion, and the Timer1 (or Timer3) counter will be counter. reset to zero. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal software overhead (firmware must move ADRESH:ADRESL to TABLE 2-2: REGISTERS ASSOCIATED WITH A/D OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF (4) PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF (4) PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE (4) IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP (4) PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF (4) PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE (4) IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP (4) ADRESH A/D Result Register High Byte (4) ADRESL A/D Result Register Low Byte (4) ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 21 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 22 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 23 PORTA — RA6(2) RA5 RA4 RA3 RA2 RA1 RA0 (4) TRISA — TRISA6(2) PORTA Data Direction Control Register (4) PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 (4) TRISB PORTB Data Direction Control Register (4) LATB PORTB Data Latch Register (Read and Write to Data Latch) (4) PORTE(1) RDPU — — — RE3(3) RE2(1) RE1(1) RE0(1) (4) TRISE(1) — — — — — TRISE2 TRISE1 TRISE0 (4) LATE(1) — — — — — PORTE Data Latch Register (4) Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. 2: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. 3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’. 4: For these Reset values, see the “PIC18F2455/2550/4455/4550 Data Sheet”. DS39887C-page 30 © 2009 Microchip Technology Inc.

PIC18F2458/2553/4458/4553 3.0 SPECIAL FEATURES OF THE 3.1 Device ID Registers CPU The Device ID registers are “read-only” registers. They identify the device type and revision to device Note: For additional details on the Con- programmers, and can be read by firmware using figuration bits, refer to the table reads. “PIC18F2455/2550/4455/4550 Data Sheet”, Section 25.1 “Configuration Bits”. Device ID information presented in this section is for PIC18F2458/2553/4458/4553 only. PIC18F2458/2553/4458/4553 devices include several features intended to maximize reliability and minimize cost through elimination of external components. These include: • Device ID Registers TABLE 3-1: DEVICE IDs Default/ File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed Value 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(1) 3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 xxxx xxxx(1) Legend: x = unknown, u = unchanged Note 1: See Register3-1 and Register3-2 for DEVID values. DEVID registers are read-only and cannot be programmed by the user. © 2009 Microchip Technology Inc. DS39887C-page 31

PIC18F2458/2553/4458/4553 REGISTER 3-1: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2458/2553/4458/4553 DEVICES R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-5 DEV2:DEV0: Device ID bits See Register3-2 for a complete listing. bit 4-0 REV3:REV0: Revision ID bits These bits are used to indicate the device revision. REGISTER 3-2: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2458/2553/4458/4553 DEVICES R R R R R R R R DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-0 DEV10:DEV3: Device ID bits DEV10:DEV3 DEV2:DEV0 Device (DEVID2<7:0>) (DEVID1<7:5>) 0010 1010 011 PIC18F2458 0010 1010 010 PIC18F2553 0010 1010 001 PIC18F4458 0010 1010 000 PIC18F4553 DS39887C-page 32 © 2009 Microchip Technology Inc.

PIC18F2458/2553/4458/4553 4.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR)...................................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2).........................................................................................0V to +13.25V Total power dissipation (Note 1)...............................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300mA Maximum current into VDD pin..............................................................................................................................250mA Input clamp current, IIK (VI < 0 or VI > VDD)......................................................................................................................±20mA Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................±20mA Maximum output current sunk by any I/O pin..........................................................................................................25mA Maximum output current sourced by any I/O pin....................................................................................................25mA Maximum current sunk by all ports.......................................................................................................................200mA Maximum current sourced by all ports..................................................................................................................200mA Note1: Power dissipation is calculated as follows: Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL) 2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP/ RE3 pin, rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2009 Microchip Technology Inc. DS39887C-page 33

PIC18F2458/2553/4458/4553 FIGURE 4-1: PIC18F2458/2553/4458/4553 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18F2458/2553/4458/4553 4.5V e g 4.2V a 4.0V t l o 3.5V V 3.0V 2.5V 2.0V 48 MHz Frequency FIGURE 4-2: PIC18LF2458/2553/4458/4553 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18LF2458/2553/4458/4553 4.5V e g 4.2V 4.0V a t l o 3.5V V 3.0V 2.5V 2.0V 4 MHz 40 MHz 48 MHz Frequency For 2.0V ≤ VDD < 4.2V: FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz For 4.2V ≤ VDD: FMAX = 48 MHz Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application. DS39887C-page 34 © 2009 Microchip Technology Inc.

PIC18F2458/2553/4458/4553 TABLE 4-1: A/D CONVERTER CHARACTERISTICS:PIC18F2458/2553/4458/4553 (INDUSTRIAL) PIC18LF2458/2553/4458/4553 (INDUSTRIAL) Param Sym Characteristic Min Typ Max Units Conditions No. A01 NR Resolution — — 12 bit ΔVREF ≥ 3.0V A03 EIL Integral Linearity Error — ±1 ±2.0 LSB VDD = 3.0V ΔVREF ≥ 3.0V — — ±2.0 LSB VDD = 5.0V A04 EDL Differential Linearity Error — ±1 +1.5/-1.0 LSB VDD = 3.0V ΔVREF ≥ 3.0V — — +1.5/-1.0 LSB VDD = 5.0V A06 EOFF Offset Error — ±1 ±5 LSB VDD = 3.0V ΔVREF ≥ 3.0V — — ±3 LSB VDD = 5.0V A07 EGN Gain Error — ±1 ±1.25 LSB VDD = 3.0V ΔVREF ≥ 3.0V — — ±2.00 LSB VDD = 5.0V A10 — Monotonicity Guaranteed(1) — VSS ≤ VAIN ≤ VREF A20 ΔVREF Reference Voltage Range 3 — VDD – VSS V For 12-bit resolution (VREFH – VREFL) A21 VREFH Reference Voltage High VSS + 3.0V — VDD + 0.3V V For 12-bit resolution A22 VREFL Reference Voltage Low VSS – 0.3V — VDD – 3.0V V For 12-bit resolution A25 VAIN Analog Input Voltage VREFL — VREFH V A30 ZAIN Recommended — — 2.5 kΩ Impedance of Analog Voltage Source A50 IREF VREF Input Current(2) — — 5 μA During VAIN acquisition. — — 150 μA During A/D conversion cycle. Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2: VREFH current is from the RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from the RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source. © 2009 Microchip Technology Inc. DS39887C-page 35

PIC18F2458/2553/4458/4553 FIGURE 4-3: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK(1) 132 . . . . . . A/D DATA 11 10 9 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF TCY GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. TABLE 4-2: A/D CONVERSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 130 TAD A/D Clock Period PIC18FXXXX 0.8 12.5(1) μs TOSC based, VREF ≥ 3.0V PIC18LFXXXX 1.4 25.0(1) μs VDD = 3.0V; TOSC based, VREF full range PIC18FXXXX — 1 μs A/D RC mode PIC18LFXXXX — 3 μs VDD = 3.0V; A/D RC mode 131 TCNV Conversion Time 13 14 TAD (not including acquisition time)(2) 132 TACQ Acquisition Time(3) 1.4 — μs 135 TSWC Switching Time from Convert → Sample — (Note 4) 137 TDIS Discharge Time 0.2 — μs Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. 2: ADRES registers may be read on the following TCY cycle. 3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω. 4: On the following cycle of the device clock. DS39887C-page 36 © 2009 Microchip Technology Inc.

PIC18F2458/2553/4458/4553 5.0 PACKAGING INFORMATION For packaging information, see the “PIC18F2455/ 2550/4455/4550 Data Sheet” (DS39632). © 2009 Microchip Technology Inc. DS39887C-page 37

PIC18F2458/2553/4458/4553 NOTES: DS39887C-page 38 © 2009 Microchip Technology Inc.

PIC18F2458/2553/4458/4553 APPENDIX A: REVISION HISTORY APPENDIX B: DEVICE DIFFERENCES Revision A (May 2007) The differences between the devices listed in this data Original data sheet for the PIC18F2458/2553/4458/ sheet are shown in TableB-1. 4553 devices. Revision B (June 2007) Changes to Figure 4-2: PIC18LF2458/2553/4458/4553 Voltage-Frequency Graph (Industrial). Revision C (October 2009) Removed “Preliminary” marking. TABLE B-1: DEVICE DIFFERENCES Features PIC18F2458 PIC18F2553 PIC18F4458 PIC18F4553 Program Memory (Bytes) 24576 32768 24576 32768 Program Memory (Instructions) 12288 16384 12288 16384 Interrupt Sources 19 19 20 20 I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E Capture/Compare/PWM Modules 2 2 1 1 Enhanced Capture/Compare/ 0 0 1 1 PWM Modules Parallel Communications (SPP) No No Yes Yes 12-Bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels Packages 28-Pin SPDIP 28-Pin SPDIP 40-Pin PDIP 40-Pin PDIP 28-Pin SOIC 28-Pin SOIC 44-Pin TQFP 44-Pin TQFP 44-Pin QFN 44-Pin QFN © 2009 Microchip Technology Inc. DS39887C-page 39

PIC18F2458/2553/4458/4553 APPENDIX C: MIGRATION FROM APPENDIX D: MIGRATION FROM MID-RANGE TO HIGH-END TO ENHANCED DEVICES ENHANCED DEVICES A detailed discussion of the differences between the A detailed discussion of the migration pathway and mid-range MCU devices (i.e., PIC16CXXX) and the differences between the high-end MCU devices (i.e., enhanced devices (i.e., PIC18FXXX) is provided in PIC17CXXX) and the enhanced devices (i.e., AN716, “Migrating Designs from PIC16C74A/74B to PIC18FXXX) is provided in AN726, “PIC17CXXX to PIC18C442”. The changes discussed, while device PIC18CXXX Migration”. specific, are generally applicable to all mid-range to This Application Note is available as Literature Number enhanced device migrations. DS00726. This Application Note is available as Literature Number DS00716. DS39887C-page 40 © 2009 Microchip Technology Inc.

PIC18F2458/2553/4458/4553 INDEX A M A/D .....................................................................................21 Microchip Internet Web Site ...............................................43 A/D Converter Interrupt, Configuring .........................25 Migration from High-End to Enhanced Devices .................40 Acquisition Requirements ..........................................26 Migration from Mid-Range to Enhanced Devices ..............40 ADCON0 Register ......................................................21 P ADCON1 Register ......................................................21 ADCON2 Register ......................................................21 Packaging Information .......................................................37 ADRESH Register ................................................21, 24 Pin Functions ADRESL Register ......................................................21 MCLR/VPP/RE3 .........................................................11 Analog Port Pins, Configuring ....................................28 MCLR/VPP/RE3 .........................................................15 Associated Registers .................................................30 NC/ICCK/ICPGC .......................................................20 Calculating the Minimum Required Acquisition Time .26 NC/ICDT/ICPGD ........................................................20 Configuring the Module ..............................................25 NC/ICPORTS ............................................................20 Conversion Clock (TAD) .............................................27 NC/ICRST/ICVPP .......................................................20 Conversion Status (GO/DONE Bit) ............................24 OSC1/CLKI ..........................................................11, 15 Conversions ...............................................................29 OSC2/CLKO/RA6 ................................................11, 15 Converter Characteristics ..........................................35 RA0/AN0 ..............................................................12, 16 Discharge ...................................................................29 RA1/AN1 ..............................................................12, 16 Operation in Power-Managed Modes ........................28 RA2/AN2/VREF-/CVREF .......................................12, 16 Selecting and Configuring Acquisition Time ..............27 RA3/AN3/VREF+ ..................................................12, 16 Special Event Trigger (CCP) ......................................30 RA4/T0CKI/C1OUT/RCV .....................................12, 16 Use of the CCP2 Trigger ............................................30 RA5/AN4/SS/HLVDIN/C2OUT ............................12, 16 Absolute Maximum Ratings ...............................................33 RB0/AN12/INT0/FLT0/SDI/SDA ..........................13, 17 ADCON0 Register ..............................................................21 RB1/AN10/INT1/SCK/SCL ..................................13, 17 GO/DONE Bit .............................................................24 RB2/AN8/INT2/VMO ............................................13, 17 ADCON1 Register ..............................................................21 RB3/AN9/CCP2/VPO ..........................................13, 17 ADCON2 Register ..............................................................21 RB4/AN11/KBI0 .........................................................13 ADRESH Register ..............................................................21 RB4/AN11/KBI0/CSSPP ............................................17 ADRESL Register ........................................................21, 24 RB5/KBI1/PGM ....................................................13, 17 Analog-to-Digital Converter. See A/D. RB6/KBI2/PGC ....................................................13, 17 RB7/KBI3/PGD ....................................................13, 17 B RC0/T1OSO/T13CKI ...........................................14, 18 Block Diagrams RC1/T1OSI/CCP2/UOE .......................................14, 18 A/D .............................................................................24 RC2/CCP1 .................................................................14 Analog Input Model ....................................................25 RC2/CCP1/P1A .........................................................18 PIC18F2458/2553 ........................................................9 RC4/D-/VM ..........................................................14, 18 PIC18F4458/4553 ......................................................10 RC5/D+/VP ..........................................................14, 18 RC6/TX/CK ..........................................................14, 18 C RC7/RX/DT/SDO .................................................14, 18 Compare (CCP Module) RD0/SPP0 .................................................................19 Special Event Trigger .................................................30 RD1/SPP1 .................................................................19 Customer Change Notification Service ..............................43 RD2/SPP2 .................................................................19 Customer Notification Service ............................................43 RD3/SPP3 .................................................................19 Customer Support ..............................................................43 RD4/SPP4 .................................................................19 RD5/SPP5/P1B .........................................................19 D RD6/SPP6/P1C .........................................................19 Device Differences .............................................................39 RD7/SPP7/P1D .........................................................19 Device ID Registers ...........................................................31 RE0/AN5/CK1SPP ....................................................20 Device Overview ..................................................................7 RE1/AN6/CK2SPP ....................................................20 Other Special Features ................................................7 RE2/AN7/OESPP ......................................................20 E VDD ......................................................................14, 20 VSS ......................................................................14, 20 Electrical Characteristics ....................................................33 VUSB ....................................................................14, 20 Equations Pinout I/O Descriptions A/D Acquisition Time ..................................................26 PIC18F2458/2553 .....................................................11 A/D Minimum Charging Time .....................................26 PIC18F4458/4553 .....................................................15 Errata ...................................................................................6 Power-Managed Modes I and A/D Operation .....................................................28 Internet Address .................................................................43 R Interrupt Sources Reader Response ..............................................................44 A/D Conversion Complete .........................................25 Registers ADCON0 (A/D Control 0) ...........................................21 © 2009 Microchip Technology Inc. DS39887C-page 41

PIC18F2458/2553/4458/4553 ADCON1 (A/D Control 1) ...........................................22 ADCON2 (A/D Control 2) ...........................................23 DEVID1 (Device ID 1) ................................................32 DEVID2 (Device ID 2) ................................................32 Revision History .................................................................39 S Special Features of the CPU ..............................................31 T Timing Diagrams A/D Conversion ..........................................................36 Timing Diagrams and Specifications A/D Conversion Requirements ..................................36 W WWW Address ...................................................................43 WWW, On-Line Support .......................................................6 DS39887C-page 42 © 2009 Microchip Technology Inc.

PIC18F2458/2553/4458/4553 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2009 Microchip Technology Inc. DS39887C-page 43

PIC18F2458/2553/4458/4553 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC18F2458/2553/4458/4553 Literature Number: DS39887C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39887C-page 44 © 2009 Microchip Technology Inc.

PIC18F2458/2553/4458/4553 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC18LF4553-I/P 301 = Industrial temp., PDIP Range package, Extended VDD limits, QTP pattern #301. b) PIC18LF2458-I/SO = Industrial temp., SOIC package, Extended VDD limits. Device PIC18F2458/2553(1), PIC18F4458/4553(1), c) PIC18F4458-I/P = Industrial temp., PDIP PIC18F2458/2553T(2), PIC18F4458/4553T(2); package, normal VDD limits. VDD range 4.2V to 5.5V PIC18LF2458/2553(1), PIC18LF4458/4553(1), PIC18LF2458/2553T(2), PIC18LF4458/4553T(2); VDD range 2.0V to 5.5V Temperature Range I = -40°C to +85°C (Industrial) E = -40°C to +125°C (Extended) Package PT = TQFP (Thin Quad Flatpack) Note1: F = Standard Voltage Range SO = SOIC SP = Skinny PDIP LF = Wide Voltage Range P = PDIP 2: T = In tape and reel TQFP ML = QFN packages only. Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) © 2009 Microchip Technology Inc. DS39887C-page 45

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC18F2553-I/SO PIC18F2553-I/SP PIC18F2553T-I/SO PIC18F4553-I/ML PIC18F4553-I/P PIC18F4553-I/PT PIC18F4553T-I/ML PIC18F4553T-I/PT PIC18LF2553-I/SO PIC18LF2553-I/SP PIC18LF2553T-I/SO PIC18LF4553- I/ML PIC18LF4553-I/P PIC18LF4553-I/PT PIC18LF4553T-I/ML PIC18LF4553T-I/PT PIC18LF4458-I/ML PIC18LF2458T-I/SO PIC18F4458-I/P PIC18LF4458-I/PT PIC18F4458-I/PT PIC18F2458-I/SP PIC18F4458T-I/PT PIC18LF4458T-I/ML PIC18F4458-I/ML PIC18LF2458-I/SO PIC18LF2458-I/SP PIC18F4458T-I/ML PIC18F2458-I/SO PIC18LF4458T-I/PT PIC18F2458T-I/SO PIC18LF4458-I/P