PIC18F8722 Family Data Sheet 64/80-Pin, 1-Mbit, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology © 2008 Microchip Technology Inc. DS39646C

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, rfPIC, SmartShunt and UNI/O are registered MICROCHIP MAKES NO REPRESENTATIONS OR trademarks of Microchip Technology Incorporated in the WARRANTIES OF ANY KIND WHETHER EXPRESS OR U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Linear Active Thermistor, MXDEV, MXLAB, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB suits, or expenses resulting from such use. No licenses are Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, conveyed, implicitly or otherwise, under any Microchip PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, intellectual property rights. PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39646C-page ii © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 64/80-Pin, 1-Mbit, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology Power Management Features: Peripheral Highlights (Continued): • Run: CPU On, Peripherals On • Up to 2 Capture/Compare/PWM (CCP) modules, • Idle: CPU Off, Peripherals On one with Auto-Shutdown (28-pin devices) • Sleep: CPU Off, Peripherals Off • Master Synchronous Serial Port (MSSP) module • Ultra Low 50 nA Input Leakage Supporting 3-Wire SPI (all 4 modes) and I2C™ • Run mode Currents Down to 25 μA Typical Master and Slave modes • Idle mode Currents Down to 6.8μA Typical • Enhanced Addressable USART module: • Sleep mode Current Down to 120nA Typical - Supports RS-485, RS-232 and LIN/J2602 • Timer1 Oscillator: 900nA, 32kHz, 2V - RS-232 operation using internal oscillator block (no external crystal required) • Watchdog Timer: 1.6μA, 2V Typical • 10-Bit, up to 13-Channel Analog-to-Digital (A/D) • Two-Speed Oscillator Start-up Converter module: Flexible Oscillator Structure: - Conversion available during Sleep • Four Crystal modes, up to 40 MHz • Dual Analog Comparators with Input Multiplexing • 4x Phase Lock Loop (PLL) – Available for Crystal • Programmable 16-Level High/Low-Voltage and Internal Oscillators Detection (HLVD) module • Internal Oscillator Block: Special Microcontroller Features: - Fast wake from Sleep and Idle, 1 μs typical • C Compiler Optimized Architecture - Provides a complete range of clock speeds • 100,000 Erase/Write Cycle Enhanced Flash from 31 kHz to 32 MHz when used with PLL Program Memory Typical - User-tunable to compensate for frequency drift • 1,000,000 Erase/Write Cycle Data EEPROM • Secondary oscillator using Timer1 @ 32 kHz Memory Typical • Fail-Safe Clock Monitor: • Flash/Data EEPROM Retention: 100 Years Typical - Allows for safe shutdown if peripheral clock stops • Self-Programmable under Software Control Peripheral Highlights: • Priority Levels for Interrupts • High-Current Sink/Source 25mA/25mA • 8 x 8 Single-Cycle Hardware Multiplier • Three Programmable External Interrupts • Extended Watchdog Timer (WDT): • Four Input Change Interrupts - Programmable period from 4ms to 131s • Enhanced Capture/Compare/PWM (ECCP) • Single-Supply 5V In-Circuit Serial Programming™ module (40/44-pin devices only): (ICSP™) via Two Pins - One, two or four PWM outputs • In-Circuit Debug (ICD) via Two Pins - Programmable dead time • Wide Operating Voltage Range: 2.0V to 5.5V - Auto-shutdown and auto-restart • Programmable Brown-out Reset (BOR) with Software Enable Option Device (FblyaPtserhso)gra#mI nS siMntrgeumlcet-oiWorynosrd ( SbDyRtaAetsMa) MEe(EbmPyoRterOys)M I/O 1(A0c-/hBD)i t (EPCCWCCPMP/) SMPSISPMI2aCs™ter EUSART omparators Timers8/16-Bit xternal Bus C E PIC18F6527 48K 24576 3936 1024 54 12 2/3 2 Y Y 2 2 2/3 N PIC18F6622 64K 32768 3936 1024 54 12 2/3 2 Y Y 2 2 2/3 N PIC18F6627 96K 49152 3936 1024 54 12 2/3 2 Y Y 2 2 2/3 N PIC18F6722 128K 65536 3936 1024 54 12 2/3 2 Y Y 2 2 2/3 N PIC18F8527 48K 24576 3936 1024 70 16 2/3 2 Y Y 2 2 2/3 Y PIC18F8622 64K 32768 3936 1024 70 16 2/3 2 Y Y 2 2 2/3 Y PIC18F8627 96K 49152 3936 1024 70 16 2/3 2 Y Y 2 2 2/3 Y PIC18F8722 128K 65536 3936 1024 70 16 2/3 2 Y Y 2 2 2/3 Y © 2008 Microchip Technology Inc. DS39646C-page 1

PIC18F8722 FAMILY Pin Diagrams 64-Pin TQFP 1)(1)/P2A DO2 DI2/SDA2 CK2/SCL2 S2 B (2 S S S S S/P2 3C 3B 1C 1B CCP SP0 SP1 SP2 SP3 SP4/ SP5/ SP6/ SP7/ C P P P P E P P P P P P P P E2/ E3/ E4/ E5/ E6/ E7/ D0/ DD SS D1/ D2/ D3/ D4/ D5/ D6/ D7/ R R R R R R R V V R R R R R R R 6463 62 61 60 59 58 57 56 55 545352 51 50 49 RE1/WR/P2C 1 48 RB0/INT0 RE0/RD/P2D 2 47 RB1/INT1 RG0/ECCP3/P3A 3 46 RB2/INT2 RG1/TX2/CK2 4 45 RB3/INT3 RG2/RX2/DT2 5 44 RB4/KBI0 RG3/CCP4/P3D 6 43 RB5/KBI1/PGM RG5/MCLR/VPP 7 PIC18F6527 42 RB6/KBI2/PGC RG4/CCP5/P1D 8 PIC18F6622 41 VSS VSS 9 PIC18F6627 40 OSC2/CLKO/RA6 VDD 10 PIC18F6722 39 OSC1/CLKI/RA7 RF7/SS1 11 38 VDD RF6/AN11 12 37 RB7/KBI3/PGD RF5/AN10/CVREF 13 36 RC5/SDO1 RF4/AN9 14 35 RC4/SDI1/SDA1 RF3/AN8 15 34 RC3/SCK1/SCL1 RF2/AN7/C1OUT 16 33 RC2/ECCP1/P1A 17 18 1920 21 2223 24 25 26 27 28 29 30 31 32 RF1/AN6/C2OUT RF0/AN5 AVDD AVSS RA3/AN3/V+REF RA2/AN2/V-REF RA1/AN1 RA0/AN0 VSS VDD RA5/AN4/HLVDIN RA4/T0CKI(1)(1)SI/ECCP2/P2A C0/T1OSO/T13CKI RC6/TX1/CK1 RC7/RX1/DT1 O R 1 T 1/ C R Note 1: The ECCP2/P2A pin placement is determined by the CCP2MX Configuration bit. DS39646C-page 2 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY Pin Diagrams (Continued) 80-Pin TQFP A17 A16AD10/CS/P2B(2)AD11/P3C(2)AD12/P3B(2)AD13/P1C(2)AD14/P1B(1)(1)AD15/ECCP2/P2A AD0/PSP0 AD1/PSP1 AD2/PSP2 AD3/PSP3 AD4/PSP4/SDO2 AD5/PSP5/SDI2/SDA2 AD6/PSP6/SCK2/SCL2AD7/PSP7/SS2 ALEOE H1/ H0/E2/ E3/ E4/ E5/ E6/ E7/ D0/ DD SS D1/ D2/ D3/ D4/ D5/ D6/D7/ J0/J1/ R RR R R R R R RV V R R R R R RR RR 8079787776757473727170696867666564636261 RH2/A18 1 60 RJ2/WRL RH3/A19 2 59 RJ3/WRH RE1/AD9/WR/P2C 3 58 RB0/INT0 RE0/AD8/RD/P2D 4 57 RB1/INT1 RG0/ECCP3/P3A 5 56 RB2/INT2 RG1/TX2/CK2 6 55 RB3/INT3/ECCP2(1)/P2A(1) RG2/RX2/DT2 7 54 RB4/KBI0 RG3/CCP4/P3D 8 53 RB5/KBI1/PGM RG5/MCLR/VPP 9 PIC18F8527 52 RB6/KBI2/PGC RG4/CCP5/P1D 10 PIC18F8622 51 VSS VSS 11 PIC18F8627 50 OSC2/CLKO/RA6 VDD 12 PIC18F8722 49 OSC1/CLKI/RA7 RF7/SS1 13 48 VDD RF6/AN11 14 47 RB7/KBI3/PGD RF5/AN10/CVREF 15 46 RC5/SDO1 RF4/AN9 16 45 RC4/SDI1/SDA1 RF3/AN8 17 44 RC3/SCK1/SCL1 RF2/AN7/C1OUT 18 43 RC2/ECCP1/P1A RH7/AN15/P1B(2) 19 42 RJ7/UB RH6/AN14/P1C(2) 20 41 RJ6/LB 212223242526272829303132 3334353637383940 (2)RH5/AN13/P3B(2)RH4/AN12/P3C RF1/AN6/C2OUT RF0/AN5 AVDD AVSSRA3/AN3/V+REF RA2/AN2/V-REF RA1/AN1 RA0/AN0VSS VDD RA5/AN4/HLVDIN RA4/T0CKI(1)(1)SI/ECCP2/P2A C0/T1OSO/T13CKI RC6/TX1/CK1RC7/RX1/DT1 RJ4/BA0RJ5/CE O R 1 T 1/ C R Note 1: The ECCP2/P2A pin placement is determined by the CCP2MX Configuration bit and Processor mode settings. 2: P1B, P1C, P3B and P3C pin placement is determined by the ECCPMX Configuration bit. © 2008 Microchip Technology Inc. DS39646C-page 3

PIC18F8722 FAMILY Table of Contents 1.0 Device Overview..........................................................................................................................................................................7 2.0 Oscillator Configurations............................................................................................................................................................31 3.0 Power-Managed Modes.............................................................................................................................................................41 4.0 Reset..........................................................................................................................................................................................49 5.0 Memory Organization.................................................................................................................................................................63 6.0 Flash Program Memory..............................................................................................................................................................87 7.0 External Memory Bus.................................................................................................................................................................97 8.0 Data EEPROM Memory...........................................................................................................................................................111 9.0 8 x 8 Hardware Multiplier..........................................................................................................................................................117 10.0 Interrupts..................................................................................................................................................................................119 11.0 I/O Ports...................................................................................................................................................................................135 12.0 Timer0 Module.........................................................................................................................................................................161 13.0 Timer1 Module.........................................................................................................................................................................165 14.0 Timer2 Module.........................................................................................................................................................................171 15.0 Timer3 Module.........................................................................................................................................................................173 16.0 Timer4 Module.........................................................................................................................................................................177 17.0 Capture/Compare/PWM (CCP) Modules.................................................................................................................................179 18.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................187 19.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................205 20.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART).......................................................................................247 21.0 10-Bit Analog-to-Digital Converter (A/D) Module.....................................................................................................................271 22.0 Comparator Module..................................................................................................................................................................281 23.0 Comparator Voltage Reference Module...................................................................................................................................287 24.0 High/Low-Voltage Detect (HLVD).............................................................................................................................................291 25.0 Special Features of the CPU....................................................................................................................................................297 26.0 Instruction Set Summary..........................................................................................................................................................321 27.0 Development Support...............................................................................................................................................................371 28.0 Electrical Characteristics..........................................................................................................................................................375 29.0 Packaging Information..............................................................................................................................................................419 Appendix A: Revision History.............................................................................................................................................................425 Appendix B: Device Differences.........................................................................................................................................................425 Appendix C: Conversion Considerations...........................................................................................................................................426 Appendix D: Migration From Baseline to Enhanced Devices.............................................................................................................426 Appendix E: Migration From Mid-Range to Enhanced Devices.........................................................................................................427 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................427 Index..................................................................................................................................................................................................429 The Microchip Web Site.....................................................................................................................................................................441 Customer Change Notification Service..............................................................................................................................................441 Customer Support..............................................................................................................................................................................441 Reader Response..............................................................................................................................................................................442 PIC18F8722 Family Product Identification System............................................................................................................................443 DS39646C-page 4 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2008 Microchip Technology Inc. DS39646C-page 5

PIC18F8722 FAMILY NOTES: DS39646C-page 6 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 1.0 DEVICE OVERVIEW 1.1.2 EXPANDED MEMORY This document contains device specific information for The PIC18F8722 family provides ample room for the following devices: application code and includes members with 48, 64, 96or 128Kbytes of code space. • PIC18F6527 • PIC18LF6527 • Data RAM and Data EEPROM: The PIC18F8722 • PIC18F6622 • PIC18LF6622 family also provides plenty of room for application • PIC18F6627 • PIC18LF6627 data. The devices have 3936bytes of data RAM, • PIC18F6722 • PIC18LF6722 as well as 1024bytes of data EEPROM, for long term retention of nonvolatile data. • PIC18F8527 • PIC18LF8527 • Memory Endurance: The Enhanced Flash cells • PIC18F8622 • PIC18LF8622 for both program memory and data EEPROM are • PIC18F8627 • PIC18LF8627 rated to last for many thousands of erase/write • PIC18F8722 • PIC18LF8722 cycles, up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without This family offers the advantages of all PIC18 micro- refresh is conservatively estimated to be greater controllers – namely, high computational performance at than 40 years. an economical price – with the addition of high- endurance, Enhanced Flash program memory. On top of 1.1.3 MULTIPLE OSCILLATOR OPTIONS these features, the PIC18F8722 family introduces AND FEATURES design enhancements that make these microcontrollers All of the devices in the PIC18F8722 family offer ten a logical choice for many high-performance, power different oscillator options, allowing users a wide range sensitive applications. of choices in developing application hardware. These 1.1 New Core Features include: • Four Crystal modes, using crystals or ceramic 1.1.1 nanoWatt TECHNOLOGY resonators All of the devices in the PIC18F8722 family incorporate • Two External Clock modes, offering the option of a range of features that can significantly reduce power using two pins (oscillator input and a divide-by-4 consumption during operation. Key items include: clock output) or one pin (oscillator input, with the • Alternate Run Modes: By clocking the controller second pin reassigned as general I/O) from the Timer1 source or the internal oscillator • Two External RC Oscillator modes with the same block, power consumption during code execution pin options as the External Clock modes can be significantly reduced. • An internal oscillator block which provides an • Multiple Idle Modes: The controller can also run 8MHz clock and an INTRC source (approxi- with its CPU core disabled but the peripherals still mately 31kHz), as well as a range of 6 user active. In these states, power consumption can be selectable clock frequencies, between 125kHz to reduced even further. 4MHz, for a total of 8 clock frequencies. This • On-the-fly Mode Switching: The power- option frees the two oscillator pins for use as managed modes are invoked by user code during additional general purpose I/O. operation, allowing the user to incorporate power- • A Phase Lock Loop (PLL) frequency multiplier, saving ideas into their application’s software available to both the high-speed crystal and inter- design. nal oscillator modes, which allows clock speeds of • Low Consumption in Key Modules: The up to 40MHz. Used with the internal oscillator, the power requirements for both Timer1 and the PLL gives users a complete selection of clock Watchdog Timer are minimized. See speeds, from 31kHz to 32MHz – all without using Section28.0 “Electrical Characteristics” an external crystal or clock circuit. for values. © 2008 Microchip Technology Inc. DS39646C-page 7

PIC18F8722 FAMILY Besides its availability as a clock source, the internal 1.2 Other Special Features oscillator block provides a stable reference source that gives the family additional features for robust operation: • Communications: The PIC18F8722 family incorporates a range of serial communication • Fail-Safe Clock Monitor: This option constantly peripherals, including 2 independent Enhanced monitors the main clock source against a reference USARTs and 2 Master SSP modules capable of signal provided by the internal oscillator. If a clock both SPI and I2C (Master and Slave) modes of failure occurs, the controller is switched to the operation. Also, one of the general purpose I/O internal oscillator block, allowing for continued ports can be reconfigured as an 8-bit Parallel low-speed operation or a safe application shutdown. Slave Port for direct processor-to-processor • Two-Speed Start-up: This option allows the communications. internal oscillator to serve as the clock source • CCP Modules: All devices in the family from Power-on Reset, or wake-up from Sleep incorporate two Capture/Compare/PWM (CCP) mode, until the primary clock source is available. modules and three Enhanced CCP (ECCP) modules to maximize flexibility in control 1.1.4 EXTERNAL MEMORY INTERFACE applications. Up to four different time bases may In the unlikely event that 128Kbytes of program be used to perform several different operations at memory is inadequate for an application, the once. Each of the three ECCP modules offer up to PIC18F8527/8622/8627/8722 members of the family four PWM outputs, allowing for a total of also implement an external memory interface. This 12 PWMs. The ECCPs also offer many beneficial allows the controller’s internal program counter to features, including polarity selection, address a memory space of up to 2Mbytes, Programmable Dead-Time, Auto-Shutdown and permitting a level of data access that few 8-bit devices Restart and Half-Bridge and Full-Bridge can claim. Output modes. With the addition of new operating modes, the external • Self-Programmability: These devices can write memory interface offers many new options, including: to their own program memory spaces under internal software control. By using a bootloader • Operating the microcontroller entirely from routine located in the protected boot block at the external memory top of program memory, it becomes possible to • Using combinations of on-chip and external create an application that can update itself in the memory, up to the 2-Mbyte limit field. • Using external Flash memory for reprogrammable • Extended Instruction Set: The PIC18F8722 application code or large data tables family introduces an optional extension to the • Using external RAM devices for storing large PIC18 instruction set, which adds 8 new instruc- amounts of variable data tions and an Indexed Addressing mode. This extension, enabled as a device configuration 1.1.5 EASY MIGRATION option, has been specifically designed to optimize Regardless of the memory size, all devices share the re-entrant application code originally developed in same rich set of peripherals, allowing for a smooth high-level languages, such as C. migration path as applications grow and evolve. • 10-bit A/D Converter: This module incorporates The consistent pinout scheme used throughout the programmable acquisition time, allowing for a entire family also aids in migrating to the next larger channel to be selected and a conversion to be device. This is true when moving between the 64-pin initiated without waiting for a sampling period and members, between the 80-pin members, or even thus, reduce code overhead. jumping from 64-pin to 80-pin devices. • Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section28.0 “Electrical Characteristics” for time-out periods. DS39646C-page 8 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 1.3 Details on Individual Family All other features for devices in this family are identical. Members These are summarized in Table1-2 and Table1-2. The pinouts for all devices are listed in Table1-3 and Devices in the PIC18F8722 family are available in Table1-4. 64-pin and 80-pin packages. Block diagrams for the two groups are shown in Figure1-1 and Figure1-2. Like all Microchip PIC18 devices, members of the PIC18F8722 family are available as both standard and The devices are differentiated from each other in five low-voltage devices. Standard devices with Enhanced ways: Flash memory, designated with an “F” in the part 1. Flash program memory (48 Kbytes for number (such as PIC18F6627), accommodate an PIC18F6527/8527 devices, 64 Kbytes for operating VDD range of 4.2V to 5.5V. Low-voltage PIC18F6622/8622 devices, 96Kbytes for parts, designated by “LF” (such as PIC18LF6627), PIC18F6627/8627 devices and 128Kbytes for function over an extended VDD range of 2.0V to 5.5V. PIC18F6722/8722). 2. A/D channels (12 for 64-pin devices, 16 for 80-pin devices). 3. I/O ports (7 bidirectional ports on 64-pin devices, 9 bidirectional ports on 80-pin devices). 4. External Memory Bus, configurable for 8 and 16-bit operation, is available on PIC18F8527/ 8622/8627/8722 devices. TABLE 1-1: DEVICE FEATURES (PIC18F6527/6622/6627/6722) Features PIC18F6527 PIC18F6622 PIC18F6627 PIC18F6722 Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz Program Memory (Bytes) 48K 64K 96K 128K Program Memory (Instructions) 24576 32768 49152 65536 Data Memory (Bytes) 3936 3936 3936 3936 Data EEPROM Memory (Bytes) 1024 1024 1024 1024 Interrupt Sources 28 28 28 28 I/O Ports Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G Timers 5 5 5 5 Capture/Compare/PWM 2 2 2 2 Modules Enhanced Capture/Compare/ 3 3 3 3 PWM Modules Enhanced USART 2 2 2 2 Serial Communications MSSP, MSSP, MSSP, MSSP, Enhanced USART Enhanced USART Enhanced USART Enhanced USART Parallel Communications (PSP) Yes Yes Yes Yes 10-bit Analog-to-Digital Module 12 Input Channels 12 Input Channels 12 Input Channels 12 Input Channels Resets (and Delays) POR, BOR, POR, BOR, POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction, Stack Full, Stack Stack Full, Stack Stack Full, Stack Stack Full, Stack Underflow (PWRT, OST), Underflow (PWRT, OST), Underflow (PWRT, OST), Underflow (PWRT, OST), MCLR (optional), WDT MCLR (optional), WDT MCLR (optional), WDT MCLR (optional), WDT Programmable Yes Yes Yes Yes High/Low-Voltage Detect Programmable Brown-out Yes Yes Yes Yes Reset Instruction Set 75 Instructions; 75 Instructions; 75 Instructions; 75 Instructions; 83 with Extended 83 with Extended 83 with Extended 83 with Extended Instruction Set enabled Instruction Set enabled Instruction Set enabled Instruction Set enabled Packages 64-pin TQFP 64-pin TQFP 64-pin TQFP 64-pin TQFP © 2008 Microchip Technology Inc. DS39646C-page 9

PIC18F8722 FAMILY TABLE 1-2: DEVICE FEATURES (PIC18F8527/8622/8627/8722) Features PIC18F8527 PIC18F8622 PIC18F8627 PIC18F8722 Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz Program Memory (Bytes) 48K 64K 96K 128K Program Memory (Instructions) 24576 32768 49152 65536 Data Memory (Bytes) 3936 3936 3936 3936 Data EEPROM Memory (Bytes) 1024 1024 1024 1024 Interrupt Sources 29 29 29 29 I/O Ports Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, F, G, H, J F, G, H, J F, G, H, J F, G, H, J Timers 5 5 5 5 Capture/Compare/PWM 2 2 2 2 Modules Enhanced Capture/Compare/ 3 3 3 3 PWM Modules Enhanced USART 2 2 2 2 Serial Communications MSSP, MSSP, MSSP, MSSP, Enhanced USART Enhanced USART Enhanced USART Enhanced USART Parallel Communications Yes Yes Yes Yes (PSP) 10-bit Analog-to-Digital Module 16 Input Channels 16 Input Channels 16 Input Channels 16 Input Channels Resets (and Delays) POR, BOR, POR, BOR, POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction, Stack Full, Stack Stack Full, Stack Stack Full, Stack Stack Full, Stack Underflow (PWRT, OST), Underflow (PWRT, OST), Underflow (PWRT, OST), Underflow (PWRT, OST), MCLR (optional), WDT MCLR (optional), WDT MCLR (optional), WDT MCLR (optional), WDT Programmable Yes Yes Yes Yes High/Low-Voltage Detect Programmable Brown-out Yes Yes Yes Yes Reset Instruction Set 75 Instructions; 75 Instructions; 75 Instructions; 75 Instructions; 83 with Extended 83 with Extended 83 with Extended 83 with Extended Instruction Set enabled Instruction Set enabled Instruction Set enabled Instruction Set enabled Packages 80-pin TQFP 80-pin TQFP 80-pin TQFP 80-pin TQFP DS39646C-page 10 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 1-1: PIC18F6527/6622/6627/6722 (64-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> PORTA Data Latch inc/dec logic 8 8 RA0:RA7(1) Data Memory 21 PCLAT U PCLATH (3.9Kbytes) 20 Address Latch PCU PCH PCL Program Counter 12 PORTB Data Address<12> RB0:RB7(1) 31-Level Stack Address Latch 4 12 4 Program Memory STKPTR BSR FSR0 ABcacensks (48/64/96/128 FSR1 Kbytes) FSR2 12 PORTC Data Latch inc/dec RC0:RC7(1) 8 logic Table Latch Address ROM Latch Instruction Bus <16> Decode PORTD IR RD0:RD7(1) 8 Instruction State Machine Decode and Control Signals Control PRODH PRODL PORTE RE0:RE7(1) 8 x 8 Multiply 3 8 OSC1(3) Internal Power-up BITOP W OsBcloillcaktor Timer 8 8 8 OSC2(3) Oscillator T1OSI OIsNcTilRlaCtor StaProt-wuper T-oimner 8 8 RFP0O:RRFT7F(1) Reset 8 MHz ALU<8> T1OSO Oscillator Watchdog Timer 8 Precision MCLR(2) SPirnogglrea-mSumpipnlgy BrRowesne-otut RBeafnedr eGnacpe In-Circuit Fail-Safe PORTG VDD,VSS Debugger Clock Monitor RG0:RG5(1) BOR ADC HLVD 10-bit Timer0 Timer1 Timer2 Timer3 Timer4 Comparators ECCP1 ECCP2 ECCP3 CCP4 CCP5 EUSART1 EUSART2 MSSP1 MSSP2 Note 1: See Table1-3 for I/O port pin descriptions. 2: RG5 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section2.0 “Oscillator Configurations” for additional information. © 2008 Microchip Technology Inc. DS39646C-page 11

PIC18F8722 FAMILY FIGURE 1-2: PIC18F8527/8622/8627/8722 (80-PIN) BLOCK DIAGRAM Data Bus<8> PORTA Table Pointer<21> 8 8 Data Latch RA0:RA7(1) Data Memory inc/dec logic PCLAT U PCLATH (3.9Kbytes) 21 20 Address Latch PCU PCH PCL PORTB Program Counter 12 RB0:RB7(1) Data Address<12> 31-Level Stack s Interface PAr(od4gd8rK/ra6ebm4sy/s 9tMe 6Lse/)1am2tc8ohry STKPTR BSR4 FFFSSSRRR10122 ABcacen4sk1s2 RPCO0:RRTCC7(1) u B Data Latch m ste 8 inloc/gdiecc PORTD Sy Table Latch RD0:RD7(1) Address ROM Latch Decode Instruction Bus <16> PORTE IR RE0:RE7(1) AD15:AD0, A19:A16 (Multiplexed with PORTD, 8 PORTE and PORTH) PORTF PRODH PRODL State Machine IDnestcroudcteio &n RF0:RF7(1) Control Signals Control 8 x 8 Multiply 3 8 BITOP W 8 8 8 PORTG RG0:RG5(1) OSC1(3) Internal Power-up Oscillator Timer 8 8 Block OSC2(3) Oscillator ALU<8> INTRC Start-up Timer PORTH T1OSI Oscillator PoRweesre-ton 8 RH0:RH7(1) 8 MHz T1OSO Oscillator Watchdog Timer Precision MCLR(2) SPirnogglrea-mSumpipnlgy BrRowesne-otut RBeafnedr eGnacpe PORTJ In-Circuit Fail-Safe RJ0:RJ7(1) VDD,VSS Debugger Clock Monitor BOR ADC HLVD 10-bit Timer0 Timer1 Timer2 Timer3 Timer4 Comparators ECCP1 ECCP2 ECCP3 CCP4 CCP5 EUSART1 EUSART2 MSSP1 MSSP2 Note 1: See Table1-4 for I/O port pin descriptions. 2: RG5 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section2.0 “Oscillator Configurations” for additional information. DS39646C-page 12 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type TQFP RG5/MCLR/VPP 7 Master Clear (input) or programming voltage (input). RG5 I ST Digital input. MCLR I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. VPP P Programming voltage input. OSC1/CLKI/RA7 39 Oscillator crystal or external clock input. OSC1 I ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode, CMOS otherwise. CLKI I CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) RA7 I/O TTL General purpose I/O pin. OSC2/CLKO/RA6 40 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power I2C™ = I2C/SMBus input buffer Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared. © 2008 Microchip Technology Inc. DS39646C-page 13

PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTA is a bidirectional I/O port. RA0/AN0 24 RA0 I/O TTL Digital I/O. AN0 I Analog Analog input 0. RA1/AN1 23 RA1 I/O TTL Digital I/O. AN1 I Analog Analog input 1. RA2/AN2/VREF- 22 RA2 I/O TTL Digital I/O. AN2 I Analog Analog input 2. VREF- I Analog A/D reference voltage (low) input. RA3/AN3/VREF+ 21 RA3 I/O TTL Digital I/O. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI 28 RA4 I/O ST Digital I/O. T0CKI I ST Timer0 external clock input. RA5/AN4/HLVDIN 27 RA5 I/O TTL Digital I/O. AN4 I Analog Analog input 4. HLVDIN I Analog High/Low-Voltage Detect input. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power I2C™ = I2C/SMBus input buffer Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared. DS39646C-page 14 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0 48 RB0 I/O TTL Digital I/O. INT0 I ST External interrupt 0. FLT0 I ST PWM Fault input for ECCPx. RB1/INT1 47 RB1 I/O TTL Digital I/O. INT1 I ST External interrupt 1. RB2/INT2 46 RB2 I/O TTL Digital I/O. INT2 I ST External interrupt 2. RB3/INT3 45 RB3 I/O TTL Digital I/O. INT3 I ST External interrupt 3. RB4/KBI0 44 RB4 I/O TTL Digital I/O. KBI0 I TTL Interrupt-on-change pin. RB5/KBI1/PGM 43 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. PGM I/O ST Low-Voltage ICSP™ Programming enable pin. RB6/KBI2/PGC 42 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP programming clock pin. RB7/KBI3/PGD 37 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power I2C™ = I2C/SMBus input buffer Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared. © 2008 Microchip Technology Inc. DS39646C-page 15

PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 30 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/ECCP2/P2A 29 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. ECCP2(1) I/O ST Enhanced Capture 2 input/Compare 2 output/ PWM 2 output. P2A(1) O — ECCP2 PWM output A. RC2/ECCP1/P1A 33 RC2 I/O ST Digital I/O. ECCP1 I/O ST Enhanced Capture 1 input/Compare 1 output/ PWM 1 output. P1A O — ECCP1 PWM output A. RC3/SCK1/SCL1 34 RC3 I/O ST Digital I/O. SCK1 I/O ST Synchronous serial clock input/output for SPI mode. SCL1 I/O ST Synchronous serial clock input/output for I2C™ mode. RC4/SDI1/SDA1 35 RC4 I/O ST Digital I/O. SDI1 I ST SPI data in. SDA1 I/O ST I2C data I/O. RC5/SDO1 36 RC5 I/O ST Digital I/O. SDO1 O — SPI data out. RC6/TX1/CK1 31 RC6 I/O ST Digital I/O. TX1 O — EUSART1 asynchronous transmit. CK1 I/O ST EUSART1 synchronous clock (see related RX1/DT1). RC7/RX1/DT1 32 RC7 I/O ST Digital I/O. RX1 I ST EUSART1 asynchronous receive. DT1 I/O ST EUSART1 synchronous data (see related TX1/CK1). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power I2C™ = I2C/SMBus input buffer Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared. DS39646C-page 16 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTD is a bidirectional I/O port. RD0/PSP0 58 RD0 I/O ST Digital I/O. PSP0 I/O TTL Parallel Slave Port data. RD1/PSP1 55 RD1 I/O ST Digital I/O. PSP1 I/O TTL Parallel Slave Port data. RD2/PSP2 54 RD2 I/O ST Digital I/O. PSP2 I/O TTL Parallel Slave Port data. RD3/PSP3 53 RD3 I/O ST Digital I/O. PSP3 I/O TTL Parallel Slave Port data. RD4/PSP4/SDO2 52 RD4 I/O ST Digital I/O. PSP4 I/O TTL Parallel Slave Port data. SDO2 O — SPI data out. RD5/PSP5/SDI2/SDA2 51 RD5 I/O ST Digital I/O. PSP5 I/O TTL Parallel Slave Port data. SDI2 I ST SPI data in. SDA2 I/O I2C/SMB I2C™ data I/O. RD6/PSP6/SCK2/SCL2 50 RD6 I/O ST Digital I/O. PSP6 I/O TTL Parallel Slave Port data. SCK2 I/O ST Synchronous serial clock input/output for SPI mode. SCL2 I/O I2C/SMB Synchronous serial clock input/output for I2C mode. RD7/PSP7/SS2 49 RD7 I/O ST Digital I/O. PSP7 I/O TTL Parallel Slave Port data. SS2 I TTL SPI slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power I2C™ = I2C/SMBus input buffer Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared. © 2008 Microchip Technology Inc. DS39646C-page 17

PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTE is a bidirectional I/O port. RE0/RD/P2D 2 RE0 I/O ST Digital I/O. RD I TTL Read control for Parallel Slave Port. P2D O — ECCP2 PWM output D. RE1/WR/P2C 1 RE1 I/O ST Digital I/O. WR I TTL Write control for Parallel Slave Port. P2C O — ECCP2 PWM output C. RE2/CS/P2B 64 RE2 I/O ST Digital I/O. CS I TTL Chip select control for Parallel Slave Port. P2B O — ECCP2 PWM output B. RE3/P3C 63 RE3 I/O ST Digital I/O. P3C O — ECCP3 PWM output C. RE4/P3B 62 RE4 I/O ST Digital I/O. P3B O — ECCP3 PWM output B. RE5/P1C 61 RE5 I/O ST Digital I/O. P1C O — ECCP1 PWM output C. RE6/P1B 60 RE6 I/O ST Digital I/O. P1B O — ECCP1 PWM output B. RE7/ECCP2/P2A 59 RE7 I/O ST Digital I/O. ECCP2(2) I/O ST Enhanced Capture 2 input/Compare 2 output/ PWM 2 output. P2A(2) O — ECCP2 PWM output A. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power I2C™ = I2C/SMBus input buffer Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared. DS39646C-page 18 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTF is a bidirectional I/O port. RF0/AN5 18 RF0 I/O ST Digital I/O. AN5 I Analog Analog input 5. RF1/AN6/C2OUT 17 RF1 I/O ST Digital I/O. AN6 I Analog Analog input 6. C2OUT O — Comparator 2 output. RF2/AN7/C1OUT 16 RF2 I/O ST Digital I/O. AN7 I Analog Analog input 7. C1OUT O — Comparator 1 output. RF3/AN8 15 RF3 I/O ST Digital I/O. AN8 I Analog Analog input 8. RF4/AN9 14 RF4 I/O ST Digital I/O. AN9 I Analog Analog input 9. RF5/AN10/CVREF 13 RF5 I/O ST Digital I/O. AN10 I Analog Analog input 10. CVREF O Analog Comparator reference voltage output. RF6/AN11 12 RF6 I/O ST Digital I/O. AN11 I Analog Analog input 11. RF7/SS1 11 RF7 I/O ST Digital I/O. SS1 I TTL SPI slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power I2C™ = I2C/SMBus input buffer Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared. © 2008 Microchip Technology Inc. DS39646C-page 19

PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTG is a bidirectional I/O port. RG0/ECCP3/P3A 3 RG0 I/O ST Digital I/O. ECCP3 I/O ST Enhanced Capture 3 input/Compare 3 output/ PWM 3 output. P3A O — ECCP3 PWM output A. RG1/TX2/CK2 4 RG1 I/O ST Digital I/O. TX2 O — EUSART2 asynchronous transmit. CK2 I/O ST EUSART2 synchronous clock (see related RX2/DT2). RG2/RX2/DT2 5 RG2 I/O ST Digital I/O. RX2 I ST EUSART2 asynchronous receive. DT2 I/O ST EUSART2 synchronous data (see related TX2/CK2). RG3/CCP4/P3D 6 RG3 I/O ST Digital I/O. CCP4 I/O ST Capture 4 input/Compare 4 output/PWM 4 output. P3D O — ECCP3 PWM output D. RG4/CCP5/P1D 8 RG4 I/O ST Digital I/O. CCP5 I/O ST Capture 5 input/Compare 5 output/PWM 5 output. P1D O — ECCP1 PWM output D. RG5 See RG5/MCLR/VPP pin. VSS 9, 25, 41, 56 P — Ground reference for logic and I/O pins. VDD 10, 26, 38, 57 P — Positive supply for logic and I/O pins. AVSS 20 P — Ground reference for analog modules. AVDD 19 P — Positive supply for analog modules. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power I2C™ = I2C/SMBus input buffer Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared. DS39646C-page 20 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type TQFP RG5/MCLR/VPP 9 Master Clear (input) or programming voltage (input). RG5 I ST Digital input. MCLR I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. VPP P Programming voltage input. OSC1/CLKI/RA7 49 Oscillator crystal or external clock input. OSC1 I ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode, CMOS otherwise. CLKI I CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) RA7 I/O TTL General purpose I/O pin. OSC2/CLKO/RA6 50 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power I2C™/SMB = I2C/SMBus input buffer Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Microcontroller mode). 2: Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). © 2008 Microchip Technology Inc. DS39646C-page 21

PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTA is a bidirectional I/O port. RA0/AN0 30 RA0 I/O TTL Digital I/O. AN0 I Analog Analog input 0. RA1/AN1 29 RA1 I/O TTL Digital I/O. AN1 I Analog Analog input 1. RA2/AN2/VREF- 28 RA2 I/O TTL Digital I/O. AN2 I Analog Analog input 2. VREF- I Analog A/D reference voltage (low) input. RA3/AN3/VREF+ 27 RA3 I/O TTL Digital I/O. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI 34 RA4 I/O ST/OD Digital I/O. Open-drain when configured as output. T0CKI I ST Timer0 external clock input. RA5/AN4/HLVDIN 33 RA5 I/O TTL Digital I/O. AN4 I Analog Analog input 4. HLVDIN I Analog High/Low-Voltage Detect input. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power I2C™/SMB = I2C/SMBus input buffer Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Microcontroller mode). 2: Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). DS39646C-page 22 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0 58 RB0 I/O TTL Digital I/O. INT0 I ST External interrupt 0. FLT0 I ST PWM Fault input for ECCPx. RB1/INT1 57 RB1 I/O TTL Digital I/O. INT1 I ST External interrupt 1. RB2/INT2 56 RB2 I/O TTL Digital I/O. INT2 I ST External interrupt 2. RB3/INT3/ECCP2/P2A 55 RB3 I/O TTL Digital I/O. INT3 I ST External interrupt 3. ECCP2(1) O — Enhanced Capture 2 input/Compare 2 output/ PWM 2 output. P2A(1) O — ECCP2 PWM output A. RB4/KBI0 54 RB4 I/O TTL Digital I/O. KBI0 I TTL Interrupt-on-change pin. RB5/KBI1/PGM 53 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. PGM I/O ST Low-Voltage ICSP™ Programming enable pin. RB6/KBI2/PGC 52 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin. RB7/KBI3/PGD 47 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power I2C™/SMB = I2C/SMBus input buffer Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Microcontroller mode). 2: Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). © 2008 Microchip Technology Inc. DS39646C-page 23

PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 36 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/ECCP2/P2A 35 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. ECCP2(2) I/O ST Enhanced Capture 2 input/Compare 2 output/ PWM 2 output. P2A(2) O — ECCP2 PWM output A. RC2/ECCP1/P1A 43 RC2 I/O ST Digital I/O. ECCP1 I/O ST Enhanced Capture 1 input/Compare 1 output/ PWM 1 output. P1A O — ECCP1 PWM output A. RC3/SCK1/SCL1 44 RC3 I/O ST Digital I/O. SCK1 I/O ST Synchronous serial clock input/output for SPI mode. SCL1 I/O ST Synchronous serial clock input/output for I2C™ mode. RC4/SDI1/SDA1 45 RC4 I/O ST Digital I/O. SDI1 I ST SPI data in. SDA1 I/O ST I2C data I/O. RC5/SDO1 46 RC5 I/O ST Digital I/O. SDO1 O — SPI data out. RC6/TX1/CK1 37 RC6 I/O ST Digital I/O. TX1 O — EUSART1 asynchronous transmit. CK1 I/O ST EUSART1 synchronous clock (see related RX1/DT1). RC7/RX1/DT1 38 RC7 I/O ST Digital I/O. RX1 I ST EUSART1 asynchronous receive. DT1 I/O ST EUSART1 synchronous data (see related TX1/CK1). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power I2C™/SMB = I2C/SMBus input buffer Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Microcontroller mode). 2: Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). DS39646C-page 24 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTD is a bidirectional I/O port. RD0/AD0/PSP0 72 RD0 I/O ST Digital I/O. AD0 I/O TTL External memory address/data 0. PSP0 I/O TTL Parallel Slave Port data. RD1/AD1/PSP1 69 RD1 I/O ST Digital I/O. AD1 I/O TTL External memory address/data 1. PSP1 I/O TTL Parallel Slave Port data. RD2/AD2/PSP2 68 RD2 I/O ST Digital I/O. AD2 I/O TTL External memory address/data 2. PSP2 I/O TTL Parallel Slave Port data. RD3/AD3/PSP3 67 RD3 I/O ST Digital I/O. AD3 I/O TTL External memory address/data 3. PSP3 I/O TTL Parallel Slave Port data. RD4/AD4/PSP4/SDO2 66 RD4 I/O ST Digital I/O. AD4 I/O TTL External memory address/data 4. PSP4 I/O TTL Parallel Slave Port data. SDO2 O — SPI data out. RD5/AD5/PSP5/ 65 SDI2/SDA2 RD5 I/O ST Digital I/O. AD5 I/O TTL External memory address/data 5. PSP5 I/O TTL Parallel Slave Port data. SDI2 I ST SPI data in. SDA2 I/O I2C/SMB I2C™ data I/O. RD6/AD6/PSP6/ 64 SCK2/SCL2 RD6 I/O ST Digital I/O. AD6 I/O TTL External memory address/data 6. PSP6 I/O TTL Parallel Slave Port data. SCK2 I/O ST Synchronous serial clock input/output for SPI mode. SCL2 I/O I2C/SMB Synchronous serial clock input/output for I2C mode. RD7/AD7/PSP7/SS2 63 RD7 I/O ST Digital I/O. AD7 I/O TTL External memory address/data 7. PSP7 I/O TTL Parallel Slave Port data. SS2 I TTL SPI slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power I2C™/SMB = I2C/SMBus input buffer Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Microcontroller mode). 2: Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). © 2008 Microchip Technology Inc. DS39646C-page 25

PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTE is a bidirectional I/O port. RE0/AD8/RD/P2D 4 RE0 I/O ST Digital I/O. AD8 I/O TTL External memory address/data 8. RD I TTL Read control for Parallel Slave Port. P2D O — ECCP2 PWM output D. RE1/AD9/WR/P2C 3 RE1 I/O ST Digital I/O. AD9 I/O TTL External memory address/data 9. WR I TTL Write control for Parallel Slave Port. P2C O — ECCP2 PWM output C. RE2/AD10/CS/P2B 78 RE2 I/O ST Digital I/O. AD10 I/O TTL External memory address/data 10. CS I TTL Chip select control for Parallel Slave Port. P2B O — ECCP2 PWM output B. RE3/AD11/P3C 77 RE3 I/O ST Digital I/O. AD11 I/O TTL External memory address/data 11. P3C(4) O — ECCP3 PWM output C. RE4/AD12/P3B 76 RE4 I/O ST Digital I/O. AD12 I/O TTL External memory address/data 12. P3B(4) O — ECCP3 PWM output B. RE5/AD13/P1C 75 RE5 I/O ST Digital I/O. AD13 I/O TTL External memory address/data 13. P1C(4) O — ECCP1 PWM output C. RE6/AD14/P1B 74 RE6 I/O ST Digital I/O. AD14 I/O TTL External memory address/data 14. P1B(4) O — ECCP1 PWM output B. RE7/AD15/ECCP2/P2A 73 RE7 I/O ST Digital I/O. AD15 I/O TTL External memory address/data 15. ECCP2(3) I/O ST Enhanced Capture 2 input/Compare 2 output/ PWM 2 output. P2A(3) O — ECCP2 PWM output A. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power I2C™/SMB = I2C/SMBus input buffer Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Microcontroller mode). 2: Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). DS39646C-page 26 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTF is a bidirectional I/O port. RF0/AN5 24 RF0 I/O ST Digital I/O. AN5 I Analog Analog input 5. RF1/AN6/C2OUT 23 RF1 I/O ST Digital I/O. AN6 I Analog Analog input 6. C2OUT O — Comparator 2 output. RF2/AN7/C1OUT 18 RF2 I/O ST Digital I/O. AN7 I Analog Analog input 7. C1OUT O — Comparator 1 output. RF3/AN8 17 RF3 I/O ST Digital I/O. AN8 I Analog Analog input 8. RF4/AN9 16 RF4 I/O ST Digital I/O. AN9 I Analog Analog input 9. RF5/AN10/CVREF 15 RF5 I/O ST Digital I/O. AN10 I Analog Analog input 10. CVREF O Analog Comparator reference voltage output. RF6/AN11 14 RF6 I/O ST Digital I/O. AN11 I Analog Analog input 11. RF7/SS1 13 RF7 I/O ST Digital I/O. SS1 I TTL SPI slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power I2C™/SMB = I2C/SMBus input buffer Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Microcontroller mode). 2: Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). © 2008 Microchip Technology Inc. DS39646C-page 27

PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTG is a bidirectional I/O port. RG0/ECCP3/P3A 5 RG0 I/O ST Digital I/O. ECCP3 I/O ST Enhanced Capture 3 input/Compare 3 output/ PWM 3 output. P3A O — ECCP3 PWM output A. RG1/TX2/CK2 6 RG1 I/O ST Digital I/O. TX2 O — EUSART2 asynchronous transmit. CK2 I/O ST EUSART2 synchronous clock (see related RX2/DT2). RG2/RX2/DT2 7 RG2 I/O ST Digital I/O. RX2 I ST EUSART2 asynchronous receive. DT2 I/O ST EUSART2 synchronous data (see related TX2/CK2). RG3/CCP4/P3D 8 RG3 I/O ST Digital I/O. CCP4 I/O ST Capture 4 input/Compare 4 output/PWM 4 output. P3D O — ECCP3 PWM output D. RG4/CCP5/P1D 10 RG4 I/O ST Digital I/O. CCP5 I/O ST Capture 5 input/Compare 5 output/PWM 5 output. P1D O — ECCP1 PWM output D. RG5 See RG5/MCLR/VPP pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power I2C™/SMB = I2C/SMBus input buffer Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Microcontroller mode). 2: Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). DS39646C-page 28 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTH is a bidirectional I/O port. RH0/A16 79 RH0 I/O ST Digital I/O. A16 I/O TTL External memory address/data 16. RH1/A17 80 RH1 I/O ST Digital I/O. A17 I/O TTL External memory address/data 17. RH2/A18 1 RH2 I/O ST Digital I/O. A18 I/O TTL External memory address/data 18. RH3/A19 2 RH3 I/O ST Digital I/O. A19 I/O TTL External memory address/data 19. RH4/AN12/P3C 22 RH4 I/O ST Digital I/O. AN12 I Analog Analog input 12. P3C(5) O — ECCP3 PWM output C. RH5/AN13/P3B 21 RH5 I/O ST Digital I/O. AN13 I Analog Analog input 13. P3B(5) O — ECCP3 PWM output B. RH6/AN14/P1C 20 RH6 I/O ST Digital I/O. AN14 I Analog Analog input 14. P1C(5) O — ECCP1 PWM output C. RH7/AN15/P1B 19 RH7 I/O ST Digital I/O. AN15 I Analog Analog input 15. P1B(5) O — ECCP1 PWM output B. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power I2C™/SMB = I2C/SMBus input buffer Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Microcontroller mode). 2: Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). © 2008 Microchip Technology Inc. DS39646C-page 29

PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTJ is a bidirectional I/O port. RJ0/ALE 62 RJ0 I/O ST Digital I/O. ALE O — External memory address latch enable. RJ1/OE 61 RJ1 I/O ST Digital I/O. OE O — External memory output enable. RJ2/WRL 60 RJ2 I/O ST Digital I/O. WRL O — External memory write low control. RJ3/WRH 59 RJ3 I/O ST Digital I/O. WRH O — External memory write high control. RJ4/BA0 39 RJ4 I/O ST Digital I/O. BA0 O — External memory byte address 0 control. RJ5/CE 40 RJ4 I/O ST Digital I/O CE O — External memory chip enable control. RJ6/LB 41 RJ6 I/O ST Digital I/O. LB O — External memory low byte control. RJ7/UB 42 RJ7 I/O ST Digital I/O. UB O — External memory high byte control. VSS 11, 31, 51, 70 P — Ground reference for logic and I/O pins. VDD 12, 32, 48, 71 P — Positive supply for logic and I/O pins. AVSS 26 P — Ground reference for analog modules. AVDD 25 P — Positive supply for analog modules. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power I2C™/SMB = I2C/SMBus input buffer Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Microcontroller mode). 2: Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). DS39646C-page 30 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 2.0 OSCILLATOR FIGURE 2-1: CRYSTAL/CERAMIC CONFIGURATIONS RESONATOR OPERATION (XT, LP, HS OR HSPLL 2.1 Oscillator Types CONFIGURATION) The PIC18F8722 family of devices can be operated in C1(1) OSC1 ten different oscillator modes. The user can program the To Configuration bits, FOSC<3:0>, in Configuration Internal Register 1H to select one of these ten modes: XTAL (3) Logic RF 1. LP Low-Power Crystal Sleep 2. XT Crystal/Resonator RS(2) 3. HS High-Speed Crystal/Resonator C2(1) OSC2 PIC18FXXXX 4. HSPLL High-Speed Crystal/Resonator with PLL enabled Note 1: See Table2-1 and Table2-2 for initial values of 5. RC External Resistor/Capacitor with C1 and C2. FOSC/4 output on RA6 2: A series resistor (RS) may be required for AT strip cut crystals. 6. RCIO External Resistor/Capacitor with I/O on RA6 3: RF varies with the oscillator mode chosen. 7. INTIO1 Internal Oscillator with FOSC/4 output on RA6 and I/O on RA7 TABLE 2-1: CAPACITOR SELECTION FOR 8. INTIO2 Internal Oscillator with I/O on RA6 CERAMIC RESONATORS and RA7 9. EC External Clock with FOSC/4 output Typical Capacitor Values Used: 10. ECIO External Clock with I/O on RA6 Mode Freq OSC1 OSC2 XT 3.58 MHz 22 pF 22 pF 2.2 Crystal Oscillator/Ceramic Resonators Capacitor values are for design guidance only. Different capacitor values may be required to produce In XT, LP, HS or HSPLL Oscillator modes, a crystal or acceptable oscillator operation. The user should test ceramic resonator is connected to the OSC1 and the performance of the oscillator over the expected OSC2 pins to establish oscillation. Figure2-1 shows VDD and temperature range for the application. Refer the pin connections. to the following application notes for oscillator specific The oscillator design requires the use of a parallel cut information: crystal. • AN588 – PIC® Microcontroller Oscillator Design Note: Use of a series cut crystal may give a Guide frequency out of the crystal manufacturer’s • AN826 – Crystal Oscillator Basics and Crystal specifications. Selection for rfPIC® and PIC® Devices • AN849 – Basic PIC® Oscillator Design • AN943 – Practical PIC® Oscillator Analysis and Design • AN949 – Making Your Oscillator Work See the notes following Table2-2 for additional information. Note: When using resonators with frequencies above 3.5 MHz, the use of HS mode, rather than XT mode, is recommended. HS mode may be used at any VDD for which the controller is rated. If HS is selected, it is possible that the gain of the oscillator will overdrive the resonator. Therefore, a series resistor may be placed between the OSC2 pin and the resonator. As a good starting point, the recommended value of RS is 330Ω. © 2008 Microchip Technology Inc. DS39646C-page 31

PIC18F8722 FAMILY TABLE 2-2: CAPACITOR SELECTION FOR An external clock source may also be connected to the QUARTZ CRYSTALS OSC1 pin in the HS mode, as shown in Figure2-2. When operated in this mode, parameters D033 and Typical Capacitor Values D043 apply. Crystal Tested: Osc Type Freq C1 C2 FIGURE 2-2: EXTERNAL CLOCK INPUT OPERATION (HS OSC LP 32 kHz 22 pF 22 pF CONFIGURATION) XT 1 MHz 22 pF 22 pF 4 MHz 22 pF 22 pF HS 4 MHz 22 pF 22 pF Clock from OSC1 10 MHz 22 pF 22 pF Ext. System PIC18FXXXX 20 MHz 22 pF 22 pF Open OSC2 (HS Mode) 25 MHz 22 pF 22 pF Capacitor values are for design guidance only. Different capacitor values may be required to produce 2.3 External Clock Input acceptable oscillator operation. The user should test the performance of the oscillator over the expected The EC and ECIO Oscillator modes require an external VDD and temperature range for the application. Refer clock source to be connected to the OSC1 pin. There is to the following application notes for oscillator specific no oscillator start-up time required after a Power-on information: Reset or after an exit from Sleep mode. • AN588 – PIC® Microcontroller Oscillator Design In the EC Oscillator mode, the oscillator frequency Guide divided by 4 is available on the OSC2 pin. This signal • AN826 – Crystal Oscillator Basics and Crystal may be used for test purposes or to synchronize other Selection for rfPIC® and PIC® Devices logic. Figure2-3 shows the pin connections for the EC • AN849 – Basic PIC® Oscillator Design Oscillator mode. • AN943 – Practical PIC® Oscillator Analysis and Design FIGURE 2-3: EXTERNAL CLOCK • AN949 – Making Your Oscillator Work INPUT OPERATION (EC CONFIGURATION) See the notes following this table for additional information. Clock from OSC1/CLKI Ext. System PIC18FXXXX Note1: Higher capacitance increases the stability FOSC/4 OSC2/CLKO of the oscillator but also increases the start-up time. 2: When operating below 3V VDD, or when The ECIO Oscillator mode functions like the EC mode, using certain ceramic resonators at any except that the OSC2 pin becomes an additional voltage, it may be necessary to use the general purpose I/O pin. The I/O pin becomes bit 6 of HS mode or switch to a crystal oscillator. PORTA (RA6). Figure2-4 shows the pin connections for the ECIO Oscillator mode. When operated in this 3: Since each resonator/crystal has its own mode, parameters D033A and D043A apply. characteristics, the user should consult the resonator/crystal manufacturer for FIGURE 2-4: EXTERNAL CLOCK appropriate values of external INPUT OPERATION components. (ECIO CONFIGURATION) 4: Rs may be required to avoid overdriving crystals with low drive level specification. 5: Always verify oscillator performance over Clock from OSC1/CLKI the VDD and temperature range that is Ext. System PIC18FXXXX expected for the application. RA6 I/O (OSC2) DS39646C-page 32 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 2.4 RC Oscillator 2.5 PLL Frequency Multiplier For timing insensitive applications, the RC and RCIO A Phase Locked Loop (PLL) circuit is provided as an Oscillator modes offer additional cost savings. The option for users who wish to use a lower frequency actual oscillator frequency is a function of several oscillator circuit or to clock the device up to its highest factors: rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due • supply voltage to high-frequency crystals or users who require higher • values of the external resistor (REXT) and clock speeds from an internal oscillator. capacitor (CEXT) • operating temperature 2.5.1 HSPLL OSCILLATOR MODE Given the same device, operating voltage and tempera- The HSPLL mode makes use of the HS mode oscillator ture and component values, there will also be unit-to-unit for frequencies up to 10 MHz. A PLL then multiplies the frequency variations. These are due to factors such as: oscillator output frequency by 4 to produce an internal • normal manufacturing variation clock frequency up to 40 MHz. The PLLEN bit is not • difference in lead frame capacitance between available when this mode is configured as the primary package types (especially for low CEXT values) clock source. • variations within the tolerance of limits of REXT The PLL is only available to the crystal oscillator when and CEXT the FOSC<3:0> Configuration bits are programmed for In the RC Oscillator mode, the oscillator frequency HSPLL mode (= 0110). divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other FIGURE 2-7: HSPLL BLOCK DIAGRAM logic. Figure2-5 shows how the R/C combination is connected. HS Oscillator Enable PLL Enable (from Configuration Register 1H) FIGURE 2-5: RC OSCILLATOR MODE VDD OSC2 Phase REXT HS Mode FIN Comparator OSC1 Internal OSC1 Crystal FOUT Clock Osc CEXT Loop PIC18FXXXX Filter VSS OSC2/CLKO FOSC/4 Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ ÷4 VCO SYSCLK 20 pF ≤ CEXT ≤ 300 pF UX M The RCIO Oscillator mode (Figure2-6) functions like the RC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). 2.5.2 PLL AND INTOSC The PLL is also available to the internal oscillator block FIGURE 2-6: RCIO OSCILLATOR MODE when the internal oscillator block is configured as the VDD primary clock source. In this configuration, the PLL is enabled in software and generates a clock output of up REXT to 32MHz. The operation of INTOSC with the PLL is Internal OSC1 described in Section2.6.4 “PLL in INTOSC Modes”. Clock CEXT PIC18FXXXX VSS RA6 I/O (OSC2) Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ 20 pF ≤ CEXT ≤ 300 pF © 2008 Microchip Technology Inc. DS39646C-page 33

PIC18F8722 FAMILY 2.6 Internal Oscillator Block 2.6.2 INTOSC OUTPUT FREQUENCY The PIC18F8722 family of devices includes an internal The internal oscillator block is calibrated at the factory oscillator block which generates two different clock to produce an INTOSC output frequency of 8MHz. signals; either can be used as the microcontroller’s The INTRC oscillator operates independently of the clock source. This may eliminate the need for external INTOSC source. Any changes in INTOSC across oscillator circuits on the OSC1 and/or OSC2 pins. voltage and temperature are not necessarily reflected The main output (INTOSC) is an 8MHz clock source, by changes in INTRC or vice versa. which can be used to directly drive the device clock. It 2.6.3 OSCTUNE REGISTER also drives a postscaler, which can provide a range of clock frequencies from 31kHz to 4MHz. The INTOSC The INTOSC output has been calibrated at the output is enabled when a clock frequency from 125kHz factory but can be adjusted in the user’s application. to 8MHz is selected. The INTOSC output can also be This is done by writing to TUN<4:0> enabled when 31kHz is selected, depending on the (OSCTUNE<4:0>) in the OSCTUNE register INTSRC bit (OSCTUNE<7>). (Register). The other clock source is the internal RC oscillator When the OSCTUNE register is modified, the INTOSC (INTRC), which provides a nominal 31kHz output. frequency will begin shifting to the new frequency. The INTRC is enabled if it is selected as the device clock INTOSC clock will stabilize within 1ms. Code execu- source; it is also enabled automatically when any of the tion continues during this shift. There is no indication following are enabled: that the shift has occurred. The INTRC is not affected by OSCTUNE. • Power-up Timer • Fail-Safe Clock Monitor The OSCTUNE register also implements the INTSRC • Watchdog Timer (OSCTUNE<7>) and PLLEN (OSCTUNE<6>) bits, • Two-Speed Start-up which control certain features of the internal oscillator block. The INTSRC bit allows users to select which These features are discussed in greater detail in internal oscillator provides the clock source when the Section25.0 “Special Features of the CPU”. 31kHz frequency option is selected. This is covered in The clock source frequency (INTOSC direct, INTRC greater detail in Section2.7.1 “Oscillator Control direct or INTOSC postscaler) is selected by configuring Register”. the IRCF bits of the OSCCON register (page39). The PLLEN bit controls the operation of the Phase Locked Loop (PLL) in internal oscillator modes (see 2.6.1 INTIO MODES Figure2-10). Using the internal oscillator as the clock source elimi- nates the need for up to two external oscillator pins, FIGURE 2-10: INTOSC AND PLL BLOCK which can then be used for digital I/O. Two distinct DIAGRAM configurations are available: • In INTIO1 mode, the OSC2 pin outputs FOSC/4, 8 or 4 MHz PLLEN while OSC1 functions as RA7 (see Figure2-8) for (OSCTUNE<6>) digital input and output. • In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6 (see Figure2-9), both for Phase digital input and output. FIN Comparator INTOSC FOUT FIGURE 2-8: INTIO1 OSCILLATOR MODE Loop RA7 I/O (OSC1) Filter PIC18FXXXX FOSC/4 OSC2 ÷4 VCO CLKO SYSCLK X FIGURE 2-9: INTIO2 OSCILLATOR MODE U M OSC2 RA7 I/O (OSC1) UX PIC18FXXXX M RA6 I/O (OSC2) RA6 DS39646C-page 34 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 2.6.4 PLL IN INTOSC MODES 2.6.5 INTOSC FREQUENCY DRIFT The 4x Phase Locked Loop (PLL) can be used with the The factory calibrates the internal oscillator block internal oscillator block to produce faster device clock output (INTOSC) for 8MHz. However, this frequency speeds than are normally possible with the internal may drift as VDD or temperature changes and can oscillator sources. When enabled, the PLL produces a affect the controller operation in a variety of ways. It is clock speed of 16 MHz or 32MHz. possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register. Depending on the Unlike HSPLL mode, the PLL is controlled through device, this may have no effect on the INTRC clock software. The control bit, PLLEN (OSCTUNE<6>), is source frequency. used to enable or disable its operation. Tuning the INTOSC source requires knowing when to The PLL is available when the device is configured to make the adjustment, in which direction it should be use the internal oscillator block as its primary clock made and in some cases, how large a change is source (FOSC<3:0> = 1001 or 1000). Additionally, the needed. Three compensation techniques are discussed PLL will only function when the selected output fre- in Section2.6.5.1 “Compensating with the quency is either 4MHz or 8MHz (OSCCON<6:4> = 111 EUSART”, Section2.6.5.2 “Compensating with the or 110). If both of these conditions are not met, the PLL Timers” and Section2.6.5.3 “Compensating with the is disabled and the PLLEN bit remains clear (writes are CCP Module in Capture Mode” but other techniques ignored). may be used. REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN(1) — TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25kHz device clock derived from 8MHz INTOSC source (divide-by-256 enabled) 0 = 31kHz device clock derived directly from INTRC internal oscillator bit 6 PLLEN: Frequency Multiplier PLL for INTOSC Enable bit(1) 1 = PLL enabled for INTOSC (4MHz and 8MHz only) 0 = PLL disabled bit 5 Unimplemented: Read as ‘0’ bit 4-0 TUN<4:0>: Frequency Tuning bits 01111 = Maximum frequency • • • • 00001 00000 = Center frequency. Oscillator module is running at the calibrated frequency. 11111 • • • • 10000 = Minimum frequency Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as ‘0’. See Section2.6.4 “PLL in INTOSC Modes” for details. © 2008 Microchip Technology Inc. DS39646C-page 35

PIC18F8722 FAMILY 2.6.5.1 Compensating with the EUSART 2.6.5.3 Compensating with the CCP Module in Capture Mode An adjustment may be required when the EUSART begins to generate framing errors or receives data with A CCP module can use free running Timer1 (or errors while in Asynchronous mode. Framing errors Timer3), clocked by the internal oscillator block and an indicate that the device clock frequency is too high. To external event with a known period (i.e., AC power adjust for this, decrement the value in OSCTUNE to frequency). The time of the first event is captured in the reduce the clock frequency. On the other hand, errors CCPRxH:CCPRxL registers and is recorded for use in data may suggest that the clock speed is too low. To later. When the second event causes a capture, the compensate, increment OSCTUNE to increase the time of the first event is subtracted from the time of the clock frequency. second event. Since the period of the external event is known, the time difference between events can be 2.6.5.2 Compensating with the Timers calculated. This technique compares device clock speed to some If the measured time is much greater than the reference clock. Two timers may be used; one timer is calculated time, the internal oscillator block is running clocked by the peripheral clock, while the other is too fast. To compensate, decrement the OSCTUNE clocked by a fixed reference source, such as the register. If the measured time is much less than the Timer1 oscillator. calculated time, the internal oscillator block is running Both timers are cleared, but the timer clocked by the too slow. To compensate, increment the OSCTUNE reference generates interrupts. When an interrupt register. occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is much greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. DS39646C-page 36 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 2.7 Clock Sources and Oscillator The secondary oscillators are those external sources Switching not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the The PIC18F8722 family of devices includes a feature controller is placed in a power-managed mode. that allows the device clock source to be switched from The PIC18F8722 family of devices offers the Timer1 the main oscillator to an alternate clock source. These oscillator as a secondary oscillator. This oscillator, in all devices also offer two alternate clock sources. When power-managed modes, is often the time base for an alternate clock source is enabled, the various functions such as a real-time clock. power-managed operating modes are available. Most often, a 32.768kHz watch crystal is connected Essentially, there are three clock sources for these between the RC0/T1OSO/T13CKI and RC1/T1OSI devices: pins. Like the LP mode oscillator circuit, loading • Primary oscillators capacitors are also connected from each pin to ground. • Secondary oscillators The Timer1 oscillator is discussed in greater detail in • Internal oscillator block Section13.3 “Timer1 Oscillator”. The primary oscillators include the External Crystal In addition to being a primary clock source, the internal and Resonator modes, the External RC modes, the oscillator block is available as a power-managed External Clock modes and the internal oscillator block. mode clock source. The INTRC source is also used as The particular mode is defined by the FOSC<3:0> the clock source for several special features, such as Configuration bits. The details of these modes are the WDT and Fail-Safe Clock Monitor. covered earlier in this chapter. The clock sources for the PIC18F8722 family of devices are shown in Figure2-11. See Section25.0 “Special Features of the CPU” for Configuration register details. FIGURE 2-11: PIC18F8722 FAMILY CLOCK DIAGRAM PIC18F6527/6622/6627/6722/8527/8622/8627/8722 Primary Oscillator LP, XT, HS, RC, EC OSC2 Sleep HSPLL, INTOSC/PLL 4 x PLL OSC1 OSCTUNE<6> Secondary Oscillator T1OSC X Peripherals T1OSO U M T1OSCEN Enable T1OSI Oscillator OSCCON<6:4> Internal Oscillator OSCCON<6:4> 8 MHz CPU 111 4 MHz Internal 110 Oscillator 2 MHz IDLEN Block er 1 MHz 101 Clock S8o MurHcze 8 MHz stscal 500 kHz 100101MUX Control INTRC (INTOSC) Po 250 kHz 010 FOSC<3:0> OSCCON< 1:0> Source 125 kHz 001 Clock Source Option 1 31 kHz 31 kHz (INTRC) 000 for other Modules 0 OSCTUNE<7> WDT, PWRT, FSCM and Two-Speed Start-up © 2008 Microchip Technology Inc. DS39646C-page 37

PIC18F8722 FAMILY 2.7.1 OSCILLATOR CONTROL REGISTER the primary clock is providing the device clock in primary clock modes. The IOFS bit indicates when the The OSCCON register (Register2-2) controls several internal oscillator block has stabilized and is providing aspects of the device clock’s operation, both in full the device clock in RC Clock modes. The T1RUN bit power operation and in power-managed modes. (T1CON<6>) indicates when the Timer1 oscillator is The System Clock Select bits, SCS<1:0>, select the providing the device clock in secondary clock modes. clock source. The available clock sources are the In power-managed modes, only one of these three bits primary clock (defined by the FOSC<3:0> Configura- will be set at any time. If none of these bits are set, the tion bits), the secondary clock (Timer1 oscillator) and INTRC is providing the clock or the internal oscillator the internal oscillator block. The clock source changes block has just started and is not yet stable. immediately after either of the SCS<1:0> bits are The IDLEN bit controls whether the device goes into changed, following a brief clock transition interval. The Sleep mode or one of the Idle modes when the SLEEP SCS bits are reset on all forms of Reset. instruction is executed. The Internal Oscillator Frequency Select bits The use of the flag and control bits in the OSCCON (IRCF<2:0>) select the frequency output of the internal register is discussed in more detail in Section3.0 oscillator block to drive the device clock. The choices “Power-Managed Modes”. are the INTRC source (31kHz), the INTOSC source (8MHz) or one of the frequencies derived from the Note1: The Timer1 oscillator must be enabled to INTOSC postscaler (31.25kHz to 4MHz). If the select the secondary clock source. The internal oscillator block is supplying the device clock, Timer1 oscillator is enabled by setting the changing the states of these bits will have an immedi- T1OSCEN bit in the Timer1 Control regis- ate change on the internal oscillator’s output. On ter (T1CON<3>). If the Timer1 oscillator device Resets, the default output frequency of the is not enabled, then any attempt to select internal oscillator block is set at 1MHz. a secondary clock source will be ignored. When a nominal output frequency of 31kHz is selected 2: It is recommended that the Timer1 (IRCF<2:0> = 000), users may choose which internal oscillator be operating and stable before oscillator acts as the source. This is done with the selecting the secondary clock source or a INTSRC bit in the OSCTUNE register (OSCTUNE<7>). very long delay may occur while the Setting this bit selects INTOSC as a 31.25kHz clock Timer1 oscillator starts. source derived from the INTOSC postscaler. Clearing INTSRC selects INTRC (nominally 31kHz) as the 2.7.2 OSCILLATOR TRANSITIONS clock source and disables the INTOSC to reduce current consumption. The PIC18F8722 family of devices contains circuitry to prevent clock “glitches” when switching between clock This option allows users to select the tunable and more sources. A short pause in the device clock occurs dur- precise INTOSC as a clock source, while maintaining ing the clock switch. The length of this pause is the sum power savings with a very low clock speed. Addition- of two cycles of the old clock source and three to four ally, the INTOSC source will already be stable should a cycles of the new clock source. This formula assumes switch to a higher frequency be needed quickly. that the new clock source is stable. Regardless of the setting of INTSRC, INTRC always remains the clock source for features such as the Clock transitions are discussed in greater detail in Watchdog Timer and the Fail-Safe Clock Monitor. Section3.1.2 “Entering Power-Managed Modes”. The OSTS, IOFS and T1RUN bits indicate which clock source is currently providing the device clock. The OSTS bit indicates that the Oscillator Start-up Timer and PLL Start-up Timer (if enabled) have timed out and DS39646C-page 38 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters an Idle mode when a SLEEP instruction is executed 0 = Device enters Sleep mode when a SLEEP instruction is executed bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits(5) 111 = 8MHz (INTOSC drives clock directly) 110 = 4MHz 101 = 2MHz 100 = 1MHz(3) 011 = 500kHz 010 = 250kHz 001 = 125kHz 000 = 31kHz (from either INTOSC/256 or INTRC directly)(2) bit 3 OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready bit 2 IOFS: INTOSC Frequency Stable bit 1 = INTOSC frequency is stable 0 = INTOSC frequency is not stable bit 1-0 SCS<1:0>: System Clock Select bits(4) 1x = Internal oscillator block 01 = Secondary (Timer1) oscillator 00 = Primary oscillator Note 1: Reset state depends on state of the IESO Configuration bit. 2: Source selected by the INTSRC bit (OSCTUNE<7>), see text. 3: Default output frequency of INTOSC on Reset. 4: Modifying the SCS<1:0> bits will cause an immediate clock source switch. 5: Modifying the IRCF<3:0> bits will cause an immediate clock frequency switch if the internal oscillator is providing the device clocks. © 2008 Microchip Technology Inc. DS39646C-page 39

PIC18F8722 FAMILY 2.8 Effects of Power-Managed Modes 2.9 Power-up Delays on the Various Clock Sources Power-up delays are controlled by two or three timers, When PRI_IDLE mode is selected, the configured so that no external Reset circuitry is required for most oscillator continues to run without interruption. For all applications. The delays ensure that the device is kept other power-managed modes, the oscillator using the in Reset until the device power supply is stable under OSC1 pin is disabled. The OSC1 pin (and OSC2 pin in normal circumstances and the primary clock is operat- crystal oscillator modes) will stop oscillating. ing and stable. For additional information on power-up delays, see Section4.5 “Device Reset Timers”. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and The first timer is the Power-up Timer (PWRT) which providing the device clock. The Timer1 oscillator may provides a fixed delay on power-up (parameter 33, also run in all power-managed modes if required to Table28-12). It is enabled by clearing (= 0) the clock Timer1 or Timer3. PWRTEN Configuration bit (CONFIG2L<0>). In internal oscillator modes (RC_RUN and RC_IDLE), 2.9.1 DELAYS FOR POWER-UP AND the internal oscillator block provides the device clock RETURN TO PRIMARY CLOCK source. The 31kHz INTRC output can be used directly to provide the clock and may be enabled to support The second timer is the Oscillator Start-up Timer various special features, regardless of the power- (OST), intended to delay execution until the crystal managed mode (see Section25.2 “Watchdog Timer oscillator is stable (LP, XT and HS modes). The OST (WDT)” and Section25.4 “Fail-Safe Clock Monitor” does this by counting 1024 oscillator cycles before for more information). The INTOSC output at 8MHz allowing the oscillator to clock the device. may be used directly to clock the device or may be When the HSPLL Oscillator mode is selected, a third divided down by the postscaler. The INTOSC output is timer delays execution for an additional 2ms following disabled if the clock is provided directly from the INTRC the HS mode OST delay, so the PLL can lock to the output. The INTOSC output is also enabled for Two- incoming clock frequency. At the end of these delays, Speed Start-up at 1MHz after Resets and when the OSTS bit (OSCCON<3>) is set. configured for wake from Sleep mode. There is a delay of interval TCSD (parameter 38, If the Sleep mode is selected, all clock sources are Table28-12), once execution is allowed to start, when stopped. Since all the transistor switching currents the controller becomes ready to execute instructions. have been stopped, Sleep mode achieves the lowest This delay runs concurrently with any other delays. current consumption of the device (only leakage This may be the only delay that occurs when any of the currents). EC, RC or INTIO modes are used as the primary clock Enabling any on-chip feature that will operate during source. Sleep will increase the current consumed during Sleep. The INTRC is required to support WDT operation. The Timer1 oscillator may be operating to support a real- time clock. Other features may be operating that do not require a device clock source (i.e., SSP slave, PSP, INTx pins and others). Peripherals that may add significant current consumption are listed in Section 28.2“DC Characteristics”. TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin OSC2 Pin RC, INTIO1 Floating, external resistor pulls high At logic low (clock/4 output) RCIO Floating, external resistor pulls high Configured as PORTA, bit 6 INTIO2 Configured as PORTA, bit 7 Configured as PORTA, bit 6 ECIO Floating, driven by external clock Configured as PORTA, bit 6 EC Floating, driven by external clock At logic low (clock/4 output) LP, XT and HS Feedback inverter disabled at quiescent Feedback inverter disabled at quiescent voltage level voltage level Note: See Table4-2 in Section4.0 “Reset” for time-outs due to Sleep and MCLR Reset. DS39646C-page 40 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 3.0 POWER-MANAGED MODES 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three The PIC18F8722 family of devices offers a total of clock sources for power-managed modes. They are: seven operating modes for more efficient power man- agement. These modes provide a variety of options for • the primary clock, as defined by the FOSC<3:0> selective power conservation in applications where Configuration bits resources may be limited (i.e., battery-powered • the secondary clock (the Timer1 oscillator) devices). • the internal oscillator block (for INTOSC modes) There are three categories of power-managed modes: 3.1.2 ENTERING POWER-MANAGED • Run modes MODES • Idle modes Switching from one power-managed mode to another • Sleep mode begins by loading the OSCCON register. The These categories define which portions of the device SCS<1:0> bits select the clock source and determine are clocked and sometimes, what speed. The Run and which Run or Idle mode is to be used. Changing these Idle modes may use any of the three available clock bits causes an immediate switch to the new clock sources (primary, secondary or internal oscillator source, assuming that it is running. The switch may block); the Sleep mode does not use a clock source. also be subject to clock transition delays. These are The power-managed modes include several power- discussed in Section3.1.3 “Clock Transitions and saving features offered on previous PIC® devices. One Status Indicators” and subsequent sections. is the clock switching feature, offered in other PIC18 Entry to the power-managed Idle or Sleep modes is devices, allowing the controller to use the Timer1 oscil- triggered by the execution of a SLEEP instruction. The lator in place of the primary oscillator. Also included is actual mode that results depends on the status of the the Sleep mode, offered by all PIC devices, where all IDLEN bit. device clocks are stopped. Depending on the current mode and the mode being switched to, a change to a power-managed mode does 3.1 Selecting Power-Managed Modes not always require setting all of these bits. Many Selecting a power-managed mode requires two transitions may be done by changing the oscillator select decisions: if the CPU is to be clocked or not and the bits, or changing the IDLEN bit, prior to issuing a SLEEP selection of a clock source. The IDLEN bit instruction. If the IDLEN bit is already configured (OSCCON<7>) controls CPU clocking, while the correctly, it may only be necessary to perform a SLEEP SCS<1:0> bits (OSCCON<1:0>) select the clock instruction to switch to the desired mode. source. The individual modes, bit settings, clock sources and affected modules are summarized in Table3-1. TABLE 3-1: POWER-MANAGED MODES OSCCON Bits Module Clocking Mode Available Clock and Oscillator Source IDLEN<7>(1) SCS<1:0> CPU Peripherals Sleep 0 N/A Off Off None – All clocks are disabled PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC and Internal Oscillator Block(2). This is the normal full power execution mode. SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2) PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC SEC_IDLE 1 01 Off Clocked Secondary – Timer1 Oscillator RC_IDLE 1 1x Off Clocked Internal Oscillator Block(2) Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. © 2008 Microchip Technology Inc. DS39646C-page 41

PIC18F8722 FAMILY 3.1.3 CLOCK TRANSITIONS AND STATUS 3.2 Run Modes INDICATORS In the Run modes, clocks to both the core and The length of the transition between clock sources is peripherals are active. The difference between these the sum of two cycles of the old clock source and three modes is the clock source. to four cycles of the new clock source. This formula assumes that the new clock source is stable. 3.2.1 PRI_RUN MODE Three bits indicate the current clock source and its The PRI_RUN mode is the normal, full power execution status. They are: mode of the microcontroller. This is also the default mode upon a device Reset, unless Two-Speed Start-up • OSTS (OSCCON<3>) is enabled (see Section25.3 “Two-Speed Start-up” • IOFS (OSCCON<2>) for details). In this mode, the OSTS bit is set. The IOFS • T1RUN (T1CON<6>) bit may be set if the internal oscillator block is the In general, only one of these bits will be set while in a primary clock source (see Section2.7.1 “Oscillator given power-managed mode. When the OSTS bit is Control Register”). set, the primary clock is providing the device clock. When the IOFS bit is set, the INTOSC output is 3.2.2 SEC_RUN MODE providing a stable 8MHz clock source to a divider that The SEC_RUN mode is the compatible mode to the actually drives the device clock. When the T1RUN bit is “clock switching” feature offered in other PIC18 set, the Timer1 oscillator is providing the clock. If none devices. In this mode, the CPU and peripherals are of these bits are set, then either the INTRC clock clocked from the Timer1 oscillator. This gives users the source is clocking the device, or the INTOSC source is option of lower power consumption while still using a not yet stable. high accuracy clock source. If the internal oscillator block is configured as the pri- SEC_RUN mode is entered by setting the SCS<1:0> mary clock source by the FOSC<3:0> Configuration bits to ‘01’. The device clock source is switched to the bits, then both the OSTS and IOFS bits may be set Timer1 oscillator (see Figure3-1), the primary oscilla- when in PRI_RUN or PRI_IDLE modes. This indicates tor is shut down, the T1RUN bit (T1CON<6>) is set and that the primary clock (INTOSC output) is generating a the OSTS bit is cleared. stable 8MHz output. Entering another INTOSC power- managed mode at the same frequency would clear the Note: The Timer1 oscillator should already be OSTS bit. running prior to entering SEC_RUN mode. Note1: Caution should be used when modifying a If the T1OSCEN bit is not set when the single IRCF bit. If VDD is less than 3V, it is SCS<1:0> bits are set to ‘01’, entry to possible to select a higher clock speed SEC_RUN mode will not occur. If the than is supported by the low VDD. Timer1 oscillator is enabled, but not yet Improper device operation may result if running, device clocks will be delayed until the VDD/FOSC specifications are violated. the oscillator has started; in such situa- tions, initial oscillator operation is far from 2: Executing a SLEEP instruction does not stable and unpredictable operation may necessarily place the device into Sleep result. mode. It acts as the trigger to place the controller into either the Sleep mode or On transitions from SEC_RUN mode to PRI_RUN, the one of the Idle modes, depending on the peripherals and CPU continue to be clocked from the setting of the IDLEN bit. Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch 3.1.4 MULTIPLE SLEEP COMMANDS back to the primary clock occurs (see Figure3-2). When the clock switch is complete, the T1RUN bit is The power-managed mode that is invoked with the cleared, the OSTS bit is set and the primary clock is SLEEP instruction is determined by the setting of the providing the clock. The IDLEN and SCS bits are not IDLEN bit at the time the instruction is executed. If affected by the wake-up; the Timer1 oscillator another SLEEP instruction is executed, the device will continues to run. enter the power-managed mode specified by IDLEN at that time. If IDLEN has changed, the device will enter the new power-managed mode specified by the new setting. DS39646C-page 42 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI 1 2 3 n-1 n OSC1 Clock Transition(1) CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition(2) CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 Counter SCS1:SCS0 bits Changed OSTS bit Set Note1:TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. 3.2.3 RC_RUN MODE This mode is entered by setting the SCS1 bit to ‘1’. Although it is ignored, it is recommended that the SCS0 In RC_RUN mode, the CPU and peripherals are bit also be cleared; this is to maintain software compat- clocked from the internal oscillator block using the ibility with future devices. When the clock source is INTOSC multiplexer. In this mode, the primary clock is switched to the INTOSC multiplexer (see Figure3-3), shut down. When using the INTRC source, this mode the primary oscillator is shut down and the OSTS bit is provides the best power conservation of all the Run cleared. The IRCF bits may be modified at any time to modes, while still executing code. It works well for user immediately change the clock speed. applications which are not highly timing-sensitive or do not require high-speed clocks at all times. Note: Caution should be used when modifying a If the primary clock source is the internal oscillator single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed block (either INTRC or INTOSC), there are no distin- guishable differences between PRI_RUN and than is supported by the low VDD. Improper device operation may result if RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from the VDD/FOSC specifications are violated. RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. © 2008 Microchip Technology Inc. DS39646C-page 43

PIC18F8722 FAMILY If the IRCF bits and the INTSRC bit are all clear, the On transitions from RC_RUN mode to PRI_RUN mode, INTOSC output is not enabled and the IOFS bit will the device continues to be clocked from the INTOSC remain clear; there will be no indication of the current multiplexer while the primary clock is started. When the clock source. The INTRC source is providing the primary clock becomes ready, a clock switch to the device clocks. primary clock occurs (see Figure3-4). When the clock switch is complete, the IOFS bit is cleared, the OSTS If the IRCF bits are changed from all clear (thus, bit is set and the primary clock is providing the device enabling the INTOSC output) or if INTSRC is set, the clock. The IDLEN and SCS bits are not affected by the IOFS bit becomes set after the INTOSC output switch. The INTRC source will continue to run if either becomes stable. Clocks to the device continue while the WDT or the Fail-Safe Clock Monitor is enabled. the INTOSC source stabilizes after an interval of TIOBST (parameter 39, Table28-12). If the IRCF bits were previously at a non-zero value, or if INTSRC was set before setting SCS1 and the INTOSC source was already stable, the IOFS bit will remain set. FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTRC 1 2 3 n-1 n OSC1 Clock Transition(1) CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. FIGURE 3-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition(2) CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 Counter SCS1:SCS0 bits Changed OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. DS39646C-page 44 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 3.3 Sleep Mode 3.4 Idle Modes The power-managed Sleep mode in the PIC18F8722 The Idle modes allow the controller’s CPU to be family of devices is identical to the legacy Sleep mode selectively shut down while the peripherals continue to offered in all other PIC devices. It is entered by clearing operate. Selecting a particular Idle mode allows users the IDLEN bit (the default state on device Reset) and to further manage power consumption. executing the SLEEP instruction. This shuts down the If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is selected oscillator (Figure3-5). All clock source status executed, the peripherals will be clocked from the clock bits are cleared. source selected using the SCS<1:0> bits; however, the Entering the Sleep mode from any other mode does not CPU will not be clocked. The clock source status bits are require a clock switch. This is because no clocks are not affected. Setting IDLEN and executing a SLEEP needed once the controller has entered Sleep. If the instruction provides a quick method of switching from a WDT is selected, the INTRC source will continue to given Run mode to its corresponding Idle mode. operate. If the Timer1 oscillator is enabled, it will also If the WDT is selected, the INTRC source will continue continue to run. to operate. If the Timer1 oscillator is enabled, it will also When a wake event occurs in Sleep mode (by interrupt, continue to run. Reset or WDT time-out), the device will not be clocked Since the CPU is not executing instructions, the only until the clock source selected by the SCS<1:0> bits exits from any of the Idle modes are by interrupt, WDT becomes ready (see Figure3-6), or it will be clocked time-out or a Reset. When a wake event occurs, CPU from the internal oscillator block if either the Two-Speed execution is delayed by an interval of TCSD Start-up or the Fail-Safe Clock Monitor are enabled (parameter38, Table28-12) while it becomes ready to (see Section25.0 “Special Features of the CPU”). In execute code. When the CPU begins executing code, either case, the OSTS bit is set when the primary clock it resumes with the same clock source for the current is providing the device clocks. The IDLEN and SCS bits Idle mode. For example, when waking from RC_IDLE are not affected by the wake-up. mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS<1:0> bits. FIGURE 3-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC PC + 2 FIGURE 3-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(1) TPLL(1) PLL Clock Output CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 PC + 6 Counter Wake Event OSTS bit Set Note1:TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. © 2008 Microchip Technology Inc. DS39646C-page 45

PIC18F8722 FAMILY 3.4.1 PRI_IDLE MODE 3.4.2 SEC_IDLE MODE This mode is unique among the three low-power Idle In SEC_IDLE mode, the CPU is disabled but the modes, in that it does not disable the primary device peripherals continue to be clocked from the Timer1 clock. For timing sensitive applications, this allows for oscillator. This mode is entered from SEC_RUN by set- the fastest resumption of device operation with its more ting the IDLEN bit and executing a SLEEP instruction. If accurate primary clock source, since the clock source the device is in another Run mode, set the IDLEN bit does not have to “warm-up” or transition from another first, then set the SCS<1:0> bits to ‘01’ and execute oscillator. SLEEP. When the clock source is switched to the Timer1 oscillator, the primary oscillator is shut down, PRI_IDLE mode is entered from PRI_RUN mode by the OSTS bit is cleared and the T1RUN bit is set. setting the IDLEN bit and executing a SLEEP instruc- tion. If the device is in another Run mode, set IDLEN When a wake event occurs, the peripherals continue to first, then clear the SCS bits and execute SLEEP. be clocked from the Timer1 oscillator. After an interval Although the CPU is disabled, the peripherals continue of TCSD following the wake event, the CPU begins exe- to be clocked from the primary clock source specified cuting code being clocked by the Timer1 oscillator. The by the FOSC<3:0> Configuration bits. The OSTS bit IDLEN and SCS bits are not affected by the wake-up; remains set (see Figure3-7). the Timer1 oscillator continues to run (see Figure3-8). When a wake event occurs, the CPU is clocked from the Note: The Timer1 oscillator should already be primary clock source. A delay of interval TCSD running prior to entering SEC_IDLE mode. (parameter 39, Table28-12) is required between the If the T1OSCEN bit is not set when the wake event and when code execution starts. This is SLEEP instruction is executed, the SLEEP required to allow the CPU to become ready to execute instruction will be ignored and entry to instructions. After the wake-up, the OSTS bit remains SEC_IDLE mode will not occur. If the set. The IDLEN and SCS bits are not affected by the Timer1 oscillator is enabled but not yet wake-up (see Figure3-8). running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. FIGURE 3-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Program PC PC + 2 Counter FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 TCSD CPU Clock Peripheral Clock Program PC Counter Wake Event DS39646C-page 46 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 3.4.3 RC_IDLE MODE On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ In RC_IDLE mode, the CPU is disabled but the periph- GIEH bit (INTCON<7>) is set. Otherwise, code execu- erals continue to be clocked from the internal oscillator tion continues or resumes without branching (see block using the INTOSC multiplexer. This mode allows Section10.0 “Interrupts”). for controllable power conservation during Idle periods. A fixed delay of interval TCSD following the wake event From RC_RUN, this mode is entered by setting the is required when leaving Sleep and Idle modes. This IDLEN bit and executing a SLEEP instruction. If the delay is required for the CPU to prepare for execution. device is in another Run mode, first set IDLEN, then set Instruction execution resumes on the first clock cycle the SCS1 bit and execute SLEEP. Although its value is following this delay. ignored, it is recommended that SCS0 also be cleared; this is to maintain software compatibility with future 3.5.2 EXIT BY WDT TIME-OUT devices. The INTOSC multiplexer may be used to select a higher clock frequency by modifying the IRCF A WDT time-out will cause different actions depending bits before executing the SLEEP instruction. When the on which power-managed mode the device is in when clock source is switched to the INTOSC multiplexer, the the time-out occurs. primary oscillator is shut down and the OSTS bit is If the device is not executing code (all Idle modes and cleared. Sleep mode), the time-out will result in an exit from the If the IRCF bits are set to any non-zero value, or the power-managed mode (see Section3.2 “Run INTSRC bit is set, the INTOSC output is enabled. The Modes” and Section3.3 “Sleep Mode”). If the device IOFS bit becomes set, after the INTOSC output is executing code (all Run modes), the time-out will becomes stable, after an interval of TIOBST result in a WDT Reset (see Section25.2 “Watchdog (parameter39, Table28-12). Clocks to the peripherals Timer (WDT)”). continue while the INTOSC source stabilizes. If the The WDT timer and postscaler are cleared by IRCF bits were previously at a non-zero value, or executing a SLEEP or CLRWDT instruction, the loss of a INTSRC was set before the SLEEP instruction was exe- currently selected clock source (if the Fail-Safe Clock cuted and the INTOSC source was already stable, the Monitor is enabled) and modifying the IRCF bits in the IOFS bit will remain set. If the IRCF bits and INTSRC OSCCON register if the internal oscillator block is the are all clear, the INTOSC output will not be enabled, the device clock source. IOFS bit will remain clear and there will be no indication of the current clock source. 3.5.3 EXIT BY RESET When a wake event occurs, the peripherals continue to Normally, the device is held in Reset by the Oscillator be clocked from the INTOSC multiplexer. After a delay Start-up Timer (OST) until the primary clock becomes of TCSD (parameter 38, Table28-12) following the wake ready. At that time, the OSTS bit is set and the device event, the CPU begins executing code being clocked begins executing code. If the internal oscillator block is by the INTOSC multiplexer. The IDLEN and SCS bits the new clock source, the IOFS bit is set instead. are not affected by the wake-up. The INTRC source will The exit delay time from Reset to the start of code continue to run if either the WDT or the Fail-Safe Clock execution depends on both the clock sources before Monitor is enabled. and after the wake-up and the type of oscillator if the new clock source is the primary clock. Exit delays are 3.5 Exiting Idle and Sleep Modes summarized in Table3-2. An exit from Sleep mode or any of the Idle modes is Code execution can begin before the primary clock triggered by an interrupt, a Reset or a WDT time-out. becomes ready. If either the Two-Speed Start-up (see This section discusses the triggers that cause exits Section25.3 “Two-Speed Start-up”) or Fail-Safe from power-managed modes. The clocking subsystem Clock Monitor (see Section25.4 “Fail-Safe Clock actions are discussed in each of the power-managed Monitor”) is enabled, the device may begin execution modes (see Section3.2 “Run Modes”, Section3.3 as soon as the Reset source has cleared. Execution is “Sleep Mode” and Section3.4 “Idle Modes”). clocked by the INTOSC multiplexer driven by the inter- nal oscillator block. Execution is clocked by the internal 3.5.1 EXIT BY INTERRUPT oscillator block until either the primary clock becomes Any of the available interrupt sources can cause the ready or a power-managed mode is entered before the device to exit from an Idle mode or the Sleep mode to primary clock becomes ready; the primary clock is then a Run mode. To enable this functionality, an interrupt shut down. source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. © 2008 Microchip Technology Inc. DS39646C-page 47

PIC18F8722 FAMILY 3.5.4 EXIT WITHOUT AN OSCILLATOR In these instances, the primary clock source either START-UP DELAY does not require an oscillator start-up delay since it is already running (PRI_IDLE), or normally does not Certain exits from power-managed modes do not require an oscillator start-up delay (RC, EC and INTIO invoke the OST at all. There are two cases: Oscillator modes). However, a fixed delay of interval • PRI_IDLE mode, where the primary clock source TCSD following the wake event is still required when is not stopped and leaving Sleep and Idle modes to allow the CPU to • the primary clock source is not any of the LP, XT, prepare for execution. Instruction execution resumes HS or HSPLL modes. on the first clock cycle following this delay. TABLE 3-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Clock Source Clock Source Clock Ready Status Exit Delay before Wake-up after Wake-up Bit (OSCCON) LP, XT, HS Primary Device Clock HSPLL OSTS TCSD(1) (PRI_IDLE mode) EC, RC INTOSC(2) IOFS LP, XT, HS TOST(3) HSPLL TOST + trc(3) OSTS T1OSC or INTRC EC, RC TCSD(1) INTOSC(2) TIOBST(4) IOFS LP, XT, HS TOST(4) INTOSC(2) HSPLL TOST + trc(3) OSTS EC, RC TCSD(1) INTOSC(2) None IOFS LP, XT, HS TOST(3) None HSPLL TOST + trc(3) OSTS (Sleep mode) EC, RC TCSD(1) INTOSC(2) TIOBST(4) IOFS Note 1: TCSD (parameter 38, Table28-12) is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other required delays (see Section3.4 “Idle Modes”). 2: Includes both the INTOSC 8MHz source and postscaler derived frequencies. On Reset, INTOSC defaults to 1 MHz. 3: TOST is the Oscillator Start-up Timer (parameter 32, Table28-12). trc is the PLL Lock-out Timer (parameter F12, Table28-7); it is also designated as TPLL. 4: Execution continues during TIOBST (parameter 39, Table28-12), the INTOSC stabilization period. DS39646C-page 48 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 4.0 RESET A simplified block diagram of the On-Chip Reset Circuit is shown in Figure4-1. The PIC18F8722 family of devices differentiates between various kinds of Reset: 4.1 RCON Register a) Power-on Reset (POR) Device Reset events are tracked through the RCON b) MCLR Reset during normal operation register (Register4-1). The lower five bits of the regis- c) MCLR Reset during power-managed modes ter indicate that a specific Reset event has occurred. In d) Watchdog Timer (WDT) Reset (during most cases, these bits can only be cleared by the event execution) and must be set by the application after the event. The e) Programmable Brown-out Reset (BOR) state of these flag bits, taken together, can be read to f) RESET Instruction indicate the type of Reset that just occurred. This is described in more detail in Section4.6 “Reset State g) Stack Full Reset of Registers”. h) Stack Underflow Reset The RCON register also has control bits for setting This section discusses Resets generated by MCLR, interrupt priority (IPEN) and software control of the POR and BOR and covers the operation of the various BOR (SBOREN). Interrupt priority is discussed in start-up timers. Stack Reset events are covered in Section10.0 “Interrupts”. BOR is covered in Section5.1.3.4 “Stack Full and Underflow Resets”. Section4.4 “Brown-out Reset (BOR)”. WDT Resets are covered in Section25.2 “Watchdog Timer (WDT)”. FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Stack Full/Underflow Reset Pointer External Reset MCLRE MCLR ( )_IDLE Sleep WDT Time-out VDD Rise POR Pulse Detect VDD Brown-out Reset BOREN S OST/PWRT OST 1024 Cycles Chip_Reset 10-bit Ripple Counter R Q OSC1 31 μs PWRT 64 ms INTRC(1) 11-Bit Ripple Counter Enable PWRT Enable OST(2) Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table4-2 for time-out situations. © 2008 Microchip Technology Inc. DS39646C-page 49

PIC18F8722 FAMILY REGISTER 4-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0 IPEN SBOREN — RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit(1) If BOREN<1:0> = 01: 1 = BOR is enabled 0 = BOR is disabled If BOREN<1:0> = 00, 10 or 11: Bit is disabled and read as ‘0’ bit 5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit(2) 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’. 2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this register and Section4.6 “Reset State of Registers” for additional information. Note1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected. 2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after POR). DS39646C-page 50 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 4.2 Master Clear (MCLR) FIGURE 4-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR The MCLR pin provides a method for triggering an SLOW VDD POWER-UP)(1) external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small VDD VDD pulses. The MCLR pin is not driven low by any internal Resets, D R(2) including the WDT. R1(3) MCLR In the PIC18F8722 family of devices, the MCLR input can be disabled with the MCLRE Configuration bit. C PIC18FXXXX When MCLR is disabled, the pin becomes a digital input. See Section11.5 “PORTE, TRISE and LATE Registers” for more information. Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. 4.3 Power-on Reset (POR) The diode D helps discharge the capacitor A Power-on Reset pulse is generated on-chip quickly when VDD powers down. whenever VDD rises above a certain threshold. This 2: R < 40kΩ is recommended to make sure that the voltage drop across R does not violate allows the device to start in the initialized state when the device’s electrical specification. VDD is adequate for operation. 3: R1 ≥ 1 kΩ will limit any current flowing into To take advantage of the POR circuitry, tie the MCLR pin MCLR from external capacitor C, in the event through a resistor (1kΩ to 10kΩ) to VDD. This will of MCLR/VPP pin breakdown, due to eliminate external RC components usually needed to Electrostatic Discharge (ESD) or Electrical create a Power-on Reset delay. A minimum rise rate for Overstress (EOS). VDD is specified (parameter D004, “Section28.2 “DC Characteristics: Power-Down and Supply Current”). For a slow rise time, see Figure4-2. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (volt- age, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. POR events are captured by the POR bit (RCON<1>). The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. © 2008 Microchip Technology Inc. DS39646C-page 51

PIC18F8722 FAMILY 4.4 Brown-out Reset (BOR) Placing the BOR under software control gives the user the additional flexibility of tailoring the application to its The PIC18F8722 family of devices implements a BOR environment without having to reprogram the device to circuit that provides the user with a number of con- change the BOR configuration. It also allows the user figuration and power-saving options. The BOR is to tailor device power consumption in software by controlled by the BORV<1:0> and BOREN<1:0> eliminating the incremental current that the BOR con- Configuration bits. There are a total of four BOR sumes. While the BOR current is typically very small, it configurations which are summarized in Table4-1. may have some impact in low-power applications. The BOR threshold is set by the BORV<1:0> bits. If Note: Even when BOR is under software control, BOR is enabled (any values of BOREN<1:0>, except the BOR Reset voltage level is still set by ‘00’), any drop of VDD below VBOR (parameter D005, the BORV<1:0> Configuration bits. It Section28.1 “DC Characteristics”) for greater than cannot be changed in software. TBOR (parameter 35, Table28-12) will reset the device. A Reset may or may not occur if VDD falls below VBOR 4.4.2 DETECTING BOR for less than TBOR. The chip will remain in Brown-out Reset until VDD rises above VBOR. When BOR is enabled, the BOR bit always resets to ‘0’ on any BOR or POR event. This makes it difficult to If the Power-up Timer is enabled, it will be invoked after determine if a BOR event has occurred just by reading VDD rises above VBOR; it then will keep the chip in the state of BOR alone. A more reliable method is to Reset for an additional time delay, TPWRT simultaneously check the state of both POR and BOR. (parameter33, Table28-12). If VDD drops below VBOR This assumes that the POR bit is reset to ‘1’ in software while the Power-up Timer is running, the chip will go immediately after any POR event. If BOR is ‘0’ while back into a Brown-out Reset and the Power-up Timer POR is ‘1’, it can be reliably assumed that a BOR event will be initialized. Once VDD rises above VBOR, the has occurred. Power-up Timer will execute the additional time delay. BOR and the Power-on Timer (PWRT) are 4.4.3 DISABLING BOR IN SLEEP MODE independently configured. Enabling BOR Reset does When BOREN<1:0> = 10, the BOR remains under not automatically enable the PWRT. hardware control and operates as previously described. Whenever the device enters Sleep mode, 4.4.1 SOFTWARE ENABLED BOR however, the BOR is automatically disabled. When the When BOREN<1:0> = 01, the BOR can be enabled or device returns to any other operating mode, BOR is disabled by the user in software. This is done with the automatically re-enabled. control bit, SBOREN (RCON<6>). Setting SBOREN This mode allows for applications to recover from enables the BOR to function as previously described. brown-out situations, while actively executing code, Clearing SBOREN disables the BOR entirely. The when the device requires BOR protection the most. At SBOREN bit operates only in this mode; otherwise it is the same time, it saves additional power in Sleep mode read as ‘0’. by eliminating the small incremental BOR current. TABLE 4-1: BOR CONFIGURATIONS BOR Configuration Status of SBOREN BOR Operation BOREN1 BOREN0 (RCON<6>) 0 0 Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits. 0 1 Available BOR enabled in software; operation controlled by SBOREN. 1 0 Unavailable BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. 1 1 Unavailable BOR enabled in hardware; must be disabled by reprogramming the Configuration bits. DS39646C-page 52 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 4.5 Device Reset Timers 4.5.3 PLL LOCK TIME-OUT The PIC18F8722 family of devices incorporates three With the PLL enabled in its PLL mode, the time-out separate on-chip timers that help regulate the Power-on sequence following a Power-on Reset is slightly differ- Reset process. Their main function is to ensure that the ent from other oscillator modes. A separate timer is device clock is stable before code is executed. These used to provide a fixed time-out that is sufficient for the timers are: PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the • Power-up Timer (PWRT) oscillator start-up time-out. • Oscillator Start-up Timer (OST) • PLL Lock Time-out 4.5.4 TIME-OUT SEQUENCE On power-up, the time-out sequence is as follows: 4.5.1 POWER-UP TIMER (PWRT) 1. After the POR pulse has cleared, PWRT time-out The Power-up Timer (PWRT) of the PIC18F8722 is invoked (if enabled). family of devices is an 11-bit counter which uses the INTRC source as the clock input. While the PWRT is 2. Then, the OST is activated. counting, the device is held in Reset. The total time-out will vary based on oscillator configu- The power-up time delay depends on the INTRC clock ration and the status of the PWRT. Figure4-3, and will vary from chip-to-chip due to temperature and Figure4-4, Figure4-5, Figure4-6 and Figure4-7 all process variation. See DC parameter 33 in Table28-12 depict time-out sequences on power-up, with the for details. Power-up Timer enabled and the device operating in HS Oscillator mode. Figures4-3 through4-6 also apply The PWRT is enabled by clearing the PWRTEN to devices operating in XT or LP modes. For devices in Configuration bit. RC mode and with the PWRT disabled, on the other hand, there will be no time-out at all. 4.5.2 OSCILLATOR START-UP TIMER (OST) Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire. Bring- The Oscillator Start-up Timer (OST) provides a 1024 ing MCLR high will begin execution immediately oscillator cycle (from OSC1 input) delay after the (Figure4-5). This is useful for testing purposes or to PWRT delay is over (parameter 33, Table28-12). This synchronize more than one PIC18F8722 family device ensures that the crystal oscillator or resonator has operating in parallel. started and stabilized. The OST time-out is invoked only for XT, LP, HS and HSPLL modes and only on Power-on Reset, or on exit from most power-managed modes. TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) and Brown-out Oscillator Exit from Configuration Power-Managed Mode PWRTEN = 0 PWRTEN = 1 HSPLL TPWRT(1) + 1024 TOSC + TPLL(2) 1024 TOSC + TPLL(2) 1024 TOSC + TPLL(2) HS, XT, LP TPWRT(1) + 1024 TOSC 1024 TOSC 1024 TOSC EC, ECIO TPWRT(1) — — RC, RCIO TPWRT(1) — — INTIO1, INTIO2 TPWRT(1) — — Note 1: See parameter 33, Table28-12. 2: 2 ms is the nominal time required for the PLL to lock. © 2008 Microchip Technology Inc. DS39646C-page 53

PIC18F8722 FAMILY FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS39646C-page 54 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-7: TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL ≈ 2ms is the nominal time required for the PLL to lock. © 2008 Microchip Technology Inc. DS39646C-page 55

PIC18F8722 FAMILY 4.6 Reset State of Registers Table4-4 describes the Reset states for all of the Special Function Registers. These are categorized by Most registers are unaffected by a Reset. Their status Power-on and Brown-out Resets, Master Clear and is unknown on POR and unchanged by all other WDT Resets and WDT wake-ups. Resets. All other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal oper- ation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table4-3. These bits are used in software to determine the nature of the Reset. TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER RCON Register STKPTR Register Program Condition Counter SBOREN RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 1 1 1 1 0 0 0 0 RESET Instruction 0000h u(2) 0 u u u u u u Brown-out Reset 0000h u(2) 1 1 1 u 0 u u MCLR during Power-Managed 0000h u(2) u 1 u u u u u Run Modes MCLR during Power-Managed 0000h u(2) u 1 0 u u u u Idle Modes and Sleep Mode WDT Time-out during Full Power 0000h u(2) u 0 u u u u u or Power-Managed Run Mode MCLR during Full Power 0000h u(2) u u u u u u u Execution Stack Full Reset (STVREN = 1) 0000h u(2) u u u u u 1 u Stack Underflow Reset 0000h u(2) u u u u u u 1 (STVREN = 1) Stack Underflow Error (not an 0000h u(2) u u u u u u 1 actual Reset, STVREN = 0) WDT Time-out during PC + 2 u(2) u 0 0 u u u u Power-Managed Idle or Sleep Modes Interrupt Exit from PC + 2(1) u(2) u u 0 u u u u Power-Managed Modes Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (008h or 0018h). 2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled (BOREN<1:0> Configuration bits = 01 and SBOREN = 1). Otherwise, the Reset state is ‘0’. DS39646C-page 56 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets TOSU 6X27 6X22 8X27 8X22 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu(3) TOSL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 6X27 6X22 8X27 8X22 00-0 0000 uu-u uuuu uu-u uuuu(3) PCLATU 6X27 6X22 8X27 8X22 ---0 0000 ---0 0000 ---u uuuu PCLATH 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu PCL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 PC + 2(2) TBLPTRU 6X27 6X22 8X27 8X22 --00 0000 --00 0000 --uu uuuu TBLPTRH 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu TBLPTRL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu TABLAT 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu PRODH 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu PRODL 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu INTCON 6X27 6X22 8X27 8X22 0000 000x 0000 000u uuuu uuuu(1) INTCON2 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu(1) INTCON3 6X27 6X22 8X27 8X22 1100 0000 1100 0000 uuuu uuuu(1) INDF0 6X27 6X22 8X27 8X22 N/A N/A N/A POSTINC0 6X27 6X22 8X27 8X22 N/A N/A N/A POSTDEC0 6X27 6X22 8X27 8X22 N/A N/A N/A PREINC0 6X27 6X22 8X27 8X22 N/A N/A N/A PLUSW0 6X27 6X22 8X27 8X22 N/A N/A N/A FSR0H 6X27 6X22 8X27 8X22 ---- 0000 ---- 0000 ---- uuuu FSR0L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu WREG 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 6X27 6X22 8X27 8X22 N/A N/A N/A POSTINC1 6X27 6X22 8X27 8X22 N/A N/A N/A POSTDEC1 6X27 6X22 8X27 8X22 N/A N/A N/A PREINC1 6X27 6X22 8X27 8X22 N/A N/A N/A PLUSW1 6X27 6X22 8X27 8X22 N/A N/A N/A Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2008 Microchip Technology Inc. DS39646C-page 57

PIC18F8722 FAMILY TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets FSR1H 6X27 6X22 8X27 8X22 ---- 0000 ---- 0000 ---- uuuu FSR1L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu BSR 6X27 6X22 8X27 8X22 ---- 0000 ---- 0000 ---- uuuu INDF2 6X27 6X22 8X27 8X22 N/A N/A N/A POSTINC2 6X27 6X22 8X27 8X22 N/A N/A N/A POSTDEC2 6X27 6X22 8X27 8X22 N/A N/A N/A PREINC2 6X27 6X22 8X27 8X22 N/A N/A N/A PLUSW2 6X27 6X22 8X27 8X22 N/A N/A N/A FSR2H 6X27 6X22 8X27 8X22 ---- 0000 ---- 0000 ---- uuuu FSR2L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu STATUS 6X27 6X22 8X27 8X22 ---x xxxx ---u uuuu ---u uuuu TMR0H 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu TMR0L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu T0CON 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu OSCCON 6X27 6X22 8X27 8X22 0100 q000 0100 q000 uuuu uuqu HLVDCON 6X27 6X22 8X27 8X22 0-00 0101 0-00 0101 u-uu uuuu WDTCON 6X27 6X22 8X27 8X22 ---- ---0 ---- ---0 ---- ---u RCON(4) 6X27 6X22 8X27 8X22 0q-1 11q0 0q-q qquu uq-u qquu TMR1H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 6X27 6X22 8X27 8X22 0000 0000 u0uu uuuu uuuu uuuu TMR2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu PR2 6X27 6X22 8X27 8X22 1111 1111 uuuu uuuu uuuu uuuu T2CON 6X27 6X22 8X27 8X22 -000 0000 -000 0000 -uuu uuuu SSP1BUF 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu SSP1ADD 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu SSP1STAT 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu SSP1CON1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu SSP1CON2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. DS39646C-page 58 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets ADRESH 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 6X27 6X22 8X27 8X22 --00 0000 --00 0000 --uu uuuu ADCON1 6X27 6X22 8X27 8X22 --00 0000 --00 0000 --uu uuuu ADCON2 6X27 6X22 8X27 8X22 0-00 0000 0-00 0000 u-uu uuuu CCPR1H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu CCPR2H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu CCPR3H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu CCPR3L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu CCP3CON 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu ECCP1AS 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu CVRCON 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu CMCON 6X27 6X22 8X27 8X22 0000 0111 0000 0111 uuuu uuuu TMR3H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu T3CON 6X27 6X22 8X27 8X22 0000 0000 uuuu uuuu uuuu uuuu PSPCON 6X27 6X22 8X27 8X22 0000 ---- 0000 ---- uuuu ---- SPBRG1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu RCREG1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu TXREG1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu TXSTA1 6X27 6X22 8X27 8X22 0000 0010 0000 0010 uuuu uuuu RCSTA1 6X27 6X22 8X27 8X22 0000 000x 0000 000x uuuu uuuu EEADRH 6X27 6X22 8X27 8X22 ---- --00 ---- --00 ---- --uu EEADR 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu EEDATA 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu EECON2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 0000 0000 EECON1 6X27 6X22 8X27 8X22 xx-0 x000 uu-0 u000 uu-u uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2008 Microchip Technology Inc. DS39646C-page 59

PIC18F8722 FAMILY TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets IPR3 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu PIR3 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu(1) PIE3 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu IPR2 6X27 6X22 8X27 8X22 11-1 1111 11-1 1111 uu-u uuuu PIR2 6X27 6X22 8X27 8X22 00-0 0000 00-0 0000 uu-u uuuu(1) PIE2 6X27 6X22 8X27 8X22 00-0 0000 00-0 0000 uu-u uuuu IPR1 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu PIR1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu(1) PIE1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu MEMCON 6X27 6X22 8X27 8X22 0-00 --00 0-00 --00 u-uu --uu OSCTUNE 6X27 6X22 8X27 8X22 00-0 0000 00-0 0000 uu-u uuuu TRISJ 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu TRISH 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu TRISG 6X27 6X22 8X27 8X22 ---1 1111 ---1 1111 ---u uuuu TRISF 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu TRISE 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu TRISD 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu TRISC 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu TRISB 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu TRISA(5) 6X27 6X22 8X27 8X22 1111 1111(5) 1111 1111(5) uuuu uuuu(5) LATJ 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu LATH 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu LATG 6X27 6X22 8X27 8X22 --xx xxxx --uu uuuu --uu uuuu LATF 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu LATE 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu LATD 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu LATC 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu LATB 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu LATA(5) 6X27 6X22 8X27 8X22 xxxx xxxx(5) uuuu uuuu(5) uuuu uuuu(5) PORTJ 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu PORTH 6X27 6X22 8X27 8X22 0000 xxxx uuuu uuuu uuuu uuuu PORTG 6X27 6X22 8X27 8X22 --xx xxxx --uu uuuu --uu uuuu PORTF 6X27 6X22 8X27 8X22 x000 0000 u000 0000 uuuu uuuu PORTE 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu PORTD 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu PORTC 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu PORTB 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. DS39646C-page 60 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, Power-on Reset, WDT Reset, Wake-up via WDT Register Applicable Devices Brown-out Reset RESET Instruction, or Interrupt Stack Resets PORTA(5) 6X27 6X22 8X27 8X22 xx0x 0000(5) uu0u 0000(5) uuuu uuuu(5) SPBRGH1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu BAUDCON1 6X27 6X22 8X27 8X22 01-0 0-00 01-0 0-00 uu-u u-uu SPBRGH2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu BAUDCON2 6X27 6X22 8X27 8X22 01-0 0-00 01-0 0-00 uu-u u-uu ECCP1DEL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu TMR4 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu PR4 6X27 6X22 8X27 8X22 1111 1111 uuuu uuuu uuuu uuuu T4CON 6X27 6X22 8X27 8X22 -000 0000 -000 0000 -uuu uuuu CCPR4H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu CCPR4L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu CCP4CON 6X27 6X22 8X27 8X22 --00 0000 --00 0000 --uu uuuu CCPR5H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu CCPR5L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu CCP5CON 6X27 6X22 8X27 8X22 --00 0000 --00 0000 --uu uuuu SPBRG2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu RCREG2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu TXREG2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu TXSTA2 6X27 6X22 8X27 8X22 0000 0010 0000 0010 uuuu uuuu RCSTA2 6X27 6X22 8X27 8X22 0000 000x 0000 000x uuuu uuuu ECCP3AS 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu ECCP3DEL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu ECCP2AS 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu ECCP2DEL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu SSP2BUF 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu SSP2ADD 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu SSP2STAT 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu SSP2CON1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu SSP2CON2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2008 Microchip Technology Inc. DS39646C-page 61

PIC18F8722 FAMILY NOTES: DS39646C-page 62 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 5.0 MEMORY ORGANIZATION 5.1.1 PIC18F8527/8622/8627/8722 PROGRAM MEMORY MODES There are three types of memory in PIC18 Enhanced microcontroller devices: PIC18F8527/8622/8627/8722 devices differ signifi- cantly from their PIC18 predecessors in their utilization • Program Memory of program memory. In addition to available on-chip • Data RAM Flash program memory, these controllers can also • Data EEPROM address up to 2 Mbytes of external program memory As Harvard architecture devices, the data and program through the external memory interface. There are four memories use separate busses; this allows for concur- distinct operating modes available to the controllers: rent access of the two memory spaces. The data • Microprocessor (MP) EEPROM, for practical purposes, can be regarded as • Microprocessor with Boot Block (MPBB) a peripheral device, since it is addressed and accessed • Extended Microcontroller (EMC) through a set of control registers. • Microcontroller (MC) Additional detailed information on the operation of the The program memory mode is determined by setting Flash program memory is provided in Section6.0 the two Least Significant bits of the Configuration “Flash Program Memory”. Data EEPROM is Register 3L (CONFIG3L) as shown in Register25-4 discussed separately in Section8.0 “Data EEPROM (see Section25.1 “Configuration Bits” for additional Memory”. details on the device Configuration bits). 5.1 Program Memory Organization The program memory modes operate as follows: • The Microprocessor Mode permits access only PIC18 microcontrollers implement a 21-bit program to external program memory; the contents of the counter, which is capable of addressing a 2-Mbyte on-chip Flash memory are ignored. The 21-bit program memory space. Accessing a location between program counter permits access to a 2-Mbyte the upper boundary of the physically implemented linear program memory space. memory and the 2-Mbyte address will return all ‘0’s (a • The Microprocessor with Boot Block Mode NOP instruction). accesses on-chip Flash memory from the boot The PIC18F6527 and PIC18F8527 each have 48 Kbytes block. Above this, external program memory is of Flash memory and can store up to 24,576 single-word accessed all the way up to the 2-Mbyte limit. instructions. Program execution automatically switches The PIC18F6622 and PIC18F8622 each have 64 Kbytes between the two memories as required. The boot of Flash memory and can store up to 32,768 single-word block is configurable to 1, 2 or 4 Kbytes. instructions. • The Microcontroller Mode accesses only on-chip Flash memory. Attempts to read above the The PIC18F6627 and PIC18F8627 each have 96Kbytes physical limit of the on-chip Flash (0BFFFh for the of Flash memory and can store up to 49,152 single-word PIC18F8527, 0FFFFh for the PIC18F8622, instructions. 17FFFh for the PIC18F8627, 1FFFFh for the The PIC18F6722 and PIC18F8722 each have PIC18F8722) causes a read of all ‘0’s (a NOP 128Kbytes of Flash memory and can store up to instruction). 65,536 single-word instructions. The Microcontroller mode is also the only operating PIC18 devices have two interrupt vectors. The Reset mode available to PIC18F6527/6622/6627/6722 vector address is at 0000h and the interrupt vector devices. addresses are at 0008h and 0018h. • The Extended Microcontroller Mode allows access to both internal and external program The program memory map for the PIC18F8722 family memories as a single block. The device can of devices is shown in Figure5-1. access its entire on-chip Flash memory; above this, the device accesses external program memory up to the 2-Mbyte program space limit. As with Boot Block mode, execution automatically switches between the two memories as required. In all modes, the microcontroller has complete access to data RAM and EEPROM. Figure5-2 compares the memory maps of the different program memory modes. The differences between on-chip and external memory access limitations are more fully explained in Table5-1. © 2008 Microchip Technology Inc. DS39646C-page 63

PIC18F8722 FAMILY FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F8722 FAMILY DEVICES PC<20:0> CALL,RCALL,RETURN 21 RETFIE,RETLW Stack Level 1 • • • Stack Level 31 Reset Vector 0000h High-Priority Interrupt Vector 0008h Low-Priority Interrupt Vector 0018h On-Chip On-Chip On-Chip On-Chip Program Memory Program Memory Program Memory Program Memory PIC18FX527 PIC18FX622 PIC18FX627 PIC18FX722 0BFFFh 0C000h e c a p S y 0FFFFh mor 10000h Me er s U 017FFFh 018000h Read ‘0’ Read ‘0’ Read ‘0’ 01FFFFh 1FFFFFh TABLE 5-1: MEMORY ACCESS FOR PIC18F8527/8622/8627/8722 PROGRAM MEMORY MODES Internal Program Memory External Program Memory Operating Mode Execution Table Read Execution Table Read Table Write To Table Write To From From From From Microprocessor No Access No Access No Access Yes Yes Yes Microprocessor Yes Yes Yes Yes Yes Yes w/ Boot Block Microcontroller Yes Yes Yes No Access No Access No Access Extended Yes Yes Yes Yes Yes Yes Microcontroller DS39646C-page 64 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 5-2: MEMORY MAPS FOR PIC18F8722 FAMILY PROGRAM MEMORY MODES Microprocessor Extended Microprocessor Microcontroller Mode with Boot Block Mode(5) Microcontroller Mode Mode 000000h 000000h 000000h 000000h On-Chip Program On-Chip On-Chip On-Chip Memory 0007FFh(6) or Program Program Program (No 000FFFh(6) or Memory 0BFFFh(1) Memory 0BFFFh(1) Memory n access) 001FFFh(6) 0FFFFh(2) 0FFFFh(2) xecutio External 000000012800000000hhh(((666))) oorr 00011C7F0FF0FF0FFhh(h1(()34)) 00011CF70FF0FF0FFhh(h1(()34)) pace E PMreomgroarmy External 000121008000000000hhh(((243))) R e‘0a’sds 000121008000000000hhh(((432))) External S Program Program m Memory Memory a gr o Pr 1FFFFFh 1FFFFFh 1FFFFFh 1FFFFFh External On-Chip External On-Chip On-Chip External On-Chip Memory Flash Memory Flash Flash Memory Flash Note 1: PIC18F6527 and PIC18F8527. 2: PIC18F6622 and PIC18F8622. 3: PIC18F6627 and PIC18F8627. 4: PIC18F6722 and PIC18F8722. 5: This is the only mode available on PIC18F6527/6622/6627/6722 devices. 6: Boot block size is determined by the BBSIZ<1:0> bits in CONFIG4L. © 2008 Microchip Technology Inc. DS39646C-page 65

PIC18F8722 FAMILY 5.1.2 PROGRAM COUNTER The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not The Program Counter (PC) specifies the address of the part of either program or data space. The Stack Pointer instruction to fetch for execution. The PC is 21 bits wide is readable and writable and the address on the top of and is contained in three separate 8-bit registers. The the stack is readable and writable through the top-of- low byte, known as the PCL register, is both readable stack Special File Registers. Data can also be pushed and writable. The high byte, or PCH register, contains to, or popped from the stack, using these registers. the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the A CALL type instruction causes a push onto the stack; PCLATH register. The upper byte is called PCU. This the Stack Pointer is first incremented and the location register contains the PC<20:16> bits; it is also not pointed to by the Stack Pointer is written with the directly readable or writable. Updates to the PCU contents of the PC (already pointing to the instruction register are performed through the PCLATU register. following the CALL). A RETURN type instruction causes a POP from the stack; the contents of the location The contents of PCLATH and PCLATU are transferred pointed to by the STKPTR are transferred to the PC to the program counter by any operation that writes and then the Stack Pointer is decremented. PCL. Similarly, the upper two bytes of the program counter are transferred to PCLATH and PCLATU by an The Stack Pointer is initialized to ‘00000’ after all operation that reads PCL. This is useful for computed Resets. There is no RAM associated with the location offsets to the PC (see Section5.1.5.1 “Computed corresponding to a Stack Pointer value of ‘00000’; this GOTO”). is only a Reset value. Status bits indicate if the stack is full or has overflowed or has underflowed. The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word 5.1.3.1 Top-of-Stack Access instructions, the Least Significant bit of PCL is fixed to a value of ‘0’. The PC increments by 2 to address Only the top of the return address stack (TOS) is sequential instructions in the program memory. readable and writable. A set of three registers, TOSU:TOSH:TOSL, hold the contents of the stack loca- The CALL, RCALL, GOTO and program branch tion pointed to by the STKPTR register (Figure5-3). This instructions write to the program counter directly. For allows users to implement a software stack if necessary. these instructions, the contents of PCLATH and After a CALL, RCALL or interrupt, the software can read PCLATU are not transferred to the program counter. the pushed value by reading the TOSU:TOSH:TOSL registers. These values can be placed on a user defined 5.1.3 RETURN ADDRESS STACK software stack. At return time, the software can return The return address stack allows any combination of up these values to TOSU:TOSH:TOSL and do a return. to 31 program calls and interrupts to occur. The PC is The user must disable the global interrupt enable bits pushed onto the stack when a CALL or RCALL instruc- while accessing the stack to prevent inadvertent stack tion is executed or an interrupt is Acknowledged. The corruption. PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. FIGURE 5-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack <20:0> 11111 11110 Top-of-Stack Registers Stack Pointer 11101 TOSU TOSH TOSL STKPTR<4:0> 00h 1Ah 34h 00010 00011 Top-of-Stack 001A34h 00010 000D58h 00001 00000 DS39646C-page 66 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 5.1.3.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next POP will return a value of The STKPTR register (Register5-1) contains the Stack zero to the PC and set the STKUNF bit, while the Stack Pointer value, the STKFUL (Stack Full) status bit and Pointer remains at zero. The STKUNF bit will remain the STKUNF (Stack Underflow) status bits. The value set until cleared by software or until a POR occurs. of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the Note: Returning a value of zero to the PC on an stack and decrements after values are popped off the underflow has the effect of vectoring the stack. On Reset, the Stack Pointer value will be zero. program to the Reset vector, where the The user may read and write the Stack Pointer value. stack conditions can be verified and This feature can be used by a Real-Time Operating appropriate actions can be taken. This is System (RTOS) for return stack maintenance. not the same as a Reset, as the contents of the SFRs are not affected. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a 5.1.3.3 PUSH and POP Instructions POR. Since the Top-of-Stack is readable and writable, the The action that takes place when the stack becomes ability to push values onto the stack and pull values off full depends on the state of the STVREN (Stack Over- the stack without disturbing normal program execution flow Reset Enable) Configuration bit. (Refer to is a desirable feature. The PIC18 instruction set Section25.1 “Configuration Bits” for a description of includes two instructions, PUSH and POP, that permit the device Configuration bits.) If STVREN is set the TOS to be manipulated under software control. (default), the 31st PUSH will push the (PC + 2) value TOSU, TOSH and TOSL can be modified to place data onto the stack, set the STKFUL bit and reset the or a return address on the stack. device. The STKFUL bit will remain set and the Stack The PUSH instruction places the current PC value onto Pointer will be set to zero. the stack. This increments the Stack Pointer and loads If STVREN is cleared, the STKFUL bit will be set on the the current PC value onto the stack. 31st PUSH and the Stack Pointer will increment to 31. The POP instruction discards the current TOS by decre- Any additional pushes will not overwrite the 31st PUSH menting the Stack Pointer. The previous value pushed and STKPTR will remain at 31. onto the stack then becomes the TOS value. REGISTER 5-1: STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP<4:0>: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. © 2008 Microchip Technology Inc. DS39646C-page 67

PIC18F8722 FAMILY 5.1.3.4 Stack Full and Underflow Resets EXAMPLE 5-1: FAST REGISTER STACK CODE EXAMPLE Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in CALL SUB1, FAST ;STATUS, WREG, BSR Configuration Register 4L. When STVREN is set, a full ;SAVED IN FAST REGISTER ;STACK or underflow will set the appropriate STKFUL or • STKUNF bit and then cause a device Reset. When • STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause SUB1 • a device Reset. The STKFUL or STKUNF bits are • cleared by the user software or a Power-on Reset. RETURN, FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK 5.1.4 FAST REGISTER STACK A fast register stack is provided for the STATUS, 5.1.5 LOOK-UP TABLES IN PROGRAM WREG and BSR registers, to provide a “fast return” MEMORY option for interrupts. The stack for each register is only There may be programming situations that require the one level deep and is neither readable nor writable. It is creation of data structures, or look-up tables, in loaded with the current value of the corresponding reg- program memory. For PIC18 devices, look-up tables ister when the processor vectors for an interrupt. All can be implemented in two ways: interrupt sources will push values into the Stack regis- ters. The values in the registers are then loaded back • Computed GOTO into their associated registers if the RETFIE, FAST • Table Reads instruction is used to return from the interrupt. 5.1.5.1 Computed GOTO If both low and high-priority interrupts are enabled, the A computed GOTO is accomplished by adding an offset stack registers cannot be used reliably to return from to the program counter. An example is shown in low-priority interrupts. If a high-priority interrupt occurs Example5-2. while servicing a low-priority interrupt, the Stack regis- ter values stored by the low-priority interrupt will be A look-up table can be formed with an ADDWF PCL overwritten. In these cases, users must save the key instruction and a group of RETLW nn instructions. The W registers in software during a low-priority interrupt. register is loaded with an offset into the table before exe- cuting a call to that table. The first instruction of the called If interrupt priority is not used, all interrupts may use the routine is the ADDWF PCL instruction. The next instruction fast register stack for returns from interrupt. If no inter- executed will be one of the RETLW nn instructions that rupts are used, the fast register stack can be used to returns the value ‘nn’ to the calling function. restore the STATUS, WREG and BSR registers at the end of a subroutine call. To use the fast register stack The offset value (in WREG) specifies the number of for a subroutine call, a CALL label, FAST instruction bytes that the program counter should advance and must be executed to save the STATUS, WREG and should be multiples of 2 (LSb = 0). BSR registers to the fast register stack. A In this method, only one data byte may be stored in RETURN, FAST instruction is then executed to restore each instruction location and room on the return these registers from the fast register stack. address stack is required. Example5-1 shows a source code example that uses Note: The “ADDWF PCL” instruction does not the fast register stack during a subroutine call and return. update the PCLATH and PCLATU registers. A read operation on PCL must be performed to update PCLATH and PCLATU. EXAMPLE 5-2: COMPUTED GOTO USING AN OFFSET VALUE MAIN: ORG 0x0000 MOVLW 0x00 CALL TABLE … ORG 0x8000 TABLE MOVF PCL, F ; A simple read of PCL will update PCLATH, PCLATU RLNCF W, W ; Multiply by 2 to get correct offset in table ADDWF PCL ; Add the modified offset to force jump into table RETLW ‘A’ RETLW ‘B’ RETLW ‘C’ RETLW ‘D’ RETLW ‘E’ END DS39646C-page 68 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 5.1.5.2 Table Reads and Table Writes memory and latched into the instruction register during Q4. The instruction is decoded and executed during the A better method of storing data in program memory following Q1 through Q4. The clocks and instruction allows two bytes of data to be stored in each instruction execution flow are shown in Figure5-4. location. Look-up table data may be stored two bytes per pro- 5.2.2 INSTRUCTION FLOW/PIPELINING gram word by using table reads and writes. The Table An “Instruction Cycle” consists of four Q cycles: Q1 Pointer (TBLPTR) register specifies the byte address through Q4. The instruction fetch and execute are and the Table Latch (TABLAT) register contains the pipelined in such a manner that a fetch takes one data that is read from or written to program memory. instruction cycle, while the decode and execute take Data is transferred to or from program memory one another instruction cycle. However, due to the pipe- byte at a time. lining, each instruction effectively executes in one Table read and table write operations are discussed cycle. If an instruction causes the program counter to further in Section6.1 “Table Reads and Table change (e.g., GOTO), then two cycles are required to Writes”. complete the instruction (Example5-3). A fetch cycle begins with the program counter 5.2 PIC18 Instruction Cycle incrementing in Q1. 5.2.1 CLOCKING SCHEME In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This The microcontroller clock input, whether from an internal instruction is then decoded and executed during the or external source, is internally divided by four to gener- Q2, Q3 and Q4 cycles. Data memory is read during Q2 ate four non-overlapping quadrature clocks (Q1, Q2, Q3 (operand read) and written during Q4 (destination and Q4). Internally, the program counter is incremented write). on every Q1; the instruction is fetched from the program FIGURE 5-4: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Q3 Clock Q4 PC PC PC + 2 PC + 4 OSC2/CLKO (RC mode) Execute INST (PC – 2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 2) Fetch INST (PC + 4) EXAMPLE 5-3: INSTRUCTION PIPELINE FLOW TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP) 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2008 Microchip Technology Inc. DS39646C-page 69

PIC18F8722 FAMILY 5.2.3 INSTRUCTIONS IN PROGRAM The CALL and GOTO instructions have the absolute pro- MEMORY gram memory address embedded into the instruction. Since instructions are always stored on word boundar- The program memory is addressed in bytes. Instruc- ies, the data contained in the instruction is a word tions are stored as two bytes or four bytes in program address. The word address is written to PC<20:1>, memory. The Least Significant Byte of an instruction which accesses the desired byte address in program word is always stored in a program memory location memory. Instruction #2 in Figure5-5 shows how the with an even address (LSb = 0). To maintain alignment instruction GOTO 0006h is encoded in the program with instruction boundaries, the PC increments in steps memory. Program branch instructions, which encode a of 2 and the LSb will always read ‘0’ (see Section5.1.2 relative address offset, operate in the same manner. The “Program Counter”). offset value stored in a branch instruction represents the Figure5-5 shows an example of how instruction words number of single-word instructions that the PC will be are stored in the program memory. offset by. Section26.0 “Instruction Set Summary” provides further details of the instruction set. FIGURE 5-5: INSTRUCTIONS IN PROGRAM MEMORY Word Address LSB = 1 LSB = 0 ↓ Program Memory 000000h Byte Locations → 000002h 000004h 000006h Instruction 1: MOVLW 055h 0Fh 55h 000008h Instruction 2: GOTO 0006h EFh 03h 00000Ah F0h 00h 00000Ch Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh F4h 56h 000010h 000012h 000014h DS39646C-page 70 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 5.2.4 TWO-WORD INSTRUCTIONS the instruction sequence. If the first word is skipped for some reason and the second word is executed by itself, The standard PIC18 instruction set has 8 two-word a NOP is executed instead. This is necessary for cases instructions: CALL, MOVFF, GOTO, LSFR, ADDULNK, when the two-word instruction is preceded by a condi- CALLW, MOVSS and SUBULNK. In all cases, the tional instruction that changes the PC. Example5-4 second word of the instructions always has ‘1111’ as shows how this works. its four Most Significant bits; the other 12 bits are literal data, usually a data memory address. Note: See Section5.6 “PIC18 Instruction Execution and the Extended Instruc- The use of ‘1111’ in the 4 MSbs of an instruction spec- tion Set” for information on two-word ifies a special form of NOP. If the instruction is executed instructions in the extended instruction set. in proper sequence – immediately after the first word – the data in the second word is accessed and used by EXAMPLE 5-4: TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word 1111 0100 0101 0110 ; Execute this word as a NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 ADDWF REG3 ; continue code © 2008 Microchip Technology Inc. DS39646C-page 71

PIC18F8722 FAMILY 5.3 Data Memory Organization 5.3.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient Note: The operation of some aspects of data addressing scheme to make rapid access to any memory are changed when the PIC18 address possible. Ideally, this means that an entire extended instruction set is enabled. See address does not need to be provided for each read or Section5.5 “Data Memory and the write operation. For PIC18 devices, this is accom- Extended Instruction Set” for more plished with a RAM banking scheme. This divides the information. memory space into 16 contiguous banks of 256 bytes. The data memory in PIC18 devices is implemented as Depending on the instruction, each location can be static RAM. Each register in the data memory has a addressed directly by its full 12-bit address, or an 8-bit 12-bit address, allowing up to 4096 bytes of data low-order address and a 4-bit Bank Pointer. memory. The memory space is divided into as many as Most instructions in the PIC18 instruction set make use 16banks that contain 256 bytes each; the PIC18F8722 of the Bank Pointer, known as the Bank Select Register family of devices implements all 16banks. Figure5-6 (BSR). This SFR holds the 4 Most Significant bits of a shows the data memory organization for the location’s address; the instruction itself includes the PIC18F8722 family of devices. 8Least Significant bits. Only the four lower bits of the The data memory contains Special Function Registers BSR are implemented (BSR<3:0>). The upper four bits (SFRs) and General Purpose Registers (GPRs). The are unused; they will always read ‘0’ and cannot be SFRs are used for control and status of the controller written to. The BSR can be loaded directly by using the and peripheral functions, while GPRs are used for data MOVLB instruction. storage and scratchpad operations in the user’s The value of the BSR indicates the bank in data application. Any read of an unimplemented location will memory; the 8 bits in the instruction show the location read as ‘0’s. in the bank and can be thought of as an offset from the The instruction set and architecture allow operations bank’s lower boundary. The relationship between the across all banks. The entire data memory may be BSR’s value and the bank division in data memory is accessed by Direct, Indirect or Indexed Addressing shown in Figure5-7. modes. Addressing modes are discussed later in this Since up to 16 registers may share the same low-order subsection. address, the user must always be careful to ensure that To ensure that commonly used registers (SFRs and the proper bank is selected before performing a data select GPRs) can be accessed in a single cycle, PIC18 read or write. For example, writing what should be devices implement an Access Bank. This is a 256-byte program data to an 8-bit address of F9h while the BSR memory space that provides fast access to SFRs and is 0Fh will end up resetting the program counter. the lower portion of GPR Bank 0 without using the While any bank can be selected, only those banks that BSR. Section5.3.2 “Access Bank” provides a are actually implemented can be read or written to. detailed description of the Access RAM. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return ‘0’s. Even so, the STATUS register will still be affected as if the operation was successful. The data memory map in Figure5-6 indicates which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. DS39646C-page 72 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 5-6: DATA MEMORY MAP FOR THE PIC18F8722 FAMILY OF DEVICES When ‘a’ = 0: BSR<3:0> Data Memory Map The BSR is ignored and the 000h Access Bank is used. 00h Access RAM = 0000 05Fh Bank 0 060h The first 96 bytes are FFh GPR 0FFh general purpose RAM 00h 100h (from Bank 0). = 0001 Bank 1 GPR The second 160 bytes are FFh 1FFh Special Function Registers = 0010 00h 200h (from Bank 15). Bank 2 GPR FFh 2FFh When ‘a’ = 1: = 0011 Bank 3 00h 300h The BSR specifies the Bank GPR used by the instruction. FFh 3FFh 00h 400h = 0100 Bank 4 GPR FFh 4FFh = 0101 00h 500h Bank 5 GPR FFh 5FFh = 0110 00h 600h Bank 6 GPR Access Bank FFh 6FFh = 0111 00h 700h 00h Bank 7 Access RAM Low GPR 5Fh FFh 7FFh Access RAM High 60h = 1000 Bank 8 00h 800h (SFRs) FFh GPR FFh 8FFh = 1001 00h 900h Bank 9 GPR FFh 9FFh = 1010 00h A00h Bank 10 GPR FFh AFFh = 1011 00h B00h Bank 11 GPR FFh BFFh C00h = 1100 00h Bank 12 GPR CFFh FFh D00h = 1101 00h Bank 13 GPR DFFh FFh 00h E00h = 1110 Bank 14 GPR FFh EFFh = 1111 00h GPR FF50F0hh Bank 15 F60h FFh SFR FFFh © 2008 Microchip Technology Inc. DS39646C-page 73

PIC18F8722 FAMILY FIGURE 5-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) Data Memory From Opcode(2) 7 0 000h 00h 7 0 0 0 0 0 0 0 1 1 Bank 0 FFh 1 1 1 1 1 1 1 1 100h 00h Bank 1 Bank Select(2) FFh 200h 00h Bank 2 300h FFh 00h Bank 3 through Bank 13 FFh E00h 00h Bank 14 F00h FFh 00h Bank 15 FFFh FFh Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. 5.3.2 ACCESS BANK however, the instruction is forced to use the Access Bank address map; the current value of the BSR is While the use of the BSR with an embedded 8-bit ignored entirely. address allows users to address the entire range of data memory, it also means that the user must always Using this “forced” addressing allows the instruction to ensure that the correct bank is selected. Otherwise, operate on a data address in a single cycle, without data may be read from or written to the wrong location. updating the BSR first. For 8-bit addresses of 60h and This can be disastrous if a GPR is the intended target above, this means that users can evaluate and operate of an operation, but an SFR is written to instead. on SFRs more efficiently. The Access RAM below 60h Verifying and/or changing the BSR for each read or is a good place for data values that the user might need write to data memory can become very inefficient. to access rapidly, such as immediate computational results or common program variables. Access RAM To streamline access for the most commonly used data also allows for faster and more code efficient context memory locations, the data memory is configured with saving and switching of variables. an Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The mapping of the Access Bank is slightly different The Access Bank consists of the first 96 bytes of when the extended instruction set is enabled (XINST memory (00h-5Fh) in Bank 0 and the last 160 bytes of Configuration bit = 1). This is discussed in more detail memory (60h-FFh) in Block 15. The lower half is known in Section5.5.3 “Mapping the Access Bank in as the “Access RAM” and is composed of GPRs. This Indexed Literal Offset Mode”. upper half is also where the device’s SFRs are 5.3.3 GENERAL PURPOSE REGISTER mapped. These two areas are mapped contiguously in the Access Bank and can be addressed in a linear FILE fashion by an 8-bit address (Figure5-6). PIC18 devices may have banked memory in the GPR The Access Bank is used by core PIC18 instructions area. This is data RAM, which is available for use by all that include the Access RAM bit (the ‘a’ parameter in instructions. GPRs start at the bottom of Bank 0 the instruction). When ‘a’ is equal to ‘1’, the instruction (address 000h) and grow upwards towards the bottom of uses the BSR and the 8-bit address included in the the SFR area. GPRs are not initialized by a Power-on opcode for the data memory address. When ‘a’ is ‘0’, Reset and are unchanged on all other Resets. DS39646C-page 74 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 5.3.4 SPECIAL FUNCTION REGISTERS The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, The Special Function Registers (SFRs) are registers Resets and interrupts) and those related to the used by the CPU and peripheral modules for controlling peripheral functions. The Reset and interrupt registers the desired operation of the device. These registers are are described in their respective chapters, while the implemented as static RAM. SFRs start at the top of ALU’s STATUS register is described later in this sec- data memory (FFFh) and extend downward to occupy tion. Registers related to the operation of a peripheral the top half of Bank 15 (F60h to FFFh). A list of these feature are described in the chapter for that peripheral. registers is given in Table5-2 and Table5-3. The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR locations are unimplemented and read as ‘0’s. TABLE 5-2: SPECIAL FUNCTION REGISTER MAP FOR THE PIC18F8722 FAMILY OF DEVICES Address Name Address Name Address Name Address Name Address Name FFFh TOSU FDFh INDF2(1) FBFh CCPR1H F9Fh IPR1 F7Fh SPBRGH1 FFEh TOSH FDEh POSTINC2(1) FBEh CCPR1L F9Eh PIR1 F7Eh BAUDCON1 FFDh TOSL FDDh POSTDEC2(1) FBDh CCP1CON F9Dh PIE1 F7Dh SPBRGH2 FFCh STKPTR FDCh PREINC2(1) FBCh CCPR2H F9Ch MEMCON F7Ch BAUDCON2 FFBh PCLATU FDBh PLUSW2(1) FBBh CCPR2L F9Bh OSCTUNE F7Bh —(2) FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah TRISJ(3) F7Ah —(2) FF9h PCL FD9h FSR2L FB9h CCPR3H F99h TRISH(3) F79h ECCP1DEL FF8h TBLPTRU FD8h STATUS FB8h CCPR3L F98h TRISG F78h TMR4 FF7h TBLPTRH FD7h TMR0H FB7h CCP3CON F97h TRISF F77h PR4 FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS F96h TRISE F76h T4CON FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD F75h CCPR4H FF4h PRODH FD4h —(2) FB4h CMCON F94h TRISC F74h CCPR4L FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB F73h CCP4CON FF2h INTCON FD2h HLVDCON FB2h TMR3L F92h TRISA F72h CCPR5H FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h LATJ(3) F71h CCPR5L FF0h INTCON3 FD0h RCON FB0h PSPCON F90h LATH(3) F70h CCP5CON FEFh INDF0(1) FCFh TMR1H FAFh SPBRG1 F8Fh LATG F6Fh SPBRG2 FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG1 F8Eh LATF F6Eh RCREG2 FEDh POSTDEC0(1) FCDh T1CON FADh TXREG1 F8Dh LATE F6Dh TXREG2 FECh PREINC0(1) FCCh TMR2 FACh TXSTA1 F8Ch LATD F6Ch TXSTA2 FEBh PLUSW0(1) FCBh PR2 FABh RCSTA1 F8Bh LATC F6Bh RCSTA2 FEAh FSR0H FCAh T2CON FAAh EEADRH F8Ah LATB F6Ah ECCP3AS FE9h FSR0L FC9h SSP1BUF FA9h EEADR F89h LATA F69h ECCP3DEL FE8h WREG FC8h SSP1ADD FA8h EEDATA F88h PORTJ(3) F68h ECCP2AS FE7h INDF1(1) FC7h SSP1STAT FA7h EECON2(1) F87h PORTH(3) F67h ECCP2DEL FE6h POSTINC1(1) FC6h SSP1CON1 FA6h EECON1 F86h PORTG F66h SSP2BUF FE5h POSTDEC1(1) FC5h SSP1CON2 FA5h IPR3 F85h PORTF F65h SSP2ADD FE4h PREINC1(1) FC4h ADRESH FA4h PIR3 F84h PORTE F64h SSP2STAT FE3h PLUSW1(1) FC3h ADRESL FA3h PIE3 F83h PORTD F63h SSP2CON1 FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC F62h SSP2CON2 FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB F61h —(2) FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA F60h —(2) Note 1: This is not a physical register. 2: Unimplemented registers are read as ‘0’. 3: This register is not available on 64-pin devices. © 2008 Microchip Technology Inc. DS39646C-page 75

PIC18F8722 FAMILY TABLE 5-3: REGISTER FILE SUMMARY Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 57, 66 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 57, 66 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 57, 66 STKPTR STKFUL(6) STKUNF(6) — SP4 SP3 SP2 SP1 SP0 00-0 0000 57, 67 PCLATU — — — Holding Register for PC<20:16> ---0 0000 57, 66 PCLATH Holding Register for PC<15:8> 0000 0000 57, 66 PCL PC Low Byte (PC<7:0>) 0000 0000 57, 66 TBLPTRU — — bit 21(7) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 57, 90 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 57, 90 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 57, 90 TABLAT Program Memory Table Latch 0000 0000 57, 90 PRODH Product Register High Byte xxxx xxxx 57, 117 PRODL Product Register Low Byte xxxx xxxx 57, 117 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 57, 121 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 57, 122 INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 57, 123 INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 57, 82 POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 57, 82 POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 57, 82 PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 57, 82 PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – N/A 57, 82 value of FSR0 offset by W FSR0H — — — — Indirect Data Memory Address Pointer 0 High ---- 0000 57, 82 FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 57, 82 WREG Working Register xxxx xxxx 57 INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 57, 82 POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 57, 82 POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 57, 82 PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 57, 82 PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – N/A 57, 82 value of FSR1 offset by W FSR1H — — — — Indirect Data Memory Address Pointer 1 High ---- 0000 58, 82 FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 58, 82 BSR — — — — Bank Select Register ---- 0000 58, 72 INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 58, 82 POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 58, 82 POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 58, 82 PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 58, 82 PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – N/A 58, 82 value of FSR2 offset by W FSR2H — — — — Indirect Data Memory Address Pointer 2 High ---- 0000 58, 82 FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 58, 82 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits=01; otherwise, this bit reads as ‘0’. 2: These registers and/or bits are not implemented on 64-pin devices and are read as ‘0’. Reset values are shown for 80-pin devices; individual unimplemented bits should be interpreted as ‘-’. 3: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section2.6.4 “PLL in INTOSC Modes”. 4: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 5: RG5 and LATG5 are only available when Master Clear is disabled (MCLRE Configuration bit=0); otherwise, RG5 and LATG5 read as ‘0’. 6: Bit 7 and Bit 6 are cleared by user software or by a POR. 7: Bit 21 of TBLPTRU allows access to the device Configuration bits. DS39646C-page 76 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 5-3: REGISTER FILE SUMMARY (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: STATUS — — — N OV Z DC C ---x xxxx 58, 80 TMR0H Timer0 Register High Byte 0000 0000 58, 163 TMR0L Timer0 Register Low Byte xxxx xxxx 58, 163 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 58, 161 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 39, 58 HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 58, 291 WDTCON — — — — — — — SWDTEN --- ---0 58, 313 RCON IPEN SBOREN(1) — RI TO PD POR BOR 0q-1 11q0 50, 56, 58, 133 TMR1H Timer1 Register High Byte xxxx xxxx 58, 169 TMR1L Timer1 Register Low Byte xxxx xxxx 58, 169 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 58, 165 TMR2 Timer2 Register 0000 0000 58, 172 PR2 Timer2 Period Register 1111 1111 58, 172 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 58, 171 SSP1BUF MSSP1 Receive Buffer/Transmit Register xxxx xxxx 58, 169, 170 SSP1ADD MSSP1 Address Register in I2C™ Slave mode. MSSP1 Baud Rate Reload Register in I2C Master mode. 0000 0000 58, 170 SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 58, 162, 171 SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 58, 163, 172 SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 58, 173 ADRESH A/D Result Register High Byte xxxx xxxx 59, 280 ADRESL A/D Result Register Low Byte xxxx xxxx 59, 280 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 59, 271 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 59, 272 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 59, 273 CCPR1H Enhanced Capture/Compare/PWM Register 1 High Byte xxxx xxxx 59, 180 CCPR1L Enhanced Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 59, 180 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 59, 187 CCPR2H Enhanced Capture/Compare/PWM Register 2 High Byte xxxx xxxx 59, 180 CCPR2L Enhanced Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 59, 180 CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 59, 179 CCPR3H Enhanced Capture/Compare/PWM Register 3 High Byte xxxx xxxx 59, 180 CCPR3L Enhanced Capture/Compare/PWM Register 3 Low Byte xxxx xxxx 59, 180 CCP3CON P3M1 P3M0 DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 0000 0000 59, 179 ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 59, 201 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 59, 287 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 59, 289 TMR3H Timer3 Register High Byte xxxx xxxx 59, 175 TMR3L Timer3 Register Low Byte xxxx xxxx 59, 175 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 59, 173 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits=01; otherwise, this bit reads as ‘0’. 2: These registers and/or bits are not implemented on 64-pin devices and are read as ‘0’. Reset values are shown for 80-pin devices; individual unimplemented bits should be interpreted as ‘-’. 3: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section2.6.4 “PLL in INTOSC Modes”. 4: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 5: RG5 and LATG5 are only available when Master Clear is disabled (MCLRE Configuration bit=0); otherwise, RG5 and LATG5 read as ‘0’. 6: Bit 7 and Bit 6 are cleared by user software or by a POR. 7: Bit 21 of TBLPTRU allows access to the device Configuration bits. © 2008 Microchip Technology Inc. DS39646C-page 77

PIC18F8722 FAMILY TABLE 5-3: REGISTER FILE SUMMARY (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- 59, 252 SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 0000 0000 59, 252 RCREG1 EUSART1 Receive Register 0000 0000 59, 260 TXREG1 EUSART1 Transmit Register 0000 0000 59, 257 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 59, 248 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 59, 249 EEADRH — — — — — — EEPROM Address ---- --00 59, 111 Register High Byte EEADR EEPROM Address Register Low Byte 0000 0000 59, 111 EEDATA EEPROM Data Register 0000 0000 59, 111 EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 59, 88 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 59, 89 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 1111 1111 60, 131 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 0000 0000 60, 125 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 0000 0000 60, 129 IPR2 OSCFIP CMIP — EEIP BCL1IP HLVDIP TMR3IP CCP2IP 11-1 1111 60, 131 PIR2 OSCFIF CMIF — EEIF BCL1IF HLVDIF TMR3IF CCP2IF 00-0 0000 60, 125 PIE2 OSCFIE CMIE — EEIE BCL1IE HLVDIE TMR3IE CCP2IE 00-0 0000 60, 128 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 1111 1111 60, 130 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 60, 124 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 60, 127 MEMCON(2) EBDIS — WAIT1 WAIT0 — — WM1 WM0 0-00 --00 60, 96 OSCTUNE INTSRC PLLEN(3) — TUN4 TUN3 TUN2 TUN1 TUN0 00-0 0000 35, 60 TRISJ(2) TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3 TRISJ2 TRISJ1 TRISJ0 1111 1111 60, 157 TRISH(2) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 1111 1111 60, 155 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 ---1 1111 60, 153 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 60, 150 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 1111 1111 60, 148 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 60, 143 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 60, 140 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 60, 137 TRISA TRISA7(4) TRISA6(4) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 60, 135 LATJ(2) LATJ7 LATJ6 LATJ5 LATJ4 LATJ3 LATJ2 LATJ1 LATJ0 xxxx xxxx 60, 156 LATH(2) LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 xxxx xxxx 60, 154 LATG — — LATG5(5) LATG4 LATG3 LATG2 LATG1 LATG0 --xx xxxx 60, 151 LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx xxxx 60, 149 LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx xxxx 60, 146 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx 60, 143 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx 60, 140 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx 60, 137 LATA LATA7(4) LATA6(4) LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx xxxx 60, 135 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits=01; otherwise, this bit reads as ‘0’. 2: These registers and/or bits are not implemented on 64-pin devices and are read as ‘0’. Reset values are shown for 80-pin devices; individual unimplemented bits should be interpreted as ‘-’. 3: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section2.6.4 “PLL in INTOSC Modes”. 4: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 5: RG5 and LATG5 are only available when Master Clear is disabled (MCLRE Configuration bit=0); otherwise, RG5 and LATG5 read as ‘0’. 6: Bit 7 and Bit 6 are cleared by user software or by a POR. 7: Bit 21 of TBLPTRU allows access to the device Configuration bits. DS39646C-page 78 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 5-3: REGISTER FILE SUMMARY (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: PORTJ(2) RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 xxxx xxxx 60, 156 PORTH(2) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 0000 xxxx 60, 154 PORTG — — RG5(5) RG4 RG3 RG2 RG1 RG0 --xx xxxx 60, 151 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 x000 0000 60, 149 PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx xxxx 60, 146 PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 60, 143 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 60, 140 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 60, 137 PORTA RA7(4) RA6(4) RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 61, 135 SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 0000 0000 61, 252 BAUDCON1 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 61, 250 SPBRGH2 EUSART2 Baud Rate Generator Register High Byte 0000 0000 61, 252 BAUDCON2 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 61, 250 ECCP1DEL P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 0000 0000 61, 200 TMR4 Timer4 Register 0000 0000 61, 178 PR4 Timer4 Period Register 1111 1111 61, 178 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 61, 178 CCPR4H Capture/Compare/PWM Register 4 High Byte xxxx xxxx 61, 180 CCPR4L Capture/Compare/PWM Register 4 Low Byte xxxx xxxx 61, 180 CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000 61, 179 CCPR5H Capture/Compare/PWM Register 5 High Byte xxxx xxxx 61, 180 CCPR5L Capture/Compare/PWM Register 5 Low Byte xxxx xxxx 61, 180 CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 --00 0000 61, 179 SPBRG2 EUSART2 Baud Rate Generator Register Low Byte 0000 0000 61, 252 RCREG2 EUSART2 Receive Register 0000 0000 61, 260 TXREG2 EUSART2 Transmit Register 0000 0000 61, 257 TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 61, 248 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 61, 249 ECCP3AS ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 PSS3AC1 PSS3AC0 PSS3BD1 PSS3BD0 0000 0000 61, 201 ECCP3DEL P3RSEN P3DC6 P3DC5 P3DC4 P3DC3 P3DC2 P3DC1 P3DC0 0000 0000 61, 200 ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 61, 201 ECCP2DEL P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 61, 200 SSP2BUF MSSP2 Receive Buffer/Transmit Register xxxx xxxx 61, 170 SSP2ADD MSSP2 Address Register in I2C™ Slave mode. MSSP2 Baud Rate Reload Register in I2C Master mode. 0000 0000 61, 170 SSP2STAT SMP CKE D/A P S R/W UA BF 0000 0000 61, 216 SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 61, 217 SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 61, 218 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits=01; otherwise, this bit reads as ‘0’. 2: These registers and/or bits are not implemented on 64-pin devices and are read as ‘0’. Reset values are shown for 80-pin devices; individual unimplemented bits should be interpreted as ‘-’. 3: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section2.6.4 “PLL in INTOSC Modes”. 4: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 5: RG5 and LATG5 are only available when Master Clear is disabled (MCLRE Configuration bit=0); otherwise, RG5 and LATG5 read as ‘0’. 6: Bit 7 and Bit 6 are cleared by user software or by a POR. 7: Bit 21 of TBLPTRU allows access to the device Configuration bits. © 2008 Microchip Technology Inc. DS39646C-page 79

PIC18F8722 FAMILY 5.3.5 STATUS REGISTER It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS The STATUS register, shown in Register5-2, contains register, because these instructions do not affect the Z, the arithmetic status of the ALU. As with any other SFR, C, DC, OV or N bits in the STATUS register. it can be the operand for any instruction. For other instructions that do not affect Status bits, see If the STATUS register is the destination for an instruction the instruction set summaries in Table26-2 and that affects the Z, DC, C, OV or N bits, the results of the Table26-3. instruction are not written; instead, the STATUS register is updated according to the instruction performed. There- Note: The C and DC bits operate as the borrow fore, the result of an instruction with the STATUS register and digit borrow bits, respectively, in as its destination may be different than intended. As an subtraction. example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (‘000u u1uu’). REGISTER 5-2: STATUS: ARITHMETIC STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC(1) C(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7 of the result) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/borrow bit(1) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/borrow bit(2) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’scomplement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. 2: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’scomplement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. DS39646C-page 80 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 5.4 Data Addressing Modes The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR Note: The execution of some instructions in the (Section5.3.1 “Bank Select Register (BSR)”) are core PIC18 instruction set are changed used with the address to determine the complete 12-bit when the PIC18 extended instruction set is address of the register. When ‘a’ is ‘0’, the address is enabled. See Section5.5 “Data Memory interpreted as being a register in the Access Bank. and the Extended Instruction Set” for Addressing that uses the Access RAM is sometimes more information. also known as Direct Forced Addressing mode. The data memory space can be addressed in several A few instructions, such as MOVFF, include the entire ways. For most instructions, the addressing mode is 12-bit address (either source or destination) in their fixed. Other instructions may use up to three modes, opcodes. In these cases, the BSR is ignored entirely. depending on which operands are used and whether or The destination of the operation’s results is determined not the extended instruction set is enabled. by the destination bit ‘d’. When ‘d’ is ‘1’, the results are The addressing modes are: stored back in the source register, overwriting its origi- nal contents. When ‘d’ is ‘0’, the results are stored in • Inherent the W register. Instructions without the ‘d’ argument • Literal have a destination that is implicit in the instruction; their • Direct destination is either the target register being operated • Indirect on or the W register. An additional addressing mode, Indexed Literal Offset, 5.4.3 INDIRECT ADDRESSING is available when the extended instruction set is enabled (XINST Configuration bit = 1). Its operation is Indirect Addressing allows the user to access a location discussed in greater detail in Section5.5.1 “Indexed in data memory without giving a fixed address in the Addressing with Literal Offset”. instruction. This is done by using File Select Registers (FSRs) as pointers to the locations to be read or written 5.4.1 INHERENT AND LITERAL to. Since the FSRs are themselves located in RAM as ADDRESSING Special File Registers, they can also be directly manip- Many PIC18 control instructions do not need any argu- ulated under program control. This makes FSRs very ment at all; they either perform an operation that globally useful in implementing data structures, such as tables affects the device or they operate implicitly on one and arrays in data memory. register. This addressing mode is known as Inherent The registers for Indirect Addressing are also Addressing. Examples include SLEEP, RESET and DAW. implemented with Indirect File Operands (INDFs) that Other instructions work in a similar way but require an permit automatic manipulation of the pointer value with additional explicit argument in the opcode. This is auto-incrementing, auto-decrementing or offsetting known as Literal Addressing mode because they with another value. This allows for efficient code, using require some literal value as an argument. Examples loops, such as the example of clearing an entire RAM include ADDLW and MOVLW, which respectively, add or bank in Example5-5. move a literal value to the W register. Other examples include CALL and GOTO, which include a 20-bit EXAMPLE 5-5: HOW TO CLEAR RAM program memory address. (BANK 1) USING INDIRECT ADDRESSING 5.4.2 DIRECT ADDRESSING LFSR FSR0, 100h ; Direct Addressing specifies all or part of the source NEXT CLRF POSTINC0 ; Clear INDF and/or destination address of the operation within the ; register then opcode itself. The options are specified by the ; inc pointer arguments accompanying the instruction. BTFSS FSR0H,1 ; All done with ; Bank1? In the core PIC18 instruction set, bit-oriented and byte- BRA NEXT ; NO, clear next oriented instructions use some version of Direct CONTINUE ; YES, continue Addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section5.3.3 “General Purpose Register File”) or a location in the Access Bank (Section5.3.2 “Access Bank”) as the data source for the instruction. © 2008 Microchip Technology Inc. DS39646C-page 81

PIC18F8722 FAMILY 5.4.3.1 FSR Registers and the 5.4.3.2 FSR Registers and POSTINC, INDF Operand POSTDEC, PREINC and PLUSW At the core of Indirect Addressing are three sets of In addition to the INDF operand, each FSR register pair registers: FSR0, FSR1 and FSR2. Each represents a also has four additional indirect operands. Like INDF, pair of 8-bit registers, FSRnH and FSRnL. The four these are “virtual” registers that cannot be indirectly upper bits of the FSRnH register are not used so each read or written to. Accessing these registers actually FSR pair holds a 12-bit value. This represents a value accesses the associated FSR register pair, but also that can address the entire range of the data memory performs a specific action on its stored value. They are: in a linear fashion. The FSR register pairs, then, serve • POSTDEC: accesses the FSR value, then as pointers to data memory locations. automatically decrements it by 1 afterwards Indirect Addressing is accomplished with a set of • POSTINC: accesses the FSR value, then Indirect File Operands, INDF0 through INDF2. These automatically increments it by 1 afterwards can be thought of as “virtual” registers: they are • PREINC: increments the FSR value by 1, then mapped in the SFR space but are not physically imple- uses it in the operation mented. Reading or writing to a particular INDF register • PLUSW: adds the signed value of the W register actually accesses its corresponding FSR register pair. (range of -127 to 128) to that of the FSR and uses A read from INDF1, for example, reads the data at the the new value in the operation. address indicated by FSR1H:FSR1L. Instructions that In this context, accessing an INDF register uses the use the INDF registers as operands actually use the value in the FSR registers without changing them. contents of their corresponding FSR as a pointer to the Similarly, accessing a PLUSW register gives the FSR instruction’s target. The INDF operand is just a value offset by the value in the W register; neither value convenient way of using the pointer. is actually changed in the operation. Accessing the Because Indirect Addressing uses a full 12-bit address, other virtual registers changes the value of the FSR data RAM banking is not necessary. Thus, the current registers. contents of the BSR and the Access RAM bit have no Operations on the FSRs with POSTDEC, POSTINC effect on determining the target address. and PREINC affect the entire register pair; that is, roll- overs of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). FIGURE 5-8: INDIRECT ADDRESSING 000h Using an instruction with one of the ADDWF, INDF1, 1 Bank 0 Indirect Addressing registers as the 100h operand.... Bank 1 200h Bank 2 300h ...uses the 12-bit address stored in FSR1H:FSR1L the FSR pair associated with that 7 0 7 0 register.... Bank 3 x x x x 1 1 1 0 1 1 0 0 1 1 0 0 through Bank 13 ...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains E00h ECCh. This means the contents of Bank 14 location ECCh will be added to that F00h of the W register and stored back in Bank 15 ECCh. FFFh Data Memory DS39646C-page 82 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY The PLUSW register can be used to implement a form 5.5.1 INDEXED ADDRESSING WITH of Indexed Addressing in the data memory space. By LITERAL OFFSET manipulating the value in the W register, users can Enabling the PIC18 extended instruction set changes reach addresses that are fixed offsets from pointer the behavior of Indirect Addressing using the FSR2 addresses. In some applications, this can be used to register pair within Access RAM. Under the proper implement some powerful program control structure, conditions, instructions that use the Access Bank – that such as software stacks, inside of data memory. is, most bit-oriented and byte-oriented instructions – 5.4.3.3 Operations by FSRs on FSRs can invoke a form of Indexed Addressing using an offset specified in the instruction. This special address- Indirect Addressing operations that target other FSRs ing mode is known as Indexed Addressing with Literal or virtual registers represent special cases. For exam- Offset, or Indexed Literal Offset mode. ple, using an FSR to point to one of the virtual registers When using the extended instruction set, this will not result in successful operations. As a specific addressing mode requires the following: case, assume that FSR0H:FSR0L contains FE7h, the address of INDF1. Attempts to read the value of the • The use of the Access Bank is forced (‘a’ = 0) and INDF1 using INDF0 as an operand will return 00h. • The file address argument is less than or equal to Attempts to write to INDF1 using INDF0 as the operand 5Fh. will result in a NOP. Under these conditions, the file address of the instruc- On the other hand, using the virtual registers to write to tion is not interpreted as the lower byte of an address an FSR pair may not occur as planned. In these cases, (used with the BSR in Direct Addressing), or as an 8-bit the value will be written to the FSR pair but without any address in the Access Bank. Instead, the value is incrementing or decrementing. Thus, writing to INDF2 interpreted as an offset value to an address pointer, or POSTDEC2 will write the same value to the specified by FSR2. The offset and the contents of FSR2H:FSR2L. FSR2 are added to obtain the target address of the Since the FSRs are physical registers mapped in the operation. SFR space, they can be manipulated through all direct 5.5.2 INSTRUCTIONS AFFECTED BY operations. Users should proceed cautiously when INDEXED LITERAL OFFSET MODE working on these registers, particularly if their code uses Indirect Addressing. Any of the core PIC18 instructions that can use Direct Addressing are potentially affected by the Indexed Similarly, operations by Indirect Addressing are gener- Literal Offset Addressing mode. This includes all ally permitted on all other SFRs. Users should exercise byte-oriented and bit-oriented instructions, or almost the appropriate caution that they do not inadvertently one-half of the standard PIC18 instruction set. change settings that might affect the operation of the Instructions that only use Inherent or Literal Addressing device. modes are unaffected. 5.5 Data Memory and the Extended Additionally, byte-oriented and bit-oriented instructions Instruction Set are not affected if they do not use the Access Bank (Access RAM bit is ‘1’), or include a file address of 60h Enabling the PIC18 extended instruction set (XINST or above. Instructions meeting these criteria will Configuration bit = 1) significantly changes certain continue to execute as before. A comparison of the dif- aspects of data memory and its addressing. Specifi- ferent possible addressing modes when the extended cally, the use of the Access Bank for many of the core instruction set is enabled in shown in Figure5-9. PIC18 instructions is different; this is due to the Those who desire to use byte-oriented or bit-oriented introduction of a new addressing mode for the data instructions in the Indexed Literal Offset mode should memory space. note the changes to assembler syntax for this mode. What does not change is just as important. The size of This is described in more detail in Section26.2.1 the data memory space is unchanged, as well as its “Extended Instruction Syntax”. linear addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect Addressing with FSR0 and FSR1 also remain unchanged. © 2008 Microchip Technology Inc. DS39646C-page 83

PIC18F8722 FAMILY FIGURE 5-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) 000h When ‘a’ = 0 and f ≥ 60h: The instruction executes in 060h Direct Forced mode. ‘f’ is inter- 080h Bank 0 preted as a location in the 100h Access RAM between 060h 00h and 0FFh. This is the same as Bank 1 through 60h locations 060h to 07Fh Bank 14 80h (Bank0) and F80h to FFFh Valid range for ‘f’ (Bank 15) of data memory. FFh Locations below 60h are not F00h Access RAM available in this addressing Bank 15 mode. F80h SFRs FFFh Data Memory When ‘a’ = 0 and f ≤ 5Fh: 000h The instruction executes in Bank 0 Indexed Literal Offset mode. ‘f’ 080h is interpreted as an offset to the address value in FSR2. The 100h 001001da ffffffff two are added together to Bank 1 obtain the address of the target through register for the instruction. The Bank 14 address can be anywhere in FSR2H FSR2L the data memory space. F00h Note that in this mode, the Bank 15 correct syntax is now: F80h ADDWF [k], d SFRs where ‘k’ is the same as ‘f’. FFFh Data Memory BSR When ‘a’ = 1 (all values of f): 000h 00000000 The instruction executes in Bank 0 080h Direct mode (also known as Direct Long mode). ‘f’ is inter- 100h preted as a location in one of the 16 banks of the data Bank 1 001001da ffffffff memory space. The bank is through Bank 14 designated by the Bank Select Register (BSR). The address can be in any implemented F00h bank in the data memory Bank 15 space. F80h SFRs FFFh Data Memory DS39646C-page 84 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 5.5.3 MAPPING THE ACCESS BANK IN Remapping of the Access Bank applies only to opera- INDEXED LITERAL OFFSET MODE tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue The use of Indexed Literal Offset Addressing mode to use Direct Addressing as before. effectively changes how the first 96 locations of Access RAM (00h to 5Fh) are mapped. Rather than containing 5.6 PIC18 Instruction Execution and just the contents of the bottom half of Bank 0, this mode the Extended Instruction Set maps the contents from Bank 0 and a user defined “window” that can be located anywhere in the data Enabling the extended instruction set adds eight memory space. The value of FSR2 establishes the additional commands to the existing PIC18 instruction lower boundary of the addresses mapped into the set. These instructions are executed as described in window, while the upper boundary is defined by FSR2 Section26.2 “Extended Instruction Set”. plus 95 (5Fh). Addresses in the Access RAM above 5Fh are mapped as previously described (see Section5.3.2 “Access Bank”). An example of Access Bank remapping in this addressing mode is shown in Figure5-10. FIGURE 5-10: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Example Situation: ADDWF f, d, a 000h Bank 0 FSR2H:FSR2L = 120h 05Fh 07Fh Locations in the region Bank 0 from the FSR2 Pointer 100h (120h) to the pointer plus Bank 1 120h 05Fh (17Fh) are mapped Window 17Fh 00h to the bottom of the Bank 1 Bank 1 “Window” Access RAM (000h-05Fh). 200h 5Fh Locations in Bank 0 from Bank 0 060h to 07Fh are mapped, 7Fh as usual, to the middle half Bank 2 80h of the Access Bank. through SFRs Special File Registers at Bank 14 F80h through FFFh are FFh mapped to 80h through Access Bank FFh, as usual. F00h Bank 0 addresses below Bank 15 5Fh can still be addressed F80h by using the BSR. SFRs FFFh Data Memory © 2008 Microchip Technology Inc. DS39646C-page 85

PIC18F8722 FAMILY NOTES: DS39646C-page 86 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 6.0 FLASH PROGRAM MEMORY 6.1 Table Reads and Table Writes The Flash program memory is readable, writable and In order to read and write program memory, there are erasable during normal operation over the entire VDD two operations that allow the processor to move bytes range. between the program memory space and the data RAM: A read from program memory is executed on one byte • Table Read (TBLRD) at a time. A write to program memory is executed on • Table Write (TBLWT) blocks of 64 bytes at a time. Program memory is The program memory space is 16 bits wide, while the erased in blocks of 64 bytes at a time. A bulk erase data RAM space is 8 bits wide. Table reads and table operation may not be issued from user code. writes move data between these two memory spaces Writing or erasing program memory will cease through an 8-bit register (TABLAT). instruction fetches until the operation is complete. The Table read operations retrieve data from program program memory cannot be accessed during the write memory and place it into the data RAM space. or erase, therefore, code cannot execute. An internal Figure6-1 shows the operation of a table read with programming timer terminates program memory writes program memory and data RAM. and erases. Table write operations store data from the data memory A value written to program memory does not need to be space into holding registers in program memory. The a valid instruction. Executing a program memory procedure to write the contents of the holding registers location that forms an invalid instruction results in a into program memory is detailed in Section6.5 “Writing NOP. to Flash Program Memory”. Figure6-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word aligned. FIGURE 6-1: TABLE READ OPERATION Instruction: TBLRD* Table Pointer(1) Program Memory Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1:Table Pointer register points to a byte in program memory. © 2008 Microchip Technology Inc. DS39646C-page 87

PIC18F8722 FAMILY FIGURE 6-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section6.5 “Writing to Flash Program Memory”. 6.2 Control Registers registers regardless of EEPGD (see Section25.0 “Special Features of the CPU”). When clear, memory Several control registers are used in conjunction with selection access is determined by EEPGD. the TBLRD and TBLWT instructions. These include the: The FREE bit, when set, will allow a program memory • EECON1 register erase operation. When FREE is set, the erase • EECON2 register operation is initiated on the next WR command. When • TABLAT register FREE is clear, only writes are enabled. • TBLPTR registers The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is 6.2.1 EECON1 AND EECON2 REGISTERS set in hardware when the WR bit is set and cleared The EECON1 register (Register6-1) is the control when the internal programming timer expires and the register for memory accesses. The EECON2 register is write operation is complete. not a physical register; it is used exclusively in the Note: During normal operation, the WRERR is memory write and erase sequences. Reading read as ‘1’. This can indicate that a write EECON2 will read all ‘0’s. operation was prematurely terminated by The EEPGD control bit determines if the access will be a Reset, or a write operation was a program or data EEPROM memory access. When attempted improperly. clear, any subsequent operations will operate on the data EEPROM memory. When set, any subsequent The WR control bit initiates write operations. The bit operations will operate on the program memory. cannot be cleared, only set, in software; it is cleared in The CFGS control bit determines if the access will be hardware at the completion of the write operation. to the Configuration/Calibration registers or to program Note: The EEIF interrupt flag bit (PIR2<4>) is set memory/data EEPROM memory. When set, when the write is complete. It must be subsequent operations will operate on Configuration cleared in software. DS39646C-page 88 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY REGISTER 6-1: EECON1: EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2008 Microchip Technology Inc. DS39646C-page 89

PIC18F8722 FAMILY 6.2.2 TABLAT – TABLE LATCH REGISTER 6.2.4 TABLE POINTER BOUNDARIES The Table Latch (TABLAT) is an 8-bit register mapped TBLPTR is used in reads, writes and erases of the into the SFR space. The Table Latch register is used to Flash program memory. hold 8-bit data during data transfers between program When a TBLRD is executed, all 22 bits of the TBLPTR memory and data RAM. determine which byte is read from program memory into TABLAT. 6.2.3 TBLPTR – TABLE POINTER REGISTER When a TBLWT is executed, the six LSbs of the Table Pointer register (TBLPTR<5:0>) determine which of The Table Pointer (TBLPTR) register addresses a byte the 64 program memory holding registers is written to. within the program memory. The TBLPTR is comprised When the timed write to program memory begins (via of three SFR registers: Table Pointer Upper Byte, Table the WR bit), the 16 MSbs of the TBLPTR Pointer High Byte and Table Pointer Low Byte (TBLPTR<21:6>) determine which program memory (TBLPTRU:TBLPTRH:TBLPTRL). These three regis- block of 64 bytes is written to. For more detail, see ters join to form a 22-bit wide pointer. The low-order Section6.5 “Writing to Flash Program Memory”. 21bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to When an erase of program memory is executed, the the device ID, the user ID and the Configuration bits. 16MSbs of the Table Pointer register (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least The Table Pointer register, TBLPTR, is used by the Significant bits (TBLPTR<5:0>) are ignored. TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the Figure6-3 describes the relevant boundaries of table operation. These operations are shown in TBLPTR based on Flash program memory operations. Table6-1. These operations on the TBLPTR only affect the low-order 21bits. TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLPTR is not modified TBLWT* TBLRD*+ TBLPTR is incremented after the read/write TBLWT*+ TBLRD*- TBLPTR is decremented after the read/write TBLWT*- TBLRD+* TBLPTR is incremented before the read/write TBLWT+* FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION 21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 TABLE ERASE/WRITE TABLE WRITE TBLPTR<21:6> TBLPTR<5:0> TABLE READ – TBLPTR<21:0> DS39646C-page 90 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 6.3 Reading the Flash Program TBLPTR points to a byte address in program space. Memory Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified The TBLRD instruction is used to retrieve data from automatically for the next table read operation. program memory and places it into data RAM. Table The internal program memory is typically organized by reads from program memory are performed one byte at words. The Least Significant bit of the address selects a time. between the high and low bytes of the word. Figure6-4 shows the interface between the internal program memory and the TABLAT. FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register TABLAT FETCH TBLRD (IR) Read Register EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_WORD TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_EVEN TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVF WORD_ODD © 2008 Microchip Technology Inc. DS39646C-page 91

PIC18F8722 FAMILY 6.4 Erasing Flash Program Memory 6.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through The sequence of events for erasing a block of internal ICSP control, can larger blocks of program memory be program memory location is: bulk erased. Word erase in the Flash array is not 1. Load Table Pointer register with address of row supported. being erased. When initiating an erase sequence from the micro- 2. Set the EECON1 register for the erase operation: controller itself, a block of 64 bytes of program memory • set EEPGD bit to point to program memory; is erased. The Most Significant 16 bits of the • clear the CFGS bit to access program memory; TBLPTR<21:6> point to the block being erased. • set WREN bit to enable writes; TBLPTR<5:0> are ignored. • set FREE bit to enable the erase. The EECON1 register commands the erase operation. 3. Disable interrupts. The EEPGD bit must be set to point to the Flash 4. Write 55h to EECON2. program memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase 5. Write 0AAh to EECON2. operation. 6. Set the WR bit. This will begin the row erase cycle. For protection, the write initiate sequence for EECON2 must be used. 7. The CPU will stall for duration of the erase for TIW (see parameter D133A). A long write is necessary for erasing the internal Flash. 8. Re-enable interrupts. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY ROW MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_ROW BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts Required MOVLW 55h Sequence MOVWF EECON2 ; write 55h MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts DS39646C-page 92 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 6.5 Writing to Flash Program Memory The long write is necessary for programming the inter- nal Flash. Instruction execution is halted while in a long The minimum programming block is 32 words or write cycle. The long write will be terminated by the 64bytes. Word or byte programming is not supported. internal programming timer. Table writes are used internally to load the holding The EEPROM on-chip timer controls the write time. registers needed to program the Flash memory. There The write/erase voltages are generated by an on-chip are 64 holding registers used by the table writes for charge pump, rated to operate over the voltage range programming. of the device. Since the Table Latch (TABLAT) is only a single byte, the Note: The default value of the holding registers on TBLWT instruction may need to be executed 64times for device Resets and after write operations is each programming operation. All of the table write oper- FFh. A write of FFh to a holding register ations will essentially be short writes because only the does not modify that byte. This means that holding registers are written. At the end of updating the individual bytes of program memory may be 64 holding registers, the EECON1 register must be modified, provided that the change does not written to in order to start the programming operation attempt to change any bit from a ‘0’ to a ‘1’. with a long write. When modifying individual bytes, it is not necessary to load all 64 holding registers before executing a write operation. FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 8 8 TBLPTR = xxxxx0 TBLPTR = xxxxx1 TBLPTR = xxxxx2 TBLPTR = xxxx3F Holding Register Holding Register Holding Register Holding Register Program Memory 6.5.1 FLASH PROGRAM MEMORY WRITE 8. Disable interrupts. SEQUENCE 9. Write 55h to EECON2. The sequence of events for programming an internal 10. Write 0AAh to EECON2. program memory location should be: 11. Set the WR bit. This will begin the write cycle. 1. Read 64 bytes into RAM. 12. The CPU will stall for duration of the write for TIW (see parameter D133A). 2. Update data values in RAM as necessary. 13. Re-enable interrupts. 3. Load Table Pointer register with address being erased. 14. Verify the memory (table read). 4. Execute the row erase procedure. An example of the required code is shown in 5. Load Table Pointer register with address of first Example6-3 on the following page. byte being written. Note: Before setting the WR bit, the Table 6. Write the 64 bytes into the holding registers with Pointer address needs to be within the auto-increment. intended address range of the 64 bytes in 7. Set the EECON1 register for the write operation: the holding register. • set EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN to enable byte writes. © 2008 Microchip Technology Inc. DS39646C-page 93

PIC18F8722 FAMILY EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'64' ; number of bytes in erase block MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ ; read into TABLAT, and inc MOVF TABLAT, W ; get data MOVWF POSTINC0 ; store data DECFSZ COUNTER ; done? BRA READ_BLOCK ; repeat MODIFY_WORD MOVLWD ATA_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW DATA_ADDR_LOW MOVWF FSR0L MOVLW NEW_DATA_LOW ; update buffer word MOVWF POSTINC0 MOVLW NEW_DATA_HIGH MOVWF INDF0 ERASE_BLOCK MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Row Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts TBLRD*- ; dummy read decrement MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L WRITE_BUFFER_BACK MOVLW D'64' ; number of bytes in holding register MOVWF COUNTER WRITE_BYTE_TO_HREGS MOVFF POSTINC0, WREG ; get low byte of buffer data MOVWF TABLAT ; present data to table latch TBLWT+* ; write data, perform a short write ; to internal TBLWT holding register. DECFSZ COUNTER ; loop until buffers are full BRA WRITE_WORD_TO_HREGS DS39646C-page 94 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BSF EECON1, EEPGD ; point to Flash program memory BCF EECON1, CFGS ; access Flash program memory BSF EECON1, WREN ; enable write to memory BCF INTCON, GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start program (CPU stall) BSF INTCON, GIE ; re-enable interrupts BCF EECON1, WREN ; disable write to memory 6.5.2 WRITE VERIFY 6.5.4 PROTECTION AGAINST SPURIOUS WRITES Depending on the application, good programming practice may dictate that the value written to the To protect against spurious writes to Flash program memory should be verified against the original value. memory, the write initiate sequence must also be This should be used in applications where excessive followed. See Section25.0 “Special Features of the writes can stress bits near the specification limit. CPU” for more detail. 6.5.3 UNEXPECTED TERMINATION OF 6.6 Flash Program Operation During WRITE OPERATION Code Protection If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory See Section25.5 “Program Verification and Code Protection” for details on code protection of Flash location just programmed should be verified and repro- grammed if needed. If the write operation is interrupted program memory. by a MCLR Reset or a WDT Time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed. TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page TBLPTRU — — bit 21(1) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 57 TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 57 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 57 TABLAT Program Memory Table Latch 57 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 EECON2 EEPROM Control Register 2 (not a physical register) 59 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 59 IPR2 OSCFIP CMIP — EEIP BCL1IP HLVDIP TMR3IP CCP2IP 60 PIR2 OSCFIF CMIF — EEIF BCL1IF HLVDIF TMR3IF CCP2IF 60 PIE2 OSCFIE CMIE — EEIE BCL1IE HLVDIE TMR3IE CCP2IE 60 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: Bit 21 of TBLPTRU allows access to the device Configuration bits. © 2008 Microchip Technology Inc. DS39646C-page 95

PIC18F8722 FAMILY NOTES: DS39646C-page 96 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 7.0 EXTERNAL MEMORY BUS The bus is implemented with 28 pins, multiplexed across four I/O ports. Three ports (PORTD, PORTE Note: The External Memory Bus is not imple- and PORTH) are multiplexed with the address/data bus mented on PIC18F6527/6622/6627/6722 for a total of 20 available lines, while PORTJ is (64-pin) devices. multiplexed with the bus control signals. The External Memory Bus (EMB) allows the device to A list of the pins and their functions is provided in access external memory devices (such as Flash, Table7-1. EPROM, SRAM, etc.) as program or data memory. It supports both 8-bit and 16-bit Data Width modes and four address widths from 8 to 20 bits. TABLE 7-1: PIC18F8527/8622/8627/8722 EXTERNAL BUS – I/O PORT FUNCTIONS Name Port Bit External Memory Bus Function RD0/AD0 PORTD 0 Address bit 0 or Data bit 0 RD1/AD1 PORTD 1 Address bit 1 or Data bit 1 RD2/AD2 PORTD 2 Address bit 2 or Data bit 2 RD3/AD3 PORTD 3 Address bit 3 or Data bit 3 RD4/AD4 PORTD 4 Address bit 4 or Data bit 4 RD5/AD5 PORTD 5 Address bit 5 or Data bit 5 RD6/AD6 PORTD 6 Address bit 6 or Data bit 6 RD7/AD7 PORTD 7 Address bit 7 or Data bit 7 RE0/AD8 PORTE 0 Address bit 8 or Data bit 8 RE1/AD9 PORTE 1 Address bit 9 or Data bit 9 RE2/AD10 PORTE 2 Address bit 10 or Data bit 10 RE3/AD11 PORTE 3 Address bit 11 or Data bit 11 RE4/AD12 PORTE 4 Address bit 12 or Data bit 12 RE5/AD13 PORTE 5 Address bit 13 or Data bit 13 RE6/AD14 PORTE 6 Address bit 14 or Data bit 14 RE7/AD15 PORTE 7 Address bit 15 or Data bit 15 RH0/A16 PORTH 0 Address bit 16 RH1/A17 PORTH 1 Address bit 17 RH2/A18 PORTH 2 Address bit 18 RH3/A19 PORTH 3 Address bit 19 RJ0/ALE PORTJ 0 Address Latch Enable (ALE) Control pin RJ1/OE PORTJ 1 Output Enable (OE) Control pin RJ2/WRL PORTJ 2 Write Low (WRL) Control pin RJ3/WRH PORTJ 3 Write High (WRH) Control pin RJ4/BA0 PORTJ 4 Byte Address bit 0 (BA0) RJ5/CE PORTJ 5 Chip Enable (CE) Control pin RJ6/LB PORTJ 6 Lower Byte Enable (LB) Control pin RJ7/UB PORTJ 7 Upper Byte Enable (UB) Control pin Note: For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional multiplexed features may be available on some pins. © 2008 Microchip Technology Inc. DS39646C-page 97

PIC18F8722 FAMILY 7.1 External Memory Bus Control The operation of the EBDIS bit is also influenced by the program memory mode being used. This is discussed The operation of the interface is controlled by the in more detail in Section7.4 “Program Memory MEMCON register (Register7-1). This register is Modes and the External Memory Bus”. available in all program memory operating modes The WAIT bits allow for the addition of wait states to except Microcontroller mode. In this mode, the register external memory operations. The use of these bits is is disabled and cannot be written to. discussed in Section7.3 “Wait States”. The EBDIS bit (MEMCON<7>) controls the operation The WM bits select the particular operating mode used of the bus and related port functions. Clearing EBDIS when the bus is operating in 16-bit Data Width mode. enables the interface and disables the I/O functions of These are discussed in more detail in Section7.5 the ports, as well as any other functions multiplexed to “16-Bit Data Width Modes”. These bits have no effect those pins. Setting the bit enables the I/O ports and when an 8-bit Data Width mode is selected. other functions but allows the interface to override everything else on the pins when an external memory WM<1:0>: TBLWT Operation with 16-Bit Data Bus operation is required. By default, the external bus is Width Select bits always enabled and disables all other I/O. 1x = Word Write mode: TABLAT0 and TABLAT1 word output, WRH active when TABLAT1 written 01 = Byte Select mode: TABLAT data copied on both MSB and LSB; WRH and (UB or LB) will activate REGISTER 7-1: MEMCON: EXTERNAL MEMORY BUS CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EBDIS — WAIT1 WAIT0 — — WM1 WM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EBDIS: External Bus Disable bit 1 = External bus enabled when microcontroller accesses external memory; otherwise, all external bus drivers are mapped as I/O ports 0 = External bus always enabled, I/O ports are disabled bit 6 Unimplemented: Read as ‘0’ bit 5-4 WAIT<1:0>: Table Reads and Writes Bus Cycle Wait Count bits 11 = Table reads and writes will wait 0 TCY 10 = Table reads and writes will wait 1 TCY 01 = Table reads and writes will wait 2 TCY 00 = Table reads and writes will wait 3 TCY bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 WM<1:0>: TBLWT Operation with 16-Bit Data Bus Width Select bits 1 = Result was negative 0 = Result was positive DS39646C-page 98 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 7.2 Address and Data Width 7.2.1 21-BIT ADDRESSING PIC18F8527/8622/8627/8722 devices can be indepen- As an extension of 20-bit address width operation, the dently configured for different address and data widths External Memory Bus can also fully address a 2Mbyte on the same memory bus. Both address and data width memory space. This is done by using the Bus Address are set by Configuration bits in the CONFIG3L register. bit 0 (BA0) control line as the Least Significant bit of the As Configuration bits, this means that these options address. The UB and LB control signals may also be used with certain memory devices to select the upper can only be configured by programming the device and are not controllable in software. and lower bytes within a 16-bit wide data word. This addressing mode is available in both 8-bit and The BW bit selects an 8-bit or 16-bit data bus width. certain 16-bit Data Width modes. Additional details are Setting this bit (default) selects a data width of 16 bits. provided in Section7.5.3 “16-bit Byte Select Mode” The ADW<1:0> bits determine the address bus width. and Section7.6 “8-Bit Data Width Modes”. The available options are 20-bit (default), 16-bit, 12-bit and 8-bit. Selecting any of the options other than 20-bit 7.3 Wait States width makes a corresponding number of high-order lines available for I/O functions; these pins are no While it may be assumed that external memory devices longer affected by the setting of the EBDIS bit. For will operate at the microcontroller clock rate, this is example, selecting a 16-bit Address mode often not the case. In fact, many devices require longer (ADW<1:0>=10) disables A<19:16> and allows times to write or retrieve data than the time allowed by PORTH<3:0> to function without interruptions from the the execution of table read or table write operations. bus. Using smaller address widths allows users to tailor To compensate for this, the External Memory Bus can the memory bus to the size of the external memory be configured to add a fixed delay to each table opera- space for a particular design while freeing up pins for tion using the bus. Wait states are enabled by setting dedicated I/O operation. the WAITx bit. When enabled, the amount of delay is Because the ADW bits have the effect of disabling pins set by the WAIT<1:0> bits (MEMCON<5:4>). The delay for memory bus operations, it is important to always is based on multiples of microcontroller instruction select an address width at least equal to the data width. cycle time and are added following the instruction cycle If 8-bit or 12-bit address widths are used with a 16-bit when the table operation is executed. The range is data width, the upper bits of data will not be available from no delay to 3TCY (default value). on the bus. All combinations of address and data widths require multiplexing of address and data information on the same lines. The address and data multiplexing, as well as I/O ports made available by the use of smaller address widths, are summarized in Table7-2. TABLE 7-2: ADDRESS AND DATA LINES FOR DIFFERENT ADDRESS AND DATA WIDTHS Multiplexed Data and Address-Only Ports Available Data Width Address Width Address Lines (and Lines (and for I/O Corresponding Ports) Corresponding Ports) All of PORTE and 8-bit — PORTH AD<11:8> PORTE<7:4>, 12-bit (PORTE<3:0>) All of PORTH AD<7:0> 8-bit AD<15:8> 16-bit (PORTD<7:0>) All of PORTH (PORTE<7:0>) A<19:16>, AD<15:8> 20-bit (PORTH<3:0>, — PORTE<7:0>) 16-bit AD<15:0> — All of PORTH 16-bit (PORTD<7:0>, A<19:16> 20-bit — PORTE<7:0>) (PORTH<3:0>) © 2008 Microchip Technology Inc. DS39646C-page 99

PIC18F8722 FAMILY 7.4 Program Memory Modes and the 7.5 16-Bit Data Width Modes External Memory Bus In 16-Bit Data Width mode, the External Memory Bus PIC18F8527/8622/8627/8722 devices are capable of can be connected to external memories in three operating in any one of four program memory modes, different configurations: using combinations of on-chip and external program • 16-bit Byte Write memory. The functions of the multiplexed port pins • 16-bit Word Write depends on the program memory mode selected, as • 16-bit Byte Select well as the setting of the EBDIS bit. The configuration to be used is determined by the In Microcontroller Mode, the bus is not active and the WM1:WM0 bits in the MEMCON register pins have their port functions only. Writes to the (MEMCON<1:0>). These three different configurations MEMCOM register are not permitted. The Reset value allow the designer maximum flexibility in using both of EBDIS (‘0’) is ignored and EMB pins behave as I/O 8-bit and 16-bit devices with 16-bit data. ports. For all 16-bit modes, the Address Latch Enable (ALE) In Microprocessor Mode, the external bus is always pin indicates that the address bits AD<15:0> are active and the port pins have only the external bus available on the external memory interface bus. function. The value of EBDIS is ignored. Following the address latch, the Output Enable signal In Microprocessor with Boot Block or Extended (OE) will enable both bytes of program memory at once Microcontroller Mode, the external program memory to form a 16-bit instruction word. The Chip Enable bus shares I/O port functions on the pins. When the signal (CE) is active at any time that the microcontroller device is fetching or doing table read/table write opera- accesses external memory, whether reading or writing; tions on the external program memory space, the pins it is inactive (asserted high) whenever the device is in will have the external bus function. If the device is Sleep mode. fetching and accessing internal program memory loca- In Byte Select mode, JEDEC standard Flash memories tions only, the EBDIS control bit will change the pins will require BA0 for the byte address line and one I/O from external memory to I/O port functions. When line to select between Byte and Word mode. The other EBDIS = 0, the pins function as the external bus. When 16-bit modes do not need BA0. JEDEC standard static EBDIS = 1, the pins function as I/O ports. RAM memories will use the UB or LB signals for byte If the device fetches or accesses external memory selection. while EBDIS = 1, the pins will switch from I/O to exter- nal bus. If the EBDIS bit is set by a program executing from external memory, the action of setting the bit will be delayed until the program branches into the internal memory. At that time, the pins will change from external bus to I/O ports. If the device is executing out of internal memory when EBDIS = 0, the memory bus address/data and control pins will not be active. They will go to a state where the active address/data pins are tri-state; the CE, OE, WRH, WRL, UB and LB signals are ‘1’; and ALE and BA0 are ‘0’. Note that only those pins associated with the current address width are forced to tri-state; the other pins continue to function as I/O. In the case of 16-bit address width, for example, only AD<15:0> (PORTD and PORTE) are affected; A<19:16> (PORTH<3:0>) continue to function as I/O. In all external memory modes, the bus takes priority over any other peripherals that may share pins with it. This includes the Parallel Slave Port and serial commu- nications modules which would otherwise take priority over the I/O port. DS39646C-page 100 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 7.5.1 16-BIT BYTE WRITE MODE During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the Figure7-1 shows an example of 16-bit Byte Write AD<15:0> bus. The appropriate WRH or WRL control mode for PIC18F8527/8622/8627/8722 devices. This line is strobed on the LSb of the TBLPTR. mode is used for two separate 8-bit memories con- nected for 16-bit operation. This generally includes basic EPROM and Flash devices. It allows table writes to byte-wide external memories. FIGURE 7-1: 16-BIT BYTE WRITE MODE EXAMPLE D<7:0> PIC18F8X27/8X22 (MSB) (LSB) A<19:0> AD<7:0> 373 A<x:0> A<x:0> D<15:8> D<7:0> D<7:0> D<7:0> CE CE AD<15:8> 373 OE WR(2) OE WR(2) ALE A<19:16>(1) CE OE WRH WRL Address Bus Data Bus Control Lines Note 1: Upper-order address lines are used only for 20-bit address widths. 2: This signal only applies to table writes. See Section6.1 “Table Reads and Table Writes”. © 2008 Microchip Technology Inc. DS39646C-page 101

PIC18F8722 FAMILY 7.5.2 16-BIT WORD WRITE MODE During a TBLWT cycle to an odd address (TBLPTR<0>=1), the TABLAT data is presented on Figure7-2 shows an example of 16-bit Word Write the upper byte of the AD15:AD0 bus. The contents of mode for PIC18F8527/8622/8627/8722 devices. This the holding latch are presented on the lower byte of the mode is used for word-wide memories which includes AD<15:0> bus. some of the EPROM and Flash-type memories. This mode allows opcode fetches and table reads from all The WRH signal is strobed for each write cycle; the forms of 16-bit memory and table writes to any type of WRL pin is unused. The signal on the BA0 pin indicates word-wide external memories. This method makes a the Least Significant bit of TBLPTR but it is left distinction between TBLWT cycles to even or odd unconnected. Instead, the UB and LB signals are addresses. active to select both bytes. The obvious limitation to this method is that the table write must be done in pairs During a TBLWT cycle to an even address on a specific word boundary to correctly write a word (TBLPTR<0>=0), the TABLAT data is transferred to a location. holding latch and the external address data bus is tri-stated for the data portion of the bus cycle. No write signals are activated. FIGURE 7-2: 16-BIT WORD WRITE MODE EXAMPLE PIC18F8X27/8X22 AD<7:0> 373 A<20:1> A<x:0> JEDEC Word EPROM Memory D<15:0> D<15:0> CE OE WR(2) AD<15:8> 373 ALE A<19:16>(1) CE OE WRH Address Bus Data Bus Control Lines Note 1: Upper-order address lines are used only for 20-bit address widths. 2: This signal only applies to table writes. See Section6.1 “Table Reads and Table Writes”. DS39646C-page 102 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 7.5.3 16-BIT BYTE SELECT MODE Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC Figure7-3 shows an example of 16-bit Byte Select standard Flash memories require that a controller I/O mode. This mode allows table write operations to port pin be connected to the memory’s BYTE/WORD word-wide external memories with byte selection pin to provide the select signal. They also use the BA0 capability. This generally includes both word-wide signal from the controller as a byte address. JEDEC Flash and SRAM devices. standard static RAM memories, on the other hand, use During a TBLWT cycle, the TABLAT data is presented the UB or LB signals to select the byte. on the upper and lower byte of the AD<15:0> bus. The WRH signal is strobed for each write cycle; the WRL pin is not used. The BA0 or UB/LB signals are used to select the byte to be written, based on the Least Significant bit of the TBLPTR register. FIGURE 7-3: 16-BIT BYTE SELECT MODE EXAMPLE PIC18F8X27/8X22 A<20:1> AD<7:0> 373 A<x:1> JEDEC Word Flash Memory D<15:0> D<15:0> AD<15:8> 138(3) CE 373 A0 ALE BYTE/WORD OE WR(1) A<19:16>(2) OE WRH WRL A<20:1> A<x:1> JEDEC Word BA0 SRAM Memory I/O D<15:0> CE D<15:0> LB LB UB UB OE WR(1) Address Bus Data Bus Control Lines Note 1: This signal only applies to table writes. See Section6.1 “Table Reads and Table Writes”. 2: Upper-order address lines are used only for 20-bit address width. 3: Demultiplexing is only required when multiple memory devices are accessed. © 2008 Microchip Technology Inc. DS39646C-page 103

PIC18F8722 FAMILY 7.5.4 16-BIT MODE TIMING The presentation of control signals on the External Memory Bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure7-4 through Figure7-6. All examples assume either 20-bit or 21-bit address widths. FIGURE 7-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD WITH A 1 TCY WAIT STATE (MICROPROCESSOR MODE) Apparent Q Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q4 Q4 Q4 Q4 Actual Q Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:16> 00h 0Ch AD<15:0> 3AABh 0E55h CF33h 9256h BA0 ALE OE WRH ‘1’ ‘1’ WRL ‘1’ ‘1’ CE ‘0’ ‘0’ 1 TCY Wait Memory Opcode Fetch Table Read Cycle MOVLW 55h of 92h from 007556h from 199E67h Instruction TBLRD Cycle 1 TBLRD Cycle 2 Execution FIGURE 7-5: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:16> 0Ch AD<15:0> CF33h 9256h CE ALE OE Memory Opcode Fetch Opcode Fetch TBLRD 92h Opcode Fetch Cycle TBLRD * MOVLW 55h from 199E67h ADDLW 55h from 000100h from 000102h from 000104h Instruction INST(PC – 2) TBLRD Cycle 1 TBLRD Cycle 2 MOVLW Execution DS39646C-page 104 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 7-6: EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 A<19:16> 00h 00h AD<15:0> 3AAAh 0003h 3AABh 0E55h CE ALE OE Memory Opcode Fetch Opcode Fetch Sleep Mode, Bus Inactive(1) Cycle SLEEP MOVLW 55h from 007554h from 007556h Instruction Execution INST(PC – 2) SLEEP Note 1: Bus becomes inactive regardless of power-managed mode entered when SLEEP is executed. © 2008 Microchip Technology Inc. DS39646C-page 105

PIC18F8722 FAMILY 7.6 8-Bit Data Width Modes The Address Latch Enable (ALE) pin indicates that the address bits A<15:0> are available on the External In 8-Bit Data Width mode, the External Memory Bus Memory Interface bus. The Output Enable signal (OE) operates only in Multiplexed mode; that is, data shares will enable one byte of program memory for a portion of the 8 least significant bits of the address bus. the instruction cycle, then BA0 will change and the sec- Figure7-7 shows an example of 8-bit Multiplexed ond byte will be enabled to form the 16-bit instruction mode for PIC18F8527/8622/8627/8722 devices. This word. The least significant bit of the address, BA0, mode is used for a single 8-bit memory connected for must be connected to the memory devices in this 16-bit operation. The instructions will be fetched as two mode. The Chip Enable signal (CE) is active at any 8-bit bytes on a shared data/address bus. The two time that the microcontroller accesses external bytes are sequentially fetched within one instruction memory, whether reading or writing; it is inactive cycle (TCY). Therefore, the designer must choose (asserted high) whenever the device is in Sleep mode. external memory devices according to timing calcula- This generally includes basic EPROM and Flash tions based on 1/2 TCY (2 times the instruction rate). devices. It allows table writes to byte-wide external For proper memory speed selection, glue logic memories. propagation delay times must be considered along with The appropriate level of BA0 control line is strobed on setup and hold times. the LSb of the TBLPTR. FIGURE 7-7: 8-BIT MULTIPLEXED MODE EXAMPLE D<7:0> PIC18F8X27/8X22 A<19:0> AD<7:0> 373 A<x:1> ALE D<15:8> A0 D<7:0> AD<15:8>(1) CE A<19:16>(1) OE WR(2) BA0 CE OE WRL Address Bus Data Bus Control Lines Note 1: Upper-order address bits are used only for 20-bit address width. The upper AD byte is used for all address widths except 8-bit. 2: This signal only applies to table writes. See Section6.1 “Table Reads and Table Writes”. DS39646C-page 106 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 7.6.1 8-BIT MODE TIMING The presentation of control signals on the External Memory Bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure7-8 through Figure7-11. FIGURE 7-8: EXTERNAL BUS TIMING FOR TBLRD (MICROPROCESSOR MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 AD<15:8>, 03Ah 03Ah CCFh 03Ah A<19:16>(1) AD<7:0> AAh 08h 00h ABh 55h 0Eh 33h 92h ACh 55h 0Fh BA0 ALE OE WRH ‘1’ ‘1’ WRL ‘1’ ‘1’ Opcode Fetch Opcode Fetch Table Read 92h Opcode Fetch Memory Cycle TBLRD * MOVLW 55h from 199E67h ADDLW 55h from 007554h from 007556h from 007558h Instruction Execution INST(PC – 2) TBLRD Cycle 1 TBLRD Cycle 2 MOVLW Note 1: The address lines actually used depends on the address width selected. This example assumes 20-bit addressing. FIGURE 7-9: EXTERNAL BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:16>(1) 0Ch AD<15:8>(1) CFh AD<7:0> 33h 92h CE ALE OE Memory Opcode Fetch Opcode Fetch TBLRD 92h Opcode Fetch Cycle TBLRD * MOVLW 55h from 199E67h ADDLW 55h from 000100h from 000102h from 000104h Instruction Execution INST(PC – 2) TBLRD Cycle 1 TBLRD Cycle 2 MOVLW Note 1: The address lines actually used depends on the address width selected. This example assumes 20-bit addressing. © 2008 Microchip Technology Inc. DS39646C-page 107

PIC18F8722 FAMILY FIGURE 7-10: EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 A<19:16>(1) 00h 00h AD<15:8>(1) 3Ah 3Ah AD<7:0> AAh 00h 03h ABh 0Eh 55h BA0 CE ALE OE Memory Opcode Fetch Opcode Fetch Sleep Mode, Bus Inactive(2) Cycle SLEEP MOVLW 55h from 007554h from 007556h Instruction Execution INST(PC – 2) SLEEP Note 1: The address lines actually used depends on the address width selected. This example assumes 20-bit addressing. 2: Bus becomes inactive regardless of power-managed mode entered when SLEEP is executed. FIGURE 7-11: TYPICAL OPCODE FETCH, 8-BIT MODE Q1 Q2 Q3 Q4 AD<15:8>(1) 03Ah AD<7:0> 55h 0Eh 55h BA0 ALE OE ‘1’ ‘1’ WRL Memory Opcode Fetch MOVLW 55h from 007556h Cycle Note 1: The address lines actually used depends on the address width selected. This example assumes 16-bit addressing. DS39646C-page 108 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 7.7 Operation in Power-Managed In Sleep and Idle modes, the microcontroller core does Modes not need to access data; bus operations are sus- pended. The state of the external bus is frozen with the In alternate power-managed Run modes, the external address/data pins and most of the control pins holding bus continues to operate normally. If a clock source at the same state they were in when the mode was with a lower speed is selected, bus operations will run invoked. The only potential changes are the CE, LB at that speed. In these cases, excessive access times and UB pins which are held at logic high. for the external memory may result if wait states have been enabled and added to external memory opera- tions. If operations in a lower power Run mode are anticipated, users should provide in their applications for adjusting memory access times at the lower clock speeds. TABLE 7-3: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-MANAGED MODES Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page MEMCON(1) EBDIS — WAIT1 WAIT0 — — WM1 WM0 60 CONFIG3L(2) WAIT BW ABW1 ABW0 — — PM1 PM0 302 CONFIG3H MCLRE — — — — LPT1OSC ECCPMX(2) CCP2MX 303 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the External Memory Bus. Note 1: This register is not implemented on 64-pin devices. 2: Unimplemented in PIC18F6527/6622/6627/6722 devices. © 2008 Microchip Technology Inc. DS39646C-page 109

PIC18F8722 FAMILY NOTES: DS39646C-page 110 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 8.0 DATA EEPROM MEMORY 8.2 EECON1 and EECON2 Registers The data EEPROM is a nonvolatile memory array, Access to the data EEPROM is controlled by two separate from the data RAM and program memory, that registers: EECON1 and EECON2. These are the same is used for long-term storage of program data. It is not registers which control access to the program memory directly mapped in either the register file or program and are used in a similar manner for the data memory space, but is indirectly addressed through the EEPROM. Special Function Registers (SFRs). The EEPROM is The EECON1 register (Register) is the control register readable and writable during normal operation over the for data and program memory access. Control bit entire VDD range. EEPGD determines if the access will be to program or Five SFRs are used to read and write to the data data EEPROM memory. When clear, operations will EEPROM, as well as the program memory. They are: access the data EEPROM memory. When set, program memory is accessed. • EECON1 • EECON2 Control bit CFGS determines if the access will be to the • EEDATA Configuration registers or to program memory/data EEPROM memory. When set, subsequent operations • EEADR access Configuration registers. When CFGS is clear, • EEADRH the EEPGD bit selects either program Flash or data The data EEPROM allows byte read and write. When EEPROM memory. interfacing to the data memory block, EEDATA holds The WREN bit, when set, will allow a write operation. the 8-bit data for read/write and the EEADRH:EEADR On power-up, the WREN bit is clear. The WRERR bit is register pair holds the address of the EEPROM location set in hardware when the WREN bit is set and cleared being accessed. when the internal programming timer expires and the The EEPROM data memory is rated for high erase/write write operation is complete. cycle endurance. A byte write automatically erases the Note: During normal operation, the WRERR is location and writes the new data (erase-before-write). The write time is controlled by an on-chip timer; it will read as ‘1’. This can indicate that a write operation was prematurely terminated by vary with voltage and temperature, as well as from chip- a Reset, or a write operation was to-chip. Please refer to parameter D122 (Table28-1 in attempted improperly. Section28.0 “Electrical Characteristics”) for exact limits. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software; it is cleared in 8.1 EEADR and EEADRH Registers hardware at the completion of the write operation. The EEADRH:EEADR register pair is used to address Note: The EEIF interrupt flag bit (PIR2<4>) is set the data EEPROM for read and write operations. when the write is complete. It must be EEADRH holds the two MSbs of the address; the upper cleared in software. 6 bits are ignored. The 10-bit range of the pair can Control bits, RD and WR, start read and erase/write address a memory range of 1024 bytes (00h to 3FFh). operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section6.1 “Table Reads and Table Writes” regarding table reads. The EECON2 register is not a physical register. It is used exclusively in the memory write and erase sequences. Reading EECON2 will read all ‘0’s. © 2008 Microchip Technology Inc. DS39646C-page 111

PIC18F8722 FAMILY REGISTER 8-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS39646C-page 112 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 8.3 Reading the Data EEPROM Additionally, the WREN bit in EECON1 must be set to Memory enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code exe- To read a data memory location, the user must write the cution (i.e., runaway programs). The WREN bit should address to the EEADRH:EEADR register pair, clear the be kept clear at all times, except when updating the EEPGD control bit (EECON1<7>) and then set control EEPROM. The WREN bit is not cleared byhardware. bit, RD (EECON1<0>). The data is available on the After a write sequence has been initiated, EECON1, very next instruction cycle; therefore, the EEDATA EEADRH:EEADR and EEDATA cannot be modified. register can be read by the next instruction. EEDATA The WR bit will be inhibited from being set unless the will hold this value until another read operation, or until WREN bit is set. The WREN bit must be set on a it is written to by the user (during a write operation). previous instruction. Both WR and WREN cannot be The basic process is shown in Example8-1. set with the same instruction. At the completion of the write cycle, the WR bit is 8.4 Writing to the Data EEPROM cleared in hardware and the EEPROM Interrupt Flag bit Memory (EEIF) is set. The user may either enable this interrupt, or poll this bit. EEIF must be cleared by software. To write an EEPROM data location, the address must first be written to the EEADRH:EEADR register pair 8.5 Write Verify and the data written to the EEDATA register. The sequence in Example8-2 must be followed to initiate Depending on the application, good programming the write cycle. practice may dictate that the value written to the The write will not begin if this sequence is not exactly memory should be verified against the original value. followed (write 55h to EECON2, write 0AAh to This should be used in applications where excessive EECON2, then set WR bit) for each byte. It is strongly writes can stress bits near the specification limit. recommended that interrupts be disabled during this codesegment. EXAMPLE 8-1: DATA EEPROM READ MOVLW DATA_EE_ADDRH ; MOVWF EEADRH ; Upper bits of Data Memory Address to read MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Lower bits of Data Memory Address to read BCF EECON1, EEPGD ; Point to DATA memory BCF EECON1, CFGS ; Access EEPROM BSF EECON1, RD ; EEPROM Read MOVF EEDATA, W ; W = EEDATA EXAMPLE 8-2: DATA EEPROM WRITE MOVLW DATA_EE_ADDRH ; MOVWF EEADRH ; Upper bits of Data Memory Address to write MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Lower bits of Data Memory Address to write MOVLW DATA_EE_DATA ; MOVWF EEDATA ; Data Memory Value to write BCF EECON1, EPGD ; Point to DATA memory BCF EECON1, CFGS ; Access EEPROM BSF EECON1, WREN ; Enable writes BCF INTCON, GIE ; Disable Interrupts MOVLW 55h ; Required MOVWF EECON2 ; Write 55h Sequence MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BSF INTCON, GIE ; Enable Interrupts ; User code execution BCF EECON1, WREN ; Disable writes on write complete (EEIF set) © 2008 Microchip Technology Inc. DS39646C-page 113

PIC18F8722 FAMILY 8.6 Operation During Code-Protect 8.8 Using the Data EEPROM Data EEPROM memory has its own code-protect bits in The data EEPROM is a high-endurance, byte address- Configuration Words. External read and write able array that has been optimized for the storage of operations are disabled if code protection is enabled. frequently changing information (e.g., program variables or other data that are updated often). The microcontroller itself can both read and write to the Frequently changing values will typically be updated internal data EEPROM regardless of the state of the more often than specification D124. If this is not the code-protect Configuration bit. Refer to Section25.0 case, an array refresh must be performed. For this “Special Features of the CPU” for additional reason, variables that change infrequently (such as information. constants, IDs, calibration, etc.) should be stored in Flash program memory. 8.7 Protection Against Spurious Write A simple data EEPROM refresh routine is shown in There are conditions when the device may not want to Example8-3. write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have Note: If data EEPROM is only used to store constants and/or data that changes often, been implemented. On power-up, the WREN bit is cleared. In addition, writes to the EEPROM are blocked an array refresh is likely not required. See during the Power-up Timer period (TPWRT, specification D124. parameter33). The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch or software malfunction. EXAMPLE 8-3: DATA EEPROM REFRESH ROUTINE CLRF EEADR ; Start at address 0 CLRF EEADRH ; BCF EECON1, CFGS ; Set for memory BCF EECON1, EEPGD ; Set for Data EEPROM BCF INTCON, GIE ; Disable interrupts BSF EECON1, WREN ; Enable writes Loop ; Loop to refresh array BSF EECON1, RD ; Read current address MOVLW 55h ; MOVWF EECON2 ; Write 55h MOVLW 0AAh ; MOVWF EECON2 ; Write 0AAh BSF EECON1, WR ; Set WR bit to begin write BTFSC EECON1, WR ; Wait for write to complete BRA $-2 INCFSZ EEADR, F ; Increment address BRA LOOP ; Not zero, do it again INCFSZ EEADRH, F ; Increment the high address BRA LOOP ; Not zero, do it again BCF EECON1, WREN ; Disable writes BSF INTCON, GIE ; Enable interrupts DS39646C-page 114 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 8-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 EEADRH — — — — — — EEPROM Address 59 Register High Byte EEADR EEPROM Address Register Low Byte 59 EEDATA EEPROM Data Register 59 EECON2 EEPROM Control Register 2 (not a physical register) 59 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 59 IPR2 OSCFIP CMIP — EEIP BCL1IP HLVDIP TMR3IP CCP2IP 60 PIR2 OSCFIF CMIF — EEIF BCL1IF HLVDIF TMR3IF CCP2IF 60 PIE2 OSCFIE CMIE — EEIE BCL1IE HLVDIE TMR3IE CCP2IE 60 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2008 Microchip Technology Inc. DS39646C-page 115

PIC18F8722 FAMILY NOTES: DS39646C-page 116 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 9.0 8 x 8 HARDWARE MULTIPLIER EXAMPLE 9-1: 8 x 8 UNSIGNED MULTIPLY ROUTINE 9.1 Introduction MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 -> All PIC18 devices include an 8 x 8 hardware multiplier ; PRODH:PRODL as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS EXAMPLE 9-2: 8 x 8 SIGNED MULTIPLY register. ROUTINE Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the MOVF ARG1, W advantages of higher computational throughput and MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL reduced code size for multiplication algorithms and BTFSC ARG2, SB ; Test Sign Bit allows the PIC18 devices to be used in many applica- SUBWF PRODH, F ; PRODH = PRODH tions previously reserved for digital signal processors. ; - ARG1 A comparison of various hardware and software MOVF ARG2, W multiply operations, along with the savings in memory BTFSC ARG1, SB ; Test Sign Bit and execution time, is shown in Table9-1. SUBWF PRODH, F ; PRODH = PRODH ; - ARG2 9.2 Operation Example9-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example9-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the argu- ments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 9-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Program Time Cycles Routine Multiply Method Memory (Max) (Words) @ 40 MHz @ 10 MHz @ 4 MHz Without hardware multiply 13 69 6.9 μs 27.6 μs 69 μs 8 x 8 unsigned Hardware multiply 1 1 100 ns 400 ns 1 μs Without hardware multiply 33 91 9.1 μs 36.4 μs 91 μs 8 x 8 signed Hardware multiply 6 6 600 ns 2.4 μs 6 μs Without hardware multiply 21 242 24.2 μs 96.8 μs 242 μs 16 x 16 unsigned Hardware multiply 28 28 2.8 μs 11.2 μs 28 μs Without hardware multiply 52 254 25.4 μs 102.6 μs 254 μs 16 x 16 signed Hardware multiply 35 40 4.0 μs 16.0 μs 40 μs © 2008 Microchip Technology Inc. DS39646C-page 117

PIC18F8722 FAMILY Example9-3 shows the sequence to do a 16 x 16 EQUATION 9-2: 16 x 16 SIGNED unsigned multiplication. Equation9-1 shows the MULTIPLICATION algorithm that is used. The 32-bit result is stored in four ALGORITHM registers (RES3:RES0). RES3:RES0=ARG1H:ARG1L • ARG2H:ARG2L = (ARG1H • ARG2H • 216) + EQUATION 9-1: 16 x 16 UNSIGNED (ARG1H • ARG2L • 28) + MULTIPLICATION (ARG1L • ARG2H • 28) + ALGORITHM (ARG1L • ARG2L) + (-1 • ARG2H<7> • ARG1H:ARG1L • 216) + RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L (-1 • ARG1H<7> • ARG2H:ARG2L • 216) = (ARG1H • ARG2H • 216) + (ARG1H • ARG2L • 28) + (ARG1L • ARG2H • 28) + EXAMPLE 9-4: 16 x 16 SIGNED (ARG1L • ARG2L) MULTIPLY ROUTINE MOVF ARG1L, W EXAMPLE 9-3: 16 x 16 UNSIGNED MULWF ARG2L ; ARG1L * ARG2L -> MULTIPLY ROUTINE ; PRODH:PRODL MOVFF PRODH, RES1 ; MOVF ARG1L, W MOVFF PRODL, RES0 ; MULWF ARG2L ; ARG1L * ARG2L-> ; ; PRODH:PRODL MOVF ARG1H, W MOVFF PRODH, RES1 ; MULWF ARG2H ; ARG1H * ARG2H -> MOVFF PRODL, RES0 ; ; PRODH:PRODL ; MOVFF PRODH, RES3 ; MOVF ARG1H, W MOVFF PRODL, RES2 ; MULWF ARG2H ; ARG1H * ARG2H-> ; ; PRODH:PRODL MOVF ARG1L, W MOVFF PRODH, RES3 ; MULWF ARG2H ; ARG1L * ARG2H -> MOVFF PRODL, RES2 ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1L, W ADDWF RES1, F ; Add cross MULWF ARG2H ; ARG1L * ARG2H-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; MOVF ARG1H, W ; CLRF WREG ; MULWF ARG2L ; ARG1H * ARG2L -> ADDWFC RES3, F ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1H, W ; ADDWF RES1, F ; Add cross MULWF ARG2L ; ARG1H * ARG2L-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? CLRF WREG ; BRA SIGN_ARG1 ; no, check ARG1 ADDWFC RES3, F ; MOVF ARG1L, W ; SUBWF RES2 ; Example9-4 shows the sequence to do a 16 x 16 MOVF ARG1H, W ; signed multiply. Equation9-2 shows the algorithm SUBWFB RES3 used. The 32-bit result is stored in four registers ; (RES<3:0>). To account for the sign bits of the argu- SIGN_ARG1 ments, the MSb for each argument pair is tested and BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? the appropriate subtractions are done. BRA CONT_CODE ; no, done MOVF ARG2L, W ; SUBWF RES2 ; MOVF ARG2H, W ; SUBWFB RES3 ; CONT_CODE : DS39646C-page 118 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 10.0 INTERRUPTS When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are The PIC18F8722 family of devices have multiple compatible with PIC® mid-range devices. In interrupt sources and an interrupt priority feature that Compatibility mode, the interrupt priority bits for each allows most interrupt sources to be assigned a high- source have no effect. INTCON<6> is the PEIE bit, priority level or a low-priority level. The high-priority which enables/disables all peripheral interrupt sources. interrupt vector is at 0008h and the low-priority interrupt INTCON<7> is the GIE bit, which enables/disables all vector is at 0018h. High-priority interrupt events will interrupt sources. All interrupts branch to address interrupt any low-priority interrupts that may be in 0008h in Compatibility mode. progress. When an interrupt is responded to, the global interrupt There are ten registers which are used to control enable bit is cleared to disable further interrupts. If the interrupt operation. These registers are: IPEN bit is cleared, this is the GIE bit. If interrupt priority • RCON levels are used, this will be either the GIEH or GIEL bit. • INTCON High-priority interrupt sources can interrupt a low- priority interrupt. Low-priority interrupts are not • INTCON2 processed while high-priority interrupts are in progress. • INTCON3 • PIR1, PIR2, PIR3 The return address is pushed onto the stack and the • PIE1, PIE2, PIE3 PC is loaded with the interrupt vector address (0008h or 0018h). Once in the Interrupt Service Routine, the • IPR1, IPR2, IPR3 source(s) of the interrupt can be determined by polling It is recommended that the Microchip header files the interrupt flag bits. The interrupt flag bits must be supplied with MPLAB® IDE be used for the symbolic bit cleared in software before re-enabling interrupts to names in these registers. This allows the assembler/ avoid recursive interrupts. compiler to automatically take care of the placement of The “return from interrupt” instruction, RETFIE, exits these bits within the specified register. the interrupt routine and sets the GIE bit (GIEH or GIEL In general, interrupt sources have three bits to control if priority levels are used), which re-enables interrupts. their operation. They are: For external interrupt events, such as the INTx pins or • Flag bit to indicate that an interrupt event the PORTB input change interrupt, the interrupt latency occurred will be three to four instruction cycles. The exact • Enable bit that allows program execution to latency is the same for one or two-cycle instructions. branch to the interrupt vector address when the Individual interrupt flag bits are set, regardless of the flag bit is set status of their corresponding enable bit or the GIE bit. • Priority bit to select high priority or low priority Note: Do not use the MOVFF instruction to modify The interrupt priority feature is enabled by setting the any of the interrupt control registers while IPEN bit (RCON<7>). When interrupt priority is any interrupt is enabled. Doing so may enabled, there are two bits which enable interrupts cause erratic microcontroller behavior. globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 0008h or 0018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits. © 2008 Microchip Technology Inc. DS39646C-page 119

PIC18F8722 FAMILY FIGURE 10-1: PIC18F8722 FAMILY INTERRUPT LOGIC TMR0IF Wake-up if in TMR0IE Idle or Sleep modes TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE Interrupt to CPU INT1IP Vector to Location INT2IF PIR1<7:0> INT2IE 0008h PIE1<7:0> INT2IP IPR1<7:0> INT3IF INT3IE INT3IP GIEH/GIE PIR2<7:6, 4:0> PIE2<7:6, 4:0> IPR2<7:6, 4:0> IPEN PIR3<7:0> IPEN PIE3<7:0> IPR3<7:0> GIEL/PEIE IPEN High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 4:0> PIE2<7:6, 4:0> IPR2<7:6, 4:0> Interrupt to CPU PIR3<7:0> TTMMRR00IIEF IPEN V00e1c8tohr to Location PIE3<7:0> TMR0IP IPR3<7:0> RBIF RBIE RBIP GIEH/GIE GIEL/PEIE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP DS39646C-page 120 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 10.1 INTCON Registers Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of The INTCON registers are readable and writable its corresponding enable bit or the global registers which contain various enable, priority and flag interrupt enable bit. User software should bits. ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. REGISTER 10-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high-priority interrupts 0 = Disables all interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low-priority peripheral interrupts 0 = Disables all low-priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit(1) 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2008 Microchip Technology Inc. DS39646C-page 121

PIC18F8722 FAMILY REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 INTEDG3: External Interrupt 3 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 INT3IP: INT3 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39646C-page 122 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY REGISTER 10-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 INT3IE: INT3 External Interrupt Enable bit 1 = Enables the INT3 external interrupt 0 = Disables the INT3 external interrupt bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 INT3IF: INT3 External Interrupt Flag bit 1 = The INT3 external interrupt occurred (must be cleared in software) 0 = The INT3 external interrupt did not occur bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2008 Microchip Technology Inc. DS39646C-page 123

PIC18F8722 FAMILY 10.2 PIR Registers Note1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of The PIR registers contain the individual flag bits for the its corresponding enable bit or the Global peripheral interrupts. Due to the number of peripheral Interrupt Enable bit, GIE (INTCON<7>). interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. REGISTER 10-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RC1IF: EUSART1 Receive Interrupt Flag bit 1 = The EUSART1 receive buffer, RCREG1, is full (cleared when RCREG1 is read) 0 = The EUSART1 receive buffer is empty bit 4 TX1IF: EUSART1 Transmit Interrupt Flag bit 1 = The EUSART1 transmit buffer, TXREG1, is empty (cleared when TXREG1 is written) 0 = The EUSART1 transmit buffer is full bit 3 SSP1IF: MSSP1 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: ECCP1 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow DS39646C-page 124 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY REGISTER 10-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF CMIF — EEIF BCL1IF HLVDIF TMR3IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = Device clock operating bit 6 CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed bit 5 Unimplemented: Read as ‘0’ bit 4 EEIF: EEPROM or Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared in software) 0 = The write operation is not complete or has not been started bit 3 BCL1IF: MSSP1 Bus Collision Interrupt Flag bit 1 = A bus collision occurred while the MSSP1 module configured in I2C™ Master mode was transmitting (must be cleared in software) 0 = No bus collision occurred bit 2 HLVDIF: High/Low-Voltage Detect Interrupt Flag bit 1 = A low-voltage condition occurred (must be cleared in software) 0 = The device voltage is above the Low-Voltage Detect trip point bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow bit 0 CCP2IF: ECCP2 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. © 2008 Microchip Technology Inc. DS39646C-page 125

PIC18F8722 FAMILY REGISTER 10-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IF: MSSP2 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 6 BCL2IF: MSSP2 Bus Collision Interrupt Flag bit 1 = A bus collision has occurred while the MSSP2 module configured in I2C™ master was transmitting (must be cleared in software) 0 = No bus collision occurred bit 5 RC2IF: EUSART2 Receive Interrupt Flag bit 1 = The EUSART2 receive buffer, RCREG2, is full (cleared when RCREG2 is read) 0 = The EUSART2 receive buffer is empty bit 4 TX2IF: EUSART2 Transmit Interrupt Flag bit 1 = The EUSART2 transmit buffer, TXREG2, is empty (cleared when TXREG2 is written) 0 = The EUSART2 transmit buffer is full bit 3 TMR4IF: TMR4 to PR4 Match Interrupt Flag bit 1 = TMR4 to PR4 match occurred (must be cleared in software) 0 = No TMR4 to PR4 match occurred bit 2 CCP5IF: CCP5 Interrupt Flag bit Capture mode: 1 = A TMR register capture occurred (must be cleared in software) 0 = No TMR register capture occurred Compare mode: 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM Mode: bit 1 CCP4IF: CCP4 Interrupt Flag bit Capture mode: 1 = A TMR register capture occurred (must be cleared in software) 0 = No TMR register capture occurred Compare mode: 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM mode: Not used in PWM mode. bit 0 CCP3IF: ECCP3 Interrupt Flag bit Capture mode: 1 = A TMR register capture occurred (must be cleared in software) 0 = No TMR register capture occurred Compare mode: 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM mode: Not used in PWM mode. DS39646C-page 126 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 10.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 10-7: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RC1IE: EUSART1 Receive Interrupt Enable bit 1 = Enables the EUSART1 receive interrupt 0 = Disables the EUSART1 receive interrupt bit 4 TX1IE: EUSART1 Transmit Interrupt Enable bit 1 = Enables the EUSART1 transmit interrupt 0 = Disables the EUSART1 transmit interrupt bit 3 SSP1IE: MSSP1 Interrupt Enable bit 1 = Enables the MSSP1 interrupt 0 = Disables the MSSP1 interrupt bit 2 CCP1IE: ECCP1 Interrupt Enable bit 1 = Enables the ECCP1 interrupt 0 = Disables the ECCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt © 2008 Microchip Technology Inc. DS39646C-page 127

PIC18F8722 FAMILY REGISTER 10-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE CMIE — EEIE BCL1IE HLVDIE TMR3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 Unimplemented: Read as ‘0’ bit 4 EEIE: Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 BCL1IE: MSSP1 Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: ECCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS39646C-page 128 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY REGISTER 10-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IE: MSSP2 Interrupt Enable bit 1 = Enables the MSSP2 interrupt 0 = Disables the MSSP2 interrupt bit 6 BCL2IE: MSSP2 Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 RC2IE: EUSART2 Receive Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 TX2IE: EUSART2 Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 CCP5IE: CCP5 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 CCP4IE: CCP4 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP3IE: ECCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled © 2008 Microchip Technology Inc. DS39646C-page 129

PIC18F8722 FAMILY 10.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 10-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RC1IP: EUSART1 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX1IP: EUSART1 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSP1IP: MSSP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: ECCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS39646C-page 130 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY REGISTER 10-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP CMIP — EEIP BCL1IP HLVDIP TMR3IP CCP2IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 EEIP: Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCL1IP: MSSP1 Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 HLVDIP: High/Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2008 Microchip Technology Inc. DS39646C-page 131

PIC18F8722 FAMILY REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IP: MSSP2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 BCL2IP: MSSP2 Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RC2IP: EUSART2 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX2IP: EUSART2 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TMR4IP: TMR4 to PR4 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP5IP: CCP5 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 CCP4IP: CCP4 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP3IP: ECCP3 Interrupt Priority bit 1 = High priority 0 = Low priority DS39646C-page 132 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 10.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN). REGISTER 10-13: RCON: RESET CONTROL REGISTER R/W-0 R/W-1 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN SBOREN — RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: Software BOR Enable bit For details of bit operation and Reset state, see Register4-1. bit 5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register4-1. bit 3 TO: Watchdog Timer Time-out Flag bit For details of bit operation, see Register4-1. bit 2 PD: Power-Down Detection Flag bit For details of bit operation, see Register4-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register4-1. © 2008 Microchip Technology Inc. DS39646C-page 133

PIC18F8722 FAMILY 10.6 INTx Pin Interrupts 10.7 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1, RB2/ In 8-bit mode (which is the default), an overflow in the INT2 and RB3/INT3 pins are edge-triggered. If the TMR0 register (FFh→00h) will set flag bit, TMR0IF. In corresponding INTEDGx bit in the INTCON2 register is 16-bit mode, an overflow in the TMR0H:TMR0L register set (= 1), the interrupt is triggered by a rising edge; if pair (FFFFh → 0000h) will set TMR0IF. The interrupt can the bit is clear, the trigger is on the falling edge. When be enabled/disabled by setting/clearing enable bit, a valid edge appears on the RBx/INTx pin, the TMR0IE (INTCON<5>). Interrupt priority for Timer0 is corresponding flag bit, INTxIF, is set. This interrupt can determined by the value contained in the interrupt be disabled by clearing the corresponding enable bit, priority bit, TMR0IP (INTCON2<2>). See Section12.0 INTxIE. Flag bit, INTxIF, must be cleared in software in “Timer0 Module” for further details on the Timer0 the Interrupt Service Routine before re-enabling the module. interrupt. 10.8 PORTB Interrupt-on-Change All external interrupts (INT0, INT1, INT2 and INT3) can wake-up the processor from the power-managed An input change on PORTB<7:4> sets flag bit, RBIF modes if bit INTxIE was set prior to going into power- (INTCON<0>). The interrupt can be enabled/disabled managed modes. If the Global Interrupt Enable bit, by setting/clearing enable bit, RBIE (INTCON<3>). GIE, is set, the processor will branch to the interrupt Interrupt priority for PORTB interrupt-on-change is vector following wake-up. determined by the value contained in the interrupt Interrupt priority for INT1, INT2 and INT3 is determined priority bit, RBIP (INTCON2<0>). by the value contained in the interrupt priority bits, INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and 10.9 Context Saving During Interrupts INT3IP (INTCON2<1>). There is no priority bit associated with INT0. It is always a high-priority During interrupts, the return PC address is saved on interrupt source. the stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (see Section5.3 “Data Memory Organization”), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user’s application, other registers may also need to be saved. Example10-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 10-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in virtual bank MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR ; Restore BSR MOVF W_TEMP, W ; Restore WREG MOVFF STATUS_TEMP, STATUS ; Restore STATUS DS39646C-page 134 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 11.0 I/O PORTS 11.1 PORTA, TRISA and LATA Registers Depending on the device selected and features enabled, there are up to nine ports available. Some PORTA is an 8-bit wide, bidirectional port. The corre- pins of the I/O ports are multiplexed with an alternate sponding data direction register is TRISA. Setting a function from the peripheral features on the device. In TRISA bit (= 1) will make the corresponding PORTA pin general, when a peripheral is enabled, that pin may not an input (i.e., put the corresponding output driver in a be used as a general purpose I/O pin. high-impedance mode). Clearing a TRISA bit (= 0) will Each port has three registers for its operation. These make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). registers are: • TRIS register (Data Direction register) Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. • Port register (reads the levels on the pins of the device) The Data Latch register (LATA) is also memory • LAT register (output latch) mapped. Read-modify-write operations on the LATA register read and write the latched output value for The Data Latch (LAT register) is useful for PORTA. read-modify-write operations on the value that the I/O pins are driving. The RA4 pin is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. Pins RA6 A simplified model of a generic I/O port, without the and RA7 are multiplexed with the main oscillator pins; interfaces to other peripherals, is shown in Figure11-1. they are enabled as oscillator or I/O pins by the selec- tion of the main oscillator in the Configuration register FIGURE 11-1: GENERIC I/O PORT (see Section25.1 “Configuration Bits” for details). OPERATION When they are not used as port pins, RA6 and RA7 and their associated TRIS and LAT bits are read as ‘0’. RD LAT The other PORTA pins are multiplexed with the analog VREF+ and VREF- inputs. The operation of pins Data Bus RA5:RA0 as A/D converter inputs is selected by D Q clearing or setting the PCFG<3:0> control bits in the WR LAT I/O pin(1) ADCON1 register. or Port CKx Note: On a Power-on Reset, RA5 and RA<3:0> Data Latch are configured as analog inputs and read D Q as ‘0’. RA4 is configured as a digital input. WR TRIS The RA4/T0CKI pin is a Schmitt Trigger input and an CKx open-drain output. All other PORTA pins have TTL TRIS Latch Input input levels and full CMOS output drivers. Buffer The TRISA register controls the direction of the PORTA RD TRIS pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are Q D maintained set when using them as analog inputs. ENEN EXAMPLE 11-1: INITIALIZING PORTA RD Port CLRF PORTA ; Initialize PORTA by ; clearing output Note1: I/O pins have diode protection to VDD and VSS. ; data latches CLRF LATA ; Alternate method ; to clear output ; data latches MOVLW 0Fh ; Configure A/D MOVWF ADCON1 ; for digital inputs MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs © 2008 Microchip Technology Inc. DS39646C-page 135

PIC18F8722 FAMILY TABLE 11-1: PORTA FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RA0/AN0 RA0 0 O DIG LATA<0> data output; not affected by analog input. 1 I TTL PORTA<0> data input; disabled when analog input enabled. AN0 1 I ANA A/D input channel 0. Default input configuration on POR; does not affect digital output. RA1/AN1 RA1 0 O DIG LATA<1> data output; not affected by analog input. 1 I TTL PORTA<1> data input; disabled when analog input enabled. AN1 1 I ANA A/D input channel 1. Default input configuration on POR; does not affect digital output. RA2/AN2/VREF- RA2 0 O DIG LATA<2> data output; not affected by analog input. 1 I TTL PORTA<2> data input. Disabled when analog functions enabled. AN2 1 I ANA A/D input channel 2. Default input configuration on POR. VREF- 1 I ANA Comparator voltage reference low input and A/D voltage reference low input. RA3/AN3/VREF+ RA3 0 O DIG LATA<3> data output; not affected by analog input. 1 I TTL PORTA<3> data input; disabled when analog input enabled. AN3 1 I ANA A/D input channel 3. Default input configuration on POR. VREF+ 1 I ANA Comparator voltage reference high input and A/D voltage reference high input. RA4/T0CKI RA4 0 O DIG LATA<4> data output. 1 I ST PORTA<4> data input; default configuration on POR. T0CKI x I ST Timer0 clock input. RA5/AN4/HLVDIN RA5 0 O DIG LATA<5> data output; not affected by analog input. 1 I TTL PORTA<5> data input; disabled when analog input enabled. AN4 1 I ANA A/D input channel 4. Default configuration on POR. HLVDIN 1 I ANA High/Low-Voltage Detect external trip point input. OSC2/CLKO/RA6 OSC2 x O ANA Main oscillator feedback output connection (XT, HS, HSPLL and LP modes). CLKO x O DIG System cycle clock output (FOSC/4) in all oscillator modes except RC, INTIO7 and EC. RA6 0 O DIG LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only. 1 I TTL PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only. OSC1/CLKI/RA7 OSC1 x I ANA Main oscillator input connection. CLKI x I ANA Main clock input connection. RA7 0 O DIG LATA<7> data output. Disabled in external oscillator modes. 1 I TTL PORTA<7> data input. Disabled in external oscillator modes. Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST= Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). TABLE 11-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 61 LATA LATA7(1) LATA6(1) LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 60 TRISA TRISA7(1) TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 60 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 59 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA<7:6> and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. DS39646C-page 136 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 11.2 PORTB, TRISB and Four of the PORTB pins (RB<7:4>) have an LATB Registers interrupt-on-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any PORTB is an 8-bit wide, bidirectional port. The corre- RB7:RB4 pin configured as an output is excluded from sponding Data Direction register is TRISB. Setting a the interrupt-on-change comparison). The input pins (of TRISB bit (= 1) will make the corresponding PORTB RB7:RB4) are compared with the old value latched on pin an input (i.e., put the corresponding output driver in the last read of PORTB. The “mismatch” outputs of a high-impedance mode). Clearing a TRISB bit (= 0) RB7:RB4 are ORed together to generate the RB Port will make the corresponding PORTB pin an output Change Interrupt with Flag bit, RBIF (INTCON<0>). (i.e., put the contents of the output latch on the This interrupt can wake the device from selected pin). power-managed modes. The user, in the Interrupt The Data Latch register (LATB) is also memory Service Routine, can clear the interrupt in the following mapped. Read-modify-write operations on the LATB manner: register read and write the latched output value for a) Any read or write of PORTB (except with the PORTB. MOVSF, MOVSS, MOVFF (ANY), PORTB instruction). This will end the mismatch EXAMPLE 11-2: INITIALIZING PORTB condition. CLRF PORTB ; Initialize PORTB by b) Clear flag bit, RBIF. ; clearing output A mismatch condition will continue to set flag bit, RBIF. ; data latches CLRF LATB ; Alternate method Reading PORTB will end the mismatch condition and ; to clear output allow flag bit, RBIF, to be cleared. ; data latches The interrupt-on-change feature is recommended for MOVLW 0CFh ; Value used to wake-up on key depression operation and operations ; initialize data where PORTB is only used for the interrupt-on-change ; direction MOVWF TRISB ; Set RB<3:0> as inputs feature. Polling of PORTB is not recommended while ; RB<5:4> as outputs using the interrupt-on-change feature. ; RB<7:6> as inputs For 80-pin devices, RB3 can be configured as the alternate peripheral pin for the ECCP2 module by Each of the PORTB pins has a weak internal pull-up. A clearing the CCP2MX Configuration bit. This applies single control bit can turn on all the pull-ups. This is only when the device is in one of the operating modes performed by clearing bit RBPU (INTCON2<7>). The other than the default Microcontroller mode. If the weak pull-up is automatically turned off when the port device is in Microcontroller mode, the alternate pin is configured as an output. The pull-ups are assignment for ECCP2 is RE7. As with other ECCP2 disabled on a Power-on Reset. configurations, the user must ensure that the TRISB<3> bit is set appropriately for the intended operation. © 2008 Microchip Technology Inc. DS39646C-page 137

PIC18F8722 FAMILY TABLE 11-3: PORTB FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RB0/INT0/FLT0 RB0 0 O DIG LATB<0> data output. 1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. INT0 1 I ST External interrupt 0 input. FLT0 1 I ST ECCPx PWM Fault input, enabled in software. RB1/INT1 RB1 0 O DIG LATB<1> data output. 1 I TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared. INT1 1 I ST External interrupt 1 input. RB2/INT2 RB2 0 O DIG LATB<2> data output. 1 I TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared. INT2 1 I ST External interrupt 2 input. RB3/INT3/ RB3 0 O DIG LATB<3> data output. ECCP2/P2A 1 I TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared and capture input is disabled. INT3 1 I ST External interrupt 3 input. ECCP2(1) 0 O DIG ECCP2 compare output and ECCP2 PWM output. Takes priority over port data. 1 I ST ECCP2 capture input. P2A(1) 0 O DIG ECCP2 Enhanced PWM output, channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RB4/KBI0 RB4 0 O DIG LATB<4> data output. 1 I TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared. KBI0 1 I TTL Interrupt-on-pin change. RB5/KBI1/PGM RB5 0 O DIG LATB<5> data output 1 I TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared. KBI1 1 I TTL Interrupt-on-pin change. PGM x I ST Single-Supply Programming mode entry (ICSP). Enabled by LVP Configuration bit; all other pin functions disabled. RB6/KBI2/PGC RB6 0 O DIG LATB<6> data output. 1 I TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared. KBI2 1 I TTL Interrupt-on-pin change. PGC x I ST Serial execution (ICSP™) clock input for ICSP and ICD operation(2). RB7/KBI3/PGD RB7 0 O DIG LATB<7> data output. 1 I TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared. KBI3 1 I TTL Interrupt-on-pin change. PGD x O DIG Serial execution data output for ICSP and ICD operation(2). x I ST Serial execution data input for ICSP and ICD operation(2). Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared (Microprocessor, Extended Microcontroller and Microcontroller with Boot Block modes, 80-pin devices only). Default assignment is RC1. 2: All other pin functions are disabled when ICSP or ICD operations are enabled. DS39646C-page 138 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 11-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 60 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 60 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 60 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 57 INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 57 Legend: Shaded cells are not used by PORTB. © 2008 Microchip Technology Inc. DS39646C-page 139

PIC18F8722 FAMILY 11.3 PORTC, TRISC and Note: On a Power-on Reset, these pins are LATC Registers configured as digital inputs. PORTC is an 8-bit wide, bidirectional port. The corre- The contents of the TRISC register are affected by sponding Data Direction register is TRISC. Setting a peripheral overrides. Reading TRISC always returns TRISC bit (= 1) will make the corresponding PORTC the current contents, even though a peripheral device pin an input (i.e., put the corresponding output driver in may be overriding one or more of the pins. a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output EXAMPLE 11-3: INITIALIZING PORTC (i.e., put the contents of the output latch on the CLRF PORTC ; Initialize PORTC by selected pin). ; clearing output The Data Latch register (LATC) is also memory ; data latches mapped. Read-modify-write operations on the LATC CLRF LATC ; Alternate method register read and write the latched output value for ; to clear output PORTC. ; data latches MOVLW 0CFh ; Value used to PORTC is multiplexed with several peripheral ; initialize data functions. All port pins have Schmitt Trigger input ; direction buffers. RC1 is normally configured by Configuration MOVWF TRISC ; Set RC<3:0> as inputs bit, CCP2MX, as the default peripheral pin of the ; RC<5:4> as outputs ECCP2 module (default/erased state, CCP2MX = 1). ; RC<7:6> as inputs When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. DS39646C-page 140 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 11-5: PORTC FUNCTIONS TRIS Pin Name Function I/O I/O Type Description Setting RC0/T1OSO/T13CKI RC0 0 O DIG LATC<0> data output. 1 I ST PORTC<0> data input. T1OSO x O ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled. Disables digital I/O. T13CKI 1 I ST Timer1/Timer3 counter input. RC1/T1OSI/ RC1 0 O DIG LATC<1> data output. ECCP2/P2A 1 I ST PORTC<1> data input. T1OSI x I ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled. Disables digital I/O. ECCP2(1) 0 O DIG ECCP2 compare output and ECCP2 PWM output. Takes priority over port data. 1 I ST ECCP2 capture input. P2A(1) 0 O DIG ECCP2 Enhanced PWM output, channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RC2/ECCP1/P1A RC2 0 O DIG LATC<2> data output. 1 I ST PORTC<2> data input. ECCP1 0 O DIG ECCP1 compare output and ECCP1 PWM output. Takes priority over port data. 1 I ST ECCP1 capture input. P1A 0 O DIG ECCP1 Enhanced PWM output, channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RC3/SCK1/SCL1 RC3 0 O DIG LATC<3> data output. 1 I ST PORTC<3> data input. SCK1 0 O DIG SPI clock output (MSSP1 module). Takes priority over port data. 1 I ST SPI clock input (MSSP1 module). SCL1 0 O DIG I2C™ clock output (MSSP1 module). Takes priority over port data. 1 I I2C/SMB I2C clock input (MSSP1 module); input type depends on module setting. RC4/SDI1/SDA1 RC4 0 O DIG LATC<4> data output. 1 I ST PORTC<4> data input. SDI1 1 I ST SPI data input (MSSP1 module). SDA1 1 O DIG I2C data output (MSSP1 module). Takes priority over port data. 1 I I2C/SMB I2C data input (MSSP1 module); input type depends on module setting. RC5/SDO1 RC5 0 O DIG LATC<5> data output. 1 I ST PORTC<5> data input. SDO1 0 O DIG SPI data output (MSSP1 module). Takes priority over port data. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for ECCP2 when CCP2MX Configuration bit is set. © 2008 Microchip Technology Inc. DS39646C-page 141

PIC18F8722 FAMILY TABLE 11-5: PORTC FUNCTIONS (CONTINUED) TRIS Pin Name Function I/O I/O Type Description Setting RC6/TX1/CK1 RC6 0 O DIG LATC<6> data output. 1 I ST PORTC<6> data input. TX1 0 O DIG Asynchronous serial transmit data output (EUSART1 module). Takes priority over port data. CK1 0 O DIG Synchronous serial clock output (EUSART1 module). Takes priority over port data. 1 I ST Synchronous serial clock input (EUSART1 module). RC7/RX1/DT1 RC7 0 O DIG LATC<7> data output. 1 I ST PORTC<7> data input. RX1 1 I ST Asynchronous serial receive data input (EUSART1 module) DT1 1 O DIG Synchronous serial data output (EUSART1 module). Takes priority over port data. User must configure as input. 1 I ST Synchronous serial data input (EUSART1 module). User must configure as an input. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for ECCP2 when CCP2MX Configuration bit is set. TABLE 11-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 60 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 60 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60 DS39646C-page 142 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 11.4 PORTD, TRISD and PORTD can also be configured to function as an 8-bit LATD Registers wide parallel microprocessor port by setting the PSPMODE control bit (PSPCON<4>). In this mode, PORTD is an 8-bit wide, bidirectional port. The corre- parallel port data takes priority over other digital I/O (but sponding Data Direction register is TRISD. Setting a not the external memory interface). When the parallel TRISD bit (= 1) will make the corresponding PORTD port is active, the input buffers are TTL. For more pin an input (i.e., put the corresponding output driver in information, refer to Section11.10 “Parallel Slave a high-impedance mode). Clearing a TRISD bit (= 0) Port”. will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the EXAMPLE 11-4: INITIALIZING PORTD selected pin). CLRF PORTD ; Initialize PORTD by The Data Latch register (LATD) is also memory ; clearing output mapped. Read-modify-write operations on the LATD ; data latches register read and write the latched output value for CLRF LATD ; Alternate method PORTD. ; to clear output ; data latches All pins on PORTD are implemented with Schmitt MOVLW 0CFh ; Value used to Trigger input buffers. Each pin is individually ; initialize data configurable as an input or output. ; direction MOVWF TRISD ; Set RD<3:0> as inputs Note: On a Power-on Reset, these pins are ; RD<5:4> as outputs configured as digital inputs. ; RD<7:6> as inputs In 80-pin devices, PORTD is multiplexed with the system bus as part of the external memory interface. I/O port and other functions are only available when the interface is disabled by setting the EBDIS bit (MEMCON<7>). When the interface is enabled, PORTD is the low-order byte of the multiplexed address/data bus (AD<7:0>). The TRISD bits are also overridden. © 2008 Microchip Technology Inc. DS39646C-page 143

PIC18F8722 FAMILY TABLE 11-7: PORTD FUNCTIONS TRIS Pin Name Function I/O I/O Type Description Setting RD0/AD0/PSP0 RD0 0 O DIG LATD<0> data output. 1 I ST PORTD<0> data input. AD0(1) x O DIG External memory interface, address/data bit 0 output. Takes priority over PSP and port data. x I TTL External memory interface, data bit 0 input. PSP0 x O DIG PSP read data output (LATD<0>). Takes priority over port data. x I TTL PSP write data input. RD1/AD1/PSP1 RD1 0 O DIG LATD<1> data output. 1 I ST PORTD<1> data input. AD1(1) x O DIG External memory interface, address/data bit 1 output. Takes priority over PSP and port data. x I TTL External memory interface, data bit 1 input. PSP1 x O DIG PSP read data output (LATD<1>). Takes priority over port data. x I TTL PSP write data input. RD2/AD2/PSP2 RD2 0 O DIG LATD<2> data output. 1 I ST PORTD<2> data input. AD2(1) x O DIG External memory interface, address/data bit 2 output. Takes priority over PSP and port data. x I TTL External memory interface, data bit 2 input. PSP2 x O DIG PSP read data output (LATD<2>). Takes priority over port data. x I TTL PSP write data input. RD3/AD3/PSP3 RD3 0 O DIG LATD<3> data output. 1 I ST PORTD<3> data input. AD3(1) x O DIG External memory interface, address/data bit 3 output. Takes priority over PSP and port data. x I TTL External memory interface, data bit 3 input. PSP3 x O DIG PSP read data output (LATD<3>). Takes priority over port data. x I TTL PSP write data input. RD4/AD4/ RD4 0 O DIG LATD<4> data output. PSP4/SDO2 1 I ST PORTD<4> data input. AD4(1) x O DIG External memory interface, address/data bit 4 output. Takes priority over PSP, MSSP and port data. x I TTL External memory interface, data bit 4 input. PSP4 x O DIG PSP read data output (LATD<4>). Takes priority over port and PSP data. x I TTL PSP write data input. SDO2 0 O DIG SPI data output (MSSP2 module). Takes priority over PSP and port data. Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Implemented on 80-pin devices only. DS39646C-page 144 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 11-7: PORTD FUNCTIONS (CONTINUED) TRIS Pin Name Function I/O I/O Type Description Setting RD5/AD5/ RD5 0 O DIG LATD<5> data output. PSP5/SDI2 1 I ST PORTD<5> data input. /SDA2 AD5(1) x O DIG External memory interface, address/data bit 5 output. Takes priority over PSP, MSSP and port data. x I TTL External memory interface, data bit 5 input. PSP5 x O DIG PSP read data output (LATD<5>). Takes priority over port data. x I TTL PSP write data input. SDI2 1 I ST SPI data input (MSSP2 module). SDA2 1 O DIG I2C™ data output (MSSP2 module). Takes priority over PSP and port data. 1 I I2C/SMB I2C data input (MSSP2 module); input type depends on module setting. RD6/AD6/ RD6 0 O DIG LATD<6> data output. PSP6/SCK2/ 1 I ST PORTD<6> data input. SCL2 AD6(1) x O DIG-3 External memory interface, address/data bit 6 output. Takes priority over PSP, MSSP and port data. x I TTL External memory interface, data bit 6 input. PSP6 x O DIG PSP read data output (LATD<6>). Takes priority over port data. x I TTL PSP write data input. SCK2 0 O DIG SPI clock output (MSSP2 module). Takes priority over PSP and port data. 1 I ST SPI clock input (MSSP2 module). SCL2 0 O DIG I2C clock output (MSSP2 module). Takes priority over PSP and port data. 1 I I2C/SMB I2C clock input (MSSP2 module); input type depends on module setting. RD7/AD7/ RD7 0 O DIG LATD<7> data output. PSP7/SS2 1 I ST PORTD<7> data input. AD7(1) x O DIG External memory interface, address/data bit 7 output. Takes priority over PSP and port data. x I TTL External memory interface, data bit 7 input. PSP7 x O DIG PSP read data output (LATD<7>). Takes priority over port data. x I TTL PSP write data input. SS2 1 I TTL Slave select input for SSP (MSSP2 module). Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Implemented on 80-pin devices only. TABLE 11-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 60 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 60 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 60 © 2008 Microchip Technology Inc. DS39646C-page 145

PIC18F8722 FAMILY 11.5 PORTE, TRISE and When the Parallel Slave Port is active on PORTD, LATE Registers three of the PORTE pins (RE0/AD8/RD/P2D, RE1/AD9/WR/P2C and RE2/AD10/CS/P2B) are config- PORTE is an 8-bit wide, bidirectional port. The ured as digital control inputs for the port. The control corresponding Data Direction register is TRISE. Setting functions are summarized in Table11-9. The reconfigu- a TRISE bit (= 1) will make the corresponding PORTE ration occurs automatically when the PSPMODE control pin an input (i.e., put the corresponding output driver in bit (PSPCON<4>) is set. Users must still make certain a high-impedance mode). Clearing a TRISE bit (= 0) the corresponding TRISE bits are set to configure these will make the corresponding PORTE pin an output pins as digital inputs. (i.e., put the contents of the output latch on the selected pin). EXAMPLE 11-5: INITIALIZING PORTE The Data Latch register (LATE) is also memory CLRF PORTE ; Initialize PORTE by mapped. Read-modify-write operations on the LATE ; clearing output register read and write the latched output value for ; data latches PORTE. CLRF LATE ; Alternate method ; to clear output All pins on PORTE are implemented with Schmitt ; data latches Trigger input buffers. Each pin is individually MOVLW 03h ; Value used to configurable as an input or output. ; initialize data ; direction Note: On a Power-on Reset, these pins are MOVWF TRISE ; Set RE<1:0> as inputs configured as digital inputs. ; RE<7:2> as outputs When the device is operating in Microcontroller mode, pin RE7 can be configured as the alternate peripheral pin for the ECCP2 module. This is done by clearing the CCP2MX Configuration bit. In 80-pin devices, PORTE is multiplexed with the system bus as part of the external memory interface. I/O port and other functions are only available when the interface is disabled by setting the EBDIS bit (MEMCON<7>). When the interface is enabled (80-pin devices only), PORTE is the high-order byte of the multiplexed address/data bus (AD<15:8>). The TRISE bits are also overridden. DS39646C-page 146 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 11-9: PORTE FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RE0/AD8/ RE0 0 O DIG LATE<0> data output. RD/P2D 1 I ST PORTE<0> data input. AD8(2) x O DIG External memory interface, address/data bit 8 output. Takes priority over ECCP and port data. x I TTL External memory interface, data bit 8 input. RD 1 I TTL Parallel Slave Port read enable control input. P2D 0 O DIG ECCP2 Enhanced PWM output, channel D. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RE1/AD9/ RE1 0 O DIG LATE<1> data output. WR/P2C 1 I ST PORTE<1> data input. AD9(2) x O DIG External memory interface, address/data bit 9 output. Takes priority over ECCP and port data. x I TTL External memory interface, data bit 9 input. WR 1 I TTL Parallel Slave Port write enable control input. P2C 0 O DIG ECCP2 Enhanced PWM output, channel C. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RE2/AD10/ RE2 0 O DIG LATE<2> data output. CS/P2B 1 I ST PORTE<2> data input. AD10(2) x O DIG External memory interface, address/data bit 10 output. Takes priority over ECCP and port data. x I TTL External memory interface, data bit 10 input. CS 1 I TTL Parallel Slave Port chip select control input. P2B 0 O DIG ECCP2 Enhanced PWM output, channel B. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RE3/AD11/P3C RE3 0 O DIG LATE<3> data output. 1 I ST PORTE<3> data input. AD11(2) x O DIG External memory interface, address/data bit 11 output. Takes priority over ECCP and port data. x I TTL External memory interface, data bit 11 input. P3C 0 O DIG ECCP3 Enhanced PWM output, channel C. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RE4/AD12/P3B RE4 0 O DIG LATE<4> data output. 1 I ST PORTE<4> data input. AD12(2) x O DIG External memory interface, address/data bit 12 output. Takes priority over ECCP and port data. x I TTL External memory interface, data bit 12 input. P3B 0 O DIG ECCP3 Enhanced PWM output, channel B. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignment for ECCP2 when CCP2MX Configuration bit is cleared (all devices in Microcontroller mode). 2: Implemented on 80-pin devices only. © 2008 Microchip Technology Inc. DS39646C-page 147

PIC18F8722 FAMILY TABLE 11-9: PORTE FUNCTIONS (CONTINUED) TRIS I/O Pin Name Function I/O Description Setting Type RE5/AD13/P1C RE5 0 O DIG LATE<5> data output. 1 I ST PORTE<5> data input. AD13(2) x O DIG External memory interface, address/data bit 13 output. Takes priority over ECCP and port data. x I TTL External memory interface, data bit 13 input. P1C 0 O DIG ECCP1 Enhanced PWM output, channel C. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RE6/AD14/P1B RE6 0 O DIG LATE<6> data output. 1 I ST PORTE<6> data input. AD14(2) x O DIG External memory interface, address/data bit 14 output. Takes priority over ECCP and port data. x I TTL External memory interface, data bit 14 input. P1B 0 O DIG ECCP1 Enhanced PWM output, channel B. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RE7/AD15/ RE7 0 O DIG LATE<7> data output. ECCP2/P2A 1 I ST PORTE<7> data input. AD15(2) x O DIG External memory interface, address/data bit 15 output. Takes priority over ECCP and port data. x I TTL External memory interface, data bit 15 input. ECCP2(1) 0 O DIG ECCP2 compare output and ECCP2 PWM output. Takes priority over port data. 1 I ST ECCP2 capture input. P2A(1) 0 O DIG ECCP2 Enhanced PWM output, channel A. Takes priority over port and data. May be configured for tri-state during Enhanced PWM shutdown events. Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignment for ECCP2 when CCP2MX Configuration bit is cleared (all devices in Microcontroller mode). 2: Implemented on 80-pin devices only. TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 60 LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 60 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 60 DS39646C-page 148 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 11.6 PORTF, LATF and TRISF Registers Note1: On a Power-on Reset, the RF<6:0> pins PORTF is an 8-bit wide, bidirectional port. The corre- are configured as analog inputs and read sponding Data Direction register is TRISF. Setting a as ‘0’. TRISF bit (= 1) will make the corresponding PORTF pin 2: To configure PORTF as digital I/O, set the an input (i.e., put the corresponding output driver in a ADCON1 register. high-impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i.e., put EXAMPLE 11-6: INITIALIZING PORTF the contents of the output latch on the selected pin). CLRF PORTF ; Initialize PORTF by The Data Latch register (LATF) is also memory ; clearing output mapped. Read-modify-write operations on the LATF ; data latches register read and write the latched output value for CLRF LATF ; Alternate method PORTF. ; to clear output ; data latches All pins on PORTF are implemented with Schmitt MOVLW 0x0F ; Trigger input buffers. Each pin is individually MOVWF ADCON1 ; Set PORTF as digital I/O configurable as an input or output. MOVLW 0xCF ; Value used to PORTF is multiplexed with several analog peripheral ; initialize data ; direction functions, including the A/D converter and comparator MOVWF TRISF ; Set RF3:RF0 as inputs inputs, as well as the comparator outputs. Pins RF1 ; RF5:RF4 as outputs through RF2 may be used as comparator inputs or ; RF7:RF6 as inputs outputs by setting the appropriate bits in the CMCON register. To use RF<6:0:> as digital inputs, it is necessary to turn off the A/D inputs. © 2008 Microchip Technology Inc. DS39646C-page 149

PIC18F8722 FAMILY TABLE 11-11: PORTF FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RF0/AN5 RF0 0 O DIG LATF<0> data output; not affected by analog input. 1 I ST PORTF<0> data input; disabled when analog input enabled. AN5 1 I ANA A/D input channel 5. Default configuration on POR. RF1/AN6/C2OUT RF1 0 O DIG LATF<1> data output; not affected by analog input. 1 I ST PORTF<1> data input; disabled when analog input enabled. AN6 1 I ANA A/D input channel 6. Default configuration on POR. C2OUT 0 O DIG Comparator 2 output; takes priority over port data. RF2/AN7/C1OUT RF2 0 O DIG LATF<2> data output; not affected by analog input. 1 I ST PORTF<2> data input; disabled when analog input enabled. AN7 1 I ANA A/D input channel 7. Default configuration on POR. C1OUT 0 O TTL Comparator 1 output; takes priority over port data. RF3/AN8 RF3 0 O DIG LATF<3> data output; not affected by analog input. 1 I ST PORTF<3> data input; disabled when analog input enabled. AN8 1 I ANA A/D input channel 8 and Comparator C2+ input. Default input configuration on POR; not affected by analog output. RF4/AN9 RF4 0 O DIG LATF<4> data output; not affected by analog input. 1 I ST PORTF<4> data input; disabled when analog input enabled. AN9 1 I ANA A/D input channel 9 and Comparator C2- input. Default input configuration on POR; does not affect digital output. RF5/AN10/CVREF RF5 0 O DIG LATF<5> data output; not affected by analog input. Disabled when CVREF output enabled. 1 I ST PORTF<5> data input; disabled when analog input enabled. Disabled when CVREF output enabled. AN10 1 I ANA A/D input channel 10 and Comparator C1+ input. Default input configuration on POR; not affected by analog output. CVREF x O ANA Comparator voltage reference output. Enabling this feature disables digital I/O. RF6/AN11 RF6 0 O DIG LATF<6> data output; not affected by analog input. 1 I ST PORTF<6> data input; disabled when analog input enabled. AN11 1 I ANA A/D input channel 11 and Comparator C1- input. Default input configuration on POR; does not affect digital output. RF7/SS1 RF7 0 O DIG LATF<7> data output. 1 I ST PORTF<7> data input. SS1 1 I TTL Slave select input for SSP (MSSP1 module). Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). TABLE 11-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 60 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 60 LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 60 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 59 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 59 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF. DS39646C-page 150 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 11.7 PORTG, TRISG and The sixth pin of PORTG (RG5/MCLR/VPP) is an input LATG Registers only pin. Its operation is controlled by the MCLRE Configuration bit. When selected as a port pin PORTG is a 6-bit wide, bidirectional port. The corre- (MCLRE=0), it functions as a digital input only pin; as sponding Data Direction register is TRISG. Setting a such, it does not have TRIS or LAT bits associated with TRISG bit (= 1) will make the corresponding PORTG its operation. Otherwise, it functions as the device’s pin an input (i.e., put the corresponding output driver in Master Clear input. In either configuration, RG5 also a high-impedance mode). Clearing a TRISG bit (= 0) functions as the programming voltage input during programming. will make the corresponding PORTG pin an output (i.e., put the contents of the output latch on the Note: On a Power-on Reset, RG5 is enabled as selected pin). a digital input only if Master Clear The Data Latch register (LATG) is also memory functionality is disabled. All other 5 pins mapped. Read-modify-write operations on the LATG are configured as digital inputs. register, read and write the latched output value for PORTG. EXAMPLE 11-7: INITIALIZING PORTG PORTG is multiplexed with EUSART and CCP CLRF PORTG ; Initialize PORTG by functions (Table11-13). PORTG pins have Schmitt ; clearing output Trigger input buffers. ; data latches CLRF LATG ; Alternate method When enabling peripheral functions, care should be ; to clear output taken in defining TRIS bits for each PORTG pin. Some ; data latches peripherals override the TRIS bit to make a pin an MOVLW 0x04 ; Value used to output, while other peripherals override the TRIS bit to ; initialize data make a pin an input. The user should refer to the ; direction corresponding peripheral section for the correct TRIS MOVWF TRISG ; Set RG1:RG0 as outputs bit settings. The pin override value is not loaded into ; RG2 as input ; RG4:RG3 as inputs the TRIS register. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. © 2008 Microchip Technology Inc. DS39646C-page 151

PIC18F8722 FAMILY TABLE 11-13: PORTG FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RG0/ECCP3/P3A RG0 0 O DIG LATG<0> data output. 1 I ST PORTG<0> data input. ECCP3 0 O DIG ECCP3 compare and ECCP3 PWM output. Takes priority over port data. 1 I ST ECCP3 capture input. P3A 0 O DIG ECCP3 Enhanced PWM output, channel B. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RG1/TX2/CK2 RG1 0 O DIG LATG<1> data output. 1 I ST PORTG<1> data input. TX2 0 O DIG Asynchronous serial transmit data output (EUSART2 module). Takes priority over port data. CK2 0 O DIG Synchronous serial clock output (EUSART2 module). Takes priority over port data. 1 I ST Synchronous serial clock input (EUSART2 module). RG2/RX2/DT2 RG2 0 O DIG LATG<2> data output. 1 I ST PORTG<2> data input. RX2 1 I ST Asynchronous serial receive data input (EUSART2 module). DT2 1 O DIG Synchronous serial data output (EUSART2 module). Takes priority over port data. User must configure as an input. 1 I ST Synchronous serial data input (EUSART2 module). User must configure as an input. RG3/CCP4/P3D RG3 0 O DIG LATG<3> data output. 1 I ST PORTG<3> data input. CCP4 0 O DIG CCP4 compare and PWM output; takes priority over port data and P3D function. 1 I ST CCP4 capture input. P3D 0 O DIG ECCP3 Enhanced PWM output, channel D. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RG4/CCP5/P1D RG4 0 O DIG LATG<4> data output. 1 I ST PORTG<4> data input. CCP5 0 O DIG CCP5 compare and PWM output. Takes priority over port data and P1D function. 1 I ST CCP5 capture input. P1D 0 O DIG ECCP1 Enhanced PWM output, channel B. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RG5/MCLR/VPP RG5 —(1) I ST PORTG<5> data input; enabled when MCLRE Configuration bit is clear. MCLR — I ST External Master Clear input; enabled when MCLRE Configuration bit is set. VPP — I ANA High-voltage detection; used for ICSP™ mode entry detection. Always available regardless of pin mode. Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: RG5 does not have a corresponding TRISG bit. DS39646C-page 152 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 11-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTG — — RG5(1) RG4 RG3 RG2 RG1 RG0 60 LATG — — LATG5(1) LATG4 LATG3 LATG2 LATG1 LATG0 60 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG. Note 1: RG5 and LATG5 are only available when MCLR is disabled (MCLRE Configuration bit = 0; otherwise, RG5 and LATG5 read as ‘0’. © 2008 Microchip Technology Inc. DS39646C-page 153

PIC18F8722 FAMILY 11.8 PORTH, LATH and When the external memory interface is enabled, four of TRISH Registers the PORTH pins function as the high-order address lines for the interface. The address output from the Note: PORTH is available only on interface takes priority over other digital I/O. The PIC18F8527/8622/8627/8722 devices. corresponding TRISH bits are also overridden. PORTH is an 8-bit wide, bidirectional I/O port. The EXAMPLE 11-8: INITIALIZING PORTH corresponding Data Direction register is TRISH. Set- ting a TRISH bit (= 1) will make the corresponding CLRF PORTH ; Initialize PORTH by PORTH pin an input (i.e., put the corresponding output ; clearing output driver in a high-impedance mode). Clearing a TRISH ; data latches CLRF LATH ; Alternate method bit (= 0) will make the corresponding PORTH pin an ; to clear output output (i.e., put the contents of the output latch on the ; data latches selected pin). MOVLW 0CFh ; Value used to The Data Latch register (LATH) is also memory ; initialize data mapped. Read-modify-write operations on the LATH ; direction register, read and write the latched output value for MOVWF TRISH ; Set RH3:RH0 as inputs ; RH5:RH4 as outputs PORTH. ; RH7:RH6 as inputs All pins on PORTH are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: On a Power-on Reset, these pins are configured as digital inputs. DS39646C-page 154 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 11-15: PORTH FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RH0/A16 RH0 0 O DIG LATH<0> data output. 1 I ST PORTH<0> data input. A16 x O DIG External memory interface, address line 16. Takes priority over port data. RH1/A17 RH1 0 O DIG LATH<1> data output. 1 I ST PORTH<1> data input. A17 x O DIG External memory interface, address line 17. Takes priority over port data. RH2/A18 RH2 0 O DIG LATH<2> data output. 1 I ST PORTH<2> data input. A18 x O DIG External memory interface, address line 18. Takes priority over port data. RH3/A19 RH3 0 O DIG LATH<3> data output. 1 I ST PORTH<3> data input. A19 x O DIG External memory interface, address line 19. Takes priority over port data. RH4/AN12/ RH4 0 O DIG LATH<4> data output. P3C 1 I ST PORTH<4> data input. AN12 1 I ANA A/D input channel 12. Default configuration on POR. P3C(1) 0 O DIG ECCP3 Enhanced PWM output, channel C. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RH5/AN13/ RH5 0 O DIG LATH<5> data output. P3B 1 I ST PORTH<5> data input. AN13 1 I ANA A/D input channel 13. Default configuration on POR. P3B(1) 0 O DIG ECCP3 Enhanced PWM output, channel B. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RH6/AN14/ RH6 0 O DIG LATH<6> data output. P1C 1 I ST PORTH<6> data input. AN14 1 I ANA A/D input channel 14. Default configuration on POR. P1C(1) 0 O DIG ECCP1 Enhanced PWM output, channel C. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RH7/AN15/ RH7 0 O DIG LATH<7> data output. P1B 1 I ST PORTH<7> data input. AN15 1 I ANA A/D input channel 15. Default configuration on POR. P1B(1) 0 O DIG ECCP1 Enhanced PWM output, channel B. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). TABLE 11-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page TRISH TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 60 PORTH RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 60 LATH LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 60 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 59 © 2008 Microchip Technology Inc. DS39646C-page 155

PIC18F8722 FAMILY 11.9 PORTJ, TRISJ and When the external memory interface is enabled, all of LATJ Registers the PORTJ pins function as control outputs for the interface. This occurs automatically when the interface Note: PORTJ is available only on is enabled by clearing the EBDIS control bit PIC18F8527/8622/8627/8722 devices. (MEMCON<7>). The TRISJ bits are also overridden. PORTJ is an 8-bit wide, bidirectional port. The corre- EXAMPLE 11-9: INITIALIZING PORTJ sponding Data Direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding PORTJ pin CLRF PORTJ ; Initialize PORTJ by ; clearing output an input (i.e., put the corresponding output driver in a ; data latches high-impedance mode). Clearing a TRISJ bit (= 0) will CLRF LATJ ; Alternate method make the corresponding PORTJ pin an output (i.e., put ; to clear output the contents of the output latch on the selected pin). ; data latches The Data Latch register (LATJ) is also memory MOVLW 0xCF ; Value used to mapped. Read-modify-write operations on the LATJ ; initialize data register, read and write the latched output value for ; direction MOVWF TRISJ ; Set RJ3:RJ0 as inputs PORTJ. ; RJ5:RJ4 as output All pins on PORTJ are implemented with Schmitt ; RJ7:RJ6 as inputs Trigger input buffers. Each pin is individually configurable as an input or output. Note: On a Power-on Reset, these pins are configured as digital inputs. DS39646C-page 156 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 11-17: PORTJ FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RJ0/ALE RJ0 0 O DIG LATJ<0> data output. 1 I ST PORTJ<0> data input. ALE x O DIG External memory interface address latch enable control output. Takes priority over digital I/O. RJ1/OE RJ1 0 O DIG LATJ<1> data output. 1 I ST PORTJ<1> data input. OE x O DIG External memory interface output enable control output. Takes priority over digital I/O. RJ2/WRL RJ2 0 O DIG LATJ<2> data output. 1 I ST PORTJ<2> data input. WRL x O DIG External Memory Bus write low byte control. Takes priority over digital I/O. RJ3/WRH RJ3 0 O DIG LATJ<3> data output. 1 I ST PORTJ<3> data input. WRH x O DIG External memory interface write high byte control output. Takes priority over digital I/O. RJ4/BA0 RJ4 0 O DIG LATJ<4> data output. 1 I ST PORTJ<4> data input. BA0 x O DIG External memory interface byte address 0 control output. Takes priority over digital I/O. RJ5/CE RJ5 0 O DIG LATJ<5> data output. 1 I ST PORTJ<5> data input. CE x O DIG External memory interface chip enable control output. Takes priority over digital I/O. RJ6/LB RJ6 0 O DIG LATJ<6> data output. 1 I ST PORTJ<6> data input. LB x O DIG External memory interface lower byte enable control output. Takes priority over digital I/O. RJ7/UB RJ7 0 O DIG LATJ<7> data output. 1 I ST PORTJ<7> data input. UB x O DIG External memory interface upper byte enable control output. Takes priority over digital I/O. Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). TABLE 11-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTJ RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 60 LATJ LATJ7 LATJ6 LATJ5 LATJ4 LATJ3 LATJ2 LATJ1 LATJ0 60 TRISJ TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3 TRISJ2 TRISJ1 TRISJ0 60 © 2008 Microchip Technology Inc. DS39646C-page 157

PIC18F8722 FAMILY 11.10 Parallel Slave Port FIGURE 11-2: PORTD AND PORTE BLOCK DIAGRAM PORTD can also function as an 8-bit wide Parallel (PARALLEL SLAVE PORT) Slave Port, or microprocessor port, when control bit PSPMODE (PSPCON<4>) is set. It is asynchronously readable and writable by the external world through the Data Bus D Q RD and WR control input pins. RDx Note: For PIC18F8527/8622/8627/8722 devices, WR LATD CKx pin or the Parallel Slave Port is available only in PORTD Data Latch TTL Microcontroller mode. Q D The PSP can directly interface to an 8-bit micro- processor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting RD PORTD ENEN bit PSPMODE enables port pin RE0/RD to be the RD TRIS Latch input, RE1/WR to be the WR input and RE2/CS to be the CS (Chip Select) input. For this functionality, the corresponding data direction bits of the TRISE register RD LATD (TRISE<2:0>) must be configured as inputs (set). A write to the PSP occurs when both the CS and WR lines are first detected low and ends when either are One bit of PORTD detected high. The PSPIF and IBF flag bits are both set Set Interrupt Flag when the write ends. PSPIF (PIR1<7>) A read from the PSP occurs when both the CS and RD lines are first detected low. The data in PORTD is read out and the OBF bit is set. If the user writes new data to PORTD to set OBF, the data is immediately read out; however, the OBF bit is not set. When either the CS or RD lines are detected high, the Read TTL RD PORTD pins return to the input state and the PSPIF bit is set. User applications should wait for PSPIF to be set Chip Select TTL CS before servicing the PSP; when this happens, the IBF and OBF bits can be polled and the appropriate action Write taken. TTL WR The timing for the control signals in Write and Read Note: I/O pin has protection diodes to VDD and VSS. modes is shown in Figure11-3 and Figure11-4, respectively. DS39646C-page 158 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY REGISTER 11-1: PSPCON: PARALLEL SLAVE PORT CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IBF OBF IBOV PSPMODE — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode bit 3-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. DS39646C-page 159

PIC18F8722 FAMILY FIGURE 11-3: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 11-4: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 11-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 60 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 60 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 60 PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 60 LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 60 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 60 PSPCON IBF OBF IBOV PSPMODE — — — — 59 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. DS39646C-page 160 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 12.0 TIMER0 MODULE The T0CON register (Register12-1) controls all aspects of the module’s operation, including the The Timer0 module incorporates the following features: prescale selection. It is both readable and writable. • Software selectable operation as a timer or A simplified block diagram of the Timer0 module in 8-bit counter in both 8-bit or 16-bit modes mode is shown in Figure12-1. Figure12-2 shows a • Readable and writable registers simplified block diagram of the Timer0 module in 16-bit • Dedicated 8-bit, software programmable mode. prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow REGISTER 12-1: T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2008 Microchip Technology Inc. DS39646C-page 161

PIC18F8722 FAMILY 12.1 Timer0 Operation internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the Timer0 can operate as either a timer or a counter; the timer/counter. mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on 12.2 Timer0 Reads and Writes in every clock by default unless a different prescaler value 16-bit Mode is selected (see Section12.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited TMR0H is not the actual high byte of Timer0 in 16-bit for the following two instruction cycles. The user can mode; it is actually a buffered version of the real high work around this by writing an adjusted value to the byte of Timer0 which is not directly readable nor writ- TMR0 register. able (refer to Figure12-2). TMR0H is updated with the contents of the high byte of Timer0 during a read of The Counter mode is selected by setting the T0CS bit TMR0L. This provides the ability to read all 16 bits of (= 1). In this mode, Timer0 increments either on every Timer0 without having to verify that the read of the high rising or falling edge of pin RA4/T0CKI. The increment- and low byte were valid, due to a rollover between ing edge is determined by the Timer0 Source Edge successive reads of the high and low byte. Select bit, T0SE (T0CON<4>); clearing this bit selects the rising edge. Restrictions on the external clock input Similarly, a write to the high byte of Timer0 must also are discussed below. take place through the TMR0H Buffer register. The high byte is updated with the contents of TMR0H when a An external clock source can be used to drive Timer0; write occurs to TMR0L. This allows all 16 bits of Timer0 however, it must meet certain requirements to ensure to be updated at once. that the external clock can be synchronized with the FIGURE 12-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 Sync with Set 1 Internal TMR0L TMR0IF T0CKI pin Programmable 0 Clocks on Overflow Prescaler T0SE (2 TCY Delay) 8 T0CS 3 T0PS<2:0> 8 PSA Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 12-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 1 1 SIynntecr nwaitlh TMR0L HTigMh RB0yte STMetR 0IF T0CKI pin ProPgrreasmcamlearble 0 Clocks 8 on Overflow T0SE (2 TCY Delay) T0CS 3 Read TMR0L T0PS<2:0> Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS39646C-page 162 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 12.3 Prescaler 12.3.1 SWITCHING PRESCALER ASSIGNMENT An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable; The prescaler assignment is fully under software its value is set by the PSA and T0PS<2:0> bits control and can be changed “on-the-fly” during program (T0CON<3:0>) which determine the prescaler execution. assignment and prescale ratio. 12.4 Timer0 Interrupt Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values The TMR0 interrupt is generated when the TMR0 from 1:2 through 1:256 in power-of-2 increments are register overflows from FFh to 00h in 8-bit mode, or selectable. from FFFFh to 0000h in 16-bit mode. This overflow sets When assigned to the Timer0 module, all instructions the TMR0IF flag bit. The interrupt can be masked by writing to the TMR0 register (e.g., CLRF TMR0, MOVWF clearing the TMR0IE bit (INTCON<5>). Before re- TMR0, BSF TMR0, etc.) clear the prescaler count. enabling the interrupt, the TMR0IF bit must be cleared in software by the Interrupt Service Routine. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler Since Timer0 is shut down in Sleep mode, the TMR0 count, but will not change the prescaler interrupt cannot awaken the processor from Sleep. assignment. TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER0 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page TMR0L Timer0 Register Low Byte 58 TMR0H Timer0 Register High Byte 58 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 58 TRISA TRISA7(1) TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 60 Legend: Shaded cells are not used by Timer0. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2008 Microchip Technology Inc. DS39646C-page 163

PIC18F8722 FAMILY NOTES: DS39646C-page 164 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 13.0 TIMER1 MODULE A simplified block diagram of the Timer1 module is shown in Figure13-1. A block diagram of the module’s The Timer1 timer/counter module incorporates these operation in Read/Write mode is shown in Figure13-2. features: The module incorporates its own low-power oscillator • Software selectable operation as a 16-bit timer or to provide an additional clocking option. The Timer1 counter oscillator can also be used as a low-power clock source • Readable and writable 8-bit registers (TMR1H for the microcontroller in power-managed operation. and TMR1L) Timer1 can also be used to provide Real-Time Clock • Selectable clock source (internal or external) with (RTC) functionality to applications with only a minimal device clock or Timer1 oscillator internal options addition of external components and code overhead. • Interrupt-on-overflow Timer1 is controlled through the T1CON Control • Reset on CCP Special Event Trigger register (Register13-1). It also contains the Timer1 • Device clock status flag (T1RUN) Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>). REGISTER 13-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 6 T1RUN: Timer1 System Clock Status bit 1 = Device clock is derived from Timer1 oscillator 0 = Device clock is derived from another source bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 =Timer1 oscillator is enabled 0 = Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2008 Microchip Technology Inc. DS39646C-page 165

PIC18F8722 FAMILY 13.1 Timer1 Operation cycle (FOSC/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input Timer1 can operate in one of these modes: or the Timer1 oscillator, if enabled. • Timer When Timer1 is enabled, the RC1/T1OSI and RC0/ • Synchronous Counter T1OSO/T13CKI pins become inputs. This means the • Asynchronous Counter values of TRISC<1:0> are ignored and the pins are The operating mode is determined by the clock select read as ‘0’. bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 13-1: TIMER1 BLOCK DIAGRAM Timer1 Oscillator Timer1 Clock Input On/Off 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR1CS Timer1 On/Off T1CKPS<1:0> T1SYNC TMR1ON Clear TMR1 TMR1L HTigMh RB1yte TMSRet1 IF (CCP Special Event Trigger) on Overflow Note 1:When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 13-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator Timer1 Clock Input 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR1CS Timer1 T1CKPS1:T1CKPS0 On/Off T1SYNC TMR1ON Clear TMR1 TMR1L HTigMh RB1yte TMSRet1 IF (CCP Special Event Trigger) on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39646C-page 166 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 13.2 Timer1 16-bit Read/Write Mode TABLE 13-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR(2,3,4) Timer1 can be configured for 16-bit reads and writes (see Figure13-2). When the RD16 control bit Osc Type Freq C1 C2 (T1CON<7>) is set, the address for TMR1H is mapped LP 32kHz 27pF(1) 27pF(1) to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Note1: Microchip suggests these values as a Timer1 into the Timer1 high byte buffer. This provides starting point in validating the oscillator the user with the ability to accurately read all 16 bits of circuit. Timer1 without having to determine whether a read of 2: Higher capacitance increases the stability the high byte, followed by a read of the low byte, has of the oscillator but also increases the become invalid due to a rollover between reads. start-up time. A write to the high byte of Timer1 must also take place 3: Since each resonator/crystal has its own through the TMR1H Buffer register. The Timer1 high characteristics, the user should consult byte is updated with the contents of TMR1H when a the resonator/crystal manufacturer for write occurs to TMR1L. This allows a user to write all appropriate values of external 16 bits to both the high and low bytes of Timer1 at once. components. The high byte of Timer1 is not directly readable or 4: Capacitor values are for design guidance writable in this mode. All reads and writes must take only. place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. 13.3.1 USING TIMER1 AS A The prescaler is only cleared on writes to TMR1L. CLOCK SOURCE The Timer1 oscillator is also available as a clock source 13.3 Timer1 Oscillator in power-managed modes. By setting the clock select An on-chip crystal oscillator circuit is incorporated bits, SCS<1:0> (OSCCON<1:0>), to ‘01’, the device between pins T1OSI (input) and T1OSO (amplifier out- switches to SEC_RUN mode; both the CPU and put). It is enabled by setting the Timer1 Oscillator Enable peripherals are clocked from the Timer1 oscillator. If the bit, T1OSCEN (T1CON<3>). The oscillator is a low- IDLEN bit (OSCCON<7>) is cleared and a SLEEP power circuit rated for 32kHz crystals. It will continue to instruction is executed, the device enters SEC_IDLE run during all power-managed modes. The circuit for a mode. Additional details are available in Section3.0 typical LP oscillator is shown in Figure13-3. Table13-1 “Power-Managed Modes”. shows the capacitor selection for the Timer1 oscillator. Whenever the Timer1 oscillator is providing the clock The user must provide a software time delay to ensure source, the Timer1 system clock status flag, T1RUN proper start-up of the Timer1 oscillator. (T1CON<6>), is set. This can be used to determine the controller’s current clocking mode. It can also indicate FIGURE 13-3: EXTERNAL the clock source being currently used by the Fail-Safe Clock Monitor. If the Clock Monitor is enabled and the COMPONENTS FOR THE Timer1 oscillator fails while providing the clock, polling TIMER1 LP OSCILLATOR the T1RUN bit will indicate whether the clock is being C1 provided by the Timer1 oscillator or another source. PIC18FXXXX 27 pF T1OSI 13.3.2 LOW-POWER TIMER1 OPTION The Timer1 oscillator can operate at two distinct levels XTAL of power consumption based on device configuration. 32.768 kHz When the LPT1OSC Configuration bit is set, the Timer1 oscillator operates in a low-power mode. When T1OSO LPT1OSC is not set, Timer1 operates at a higher power C2 level. Power consumption for a particular mode is rela- 27 pF tively constant, regardless of the device’s operating Note: See the Notes with Table13-1 for additional mode. The default Timer1 configuration is the higher information about capacitor selection. power mode. As the low-power Timer1 mode tends to be more sensitive to interference, high noise environments may cause some oscillator instability. The low-power option is, therefore, best suited for low noise applications where power conservation is an important design consideration. © 2008 Microchip Technology Inc. DS39646C-page 167

PIC18F8722 FAMILY 13.3.3 TIMER1 OSCILLATOR LAYOUT In the event that a write to Timer1 coincides with a CONSIDERATIONS Special Event Trigger, the write operation will take precedence. The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the Note: The Special Event Triggers from the CCPx oscillator, it may also be sensitive to rapidly changing module will not set the TMR1IF interrupt signals in close proximity. flag bit (PIR1<0>). The oscillator circuit, shown in Figure13-3, should be 13.6 Using Timer1 as a Real-Time Clock located as close as possible to the microcontroller. There should be no circuits passing within the oscillator Adding an external LP oscillator to Timer1 (such as the circuit boundaries other than VSS or VDD. one described in Section13.3 “Timer1 Oscillator” If a high-speed circuit must be located near the Timer1 above) gives users the option to include RTC function- oscillator, a grounded guard ring around the oscillator ality to their applications. This is accomplished with an circuit may be helpful when used on a single-sided inexpensive watch crystal to provide an accurate time PCB or in addition to a ground plane. base and several lines of application code to calculate the time. When operating in Sleep mode and using a 13.4 Timer1 Interrupt battery or supercapacitor as a power source, it can completely eliminate the need for a separate RTC The TMR1 register pair (TMR1H:TMR1L) increments device and battery backup. from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow, The application code routine, RTCisr, shown in which is latched in interrupt flag bit, TMR1IF Example13-1, demonstrates a simple method to (PIR1<0>). This interrupt can be enabled or disabled increment a counter at one-second intervals using an by setting or clearing the Timer1 Interrupt Enable bit, Interrupt Service Routine. Incrementing the TMR1 TMR1IE (PIE1<0>). register pair to overflow triggers the interrupt and calls the routine, which increments the seconds counter by 13.5 Resetting Timer1 Using the CCP one; additional counters for minutes and hours are incremented as the previous counter overflow. Special Event Trigger Since the register pair is 16 bits wide, counting up to If any of the CCP modules are configured to use Timer1 overflow the register directly from a 32.768kHz clock and generate a Special Event Trigger in Compare mode would take 2 seconds. To force the overflow at the (CCPxM<3:0>, this signal will reset Timer1. The trigger required one-second intervals, it is necessary to pre- from the ECCP2 module will also start an A/D conver- load it; the simplest method is to set the MSb of TMR1H sion if the A/D module is enabled (see Section17.3.4 with a BSF instruction. Note that the TMR1L register is “Special Event Trigger” for more information). never preloaded or altered; doing so may introduce The module must be configured as either a timer or a cumulative error over many cycles. synchronous counter to take advantage of this feature. For this method to be accurate, Timer1 must operate in When used this way, the CCPRH:CCPRL register pair Asynchronous mode and the Timer1 overflow interrupt effectively becomes a period register for Timer1. must be enabled (PIE1<0> = 1), as shown in the If Timer1 is running in Asynchronous Counter mode, routine, RTCinit. The Timer1 oscillator must also be this Reset operation may not work. enabled and running at all times. DS39646C-page 168 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY EXAMPLE 13-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW 80h ; Preload TMR1 register pair MOVWF TMR1H ; for 1 second overflow CLRF TMR1L MOVLW b’00001111’ ; Configure for external clock, MOVWF T1CON ; Asynchronous operation, external oscillator CLRF secs ; Initialize timekeeping registers CLRF mins ; MOVLW .12 MOVWF hours BSF PIE1, TMR1IE ; Enable Timer1 interrupt RETURN RTCisr BSF TMR1H, 7 ; Preload for 1 sec overflow BCF PIR1, TMR1IF ; Clear interrupt flag INCF secs, F ; Increment seconds MOVLW .59 ; 60 seconds elapsed? CPFSGT secs RETURN ; No, done CLRF secs ; Clear seconds INCF mins, F ; Increment minutes MOVLW .59 ; 60 minutes elapsed? CPFSGT mins RETURN ; No, done CLRF mins ; clear minutes INCF hours, F ; Increment hours MOVLW .23 ; 24 hours elapsed? CPFSGT hours RETURN ; No, done CLRF hours ; Reset hours RETURN ; Done TABLE 13-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 TMR1L Timer1 Register Low Byte 58 TMR1H Timer1 Register High Byte 58 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 58 Legend: Shaded cells are not used by the Timer1 module. © 2008 Microchip Technology Inc. DS39646C-page 169

PIC18F8722 FAMILY NOTES: DS39646C-page 170 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 14.0 TIMER2 MODULE 14.1 Timer2 Operation The Timer2 timer module incorporates the following In normal operation, TMR2 is incremented from 00h on features: each clock (FOSC/4). A 4-bit counter/prescaler on the clock input gives direct input, divide-by-4 and divide-by- • 8-bit Timer and Period registers (TMR2 and PR2, 16 prescale options; these are selected by the prescaler respectively) control bits, T2CKPS<1:0> (T2CON<1:0>). The value of • Readable and writable (both registers) TMR2 is compared to that of the period register, PR2, on • Software programmable prescaler each clock cycle. When the two values match, the com- (1:1, 1:4 and 1:16) parator generates a match signal as the timer output. • Software programmable postscaler This signal also resets the value of TMR2 to 00h on the (1:1 through 1:16) next cycle and drives the output counter/postscaler (see • Interrupt on TMR2 to PR2 match Section14.2 “Timer2 Interrupt”). • Optional use as the shift clock for the The TMR2 and PR2 registers are both directly readable MSSPx module and writable. The TMR2 register is cleared on any The module is controlled through the T2CON register device Reset, while the PR2 register initializes at FFh. (Register14-1), which enables or disables the timer Both the prescaler and postscaler counters are cleared and configures the prescaler and postscaler. Timer2 on the following events: can be shut off by clearing control bit, TMR2ON • a write to the TMR2 register (T2CON<2>), to minimize power consumption. • a write to the T2CON register A simplified block diagram of the module is shown in • any device Reset (Power-on Reset, MCLR Reset, Figure14-1. Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written. REGISTER 14-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 © 2008 Microchip Technology Inc. DS39646C-page 171

PIC18F8722 FAMILY 14.2 Timer2 Interrupt 14.3 Timer2 Output Timer2 also can generate an optional device interrupt. The unscaled output of TMR2 is available primarily to The Timer2 output signal (TMR2 to PR2 match) pro- the CCP modules, where it is used as a time base for vides the input for the 4-bit output counter/postscaler. operations in PWM mode. This counter generates the TMR2 match interrupt flag Timer2 can be optionally used as the shift clock source which is latched in TMR2IF (PIR1<1>). The interrupt is for the MSSP module operating in SPI mode. Addi- enabled by setting the TMR2 Match Interrupt Enable tional information is provided in Section19.0 “Master bit, TMR2IE (PIE1<1>). Synchronous Serial Port (MSSP) Module”. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0> (T2CON<6:3>). FIGURE 14-1: TIMER2 BLOCK DIAGRAM 4 1:1 to 1:16 T2OUTPS<3:0> Set TMR2IF Postscaler 2 T2CKPS<1:0> TMR2 Output (to PWM or MSSP) TMR2/PR2 Reset Match 1:1, 1:4, 1:16 FOSC/4 TMR2 Comparator PR2 Prescaler 8 8 8 Internal Data Bus TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 TMR2 Timer2 Register 58 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 58 PR2 Timer2 Period Register 58 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. DS39646C-page 172 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 15.0 TIMER3 MODULE A simplified block diagram of the Timer3 module is shown in Figure15-1. A block diagram of the module’s The Timer3 timer/counter module incorporates these operation in Read/Write mode is shown in Figure15-2. features: The Timer3 module is controlled through the T3CON • Software selectable operation as a 16-bit timer or register (Register15-1). It also selects the clock source counter options for the CCP modules (see Section17.1.1 • Readable and writable 8-bit registers “CCP Modules and Timer Resources” for more (TMR3H and TMR3L) information). • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt-on-overflow • Module Reset on CCP Special Event Trigger REGISTER 15-1: T3CON: TIMER3 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations bit 6, 3 T3CCP<2:1>: Timer3 and Timer1 to CCPx Enable bits 11 = Timer3 and Timer4 are the clock sources for ECCP1, ECCP2, ECCP3, CCP4 and CCP5 10 = Timer3 and Timer4 are the clock sources for ECCP3, CCP4 and CCP5; Timer1 and Timer2 are the clock sources for ECCP1 and ECCP2 01 = Timer3 and Timer4 are the clock sources for ECCP2, ECCP3, CCP4 and CCP5; Timer1 and Timer2 are the clock sources for ECCP1 00 = Timer1 and Timer2 are the clock sources for ECCP1, ECCP2, ECCP3, CCP4 and CCP5 bit 5-4 T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the device clock comes from Timer1/Timer3.) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2008 Microchip Technology Inc. DS39646C-page 173

PIC18F8722 FAMILY 15.1 Timer3 Operation The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared Timer3 can operate in one of three modes: (= 0), Timer3 increments on every internal instruction • Timer cycle (FOSC/4). When the bit is set, Timer3 increments • Synchronous Counter on every rising edge of the Timer1 external clock input • Asynchronous Counter or the Timer1 oscillator, if enabled. As with Timer1, the RC1/T1OSI and RC0/T1OSO/ T13CKI pins become inputs when the Timer1 oscillator is enabled. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’. FIGURE 15-1: TIMER3 BLOCK DIAGRAM Timer1 Oscillator Timer1 Clock Input 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR3CS Timer3 On/Off T3CKPS<1:0> T3SYNC TMR3ON CCPx Special Event Trigger Clear TMR3 TMR3 Set CCPx Select from T3CON<6,3> TMR3L High Byte TMR3IF on Overflow Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 15-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator Timer1 Clock Input 1 T13CKI/T1OSO 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR3CS Timer3 T3CKPS<1:0> On/Off T3SYNC TMR3ON CCPx Special Event Trigger Clear TMR3 TMR3 Set CCPx Select from T3CON<6,3> TMR3L High Byte TMR3IF on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR3H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39646C-page 174 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 15.2 Timer3 16-bit Read/Write Mode 15.4 Timer3 Interrupt Timer3 can be configured for 16-bit reads and writes The TMR3 register pair (TMR3H:TMR3L) increments (see Figure15-2). When the RD16 control bit from 0000h to FFFFh and overflows to 0000h. The (T3CON<7>) is set, the address for TMR3H is mapped Timer3 interrupt, if enabled, is generated on overflow to a buffer register for the high byte of Timer3. A read and is latched in interrupt flag bit, TMR3IF (PIR2<1>). from TMR3L will load the contents of the high byte of This interrupt can be enabled or disabled by setting or Timer3 into the Timer3 High Byte Buffer register. This clearing the Timer3 Interrupt Enable bit, TMR3IE provides the user with the ability to accurately read all (PIE2<1>). 16 bits of Timer3 without having to determine whether a read of the high byte, followed by a read of the low 15.5 Resetting Timer3 Using the CCP byte, has become invalid due to a rollover between Special Event Trigger reads. If any of the CCP modules are configured to use Timer3 A write to the high byte of Timer3 must also take place and to generate a Special Event Trigger in Compare through the TMR3H Buffer register. The Timer3 high mode (CCPxM<3:0>=1011), this signal will reset byte is updated with the contents of TMR3H when a Timer3. ECCP2 can also start an A/D conversion if the write occurs to TMR3L. This allows a user to write all A/D module is enabled (see Section17.3.4 “Special 16 bits to both the high and low bytes of Timer3 at once. Event Trigger” for more information). The high byte of Timer3 is not directly readable or The module must be configured as either a timer or writable in this mode. All reads and writes must take synchronous counter to take advantage of this feature. place through the Timer3 High Byte Buffer register. When used this way, the CCPRxH:CCPRxL register Writes to TMR3H do not clear the Timer3 prescaler. pair effectively becomes a period register for Timer3. The prescaler is only cleared on writes to TMR3L. If Timer3 is running in Asynchronous Counter mode, the Reset operation may not work. 15.3 Using the Timer1 Oscillator as the Timer3 Clock Source In the event that a write to Timer3 coincides with a Special Event Trigger from a CCP module, the write will The Timer1 internal oscillator may be used as the clock take precedence. source for Timer3. The Timer1 oscillator is enabled by Note: The Special Event Triggers from the CCPx setting the T1OSCEN (T1CON<3>) bit. To use it as the module will not set the TMR3IF interrupt Timer3 clock source, the TMR3CS bit must also be set. flag bit (PIR2<1>). As previously noted, this also configures Timer3 to increment on every rising edge of the oscillator source. The Timer1 oscillator is described in Section13.0 “Timer1 Module”. TABLE 15-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR2 OSCFIF CMIF — EEIF BCL1IF HLVDIF TMR3IF CCP2IF 60 PIE2 OSCFIE CMIE — EEIE BCL1IE HLVDIE TMR3IE CCP2IE 60 IPR2 OSCFIP CMIP — EEIP BCL1IP HLVDIP TMR3IP CCP2IP 60 TMR3L Timer3 Register Low Byte 59 TMR3H Timer3 Register High Byte 59 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 58 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 59 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2008 Microchip Technology Inc. DS39646C-page 175

PIC18F8722 FAMILY NOTES: DS39646C-page 176 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 16.0 TIMER4 MODULE 16.1 Timer4 Operation The Timer4 timer module has the following features: Timer4 can be used as the PWM time base for the PWM mode of the CCP modules. The TMR4 register is • 8-bit Timer register (TMR4) readable and writable and is cleared on any device • 8-bit Period register (PR4) Reset. The input clock (FOSC/4) has a prescale option • Readable and writable (both registers) of 1:1, 1:4 or 1:16, selected by control bits • Software programmable prescaler (1:1, 1:4, 1:16) T4CKPS<1:0> (T4CON<1:0>). The match output of • Software programmable postscaler (1:1 to 1:16) TMR4 goes through a 4-bit postscaler (which gives a • Interrupt on TMR4 match of PR4 1:1 to 1:16 scaling inclusive) to generate a TMR4 Timer4 has a control register shown in Register16-1. interrupt, latched in flag bit, TMR4IF (PIR3<3>). Timer4 can be shut off by clearing control bit, TMR4ON The prescaler and postscaler counters are cleared (T4CON<2>), to minimize power consumption. The when any of the following occurs: prescaler and postscaler selection of Timer4 are also • a write to the TMR4 register controlled by this register. Figure16-1 is a simplified • a write to the T4CON register block diagram of the Timer4 module. • any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR4 is not cleared when T4CON is written. REGISTER 16-1: T4CON: TIMER4 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 T4OUTPS<3:0>: Timer4 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR4ON: Timer4 On bit 1 = Timer4 is on 0 = Timer4 is off bit 1-0 T4CKPS<1:0>: Timer4 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 © 2008 Microchip Technology Inc. DS39646C-page 177

PIC18F8722 FAMILY 16.2 Timer4 Interrupt 16.3 Output of TMR4 The Timer4 module has an 8-bit Period register, PR4, The output of TMR4 (before the postscaler) is used which is both readable and writable. Timer4 increments only as a PWM time base for the CCP modules. It is not from 00h until it matches PR4 and then resets to 00h on used as a baud rate clock for the MSSP, as is the the next increment cycle. The PR4 register is initialized Timer2 output. to FFh upon Reset. FIGURE 16-1: TIMER4 BLOCK DIAGRAM Sets Flag TMR4 Output(1) bit TMR4IF Prescaler Reset FOSC/4 TMR4 1:1, 1:4, 1:16 2 Comparator Postscaler EQ 1:1 to 1:16 T4CKPS<1:0> PR4 4 T4OUTPS<3:0> TABLE 16-1: REGISTERS ASSOCIATED WITH TIMER4 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 60 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 60 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 60 TMR4 Timer4 Register 61 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 61 PR4 Timer4 Period Register 61 Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer4 module. DS39646C-page 178 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 17.0 CAPTURE/COMPARE/PWM Capture and Compare operations described in this chap- (CCP) MODULES ter apply to all standard and Enhanced CCP modules. The operations of PWM mode described in Section17.4 The PIC18F8722 family of devices all have a total of “PWM Mode” apply to CCP4 and CCP5 only. five CCP (Capture/Compare/PWM) modules. Two of Note: Throughout this section and Section18.0 these (CCP4 and CCP5) implement standard Capture, “Enhanced Capture/Compare/PWM Compare and Pulse-Width Modulation (PWM) modes (ECCP) Module”, references to register and are discussed in this section. The other three and bit names that may be associated with modules (ECCP1, ECCP2, ECCP3) implement a specific CCP module are referred to standard Capture and Compare modes, as well as generically by the use of ‘x’ or ‘y’ in place of Enhanced PWM modes. These are discussed in the specific module number. Thus, Section18.0 “Enhanced Capture/Compare/PWM “CCPxCON” might refer to the control (ECCP) Module”. register for CCP4 or CCP5, or ECCP1, Each CCP/ECCP module contains a 16-bit register ECCP2 or ECCP3. “CCPxCON” is used which can operate as a 16-bit Capture register, a 16-bit throughout these sections to refer to the Compare register or a PWM Master/Slave Duty Cycle module control register, regardless of register. For the sake of clarity, all CCP module opera- whether the CCP module is a standard or tions in the following sections are described with enhanced implementation. respect to CCP4, but are equally applicable to CCP5. REGISTER 17-1: CCPxCON: CCPx CONTROL REGISTER (CCP4 AND CCP5 MODULES) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCP Module x Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight Most Significant bits (DCx<9:2>) of the duty cycle are found in CCPRxL. bit 3-0 CCPxM<3:0>: CCP Module x Mode Select bits 0000 = Capture/Compare/PWM disabled; resets CCPx module 0001 = Reserved 0010 = Compare mode, toggle output on match; CCPxIF bit is set 0011 = Reserved 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, initialize CCPx pin low; on compare match, force CCPx pin high; CCPxIF bit is set 1001 = Compare mode, initialize CCPx pin high; on compare match, force CCPx pin low; CCPxIF bit is set 1010 = Compare mode, generate software interrupt on compare match; CCPxIF bit is set; CCPx pin reflects I/O state 1011 = Compare mode, trigger special event; CCPxIF bit is set, CCPx pin is unaffected (For the effects of the trigger, see Section17.3.4 “Special Event Trigger”.) 11xx = PWM mode © 2008 Microchip Technology Inc. DS39646C-page 179

PIC18F8722 FAMILY 17.1 CCP Module Configuration The assignment of a particular timer to a module is determined by the Timer to CCP enable bits in the Each Capture/Compare/PWM module is associated T3CON register (Register15-1). Depending on the with a control register (generically, CCPxCON) and a configuration selected, up to four timers may be active data register (CCPRx). The data register, in turn, is at once, with modules in the same configuration comprised of two 8-bit registers: CCPRxL (low byte) (Capture/Compare or PWM) sharing timer resources. and CCPRxH (high byte). All registers are both The possible configurations are shown in Figure17-1. readable and writable. 17.1.2 ECCP2 PIN ASSIGNMENT 17.1.1 CCP MODULES AND TIMER The pin assignment for ECCP2 (Capture input, RESOURCES Compare and PWM output) can change, based on The CCP/ECCP modules utilize Timers 1, 2, 3 or 4, device configuration. The CCP2MX Configuration bit depending on the mode selected. Timer1 and Timer3 determines which pin ECCP2 is multiplexed to. By are available to modules in Capture or Compare default, it is assigned to RC1 (CCP2MX = 1). If the modes, while Timer2 and Timer4 are available for Configuration bit is cleared, ECCP2 is multiplexed with modules in PWM mode. RE7 in Microcontroller mode, or RE3 in all other modes. TABLE 17-1: CCP MODE – TIMER Changing the pin assignment of ECCP2 does not auto- RESOURCE matically change any requirements for configuring the CCP Mode Timer Resource port pin. Users must always verify that the appropriate TRIS register is configured correctly for ECCP2 Capture Timer1 or Timer3 operation regardless of where it is located. Compare Timer1 or Timer3 PWM Timer2 or Timer4 FIGURE 17-1: CCP AND TIMER INTERCONNECT CONFIGURATIONS T3CCP<2:1> = 00 T3CCP<2:1> = 01 T3CCP<2:1> = 10 T3CCP<2:1> = 11 TMR1 TMR3 TMR1 TMR3 TMR1 TMR3 TMR1 TMR3 ECCP1 ECCP1 ECCP1 ECCP1 ECCP2 ECCP2 ECCP2 ECCP2 ECCP3 ECCP3 ECCP3 ECCP3 CCP4 CCP4 CCP4 CCP4 CCP5 CCP5 CCP5 CCP5 TMR2 TMR4 TMR2 TMR4 TMR2 TMR4 TMR2 TMR4 Timer1 is used for all Capture Timer1 and Timer2 are used Timer1 and Timer2 are used Timer3 is used for all Capture and Compare operations for for Capture and Compare or for Capture and Compare or and Compare operations for all CCP modules. Timer2 is PWM operations for ECCP1 PWM operations for ECCP1 all CCP modules. Timer4 is used for PWM operations for only (depending on selected and ECCP2 only (depending used for PWM operations for all CCP modules. Modules mode). on the mode selected for each all CCP modules. Modules may share either timer All other modules use either module). Both modules may may share either timer resource as a common time Timer3 or Timer4. Modules use a timer as a common time resource as a common time base. may share either timer base if they are both in base. Capture/Compare or PWM Timer3 and Timer4 are not resource as a common time Timer1 and Timer2 are not modes. available. base if they are in Capture/ available. Compare or PWM modes. The other modules use either Timer3 or Timer4. Modules may share either timer resource as a common time base if they are in Capture/ Compare or PWM modes. DS39646C-page 180 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 17.2 Capture Mode 17.2.3 SOFTWARE INTERRUPT In Capture mode, the CCPRxH:CCPRxL register pair When the Capture mode is changed, a false capture captures the 16-bit value of the TMR1 or TMR3 interrupt may be generated. The user should keep the registers when an event occurs on the corresponding CCPxIE interrupt enable bit clear to avoid false inter- CCPx pin. An event is defined as one of the following: rupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode. • every falling edge • every rising edge 17.2.4 CCP PRESCALER • every 4th rising edge There are four prescaler settings in Capture mode; they • every 16th rising edge are specified as part of the operating mode selected by The event is selected by the mode select bits, the mode select bits (CCPxM<3:0>). Whenever the CCPxM<3:0> (CCPxCON<3:0>). When a capture is CCP module is turned off, or Capture mode is disabled, made, the interrupt request flag bit, CCPxIF, is set; it the prescaler counter is cleared. This means that any must be cleared in software. If another capture occurs Reset will clear the prescaler counter. before the value in the CCPRx registers is read, the old Switching from one capture prescaler to another may captured value is overwritten by the new captured value. generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from 17.2.1 CCPx PIN CONFIGURATION a non-zero prescaler. Example17-1 shows the In Capture mode, the appropriate CCPx pin should be recommended method for switching between capture configured as an input by setting the corresponding prescalers. This example also clears the prescaler TRIS direction bit. counter and will not generate the “false” interrupt. Note: If a CCPx pin is configured as an output, a EXAMPLE 17-1: CHANGING BETWEEN write to the port can cause a capture CAPTURE PRESCALERS condition. (CCP5 SHOWN) 17.2.2 TIMER1/TIMER3 MODE SELECTION CLRF CCP5CON ; Turn CCP module off The timers that are to be used with the capture feature MOVLW NEW_CAPT_PS ; Load WREG with the ; new prescaler mode (Timer1 and/or Timer3) must be running in Timer mode or ; value and CCP ON Synchronized Counter mode. In Asynchronous Counter MOVWF CCP5CON ; Load CCP5CON with mode, the capture operation will not work. The timer to be ; this value used with each CCP module is selected in the T3CON register (see Section17.1.1 “CCP Modules and Timer Resources”). FIGURE 17-2: CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H TMR3L Set Flag bit CCP4IF T3CCP2 TMR3 Prescaler Enable ÷ 1, 4, 16 RG3/CCP4 pin CCPR4H CCPR4L TMR1 and T3CCP2 Enable Edge Detect TMR1H TMR1L CCP1CON<3:0> Q’s © 2008 Microchip Technology Inc. DS39646C-page 181

PIC18F8722 FAMILY 17.3 Compare Mode 17.3.3 SOFTWARE INTERRUPT MODE In Compare mode, the 16-bit value of the CCPRx When the Generate Software Interrupt mode is chosen registers is constantly compared against either the (CCPxM<3:0> = 1010), the corresponding CCPx pin is TMR1 or TMR3 register pair value. When a match not affected. Only a CCP interrupt is generated, if occurs, the CCPx pin can be: enabled and the CCPxIE bit is set. • driven high 17.3.4 SPECIAL EVENT TRIGGER • driven low All CCP modules are equipped with a Special Event • toggled (high-to-low or low-to-high) Trigger. This is an internal hardware signal generated • remain unchanged (that is, reflects the state of the in Compare mode to trigger actions by other modules. I/O latch) The Special Event Trigger is enabled by selecting The action on the pin is based on the value of the mode the Compare Special Event Trigger mode select bits (CCPxM<3:0>). At the same time, the (CCPxM<3:0> = 1011). interrupt flag bit, CCPxIF, is set. For all CCP modules, the Special Event Trigger resets the timer register pair for whichever timer resource is 17.3.1 CCPx PIN CONFIGURATION currently assigned as the module’s time base. This The user must configure the CCPx pin as an output by allows the CCPRx registers to serve as a programmable clearing the appropriate TRIS bit. period register for either timer. Note: Clearing the CCPxCON register will force The ECCP2 Special Event Trigger can also start an A/D the compare output latch (depending on conversion. In order to do this, the A/D converter must device configuration) to the default low already be enabled. level. This is not the port I/O data latch. 17.3.2 TIMER1/TIMER3 MODE SELECTION Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. FIGURE 17-3: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger Set Flag bit CCP4IF CCPR4H CCPR4L Q S Output RG3/CCP4 pin R Logic Match Comparator TRISG<3> Output Enable CCP4CON<3:0> T3CCP2 0 1 Mode Select TMR1H TMR1L TMR3H TMR3L DS39646C-page 182 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 17-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 RCON IPEN SBOREN — RI TO PD POR BOR 56 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 PIR2 OSCFIF CMIF — EEIF BCL1IF HLVDIF TMR3IF CCP2IF 60 PIE2 OSCFIE CMIE — EEIE BCL1IE HLVDIE TMR3IE CCP2IE 60 IPR2 OSCFIP CMIP — EEIP BCL1IP HLVDIP TMR3IP CCP2IP 60 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 60 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 60 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 60 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 60 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 60 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60 TRISH(1) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 60 TMR1L Timer1 Register Low Byte 58 TMR1H Timer1 Register High Byte 58 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 58 TMR3H Timer3 Register High Byte 59 TMR3L Timer3 Register Low Byte 59 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 59 CCPR1L Enhanced Capture/Compare/PWM Register 1 Low Byte 59 CCPR1H Enhanced Capture/Compare/PWM Register 1 High Byte 59 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 59 CCPR2L Enhanced Capture/Compare/PWM Register 2 Low Byte 59 CCPR2H Enhanced Capture/Compare/PWM Register 2 High Byte 59 CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 59 CCP3CON P3M1 P3M0 DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 59 CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 61 CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 61 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3. Note 1: Implemented on 80-pin devices only. © 2008 Microchip Technology Inc. DS39646C-page 183

PIC18F8722 FAMILY 17.4 PWM Mode 17.4.1 PWM PERIOD In Pulse-Width Modulation (PWM) mode, the CCPx pin The PWM period is specified by writing to the PR2 produces up to a 10-bit resolution PWM output. Since (PR4) register. The PWM period can be calculated the CCP4 and CCP5 pins are multiplexed with a using the following formula: PORTG data latch, the appropriate TRISG bit must be cleared to make the CCP4 or CCP5 pin an output. EQUATION 17-1: Note: Clearing the CCP4CON or CCP5CON PWM Period = [(PR2) + 1] • 4 • TOSC • register will force the RG3 or RG4 output (TMR2 Prescale Value) latch (depending on device configuration) to the default low level. This is not the PWM frequency is defined as 1/[PWM period]. PORTG I/O data latch. When TMR2 (TMR4) is equal to PR2 (PR4), the Figure17-4 shows a simplified block diagram of the following three events occur on the next increment CCP module in PWM mode. cycle: For a step-by-step procedure on how to set up a CCP • TMR2 (TMR4) is cleared module for PWM operation, see Section17.4.3 • The CCPx pin is set (exception: if PWM duty “Setup for PWM Operation”. cycle=0%, the CCPx pin will not be set) • The PWM duty cycle is latched from CCPRxL into FIGURE 17-4: SIMPLIFIED PWM BLOCK CCPRxH DIAGRAM Note: The Timer2 and Timer 4 postscalers (see Section14.0 “Timer2 Module” and CCPxCON<5:4> Duty Cycle Registers Section16.0 “Timer4 Module”) are not CCPRxL used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. CCPRxH (Slave) CCPx Output 17.4.2 PWM DUTY CYCLE Comparator R Q The PWM duty cycle is specified by writing to the CCPRxL register and to the CCPxCON<5:4> bits. Up TMR2 (TMR4) (Note 1) to 10-bit resolution is available. The CCPRxL contains S the eight MSbs and the CCPxCON<5:4> contains the two LSbs. This 10-bit value is represented by Corresponding Comparator TRIS bit CCPRxL:CCPxCON<5:4>. The following equation is Clear Timer, CCPx pin and used to calculate the PWM duty cycle in time: latch D.C. PR2 (PR4) EQUATION 17-2: Note1:The 8-bit TMR2 or TMR4 value is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to cre- PWM Duty Cycle = (CCPRxL:CCPxCON<5:4>) • ate the 10-bit time base. TOSC • (TMR2 Prescale Value) A PWM output (Figure17-5) has a time base (period) and a time that the output stays high (duty cycle). CCPRxL and CCPxCON<5:4> can be written to at any The frequency of the PWM is the inverse of the time, but the duty cycle value is not latched into period (1/period). CCPRxH until after a match between PR2 (PR4) and TMR2 (TMR4) occurs (i.e., the period is complete). In FIGURE 17-5: PWM OUTPUT PWM mode, CCPRxH is a read-only register. Period Duty Cycle TMR2 (TMR4) = PR2 (PR4) TMR2 (TMR4) = Duty Cycle TMR2 (TMR4) = PR2 (TMR4) DS39646C-page 184 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY The CCPRxH register and a 2-bit internal latch are 17.4.3 SETUP FOR PWM OPERATION used to double-buffer the PWM duty cycle. This The following steps should be taken when configuring double-buffering is essential for glitchless PWM the CCP module for PWM operation: operation. 1. Set the PWM period by writing to the PR2 (PR4) When the CCPRxH and 2-bit latch match TMR2 register. (TMR4), concatenated with an internal 2-bit Q clock or 2. Set the PWM duty cycle by writing to the 2 bits of the TMR2 (TMR4) prescaler, the CCPx pin is CCPRxL register and CCPxCON<5:4> bits. cleared. 3. Make the CCPx pin an output by clearing the The maximum PWM resolution (bits) for a given PWM appropriate TRIS bit. frequency is given by the equation: 4. Set the TMR2 (TMR4) prescale value, then enable Timer2 (Timer4) by writing to T2CON EQUATION 17-3: (T4CON). log⎛--F---O----S---C---⎞ 5. Configure the CCPx module for PWM operation. ⎝FPWM⎠ PWM Resolution (max) = -----------------------------bits log(2) Note: If the PWM duty cycle value is longer than the PWM period, the CCPx pin will not be cleared. TABLE 17-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 © 2008 Microchip Technology Inc. DS39646C-page 185

PIC18F8722 FAMILY TABLE 17-4: REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 RCON IPEN SBOREN — RI TO PD POR BOR 56 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 60 PIE3 SSP2IE BCL2IF RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 60 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 60 TMR2 Timer2 Register 58 PR2 Timer2 Period Register 58 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 58 TMR4 Timer4 Register 61 PR4 Timer4 Period Register 61 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 61 CCPR1L Enhanced Capture/Compare/PWM Register 1 Low Byte 59 CCPR1H Enhanced Capture/Compare/PWM Register 1 High Byte 59 CCPR2L Enhanced Capture/Compare/PWM Register 2 Low Byte 59 CCPR2H Enhanced Capture/Compare/PWM Register 2 High Byte 59 CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 61 CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 61 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM, Timer2 or Timer4. DS39646C-page 186 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 18.0 ENHANCED CAPTURE/ The control register for the Enhanced CCP modules is COMPARE/PWM (ECCP) shown in Register18-1. It differs from the CCPxCON registers discussed in Section17.0 “Capture/ MODULE Compare/PWM (CCP) Modules” in that the two Most In the PIC18F8722 family of devices, ECCP1, ECCP2 Significant bits are implemented to control PWM and ECCP3 are implemented as a standard CCP functionality. In addition to the expanded range of module with Enhanced PWM capabilities. These modes available through the Enhanced CCPxCON include the provision for 2 or 4 output channels, user register, the ECCP modules each have two additional selectable polarity, dead-band control and automatic features associated with Enhanced PWM operation shutdown and restart. The enhanced features are and auto-shutdown features. They are: discussed in detail in Section18.4 “Enhanced PWM • ECCPxDEL (Dead-Band Delay) Mode”. Capture, Compare and single-output PWM • ECCPxAS (Auto-Shutdown Configuration) functions of the ECCP module are the same as described for the standard CCP module. REGISTER 18-1: CCPxCON: ENHANCED CCPx CONTROL REGISTER (ECCP1, ECCP2, ECCP3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 PxM1:PxM0: Enhanced PWM Output Configuration bits If CCPxM<3:2> = 00, 01, 10: xx = PxA assigned as Capture/Compare input/output; PxB, PxC, PxD assigned as port pins If CCPxM<3:2> = 11: 00 = Single output: PxA modulated; PxB, PxC, PxD assigned as port pins 01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive 10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive bit 5-4 DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPRxL. bit 3-0 CCPxM3:CCPxM0: Enhanced CCP Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCPx module) 0001 = Reserved 0010 = Compare mode: toggle output on match 0011 = Capture mode 0100 = Capture mode: every falling edge 0101 = Capture mode: every rising edge 0110 = Capture mode: every 4th rising edge 0111 = Capture mode: every 16th rising edge 1000 = Compare mode: initialize ECCPx pin low; set output on compare match (set CCPxIF) 1001 = Compare mode: initialize ECCPx pin high; clear output on compare match (set CCPxIF) 1010 = Compare mode: generate software interrupt only; ECCPx pin reverts to I/O state 1011 = Compare mode: trigger special event (ECCP resets TMR1 or TMR3, sets CCPxIF bit; ECCP2 trigger starts A/D conversion if A/D module is enabled) 1100 = PWM mode: PxA, PxC active-high; PxB, PxD active-high 1101 = PWM mode: PxA, PxC active-high; PxB, PxD active-low 1110 = PWM mode: PxA, PxC active-low; PxB, PxD active-high 1111 = PWM mode: PxA, PxC active-low; PxB, PxD active-low © 2008 Microchip Technology Inc. DS39646C-page 187

PIC18F8722 FAMILY 18.1 ECCP Outputs and Configuration 18.1.2 ECCP MODULE OUTPUTS, PROGRAM MEMORY MODES AND Each of the Enhanced CCP modules may have up to EMB ADDRESS BUS WIDTH four PWM outputs, depending on the selected operating mode. These outputs, designated PxA For PIC18F8527/8622/8627/8722 devices, the through PxD, are multiplexed with various I/O pins. program memory mode of the device (Section7.2 Some ECCPx pin assignments are constant, while “Address and Data Width” and Section7.4 “Pro- others change based on device configuration. For gram Memory Modes and the External Memory those pins that do change, the controlling bits are: Bus”) impacts both pin multiplexing and the operation of the module. • CCP2MX Configuration bit (CONFIG3H<0>) • ECCPMX Configuration bit (CONFIG3H<1>) The ECCP2 input/output (ECCP2/P2A) can be multi- • Program Memory mode (set by Configuration bits, plexed to one of three pins. By default, this is RC1 for CONFIG3L<1:0>) all devices; in this case, the default is in effect when CCP2MX is set and the device is operating in Micro- The pin assignments for the Enhanced CCP modules controller mode. With PIC18F8527/8622/8627/8722 are summarized in Table18-1, Table18-2 and devices, three other options exist. When CCP2MX is Table18-3. To configure the I/O pins as PWM outputs, not set (= 0) and the device is in Microcontroller mode, the proper PWM mode must be selected by setting the ECCP2/P2A is multiplexed to RE7; in all other program PxMx and CCPxMx bits (CCPxCON<7:6> and <3:0>, memory modes, it is multiplexed to RB3. respectively). The appropriate TRIS direction bits for the corresponding port pins must also be set as Another option is for ECCPMX to be set while the outputs. device is operating in one of the three other program memory modes. In this case, ECCP1 and ECCP3 oper- 18.1.1 USE OF CCP4 AND CCP5 WITH ate as compatible (i.e., single output) CCP modules. ECCP1 AND ECCP3 The pins used by their other outputs (PxB through PxD) are available for other multiplexed functions. ECCP2 Only the ECCP2 module has four dedicated output pins continues to operate as an Enhanced CCP module available for use. Assuming that the I/O ports or other regardless of the program memory mode. multiplexed functions on those pins are not needed, they may be used whenever needed without interfering The final option is that the ABW<1:0> Configuration with any other CCP module. bits can be used to select 8, 12, 16 or 20-bit EMB addressing. Pins not assigned to EMB address pins are ECCP1 and ECCP3, on the other hand, only have available for peripheral or port functions. three dedicated output pins: ECCPx/P3A, PxB and PxC. Whenever these modules are configured for Quad PWM mode, the pin used for CCP4 or CCP5 takes priority over the D output pins for ECCP3 and ECCP1, respectively. DS39646C-page 188 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 18-1: PIN CONFIGURATIONS FOR ECCP1 CCP1CON ECCP Mode RC2 RE6 RE5 RG4 RH7 RH6 Configuration PIC18F6527/6622/6627/6722 Devices: Compatible CCP 00xx 11xx ECCP1 RE6 RE5 RG4/CCP5 N/A N/A Dual PWM 10xx 11xx P1A P1B RE5 RG4/CCP5 N/A N/A Quad PWM x1xx 11xx P1A P1B P1C CCP5/P1D(1) N/A N/A PIC18F8527/8622/8627/8722 Devices, ECCPMX = 1, Microcontroller mode: Compatible CCP 00xx 11xx ECCP1 RE6 RE5 RG4/CCP5 RH7/AN15 RH6/AN14 Dual PWM 10xx 11xx P1A P1B RE5 RG4/CCP5 RH7/AN15 RH6/AN14 Quad PWM x1xx 11xx P1A P1B P1C CCP5/P1D(1) RH7/AN15 RH6/AN14 PIC18F8527/8622/8627/8722 Devices, ECCPMX = 0, Microcontroller mode: Compatible CCP 00xx 11xx ECCP1 RE6 RE5 RG4/CCP5 RH7/AN15 RH6/AN14 Dual PWM 10xx 11xx P1A RE6 RE5 RG4/CCP5 P1B RH6/AN14 Quad PWM x1xx 11xx P1A RE6 RE5 CCP5/P1D(1) P1B P1C PIC18F8527/8622/8627/8722 Devices, ECCPMX = 1, all other Program Memory modes: Compatible CCP 00xx 11xx ECCP1 AD14(2) AD13(2) RG4/CCP5 RH7/AN15 RH6/AN14 Dual PWM 10xx 11xx P1A P1B/AD14(2) AD13(2) RG4/CCP5 RH7/AN15 RH6/AN14 Quad PWM x1xx 11xx P1A P1B/AD14(2) P1C/AD13(2) CCP5/P1D(1) RH7/AN15 RH6/AN14 PIC18F8527/8622/8627/8722 Devices, ECCPMX = 0, all other Program Memory modes: Compatible CCP 00xx 11xx ECCP1 AD14(2) AD13(2) RG4/CCP5 RH7/AN15 RH6/AN14 Dual PWM 10xx 11xx P1A AD14(2) AD13(2) RG4/CCP5 P1B RH6/AN14 Quad PWM x1xx 11xx P1A AD14(2) AD13(2) CCP5/P1D(1) P1B P1C Legend: x = Don’t care, N/A = Not available. Shaded cells indicate pin assignments not used by ECCP1 in a given mode. Note 1: With ECCP1 in Quad PWM mode, the CCP5 module’s output overrides P1D. 2: The EMB address bus width will determine whether the pin will perform an EMB or port/peripheral function. © 2008 Microchip Technology Inc. DS39646C-page 189

PIC18F8722 FAMILY TABLE 18-2: PIN CONFIGURATIONS FOR ECCP2 CCP2CON ECCP Mode RB3 RC1 RE7 RE2 RE1 RE0 Configuration PIC18F6527/6622/6627/6722 Devices, CCP2MX = 1: Compatible CCP 00xx 11xx RB3/INT3 ECCP2 RE7 RE2 RE1 RE0 Dual PWM 10xx 11xx RB3/INT3 P2A RE7 P2B RE1 RE0 Quad PWM x1xx 11xx RB3/INT3 P2A RE7 P2B P2C P2D PIC18F6527/6622/6627/6722 Devices CCP2MX = 0: Compatible CCP 00xx 11xx RB3/INT3 RC1/T1OSI ECCP2 RE2 RE1 RE0 Dual PWM 10xx 11xx RB3/INT3 RC1/T1OSI P2A P2B RE1 RE0 Quad PWM x1xx 11xx RB3/INT3 RC1/T1OSI P2A P2B P2C P2D PIC18F8527/8622/8627/8722 Devices, CCP2MX = 1, Microcontroller mode: Compatible CCP 00xx 11xx RB3/INT3 ECCP2 RE7 RE2 RE1 RE0 Dual PWM 10xx 11xx RB3/INT3 P2A RE7 P2B RE1 RE0 Quad PWM x1xx 11xx RB3/INT3 P2A RE7 P2B P2C P2D PIC18F8527/8622/8627/8722 Devices, CCP2MX = 0, Microcontroller mode: Compatible CCP 00xx 11xx RB3/INT3 RC1/T1OSI ECCP2 RE2 RE1 RE0 Dual PWM 10xx 11xx RB3/INT3 RC1/T1OSI P2A P2B RE1 RE0 Quad PWM x1xx 11xx RB3/INT3 RC1/T1OSI P2A P2B P2C P2D PIC18F8527/8622/8627/8722 Devices, CCP2MX = 1, all other Program Memory modes: Compatible CCP 00xx 11xx RB3/INT3 ECCP2 AD15(1) AD10(1) AD9(1) AD8(1) Dual PWM 10xx 11xx RB3/INT3 P2A AD15(1) AD10/P2B(1) AD9(1) AD8(1) Quad PWM x1xx 11xx RB3/INT3 P2A AD15(1) AD10/P2B(1) AD9/P2C(1) P2D/AD8(1) PIC18F8527/8622/8627/8722 Devices, CCP2MX = 0, all other Program Memory modes: Compatible CCP 00xx 11xx ECCP2 RC1/T1OSI AD15(1) AD10(1) AD9(1) AD8(1) Dual PWM 10xx 11xx P2A RC1/T1OSI AD15(1) AD10/P2B(1) AD9(1) AD8(1) Quad PWM x1xx 11xx P2A RC1/T1OSI AD15(1) AD10/P2B(1) AD9/P2C(1) P2D/AD8(1) Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP2 in a given mode. Note 1: The EMB address bus width will determine whether the pin will perform an EMB or port/peripheral function. DS39646C-page 190 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 18-3: PIN CONFIGURATIONS FOR ECCP3 CCP3CON ECCP Mode RG0 RE4 RE3 RG3 RH5 RH4 Configuration PIC18F6527/6622/6627/6722 Devices: Compatible CCP 00xx 11xx ECCP3 RE4 RE3 RG3/CCP4 N/A N/A Dual PWM 10xx 11xx P3A P3B RE3 RG3/CCP4 N/A N/A Quad PWM x1xx 11xx P3A P3B P3C CCP4/P3D(1) N/A N/A PIC18F8527/8622/8627/8722 Devices, ECCPMX = 1, Microcontroller mode: Compatible CCP 00xx 11xx ECCP3 RE4 RE3 RG3/CCP4 RH5/AN13 RH4/AN12 Dual PWM 10xx 11xx P3A P3B RE3 RG3/CCP4 RH5/AN13 RH4/AN12 Quad PWM x1xx 11xx P3A P3B P3C CCP4/P3D(1) RH5/AN13 RH4/AN12 PIC18F8527/8622/8627/8722 Devices, ECCPMX = 0, Microcontroller mode: Compatible CCP 00xx 11xx ECCP3 RE4 RE3 RG3/CCP4 RH5/AN13 RH4/AN12 Dual PWM 10xx 11xx P3A RE4 RE3 RG3/CCP4 P3B RH4/AN12 Quad PWM x1xx 11xx P3A RE4 RE3 CCP4/P3D(1) P3B P3C PIC18F8527/8622/8627/8722 Devices, ECCPMX = 1, all other Program Memory modes: Compatible CCP 00xx 11xx ECCP3 AD12(2) AD10(2) RG3/CCP4 RH5/AN13 RH4/AN12 Dual PWM 10xx 11xx P3A AD12/P3B(2) AD10(2) RG3/CCP4 RH5/AN13 RH4/AN12 Quad PWM x1xx 11xx P3A AD12/P3B(2) P3C/AD10(1) CCP4/P3D(1) RH5/AN13 RH4/AN12 PIC18F8527/8622/8627/8722 Devices, ECCPMX = 0, all other Program Memory modes: Compatible CCP 00xx 11xx ECCP3 AD12(2) AD10(2) RG3/CCP4 RH5/AN13 RH4/AN12 Dual PWM 10xx 11xx P3A AD12(2) AD10(2) RG3/CCP4 P3B RH4/AN12 Quad PWM x1xx 11xx P3A AD12(2) AD10(2) CCP4/P3D(1) P3B P3C Legend: x = Don’t care, N/A = Not available. Shaded cells indicate pin assignments not used by ECCP3 in a given mode. Note 1: With ECCP3 in Quad PWM mode, the CCP4 module’s output overrides P3D. 2: The EMB address bus width will determine whether the pin will perform an EMB or port/peripheral function. © 2008 Microchip Technology Inc. DS39646C-page 191

PIC18F8722 FAMILY 18.1.3 ECCP MODULES AND TIMER For the sake of clarity, Enhanced PWM mode operation RESOURCES is described generically throughout this section with respect to ECCP1 and TMR2 modules. Control register Like the standard CCP modules, the ECCP modules names are presented in terms of ECCP1. All three can utilize Timers 1, 2, 3 or 4, depending on the mode Enhanced modules, as well as the two timer resources, selected. Timer1 and Timer3 are available for modules can be used interchangeably and function identically. in Capture or Compare modes, while Timer2 and TMR2 or TMR4 can be selected for PWM operation by Timer4 are available for modules in PWM mode. selecting the proper bits in T3CON. Additional details on timer resources are provided in Section17.1.1 “CCP Modules and Timer Figure18-1 shows a simplified block diagram of PWM Resources”. operation. All control registers are double-buffered and are loaded at the beginning of a new PWM cycle (the 18.2 Capture and Compare Modes period boundary when Timer2 resets) in order to prevent glitches on any of the outputs. The exception is With the exception of the Special Event Trigger the PWM Dead-Band Delay register, ECCP1DEL, discussed below, the Capture and Compare modes of which is loaded at either the duty cycle boundary or the the ECCP modules are identical in operation to that of boundary period (whichever comes first). Because of CCP4. These are discussed in detail in Section17.2 the buffering, the module waits until the assigned timer “Capture Mode” and Section17.3 “Compare resets instead of starting immediately. This means that Mode”. Enhanced PWM waveforms do not exactly match the standard PWM waveforms, but are instead offset by 18.2.1 SPECIAL EVENT TRIGGER one full instruction cycle (4 TOSC). The Special Event Trigger output of ECCPx resets the As before, the user must manually configure the TMR1 or TMR3 register pair, depending on which timer appropriate TRIS bits for output. resource is currently selected. This allows the CCPRx registers to effectively be 16-bit programmable period 18.4.1 PWM PERIOD registers for Timer1 or Timer3. The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the 18.3 Standard PWM Mode following equation: When configured in Single Output mode, the ECCP EQUATION 18-1: module functions identically to the standard CCP module in PWM mode as described in Section17.4 PWM Period = [(PR2) + 1] • 4 • TOSC • “PWM Mode”. This is also sometimes referred to as (TMR2 Prescale Value) “Compatible CCP” mode as in Tables18-1 through18-3. PWM frequency is defined as 1/[PWM period]. When TMR2 is equal to PR2, the following three events occur Note: When setting up single output PWM on the next increment cycle: operations, users are free to use either of the processes described in Section17.4.3 • TMR2 is cleared “Setup for PWM Operation” or • The ECCP1 pin is set (if PWM duty cycle=0%, Section18.4.9 “Setup for PWM Opera- the ECCP1 pin will not be set) tion”. The latter is more generic, but will • The PWM duty cycle is copied from CCPR1L into work for either single or multi-output PWM. CCPR1H Note: The Timer2 postscaler (see Section14.0 18.4 Enhanced PWM Mode “Timer2 Module”) is not used in the The Enhanced PWM mode provides additional PWM determination of the PWM frequency. The output options for a broader range of control applica- postscaler could be used to have a servo tions. The module is a backward compatible version of update rate at a different frequency than the standard CCP module and offers up to four outputs, the PWM output. designated PxA through PxD. Users are also able to select the polarity of the signal (either active-high or active-low). The module’s output mode and polarity areconfigured by setting the PxM<1:0> and CCPxM<3:0> bits of the CCPxCON register (CCPxCON<7:6> and CCPxCON<3:0>, respectively). DS39646C-page 192 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 18-1: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE CCP1CON<5:4> P1M1<1:0> CCP1M<3:0> Duty Cycle Registers 2 4 CCPR1L ECCP1/P1A ECCP1/P1A TRISx<x> CCPR1H (Slave) P1B P1B Output TRISx<x> Comparator R Q Controller P1C P1C TMR2 (Note 1) S TRISx<x> P1D P1D Comparator Clear Timer, TRISx<x> set ECCP1 pin and latch D.C. PR2 ECCP1DEL Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. 18.4.2 PWM DUTY CYCLE The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This The PWM duty cycle is specified by writing to the double-buffering is essential for glitchless PWM opera- CCPR1L register and to the CCP1CON<5:4> bits. Up tion. When the CCPR1H and 2-bit latch match TMR2, to 10-bit resolution is available. The CCPR1L contains concatenated with an internal 2-bit Q clock or two bits the eight MSbs and the CCP1CON<5:4> contains the of the TMR2 prescaler, the ECCP1 pin is cleared. The two LSbs. This 10-bit value is represented by maximum PWM resolution (bits) for a given PWM CCPR1L:CCP1CON<5:4>. The PWM duty cycle is frequency is given by the equation: calculated by the equation: EQUATION 18-3: EQUATION 18-2: PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) • log(FOSC) TOSC • (TMR2 Prescale Value) PWM Resolution (max) = FPWM bits log(2) CCPR1L and CCP1CON<5:4> can be written to at any time but the duty cycle value is not copied into CCPR1H until a match between PR2 and TMR2 occurs Note: If the PWM duty cycle value is longer than (i.e., the period is complete). In PWM mode, CCPR1H the PWM period, the ECCP1 pin will not is a read-only register. be cleared. TABLE 18-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 © 2008 Microchip Technology Inc. DS39646C-page 193

PIC18F8722 FAMILY 18.4.3 PWM OUTPUT CONFIGURATIONS The Single Output mode is the standard PWM mode discussed in Section18.4 “Enhanced PWM Mode”. The P1M1:P1M0 bits in the CCP1CON register allow The Half-Bridge and Full-Bridge Output modes are one of four configurations: covered in detail in the sections that follow. • Single Output The general relationship of the outputs in all • Half-Bridge Output configurations is summarized in Figure18-2. • Full-Bridge Output, Forward mode • Full-Bridge Output, Reverse mode FIGURE 18-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) 0 Duty PR2 + 1 CCP1CON<7:6> SIGNAL Cycle Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (ECCP1DEL<6:0>) Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section18.4.6 “Programmable Dead-Band Delay”). DS39646C-page 194 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 18-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) 0 Duty PR2 + 1 CCP1CON<7:6> SIGNAL Cycle Period 00 (Single Output) P1A Modulated P1A Modulated Delay(1) Delay(1) 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (ECCP1DEL<6:0>) Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section18.4.6 “Programmable Dead-Band Delay”). © 2008 Microchip Technology Inc. DS39646C-page 195

PIC18F8722 FAMILY 18.4.4 HALF-BRIDGE MODE The P1A and P1B outputs are multiplexed with the PORTC<2> and PORTE<6> data latches. Alternatively, In the Half-Bridge Output mode, two pins are used as P1B can be assigned to PORTH<7> by programming outputs to drive push-pull loads. The PWM output sig- the ECCPMX Configuration bit to ‘0’. See Table18-1, nal is output on the P1A pin, while the complementary Table18-2 and Table18-3 for more information. The PWM output signal is output on the P1B pin associated TRIS bit must be cleared to configure P1A (Figure18-4). This mode can be used for half-bridge and P1B as outputs. applications, as shown in Figure18-5, or for full-bridge applications, where four power switches are being FIGURE 18-4: HALF-BRIDGE PWM modulated with two PWM signals. OUTPUT In Half-Bridge Output mode, the programmable Period Period dead-band delay can be used to prevent shoot-through current in half-bridge power devices. The value of bits, Duty Cycle P1DC<6:0> sets the number of instruction cycles P1A(2) before the output is driven active. If the value is greater td than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section18.4.6 td “Programmable Dead-Band Delay” for more details P1B(2) on dead-band delay operations. (1) (1) (1) td = Dead Band Delay Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. FIGURE 18-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) V+ PIC18F6X27/6X22/8X27/8X22 FET Driver + P1A V - Load FET Driver + P1B V - V- Half-Bridge Output Driving a Full-Bridge Circuit V+ PIC18F6X27/6X22/8X27/8X22 FET FET Driver Driver P1A Load FET FET Driver Driver P1B V- DS39646C-page 196 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 18.4.5 FULL-BRIDGE MODE P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2>, PORTE<6:5> and PORTG<4> data In Full-Bridge Output mode, four pins are used as latches. Alternatively, P1B and P1C can be assigned to outputs; however, only two outputs are active at a time. PORTH<7> and PORTH<6>, respectively, by program- In the Forward mode, pin P1A is continuously active ming the ECCPMX Configuration bit to ‘0’. See and pin P1D is modulated. In the Reverse mode, pin Table18-1, Table18-2 and Table18-3 for more infor- P1C is continuously active and pin P1B is modulated. mation. The associated bits must be cleared to make These are illustrated in Figure18-6. the P1A, P1B, P1C and P1D pins outputs. FIGURE 18-6: FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A(2) Duty Cycle P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Duty Cycle P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2008 Microchip Technology Inc. DS39646C-page 197

PIC18F8722 FAMILY FIGURE 18-7: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18F6X27/6X22/8X27/8X22 FET QA QC FET Driver Driver P1A Load P1B FET FET Driver Driver P1C QB QD V- P1D 18.4.5.1 Direction Change in Full-Bridge Mode Figure18-9 shows an example where the PWM direc- tion changes from forward to reverse at a near 100% In the Full-Bridge Output mode, the P1M1 bit in the duty cycle. At time, t1, the outputs P1A and P1D CCP1CON register allows users to control the forward/ become inactive, while output P1C becomes active. In reverse direction. When the application firmware this example, since the turn-off time of the power changes this direction control bit, the module will devices is longer than the turn-on time, a shoot-through assume the new direction on the next PWM cycle. current may flow through power devices QC and QD Just before the end of the current PWM period, the (see Figure18-7) for the duration of ‘t’. The same modulated outputs (P1B and P1D) are placed in their phenomenon will occur to power devices QA and QB inactive state, while the unmodulated outputs (P1A and for PWM direction change from reverse to forward. P1C) are switched to drive in the opposite direction. If changing PWM direction at high duty cycle is required This occurs in a time interval of (4 TOSC * (Timer2 for an application, one of the following requirements Prescale Value)) before the next PWM period begins. must be met: The Timer2 prescaler will be either 1, 4 or 16, depend- ing on the value of the T2CKPSx bit (T2CON<1:0>). 1. Reduce PWM for a PWM period before During the interval from the switch of the unmodulated changing directions. outputs to the beginning of the next period, the 2. Use switch drivers that can drive the switches off modulated outputs (P1B and P1D) remain inactive. faster than they can drive them on. This relationship is shown in Figure18-8. Other options to prevent shoot-through current may Note that in the Full-Bridge Output mode, the ECCP1 exist. module does not provide any dead-band delay. In gen- eral, since only one output is modulated at all times, dead-band delay is not required. However, there is a situation where a dead-band delay might be required. This situation occurs when both of the following conditions are true: 1. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. 2. The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. DS39646C-page 198 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 18-8: PWM DIRECTION CHANGE Period(1) Period SIGNAL P1A (Active-High) P1B (Active-High) DC P1C (Active-High) (Note 2) P1D (Active-High) DC Note 1: The direction bit in the ECCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals are inactive at this time. FIGURE 18-9: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE(1) Forward Period t1 Reverse Period P1A P1B DC P1C P1D DC t (2) ON External Switch C t (3) OFF External Switch D Potential t = t – t OFF ON Shoot-Through Current Note 1: All signals are shown as active-high. 2: t is the turn-on delay of power switch QC and its driver. ON 3: t is the turn-off delay of power switch QD and its driver. OFF © 2008 Microchip Technology Inc. DS39646C-page 199

PIC18F8722 FAMILY 18.4.6 PROGRAMMABLE DEAD-BAND A shutdown event can be caused by either of the two DELAY comparator modules or the FLT0 pin (or any combina- tion of these three sources). The comparators may be In half-bridge applications where all power switches are used to monitor a voltage input proportional to a current modulated at the PWM frequency at all times, the being monitored in the bridge circuit. If the voltage power switches normally require more time to turn off exceeds a threshold, the comparator switches state and than to turn on. If both the upper and lower power triggers a shutdown. Alternatively, a digital signal on the switches are switched at the same time (one turned on FLT0 pin can also trigger a shutdown. The and the other turned off), both switches may be on for auto-shutdown feature can be disabled by not selecting a short period of time until one switch completely turns any auto-shutdown sources. The auto-shutdown off. During this brief interval, a very high current sources to be used are selected using the (shoot-through current) may flow through both power ECCP1AS<2:0> bits (ECCP1AS<6:4>). switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flow- When a shutdown occurs, the output pins are ing during switching, turning on either of the power asynchronously placed in their shutdown states, switches is normally delayed to allow the other switch specified by the PSS1AC<1:0> and PSS1BD<1:0> bits to completely turn off. (ECCP1AS<3:0>). Each pin pair (P1A/P1C and P1B/ P1D) may be set to drive high, drive low or be tri-stated In the Half-Bridge Output mode, a digitally program- (not driving). The ECCP1ASE bit (ECCP1AS<7>) is mable dead-band delay is available to avoid also set to hold the Enhanced PWM outputs in their shoot-through current from destroying the bridge shutdown states. power switches. The delay occurs at the signal transi- tion from the non-active state to the active state. See The ECCP1ASE bit is set by hardware when a shut- Figure18-4 for illustration. The lower seven bits of the down event occurs. If automatic restarts are not ECCP1DEL register (Register18-2) set the delay enabled, the ECCP1ASE bit is cleared by firmware period in terms of microcontroller instruction cycles when the cause of the shutdown clears. If automatic (TCY or 4 TOSC). restarts are enabled, the ECCP1ASE bit is auto- matically cleared when the cause of the auto-shutdown 18.4.7 ENHANCED PWM has cleared. AUTO-SHUTDOWN If the ECCP1ASE bit is set when a PWM period begins, When the ECCP is programmed for any of the the PWM outputs remain in their shutdown state for that Enhanced PWM modes, the active output pins may be entire PWM period. When the ECCP1ASE bit is cleared, configured for auto-shutdown. Auto-shutdown immedi- the PWM outputs will return to normal operation at the ately places the Enhanced PWM output pins into a beginning of the next PWM period. defined shutdown state when a shutdown event Note: Writing to the ECCP1ASE bit is disabled occurs. while a shutdown condition is active. REGISTER 18-2: ECCPxDEL: ENHANCED PWM DEAD-BAND DELAY REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxRSEN PxDC6 PxDC5 PxDC4 PxDC3 PxDC2 PxDC1 PxDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPxASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, the ECCPxASE bit must be cleared in software to restart the PWM bit 6-0 PxDC<6:0>: PWM Delay Count bits Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for a PWM signal to transition to active. DS39646C-page 200 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY REGISTER 18-3: ECCPxAS: ENHANCED CCP AUTO-SHUTDOWN CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPxASE ECCPxAS2 ECCPxAS1 ECCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCPxASE: ECCP Auto-Shutdown Event Status bit 0 = ECCP outputs are operating 1 = A shutdown event has occurred; ECCP outputs are in shutdown state bit 6-4 ECCPxAS<2:0>: ECCP Auto-Shutdown Source Select bits 000 = Auto-shutdown is disabled 001 = Comparator 1 output 010 = Comparator 2 output 011 = Either Comparator 1 or 2 100 = FLT0 101 = FLT0 or Comparator 1 110 = FLT0 or Comparator 2 111 = FLT0 or Comparator 1 or Comparator 2 bit 3-2 PSSxAC<1:0>: Pins A and C Shutdown State Control bits 00 = Drive pins A and C to ‘0’ 01 = Drive pins A and C to ‘1’ 1x = Pins A and C tri-state bit 1-0 PSSxBD<1:0>: Pins B and D Shutdown State Control bits 00 = Drive pins B and D to ‘0’ 01 = Drive pins B and D to ‘1’ 1x = Pins B and D tri-state © 2008 Microchip Technology Inc. DS39646C-page 201

PIC18F8722 FAMILY 18.4.7.1 Auto-Shutdown and Automatic 18.4.8 START-UP CONSIDERATIONS Restart When the ECCP module is used in the PWM mode, the The Auto-Shutdown feature can be configured to allow application hardware must use the proper external automatic restarts of the module following a shutdown pull-up and/or pull-down resistors on the PWM output event. This is enabled by setting the P1RSEN bit of the pins. When the microcontroller is released from Reset, ECCP1DEL register (ECCP1DEL<7>). all of the I/O pins are in the high-impedance state. The external circuits must keep the power switch devices in In Shutdown mode with P1RSEN = 1 (Figure18-10), the OFF state until the microcontroller drives the I/O the ECCP1ASE bit will remain set for as long as the pins with the proper signal levels or activates the PWM cause of the shutdown continues. When the shutdown output(s). condition clears, the ECCP1ASE bit is cleared. If P1RSEN =0 (Figure18-11), once a shutdown condi- The CCP1M<1:0> bits (CCP1CON<1:0>) allow the tion occurs, the ECCP1ASE bit will remain set until it is user to choose whether the PWM output signals are cleared by firmware. Once ECCP1ASE is cleared, the active-high or active-low for each pair of PWM output Enhanced PWM will resume at the beginning of the pins (P1A/P1C and P1B/P1D). The PWM output next PWM period. polarities must be selected before the PWM pins are configured as outputs. Changing the polarity configura- Note: Writing to the ECCP1ASE bit is disabled tion while the PWM pins are configured as outputs is while a shutdown condition is active. not recommended since it may result in damage to the Independent of the P1RSEN bit setting, if the application circuits. auto-shutdown source is one of the comparators, the The P1A, P1B, P1C and P1D output latches may not be shutdown condition is a level. The ECCP1ASE bit can- in the proper states when the PWM module is initialized. not be cleared as long as the cause of the shutdown Enabling the PWM pins for output at the same time as persists. the ECCP1 module may cause damage to the applica- The Auto-Shutdown mode can be forced by writing a ‘1’ tion circuit. The ECCP1 module must be enabled in the to the ECCP1ASE bit. proper output mode and complete a full PWM cycle before configuring the PWM pins as outputs. The com- pletion of a full PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. FIGURE 18-10: PWM AUTO-SHUTDOWN (P1RSEN = 1, AUTO-RESTART ENABLED) PWM Period ShutdownEvent ECCP1ASE bit PWM Activity Normal PWM Start of Shutdown Shutdown PWM PWM Period Event Occurs Event Clears Resumes FIGURE 18-11: PWM AUTO-SHUTDOWN (P1RSEN = 0, AUTO-RESTART DISABLED) PWM Period ShutdownEvent ECCP1ASE bit PWM Activity Normal PWM ECCP1ASE Cleared by Start of Shutdown Shutdown Firmware PWM PWM Period Event Occurs Event Clears Resumes DS39646C-page 202 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 18.4.9 SETUP FOR PWM OPERATION 18.4.10 OPERATION IN POWER-MANAGED MODES The following steps should be taken when configuring the ECCP1 module for PWM operation using Timer2: In Sleep mode, all clock sources are disabled. Timer2 or 1. Configure the PWM pins, P1A and P1B (and Timer4 will not increment and the state of the module will P1C and P1D, if used), as inputs by setting the not change. If the ECCP1 pin is driving a value, it will corresponding TRIS bits. continue to drive that value. When the device wakes up, 2. Set the PWM period by loading the PR2 register. it will continue from this state. If Two-Speed Start-ups are enabled, the initial start-up frequency from INTOSC and 3. If auto-shutdown is required do the following: the postscaler may not be stable immediately. • Disable auto-shutdown (ECCP1AS = 0) In PRI_IDLE mode, the primary clock will continue to • Configure source (FLT0, Comparator 1 or clock the ECCP1 module without change. In all other Comparator 2) power-managed modes, the selected power-managed • Wait for non-shutdown condition mode clock will clock Timer2 or Timer4. Other 4. Configure the ECCP1 module for the desired power-managed mode clocks will most likely be PWM mode and configuration by loading the different than the primary clock frequency. CCP1CON register with the appropriate values: • Select one of the available output 18.4.10.1 Operation with Fail-Safe configurations and direction with the Clock Monitor P1M<1:0> bits. If the Fail-Safe Clock Monitor is enabled, a clock failure • Select the polarities of the PWM output will force the device into the power-managed RC_RUN signals with the CCP1M<3:0> bits. mode and the OSCFIF bit (PIR2<7>) will be set. The 5. Set the PWM duty cycle by loading the CCPR1L ECCP1 will then be clocked from the internal oscillator register and CCP1CON<5:4> bits. clock source, which may have a different clock 6. For Half-Bridge Output mode, set the frequency than the primary clock. dead-band delay by loading ECCP1DEL<6:0> See the previous section for additional details. with the appropriate value. 7. If auto-shutdown operation is required, load the 18.4.11 EFFECTS OF A RESET ECCP1AS register: Both Power-on Reset and subsequent Resets will force • Select the auto-shutdown sources using the all ports to Input mode and the CCP registers to their ECCP1AS<2:0> bits. Reset states. • Select the shutdown states of the PWM This forces the Enhanced CCP module to reset to a output pins using the PSS1AC<1:0> and state compatible with the standard CCP module. PSS1BD<1:0> bits. • Set the ECCP1ASE bit (ECCP1AS<7>). • Configure the comparators using the CMCON register. • Configure the comparator inputs as analog inputs. 8. If auto-restart operation is required, set the P1RSEN bit (ECCP1DEL<7>). 9. Configure and start TMR2: • Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit (PIR1<1>). • Set the TMR2 prescale value by loading the T2CKPS bits (T2CON<1:0>). • Enable Timer2 by setting the TMR2ON bit (T2CON<2>). 10. Enable PWM outputs after a new PWM cycle has started: • Wait until TMRx overflows (TMRxIF bit is set). • Enable the ECCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCP1ASE bit (ECCP1AS<7>). © 2008 Microchip Technology Inc. DS39646C-page 203

PIC18F8722 FAMILY TABLE 18-5: REGISTERS ASSOCIATED WITH ECCP MODULES AND TIMER1 TO TIMER4 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 RCON IPEN SBOREN — RI TO PD POR BOR 58 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 PIR2 OSCFIF CMIF — EEIF BCL1IF HLVDIF TMR3IF CCP2IF 60 PIE2 OSCFIE CMIE — EEIE BCL1IE HLVDIE TMR3IE CCP2IE 60 IPR2 OSCFIP CMIP — EEIP BCL1IP HLVDIP TMR3IP CCP2IP 60 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 60 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 60 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 60 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 60 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 60 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60 TRISH(2) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 60 TMR1L Timer1 Register Low Byte 58 TMR1H Timer1 Register High Byte 58 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 58 TMR2 Timer2 Register 58 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 58 PR2 Timer2 Period Register 58 TMR3L Timer3 Register Low Byte 59 TMR3H Timer3 Register High Byte 59 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 59 TMR4 Timer4 Register 61 T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 61 PR4 Timer4 Period Register 61 CCPRxL(1) Enhanced Capture/Compare/PWM Register x Low Byte 59, 61 CCPRxH(1) Enhanced Capture/Compare/PWM Register x High Byte 59, 61 CCPxCON(1) PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 59 ECCPxAS(1) ECCPxASE ECCPxAS2 ECCPxAS1 ECCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0 59, 61 ECCPxDEL(1) PxRSEN PxDC6 PxDC5 PxDC4 PxDC3 PxDC2 PxDC1 PxDC0 61 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation. Note 1: Generic term for all of the identical registers of this name for all Enhanced CCP modules, where ‘x’ identifies the individual module (ECCP1, ECCP2 or ECCP3). Bit assignments and Reset values for all registers of the same generic name are identical. 2: This register is not implemented on PIC18F6527/6622/6627/6722 devices. DS39646C-page 204 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 19.0 MASTER SYNCHRONOUS 19.3 SPI Mode SERIAL PORT (MSSP) The SPI mode allows 8 bits of data to be synchronously MODULE transmitted and received simultaneously. All four modes of SPI are supported. To accomplish 19.1 Master SSP (MSSP) Module communication, typically three pins are used: Overview • Serial Data Out (SDOx) – RC5/SDO1 or RD4/SDO2 The Master Synchronous Serial Port (MSSP) module is • Serial Data In (SDIx) – RC4/SDI1/SDA1 or a serial interface, useful for communicating with other RD5/SDI2/SDA2 peripheral or microcontroller devices. These peripheral • Serial Clock (SCKx) – RC3/SCK1/SCL1 or devices may be serial EEPROMs, shift registers, RD6/SCK2/SCL2 display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: Additionally, a fourth pin may be used when in a Slave mode of operation: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C™) • Slave Select (SSx) – RF7/SS1 or RD7/SS2 - Full Master mode Figure19-1 shows the block diagram of the MSSP - Slave mode (with general address call) module when operating in SPI mode. The I2C interface supports the following modes in FIGURE 19-1: MSSP BLOCK DIAGRAM hardware: (SPIMODE) • Master mode • Multi-Master mode Internal Data Bus • Slave mode Read Write All members of the PIC18F8722 family have two MSSP modules, designated as MSSP1 and MSSP2. Each SSPxBUF reg module operates independently of the other. Note: Throughout this section, generic refer- ences to an MSSP module in any of its RC4 or RD5 operating modes may be interpreted as SSPxSR reg being equally applicable to MSSP1 or RC5 or RD4 bit 0 Shift MSSP2. Register names and module I/O Clock signals use the generic designator ‘x’ to indicate the use of a numeral to distinguish a particular module when required. Control bit names are not individuated. RF7 or RD7 SSxControl Enable 19.2 Control Registers Edge Each MSSP module has three associated control regis- Select ters. These include a status register (SSPxSTAT) and two control registers (SSPxCON1 and SSPxCON2). The 2 use of these registers and their individual Configuration Clock Select bits differ significantly depending on whether the MSSP SSPM<3:0> module is operated in SPI or I2C mode. SMP:CKE ( ) 4 TMR2 Output Additional details are provided under the individual RC3 or RD6 2 2 sections. Edge Select Prescaler TOSC Note: In devices with more than one MSSP 4, 16, 64 module, it is very important to pay close attention to SSPCON register names. Data to TXx/RXx in SSPxSR SSP1CON1 and SSP1CON2 control TRIS bit different operational aspects of the same Note: Only port I/O names are used in this diagram for module, while SSP1CON1 and the sake of brevity. Refer to the text for a full list of SSP2CON1 control the same features for multiplexed functions. two different modules. © 2008 Microchip Technology Inc. DS39646C-page 205

PIC18F8722 FAMILY 19.3.1 REGISTERS SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data Each MSSP module has four registers for SPI mode bytes are written to or read from. operation. These are: In receive operations, SSPxSR and SSPxBUF • MSSP Control Register 1 (SSPxCON1) together create a double-buffered receiver. When • MSSP Status Register (SSPxSTAT) SSPxSR receives a complete byte, it is transferred to • Serial Receive/Transmit Buffer Register SSPxBUF and the SSPxIF interrupt is set. (SSPxBUF) During transmission, the SSPxBUF is not • MSSP Shift Register (SSPxSR) – Not directly double-buffered. A write to SSPxBUF will write to both accessible SSPxBUF and SSPxSR. SSPxCON1 and SSPxSTAT are the control and status registers in SPI mode operation. The SSPxCON1 register is readable and writable. The lower 6 bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. REGISTER 19-1: SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Select bit 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state Note: Polarity of clock state is set by the CKP bit (SSPxCON1<4>). bit 5 D/A: Data/Address bit Used in I2C mode only. bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write Information bit Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty DS39646C-page 206 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY REGISTER 19-2: SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) SPI Slave mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in soft- ware). 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit(2) 1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits(3) 0101 = SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin 0100 = SPI Slave mode, clock = SCKx pin, SSx pin control enabled 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only. © 2008 Microchip Technology Inc. DS39646C-page 207

PIC18F8722 FAMILY 19.3.2 OPERATION before reading the data that was just received. Any write to the SSPxBUF register during transmis- When initializing the SPI, several options need to be sion/reception of data will be ignored and the Write specified. This is done by programming the appropriate Collision Detect bit, WCOL (SSPxCON1<7>), will be control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). set. User software must clear the WCOL bit so that it These control bits allow the following to be specified: can be determined if the following write(s) to the • Master mode (SCKx is the clock output) SSPxBUF register completed successfully. • Slave mode (SCKx is the clock input) When the application software is expecting to receive • Clock Polarity (Idle state of SCKx) valid data, the SSPxBUF should be read before the • Data Input Sample Phase (middle or end of data next byte of data to transfer is written to the SSPxBUF. output time) The Buffer Full bit, BF (SSPxSTAT<0>), indicates when • Clock Edge (output data on rising/falling edge of SSPxBUF has been loaded with the received data SCKx) (transmission is complete). When the SSPxBUF is • Clock Rate (Master mode only) read, the BF bit is cleared. This data may be irrelevant • Slave Select mode (Slave mode only) if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmis- Each MSSP module consists of a transmit/receive shift sion/reception has completed. If the interrupt method is register (SSPxSR) and a buffer register (SSPxBUF). not going to be used, then software polling can be done The SSPxSR shifts the data in and out of the device, to ensure that a write collision does not occur. MSb first. The SSPxBUF holds the data that was Example19-1 shows the loading of the SSPxBUF written to the SSPxSR until the received data is ready. (SSPxSR) for data transmission. Once the 8 bits of data have been received, that byte is moved to the SSPxBUF register. Then, the Buffer Full The SSPxSR is not directly readable or writable and detect bit, BF (SSPxSTAT<0>) and the interrupt flag bit, can only be accessed by addressing the SSPxBUF SSPxIF, are set. This double-buffering of the received register. Additionally, the SSPxSTAT register indicates data (SSPxBUF) allows the next byte to start reception the various status conditions. EXAMPLE 19-1: LOADING THE SSP1BUF (SSP1SR) REGISTER LOOP BTFSS SSP1STAT, BF ;Has data been received (transmit complete)? BRA LOOP ;No MOVF SSP1BUF, W ;WREG reg = contents of SSP1BUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSP1BUF ;New data to xmit DS39646C-page 208 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 19.3.3 ENABLING SPI I/O Any serial port function that is not desired may be overridden by programming the corresponding data To enable the serial port, SSP Enable bit, SSPEN direction (TRIS) register to the opposite value. (SSPxCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the 19.3.4 TYPICAL CONNECTION SSPxCON registers and then set the SSPEN bit. This configures the SDIx, SDOx, SCKx and SSx pins as Figure19-2 shows a typical connection between two serial port pins. For the pins to behave as the serial port microcontrollers. The master controller (Processor 1) function, some must have their data direction bits (in initiates the data transfer by sending the SCKx signal. the TRIS register) appropriately programmed as Data is shifted out of both shift registers on their pro- follows: grammed clock edge and latched on the opposite edge of the clock. Both processors should be programmed to • SDIx is automatically controlled by the the same Clock Polarity (CKP), then both controllers SPI module would send and receive data at the same time. • SDOx must have the TRISC<5> or TRISD<4> bit Whether the data is meaningful (or dummy data) cleared depends on the application software. This leads to • SCKx (Master mode) must have the TRISC<3> or three scenarios for data transmission: TRISD<6>bit cleared • Master sends data – Slave sends dummy data • SCKx (Slave mode) must have the TRISC<3> or • Master sends data – Slave sends data TRISD<6> bit set • Master sends dummy data – Slave sends data • SSx must have the TRISF<7> or TRISD<7> bit set FIGURE 19-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xxb SPI Slave SSPM<3:0> = 010xb SDOx SDIx Serial Input Buffer Serial Input Buffer (SSPxBUF) (SSPxBUF) SDIx SDOx Shift Register Shift Register (SSPxSR) (SSPxSR) MSb LSb MSb LSb Serial Clock SCKx SCKx PROCESSOR 1 PROCESSOR 2 © 2008 Microchip Technology Inc. DS39646C-page 209

PIC18F8722 FAMILY 19.3.5 MASTER MODE shown in Figure19-3, Figure19-5 and Figure19-6, where the MSB is transmitted first. In Master mode, the The master can initiate the data transfer at any time SPI clock rate (bit rate) is user programmable to be one because it controls the SCKx. The master determines of the following: when the slave (Processor 1, Figure19-2) is to broadcast data by the software protocol. • FOSC/4 (or TCY) In Master mode, the data is transmitted/received as • FOSC/16 (or 4 • TCY) soon as the SSPxBUF register is written to. If the SPI • FOSC/64 (or 16 • TCY) is only going to receive, the SDOx output could be dis- • Timer2 output/2 abled (programmed as an input). The SSPxSR register This allows a maximum data rate (at 40MHz) of will continue to shift in the signal present on the SDIx 10.00Mbps. pin at the programmed clock rate. As each byte is Figure19-3 shows the waveforms for Master mode. received, it will be loaded into the SSPxBUF register as When the CKE bit is set, the SDOx data is valid before if a normal received byte (interrupts and status bits there is a clock edge on SCKx. The change of the input appropriately set). This could be useful in receiver sample is shown based on the state of the SMP bit. The applications as a “Line Activity Monitor” mode. time when the SSPxBUF is loaded with the received The clock polarity is selected by appropriately data is shown. programming the CKP bit (SSPxCON1<4>). This then, would give waveforms for SPI communication as FIGURE 19-3: SPI MODE WAVEFORM (MASTER MODE) Write to SSPxBUF SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) 4 Clock Modes SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDIx (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDIx (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPxIF Next Q4 Cycle SSPxSR to after Q2↓ SSPxBUF DS39646C-page 210 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 19.3.6 SLAVE MODE transmitted byte and becomes a floating output. Exter- nal pull-up/pull-down resistors may be desirable In Slave mode, the data is transmitted and received as depending on the application. the external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. Note1: When the SPI is in Slave mode While in Slave mode, the external clock is supplied by with SSx pin control enabled the external clock source on the SCKx pin. This exter- (SSPxCON1<3:0>=0100), the SPI nal clock must meet the minimum high and low times module will reset if the SSx pin is set to VDD. as specified in the electrical specifications. 2: If the SPI is used in Slave mode with CKE While in Sleep mode, the slave can transmit/receive set, then the SSx pin control must be data. When a byte is received, the device can be enabled. configured to wake-up from Sleep. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SSx pin to 19.3.7 SLAVE SELECT a high level or clearing the SSPEN bit. SYNCHRONIZATION To emulate two-wire communication, the SDOx pin can The SSx pin allows a Synchronous Slave mode. The be connected to the SDIx pin. When the SPI needs to SPI must be in Slave mode with the SSx pin control operate as a receiver, the SDOx pin can be configured enabled (SSPxCON1<3:0> = 04h). When the SSx pin as an input. This disables transmissions from the is low, transmission and reception are enabled and the SDOx. The SDIx can always be left as an input (SDI SDOx pin is driven. When the SSx pin goes high, the function) since it cannot create a bus conflict. SDOx pin is no longer driven, even if in the middle of a FIGURE 19-4: SLAVE SYNCHRONIZATION WAVEFORM SSx SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx bit 7 bit 6 bit 7 bit 0 SDIx bit 0 (SMP = 0) bit 7 bit 7 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle SSPxSR to after Q2↓ SSPxBUF © 2008 Microchip Technology Inc. DS39646C-page 211

PIC18F8722 FAMILY FIGURE 19-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle SSPxSR to after Q2↓ SSPxBUF FIGURE 19-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle after Q2↓ SSPxSR to SSPxBUF DS39646C-page 212 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 19.3.8 OPERATION IN POWER-MANAGED 19.3.10 BUS MODE COMPATIBILITY MODES Table19-1 shows the compatibility between the In SPI Master mode, module clocks may be operating standard SPI modes and the states of the CKP and at a different speed than when in full power mode; in CKE control bits. the case of the Sleep mode, all clocks are halted. TABLE 19-1: SPI BUS MODES In Idle modes, a clock is provided to the peripherals. That clock can be from the primary clock source, the Control Bits State Standard SPI Mode secondary clock (Timer1 oscillator) or the INTOSC Terminology CKP CKE source. See Section2.7 “Clock Sources and Oscillator Switching” for additional information. 0, 0 0 1 In most cases, the speed that the master clocks SPI 0, 1 0 0 data is not important; however, this should be 1, 0 1 1 evaluated for each system. 1, 1 1 0 If MSSP interrupts are enabled, they can wake the con- There is also an SMP bit which controls when the data troller from Sleep mode, or one of the Idle modes, when is sampled. the master completes sending data. If an exit from Sleep or Idle mode is not desired, MSSP interrupts 19.3.11 SPI CLOCK SPEED AND MODULE should be disabled. INTERACTIONS If the Sleep mode is selected, all module clocks are Because MSSP1 and MSSP2 are independent halted and the transmission/reception will remain in modules, they can operate simultaneously at different that state until the devices wakes. After the device data rates. Setting the SSPM3:SSPM0 bits of the returns to Run mode, the module will resume SSPxCON register determines the rate for the transmitting and receiving data. corresponding module. In SPI Slave mode, the SPI Transmit/Receive Shift An exception is when both modules use Timer2 as a register operates asynchronously to the device. This time base in Master mode. In this instance, any allows the device to be placed in any power-managed changes to the Timer2 module’s operation will affect mode and data to be shifted into the SPI Trans- both MSSP modules equally. If different bit rates are mit/Receive Shift register. When all 8 bits have been required for each module, the user should select one of received, the MSSP interrupt flag bit will be set and if the other three time base options for one of the enabled, will wake the device. modules. 19.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. © 2008 Microchip Technology Inc. DS39646C-page 213

PIC18F8722 FAMILY TABLE 19-2: REGISTERS ASSOCIATED WITH SPI OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 60 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 60 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 60 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 60 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 60 TMR2 Timer2 Register 58 PR2 Timer2 Period Register 58 SSP1BUF MSSP1 Receive Buffer/Transmit Register 58 SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 58 SSP1STAT SMP CKE D/A P S R/W UA BF 58 SSP2BUF MSSP2 Receive Buffer/Transmit Register 61 SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 61 SSP2STAT SMP CKE D/A P S R/W UA BF 61 Legend: Shaded cells are not used by the MSSP module in SPI mode. DS39646C-page 214 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 19.4 I2C Mode FIGURE 19-7: MSSP BLOCK DIAGRAM (I2C™ MODE) The MSSP module in I2C mode fully implements all master and slave functions (including general call Internal support) and provides interrupts on Start and Stop bits Data Bus in hardware to determine a free bus (multi-master Read Write function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit RC3 or SSPxBUF reg addressing. RD6 Two pins are used for data transfer: Shift • Serial clock (SCLx) – RC3/SCK1/SCL1 or Clock RD6/SCK2/SCL2 SSPxSR reg • Serial data (SDAx) – RC4/SDI1/SDA1 or RC4 or MSb LSb RD5 RD5/SDI2/SDA2 The user must configure these pins as inputs by setting Match Detect Addr Match the associated TRIS bits. SSPxADD reg Start and Set, Reset Stop bit Detect S, P bits (SSPxSTAT reg) Note: Only port I/O names are used in this diagram for the sake of brevity. Refer to the text for a full list of multiplexed functions. © 2008 Microchip Technology Inc. DS39646C-page 215

PIC18F8722 FAMILY REGISTER 19-3: SSPxSTAT: MSSPx STATUS REGISTER (I2C™ MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P(1) S(1) R/W(2,3) UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit(1) 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last bit 3 S: Start bit(1) 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last bit 2 R/W: Read/Write Information bit(2,3) In Slave mode: 1 = Read 0 = Write In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress bit 1 UA: Update Address bit (10-bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = SSPxBUF is full 0 = SSPxBUF is empty In Receive mode: 1 = SSPxBUF is full (does not include the ACK and Stop bits) 0 = SSPxBUF is empty (does not include the ACK and Stop bits) Note 1: This bit is cleared on Reset and when SSPEN is cleared. 2: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode. DS39646C-page 216 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY REGISTER 19-4: SSPxCON1: MSSPx CONTROL REGISTER 1 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN(1) CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPxBUF register was attempted while the I2C™ conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a “don’t care” bit. bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a “don’t care” bit in Transmit mode. bit 5 SSPEN: Synchronous Serial Port Enable bit(1) 1 = Enables the serial port and configures the SDAx and SCLx pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: SCKx Release Control bit In Slave mode: 1 = Release clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode. bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (Slave Idle) 1000 = I2C Master mode, clock = FOSC/(4 * (SSPxADD + 1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. Note 1: When enabled, the SDAx and SCLx pins must be configured as input. © 2008 Microchip Technology Inc. DS39646C-page 217

PIC18F8722 FAMILY REGISTER 19-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPxSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(1) 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)(2) 1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (Master mode only)(2) 1 = Enables Receive mode for I2C 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit (Master mode only)(2) 1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit (Master mode only)(2) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable/Stretch Enable bit(2) In Master mode: 1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. 2: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C™ module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). DS39646C-page 218 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 19.4.2 OPERATION 19.4.3.1 Addressing The MSSP module functions are enabled by setting Once the MSSP module has been enabled, it waits for MSSP Enable bit, SSPEN (SSPxCON1<5>). a Start condition to occur. Following the Start condition, The SSPxCON1 register allows control of the I2C the 8 bits are shifted into the SSPxSR register. All incoming bits are sampled with the rising edge of the operation. Four mode selection bits (SSPxCON1<3:0>) allow one of the following I2C modes to be selected: clock (SCLx) line. The value of register SSPxSR<7:1> is compared to the value of the SSPxADD register. The • I2C Master mode, clock address is compared on the falling edge of the eighth • I2C Slave mode (7-bit address) clock (SCLx) pulse. If the addresses match and the BF • I2C Slave mode (10-bit address) and SSPOV bits are clear, the following events occur: • I2C Slave mode (7-bit address) with Start and 1. The SSPxSR register value is loaded into the Stop bit interrupts enabled SSPxBUF register. • I2C Slave mode (10-bit address) with Start and 2. The Buffer Full bit, BF, is set. Stop bit interrupts enabled • I2C Firmware Controlled Master mode, slave is 3. An ACK pulse is generated. Idle 4. The MSSP Interrupt Flag bit, SSPxIF, is set (and interrupt is generated, if enabled) on the falling Selection of any I2C mode with the SSPEN bit set edge of the ninth SCLx pulse. forces the SCLx and SDAx pins to be open-drain, provided these pins are programmed as inputs by In 10-Bit Addressing mode, two address bytes need to setting the appropriate TRISC or TRISD bits. To ensure be received by the slave. The five Most Significant bits proper operation of the module, pull-up resistors must (MSbs) of the first address byte specify if this is a 10-bit be provided externally to the SCLx and SDAx pins. address. Bit R/W (SSPxSTAT<2>) must specify a write so the slave device will receive the second address byte. 19.4.3 SLAVE MODE For a 10-bit address, the first byte would equal ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the In Slave mode, the SCLx and SDAx pins must be address. The sequence of events for 10-bit address is as configured as inputs (TRISC<4:3> set). The MSSP follows, with steps 7 through 9 for the slave-transmitter: module will override the input state with the output data when required (slave-transmitter). 1. Receive first (high) byte of address (bits SSPxIF, BF and UA (SSPxSTAT<1>) are set on address The I2C Slave mode hardware will always generate an match). interrupt on an address match. Through the mode 2. Update the SSPxADD register with second (low) select bits, the user can also choose to interrupt on byte of address (clears bit UA and releases the Start and Stop bits SCLx line). When an address is matched, or the data transfer after 3. Read the SSPxBUF register (clears bit BF) and an address match is received, the hardware auto- clear flag bit SSPxIF. matically will generate the Acknowledge (ACK) pulse 4. Receive second (low) byte of address (bits and load the SSPxBUF register with the received value SSPxIF, BF and UA are set). currently in the SSPxSR register. 5. Update the SSPxADD register with the first Any combination of the following conditions will cause (high) byte of address. If match releases SCLx the MSSP module not to give this ACK pulse: line, this will clear bit UA. • The Buffer Full bit, BF (SSPxSTAT<0>), was set 6. Read the SSPxBUF register (clears bit BF) and before the transfer was received. clear flag bit SSPxIF. • The overflow bit, SSPOV (SSPxCON1<6>), was 7. Receive Repeated Start condition. set before the transfer was received. 8. Receive first (high) byte of address (bits SSPxIF In this case, the SSPxSR register value is not loaded and BF are set). into the SSPxBUF, but bit SSPxIF is set. The BF bit is 9. Read the SSPxBUF register (clears bit BF) and cleared by reading the SSPxBUF register, while bit clear flag bit SSPxIF. SSPOV is cleared through software. The SCLx clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101. © 2008 Microchip Technology Inc. DS39646C-page 219

PIC18F8722 FAMILY 19.4.3.2 Reception 19.4.3.3 Transmission When the R/W bit of the address byte is clear and an When the R/W bit of the incoming address byte is set address match occurs, the R/W bit of the SSPxSTAT and an address match occurs, the R/W bit of the register is cleared. The received address is loaded into SSPxSTAT register is set. The received address is the SSPxBUF register and the SDAx line is held low loaded into the SSPxBUF register. The ACK pulse will (ACK). be sent on the ninth bit and pin SCLx is held low regard- less of SEN (see Section19.4.4 “Clock Stretching” When the address byte overflow condition exists, then for more detail). By stretching the clock, the master will the no Acknowledge (ACK) pulse is given. An overflow be unable to assert another clock pulse until the slave condition is defined as either bit BF (SSPxSTAT<0>) is is done preparing the transmit data. The transmit data set, or bit SSPOV (SSPxCON1<6>) is set. must be loaded into the SSPxBUF register which also An MSSP interrupt is generated for each data transfer loads the SSPxSR register. Then pin SCLx should be byte. The interrupt flag bit, SSPxIF, must be cleared in enabled by setting bit, CKP (SSPxCON1<4>). The software. The SSPxSTAT register is used to determine eight data bits are shifted out on the falling edge of the the status of the byte. SCLx input. This ensures that the SDAx signal is valid If SEN is enabled (SSPxCON2<0> = 1), SCLx will be during the SCLx high time (Figure19-9). held low (clock stretch) following each data transfer. The The ACK pulse from the master-receiver is latched on clock must be released by setting bit, CKP the rising edge of the ninth SCLx input pulse. If the (SSPxCON1<4>). See Section19.4.4 “Clock SDAx line is high (not ACK), then the data transfer is Stretching” for more detail. complete. In this case, when the ACK is latched by the slave, the slave logic is reset (resets SSPxSTAT register) and the slave monitors for another occurrence of the Start bit. If the SDAx line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, pin SCLx must be enabled by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared in software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse. DS39646C-page 220 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 2 FIGURE 19-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 D6 2 7 D 1 K C A 9 0 D 8 1 D 7 D2 6 a 3 at D 5 D e eceiving D4 4 n softwarF is read R D6D5 23 Cleared iSSPxBU 7 D 1 0= ACK 9 W 8 R/ A1 7 2 0) A 6 = ddress A3 5 n SEN A e Receiving A5A4 34 set to ‘’ wh0 e SDAxA7A6 SCLx12S SSPxIF (PIR1<3> or PIR3<7>) BF (SSPxSTAT<0>) SSPOV (SSPxCON1<6>) CKP(CKP does not r © 2008 Microchip Technology Inc. DS39646C-page 221

PIC18F8722 FAMILY 2 FIGURE 19-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) P R S K F I AC 9 PxI S D0 8 m S o Data D1 7 Fr Transmitting D5D4D3D2 3456 eared in software UF is written in software et in software D6 2 Cl SSPxB KP is s C D7 1 R S ACK 9 PxIF I S S D0 8 m o Fr D1 7 Transmitting Data D6D5D4D3D2 23456 F Cleared in software SSPxBUF is written in software CKP is set in software D7 1 PxI SCLx held lowwhile CPUresponds to SS K C 0 A 9 = W 8 R/ 1 A 7 ess A2 6 Addr A3 5 g n eivi A4 4 ec R A5 3 >) 7 A6A7 12 Data in sampled > or PIR3< 0>) 3 < < T 1 A R T DAx CLx S SPxIF (PI F (SSPxS KP S S S B C DS39646C-page 222 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 19-10: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 e Byte 3D2 6 softwar a D 5 n ceive Dat D5D4 34 Cleared i e R D6 2 7 D 1 K AC 9 0 D 8 untilDD has Receive Data Byte D6D5D4D3D1D2 234576 Cleared in software Cleared by hardware whenSSPxADD is updated with highbyte of address d low SPxA D7 1 Clock is helupdate of Staken place ACK0 89 A Clock is held low untilupdate of SSPxADD has taken place Receive First Byte of AddressReceive Second Byte of Address0R/W = ACKDAx11110A9A8A7A6A5A4A3A2A1 CLx1234567891234567S SPxIF (PIR1<3> or PIR3<7>) Cleared in softwareCleared in software F (SSPxSTAT<0>) SSPxBUF is written withDummy read of SSPxBUFcontents of SSPxSRto clear BF flag SPOV (SSPxCON1<6>) A (SSPxSTAT<1>) UA is set indicating thatCleared by hardwarethe SSPxADD needs to bewhen SSPxADD is updatedupdatedwith low byte of address UA is set indicating thatSSPxADD needs to beupdated KP00(CKP does not reset to ‘’ when SEN = ) S S S B S U C © 2008 Microchip Technology Inc. DS39646C-page 223

PIC18F8722 FAMILY 2 FIGURE 19-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) Bus masterterminatestransfer ACK D0 89P Completion ofdata transmissionclears BF flag are, holding SCLx low w Clock is held low untilupdate of SSPxADD has Clock is held low untiltaken place1CKP is set to ‘’ 1Receive First Byte of AddressTransmitting Data ByteR/W = ACK11110A8A9D7D6D5D4D3D1D2ACK 91234578961234576Sr Cleared in softwareCleared in software Dummy read of SSPxBUFWrite of SSPxBUFBF flag is clearto clear BF flaginitiates transmitat the end of thethird address sequence Cleared by hardware whenSSPxADD is updated with highbyte of address. CKP is set in software CKP is automatically cleared in hard Clock is held low untilupdate of SSPxADD has taken place 0W = Receive Second Byte of Address A7A6A5A4A3A2A1A0ACK 912345678 Cleared in software Dummy read of SSPxBUFto clear BF flag Cleared by hardware whenSSPxADD is updated with lowbyte of address UA is set indicating thatSSPxADD needs to beupdated R/ 8 h be Receive First Byte of Address DAx11110A9A8 CLx1234567S SPxIF (PIR1<3> or PIR3<7>) F (SSPxSTAT<0>) SSPxBUF is written witcontents of SSPxSR A (SSPxSTAT<1>) UA is set indicating thatthe SSPxADD needs to updated KP (SSPxCON1<4>) S S S B U C DS39646C-page 224 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 19.4.4 CLOCK STRETCHING 19.4.4.3 Clock Stretching for 7-Bit Slave Transmit Mode Both 7-Bit and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The 7-Bit Slave Transmit mode implements clock The SEN bit (SSPxCON2<0>) allows clock stretching stretching by clearing the CKP bit after the falling edge of the ninth clock if the BF bit is clear. This occurs to be enabled during receives. Setting SEN will cause the SCLx pin to be held low at the end of each data regardless of the state of the SEN bit. receive sequence. The user’s ISR must set the CKP bit before transmis- sion is allowed to continue. By holding the SCLx line 19.4.4.1 Clock Stretching for 7-Bit Slave low, the user has time to service the ISR and load the Receive Mode (SEN = 1) contents of the SSPxBUF before the master device In 7-Bit Slave Receive mode, on the falling edge of the can initiate another transmit sequence (see ninth clock at the end of the ACK sequence, if the BF Figure19-9). bit is set, the CKP bit in the SSPxCON1 register is Note1: If the user loads the contents of automatically cleared, forcing the SCLx output to be SSPxBUF, setting the BF bit before the held low. The CKP being cleared to ‘0’ will assert the falling edge of the ninth clock, the CKP bit SCLx line low. The CKP bit must be set in the user’s will not be cleared and clock stretching ISR before reception is allowed to continue. By holding will not occur. the SCLx line low, the user has time to service the ISR 2: The CKP bit can be set in software and read the contents of the SSPxBUF before the regardless of the state of the BF bit. master device can initiate another receive sequence. This will prevent buffer overruns from occurring (see Figure19-13). 19.4.4.4 Clock Stretching for 10-Bit Slave Transmit Mode Note1: If the user reads the contents of the SSPxBUF before the falling edge of the In 10-Bit Slave Transmit mode, clock stretching is ninth clock, thus clearing the BF bit, the controlled during the first two address sequences by CKP bit will not be cleared and clock the state of the UA bit, just as it is in 10-Bit Slave stretching will not occur. Receive mode. The first two addresses are followed by a third address sequence which contains the 2: The CKP bit can be set in software high-order bits of the 10-bit address and the R/W bit regardless of the state of the BF bit. The set to ‘1’. After the third address sequence is user should be careful to clear the BF bit performed, the UA bit is not set, the module is now in the ISR before the next receive configured in Transmit mode and clock stretching is sequence in order to prevent an overflow controlled by the BF flag as in 7-Bit Slave Transmit condition. mode (see Figure19-11). 19.4.4.2 Clock Stretching for 10-Bit Slave Receive Mode (SEN = 1) In 10-Bit Slave Receive mode during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to ‘0’. The release of the clock line occurs upon updating SSPxADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPxADD register before the falling edge of the ninth clock occurs and if the user hasn’t cleared the BF bit by read- ing the SSPxBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. © 2008 Microchip Technology Inc. DS39646C-page 225

PIC18F8722 FAMILY 19.4.4.5 Clock Synchronization and already asserted the SCLx line. The SCLx output will the CKP bit remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCLx. This When the CKP bit is cleared, the SCLx output is forced ensures that a write to the CKP bit will not violate the to ‘0’. However, clearing the CKP bit will not assert the minimum high time requirement for SCLx (see SCLx output low until the SCLx output is already Figure19-12). sampled low. Therefore, the CKP bit will not assert the SCLx line until an external I2C master device has FIGURE 19-12: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDAx DX DX – 1 SCLx Master device CKP asserts clock Master device deasserts clock WR SSPxCON1 DS39646C-page 226 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 2 FIGURE 19-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) w Clock is not held lo1because ACK = ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R D5 3 Clock is held low until1CKP is set to ‘’ ACK D0D7D6 8912 CKPwritten1to ‘’ insoftwareBF is set after falling edge of the 9th clock,0CKP is reset to ‘’ andclock stretching occurs 1 D 7 D2 6 Clock is not held lowbecause buffer full bit is clear prior to falling edge of 9th clock Receiving Data D7D6D5D4D3 12345 Cleared in software SPxBUF is read If BF is clearedprior to the fallingedge of the 9th clock,CKP will not be reset0to ‘’ and no clockstretching will occur S K 9 0 C = A W 8 R/ A1 7 A2 6 s s e ddr A3 5 A g eivin A4 4 c e R A5 3 >) A6 2 R3<7 >) A7 1 > or PI 0>) ON1<6 DAx CLxS SPxIF (PIR1<3 F (SSPxSTAT< SPOV (SSPxC KP S S S B S C © 2008 Microchip Technology Inc. DS39646C-page 227

PIC18F8722 FAMILY FIGURE 19-14: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) Clock is not held low1because ACK = ACK 0 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D 8 1 D 7 e Clock is held low untilupdate of SSPxADD has Clock is held low untiltaken place1CKP is set to ‘’ Receive Data ByteReceive Data Byte ACKD7D6D5D4D3D1D0D2D7D6D5D4D3D2 123457896123456 Cleared in softwareCleared in softwar Dummy read of SSPxBUFto clear BF flag Cleared by hardware whenSSPxADD is updated with highbyte of address after falling edgeof ninth clock 1CKP written to ‘’in software Note:An update of the SSPxADD register beforethe falling edge of the ninth clock will have noeffect on UA and UA will remain set. K C 9 A Clock is held low untilupdate of SSPxADD has taken place Receive First Byte of AddressReceive Second Byte of Address0R/W = DAx11110A9A8A7A6A5A4A3A2A1A0ACK CLx12345678912345678S SPxIF (PIR1<3> or PIR3<7>) Cleared in softwareCleared in software F (SSPxSTAT<0>) SSPxBUF is written withDummy read of SSPxBUFcontents of SSPxSRto clear BF flag SPOV (SSPxCON1<6>) A (SSPxSTAT<1>) UA is set indicating thatCleared by hardware whenthe SSPxADD needs to beSSPxADD is updated with lowupdatedbyte of address after falling edgeof ninth clock UA is set indicating thatSSPxADD needs to beupdated KPNote:An update of the SSPxADDregister before the fallingedge of the ninth clock willhave no effect on UA andUA will remain set. S S S B S U C DS39646C-page 228 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 19.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPxSR is SUPPORT transferred to the SSPxBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK The addressing procedure for the I2C bus is such that bit), the SSPxIF interrupt flag bit is set. the first byte after the Start condition usually determines which device will be the slave addressed by When the interrupt is serviced, the source for the the master. The exception is the general call address interrupt can be checked by reading the contents of the which can address all devices. When this address is SSPxBUF. The value can be used to determine if the used, all devices should, in theory, respond with an address was device specific or a general call address. Acknowledge. In 10-bit mode, the SSPxADD is required to be updated The general call address is one of eight addresses for the second half of the address to match and the UA reserved for specific purposes by the I2C protocol. It bit is set (SSPxSTAT<1>). If the general call address is consists of all ‘0’s with R/W = 0. sampled when the GCEN bit is set, while the slave is configured in 10-Bit Addressing mode, then the second The general call address is recognized when the half of the address is not necessary, the UA bit will not General Call Enable bit, GCEN, is enabled be set and the slave will begin receiving data after the (SSPxCON2<7> set). Following a Start bit detect, 8 bits Acknowledge (Figure19-15). are shifted into the SSPxSR and the address is compared against the SSPxADD. It is also compared to the general call address and fixed in hardware. FIGURE 19-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS MODE) Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK General Call Address SDAx ACK D7 D6 D5 D4 D3 D2 D1 D0 SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPxIF BF (SSPxSTAT<0>) Cleared in software SSPxBUF is read SSPOV (SSPxCON1<6>) ‘0’ GCEN (SSPxCON2<7>) ‘1’ © 2008 Microchip Technology Inc. DS39646C-page 229

PIC18F8722 FAMILY 19.4.6 MASTER MODE Note: The MSSP module, when configured in Master mode is enabled by setting and clearing the I2C Master mode, does not allow queueing appropriate SSPM bits in SSPxCON1 and by setting of events. For instance, the user is not the SSPEN bit. In Master mode, the SCLx and SDAx allowed to initiate a Start condition and lines are manipulated by the MSSP hardware if the immediately write the SSPxBUF register to TRIS bits are set. initiate transmission before the Start condi- tion is complete. In this case, the Master mode of operation is supported by interrupt SSPxBUF will not be written to and the generation on the detection of the Start and Stop con- WCOL bit will be set, indicating that a write ditions. The Stop (P) and Start (S) bits are cleared from to the SSPxBUF did not occur. a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is set, or the The following events will cause the SSP Interrupt Flag bus is Idle, with both the S and P bits clear. bit, SSPxIF, to be set (and SSP interrupt, if enabled): In Firmware Controlled Master mode, user code • Start condition conducts all I2C bus operations based on Start and • Stop condition Stop bit conditions. • Data transfer byte transmitted/received Once Master mode is enabled, the user has six • Acknowledge transmit options. • Repeated Start 1. Assert a Start condition on SDAx and SCLx. 2. Assert a Repeated Start condition on SDAx and SCLx. 3. Write to the SSPxBUF register initiating transmission of data/address. 4. Configure the I2C port to receive data. 5. Generate an Acknowledge condition at the end of a received byte of data. 6. Generate a Stop condition on SDAx and SCLx. 2 FIGURE 19-16: MSSP BLOCK DIAGRAM (I C™ MASTER MODE) Internal SSPM<3:0> Data Bus SSPxADD<6:0> Read Write SSPxBUF Baud Rate Generator SDAx Shift SDAx In Clock ct e SSPxSR Detce) MSb LSb L ur e Oo abl WCk s SCLx Receive En StAarcGtk bneiont,we Srlaetotdepg ebit, Clock Cntl ck Arbitrate/(hold off cloc o Cl Start bit Detect Stop bit Detect SCLx In Write Collision Detect Set/Reset S, P (SSPxSTAT), WCOL (SSPxCON1) Clock Arbitration Set SSPxIF, BCLxIF Bus Collision State Counter for Reset ACKSTAT, PEN (SSPxCON2) end of XMIT/RCV DS39646C-page 230 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 19.4.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock 1. The user generates a Start condition by setting pulses and the Start and Stop conditions. A transfer is the Start Enable bit, SEN (SSPxCON2<0>). ended with a Stop condition or with a Repeated Start 2. SSPxIF is set. The MSSP module will wait the condition. Since the Repeated Start condition is also required start time before any other operation the beginning of the next serial transfer, the I2C bus will takes place. not be released. 3. The user loads the SSPxBUF with the slave In Master Transmitter mode, serial data is output address to transmit. through SDAx, while SCLx outputs the serial clock. The 4. Address is shifted out the SDAx pin until all 8 bits first byte transmitted contains the slave address of the are transmitted. receiving device (7 bits) and the Read/Write (R/W) bit. 5. The MSSP module shifts in the ACK bit from the In this case, the R/W bit will be logic ‘0’. Serial data is slave device and writes its value into the transmitted 8 bits at a time. After each byte is transmit- SSPxCON2 register (SSPxCON2<6>). ted, an Acknowledge bit is received. Start and Stop 6. The MSSP module generates an interrupt at the conditions are output to indicate the beginning and the end of the ninth clock cycle by setting the end of a serial transfer. SSPxIF bit. In Master Receive mode, the first byte transmitted 7. The user loads the SSPxBUF with eight bits of contains the slave address of the transmitting device data. (7bits) and the R/W bit. In this case, the R/W bit will be 8. Data is shifted out the SDAx pin until all 8 bits logic ‘1’. Thus, the first byte transmitted is a 7-bit slave are transmitted. address, followed by a ‘1’ to indicate the receive bit. 9. The MSSP module shifts in the ACK bit from the Serial data is received via SDAx, while SCLx outputs slave device and writes its value into the the serial clock. Serial data is received 8 bits at a time. SSPxCON2 register (SSPxCON2<6>). After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the 10. The MSSP module generates an interrupt at the beginning and end of transmission. end of the ninth clock cycle by setting the SSPxIF bit. The Baud Rate Generator used for the SPI mode 11. The user generates a Stop condition by setting operation is used to set the SCLx clock frequency for either 100kHz, 400kHz or 1MHz I2C operation. See the Stop Enable bit, PEN (SSPxCON2<2>). Section19.4.7 “Baud Rate” for more detail. 12. Interrupt is generated once the Stop condition is complete. © 2008 Microchip Technology Inc. DS39646C-page 231

PIC18F8722 FAMILY 19.4.7 BAUD RATE 19.4.7.1 Baud Rate and Module In I2C Master mode, the Baud Rate Generator (BRG) Interdependence reload value is placed in the lower 7 bits of the Because MSSP1 and MSSP2 are independent, they SSPxADD register (Figure19-17). When a write can operate simultaneously in I2C Master mode at occurs to SSPxBUF, the Baud Rate Generator will different baud rates. This is done by using different automatically begin counting. The BRG counts down to BRG reload values for each module. ‘0’ and stops until another reload has taken place. The Because this mode derives its basic clock source from BRG count is decremented twice per instruction cycle the system clock, any changes to the clock will affect (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the both modules in the same proportion. It may be BRG is reloaded automatically. possible to change one or both baud rates back to a Once the given operation is complete (i.e., transmis- previous value by changing the BRG reload value. sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCLx pin will remain in its last state. Table19-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD. FIGURE 19-17: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPxADD<6:0> SSPM<3:0> Reload Reload SCLx Control CLKO BRG Down Counter FOSC/4 TABLE 19-3: I2C™ CLOCK RATE w/BRG FSCL FOSC FCY FCY*2 BRG Value (2 Rollovers of BRG) 40 MHz 10 MHz 20 MHz 18h 400 kHz(1) 40 MHz 10 MHz 20 MHz 1Fh 312.5 kHz 40 MHz 10 MHz 20 MHz 63h 100 kHz 16 MHz 4 MHz 8 MHz 09h 400 kHz(1) 16 MHz 4 MHz 8 MHz 0Ch 308 kHz 16 MHz 4 MHz 8 MHz 27h 100 kHz 4 MHz 1 MHz 2 MHz 02h 333 kHz(1) 4 MHz 1 MHz 2 MHz 09h 100 kHz 4 MHz 1 MHz 2 MHz 00h 1 MHz(1) Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100kHz) in all details, but may be used with care where higher rates are required by the application. DS39646C-page 232 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 19.4.7.2 Clock Arbitration SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and Clock arbitration occurs when the master, during any begins counting. This ensures that the SCLx high time receive, transmit or Repeated Start/Stop condition, will always be at least one BRG rollover count in the deasserts the SCLx pin (SCLx allowed to float high). event that the clock is held low by an external device When the SCLx pin is allowed to float high, the Baud (Figure19-18). Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the FIGURE 19-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDAx DX DX – 1 SCLx deasserted but slave holds SCLx allowed to transition high SCLx low (clock arbitration) SCLx BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCLx is sampled high, reload takes place and BRG starts its count BRG Reload © 2008 Microchip Technology Inc. DS39646C-page 233

PIC18F8722 FAMILY 19.4.8 I2C MASTER MODE START Note: If at the beginning of the Start condition, CONDITION TIMING the SDAx and SCLx pins are already sam- To initiate a Start condition, the user sets the Start pled low, or if during the Start condition, the Enable bit, SEN (SSPxCON2<0>). If the SDAx and SCLx line is sampled low before the SDAx SCLx pins are sampled high, the Baud Rate Generator line is driven low, a bus collision occurs, is reloaded with the contents of SSPxADD<6:0> and the Bus Collision Interrupt Flag, BCLxIF, is starts its count. If SCLx and SDAx are both sampled set, the Start condition is aborted and the high when the Baud Rate Generator times out (TBRG), I2C module is reset into its Idle state. the SDAx pin is driven low. The action of the SDAx 19.4.8.1 WCOL Status Flag being driven low while SCLx is high is the Start condi- tion and causes the S bit (SSPxSTAT<3>) to be set. If the user writes the SSPxBUF when a Start sequence Following this, the Baud Rate Generator is reloaded is in progress, the WCOL bit is set and the contents of with the contents of SSPxADD<6:0> and resumes its the buffer are unchanged (the write doesn’t occur). count. When the Baud Rate Generator times out Note: Because queueing of events is not (TBRG), the SEN bit (SSPxCON2<0>) will be auto- allowed, writing to the lower 5 bits of matically cleared by hardware; the Baud Rate Generator SSPxCON2 is disabled until the Start is suspended, leaving the SDAx line held low and the condition is complete. Start condition is complete. FIGURE 19-19: FIRST START BIT TIMING Set S bit (SSPxSTAT<3>) Write to SEN bit occurs here SDAx = 1, At completion of Start bit, SCLx = 1 hardware clears SEN bit and sets SSPxIF bit TBRG TBRG Write to SSPxBUF occurs here 1st bit 2nd bit SDAx TBRG SCLx TBRG S DS39646C-page 234 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 19.4.9 I2C MASTER MODE REPEATED Note1: If RSEN is programmed while any other START CONDITION TIMING event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit 2: A bus collision during the Repeated Start (SSPxCON2<1>) is programmed high and the I2C logic condition occurs if: module is in the Idle state. When the RSEN bit is set, • SDAx is sampled low when SCLx the SCLx pin is asserted low. When the SCLx pin is goes from low-to-high. sampled low, the Baud Rate Generator is loaded with • SCLx goes low before SDAx is the contents of SSPxADD<5:0> and begins counting. asserted low. This may indicate that The SDAx pin is released (brought high) for one Baud another master is attempting to Rate Generator count (TBRG). When the Baud Rate transmit a data ‘1’. Generator times out, if SDAx is sampled high, the SCLx pin will be deasserted (brought high). When SCLx is Immediately following the SSPxIF bit getting set, the sampled high, the Baud Rate Generator is reloaded user may write the SSPxBUF with the 7-bit address in with the contents of SSPxADD<6:0> and begins count- 7-bit mode or the default first address in 10-bit mode. ing. SDAx and SCLx must be sampled high for one After the first eight bits are transmitted and an ACK is TBRG. This action is then followed by assertion of the received, the user may then transmit an additional eight SDAx pin (SDAx = 0) for one TBRG while SCLx is high. bits of address (10-bit mode) or eight bits of data (7-bit Following this, the RSEN bit (SSPxCON2<1>) will be mode). automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDAx pin held low. As 19.4.9.1 WCOL Status Flag soon as a Start condition is detected on the SDAx and If the user writes the SSPxBUF when a Repeated Start SCLx pins, the S bit (SSPxSTAT<3>) will be set. The sequence is in progress, the WCOL is set and the SSPxIF bit will not be set until the Baud Rate Generator contents of the buffer are unchanged (the write doesn’t has timed out. occur). Note: Because queueing of events is not allowed, writing of the lower 5 bits of SSPxCON2 is disabled until the Repeated Start condition is complete. FIGURE 19-20: REPEATED START CONDITION WAVEFORM S bit set by hardware SDAx = 1, At completion of Start bit, Write to SSPxCON2 occurs here:SDAx = 1, SCLx = 1 hardware clears RSEN bit SCLx (no change). and sets SSPxIF TBRG TBRG TBRG SDAx 1st bit RSEN bit set by hardware on falling edge of ninth clock, Write to SSPxBUF occurs here end of Xmit TBRG SCLx TBRG Sr = Repeated Start © 2008 Microchip Technology Inc. DS39646C-page 235

PIC18F8722 FAMILY 19.4.10 I2C MASTER MODE TRANSMISSION The user should verify that the WCOL bit is clear after each write to SSPxBUF to ensure the transfer is correct. Transmission of a data byte, a 7-bit address, or the In all cases, WCOL must be cleared in software. other half of a 10-bit address, is accomplished by sim- ply writing a value to the SSPxBUF register. This action 19.4.10.3 ACKSTAT Status Flag will set the Buffer Full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next In Transmit mode, the ACKSTAT bit (SSPxCON2<6>) is cleared when the slave has sent an Acknowledge transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is (ACK=0) and is set when the slave does not Acknowl- asserted (see data hold time specification edge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), parameter106). SCLx is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid or when the slave has properly received its data. before SCLx is released high (see data setup time 19.4.11 I2C MASTER MODE RECEPTION specification parameter 107). When the SCLx pin is released high, it is held that way for TBRG. The data on Master mode reception is enabled by programming the the SDAx pin must remain stable for that duration and Receive Enable bit, RCEN (SSPxCON2<3>). some hold time after the next falling edge of SCLx. Note: The MSSP module must be in an inactive After the eighth bit is shifted out (the falling edge of the state before the RCEN bit is set or the eighth clock), the BF flag is cleared and the master RCEN bit will be disregarded. releases SDAx. This allows the slave device being addressed to respond with an ACK bit during the ninth The Baud Rate Generator begins counting and on each bit time if an address match occurred, or if data was rollover, the state of the SCLx pin changes received properly. The status of ACK is written into the (high-to-low/low-to-high) and data is shifted into the ACKDT bit on the falling edge of the ninth clock. If the SSPxSR. After the falling edge of the eighth clock, the master receives an Acknowledge, the Acknowledge receive enable flag is automatically cleared, the con- Status bit, ACKSTAT, is cleared. If not, the bit is set. tents of the SSPxSR are loaded into the SSPxBUF, the After the ninth clock, the SSPxIF bit is set and the BF flag bit is set, the SSPxIF flag bit is set and the Baud master clock (Baud Rate Generator) is suspended until Rate Generator is suspended from counting, holding the next data byte is loaded into the SSPxBUF, leaving SCLx low. The MSSP is now in Idle state awaiting the SCLx low and SDAx unchanged (Figure19-21). next command. When the buffer is read by the CPU, After the write to the SSPxBUF, each bit of the address the BF flag bit is automatically cleared. The user can will be shifted out on the falling edge of SCLx until all then send an Acknowledge bit at the end of reception seven address bits and the R/W bit are completed. On by setting the Acknowledge Sequence Enable bit, the falling edge of the eighth clock, the master will ACKEN (SSPxCON2<4>). deassert the SDAx pin, allowing the slave to respond 19.4.11.1 BF Status Flag with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDAx pin to see if the In receive operation, the BF bit is set when an address address was recognized by a slave. The status of the or data byte is loaded into SSPxBUF from SSPxSR. It ACK bit is loaded into the ACKSTAT status bit is cleared when the SSPxBUF register is read. (SSPxCON2<6>). Following the falling edge of the 19.4.11.2 SSPOV Status Flag ninth clock transmission of the address, the SSPxIF is set, the BF flag is cleared and the Baud Rate Generator In receive operation, the SSPOV bit is set when 8 bits is turned off until another write to the SSPxBUF takes are received into the SSPxSR and the BF flag bit is place, holding SCLx low and allowing SDAx to float. already set from a previous reception. 19.4.10.1 BF Status Flag 19.4.11.3 WCOL Status Flag In Transmit mode, the BF bit (SSPxSTAT<0>) is set If the user writes the SSPxBUF when a receive is when the CPU writes to SSPxBUF and is cleared when already in progress (i.e., SSPxSR is still shifting in a all 8 bits are shifted out. data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur). 19.4.10.2 WCOL Status Flag If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPxSR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur) after 2TCY after the SSPxBUF write. If SSPxBUF is rewritten within 2 TCY, the WCOL bit is set and SSPxBUF is updated. This may result in a corrupted transfer. DS39646C-page 236 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 19-21: I2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) 1 AT in ON2 = oftware STxC P n s ACKSSP ared i K e C 9 Cl A > 6 N2< D0 8 ne slave, clear ACKSTAT bit SSPxCO Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1 234567 Cleared in software service routifrom MSSP interrupt SSPxBUF is written in software om D7 1 xIF Fr ow SP 0= SCLx held lwhile CPUsponds to S CK re 0= A W, 9 are R/W A1 ess and R/ 78 d by hardw ave A2 addr 6 eare 1PxCON2<0> (SEN = ),dition begins 0SEN = Transmit Address to Sl A7A6A5A4A3 SSPxBUF written with 7-bit start transmit 12345 Cleared in software SSPxBUF written After Start condition, SEN cl Sn Write SStart co S T<0>) A T S x F SP SDAx SCLx SSPxI BF (S SEN PEN R/W © 2008 Microchip Technology Inc. DS39646C-page 237

PIC18F8722 FAMILY FIGURE 19-22: I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) pt et ACKEN, start Acknowledge sequence,1DAx = ACKDT = 1PEN bit = N clearedwritten herematically D0ACK Bus masterACK is not sentterminatestransfer98PSet SSPxIF at endof receiveSet SSPxIF interruat end of Acknow-ledge sequence Set P bit (SSPxSTAT<4>)Cleared insoftwareand SSPxIF SSPOV is set becauseSSPxBUF is still full SS RCEauto D1 7 CLK Write to SSPxCON2<4>to start Acknowledge sequence,0SDAx = ACKDT (SSPxCON2<5>) = ACK from master,er configured as a receiver0SDAx = ACKDT = 1ogramming SSPxCON2<3> (RCEN = ) 1RCEN = , startRCEN clearednext receiveautomatically Receiving Data from SlaveReceiving Data from SlaveACKD2D5D2D5D3D4D6D7D3D4D6D7D1D0 678956512343124 Data shifted in on falling edge of Set SSPxIF interruptSet SSPxIF interruptat end of receiveat end of Acknowledgesequence Cleared in softwareCleared in softwareCleared in software Last bit is shifted into SSPxSR andcontents are unloaded into SSPxBUF Mastby pr ACK from Slave 0R/W = A1ACK 798 e, 1Write to SSPxCON2<0> (SEN = ),begin Start condition 0SEN = Write to SSPxBUF occurs herstart XMIT Transmit Address to Slave A7A6A5A4A3A2SDAx 361245SCLxS SSPxIF Cleared in software01SDAx = , SCLx = ,while CPU responds to SSPxIF BF (SSPxSTAT<0>) SSPOV ACKEN DS39646C-page 238 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 19.4.12 ACKNOWLEDGE SEQUENCE 19.4.13 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDAx pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge Sequence Enable bit, ACKEN bit, PEN (SSPxCON2<2>). At the end of a (SSPxCON2<4>). When this bit is set, the SCLx pin is receive/transmit, the SCLx line is held low after the pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set, are presented on the SDAx pin. If the user wishes to the master will assert the SDAx line low. When the generate an Acknowledge, then the ACKDT bit should SDAx line is sampled low, the Baud Rate Generator is be cleared. If not, the user should set the ACKDT bit reloaded and counts down to ‘0’. When the Baud Rate before starting an Acknowledge sequence. The Baud Generator times out, the SCLx pin will be brought high Rate Generator then counts for one rollover period and one TBRG (Baud Rate Generator rollover count) (TBRG) and the SCLx pin is deasserted (pulled high). later, the SDAx pin will be deasserted. When the SDAx When the SCLx pin is sampled high (clock arbitration), pin is sampled high while SCLx is high, the P bit the Baud Rate Generator counts for TBRG. The SCLx pin (SSPxSTAT<4>) is set. A TBRG later, the PEN bit is is then pulled low. Following this, the ACKEN bit is auto- cleared and the SSPxIF bit is set (Figure19-24). matically cleared, the Baud Rate Generator is turned off 19.4.13.1 WCOL Status Flag and the MSSP module then goes into an inactive state (Figure19-23). If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the 19.4.12.1 WCOL Status Flag contents of the buffer are unchanged (the write doesn’t If the user writes the SSPxBUF when an Acknowledge occur). sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). FIGURE 19-23: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSPxCON2, ACKEN = 1, ACKDT = 0 TBRG TBRG SDAx D0 ACK SCLx 8 9 SSPxIF Cleared in SSPxIF set at Cleared in software the end of receive software SSPxIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 19-24: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPxCON2, SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG set PEN after SDAx sampled high. P bit (SSPxSTAT<4>) is set. Falling edge of PEN bit (SSPxCON2<2>) is cleared by 9th clock hardware and the SSPxIF bit is set TBRG SCLx SDAx ACK P TBRG TBRG TBRG SCLx brought high after TBRG SDAx asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. © 2008 Microchip Technology Inc. DS39646C-page 239

PIC18F8722 FAMILY 19.4.14 SLEEP OPERATION 19.4.17 MULTI -MASTER COMMUNICATION, While in Sleep mode, the I2C module can receive BUS COLLISION AND BUS ARBITRATION addresses or data and when an address match or complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra- from Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto the SDAx pin, arbitration takes place when the master 19.4.15 EFFECTS OF A RESET outputs a ‘1’ on SDAx, by letting SDAx float high and A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCLx pin floats current transfer. high, data should be stable. If the expected data on SDAx is a ‘1’ and the data sampled on the SDAx 19.4.16 MULTI-MASTER MODE pin=0, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLxIF In Multi-Master mode, the interrupt generation on the and reset the I2C port to its Idle state (Figure19-25). detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is MSSP module is disabled. Control of the I2C bus may cleared, the SDAx and SCLx lines are deasserted and be taken when the P bit (SSPxSTAT<4>) is set, or the the SSPxBUF can be written to. When the user services bus is Idle, with both the S and P bits clear. When the the bus collision Interrupt Service Routine and if the I2C bus is busy, enabling the MSSP interrupt will generate bus is free, the user can resume communication by the interrupt when the Stop condition occurs. asserting a Start condition. In multi-master operation, the SDAx line must be If a Start, Repeated Start, Stop or Acknowledge condition monitored for arbitration to see if the signal level is the was in progress when the bus collision occurred, the con- expected output level. This check is performed in dition is aborted, the SDAx and SCLx lines are hardware with the result placed in the BCLxIF bit. deasserted and the respective control bits in the SSPxCON2 register are cleared. When the user services The states where arbitration can be lost are: the bus collision Interrupt Service Routine and if the I2C • Address Transfer bus is free, the user can resume communication by • Data Transfer asserting a Start condition. • A Start Condition The master will continue to monitor the SDAx and SCLx • A Repeated Start Condition pins. If a Stop condition occurs, the SSPxIF bit will be set. • An Acknowledge Condition A write to the SSPxBUF will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the deter- mination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPxSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 19-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Sample SDAx. While SCLx is high, Data changes SDAx line pulled low data doesn’t match what is driven while SCLx = 0 by another source by the master. Bus collision has occurred. SDAx released by master SDAx SCLx Set bus collision interrupt (BCLxIF) BCLxIF DS39646C-page 240 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 19.4.17.1 Bus Collision During a Start If the SDAx pin is sampled low during this count, the Condition BRG is reset and the SDAx line is asserted early (Figure19-28). If, however, a ‘1’ is sampled on the During a Start condition, a bus collision occurs if: SDAx pin, the SDAx pin is asserted low at the end of a) SDAx or SCLx are sampled low at the beginning the BRG count. The Baud Rate Generator is then of the Start condition (Figure19-26). reloaded and counts down to ‘0’. If the SCLx pin is b) SCLx is sampled low before SDAx is asserted sampled as ‘0’ during this time, a bus collision does not low (Figure19-27). occur. At the end of the BRG count, the SCLx pin is asserted low. During a Start condition, both the SDAx and the SCLx pins are monitored. Note: The reason that bus collision is not a factor during a Start condition is that no two bus If the SDAx pin is already low, or the SCLx pin is masters can assert a Start condition at the already low, then all of the following occur: exact same time. Therefore, one master • the Start condition is aborted, will always assert SDAx before the other. • the BCLxIF flag is set and This condition does not cause a bus colli- • the MSSP module is reset to its inactive state sion because the two masters must be (Figure19-26). allowed to arbitrate the first address The Start condition begins with the SDAx and SCLx following the Start condition. If the address pins deasserted. When the SDAx pin is sampled high, is the same, arbitration must be allowed to the Baud Rate Generator is loaded from continue into the data portion, Repeated SSPxADD<6:0> and counts down to ‘0’. If the SCLx pin Start or Stop conditions. is sampled low while SDAx is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 19-26: BUS COLLISION DURING START CONDITION (SDAx ONLY) SDAx goes low before the SEN bit is set. Set BCLxIF, S bit and SSPxIF set because SDAx = 0, SCLx = 1. SDAx SCLx Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDAx = 1, SCLx = 1 MSSP module reset into Idle state. SEN SDAx sampled low before Start condition. Set BCLxIF. S bit and SSPxIF set because BCLxIF SDAx = 0, SCLx = 1. SSPxIF and BCLxIF are cleared in software S SSPxIF SSPxIF and BCLxIF are cleared in software © 2008 Microchip Technology Inc. DS39646C-page 241

PIC18F8722 FAMILY FIGURE 19-27: BUS COLLISION DURING START CONDITION (SCLx = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start SCLx sequence if SDAx = 1, SCLx = 1 SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF. BCLxIF Interrupt cleared in software S ‘0’ ‘0’ SSPxIF ‘0’ ‘0’ FIGURE 19-28: BRG RESET DUE TO SDAx ARBITRATION DURING START CONDITION SDAx = 0, SCLx = 1 Set S Set SSPxIF Less than TBRG TBRG SDAx SDAx pulled low by other master. Reset BRG and assert SDAx. SCLx S SCLx pulled low after BRG time-out SEN Set SEN, enable START sequence if SDAx = 1, SCLx = 1 BCLxIF ‘0’ S SSPxIF SDAx = 0, SCLx = 1, Interrupts cleared set SSPxIF in software DS39646C-page 242 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 19.4.17.2 Bus Collision During a Repeated If SDAx is low, a bus collision has occurred (i.e., another Start Condition master is attempting to transmit a data ‘0’, Figure19-29). If SDAx is sampled high, the BRG is reloaded and During a Repeated Start condition, a bus collision begins counting. If SDAx goes from high-to-low before occurs if: the BRG times out, no bus collision occurs because no a) A low level is sampled on SDAx when SCLx two masters can assert SDAx at exactly the same time. goes from low level to high level. If SCLx goes from high-to-low before the BRG times b) SCLx goes low before SDAx is asserted low, out and SDAx has not already been asserted, a bus indicating that another master is attempting to collision occurs. In this case, another master is transmit a data ‘1’. attempting to transmit a data ‘1’ during the Repeated When the user deasserts SDAx and the pin is allowed Start condition (see Figure19-30). to float high, the BRG is loaded with SSPxADD<6:0> If, at the end of the BRG time-out, both SCLx and SDAx and counts down to ‘0’. The SCLx pin is then are still high, the SDAx pin is driven low and the BRG is deasserted and when sampled high, the SDAx pin is reloaded and begins counting. At the end of the count, sampled. regardless of the status of the SCLx pin, the SCLx pin is driven low and the Repeated Start condition is complete. FIGURE 19-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDAx SCLx Sample SDAx when SCLx goes high. If SDAx = 0, set BCLxIF and release SDAx and SCLx. RSEN BCLxIF Cleared in software S ‘0’ SSPxIF ‘0’ FIGURE 19-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDAx SCLx SCLx goes low before SDAx, BCLxIF set BCLxIF. Release SDAx and SCLx. Interrupt cleared in software RSEN S ‘0’ SSPxIF © 2008 Microchip Technology Inc. DS39646C-page 243

PIC18F8722 FAMILY 19.4.17.3 Bus Collision During a Stop The Stop condition begins with SDAx asserted low. Condition When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with a) After the SDAx pin has been deasserted and SSPxADD<6:0> and counts down to ‘0’. After the BRG allowed to float high, SDAx is sampled low after times out, SDAx is sampled. If SDAx is sampled low, a the BRG has timed out. bus collision has occurred. This is due to another b) After the SCLx pin is deasserted, SCLx is master attempting to drive a data ‘0’ (Figure19-31). If sampled low before SDAx goes high. the SCLx pin is sampled low before SDAx is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure19-32). FIGURE 19-31: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDAx sampled low after TBRG, set BCLxIF SDAx SDAx asserted low SCLx PEN BCLxIF P ‘0’ SSPxIF ‘0’ FIGURE 19-32: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDAx SCLx goes low before SDAx goes high, Assert SDAx set BCLxIF SCLx PEN BCLxIF P ‘0’ SSPxIF ‘0’ DS39646C-page 244 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 19-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 PIR2 OSCFIF CMIF — EEIF BCL1IF HLVDIF TMR3IF CCP2IF 60 PIE2 OSCFIE CMIE — EEIE BCL1IE HLVDIE TMR3IE CCP2IE 60 IPR2 OSCFIP CMIP — EEIP BCL1IP HLVDIP TMR3IP CCP2IP 60 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 60 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 60 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 60 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 60 SSP1BUF MSSP1 Receive Buffer/Transmit Register 58 SSP2BUF MSSP2 Receive Buffer/Transmit Register 61 SSP1ADD MSSP1 Address Register in I2C™ Slave mode. MSSP1 Baud Rate Reload Register in I2C 58 Master mode. SSP2ADD MSSP2 Address Register in I2C Slave mode. MSSP2 Baud Rate Reload Register in I2C 61 Master mode. TMR2 Timer2 Register 58 PR2 Timer2 Period Register 58 SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 58 SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 58 SSP1STAT SMP CKE D/A P S R/W UA BF 58 SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 61 SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 61 SSP2STAT SMP CKE D/A P S R/W UA BF 61 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I2C mode. © 2008 Microchip Technology Inc. DS39646C-page 245

PIC18F8722 FAMILY NOTES: DS39646C-page 246 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 20.0 ENHANCED UNIVERSAL The pins of EUSART1 and EUSART2 are multiplexed SYNCHRONOUS RECEIVER with the functions of PORTC (RC6/TX1/CK1 and RC7/ RX1/DT1) and PORTG (RG1/TX2/CK2 and RG2/RX2/ TRANSMITTER (EUSART) DT2), respectively. In order to configure these pins as an EUSART: The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of two • For EUSART1: serial I/O modules. (Generically, the USART is also - bit SPEN (RCSTA1<7>) must be set (= 1) known as a Serial Communications Interface or SCI.) - bit TRISC<7> must be set (= 1) The EUSART can be configured as a full-duplex - bit TRISC<6> must be cleared (= 0) for asynchronous system that can communicate with Asynchronous and Synchronous Master peripheral devices, such as CRT terminals and modes personal computers. It can also be configured as a half- - bit TRISC<6> must be set (= 1) for duplex synchronous system that can communicate Synchronous Slave mode with peripheral devices, such as A/D or D/A integrated • For EUSART2: circuits, serial EEPROMs, etc. - bit SPEN (RCSTA2<7>) must be set (= 1) The Enhanced USART module implements additional - bit TRISG<2> must be set (= 1) features, including automatic baud rate detection and - bit TRISG<1> must be cleared (= 0) for calibration, automatic wake-up on Sync Break recep- Asynchronous and Synchronous Master tion and 12-bit Break Character transmit. These make modes it ideally suited for use in Local Interconnect Network - bit TRISC<6> must be set (= 1) for bus (LIN bus) systems. Synchronous Slave mode The EUSART can be configured in the following Note: The EUSART control will automatically modes: reconfigure the pin from input to output as • Asynchronous (full duplex) with: needed. - Auto-Wake-up on Character Reception The operation of each Enhanced USART module is - Auto-Baud Calibration controlled through three registers: - 12-bit Break Character Transmission • Transmit Status and Control (TXSTAx) • Synchronous – Master (half duplex) with • Receive Status and Control (RCSTAx) Selectable Clock Polarity • Baud Rate Control (BAUDCONx) • Synchronous – Slave (half duplex) with Selectable Clock Polarity These are detailed on the following pages in Register20-1, Register20-2 and Register20-3, respectively. Note: Throughout this section, references to register and bit names that may be associ- ated with a specific EUSART module are referred to generically by the use of ‘x’ in place of the specific module number. Thus, “RCSTAx” might refer to the Receive Status register for either EUSART1 or EUSART2 © 2008 Microchip Technology Inc. DS39646C-page 247

PIC18F8722 FAMILY REGISTER 20-1: TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in Sync mode. bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care. bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSRx empty 0 = TSRx full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. DS39646C-page 248 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY REGISTER 20-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care. Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave: Don’t care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSRx<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 9-bit (RX9 = 0): Don’t care. bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREGx register and receiving next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. © 2008 Microchip Technology Inc. DS39646C-page 249

PIC18F8722 FAMILY REGISTER 20-3: BAUDCONx: BAUD RATE CONTROL REGISTER R/W-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurred bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receive operation is inactive 0 = Receive operation is active bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: Unused in this mode. Synchronous mode: 1 = Idle state for clock (CKx) is a high level 0 = Idle state for clock (CKx) is a low level bit 3 BRG16: 16-bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator – SPBRGHx and SPBRGx 0 = 8-bit Baud Rate Generator – SPBRGx only (Compatible mode), SPBRGHx value ignored bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RXx pin – interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RXx pin not monitored or rising edge detected Synchronous mode: Unused in this mode. bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h); cleared in hardware upon completion. 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. DS39646C-page 250 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 20.1 Baud Rate Generator (BRG) advantageous to use the high baud rate (BRGH = 1) or the 16-bit BRG to reduce the baud rate error, or The BRG is a dedicated 8-bit or 16-bit generator that achieve a slow baud rate for a fast oscillator frequency. supports both the Asynchronous and Synchronous Writing a new value to the SPBRGHx:SPBRGx regis- modes of the EUSART. By default, the BRG operates ters causes the BRG timer to be reset (or cleared). This in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>) ensures the BRG does not wait for a timer overflow selects 16-bit mode. before outputting the new baud rate. The SPBRGHx:SPBRGx register pair controls the period of a free running timer. In Asynchronous mode, 20.1.1 OPERATION IN POWER-MANAGED bits BRGH (TXSTAx<2>) and BRG16 MODES (BAUDCONx<3>) also control the baud rate. In The device clock is used to generate the desired baud Synchronous mode, BRGH is ignored. Table20-1 rate. When one of the power-managed modes is shows the formula for computation of the baud rate for entered, the new clock source may be operating at a different EUSART modes which only apply in Master different frequency. This may require an adjustment to mode (internally generated clock). the value in the SPBRGx register pair. Given the desired baud rate and FOSC, the nearest integer value for the SPBRGHx:SPBRGx registers can 20.1.2 SAMPLING be calculated using the formulas in Table20-1. From The data on the RXx pin (either RC7/RX1/DT1 or RG2/ this, the error in baud rate can be determined. An RX2/DT2) is sampled three times by a majority detect example calculation is shown in Example20-1. Typical circuit to determine if a high or a low level is present at baud rates and error values for the various Asynchro- the RXx pin. nous modes are shown in Table20-2. It may be TABLE 20-1: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n + 1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n + 1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n + 1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPBRGHx:SPBRGx register pair © 2008 Microchip Technology Inc. DS39646C-page 251

PIC18F8722 FAMILY EXAMPLE 20-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGHx:SPBRGx] + 1)) Solving for SPBRGHx:SPBRGx: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate= 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.16% TABLE 20-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 59 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 59 BAUDCONx ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 61 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 59 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 59 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. DS39646C-page 252 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — — 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — — 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51 1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12 2.4 2.404 0.16 25 2.403 -0.16 12 — — — 9.6 8.929 -6.99 6 — — — — — — 19.2 20.833 8.51 2 — — — — — — 57.6 62.500 8.51 0 — — — — — — 115.2 62.500 -45.75 0 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — — — — — — — — — — 2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — © 2008 Microchip Technology Inc. DS39646C-page 253

PIC18F8722 FAMILY TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1665 1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1.201 -0.16 415 2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2.403 -0.16 207 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 0.300 -0.01 6665 1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1.200 -0.04 1665 2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2.400 -0.04 832 9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9.615 -0.16 207 19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19.230 -0.16 103 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57.142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 11.7647 -2.12 16 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.01 3332 0.300 -0.04 1665 0.300 -0.04 832 1.2 1.200 0.04 832 1.201 -0.16 415 1.201 -0.16 207 2.4 2.404 0.16 415 2.403 -0.16 207 2.403 -0.16 103 9.6 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25 19.2 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12 57.6 58.824 2.12 16 55.555 3.55 8 — — — 115.2 111.111 -3.55 8 — — — — — — DS39646C-page 254 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 20.1.3 AUTO-BAUD RATE DETECT Note1: If the WUE bit is set with the ABDEN bit, The Enhanced USART module supports the automatic Auto-Baud Rate Detection will occur on detection and calibration of baud rate. This feature is the byte following the Break character. active only in Asynchronous mode and while the WUE 2: It is up to the user to determine that the bit is clear. incoming character baud rate is within the The automatic baud rate measurement sequence range of the selected BRG clock source. (Figure20-1) begins whenever a Start bit is received Some combinations of oscillator frequency and the ABDEN bit is set. The calculation is and EUSART baud rates are not possible self-averaging. due to bit error rates. Overall system timing and communication baud rates In the Auto-Baud Rate Detect (ABD) mode, the clock to must be taken into consideration when the BRG is reversed. Rather than the BRG clocking the using the Auto-Baud Rate Detection incoming RXx signal, the RXx signal is timing the BRG. feature. In ABD mode, the internal Baud Rate Generator is used as a counter to time the bit period of the incoming serial byte stream. TABLE 20-4: BRG COUNTER CLOCK RATES Once the ABDEN bit is set, the state machine will clear the BRG and look for a Start bit. The Auto-Baud Rate BRG16 BRGH BRG Counter Clock Detect must receive a byte with the value 55h (ASCII “U”, which is also the LIN bus Sync character) in order to 0 0 FOSC/512 calculate the proper bit rate. The measurement is taken 0 1 FOSC/128 over both a low and a high bit time in order to minimize 1 0 FOSC/128 any effects caused by asymmetry of the incoming signal. 1 1 FOSC/32 After a Start bit, the SPBRGx begins counting up, using Note: During the ABD sequence, SPBRGx and the preselected clock source on the first rising edge of SPBRGHx are both used as a 16-bit counter, RXx. After eight bits on the RXx pin or the fifth rising independent of BRG16 setting. edge, an accumulated value totalling the proper BRG period is left in the SPBRGHx:SPBRGx register pair. Once the 5th edge is seen (this should correspond to the 20.1.3.1 ABD and EUSART Transmission Stop bit), the ABDEN bit is automatically cleared. Since the BRG clock is reversed during ABD acquisi- If a rollover of the BRG occurs (an overflow from FFFFh tion, the EUSART transmitter cannot be used during to 0000h), the event is trapped by the ABDOVF status ABD. This means that whenever the ABDEN bit is set, bit (BAUDCONx<7>). It is set in hardware by BRG roll- TXREGx cannot be written to. Users should also overs and can be set or cleared by the user in software. ensure that ABDEN does not become set during a ABD mode remains active after rollover events and the transmit sequence. Failing to do this may result in ABDEN bit remains set (Figure20-2). unpredictable EUSART operation. While calibrating the baud rate period, the BRG regis- ters are clocked at 1/8th the preconfigured clock rate. Note that the BRG clock will be configured by the BRG16 and BRGH bits. Independent of the BRG16 bit setting, both the SPBRGx and SPBRGHx will be used as a 16-bit counter. This allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the SPBRGHx register. Refer to Table20-4 for counter clock rates to the BRG. While the ABD sequence takes place, the EUSART state machine is held in Idle. The RCxIF interrupt is set once the fifth rising edge on RXx is detected. The value in the RCREGx needs to be read to clear the RCxIF interrupt. The contents of RCREGx should be discarded. © 2008 Microchip Technology Inc. DS39646C-page 255

PIC18F8722 FAMILY FIGURE 20-1: AUTOMATIC BAUD RATE CALCULATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RXx pin Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Stop Bit BRG Clock Set by User Auto-Cleared ABDEN bit RCxIF bit (Interrupt) Read RCREGx SPBRGx XXXXh 1Ch SPBRGHx XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE=0. FIGURE 20-2: BRG OVERFLOW SEQUENCE BRG Clock ABDEN bit RXx pin Start Bit 0 ABDOVF bit FFFFh BRG Value XXXXh 0000h 0000h DS39646C-page 256 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 20.2 EUSART Asynchronous Mode Once the TXREGx register transfers the data to the TSRx register (occurs in one TCY), the TXREGx register The Asynchronous mode of operation is selected by is empty and the TXxIF flag bit (PIR1<4>) is set. This clearing the SYNC bit (TXSTAx<4>). In this mode, the interrupt can be enabled or disabled by setting or clearing EUSART uses standard Non-Return-to-Zero (NRZ) the interrupt enable bit, TXxIE (PIE1<4>). TXxIF will be format (one Start bit, eight or nine data bits and one Stop set regardless of the state of TXxIE; it cannot be cleared bit). The most common data format is 8 bits. An on-chip in software. TXxIF is also not cleared immediately upon dedicated 8-bit/16-bit Baud Rate Generator can be used loading TXREGx, but becomes valid in the second to derive standard baud rate frequencies from the instruction cycle following the load instruction. Polling oscillator. TXxIF immediately following a load of TXREGx will return The EUSART transmits and receives the LSb first. The invalid results. EUSART’s transmitter and receiver are functionally independent, but use the same data format and baud While TXxIF indicates the status of the TXREGx regis- rate. The Baud Rate Generator produces a clock, either ter, another bit, TRMT (TXSTAx<1>), shows the status x16 or x64 of the bit shift rate depending on the BRGH of the TSRx register. TRMT is a read-only bit which is and BRG16 bits (TXSTAx<2> and BAUDCONx<3>). set when the TSRx register is empty. No interrupt logic Parity is not supported by the hardware, but can be is tied to this bit so the user has to poll this bit in order implemented in software and stored as the 9th data bit. to determine if the TSRx register is empty. When operating in Asynchronous mode, the EUSART Note1: The TSRx register is not mapped in data module consists of the following important elements: memory so it is not available to the user. • Baud Rate Generator 2: Flag bit, TXxIF, is set when enable bit • Sampling Circuit TXEN is set. • Asynchronous Transmitter To set up an Asynchronous Transmission: • Asynchronous Receiver • Auto-Wake-up on Sync Break Character 1. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the • 12-bit Break Character Transmit BRGH and BRG16 bits, as required, to achieve • Auto-Baud Rate Detection the desired baud rate. 20.2.1 EUSART ASYNCHRONOUS 2. Enable the asynchronous serial port by clearing TRANSMITTER bit, SYNC, and setting bit, SPEN. 3. If interrupts are desired, set enable bit, TXxIE. The EUSART transmitter block diagram is shown in 4. If 9-bit transmission is desired, set transmit bit, Figure20-3. The heart of the transmitter is the Transmit TX9. Can be used as address/data bit. (Serial) Shift Register (TSRx). The Shift register 5. Enable the transmission by setting bit, TXEN, obtains its data from the Read/Write Transmit Buffer which will also set bit, TXxIF. register, TXREGx. The TXREGx register is loaded with data in software. The TSRx register is not loaded until 6. If 9-bit transmission is selected, the ninth bit the Stop bit has been transmitted from the previous should be loaded in bit, TX9D. load. As soon as the Stop bit is transmitted, the TSRx 7. Load data to the TXREGx register (starts is loaded with new data from the TXREGx register (if transmission). available). 8. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. © 2008 Microchip Technology Inc. DS39646C-page 257

PIC18F8722 FAMILY FIGURE 20-3: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXxIF TXREGx Register TXxIE 8 MSb LSb (8) • • • 0 Pin Buffer and Control TSRx Register TXx pin Interrupt TXEN Baud Rate CLK TRMT SPEN BRG16 SPBRGHx SPBRGx TX9 Baud Rate Generator TX9D FIGURE 20-4: ASYNCHRONOUS TRANSMISSION Write to TXREGx Word 1 BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXxIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) FIGURE 20-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREGx Word 1 Word 2 BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXxIF bit 1 TCY Word 1 Word 2 (Interrupt Reg. Flag) 1 TCY Word 1 Word 2 TRMT bit Transmit Shift Reg. Transmit Shift Reg. (Transmit Shift Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions. DS39646C-page 258 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 20-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 59 TXREGx EUSARTx Transmit Register 59 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 59 BAUDCONx ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 61 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 61 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 59 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. © 2008 Microchip Technology Inc. DS39646C-page 259

PIC18F8722 FAMILY 20.2.2 EUSART ASYNCHRONOUS 20.2.3 SETTING UP 9-BIT MODE WITH RECEIVER ADDRESS DETECT The receiver block diagram is shown in Figure20-6. This mode would typically be used in RS-485 systems. The data is received on the RXx pin and drives the data To set up an Asynchronous Reception with Address recovery block. The data recovery block is actually a Detect Enable: high-speed shifter operating at x16 times the baud rate, 1. Initialize the SPBRGHx:SPBRGx registers for whereas the main receive serial shifter operates at the the appropriate baud rate. Set or clear the bit rate or at FOSC. This mode would typically be used BRGH and BRG16 bits, as required, to achieve in RS-232 systems. the desired baud rate. To set up an Asynchronous Reception: 2. Enable the asynchronous serial port by clearing 1. Initialize the SPBRGHx:SPBRGx registers for the SYNC bit and setting the SPEN bit. the appropriate baud rate. Set or clear the 3. If interrupts are required, set the RCEN bit and BRGH and BRG16 bits, as required, to achieve select the desired priority level with the RCxIP the desired baud rate. bit. 2. Enable the asynchronous serial port by clearing 4. Set the RX9 bit to enable 9-bit reception. bit, SYNC, and setting bit, SPEN. 5. Set the ADDEN bit to enable address detect. 3. If interrupts are desired, set enable bit, RCxIE. 6. Enable reception by setting the CREN bit. 4. If 9-bit reception is desired, set bit, RX9. 7. The RCxIF bit will be set when reception is 5. Enable the reception by setting bit, CREN. complete. The interrupt will be Acknowledged if 6. Flag bit, RCxIF, will be set when reception is the RCxIE and GIE bits are set. complete and an interrupt will be generated if 8. Read the RCSTAx register to determine if any enable bit, RCxIE, was set. error occurred during reception, as well as read 7. Read the RCSTAx register to get the 9th bit (if bit 9 of data (if applicable). enabled) and determine if any error occurred 9. Read RCREGx to determine if the device is during reception. being addressed. 8. Read the 8-bit received data by reading the 10. If any error occurred, clear the CREN bit. RCREGx register. 11. If the device has been addressed, clear the 9. If any error occurred, clear the error by clearing ADDEN bit to allow all received data into the enable bit, CREN. receive buffer and interrupt the CPU. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 20-6: EUSART RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK BRG16 SPBRGHx SPBRGx ÷ o6r4 MSb RSRx Register LSb ÷ 16 or Stop (8) 7 • • • 1 0 Start Baud Rate Generator ÷ 4 RX9 Pin Buffer Data and Control Recovery RXx RX9D RCREGx Register FIFO SPEN 8 Interrupt RCxIF Data Bus RCxIE DS39646C-page 260 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 20-7: ASYNCHRONOUS RECEPTION RXx (pin) Start Start Start bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 Read Rcv RCREGx RCREGx Buffer Reg RCREGx RCxIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (receive buffer) is read after the third word causing the OERR (Overrun) bit to be set. TABLE 20-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 59 RCREGx EUSARTx Receive Register 59 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 59 BAUDCONx ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 61 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 61 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 59 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. © 2008 Microchip Technology Inc. DS39646C-page 261

PIC18F8722 FAMILY 20.2.4 AUTO-WAKE-UP ON SYNC BREAK character and cause data or framing errors. To work CHARACTER properly, therefore, the initial character in the transmis- sion must be all ‘0’s. This can be 00h (8 bytes) for During Sleep mode, all clocks to the EUSART are standard RS-232 devices or 000h (12 bits) for LIN bus. suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be Oscillator start-up time must also be considered, performed. The auto-wake-up feature allows the especially in applications using oscillators with longer controller to wake-up due to activity on the RXx/DTx line, start-up intervals (i.e., XT or HS mode). The Sync while the EUSART is operating in Asynchronous mode. Break (or Wake-up Signal) character must be of sufficient length and be followed by a sufficient interval The auto-wake-up feature is enabled by setting the to allow enough time for the selected oscillator to start WUE bit (BAUDCONx<1>). Once set, the typical receive and provide proper initialization of the EUSART. sequence on RXx/DTx is disabled and the EUSART remains in an Idle state, monitoring for a wake-up event 20.2.4.2 Special Considerations Using independent of the CPU mode. A wake-up event the WUE Bit consists of a high-to-low transition on the RXx/DTx line. (This coincides with the start of a Sync Break or a The timing of WUE and RCxIF events may cause Wake-up Signal character for the LIN protocol.) some confusion when it comes to determining the validity of received data. As noted, setting the WUE bit Following a wake-up event, the module generates an places the EUSART in an inactive state. The wake-up RCxIF interrupt. The interrupt is generated synchro- event causes a receive interrupt by setting the RCxIF nously to the Q clocks in normal operating modes bit. The WUE bit is cleared after this when a rising (Figure20-8) and asynchronously, if the device is in edge is seen on RXx/DTx. The interrupt condition is Sleep mode (Figure20-9). The interrupt condition is then cleared by reading the RCREGx register. cleared by reading the RCREGx register. Ordinarily, the data in RCREGx will be dummy data The WUE bit is automatically cleared once a low-to- and should be discarded. high transition is observed on the RXx line following the The fact that the WUE bit has been cleared (or is still wake-up event. At this point, the EUSART module is set) and the RCxIF flag is set should not be used as an inactive and returns to normal operation. This signals to indicator of the integrity of the data in RCREGx. Users the user that the Sync Break event is over. should consider implementing a parallel method in firmware to verify received data integrity. 20.2.4.1 Special Considerations Using Auto-Wake-up To assure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process. If Since auto-wake-up functions by sensing rising edge a receive operation is not occurring, the WUE bit may transitions on RXx/DTx, information with any state then be set just prior to entering the Sleep mode. changes before the Stop bit may signal a false end-of- FIGURE 20-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit(1) RXx/DTx Line RCxIF Cleared due to user read of RCREGx Note1:The EUSART remains inactive while the WUE bit is set. FIGURE 20-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit(2) RXx/DTx Line Note 1 RCxIF Cleared due to user read of RCREGx Sleep Command Executed Sleep Ends Note1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains inactive while the WUE bit is set. DS39646C-page 262 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 20.2.5 BREAK CHARACTER SEQUENCE 1. Configure the EUSART for the desired mode. The EUSART module has the capability of sending the 2. Set the TXEN and SENDB bits to set up the special Break character sequences that are required by Break character. the LIN bus standard. The Break character transmit 3. Load the TXREGx with a dummy character to consists of a Start bit, followed by twelve ‘0’ bits and a initiate transmission (the value is ignored). Stop bit. The frame Break character is sent whenever 4. Write ‘55h’ to TXREGx to load the Sync the SENDB and TXEN bits (TXSTAx<3> and character into the transmit FIFO buffer. TXSTAx<5>) are set while the Transmit Shift register is 5. After the Break has been sent, the SENDB bit is loaded with data. Note that the value of data written to reset by hardware. The Sync character now TXREGx will be ignored and all ‘0’s will be transmitted. transmits in the preconfigured mode. The SENDB bit is automatically reset by hardware after When the TXREGx becomes empty, as indicated by the corresponding Stop bit is sent. This allows the user the TXxIF, the next data byte can be written to to preload the transmit FIFO with the next transmit byte TXREGx. following the Break character (typically, the Sync character in the LIN specification). 20.2.6 RECEIVING A BREAK CHARACTER Note that the data value written to the TXREGx for the The Enhanced USART module can receive a Break Break character is ignored. The write simply serves the character in two ways. purpose of initiating the proper sequence. The first method forces configuration of the baud rate The TRMT bit indicates when the transmit operation is at a frequency of 9/13 the typical speed. This allows for active or Idle, just as it does during normal transmis- the Stop bit transition to be at the correct sampling loca- sion. See Figure20-10 for the timing of the Break tion (13 bits for Break versus Start bit and 8 data bits for character sequence. typical data). 20.2.5.1 Break and Sync Transmit Sequence The second method uses the auto-wake-up feature described in Section20.2.4 “Auto-Wake-up on Sync The following sequence will send a message frame Break Character”. By enabling this feature, the header made up of a Break, followed by an Auto-Baud EUSART will sample the next two transitions on RXx/ Sync byte. This sequence is typical of a LIN bus DTx, cause an RCxIF interrupt and receive the next master. data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABD bit once the TXxIF interrupt is observed. FIGURE 20-10: SEND BREAK CHARACTER SEQUENCE Write to TXREGx Dummy Write BRG Output (Shift Clock) TXx (pin) Start Bit Bit 0 Bit 1 Bit 11 Stop Bit Break TXxIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB sampled here Auto-Cleared SENDB (Transmit Shift Reg. Empty Flag) © 2008 Microchip Technology Inc. DS39646C-page 263

PIC18F8722 FAMILY 20.3 EUSART Synchronous Once the TXREGx register transfers the data to the Master Mode TSRx register (occurs in one TCY), the TXREGx is empty and the TXxIF flag bit is set. The interrupt can be The Synchronous Master mode is entered by setting enabled or disabled by setting or clearing the interrupt the CSRC bit (TXSTAx<7>). In this mode, the data is enable bit, TXxIE. TXxIF is set regardless of the state transmitted in a half-duplex manner (i.e., transmission of enable bit TXxIE; it cannot be cleared in software. It and reception do not occur at the same time). When will reset only when new data is loaded into the transmitting data, the reception is inhibited and vice TXREGx register. versa. Synchronous mode is entered by setting bit While flag bit TXxIF indicates the status of the TXREGx SYNC (TXSTAx<4>). In addition, enable bit SPEN register, another bit, TRMT (TXSTAx<1>), shows the (RCSTAx<7>) is set in order to configure the TXx and status of the TSRx register. TRMT is a read-only bit RXx pins to CKx (clock) and DTx (data) lines, which is set when the TSRx is empty. No interrupt logic respectively. is tied to this bit, so the user must poll this bit in order to The Master mode indicates that the processor trans- determine if the TSRx register is empty. The TSRx is not mits the master clock on the CKx line. Clock polarity is mapped in data memory so it is not available to the user. selected with the SCKP bit (BAUDCONx<4>); setting To set up a Synchronous Master Transmission: SCKP sets the Idle state on CKx as high, while clearing the bit sets the Idle state as low. This option is provided 1. Initialize the SPBRGHx:SPBRGx registers for the to support Microwire devices with this module. appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. 20.3.1 EUSART SYNCHRONOUS MASTER 2. Enable the synchronous master serial port by TRANSMISSION setting bits SYNC, SPEN and CSRC. The EUSART transmitter block diagram is shown in 3. If interrupts are desired, set enable bit TXxIE. Figure20-3. The heart of the transmitter is the Transmit 4. If 9-bit transmission is desired, set bit TX9. (Serial) Shift Register (TSRx). The Shift register 5. Enable the transmission by setting bit TXEN. obtains its data from the Read/Write Transmit Buffer 6. If 9-bit transmission is selected, the ninth bit register, TXREGx. The TXREGx register is loaded with should be loaded in bit TX9D. data in software. The TSRx register is not loaded until 7. Start transmission by loading data to the the last bit has been transmitted from the previous load. TXREGx register. As soon as the last bit is transmitted, the TSRx is loaded with new data from the TXREGx (if available). 8. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 20-11: SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 DTx bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 CKx pin (SCKP = 0) CKx pin (SCKP = 1) Write to TXREGx Reg Write Word 1 Write Word 2 TXxIF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ ‘1’ Note: Sync Master mode, SPBRGx = 0, continuous transmission of two 8-bit words. DS39646C-page 264 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 20-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) DTx pin bit 0 bit 1 bit 2 bit 6 bit 7 CKx pin Write to TXREGx reg TXxIF bit TRMT bit TXEN bit TABLE 20-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 59 TXREGx EUSARTx Transmit Register 59 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 59 BAUDCONx ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 61 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 61 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 59 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. © 2008 Microchip Technology Inc. DS39646C-page 265

PIC18F8722 FAMILY 20.3.2 EUSART SYNCHRONOUS 3. Ensure bits, CREN and SREN, are clear. MASTER RECEPTION 4. If interrupts are desired, set enable bit, RCxIE. 5. If 9-bit reception is desired, set bit, RX9. Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, 6. If a single reception is required, set bit, SREN. SREN (RCSTAx<5>), or the Continuous Receive For continuous reception, set bit, CREN. Enable bit, CREN (RCSTAx<4>). Data is sampled on 7. Interrupt flag bit, RCxIF, will be set when recep- the RXx pin on the falling edge of the clock. tion is complete and an interrupt will be generated if the enable bit, RCxIE, was set. If enable bit SREN is set, only a single word is received. If enable bit CREN is set, the reception is continuous 8. Read the RCSTAx register to get the 9th bit (if until CREN is cleared. If both bits are set, then CREN enabled) and determine if any error occurred takes precedence. during reception. To set up a Synchronous Master Reception: 9. Read the 8-bit received data by reading the RCREGx register. 1. Initialize the SPBRGHx:SPBRGx registers for the 10. If any error occurred, clear the error by clearing appropriate baud rate. Set or clear the BRG16 bit, CREN. bit, as required, to achieve the desired baud rate. 11. If using interrupts, ensure that the GIE and PEIE bits 2. Enable the synchronous master serial port by in the INTCON register (INTCON<7:6>) are set. setting bits, SYNC, SPEN and CSRC. FIGURE 20-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 DTx pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 CKx pin (SCKP = 0) CKx pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCxIF bit (Interrupt) Read RCREGx Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. DS39646C-page 266 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 20-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 59 RCREGx EUSARTx Receive Register 59 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 59 BAUDCONx ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 61 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 61 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 59 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. © 2008 Microchip Technology Inc. DS39646C-page 267

PIC18F8722 FAMILY 20.4 EUSART Synchronous To set up a Synchronous Slave Transmission: Slave Mode 1. Enable the synchronous slave serial port by setting bits, SYNC and SPEN, and clearing bit, Synchronous Slave mode is entered by clearing bit, CSRC. CSRC (TXSTAx<7>). This mode differs from the 2. Clear bits, CREN and SREN. Synchronous Master mode in that the shift clock is supplied externally at the CKx pin (instead of being 3. If interrupts are desired, set enable bit, TXxIE. supplied internally in Master mode). This allows the 4. If 9-bit transmission is desired, set bit, TX9. device to transfer or receive data while in any low-power 5. Enable the transmission by setting enable bit, mode. TXEN. 6. If 9-bit transmission is selected, the ninth bit 20.4.1 EUSART SYNCHRONOUS should be loaded in bit, TX9D. SLAVE TRANSMISSION 7. Start transmission by loading data to the The operation of the Synchronous Master and Slave TXREGx register. modes is identical, except in the case of Sleep mode. 8. If using interrupts, ensure that the GIE and PEIE If two words are written to the TXREGx and then the bits in the INTCON register (INTCON<7:6>) are SLEEP instruction is executed, the following will occur: set. a) The first word will immediately transfer to the TSRx register and transmit. b) The second word will remain in the TXREGx register. c) Flag bit, TXxIF, will not be set. d) When the first word has been shifted out of TSRx, the TXREGx register will transfer the second word to the TSRx and flag bit, TXxIF, will now be set. e) If enable bit, TXxIE, is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. TABLE 20-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 59 TXREGx EUSARTx Transmit Register 59 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 59 BAUDCONx ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 61 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 61 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 59 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. DS39646C-page 268 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 20.4.2 EUSART SYNCHRONOUS SLAVE To set up a Synchronous Slave Reception: RECEPTION 1. Enable the synchronous master serial port by The operation of the Synchronous Master and Slave setting bits, SYNC and SPEN, and clearing bit, modes is identical, except in the case of Sleep, or any CSRC. Idle mode and bit SREN, which is a “don’t care” in 2. If interrupts are desired, set enable bit, RCxIE. Slave mode. 3. If 9-bit reception is desired, set bit, RX9. If receive is enabled by setting the CREN bit prior to 4. To enable reception, set enable bit, CREN. entering Sleep or any Idle mode, then a word may be 5. Flag bit, RCxIF, will be set when reception is received while in this low-power mode. Once the word complete. An interrupt will be generated if is received, the RSRx register will transfer the data to enable bit, RCxIE, was set. the RCREGx register; if the RCxIE enable bit is set, the 6. Read the RCSTAx register to get the 9th bit (if interrupt generated will wake the chip from the low- enabled) and determine if any error occurred power mode. If the global interrupt is enabled, the during reception. program will branch to the interrupt vector. 7. Read the 8-bit received data by reading the RCREGx register. 8. If any error occurred, clear the error by clearing bit, CREN. 9. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 20-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 59 RCREGx EUSARTx Receive Register 59 TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 59 BAUDCONx ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 61 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 61 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 59 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. © 2008 Microchip Technology Inc. DS39646C-page 269

PIC18F8722 FAMILY NOTES: DS39646C-page 270 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 21.0 10-BIT ANALOG-TO-DIGITAL The ADCON0 register, shown in Register21-1, CONVERTER (A/D) MODULE controls the operation of the A/D module. The ADCON1 register, shown in Register21-2, configures The Analog-to-Digital (A/D) converter module has the functions of the port pins. The ADCON2 register, 12inputs for the 64-pin devices and 16 for the 80-pin shown in Register21-3, configures the A/D clock devices. This module allows conversion of an analog source, programmed acquisition time and justification. input signal to a corresponding 10-bit digital number. The module has five registers: • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) • A/D Control Register 0 (ADCON0) • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) REGISTER 21-1: ADCON0: A/D CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CHS3(1) CHS2(1) CHS1(1) CHS0(1) GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-2 CHS<3:0> Analog Channel Select bits(1) 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5) 0110 = Channel 6 (AN6) 0111 = Channel 7 (AN7) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12)(1) 1101 = Channel 13 (AN13)(1) 1110 = Channel 14 (AN14)(1) 1111 = Channel 15 (AN15)(1) bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress 0 = A/D Idle bit 0 ADON: A/D On bit 1 = A/D converter module is enabled 0 = A/D converter module is disabled Note 1: These channels are not implemented on 64-pin devices. © 2008 Microchip Technology Inc. DS39646C-page 271

PIC18F8722 FAMILY REGISTER 21-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 VCFG<1:0>: Voltage Reference Configuration bits A/D VREF+ A/D VREF- 00 AVDD AVSS 01 External VREF+ AVSS 10 AVDD External VREF- 11 External VREF+ External VREF- bit 3-0 PCFG<3:0>: A/D Port Configuration Control bits: 1) 1) 1) 1) (5 (4 (3 (2 1 0 PCFG<3:0> 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 N N N N N N N N N N N N N N N N A A A A A A A A A A A A A A A A 0000 A A A A A A A A A A A A A A A A 0001 D D A A A A A A A A A A A A A A 0010 D D D A A A A A A A A A A A A A 0011 D D D D A A A A A A A A A A A A 0100 D D D D D A A A A A A A A A A A 0101 D D D D D D A A A A A A A A A A 0110 D D D D D D D A A A A A A A A A 0111 D D D D D D D D A A A A A A A A 1000 D D D D D D D D D A A A A A A A 1001 D D D D D D D D D D A A A A A A 1010 D D D D D D D D D D D A A A A A 1011 D D D D D D D D D D D D A A A A 1100 D D D D D D D D D D D D D A A A 1101 D D D D D D D D D D D D D D A A 1110 D D D D D D D D D D D D D D D A 1111 D D D D D D D D D D D D D D D D A = Analog input D = Digital I/O Note 1: AN15 through AN12 are available only on 80-pin devices. DS39646C-page 272 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY REGISTER 21-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(1) bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(1) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. © 2008 Microchip Technology Inc. DS39646C-page 273

PIC18F8722 FAMILY The analog reference voltage is software selectable to A device Reset forces all registers to their Reset state. either the device’s positive and negative supply voltage This forces the A/D module to be turned off and any (VDD and VSS), or the voltage level on the RA3/AN3/ conversion in progress is aborted. VREF+ and RA2/AN2/VREF- pins. Each port pin associated with the A/D converter can be The A/D converter has a unique feature of being able configured as an analog input, or as a digital I/O. The to operate while the device is in Sleep mode. To oper- ADRESH and ADRESL registers contain the result of ate in Sleep, the A/D conversion clock must be derived the A/D conversion. When the A/D conversion is com- from the A/D’s internal RC oscillator. plete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit (ADCON0 register) is The output of the sample and hold is the input into the cleared and A/D Interrupt Flag bit, ADIF (PIR1<6>), is converter, which generates the result via successive set. The block diagram of the A/D module is shown in approximation. Figure21-1. FIGURE 21-1: A/D BLOCK DIAGRAM CHS<3:0> 1111 AN15(1) 1110 AN14(1) 1101 AN13(1) 1100 AN12(1) 1011 AN11 1010 AN10 1001 AN9 1000 AN8 0111 AN7 0110 AN6 0101 AN5 0100 AN4 VAIN 10-Bit (Input Voltage) 0011 AN3 A/D Converter 0010 AN2 0001 VCFG<1:0> AN1 AVDD 0000 AN0 X0 VREF+ X1 Reference Voltage 1X VREF- 0X AVSS Note 1: Channels AN12 through AN15 are not available on 64-pin devices. 2: I/O pins have diode protection to VDD and VSS. DS39646C-page 274 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY The value in the ADRESH:ADRESL registers is not 5. Wait for A/D conversion to complete, by either: modified for a Power-on Reset. The ADRESH:ADRESL • Polling for the GO/DONE bit to be cleared registers will contain unknown data after a Power-on OR Reset. • Waiting for the A/D interrupt After the A/D module has been configured as desired, 6. Read A/D Result registers (ADRESH:ADRESL); the selected channel must be acquired before the conversion is started. The analog input channels must clear bit ADIF, if required. have their corresponding TRIS bits selected as an 7. For next conversion, go to step 1 or step 2, as input. To determine acquisition time, see Section21.1 required. The A/D conversion time per bit is “A/D Acquisition Requirements”. After this acquisi- defined as TAD. A minimum wait of 2 TAD is tion time has elapsed, the A/D conversion can be required before the next acquisition starts. started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual FIGURE 21-2: A/D TRANSFER FUNCTION start of the conversion. The following steps should be followed to perform an A/D 3FFh conversion: 1. Configure the A/D module: 3FEh • Configure analog pins, voltage reference and put ut digital I/O (ADCON1) O e • Select A/D input channel (ADCON0) od C • Select A/D acquisition time (ADCON2) al 003h git • Select A/D conversion clock (ADCON2) Di 002h • Turn on A/D module (ADCON0) 2. Configure A/D interrupt (if desired): 001h • Clear ADIF bit • Set ADIE bit 000h B B B B B B B B B B • Set GIE bit S S S S S S S S S S L L L L L L L L L L 34.. WStaaritt tchoen rveeqrsuiiorend: acquisition time (if required). 0.5 1 1.5 2 2.5 3 1022 1022.5 1023 1023.5 Analog Input Voltage • Set GO/DONE bit (ADCON0 register) FIGURE 21-3: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V Rs ANx RIC ≤ 1k SS RSS VAIN C5 PpIFN VT = 0.6V I±L E1A0K0A nGAE CHOLD = 25 pF VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage 6V ILEAKAGE = Leakage Current at the pin due to 5V various junctions VDD 4V 3V RIC = Interconnect Resistance 2V SS = Sampling Switch CHOLD = Sample/Hold Capacitance (from DAC) 1 2 3 4 RSS = Sampling Switch Resistance SamplingSwitch(kΩ) © 2008 Microchip Technology Inc. DS39646C-page 275

PIC18F8722 FAMILY 21.1 A/D Acquisition Requirements To calculate the minimum acquisition time, Equation21-1 may be used. This equation assumes For the A/D converter to meet its specified accuracy, that 1/2 LSb error is used (1024 steps for the A/D). The the charge holding capacitor (CHOLD) must be allowed 1/2 LSb error is the maximum error allowed for the A/D to fully charge to the input channel voltage level. The to meet its specified resolution. analog input model is shown in Figure21-3. The Example21-3 shows the calculation of the minimum source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required acquisition time TACQ. This calculation is based on the following application system required to charge the capacitor CHOLD. The sampling assumptions: switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage CHOLD = 25 pF at the analog input (due to pin leakage current). The Rs = 2.5 kΩ maximum recommended impedance for analog Conversion Error ≤ 1/2 LSb sources is 2.5 kΩ. After the analog input channel is VDD = 5V → Rss = 2 kΩ selected (changed), the channel must be sampled for Temperature = 85°C (system max.) at least the minimum acquisition time before starting a conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. EQUATION 21-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 21-2: A/D MINIMUM CHARGING TIME VHOLD = (VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))) or TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) EQUATION 21-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF TAMP = 0.2 μs TCOFF = (Temp – 25°C)(0.02 μs/°C) (85°C – 25°C)(0.02 μs/°C) 1.2 μs Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms. TC = -(CHOLD)(RIC + RSS + RS) ln(1/2047) μs -(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883) μs 1.05 μs TACQ = 0.2 μs + 1 μs + 1.2 μs 2.4 μs DS39646C-page 276 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 21.2 Selecting and Configuring 21.3 Selecting the A/D Conversion Acquisition Time Clock The ADCON2 register allows the user to select an The A/D conversion time per bit is defined as TAD. The acquisition time that occurs each time the GO/DONE A/D conversion requires 11 TAD per 10-bit conversion. bit is set. It also gives users the option to use an The source of the A/D conversion clock is software automatically determined acquisition time. selectable. There are seven possible options for TAD: Acquisition time may be set with the ACQT<2:0> bits • 2 TOSC (ADCON2<5:3>) which provides a range of 2 to 20TAD. • 4 TOSC When the GO/DONE bit is set, the A/D module • 8 TOSC continues to sample the input for the selected acquisi- • 16 TOSC tion time, then automatically begins a conversion. • 32 TOSC Since the acquisition time is programmed, there may • 64 TOSC be no need to wait for an acquisition time between • Internal RC Oscillator selecting a channel and setting the GO/DONE bit. For correct A/D conversions, the A/D conversion clock Manual acquisition is selected when (TAD) must be as short as possible, but greater than the ACQT<2:0>=000. When the GO/DONE bit is set, minimum TAD (see parameter 130, Table28-27 for sampling is stopped and a conversion begins. The user more information). is responsible for ensuring the required acquisition time has passed between selecting the desired input Table21-1 shows the resultant TAD times derived from channel and setting the GO/DONE bit. This option is the device operating frequencies and the A/D clock also the default Reset state of the ACQT<2:0> bits and source selected. is compatible with devices that do not offer programmable acquisition times. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. TABLE 21-1: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Maximum Device Frequency Operation ADCS<2:0> PIC18FXXXX PIC18LFXXXX(4) 2 TOSC 000 2.86 MHz 1.43 kHz 4 TOSC 100 5.71 MHz 2.86 MHz 8 TOSC 001 11.43 MHz 5.72 MHz 16 TOSC 101 22.86 MHz 11.43 MHz 32 TOSC 010 40.0 MHz 22.86 MHz 64 TOSC 110 40.0 MHz 22.86 MHz RC(3) x11 1.00 MHz(1) 1.00 MHz(2) Note 1: The RC source has a typical TAD time of 1.2 μs. 2: The RC source has a typical TAD time of 2.5 μs. 3: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D accuracy may be out of specification. 4: Low-power (PIC18LFXXXX) devices only. © 2008 Microchip Technology Inc. DS39646C-page 277

PIC18F8722 FAMILY 21.4 Operation in Power-Managed 21.5 Configuring Analog Port Pins Modes The ADCON1, TRISA, TRISF and TRISH registers all The selection of the automatic acquisition time and A/D configure the A/D port pins. The port pins needed as conversion clock is determined in part by the clock analog inputs must have their corresponding TRIS bits source and frequency while in a power-managed mode. set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. If the A/D is expected to operate while the device is in a power-managed mode, the ACQT<2:0> and The A/D operation is independent of the state of the ADCS<2:0> bits in ADCON2 should be updated in CHS<3:0> bits and the TRIS bits. accordance with the clock source to be used in that Note1: When reading the Port register, all pins mode. After entering the mode, an A/D acquisition or configured as analog input channels will conversion may be started. Once started, the device read as cleared (a low level). Pins con- should continue to be clocked by the same clock figured as digital inputs will convert as source until the conversion has been completed. analog inputs. Analog levels on a digitally If desired, the device may be placed into the configured input will be accurately corresponding Idle mode during the conversion. If the converted. device clock frequency is less than 1MHz, the A/D RC 2: Analog levels on any pin defined as a clock source should be selected. digital input may cause the digital input Operation in the Sleep mode requires the A/D FRC buffer to consume current out of the clock to be selected. If bits ACQT<2:0> are set to ‘000’ device’s specification limits. and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the SLEEP instruction and entry to Sleep mode. The IDLEN bit (OSCCON<7>) must have already been cleared prior to starting the conversion. DS39646C-page 278 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 21.6 A/D Conversions After the A/D conversion is completed or aborted, a 2TAD wait is required before the next acquisition can Figure21-4 shows the operation of the A/D converter be started. After this wait, acquisition on the selected after the GO/DONE bit has been set and the channel is automatically started. ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into Sleep Note: The GO/DONE bit should NOT be set in mode before the conversion begins. the same instruction that turns on the A/D. Figure21-5 shows the operation of the A/D converter 21.7 Discharge after the GO/DONE bit has been set, the ACQT<2:0> bits are set to ‘010’ and a 4 TAD acquisition time is The discharge phase is used to initialize the value of selected before the conversion starts. the capacitor array. The array is discharged before Clearing the GO/DONE bit during a conversion will abort every sample. This feature helps to optimize the unity- the current conversion. The A/D Result register pair will gain amplifier, as the circuit always needs to charge the NOT be updated with the partially completed A/D capacitor array, rather than charge/discharge based on conversion sample. This means the ADRESH:ADRESL previous measure values. registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). FIGURE 21-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY - TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 TAD1 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Discharge Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit On the following cycle: ADRESH:ADRESL are loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. FIGURE 21-5: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) TACQT Cycles TAD Cycles 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 TAD1 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Automatic Acquisition Conversion starts Discharge Time (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues On the following cycle: acquiring input) ADRESH:ADRESL are loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. © 2008 Microchip Technology Inc. DS39646C-page 279

PIC18F8722 FAMILY 21.8 Use of the ECCP2 Trigger (moving ADRESH:ADRESL to the desired location). The appropriate analog input channel must be selected An A/D conversion can be started by the Special Event and the minimum acquisition period is either timed by Trigger of the ECCP2 module. This requires that the the user, or an appropriate TACQ time selected before CCP2M<3:0> bits (CCP2CON<3:0>) be programmed the Special Event Trigger sets the GO/DONE bit (starts as ‘1011’ and that the A/D module is enabled (ADON a conversion). bit is set). When the trigger occurs, the GO/DONE bit If the A/D module is not enabled (ADON is cleared), the will be set, starting the A/D acquisition and conversion Special Event Trigger will be ignored by the A/D module and the Timer1 (or Timer3) counter will be reset to zero. but will still reset the Timer1 (or Timer3) counter. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal software overhead TABLE 21-2: REGISTERS ASSOCIATED WITH A/D OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 PIR2 OSCFIF CMIF — EEIF BCL1IF HLVDIF TMR3IF CCP2IF 60 PIE2 OSCFIE CMIE — EEIE BCL1IE HLVDIE TMR3IE CCP2IE 60 IPR2 OSCFIP CMIP — EEIP BCL1IP HLVDIP TMR3IP CCP2IP 60 ADRESH A/D Result Register High Byte 59 ADRESL A/D Result Register Low Byte 59 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 59 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 59 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 59 TRISA TRISA7(1) TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 60 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 60 TRISH(2) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 60 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 2: These registers are not implemented on 64-pin devices. DS39646C-page 280 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 22.0 COMPARATOR MODULE The CMCON register (Register22-1) selects the comparator input and output configuration. Block The analog comparator module contains two diagrams of the various comparator configurations are comparators that can be configured in a variety of shown in Figure22-1. ways. The inputs can be selected from the analog inputs multiplexed with pins RF3 through RF6, as well as the on-chip voltage reference (see Section23.0 “Comparator Voltage Reference Module”). The digital outputs (normal or inverted) are available on RF1 and RF2 and can also be read through the control register. REGISTER 22-1: CMCON: COMPARATOR MODULE CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN- 0 = C2 VIN+ < C2 VIN- When C2INV = 1: 1 = C2 VIN+ < C2 VIN- 0 = C2 VIN+ > C2 VIN- bit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN- 0 = C1 VIN+ < C1 VIN- When C1INV = 1: 1 = C1 VIN+ < C1 VIN- 0 = C1 VIN+ > C1 VIN- bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted bit 4 C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted bit 3 CIS: Comparator Input Switch bit When CM2:CM0 = 110: 1 = C1 VIN- connects to RF5/AN10/CVREF C2 VIN- connects to RF3/AN8 0 = C1 VIN- connects to RF6/AN11 C2 VIN- connects to RF4/AN9 bit 2-0 CM<2:0>: Comparator mode bits Figure22-1 shows the Comparator modes and the CM2:CM0 bit settings. © 2008 Microchip Technology Inc. DS39646C-page 281

PIC18F8722 FAMILY 22.1 Comparator Configuration mode is changed, the comparator output level may not be valid for the specified mode change delay shown in There are eight modes of operation for the compara- Section28.0 “Electrical Characteristics”. tors, shown in Figure22-1. Bits CM<2:0> of the CMCON register are used to select these modes. The Note: Comparator interrupts should be disabled TRISF register controls the data direction of the during a Comparator mode change; comparator pins for each mode. If the Comparator otherwise, a false interrupt may occur. FIGURE 22-1: COMPARATOR I/O OPERATING MODES Comparators Reset Comparators Off (POR Default Value) CM<2:0> = 000 CM<2:0> = 111 RF6/AN11 A VIN- RF6/AN11 D VIN- A VIN+ C1 Off (Read as ‘0’) RF5/AN10/ D VIN+ C1 Off (Read as ‘0’) RF5/AN10/ CVREF CVREF RF4/AN9 A VIN- RF4/AN9 D VIN- RF3/AN8 A VIN+ C2 Off (Read as ‘0’) RF3/AN8 D VIN+ C2 Off (Read as ‘0’) Two Independent Comparators Two Independent Comparators with Outputs CM<2:0> = 010 CM<2:0> = 011 RF6/AN11 A VIN- RF6/AN11 A VIN- RF5/AN10/ A VIN+ C1 C1OUT RF5/AN10 A VIN+ C1 C1OUT CVREF RF2/AN7/C1OUT* RF4/AN9 A VIN- RF3/AN8 A VIN+ C2 C2OUT RF4/AN9 A VIN- RF3/AN8 A VIN+ C2 C2OUT RF1/AN6/C2OUT* Two Common Reference Comparators Two Common Reference Comparators with Outputs CM<2:0> = 100 CM<2:0> = 101 RF6/AN11 A VIN- RF6/AN11 A VIN- RF5/AN10/ A VIN+ C1 C1OUT RF5/AN10/ A VIN+ C1 C1OUT CVREF CVREF RF2/AN7/ C1OUT* RF4/AN9 A VIN- RF3/AN8 D VIN+ C2 C2OUT RF4/AN9 A VIN- RF3/AN8 D VIN+ C2 C2OUT RF1/AN6/C2OUT* One Independent Comparator with Output Four Inputs Multiplexed to Two Comparators CM<2:0> = 001 CM<2:0> = 110 RF6/AN11 A VIN- RF6/AN11 A CIS = 0 VIN- RCFV5R/EAFN10/ A VIN+ C1 C1OUT RCFV5R/EAFN10/ A CIS = 1 VIN+ C1 C1OUT RF2/AN7/ RF4/AN9 A C1OUT* CIS = 0 VIN- RF4/AN9 D VIN- RF3/AN8 A CIS = 1 VIN+ C2 C2OUT RF3/AN8 D VIN+ C2 Off (Read as ‘0’) CVREF From VREF Module A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch * Setting the TRISF<2:1> bits will disable the comparator outputs by configuring the pins as inputs. DS39646C-page 282 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 22.2 Comparator Operation 22.3.2 INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure22-2, along with The comparator module also allows the selection of an the relationship between the analog input levels and internally generated voltage reference from the the digital output. When the analog input at VIN+ is less comparator voltage reference module. This module is than the analog input VIN-, the output of the comparator described in more detail in Section23.0 “Comparator is a digital low level. When the analog input at VIN+ is Voltage Reference Module”. greater than the analog input VIN-, the output of the The internal reference is only available in the mode comparator is a digital high level. The shaded areas of where four inputs are multiplexed to two comparators the output of the comparator in Figure22-2 represent (CM<2:0>=110). In this mode, the internal voltage the uncertainty, due to input offsets and response time. reference is applied to the VIN+ pin of both comparators. 22.3 Comparator Reference 22.4 Comparator Response Time Depending on the comparator operating mode, either an external or internal voltage reference may be used. Response time is the minimum time, after selecting a The analog signal present at VIN- is compared to the new reference voltage or input source, before the signal at VIN+ and the digital output of the comparator comparator output has a valid level. If the internal is adjusted accordingly (Figure22-2). reference is changed, the maximum delay of the internal voltage reference must be considered when FIGURE 22-2: SINGLE COMPARATOR using the comparator outputs. Otherwise, the maximum delay of the comparators should be used (see Section28.0 “Electrical Characteristics”). VIN+ + 22.5 Comparator Outputs Output VIN- – The comparator outputs are read through the CMCON register. These bits are read-only. The comparator outputs may also be directly output to the RF1 and RF2 I/O pins. When enabled, multiplexors in the output path of the RF1 and RF2 pins will switch and the output of each pin will be the unsynchronized output of the VIN- comparator. The uncertainty of each of the comparators is related to the input offset voltage and VIN+ the response time given in the specifications. Figure22-3 shows the comparator output block diagram. Output The TRISF bits will still function as an output enable/ disable for the RF1 and RF2 pins while in this mode. The polarity of the comparator outputs can be changed 22.3.1 EXTERNAL REFERENCE SIGNAL using the C2INV and C1INV bits (CMCON<5:4>). When external voltage references are used, the Note1: When reading the PORT register, all pins comparator module can be configured to have the com- configured as analog inputs will read as a parators operate from the same or different reference ‘0’. Pins configured as digital inputs will sources. However, threshold detector applications may convert an analog input according to the require the same reference. The reference signal must Schmitt Trigger input specification. be between VSS and VDD and can be applied to either 2: Analog levels on any pin defined as a pin of the comparator(s). digital input may cause the input buffer to consume more current than is specified. © 2008 Microchip Technology Inc. DS39646C-page 283

PIC18F8722 FAMILY FIGURE 22-3: COMPARATOR OUTPUT BLOCK DIAGRAM X E L + Port pins P TI CxOUT UL - M D Q Bus CxINV Data Read CMCON EN D Q Set CMIF bit EN CL From Other Reset Comparator 22.6 Comparator Interrupts 22.7 Comparator Operation During Sleep The comparator interrupt flag is set whenever there is a change in the output value of either comparator. When a comparator is active and the device is placed Software will need to maintain information about the in Sleep mode, the comparator remains active and the status of the output bits, as read from CMCON<7:6>, to interrupt is functional if enabled. This interrupt will determine the actual change that occurred. The CMIF wake-up the device from Sleep mode, when enabled. bit (PIR2<6>) is the Comparator Interrupt Flag. The Each operational comparator will consume additional CMIF bit must be reset by clearing it. Since it is also current, as shown in the comparator specifications. To possible to write a ‘1’ to this register, a simulated minimize power consumption while in Sleep mode, turn interrupt may be initiated. off the comparators (CM<2:0>=111) before entering Both the CMIE bit (PIE2<6>) and the PEIE bit Sleep. If the device wakes up from Sleep, the contents (INTCON<6>) must be set to enable the interrupt. In of the CMCON register are not affected. addition, the GIE bit (INTCON<7>) must also be set. If 22.8 Effects of a Reset any of these bits are clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt A device Reset forces the CMCON register to its Reset condition occurs. state, causing the comparator modules to be turned off Note: If a change in the CMCON register (CM<2:0>=111). However, the input pins (RF3 (C1OUT or C2OUT) should occur when a through RF6) are configured as analog inputs by read operation is being executed (start of default on device Reset. The I/O configuration for these the Q2 cycle), then the CMIF (PIR2 pins is also determined by the setting of the register) interrupt flag may not get set. PCFG<3:0> bits (ADCON1<3:0>). Therefore, device current is minimized when analog inputs are present at The user, in the Interrupt Service Routine, can clear the Reset time. interrupt in the following manner: a) Any read or write of CMCON will end the mismatch condition. b) Clear flag bit, CMIF. A mismatch condition will continue to set flag bit, CMIF. Reading CMCON will end the mismatch condition and allow flag bit, CMIF, to be cleared. DS39646C-page 284 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 22.9 Analog Input Connection range by more than 0.6V in either direction, one of the Considerations diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10kΩ is A simplified circuit for an analog input is shown in recommended for the analog sources. Any external Figure22-4. Since the analog pins are connected to a component connected to an analog input pin, such as digital output, they have reverse biased diodes to VDD a capacitor or a Zener diode, should have very little and VSS. The analog input, therefore, must be between leakage current. VSS and VDD. If the input voltage deviates from this FIGURE 22-4: COMPARATOR ANALOG INPUT MODEL VDD RS < 10k VT = 0.6V RIC Comparator AIN Input VA C5 PpIFN VT = 0.6V I±L5E0A0K AnGAE VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage TABLE 22-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 59 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 59 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 60 PIR2 OSCFIF CMIF — EEIF BCL1IF HLVDIF TMR3IF CCP2IF 60 PIE2 OSCFIE CMIE — EEIE BCL1IE HLVDIE TMR3IE CCP2IE 60 IPR2 OSCFIP CMIP — EEIP BCL1IP HLVDIP TMR3IP CCP2IP 60 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 60 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. © 2008 Microchip Technology Inc. DS39646C-page 285

PIC18F8722 FAMILY NOTES: DS39646C-page 286 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 23.0 COMPARATOR VOLTAGE primary difference between the ranges is the size of the REFERENCE MODULE steps selected by the CVREF Selection bits (CVR<3:0>), with one range offering finer resolution. The comparator voltage reference is a 16-tap resistor The equations used to calculate the output of the ladder network that provides a selectable reference comparator voltage reference are as follows: voltage. Although its primary purpose is to provide a If CVRR = 1: reference for the analog comparators, it may also be CVREF = ((CVR3:CVR0)/24) x (CVRSRC) used independently of them. If CVRR = 0: A block diagram of the module is shown in Figure23-1. CVREF=(CVRSRC/4)+((CVR3:CVR0)/32)x The resistor ladder is segmented to provide two ranges (CVRSRC) of CVREF values and has a power-down function to The comparator reference supply voltage can come conserve power when the reference is not being used. The module’s supply reference can be provided from from either VDD and VSS, or the external VREF+ and either device VDD/VSS or an external voltage reference. VREF- that are multiplexed with RA2 and RA3. The voltage source is selected by the CVRSS bit (CVRCON<4>). 23.1 Configuring the Comparator Voltage Reference The settling time of the comparator voltage reference must be considered when changing the CVREF The voltage reference module is controlled through the output (see Table28-3 in Section28.0 “Electrical CVRCON register (Register23-1). The comparator Characteristics”). voltage reference provides two ranges of output voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON<5>). The REGISTER 23-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit(1) 1 = CVREF voltage level is also output on the RF5/AN10/CVREF pin 0 = CVREF voltage is disconnected from the RF5/AN10/CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range) 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range) bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-) 0 = Comparator reference source, CVRSRC = AVDD – AVSS bit 3-0 CVR<3:0>: Comparator VREF Value Selection bits (0 ≤ (CVR<3:0>) ≤ 15) When CVRR = 1: CVREF = ((CVR<3:0>)/24) x (CVRSRC) When CVRR = 0: CVREF = (CVRSRC/4) + ((CVR<3:0>)/32) x (CVRSRC) Note 1: CVROE overrides the TRISF<5> bit setting. © 2008 Microchip Technology Inc. DS39646C-page 287

PIC18F8722 FAMILY FIGURE 23-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 VREF+ AVDD CVRSS = 0 8R CVR<3:0> R CVREN R R R X U M 16 Steps 1 CVREF o- 6-t 1 R R R CVRR 8R CVRSS = 1 VREF- CVRSS = 0 AVSS 23.2 Voltage Reference Accuracy/Error 23.4 Effects of a Reset The full range of voltage reference cannot be realized A device Reset disables the voltage reference by due to the construction of the module. The transistors clearing bit, CVREN (CVRCON<7>). This Reset also on the top and bottom of the resistor ladder network disconnects the reference from the RF5 pin by clearing (Figure23-1) keep CVREF from approaching the refer- bit, CVROE (CVRCON<6>), and selects the high- ence source rails. The voltage reference is derived voltage range by clearing bit, CVRR (CVRCON<5>). from the reference source; therefore, the CVREF output The CVR value select bits are also cleared. changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be 23.5 Connection Considerations found in Section28.0 “Electrical Characteristics”. The voltage reference module operates independently 23.3 Operation During Sleep of the comparator module. The output of the reference generator may be connected to the RF5 pin if the When the device wakes up from Sleep through an CVROE bit is set. Enabling the voltage reference out- interrupt or a Watchdog Timer time-out, the contents of put onto RF5 when it is configured as a digital input will the CVRCON register are not affected. To minimize increase current consumption. Connecting RF5 as a current consumption in Sleep mode, the voltage digital output with CVRSS enabled will also increase reference should be disabled. current consumption. The RF5 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to VREF. Figure23-2 shows an example buffering technique. DS39646C-page 288 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 23-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18FXXXX CVREF R(1) Module + Voltage RF5 – CVREF Output Reference Output Impedance Note 1: R is dependent upon the voltage reference Configuration bits, CVRCON<3:0> and CVRCON<5>. TABLE 23-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 59 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 59 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 60 Legend: Shaded cells are not used with the comparator voltage reference. © 2008 Microchip Technology Inc. DS39646C-page 289

PIC18F8722 FAMILY NOTES: DS39646C-page 290 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 24.0 HIGH/LOW-VOLTAGE DETECT The High/Low-Voltage Detect Control register (HLVD) (Register24-1) completely controls the operation of the HLVD module. This allows the circuitry to be “turned The PIC18F8722 family of devices have a off” by the user under software control, which High/Low-Voltage Detect module (HLVD). This is a pro- minimizes the current consumption for the device. grammable circuit that allows the user to specify both a The block diagram for the HLVD module is shown in device voltage trip point and the direction of change from Figure24-1. that point. If the device experiences an excursion past the trip point in that direction, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. REGISTER 24-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 VDIRMAG — IRVST HLVDEN HLVDL3(1) HLVDL2(1) HLVDL1(1) HLVDL0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 VDIRMAG: Voltage Direction Magnitude Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>) 0 = Event occurs when voltage equals or falls below trip point (HLVDL<3:0>) bit 6 Unimplemented: Read as ‘0’ bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage range and the HLVD interrupt should not be enabled bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD enabled 0 = HLVD disabled bit 3-0 HLVDL<3:0>: Voltage Detection Limit bits(1) 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = Maximum setting . . . 0000 = Minimum setting Note 1: See Table28-4 for specifications. © 2008 Microchip Technology Inc. DS39646C-page 291

PIC18F8722 FAMILY The module is enabled by setting the HLVDEN bit. event, depending on the configuration of the module. Each time that the HLVD module is enabled, the When the supply voltage is equal to the trip point, the circuitry requires some time to stabilize. The IRVST bit voltage tapped off of the resistor array is equal to the is a read-only bit and is used to indicate when the circuit internal reference voltage generated by the voltage is stable. The module can only generate an interrupt reference module. The comparator then generates an after the circuit is stable and IRVST is set. interrupt signal by setting the HLVDIF bit. The VDIRMAG bit determines the overall operation of The trip point voltage is software programmable to any one the module. When VDIRMAG is cleared, the module of 16 values. The trip point is selected by programming the monitors for drops in VDD below a predetermined set HLVDL<3:0> bits (HLVDCON<3:0>). point. When the bit is set, the module monitors for rises The HLVD module has an additional feature that allows in VDD above the set point. the user to supply the trip voltage to the module from an external source. This mode is enabled when bits 24.1 Operation HLVDL<3:0> are set to ‘1111’. In this state, the comparator input is multiplexed from the external input When the HLVD module is enabled, a comparator uses pin, HLVDIN. This gives users flexibility because it an internally generated reference voltage as the set allows them to configure the High/Low-Voltage Detect point. The set point is compared with the trip point, interrupt to occur at any voltage in the valid operating where each node in the resistor divider represents a range. trip point voltage. The “trip point” voltage is the voltage level at which the device detects a high or low-voltage FIGURE 24-1: HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT) Externally Generated Trip Point VDD VDD HLVDL<3:0> HLVDCON Register HLVDEN VDIRMAG HLVDIN X Set U M HLVDIF 1 o- 6-t 1 HLVDEN Internal Voltage BOREN Reference 1.2V Typical DS39646C-page 292 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 24.2 HLVD Setup Depending on the application, the HLVD module does not need to be operating constantly. To decrease the The following steps are needed to set up the HLVD current requirements, the HLVD circuitry may only module: need to be enabled for short periods where the voltage 1. Write the value to the HLVDL<3:0> bits that is checked. After doing the check, the HLVD module selects the desired HLVD trip point. may be disabled. 2. Set the VDIRMAG bit to detect high voltage (VDIRMAG = 1) or low voltage (VDIRMAG = 0). 24.4 HLVD Start-up Time 3. Enable the HLVD module by setting the The internal reference voltage of the HLVD module, HLVDEN bit. specified in electrical specification parameter D420 4. Clear the HLVD interrupt flag (PIR2<2>), which (Section 28.2 “DC Characteristics”), may be used may have been set from a previous interrupt. by other internal circuitry, such as the Programmable 5. Enable the HLVD interrupt if interrupts are Brown-out Reset. If the HLVD or other circuits using the desired by setting the HLVDIE and GIE bits voltage reference are disabled to lower the device’s (PIE2<2> and INTCON<7>). An interrupt will not current consumption, the reference voltage circuit will be generated until the IRVST bit is set. require time to become stable before a low or high-voltage condition can be reliably detected. This 24.3 Current Consumption start-up time, TIRVST, is an interval that is independent of device clock speed. It is specified in electrical When the module is enabled, the HLVD comparator specification parameter 36 (Table28-12). and voltage divider are enabled and will consume static The HLVD interrupt flag is not enabled until TIRVST has current. The total current consumption, when enabled, expired and a stable reference voltage is reached. For is specified in electrical specification parameter D022B this reason, brief excursions beyond the set point may (Section 28.2 “DC Characteristics”). not be detected during this interval. Refer to Figure24-2 or Figure24-3. FIGURE 24-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0) CASE 1: HLVDIF may not be set VDD VHLVD HLVDIF Enable HLVD TIRVST IRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VDD VHLVD HLVDIF Enable HLVD IRVST TIRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists © 2008 Microchip Technology Inc. DS39646C-page 293

PIC18F8722 FAMILY FIGURE 24-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: HLVDIF may not be set VHLVD VDD HLVDIF Enable HLVD IRVST TIRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VHLVD VDD HLVDIF Enable HLVD IRVST TIRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists 24.5 Applications FIGURE 24-4: TYPICAL LOW-VOLTAGE DETECT APPLICATION In many applications, the ability to detect a drop below or rise above a particular threshold is desirable. For example, the HLVD module could be periodically enabled to detect Universal Serial Bus (USB) attach or detach. This assumes the device is powered by a lower voltage source than the USB when detached. An attach VA would indicate a high-voltage detect from, for example, VB 3.3V to 5V (the voltage on USB) and vice versa for a e g detach. This feature could save a design a few extra a components and an attach signal (input pin). olt V For general battery applications, Figure24-4 shows a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage VA, the HLVD logic generates an interrupt at time TA. The interrupt could cause the execution of an ISR, Time TA TB which would allow the application to perform “house- keeping tasks” and perform a controlled shutdown Legend: VA = HLVD trip point before the device voltage exits the valid operating VB = Minimum valid device range at TB. The HLVD, thus, would give the applica- operating voltage tion a time window, represented by the difference between TA and TB, to safely exit. DS39646C-page 294 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 24.6 Operation During Sleep 24.7 Effects of a Reset When enabled, the HLVD circuitry continues to operate A device Reset forces all registers to their Reset state. during Sleep. If the device voltage crosses the trip This forces the HLVD module to be turned off. point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. TABLE 24-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 58 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR2 OSCFIF CMIF — EEIF BCL1IF HLVDIF TMR3IF CCP2IF 60 PIE2 OSCFIE CMIE — EEIE BCL1IE HLVDIE TMR3IE CCP2IE 60 IPR2 OSCFIP CMIP — EEIP BCL1IP HLVDIP TMR3IP CCP2IP 60 TRISA TRISA7(1) TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 60 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2008 Microchip Technology Inc. DS39646C-page 295

PIC18F8722 FAMILY NOTES: DS39646C-page 296 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 25.0 SPECIAL FEATURES OF THE 25.1 Configuration Bits CPU The Configuration bits can be programmed (read as ‘0’) or left unprogrammed (read as ‘1’) to select various The PIC18F8722 family of devices include several fea- device Configurations. These bits are mapped starting tures intended to maximize reliability and minimize cost at program memory location 300000h. through elimination of external components. These are: The user will note that address 300000h is beyond the • Oscillator Selection user program memory space. In fact, it belongs to the • Resets: configuration memory space (300000h-3FFFFFh), - Power-on Reset (POR) which can only be accessed using table reads and - Power-up Timer (PWRT) table writes. - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) Programming the Configuration registers is done in a manner similar to programming the Flash memory. The • Interrupts WR bit in the EECON1 register starts a self-timed write • Watchdog Timer (WDT) to the Configuration register. In normal operation mode, • Fail-Safe Clock Monitor a TBLWT instruction with the TBLPTR pointing to the • Two-Speed Start-up Configuration register sets up the address and the data • Code Protection for the Configuration register write. Setting the WR bit • ID Locations starts a long write to the Configuration register. The • In-Circuit Serial Programming Configuration registers are written a byte at a time. To The oscillator can be configured for the application write or erase a configuration cell, a TBLWT instruction depending on frequency, power, accuracy and cost. All can write a ‘1’ or a ‘0’ into the cell. For additional details of the options are discussed in detail in Section2.0 on Flash programming, refer to Section6.5 “Writing “Oscillator Configurations”. to Flash Program Memory”. A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up Timers provided for Resets, the PIC18F8722 family of devices has a Watchdog Timer, which is either perma- nently enabled via the Configuration bits or software controlled (if configured as disabled). The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. Two- Speed Start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. All of these features are enabled and configured by setting the appropriate Configuration register bits. © 2008 Microchip Technology Inc. DS39646C-page 297

PIC18F8722 FAMILY TABLE 25-1: CONFIGURATION BITS AND DEVICE IDs Default/ File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed Value 300001h CONFIG1H IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 00-- 0111 300002h CONFIG2L — — — BORV1 BORV0 BOREN1 BOREN0 PWRTEN ---1 1111 300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111 300004h CONFIG3L(5) WAIT BW ABW1 ABW0 — — PM1 PM0 1111 --11 300005h CONFIG3H MCLRE — — — — LPT1OSC ECCPMX(5) CCP2MX 1--- -011 300006h CONFIG4L DEBUG XINST BBSIZ1 BBSIZ0 — LVP — STVREN 1000 -1-1 300008h CONFIG5L CP7(1) CP6(1) CP5(2) CP4(2) CP3(3) CP2 CP1 CP0 1111 1111 300009h CONFIG5H CPD CPB — — — — — — 11-- ---- 30000Ah CONFIG6L WRT7(1) WRT6(1) WRT5(2) WRT4(2) WRT3(3) WRT2 WRT1 WRT0 1111 1111 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ---- 30000Ch CONFIG7L EBRT7(1) EBRT6(1) EBTR5(2) EBTR4(2) EBTR3(3) EBTR2 EBTR1 EBTR0 1111 1111 30000Dh CONFIG7H — EBTRB — — — — — — -1-- ---- 3FFFFEh DEVID1(4) DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx 3FFFFFh DEVID2(4) DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 xxxx xxxx Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’. Note 1: Unimplemented in PIC18F6527/6622/6627/8527/8622/8627 devices. 2: Unimplemented in PIC18F6527/6622/8527/8622 devices. 3: Unimplemented in PIC18F6527/8527 devices. 4: See Register25-13 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user. 5: Unimplemented in PIC18F6527/6622/6627/6722 devices. DS39646C-page 298 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY REGISTER 25-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-0 R/P-0 U-0 U-0 R/P-0 R/P-1 R/P-1 R/P-1 IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Two-Speed Start-up enabled 0 = Two-Speed Start-up disabled bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 FOSC<3:0>: Oscillator Selection bits 11xx = External RC oscillator, CLKO function on RA6 101x = External RC oscillator, CLKO function on RA6 1001 = Internal oscillator block, CLKO function on RA6, port function on RA7 1000 = Internal oscillator block, port function on RA6 and RA7 0111 = External RC oscillator, port function on RA6 0110 = HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) 0101 = EC oscillator, port function on RA6 0100 = EC oscillator, CLKO function on RA6 0011 = External RC oscillator, CLKO function on RA6 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator © 2008 Microchip Technology Inc. DS39646C-page 299

PIC18F8722 FAMILY REGISTER 25-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — BORV1(1) BORV0(1) BOREN1(2) BOREN0(2) PWRTEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-3 BORV<1:0>: Brown-out Reset Voltage bits(1) 11 = Minimum setting . . . 00 = Maximum setting bit 2-1 BOREN<1:0>: Brown-out Reset Enable bits(2) 11 = Brown-out Reset enabled in hardware only (SBOREN is disabled) 10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) 01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled) 00 = Brown-out Reset disabled in hardware and software bit 0 PWRTEN: Power-up Timer Enable bit(2) 1 = PWRT disabled 0 = PWRT enabled Note 1: See Section28.1 “DC Characteristics: Supply Voltage” for specifications. 2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently con- trolled. DS39646C-page 300 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY REGISTER 25-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) © 2008 Microchip Technology Inc. DS39646C-page 301

PIC18F8722 FAMILY REGISTER 25-4: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)(1) R/P-1 R/P-1 R/P-1 R/P-1 U-0 U-0 R/P-1 R/P-1 WAIT BW ABW1 ABW0 — — PM1 PM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WAIT: External Bus Data Wait Enable bit 1 = Wait selections are unavailable for table reads and table writes 0 = Wait selections for table reads and table writes are determined by the WAIT<1:0> bits bit 6 BW: Data Bus Width Select bit 1 = 16-bit External Bus mode 0 = 8-bit External Bus mode bit 5-4 ABW<1:0>: Address Bus Width Select bits 11 = 20-bit address bus 10 = 16-bit address bus 01 = 12-bit address bus 00 = 8-bit address bus bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 PM<1:0>: Processor Data Memory Mode Select bits 11 = Microcontroller mode 10 = Microprocessor mode 01 = Microprocessor with Boot Block mode 00 = Extended Microcontroller mode Note 1: This register is unimplemented in PIC18F6527/6622/6627/6722 devices. DS39646C-page 302 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY REGISTER 25-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U-0 U-0 U-0 U-0 R/P-0 R/P-1 R/P-1 MCLRE — — — — LPT1OSC ECCPMX(1) CCP2MX bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled; RG5 input pin disabled 0 = RG5 input pin enabled; MCLR disabled bit 6-3 Unimplemented: Read as ‘0’ bit 2 LPT1OSC: Low-Power Timer1 Oscillator Enable bit 1 = Timer1 configured for low-power operation 0 = Timer1 configured for higher power operation bit 1 ECCPMX: ECCP MUX bit(1) 1 = ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RE6, RE5, RE4 and RE3 respectively 0 = ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RH7, RH6, RH5 and RH4 respectively bit 0 CCP2MX: CCP2 MUX bit 1 = ECCP2 input/output is multiplexed with RC1 0 = ECCP2 input/output is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode(1). ECCP2 is multiplexed with RE7 in Microcontroller mode. Note 1: This feature is only available on PIC18F8527/8622/8627/8722 devices. © 2008 Microchip Technology Inc. DS39646C-page 303

PIC18F8722 FAMILY REGISTER 25-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 R/P-0 R/P-0 R/P-0 U-0 R/P-1 U-0 R/P-1 DEBUG XINST BBSIZ1 BBSIZ0 — LVP — STVREN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug bit 6 XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode) bit 5-4 BBSIZ<1:0>: Boot Block Size Select bits 11 = 4K words (8 Kbytes) boot block size 10 = 4K words (8 Kbytes) boot block size 01 = 2K words (4 Kbytes) boot block size 00 = 1K word (2 Kbytes) boot block size bit 3 Unimplemented: Read as ‘0’ bit 2 LVP: Single-Supply ICSP™ Enable bit 1 = Single-Supply ICSP enabled 0 = Single-Supply ICSP disabled bit 1 Unimplemented: Read as ‘0’ bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause Reset 0 = Stack full/underflow will not cause Reset DS39646C-page 304 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY REGISTER 25-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 CP7(1) CP6(1) CP5(2) CP5(2) CP3(3) CP2 CP1 CP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CP7: Code Protection bit(1) 1 = Block 7 (01C000-01FFFFh) not code-protected 0 = Block 7 (01C000-01FFFFh) code-protected bit 6 CP6: Code Protection bit(1) 1 = Block 6 (01BFFF-018000h) not code-protected 0 = Block 6 (01BFFF-018000h) code-protected bit 5 CP5: Code Protection bit(2) 1 = Block 5 (014000-017FFFh) not code-protected 0 = Block 5 (014000-017FFFh) code-protected bit 4 CP4: Code Protection bit(2) 1 = Block 4 (010000-013FFFh) not code-protected 0 = Block 4 (010000-013FFFh) code-protected bit 3 CP3: Code Protection bit(3) 1 = Block 3 (00C000-00FFFFh) not code-protected 0 = Block 3 (00C000-00FFFFh) code-protected bit 2 CP2: Code Protection bit 1 = Block 2 (008000-00BFFFh) not code-protected 0 = Block 2 (008000-00BFFFh) code-protected bit 1 CP1: Code Protection bit 1 = Block 1 (004000-007FFFh) not code-protected 0 = Block 1 (004000-007FFFh) code-protected bit 0 CP0: Code Protection bit 1 = Block 0 (000800, 001000 or 002000(4)-003FFFh) not code-protected 0 = Block 0 (000800, 001000 or 002000(4)-003FFFh) code-protected Note 1: Unimplemented in PIC18F6527/6622/6627/8527/8622/8627 devices; maintain this bit set. 2: Unimplemented in PIC18F6527/6622/8527/8622 devices; maintain this bit set. 3: Unimplemented in PIC18F6527/8527 devices; maintain this bit set. 4: Boot block size is determined by the BBSIZ<1:0> bits in CONFIG4L. © 2008 Microchip Technology Inc. DS39646C-page 305

PIC18F8722 FAMILY REGISTER 25-8: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h) R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code-protected 0 = Data EEPROM code-protected bit 6 CPB: Boot Block Code Protection bit 1 = Boot block (000000-0007FFh) not code-protected 0 = Boot block (000000-0007FFh) code-protected bit 5-0 Unimplemented: Read as ‘0’ DS39646C-page 306 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY REGISTER 25-9: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 WRT7(1) WRT6(1) WRT5(2) WRT4(2) WRT3(3) WRT2 WRT1 WRT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WRT7: Write Protection bit(1) 1 = Block 7 (01C000-01FFFFh) not write-protected 0 = Block 7 (01C000-01FFFFh) write-protected bit 6 WRT6: Write Protection bit(1) 1 = Block 6 (01BFFF-018000h) not write-protected 0 = Block 6 (01BFFF-018000h) write-protected bit 5 WRT5: Write Protection bit(2) 1 = Block 5 (014000-017FFFh) not write-protected 0 = Block 5 (014000-017FFFh) write-protected bit 4 WRT4: Write Protection bit(2) 1 = Block 4 (010000-013FFFh) not write-protected 0 = Block 4 (010000-013FFFh) write-protected bit 3 WRT3: Write Protection bit(3) 1 = Block 3 (00C000-00FFFFh) not write-protected 0 = Block 3 (00C000-00FFFFh) write-protected bit 2 WRT2: Write Protection bit 1 = Block 2 (008000-00BFFFh) not write-protected 0 = Block 2 (008000-00BFFFh) write-protected bit 1 WRT1: Write Protection bit 1 = Block 1 (004000-007FFFh) not write-protected 0 = Block 1 (004000-007FFFh) write-protected bit 0 WRT0: Write Protection bit 1 = Block 0 (000800, 001000 or 002000(4)-003FFFh) not write-protected 0 = Block 0 (000800, 001000 or 002000(4)-003FFFh) write-protected Note 1: Unimplemented in PIC18F6527/6622/6627/8527/8622/8627 devices; maintain this bit set. 2: Unimplemented in PIC18F6527/6622/8527/8622 devices; maintain this bit set. 3: Unimplemented in PIC18F6527/8527 devices; maintain this bit set. 4: Boot block size is determined by the BBSIZ<1:0> bits in CONFIG4L. © 2008 Microchip Technology Inc. DS39646C-page 307

PIC18F8722 FAMILY REGISTER 25-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh) R/C-1 R/C-1 R-1 U-0 U-0 U-0 U-0 U-0 WRTD WRTB WRTC(2) — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write-protected 0 = Data EEPROM write-protected bit 6 WRTB: Boot Block Write Protection bit 1 = Boot block (000000-007FFF, 000FFF or 001FFFh(1)) not write-protected 0 = Boot block (000000-007FFF, 000FFF or 001FFFh(1)) write-protected bit 5 WRTC: Configuration Register Write Protection bit(2) 1 = Configuration registers (300000-3000FFh) not write-protected 0 = Configuration registers (300000-3000FFh) write-protected bit 4-0 Unimplemented: Read as ‘0’ Note 1: Boot block size is determined by the BBSIZ<1:0> bits in CONFIG4L. 2: This bit is read-only in normal execution mode; it can be written only in Program mode. DS39646C-page 308 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY REGISTER 25-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 EBTR7(1) EBTR6(1) EBTR5(2) EBTR4(2) EBTR3(3) EBTR2 EBTR1 EBTR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EBTR7: Table Read Protection bit(1) 1 = Block 7 (01C000-01FFFFh) not protected from table reads executed in other blocks 0 = Block 7 (01C000-01FFFFh) protected from table reads executed in other blocks bit 6 EBTR6: Table Read Protection bit(1) 1 = Block 6 (018000-01BFFFh) not protected from table reads executed in other blocks 0 = Block 6 (018000-01BFFFh) protected from table reads executed in other blocks bit 5 EBTR5: Table Read Protection bit(2) 1 = Block 5 (014000-017FFFh) not protected from table reads executed in other blocks 0 = Block 5 (014000-017FFFh) protected from table reads executed in other blocks bit 4 EBTR4: Table Read Protection bit(2) 1 = Block 4 (010000-013FFFh) not protected from table reads executed in other blocks 0 = Block 4 (010000-013FFFh) protected from table reads executed in other blocks bit 3 EBTR3: Table Read Protection bit(3) 1 = Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks 0 = Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks bit 2 EBTR2: Table Read Protection bit 1 = Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks 0 = Block 2 (008000-00BFFFh) protected from table reads executed in other blocks bit 1 EBTR1: Table Read Protection bit 1 = Block 1 (004000-007FFFh) not protected from table reads executed in other blocks 0 = Block 1 (004000-007FFFh) protected from table reads executed in other blocks bit 0 EBTR0: Table Read Protection bit 1 = Block 0 (000800, 001000 or 002000(4)-003FFFh) not protected from table reads executed in other blocks 0 = Block 0 (000800, 001000 or 002000(4)-003FFFh) protected from table reads executed in other blocks Note 1: Unimplemented in PIC18F6527/6622/6627/8527/8622/8627 devices; maintain this bit set. 2: Unimplemented in PIC18F6527/6622/8527/8622 devices; maintain this bit set. 3: Unimplemented in PIC18F6527/8527 devices; maintain this bit set. 4: Unimplemented in PIC18F6527/8527 devices; maintain this bit set. © 2008 Microchip Technology Inc. DS39646C-page 309

PIC18F8722 FAMILY REGISTER 25-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh) U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 — EBTRB — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 EBTRB: Boot Block Table Read Protection bit 1 = Boot block (000000-007FFF, 000FFF or 001FFFh(1)) not protected from table reads executed in other blocks 0 = Boot block (000000-007FFF, 000FFF or 001FFFh(1)) protected from table reads executed in other blocks bit 5-0 Unimplemented: Read as ‘0’ Note 1: Boot block size is determined by the BBSIZ<1:0> bits in CONFIG4L. DS39646C-page 310 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY REGISTER 25-13: DEVID1: DEVICE ID REGISTER 1 FOR THE PIC18F8722 FAMILY R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 DEV<2:0>: Device ID bits 001 = PIC18F8722 111 = PIC18F8627 101 = PIC18F8622 011 = PIC18F8527 000 = PIC18F6722 110 = PIC18F6627 100 = PIC18F6622 010 = PIC18F6527 bit 4-0 REV<4:0>: Revision ID bits These bits are used to indicate the device revision. REGISTER 25-14: DEVID2: DEVICE ID REGISTER 2 FOR THE PIC18F8722 FAMILY R R R R R R R R DEV10(1) DEV9(1) DEV8(1) DEV7(1) DEV6(1) DEV5(1) DEV4(1) DEV3(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 DEV<10:3>: Device ID bits(1) These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number. 0001 0100 = PIC18F6722/8722 devices 0001 0011 = PIC18F6527/6622/6627/8527/8622/8627 devices Note 1: These values for DEV<10:3> may be shared with other devices. The specific device is always identified by using the entire DEV<10:0> bit sequence. © 2008 Microchip Technology Inc. DS39646C-page 311

PIC18F8722 FAMILY 25.2 Watchdog Timer (WDT) Note1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts For the PIC18F8722 family of devices, the WDT is when executed. driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal 2: Changing the setting of the IRCF bits WDT period is 4ms and has the same stability as the (OSCCON<6:4>) clears the WDT and INTRC oscillator. postscaler counts. The 4ms period of the WDT is multiplied by a 16-bit 3: When a CLRWDT instruction is executed, postscaler. Any output of the WDT postscaler is the postscaler count will be cleared. selected by a multiplexor, controlled by bits in Configuration Register 2H. Available periods range 25.2.1 CONTROL REGISTER from 4ms to 131.072 seconds (2.18 minutes). The Register25-15 shows the WDTCON register. This is a WDT and postscaler are cleared when any of the readable and writable register which contains a control following events occur: a SLEEP or CLRWDT instruction bit that allows software to override the WDT enable is executed, the IRCF bits (OSCCON<6:4>) are Configuration bit, but only if the Configuration bit has changed or a clock failure has occurred. disabled the WDT. FIGURE 25-1: WDT BLOCK DIAGRAM SWDTEN Enable WDT WDTEN WDT Counter INTRC Source ÷128 Wake-up from Power-Managed Modes Change on IRCF bits Programmable Postscaler Reset WDT CLRWDT Reset 1:1 to 1:32,768 All Device Resets 4 WDTPS<4:1> Sleep DS39646C-page 312 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY REGISTER 25-15: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled. TABLE 25-2: SUMMARY OF WATCHDOG TIMER REGISTERS Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page RCON IPEN SBOREN — RI TO PD POR BOR 56 WDTCON — — — — — — — SWDTEN 58 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer. © 2008 Microchip Technology Inc. DS39646C-page 313

PIC18F8722 FAMILY 25.3 Two-Speed Start-up In all other power-managed modes, Two-Speed Start- up is not used. The device will be clocked by the The Two-Speed Start-up feature helps to minimize the currently selected clock source until the primary clock latency period from oscillator start-up to code execution source becomes available. The setting of the IESO bit by allowing the microcontroller to use the INTOSC is ignored. oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO 25.3.1 SPECIAL CONSIDERATIONS FOR Configuration bit. USING TWO-SPEED START-UP Two-Speed Start-up should be enabled only if the While using the INTOSC oscillator in Two-Speed Start- primary oscillator mode is LP, XT, HS or HSPLL up, the device still obeys the normal command (crystal-based modes). Other sources do not require sequences for entering power-managed modes, an OST start-up delay; for these, Two-Speed Start-up including multiple SLEEP instructions (refer to should be disabled. Section3.1.4 “Multiple Sleep Commands”). In When enabled, Resets and wake-ups from Sleep mode practice, this means that user code can change the cause the device to configure itself to run from the SCS<1:0> bit settings or issue SLEEP instructions internal oscillator block as the clock source, following before the OST times out. This would allow an the time-out of the Power-up Timer after a Power-on application to briefly wake-up, perform routine Reset is enabled. This allows almost immediate code “housekeeping” tasks and return to Sleep before the execution while the primary oscillator starts and the device starts to operate from the primary oscillator. OST is running. Once the OST times out, the device User code can also check if the primary clock source is automatically switches to PRI_RUN mode. currently providing the device clocking by checking the To use a higher clock speed on wake-up, the INTOSC status of the OSTS bit (OSCCON<3>). If the bit is set, or postscaler clock sources can be selected to provide the primary oscillator is providing the clock. Otherwise, a higher clock speed by setting bits IRCF<2:0> the internal oscillator block is providing the clock during immediately after Reset. For wake-ups from Sleep, the wake-up from Reset or Sleep mode. INTOSC or postscaler clock sources can be selected by setting the IRCF2:0> bits prior to entering Sleep mode. FIGURE 25-2: TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTOSC Multiplexor OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition(2) CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 PC + 6 Wake from Interrupt Event OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. DS39646C-page 314 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 25.4 Fail-Safe Clock Monitor To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide The Fail-Safe Clock Monitor (FSCM) allows the a higher clock speed by setting bits, IRCF<2:0>, microcontroller to continue operation in the event of an immediately after Reset. For wake-ups from Sleep, the external oscillator failure by automatically switching the INTOSC or postscaler clock sources can be selected device clock to the internal oscillator block. The FSCM by setting the IRCF<2:0> bits prior to entering Sleep function is enabled by setting the FCMEN Configuration mode. bit. The FSCM will detect failures of the primary or second- When FSCM is enabled, the INTRC oscillator runs at ary clock sources only. If the internal oscillator block all times to monitor clocks to peripherals and provide a fails, no failure would be detected, nor would any action backup clock in the event of a clock failure. Clock be possible. monitoring (shown in Figure25-3) is accomplished by creating a sample clock signal, which is the INTRC out- 25.4.1 FSCM AND THE WATCHDOG TIMER put divided by 64. This allows ample time between Both the FSCM and the WDT are clocked by the FSCM sample clocks for a peripheral clock edge to INTRC oscillator. Since the WDT operates with a occur. The peripheral device clock and the sample separate divider and counter, disabling the WDT has clock are presented as inputs to the Clock Monitor latch no effect on the operation of the INTRC oscillator when (CM). The CM is set on the falling edge of the device the FSCM is enabled. clock source, but cleared on the rising edge of the sample clock. As already noted, the clock source is switched to the INTOSC clock when a clock failure is detected. FIGURE 25-3: FSCM BLOCK DIAGRAM Depending on the frequency selected by the IRCF<2:0> bits, this may mean a substantial change in Clock Monitor the speed of code execution. If the WDT is enabled Latch (CM) (edge-triggered) with a small prescale value, a decrease in clock speed Peripheral allows a WDT time-out to occur and a subsequent S Q Clock device Reset. For this reason, fail-safe clock events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed and INTRC decreasing the likelihood of an erroneous time-out. ÷ 64 C Q Source 25.4.2 EXITING FAIL-SAFE OPERATION (32 μs) 488 Hz (2.048 ms) The fail-safe condition is terminated by either a device Reset or by entering a power-managed mode. On Clock Reset, the controller starts the primary clock source Failure specified in Configuration Register 1H (with any Detected required start-up delays that are required for the oscillator mode, such as OST or PLL timer). The Clock failure is tested for on the falling edge of the INTOSC multiplexor provides the device clock until the sample clock. If a sample clock falling edge occurs primary clock source becomes ready (similar to a Two- while CM is still set, a clock failure has been detected Speed Start-up). The clock source is then switched to (Figure25-4). This causes the following: the primary clock (indicated by the OSTS bit in the • the FSCM generates an oscillator fail interrupt by OSCCON register becoming set). The Fail-Safe Clock setting bit, OSCFIF (PIR2<7>); Monitor then resumes monitoring the peripheral clock. • the device clock source is switched to the internal The primary clock source may never become ready oscillator block (OSCCON is not updated to show during start-up. In this case, operation is clocked by the the current clock source – this is the fail-safe INTOSC multiplexor. The OSCCON register will remain condition) and in its Reset state until a power-managed mode is • the WDT is reset. entered. During switchover, the postscaler frequency from the internal oscillator block may not be sufficiently stable for timing sensitive applications. In these cases, it may be desirable to select another clock configuration and enter an alternate power-managed mode. This can be done to attempt a partial recovery or execute a controlled shut- down. See Section3.1.4 “Multiple Sleep Commands” and Section25.3.1 “Special Considerations for Using Two-Speed Start-up” for more details. © 2008 Microchip Technology Inc. DS39646C-page 315

PIC18F8722 FAMILY FIGURE 25-4: FSCM TIMING DIAGRAM Sample Clock Device Oscillator Clock Failure Output CM Output (Q) Failure Detected OSCFIF CM Test CM Test CM Test Note: The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 25.4.3 FSCM INTERRUPTS IN For oscillator modes involving a crystal or resonator POWER-MANAGED MODES (HS, HSPLL, LP or XT), the situation is somewhat different. Since the oscillator may require a start-up By entering a power-managed mode, the clock time considerably longer than the FCSM sample clock multiplexor selects the clock source selected by the time, a false clock failure may be detected. To prevent OSCCON register. Fail-Safe Monitoring of the power- this, the internal oscillator block is automatically config- managed clock source resumes in the power-managed ured as the device clock and functions until the primary mode. clock is stable (the OST and PLL timers have timed If an oscillator failure occurs during power-managed out). This is identical to Two-Speed Start-up mode. operation, the subsequent events depend on whether Once the primary clock is stable, the INTRC returns to or not the oscillator failure interrupt is enabled. If its role as the FSCM source. enabled (OSCFIF=1), code execution will be clocked Note: The same logic that prevents false oscilla- by the INTOSC multiplexer. An automatic transition tor failure interrupts on POR, or wake from back to the failed clock source will not occur. Sleep, will also prevent the detection of If the interrupt is disabled, subsequent interrupts while the oscillator’s failure to start at all follow- in Idle mode will cause the CPU to begin executing ing these events. This can be avoided by instructions while being clocked by the INTOSC monitoring the OSTS bit and using a source. timing routine to determine if the oscillator is taking too long to start. Even so, no 25.4.4 POR OR WAKE FROM SLEEP oscillator failure interrupt will be flagged. The FSCM is designed to detect oscillator failure at any As noted in Section25.3.1 “Special Considerations point after the device has exited Power-on Reset for Using Two-Speed Start-up”, it is also possible to (POR) or low-power Sleep mode. When the primary select another clock configuration and enter an device clock is EC, RC or INTRC modes, monitoring alternate power-managed mode while waiting for the can begin immediately following these events. primary clock to become stable. When the new power- managed mode is selected, the primary clock is disabled. DS39646C-page 316 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 25.5 Program Verification and Each of the blocks has three code protection bits Code Protection associated with them. They are: • Code-Protect bit (CPn) The user program memory is divided into four blocks • Write-Protect bit (WRTn) for PIC18F6527/8527 devices, five blocks for • External Block Table Read bit (EBTRn) PIC18F6622/8622 devices, six blocks for PIC18F6627/ 8627 devices and eight blocks for PIC18F6722/8722 Figure25-5 shows the program memory organization for devices. One of these is a boot block of 2, 4 or 48, 64, 96 and 128-Kbyte devices and the specific code 8Kbytes. The remainder of the memory is divided into protection bit associated with each block. The actual blocks on binary boundaries. locations of the bits are summarized in Table25-3. FIGURE 25-5: CODE-PROTECTED PROGRAM MEMORY FOR THE PIC18F8722 FAMILY 000000h Code Memory MEMORY SIZE/DEVICE 01FFFFh 128Kbytes 96Kbytes 64Kbytes 48Kbytes Address (PIC18FX722) (PIC18FX627) (PIC18FX622) (PIC18FX527) Range 000000h Boot Block Boot Block Boot Block Boot Block 0007FFh* or 000FFFh* or Unimplemented 001FFFh* Read as ‘0’ 000800h* or 001000h* or Block 0 Block 0 Block 0 Block 0 002000h* 003FFFh 004000h Block 1 Block 1 Block 1 Block 1 007FFFh 200000h 008000h Block 2 Block 2 Block 2 Block 2 00BFFFh 00C000h Configuration Block 3 Block 3 Block 3 and ID Space 00FFFFh 010000h Block 4 Block 4 013FFFh 014000h Unimplemented Block 5 Block 5 Read ‘0’s 3FFFFFh Unimplemented 017FFFh Read ‘0’s 018000h Block 6 Unimplemented 01BFFFh Read ‘0’s 01C000h Block 7 01FFFFh Note: Sizes of memory areas are not to scale. * Boot block size is determined by the BBSIZ<1:0> bits in CONFIG4L. © 2008 Microchip Technology Inc. DS39646C-page 317

PIC18F8722 FAMILY TABLE 25-3: SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L CP7(1) CP6(1) CP5(2) CP4(2) CP3(3) CP2 CP1 CP0 300009h CONFIG5H CPD CPB — — — — — — 30000Ah CONFIG6L WRT7(1) WRT6(1) WRT5(2) WRT4(2) WRT3(3) WRT2 WRT1 WRT0 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 30000Ch CONFIG7L EBRT7(1) EBRT6(1) EBTR5(2) EBTR4(2) EBTR3(3) EBTR2 EBTR1 EBTR0 30000Dh CONFIG7H — EBTRB — — — — — — Legend: Shaded cells are unimplemented. Note 1: Unimplemented in PIC18F6527/6622/6627/8527/8622/8627 devices; maintain this bit set. 2: Unimplemented in PIC18F6527/6622/8527/8622 devices; maintain this bit set. 3: Unimplemented in PIC18F6527/8527 devices; maintain this bit set. 25.5.1 PROGRAM MEMORY not allowed to read and will result in reading ‘0’s. CODE PROTECTION Figures25-6 through25-8 illustrate table write and table read protection. The program memory may be read to or written from any location using the table read and table write Note: Code protection bits may only be written to instructions. The device ID may be read with table a ‘0’ from a ‘1’ state. It is not possible to reads. The Configuration registers may be read and write a ‘1’ to a bit in the ‘0’ state. Code written with the table read and table write instructions. protection bits are only set to ‘1’ by a full chip erase or block erase function. The full In normal execution mode, the CPn bits have no direct chip erase and block erase functions can effect. CPn bits inhibit external reads and writes. A block only be initiated via ICSP or an external of user memory may be protected from table writes if the programmer. Refer to the device WRTn Configuration bit is ‘0’. The EBTRn bits control programming specification for more table reads. For a block of user memory with the EBTRn information. bit set to ‘0’, a table read instruction that executes from within that block is allowed to read. A table read instruc- tion that executes from a location outside of that block is FIGURE 25-6: TABLE WRITE (WRTn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 01 PC = 003FFEh TBLWT* 003FFFh 004000h WRT1, EBTR1 = 11 007FFFh 008000h PC = 00BFFEh TBLWT* WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: All table writes disabled to Blockn whenever WRTn = 0. DS39646C-page 318 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 25-7: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 10 003FFFh 004000h PC = 007FFEh TBLRD* WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of ‘0’. FIGURE 25-8: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 10 PC = 003FFEh TBLRD* 003FFFh 004000h WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: Table reads permitted within Blockn, even when EBTRBn = 0. TABLAT register returns the value of the data at the location TBLPTR. © 2008 Microchip Technology Inc. DS39646C-page 319

PIC18F8722 FAMILY 25.5.2 DATA EEPROM To use the In-Circuit Debugger function of the micro- CODE PROTECTION controller, the design must implement In-Circuit Serial Programming connections to RG5/MCLR/VPP, VDD, The entire data EEPROM is protected from external VSS, RB7 and RB6. This will interface to the In-Circuit reads and writes by two bits: CPD and WRTD. CPD Debugger module available from Microchip or one of inhibits external reads and writes of data EEPROM. the third party development tool companies. WRTD inhibits internal and external writes to data EEPROM. The CPU can always read data EEPROM 25.9 Single-Supply ICSP Programming under normal operation, regardless of the protection bit settings. The LVP Configuration bit enables Single-Supply ICSP Programming (formerly known as Low-Voltage ICSP 25.5.3 CONFIGURATION REGISTER Programming or LVP). When Single-Supply Program- PROTECTION ming is enabled, the microcontroller can be programmed The Configuration registers can be write-protected. without requiring high voltage being applied to the The WRTC bit controls protection of the Configuration RG5/MCLR/VPP pin, but the RB5/KBI1/PGM pin is then registers. In normal execution mode, the WRTC bit is dedicated to controlling Program mode entry and is not readable only. WRTC can only be written via ICSP or available as a general purpose I/O pin. an external programmer. While programming, using single-supply programming mode, VDD is applied to the RG5/MCLR/VPP pin as in 25.6 ID Locations normal execution mode. To enter Programming mode, VDD is applied to the PGM pin. Eight memory locations (200000h-200007h) are designated as ID locations, where the user can store Note1: High-voltage programming is always checksum or other code identification numbers. These available, regardless of the state of the locations are both readable and writable during normal LVP bit or the PGM pin, by applying VIHH execution through the TBLRD and TBLWT instructions to the MCLR pin. or during program/verify. The ID locations can be read 2: By default, Single-Supply ICSP is when the device is code-protected. enabled in unprogrammed devices (as supplied from Microchip) and erased 25.7 In-Circuit Serial Programming devices. The PIC18F8722 family of devices can be serially 3: When Single-Supply Programming is programmed while in the end application circuit. This is enabled, the RB5 pin can no longer be simply done with two lines for clock and data and three used as a general purpose I/O pin. other lines for power, ground and the programming 4: When LVP is enabled, externally pull the voltage. This allows customers to manufacture boards PGM pin to VSS to allow normal program with unprogrammed devices and then program the execution. microcontroller just before shipping the product. This If Single-Supply ICSP Programming mode will not be also allows the most recent firmware or a custom used, the LVP bit can be cleared. RB5/KBI1/PGM then firmware to be programmed. becomes available as the digital I/O pin, RB5. The LVP bit may be set or cleared only when using standard 25.8 In-Circuit Debugger high-voltage programming (VIHH applied to the RG5/ When the DEBUG Configuration bit is programmed to MCLR/VPP pin). Once LVP has been disabled, only the a ‘0’, the In-Circuit Debugger functionality is enabled. standard high-voltage programming is available and This function allows simple debugging functions when must be used to program the device. used with MPLAB® IDE. When the microcontroller has Memory that is not code-protected can be erased using this feature enabled, some resources are not available a block erase, or erased row by row, then written at any for general use. Table25-4 shows which resources are specified VDD. If code-protected memory is to be required by the background debugger. erased, a block erase is required. If a block erase is to be performed when using Low-Voltage Programming, TABLE 25-4: DEBUGGER RESOURCES the device must be supplied with VDD of 4.5V to 5.5V. I/O pins: RB6, RB7 Stack: 2 levels Program Memory: 512 bytes Data Memory: 10 bytes DS39646C-page 320 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 26.0 INSTRUCTION SET SUMMARY The literal instructions may use some of the following operands: The PIC18F8722 family of devices incorporates the • A literal value to be loaded into a file register standard set of 75 PIC18 core instructions, as well as (specified by ‘k’) an extended set of 8 new instructions for the optimiza- • The desired FSR register to load the literal value tion of code that is recursive or that utilizes a software into (specified by ‘f’) stack. The extended set is discussed later in this section. • No operand required (specified by ‘—’) 26.1 Standard Instruction Set The control instructions may use some of the following operands: The standard PIC18 instruction set adds many enhancements to the previous PIC® MCU instruction • A program memory address (specified by ‘n’) sets, while maintaining an easy migration from these • The mode of the CALL or RETURN instructions PIC MCU instruction sets. Most instructions are a (specified by ‘s’) single program memory word (16 bits), but there are • The mode of the table read and table write four instructions that require two program memory instructions (specified by ‘m’) locations. • No operand required (specified by ‘—’) Each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and All instructions are a single word, except for four one or more operands, which further specify the double-word instructions. These instructions were operation of the instruction. made double-word to contain the required information in 32 bits. In the second word, the 4 MSbs are 1’s. If this The instruction set is highly orthogonal and is grouped second word is executed as an instruction (by itself), it into four basic categories: will execute as a NOP. • Byte-oriented operations All single-word instructions are executed in a single • Bit-oriented operations instruction cycle, unless a conditional test is true or the • Literal operations program counter is changed as a result of the instruc- • Control operations tion. In these cases, the execution takes two instruction The PIC18 instruction set summary in Table26-2 lists cycles with the additional instruction cycle(s) executed byte-oriented, bit-oriented, literal and control as a NOP. operations. Table26-1 shows the opcode field The double word instructions execute in two instruction descriptions. cycles. Most byte-oriented instructions have three operands: One instruction cycle consists of four oscillator periods. 1. The file register (specified by ‘f’) Thus, for an oscillator frequency of 4MHz, the normal 2. The destination of the result (specified by ‘d’) instruction execution time is 1μs. If a conditional test is true, or the program counter is changed as a result of 3. The accessed memory (specified by ‘a’) an instruction, the instruction execution time is 2 μs. The file register designator ‘f’ specifies which file regis- Two-word branch instructions (if true) would take 3 μs. ter is to be used by the instruction. The destination Figure26-1 shows the general formats that the instruc- designator ‘d’ specifies where the result of the tions can have. All examples use the convention ‘nnh’ operation is to be placed. If ‘d’ is zero, the result is to represent a hexadecimal number. placed in the WREG register. If ‘d’ is one, the result is placed in the file register specified in the instruction. The Instruction Set Summary, shown in Table26-2, lists the standard instructions recognized by the All bit-oriented instructions have three operands: Microchip MPASMTM Assembler. 1. The file register (specified by ‘f’) Section26.1.1 “Standard Instruction Set” provides 2. The bit in the file register (specified by ‘b’) a description of each instruction. 3. The accessed memory (specified by ‘a’) The bit field designator ‘b’ selects the number of the bit affected by the operation, while the file register designator ‘f’ represents the number of the file in which the bit is located. © 2008 Microchip Technology Inc. DS39646C-page 321

PIC18F8722 FAMILY TABLE 26-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU status bits: Carry, Digit Carry, Zero, Overflow, Negative. d Destination select bit: d = 0: store result in WREG d = 1: store result in file register f dest Destination: either the WREG register or the specified register file location. f 8-bit Register file address (00h to FFh), or 2-bit FSR designator (0h to 3h). f 12-bit Register file address (000h to FFFh). This is the source address. s f 12-bit Register file address (000h to FFFh). This is the destination address. d GIE Global Interrupt Enable bit. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No Change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) +* Pre-Increment register (such as TBLPTR with table reads and writes) n The relative address (2’s complement number) for relative branch instructions or the direct address for Call/Branch and Return instructions. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. PD Power-Down bit. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit: s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) TBLPTR 21-bit Table Pointer (points to a Program Memory location). TABLAT 8-bit Table Latch. TO Time-out bit. TOS Top-of-Stack. u Unused or Unchanged. WDT Watchdog Timer. WREG Working register (accumulator). x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. z 7-bit offset value for Indirect Addressing of register files (source). s z 7-bit offset value for Indirect Addressing of register files (destination). d { } Optional argument. [text] Indicates an indexed address. (text) The contents of text. [expr]<n> Specifies bit n of the register indicated by the pointer expr. → Assigned to. < > Register bit field. ∈ In the set of. italics User-defined term (font is Courier). DS39646C-page 322 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 26-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations Example Instruction 15 10 9 8 7 0 OPCODE d a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2 15 12 11 0 1111 f (Destination FILE #) f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 0 OPCODE k (literal) MOVLW 7Fh k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 0 OPCODE n<7:0> (literal) GOTO Label 15 12 11 0 1111 n<19:8> (literal) n = 20-bit immediate value 15 8 7 0 OPCODE S n<7:0> (literal) CALL MYFUNC 15 12 11 0 1111 n<19:8> (literal) S = Fast bit 15 11 10 0 OPCODE n<10:0> (literal) BRA MYFUNC 15 8 7 0 OPCODE n<7:0> (literal) BC MYFUNC © 2008 Microchip Technology Inc. DS39646C-page 323

PIC18F8722 FAMILY TABLE 26-2: PIC18FXXXX INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED OPERATIONS ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2 CLRF f, a Clear f 1 0110 101a ffff ffff Z 2 COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2 CPFSEQ f, a Compare f with WREG, Skip = 1 (2 or 3) 0110 001a ffff ffff None 4 CPFSGT f, a Compare f with WREG, Skip > 1 (2 or 3) 0110 010a ffff ffff None 4 CPFSLT f, a Compare f with WREG, Skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2 DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4 DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2 INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4 INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2 IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2 MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1 MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None fd (destination) 2nd word 1111 ffff ffff ffff MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2 NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2 RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N SETF f, a Set f 1 0110 100a ffff ffff None 1, 2 SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N Borrow SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2 SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N Borrow SWAPF f, d, a Swap Nibbles in f 1 0011 10da ffff ffff None 4 TSTFSZ f, a Test f, Skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2 XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS39646C-page 324 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 26-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BIT-ORIENTED OPERATIONS BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2 BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2 BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4 BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4 BTG f, b, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2 CONTROL OPERATIONS BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None CALL n, s Call Subroutine 1st word 2 1110 110s kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C GOTO n Go to Address 1st word 2 1110 1111 kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk NOP — No Operation 1 0000 0000 0000 0000 None NOP — No Operation 1 1111 xxxx xxxx xxxx None 4 POP — Pop Top of Return Stack (TOS) 1 0000 0000 0000 0110 None PUSH — Push Top of Return Stack (TOS) 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 1nnn nnnn nnnn None RESET Software Device Reset 1 0000 0000 1111 1111 All RETFIE s Return from Interrupt Enable 2 0000 0000 0001 000s GIE/GIEH, PEIE/GIEL RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. © 2008 Microchip Technology Inc. DS39646C-page 325

PIC18F8722 FAMILY TABLE 26-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb LITERAL OPERATIONS ADDLW k Add Literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND Literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR Literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move Literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None to FSR(f) 1st word 1111 0000 kkkk kkkk MOVLB k Move Literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move Literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply Literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from Literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR Literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with Post-Increment 0000 0000 0000 1001 None TBLRD*- Table Read with Post-Decrement 0000 0000 0000 1010 None TBLRD+* Table Read with Pre-Increment 0000 0000 0000 1011 None TBLWT* Table Write 2 0000 0000 0000 1100 None 5 TBLWT*+ Table Write with Post-Increment 0000 0000 0000 1101 None 5 TBLWT*- Table Write with Post-Decrement 0000 0000 0000 1110 None 5 TBLWT+* Table Write with Pre-Increment 0000 0000 0000 1111 None 5 Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS39646C-page 326 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 26.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW k Syntax: ADDWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (W) + k → W a ∈ [0,1] Status Affected: N, OV, C, DC, Z Operation: (W) + (f) → dest Encoding: 0000 1111 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: The contents of W are added to the Encoding: 0010 01da ffff ffff 8-bit literal ‘k’ and the result is placed in W. Description: Add W to register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the Words: 1 result is stored back in register ‘f’ Cycles: 1 (default). Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read Process Write to GPR bank (default). literal ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: ADDLW 15h mode whenever f ≤ 95 (5Fh). See Before Instruction Section26.2.3 “Byte-Oriented and W = 10h Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. W = 25h Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWF REG, 0, 0 Before Instruction W = 17h REG = 0C2h After Instruction W = 0D9h REG = 0C2h Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). © 2008 Microchip Technology Inc. DS39646C-page 327

PIC18F8722 FAMILY ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC f {,d {,a}} Syntax: ANDLW k Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255 d ∈ [0,1] Operation: (W) .AND. k → W a ∈ [0,1] Status Affected: N, Z Operation: (W) + (f) + (C) → dest Encoding: 0000 1011 kkkk kkkk Status Affected: N,OV, C, DC, Z Description: The contents of W are ANDed with the Encoding: 0010 00da ffff ffff 8-bit literal ‘k’. The result is placed in W. Description: Add W, the Carry flag and data memory Words: 1 location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is Cycles: 1 placed in data memory location ‘f’. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read literal Process Write to GPR bank (default). ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Example: ANDLW 05Fh in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Before Instruction Section26.2.3 “Byte-Oriented and W = A3h Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. W = 03h Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWFC REG, 0, 1 Before Instruction Carry bit = 1 REG = 02h W = 4Dh After Instruction Carry bit = 0 REG = 02h W = 50h DS39646C-page 328 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY ANDWF AND W with f BC Branch if Carry Syntax: ANDWF f {,d {,a}} Syntax: BC n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 d ∈ [0,1] Operation: if Carry bit is ‘1’ a ∈ [0,1] (PC) + 2 + 2n → PC Operation: (W) .AND. (f) → dest Status Affected: None Status Affected: N, Z Encoding: 1110 0010 nnnn nnnn Encoding: 0001 01da ffff ffff Description: If the Carry bit is ’1’, then the program Description: The contents of W are ANDed with will branch. register ‘f’. If ‘d’ is ‘0’, the result is stored The 2’s complement number ‘2n’ is in W. If ‘d’ is ‘1’, the result is stored back added to the PC. Since the PC will have in register ‘f’ (default). incremented to fetch the next If ‘a’ is ‘0’, the Access Bank is selected. instruction, the new address will be If ‘a’ is ‘1’, the BSR is used to select the PC + 2 + 2n. This instruction is then a GPR bank (default). two-cycle instruction. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates Cycles: 1(2) in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Q Cycle Activity: Section26.2.3 “Byte-Oriented and If Jump: Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4 Literal Offset Mode” for details. Decode Read literal Process Write to Words: 1 ‘n’ Data PC No No No No Cycles: 1 operation operation operation operation Q Cycle Activity: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read literal Process No register ‘f’ Data destination ‘n’ Data operation Example: ANDWF REG, 0, 0 Example: HERE BC 5 Before Instruction Before Instruction W = 17h PC = address (HERE) REG = C2h After Instruction After Instruction If Carry = 1; W = 02h PC = address (HERE + 12) REG = C2h If Carry = 0; PC = address (HERE + 2) © 2008 Microchip Technology Inc. DS39646C-page 329

PIC18F8722 FAMILY BCF Bit Clear f BN Branch if Negative Syntax: BCF f, b {,a} Syntax: BN n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 0 ≤ b ≤ 7 Operation: if Negative bit is ‘1’ a ∈ [0,1] (PC) + 2 + 2n → PC Operation: 0 → f<b> Status Affected: None Status Affected: None Encoding: 1110 0110 nnnn nnnn Encoding: 1001 bbba ffff ffff Description: If the Negative bit is ‘1’, then the Description: Bit ‘b’ in register ‘f’ is cleared. program will branch. If ‘a’ is ‘0’, the Access Bank is selected. The 2’s complement number ‘2n’ is If ‘a’ is ‘1’, the BSR is used to select the added to the PC. Since the PC will have GPR bank (default). incremented to fetch the next instruction, the new address will be If ‘a’ is ‘0’ and the extended instruction PC + 2 + 2n. This instruction is then a set is enabled, this instruction operates two-cycle instruction. in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Words: 1 Section26.2.3 “Byte-Oriented and Cycles: 1(2) Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: If Jump: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to Q Cycle Activity: ‘n’ Data PC Q1 Q2 Q3 Q4 No No No No Decode Read Process Write operation operation operation operation register ‘f’ Data register ‘f’ If No Jump: Q1 Q2 Q3 Q4 Example: BCF FLAG_REG, 7, 0 Decode Read literal Process No ‘n’ Data operation Before Instruction FLAG_REG = C7h After Instruction Example: HERE BN Jump FLAG_REG = 47h Before Instruction PC = address (HERE) After Instruction If Negative = 1; PC = address (Jump) If Negative = 0; PC = address (HERE + 2) DS39646C-page 330 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC n Syntax: BNN n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘0’ Operation: if Negative bit is ‘0’ (PC) + 2 + 2n → PC (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn Description: If the Carry bit is ‘0’, then the program Description: If the Negative bit is ‘0’, then the will branch. program will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to Decode Read literal Process Write to ‘n’ Data PC ‘n’ Data PC No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNC Jump Example: HERE BNN Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Carry = 0; If Negative = 0; PC = address (Jump) PC = address (Jump) If Carry = 1; If Negative = 1; PC = address (HERE + 2) PC = address (HERE + 2) © 2008 Microchip Technology Inc. DS39646C-page 331

PIC18F8722 FAMILY BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV n Syntax: BNZ n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘0’ Operation: if Zero bit is ‘0’ (PC) + 2 + 2n → PC (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn Description: If the Overflow bit is ‘0’, then the Description: If the Zero bit is ‘0’, then the program program will branch. will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to Decode Read literal Process Write to ‘n’ Data PC ‘n’ Data PC No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNOV Jump Example: HERE BNZ Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Overflow = 0; If Zero = 0; PC = address (Jump) PC = address (Jump) If Overflow = 1; If Zero = 1; PC = address (HERE + 2) PC = address (HERE + 2) DS39646C-page 332 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY BRA Unconditional Branch BSF Bit Set f Syntax: BRA n Syntax: BSF f, b {,a} Operands: -1024 ≤ n ≤ 1023 Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 Operation: (PC) + 2 + 2n → PC a ∈ [0,1] Status Affected: None Operation: 1 → f<b> Encoding: 1101 0nnn nnnn nnnn Status Affected: None Description: Add the 2’s complement number ‘2n’ to Encoding: 1000 bbba ffff ffff the PC. Since the PC will have incremented to fetch the next Description: Bit ‘b’ in register ‘f’ is set. instruction, the new address will be If ‘a’ is ‘0’, the Access Bank is selected. PC + 2 + 2n. This instruction is a If ‘a’ is ‘1’, the BSR is used to select the two-cycle instruction. GPR bank (default). Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 2 set is enabled, this instruction operates in Indexed Literal Offset Addressing Q Cycle Activity: mode whenever f ≤ 95 (5Fh). See Q1 Q2 Q3 Q4 Section26.2.3 “Byte-Oriented and Decode Read literal Process Write to Bit-Oriented Instructions in Indexed ‘n’ Data PC Literal Offset Mode” for details. No No No No Words: 1 operation operation operation operation Cycles: 1 Q Cycle Activity: Example: HERE BRA Jump Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write PC = address (HERE) register ‘f’ Data register ‘f’ After Instruction PC = address (Jump) Example: BSF FLAG_REG, 7, 1 Before Instruction FLAG_REG = 0Ah After Instruction FLAG_REG = 8Ah © 2008 Microchip Technology Inc. DS39646C-page 333

PIC18F8722 FAMILY BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 0 ≤ b < 7 a ∈ [0,1] a ∈ [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped. If bit ‘b’ is ‘0’, then instruction is skipped. If bit ‘b’ is ‘1’, then the next instruction fetched during the the next instruction fetched during the current instruction execution is discarded current instruction execution is discarded and a NOP is executed instead, making and a NOP is executed instead, making this a two-cycle instruction. this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set If ‘a’ is ‘0’ and the extended instruction is enabled, this instruction operates in set is enabled, this instruction operates in Indexed Literal Offset Addressing mode Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process No Decode Read Process No register ‘f’ Data operation register ‘f’ Data operation If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE BTFSC FLAG, 1, 0 Example: HERE BTFSS FLAG, 1, 0 FALSE : FALSE : TRUE : TRUE : Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If FLAG<1> = 0; If FLAG<1> = 0; PC = address (TRUE) PC = address (FALSE) If FLAG<1> = 1; If FLAG<1> = 1; PC = address (FALSE) PC = address (TRUE) DS39646C-page 334 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 0 ≤ b < 7 Operation: if Overflow bit is ‘1’ a ∈ [0,1] (PC) + 2 + 2n → PC Operation: (f<b>) → f<b> Status Affected: None Status Affected: None Encoding: 1110 0100 nnnn nnnn Encoding: 0111 bbba ffff ffff Description: If the Overflow bit is ‘1’, then the Description: Bit ‘b’ in data memory location ‘f’ is program will branch. inverted. The 2’s complement number ‘2n’ is If ‘a’ is ‘0’, the Access Bank is selected. added to the PC. Since the PC will have If ‘a’ is ‘1’, the BSR is used to select the incremented to fetch the next GPR bank (default). instruction, the new address will be PC + 2 + 2n. This instruction is then a If ‘a’ is ‘0’ and the extended instruction two-cycle instruction. set is enabled, this instruction operates in Indexed Literal Offset Addressing Words: 1 mode whenever f ≤ 95 (5Fh). See Cycles: 1(2) Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. If Jump: Q1 Q2 Q3 Q4 Words: 1 Decode Read literal Process Write to PC Cycles: 1 ‘n’ Data Q Cycle Activity: No No No No Q1 Q2 Q3 Q4 operation operation operation operation Decode Read Process Write If No Jump: register ‘f’ Data register ‘f’ Q1 Q2 Q3 Q4 Decode Read literal Process No Example: BTG PORTC, 4, 0 ‘n’ Data operation Before Instruction: PORTC = 0111 0101 [75h] Example: HERE BOV Jump After Instruction: Before Instruction PORTC = 0110 0101 [65h] PC = address (HERE) After Instruction If Overflow = 1; PC = address (Jump) If Overflow = 0; PC = address (HERE + 2) © 2008 Microchip Technology Inc. DS39646C-page 335

PIC18F8722 FAMILY BZ Branch if Zero CALL Subroutine Call Syntax: BZ n Syntax: CALL k {,s} Operands: -128 ≤ n ≤ 127 Operands: 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: if Zero bit is ‘1’ (PC) + 2 + 2n → PC Operation: (PC) + 4 → TOS, k → PC<20:1>, Status Affected: None if s = 1 Encoding: 1110 0000 nnnn nnnn (W) → WS, Description: If the Zero bit is ‘1’, then the program (STATUS) → STATUSS, will branch. (BSR) → BSRS The 2’s complement number ‘2n’ is Status Affected: None added to the PC. Since the PC will have Encoding: incremented to fetch the next 1st word (k<7:0>) 1110 110s k7kkk kkkk0 instruction, the new address will be 2nd word(k<19:8>) 1111 k19kkk kkkk kkkk8 PC + 2 + 2n. This instruction is then a Description: Subroutine call of entire 2-Mbyte two-cycle instruction. memory range. First, return address Words: 1 (PC + 4) is pushed onto the return Cycles: 1(2) stack. If ‘s’ = 1, the W, STATUS and BSR registers are also pushed into their Q Cycle Activity: respective shadow registers, WS, If Jump: STATUSS and BSRS. If ‘s’ = 0, no Q1 Q2 Q3 Q4 update occurs (default). Then, the Decode Read literal Process Write to 20-bit value ‘k’ is loaded into PC<20:1>. ‘n’ Data PC CALL is a two-cycle instruction. No No No No Words: 2 operation operation operation operation Cycles: 2 If No Jump: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No ‘n’ Data operation Decode Read literal Push PC to Read literal ‘k’<7:0>, stack ’k’<19:8>, Write to PC Example: HERE BZ Jump No No No No Before Instruction operation operation operation operation PC = address (HERE) After Instruction Example: HERE CALL THERE,1 If Zero = 1; PC = address (Jump) Before Instruction If Zero = 0; PC = address (HERE) PC = address (HERE + 2) After Instruction PC = address (THERE) TOS = address (HERE + 4) WS = W BSRS = BSR STATUSS= STATUS DS39646C-page 336 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY CLRF Clear f CLRWDT Clear Watchdog Timer Syntax: CLRF f {,a} Syntax: CLRWDT Operands: 0 ≤ f ≤ 255 Operands: None a ∈ [0,1] Operation: 000h → WDT, Operation: 000h → f 000h → WDT postscaler, 1 → Z 1 → TO, 1 → PD Status Affected: Z Status Affected: TO, PD Encoding: 0110 101a ffff ffff Encoding: 0000 0000 0000 0100 Description: Clears the contents of the specified register. Description: CLRWDT instruction resets the Watchdog Timer. It also resets the post- If ‘a’ is ‘0’, the Access Bank is selected. scaler of the WDT. Status bits, TO and If ‘a’ is ‘1’, the BSR is used to select the PD, are set. GPR bank (default). Words: 1 If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Cycles: 1 in Indexed Literal Offset Addressing Q Cycle Activity: mode whenever f ≤ 95 (5Fh). See Q1 Q2 Q3 Q4 Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Decode No Process No Literal Offset Mode” for details. operation Data operation Words: 1 Example: CLRWDT Cycles: 1 Before Instruction Q Cycle Activity: WDT Counter = ? Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write WDT Counter = 00h register ‘f’ Data register ‘f’ WDT Postscaler = 0 TO = 1 PD = 1 Example: CLRF FLAG_REG,1 Before Instruction FLAG_REG = 5Ah After Instruction FLAG_REG = 00h © 2008 Microchip Technology Inc. DS39646C-page 337

PIC18F8722 FAMILY COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF f {,d {,a}} Syntax: CPFSEQ f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W), skip if (f) = (W) Operation: (f) → dest (unsigned comparison) Status Affected: N, Z Status Affected: None Encoding: 0001 11da ffff ffff Encoding: 0110 001a ffff ffff Description: The contents of register ‘f’ are Description: Compares the contents of data memory complemented. If ‘d’ is ‘0’, the result is location ‘f’ to the contents of W by stored in W. If ‘d’ is ‘1’, the result is performing an unsigned subtraction. stored back in register ‘f’ (default). If ‘f’ = W, then the fetched instruction is If ‘a’ is ‘0’, the Access Bank is selected. discarded and a NOP is executed If ‘a’ is ‘1’, the BSR is used to select the instead, making this a two-cycle GPR bank (default). instruction. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank is selected. set is enabled, this instruction operates If ‘a’ is ‘1’, the BSR is used to select the in Indexed Literal Offset Addressing GPR bank (default). mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and If ‘a’ is ‘0’ and the extended instruction Bit-Oriented Instructions in Indexed set is enabled, this instruction operates Literal Offset Mode” for details. in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Words: 1 Section26.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Decode Read Process Write to Cycles: 1(2) register ‘f’ Data destination Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Example: COMF REG, 0, 0 Q1 Q2 Q3 Q4 Before Instruction Decode Read Process No REG = 13h register ‘f’ Data operation After Instruction If skip: REG = 13h W = ECh Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE CPFSEQ REG, 0 NEQUAL : EQUAL : Before Instruction PC Address = HERE W = ? REG = ? After Instruction If REG = W; PC = Address (EQUAL) If REG ≠ W; PC = Address (NEQUAL) DS39646C-page 338 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W), Operation: (f) – (W), skip if (f) > (W) skip if (f) < (W) (unsigned comparison) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 010a ffff ffff Encoding: 0110 000a ffff ffff Description: Compares the contents of data memory location ‘f’ to the contents of the W by Description: Compares the contents of data memory location ‘f’ to the contents of W by performing an unsigned subtraction. performing an unsigned subtraction. If the contents of ‘f’ are greater than the If the contents of ‘f’ are less than the contents of WREG, then the fetched contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f ≤ 95 (5Fh). See Note: 3 cycles if skip and followed Section26.2.3 “Byte-Oriented and by a 2-word instruction. Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 Words: 1 Decode Read Process No Cycles: 1(2) register ‘f’ Data operation Note: 3 cycles if skip and followed If skip: by a 2-word instruction. Q1 Q2 Q3 Q4 Q Cycle Activity: No No No No Q1 Q2 Q3 Q4 operation operation operation operation Decode Read Process No If skip and followed by 2-word instruction: register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 No No No No Example: HERE CPFSLT REG, 1 operation operation operation operation NLESS : No No No No LESS : operation operation operation operation Before Instruction PC = Address (HERE) Example: HERE CPFSGT REG, 0 W = ? NGREATER : After Instruction GREATER : If REG < W; PC = Address (LESS) Before Instruction If REG ≥ W; PC = Address (HERE) PC = Address (NLESS) W = ? After Instruction If REG > W; PC = Address (GREATER) If REG ≤ W; PC = Address (NGREATER) © 2008 Microchip Technology Inc. DS39646C-page 339

PIC18F8722 FAMILY DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: If [W<3:0> > 9] or [DC = 1] then a ∈ [0,1] (W<3:0>) + 6 → W<3:0>; else Operation: (f) – 1 → dest (W<3:0>) → W<3:0> Status Affected: C, DC, N, OV, Z If [W<7:4> > 9] or [C = 1] then Encoding: 0000 01da ffff ffff (W<7:4>) + 6 → W<7:4>; Description: Decrement register ‘f’. If ‘d’ is ‘0’, the C = 1; result is stored in W. If ‘d’ is ‘1’, the else result is stored back in register ‘f’ (W<7:4>) → W<7:4> (default). Status Affected: C If ‘a’ is ‘0’, the Access Bank is selected. Encoding: 0000 0000 0000 0111 If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Description: DAW adjusts the eight-bit value in W, resulting from the earlier addition of two If ‘a’ is ‘0’ and the extended instruction variables (each in packed BCD format) set is enabled, this instruction operates and produces a correct packed BCD in Indexed Literal Offset Addressing result. mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Words: 1 Bit-Oriented Instructions in Indexed Cycles: 1 Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read Process Write Q Cycle Activity: register W Data W Q1 Q2 Q3 Q4 Decode Read Process Write to Example 1: DAW register ‘f’ Data destination Before Instruction W = A5h C = 0 Example: DECF CNT, 1, 0 DC = 0 Before Instruction After Instruction CNT = 01h W = 05h Z = 0 C = 1 DC = 0 After Instruction CNT = 00h Example 2: Z = 1 Before Instruction W = CEh C = 0 DC = 0 After Instruction W = 34h C = 1 DC = 0 DS39646C-page 340 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, Operation: (f) – 1 → dest, skip if result = 0 skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). placed back in register ‘f’ (default). If the result is ‘0’, the next instruction If the result is not ‘0’, the next which is already fetched is discarded instruction which is already fetched is and a NOP is executed instead, making discarded and a NOP is executed it a two-cycle instruction. instead, making it a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction in Indexed Literal Offset Addressing set is enabled, this instruction operates mode whenever f ≤ 95 (5Fh). See in Indexed Literal Offset Addressing Section26.2.3 “Byte-Oriented and mode whenever f ≤ 95 (5Fh). See Bit-Oriented Instructions in Indexed Section26.2.3 “Byte-Oriented and Literal Offset Mode” for details. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed Cycles: 1(2) by a 2-word instruction. Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to If skip: register ‘f’ Data destination Q1 Q2 Q3 Q4 If skip: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation No No No No operation operation operation operation Example: HERE DECFSZ CNT, 1, 1 GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0 CONTINUE ZERO : NZERO : Before Instruction PC = Address (HERE) Before Instruction After Instruction TEMP = ? CNT = CNT – 1 After Instruction If CNT = 0; TEMP = TEMP – 1, PC = Address (CONTINUE) If TEMP = 0; If CNT ≠ 0; PC = Address (ZERO) PC = Address (HERE + 2) If TEMP ≠ 0; PC = Address (NZERO) © 2008 Microchip Technology Inc. DS39646C-page 341

PIC18F8722 FAMILY GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF f {,d {,a}} Operands: 0 ≤ k ≤ 1048575 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: k → PC<20:1> a ∈ [0,1] Status Affected: None Operation: (f) + 1 → dest Encoding: Status Affected: C, DC, N, OV, Z 1st word (k<7:0>) 1110 1111 k7kkk kkkk0 2nd word(k<19:8>) 1111 k19kkk kkkk kkkk8 Encoding: 0010 10da ffff ffff Description: GOTO allows an unconditional branch Description: The contents of register ‘f’ are anywhere within entire 2-Mbyte memory incremented. If ‘d’ is ‘0’, the result is range. The 20-bit value ‘k’ is loaded into placed in W. If ‘d’ is ‘1’, the result is PC<20:1>. GOTO is always a two-cycle placed back in register ‘f’ (default). instruction. If ‘a’ is ‘0’, the Access Bank is selected. Words: 2 If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Cycles: 2 If ‘a’ is ‘0’ and the extended instruction Q Cycle Activity: set is enabled, this instruction operates Q1 Q2 Q3 Q4 in Indexed Literal Offset Addressing Decode Read literal No Read literal mode whenever f ≤ 95 (5Fh). See ‘k’<7:0>, operation ‘k’<19:8>, Section26.2.3 “Byte-Oriented and Write to PC Bit-Oriented Instructions in Indexed No No No No Literal Offset Mode” for details. operation operation operation operation Words: 1 Cycles: 1 Example: GOTO THERE Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 PC = Address (THERE) Decode Read Process Write to register ‘f’ Data destination Example: INCF CNT, 1, 0 Before Instruction CNT = FFh Z = 0 C = ? DC = ? After Instruction CNT = 00h Z = 1 C = 1 DC = 1 DS39646C-page 342 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY INCFSZ Increment f, Skip if 0 INFSNZ Increment f, Skip if not 0 Syntax: INCFSZ f {,d {,a}} Syntax: INFSNZ f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest, Operation: (f) + 1 → dest, skip if result ≠ 0 skip if result = 0 Status Affected: None Status Affected: None Encoding: 0100 10da ffff ffff Encoding: 0011 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). placed back in register ‘f’. (default) If the result is not ‘0’, the next If the result is ‘0’, the next instruction instruction which is already fetched is which is already fetched is discarded discarded and a NOP is executed and a NOP is executed instead, making instead, making it a two-cycle it a two-cycle instruction. instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). GPR bank (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ‘f’ Data destination register ‘f’ Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE INCFSZ CNT, 1, 0 Example: HERE INFSNZ REG, 1, 0 NZERO : ZERO ZERO : NZERO Before Instruction Before Instruction PC = Address (HERE) PC = Address (HERE) After Instruction After Instruction CNT = CNT + 1 REG = REG + 1 If CNT = 0; If REG ≠ 0; PC = Address (ZERO) PC = Address (NZERO) If CNT ≠ 0; If REG = 0; PC = Address (NZERO) PC = Address (ZERO) © 2008 Microchip Technology Inc. DS39646C-page 343

PIC18F8722 FAMILY IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (W) .OR. k → W a ∈ [0,1] Status Affected: N, Z Operation: (W) .OR. (f) → dest Encoding: 0000 1001 kkkk kkkk Status Affected: N, Z Description: The contents of W are ORed with the Encoding: 0001 00da ffff ffff eight-bit literal ‘k’. The result is placed in W. Description: Inclusive OR W with register ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, Words: 1 the result is placed back in register ‘f’ Cycles: 1 (default). Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read Process Write to GPR bank (default). literal ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Example: IORLW 35h in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Before Instruction Section26.2.3 “Byte-Oriented and W = 9Ah Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. W = BFh Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: IORWF RESULT, 0, 1 Before Instruction RESULT = 13h W = 91h After Instruction RESULT = 13h W = 93h DS39646C-page 344 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF f {,d {,a}} Operands: 0 ≤ f ≤ 2 Operands: 0 ≤ f ≤ 255 0 ≤ k ≤ 4095 d ∈ [0,1] a ∈ [0,1] Operation: k → FSRf Operation: f → dest Status Affected: None Status Affected: N, Z Encoding: 1110 1110 00ff k11kkk 1111 0000 k7kkk kkkk Encoding: 0101 00da ffff ffff Description: The 12-bit literal ‘k’ is loaded into the Description: The contents of register ‘f’ are moved to file select register pointed to by ‘f’. a destination dependent upon the status of ‘d’. If ‘d’ is ‘0’, the result is Words: 2 placed in W. If ‘d’ is ‘1’, the result is Cycles: 2 placed back in register ‘f’ (default). Q Cycle Activity: Location ‘f’ can be anywhere in the 256-byte bank. Q1 Q2 Q3 Q4 Decode Read literal Process Write If ‘a’ is ‘0’, the Access Bank is selected. ‘k’ MSB Data literal ‘k’ If ‘a’ is ‘1’, the BSR is used to select the MSB to GPR bank (default). FSRfH If ‘a’ is ‘0’ and the extended instruction Decode Read literal Process Write literal set is enabled, this instruction operates ‘k’ LSB Data ‘k’ to FSRfL in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Example: LFSR 2, 3ABh Bit-Oriented Instructions in Indexed After Instruction Literal Offset Mode” for details. FSR2H = 03h FSR2L = ABh Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data W Example: MOVF REG, 0, 0 Before Instruction REG = 22h W = FFh After Instruction REG = 22h W = 22h © 2008 Microchip Technology Inc. DS39646C-page 345

PIC18F8722 FAMILY MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF f ,f Syntax: MOVLW k s d Operands: 0 ≤ f ≤ 4095 Operands: 0 ≤ k ≤ 255 s 0 ≤ f ≤ 4095 d Operation: k → BSR Operation: (f ) → f s d Status Affected: None Status Affected: None Encoding: 0000 0001 kkkk kkkk Encoding: Description: The eight-bit literal ‘k’ is loaded into the 1st word (source) 1100 ffff ffff ffffs Bank Select Register (BSR). The value 2nd word (destin.) 1111 ffff ffff ffffd of BSR<7:4> always remains ‘0’ Description: The contents of source register ‘f ’ are regardless of the value of k :k . s 7 4 moved to destination register ‘f ’. d Words: 1 Location of source ‘f ’ can be anywhere s in the 4096-byte data space (000h to Cycles: 1 FFFh) and location of destination ‘fd’ Q Cycle Activity: can also be anywhere from 000h to Q1 Q2 Q3 Q4 FFFh. Decode Read Process Write literal Either source or destination can be W literal ‘k’ Data ‘k’ to BSR (a useful special situation). MOVFF is particularly useful for Example: MOVLB 5 transferring a data memory location to a peripheral register (such as the transmit Before Instruction buffer or an I/O port). BSR Register = 02h After Instruction The MOVFF instruction cannot use the BSR Register = 05h PCL, TOSU, TOSH or TOSL as the destination register Words: 2 Cycles: 2 (3) Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation (src) Decode No No Write operation operation register ‘f’ No dummy (dest) read Example: MOVFF REG1, REG2 Before Instruction REG1 = 33h REG2 = 11h After Instruction REG1 = 33h REG2 = 33h DS39646C-page 346 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF f {,a} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: k → W Operation: (W) → f Status Affected: None Status Affected: None Encoding: 0000 1110 kkkk kkkk Encoding: 0110 111a ffff ffff Description: The eight-bit literal ‘k’ is loaded into W. Description: Move data from W to register ‘f’. Words: 1 Location ‘f’ can be anywhere in the Cycles: 1 256-byte bank. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read Process Write to GPR bank (default). literal ‘k’ Data W If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Example: MOVLW 5Ah in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See After Instruction Section26.2.3 “Byte-Oriented and W = 5Ah Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: MOVWF REG, 0 Before Instruction W = 4Fh REG = FFh After Instruction W = 4Fh REG = 4Fh © 2008 Microchip Technology Inc. DS39646C-page 347

PIC18F8722 FAMILY MULLW Multiply Literal with W MULWF Multiply W with f Syntax: MULLW k Syntax: MULWF f {,a} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) x k → PRODH:PRODL Operation: (W) x (f) → PRODH:PRODL Status Affected: None Status Affected: None Encoding: 0000 1101 kkkk kkkk Encoding: 0000 001a ffff ffff Description: An unsigned multiplication is carried out between the contents of W and the Description: An unsigned multiplication is carried out 8-bit literal ‘k’. The 16-bit result is between the contents of W and the placed in PRODH:PRODL register pair. register file location ‘f’. The 16-bit result is PRODH contains the high byte. stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W is unchanged. W and ‘f’ are unchanged. None of the status flags are affected. None of the status flags are affected. Note that neither Overflow nor Carry is Note that neither Overflow nor Carry is possible in this operation. A Zero result possible in this operation. A Zero result is is possible but not detected. possible but not detected. Words: 1 If ‘a’ is ‘0’, the Access Bank is selected. If Cycles: 1 ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction set Decode Read Process Write is enabled, this instruction operates in literal ‘k’ Data registers Indexed Literal Offset Addressing mode PRODH: whenever f ≤ 95 (5Fh). See PRODL Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Example: MULLW 0C4h Words: 1 Before Instruction W = E2h Cycles: 1 PRODH = ? Q Cycle Activity: PRODL = ? Q1 Q2 Q3 Q4 After Instruction W = E2h Decode Read Process Write PRODH = ADh register ‘f’ Data registers PRODL = 08h PRODH: PRODL Example: MULWF REG, 1 Before Instruction W = C4h REG = B5h PRODH = ? PRODL = ? After Instruction W = C4h REG = B5h PRODH = 8Ah PRODL = 94h DS39646C-page 348 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY NEGF Negate f NOP No Operation Syntax: NEGF f {,a} Syntax: NOP Operands: 0 ≤ f ≤ 255 Operands: None a ∈ [0,1] Operation: No operation Operation: (f) + 1 → f Status Affected: None Status Affected: N, OV, C, DC, Z Encoding: 0000 0000 0000 0000 Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx Description: Location ‘f’ is negated using two’s Description: No operation. complement. The result is placed in the Words: 1 data memory location ‘f’. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode No No No set is enabled, this instruction operates operation operation operation in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Example: Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed None. Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [3Ah] After Instruction REG = 1100 0110 [C6h] © 2008 Microchip Technology Inc. DS39646C-page 349

PIC18F8722 FAMILY POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) → bit bucket Operation: (PC + 2) → TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return Description: The PC + 2 is pushed onto the top of stack and is discarded. The TOS value the return stack. The previous TOS then becomes the previous value that value is pushed down on the stack. was pushed onto the return stack. This instruction allows implementing a This instruction is provided to enable software stack by modifying TOS and the user to properly manage the return then pushing it onto the return stack. stack to incorporate a software stack. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode PUSH No No Decode No POP TOS No PC + 2 onto operation operation operation value operation return stack Example: POP Example: PUSH GOTO NEW Before Instruction Before Instruction TOS = 345Ah TOS = 0031A2h PC = 0124h Stack (1 level down) = 014332h After Instruction After Instruction PC = 0126h TOS = 014332h TOS = 0126h PC = NEW Stack (1 level down) = 345Ah DS39646C-page 350 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY RCALL Relative Call RESET Reset Syntax: RCALL n Syntax: RESET Operands: -1024 ≤ n ≤ 1023 Operands: None Operation: (PC) + 2 → TOS, Operation: Reset all registers and flags that are (PC) + 2 + 2n → PC affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111 Description: Subroutine call with a jump up to 1K Description: This instruction provides a way to from the current location. First, return execute a MCLR Reset in software. address (PC + 2) is pushed onto the Words: 1 stack. Then, add the 2’s complement number ‘2n’ to the PC. Since the PC will Cycles: 1 have incremented to fetch the next Q Cycle Activity: instruction, the new address will be Q1 Q2 Q3 Q4 PC + 2 + 2n. This instruction is a Decode Start No No two-cycle instruction. reset operation operation Words: 1 Cycles: 2 Example: RESET Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 Registers= Reset Value Flags* = Reset Value Decode Read literal Process Write to PC ‘n’ Data PUSH PC to stack No No No No operation operation operation operation Example: HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS= Address (HERE + 2) © 2008 Microchip Technology Inc. DS39646C-page 351

PIC18F8722 FAMILY RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (TOS) → PC, Operation: k → W, 1 → GIE/GIEH or PEIE/GIEL, (TOS) → PC, if s = 1 PCLATU, PCLATH are unchanged (WS) → W, Status Affected: None (STATUSS) → STATUS, (BSRS) → BSR, Encoding: 0000 1100 kkkk kkkk PCLATU, PCLATH are unchanged Description: W is loaded with the eight-bit literal ‘k’. Status Affected: GIE/GIEH, PEIE/GIEL. The program counter is loaded from the top of the stack (the return address). Encoding: 0000 0000 0001 000s The high address latch (PCLATH) Description: Return from interrupt. Stack is popped remains unchanged. and Top-of-Stack (TOS) is loaded into Words: 1 the PC. Interrupts are enabled by setting either the high or low-priority Cycles: 2 global interrupt enable bit. If ‘s’ = 1, the Q Cycle Activity: contents of the shadow registers WS, Q1 Q2 Q3 Q4 STATUSS and BSRS are loaded into Decode Read Process POP PC their corresponding registers W, literal ‘k’ Data from stack, STATUS and BSR. If ‘s’ = 0, no update write to W of these registers occurs (default). No No No No Words: 1 operation operation operation operation Cycles: 2 Q Cycle Activity: Example: Q1 Q2 Q3 Q4 Decode No No POP PC CALL TABLE ; W contains table operation operation from stack ; offset value ; W now has Set GIEH or ; table value GIEL : No No No No TABLE operation operation operation operation ADDWF PCL ; W = offset RETLW k0 ; Begin table Example: RETFIE 1 RETLW k1 ; : After Interrupt : PC = TOS RETLW kn ; End of table W = WS BSR = BSRS STATUS = STATUSS Before Instruction GIE/GIEH, PEIE/GIEL = 1 W = 07h After Instruction W = value of kn DS39646C-page 352 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF f {,d {,a}} Operands: s ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (TOS) → PC, a ∈ [0,1] if s = 1 (WS) → W, Operation: (f<n>) → dest<n + 1>, (STATUSS) → STATUS, (f<7>) → C, (BSRS) → BSR, (C) → dest<0> PCLATU, PCLATH are unchanged Status Affected: C, N, Z Status Affected: None Encoding: 0011 01da ffff ffff Encoding: 0000 0000 0001 001s Description: The contents of register ‘f’ are rotated Description: Return from subroutine. The stack is one bit to the left through the Carry flag. popped and the top of the stack (TOS) If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is loaded into the program counter. If is ‘1’, the result is stored back in register ‘s’= 1, the contents of the shadow ‘f’ (default). registers WS, STATUSS and BSRS are If ‘a’ is ‘0’, the Access Bank is selected. loaded into their corresponding If ‘a’ is ‘1’, the BSR is used to select the registers W, STATUS and BSR. If GPR bank (default). ‘s’ = 0, no update of these registers occurs (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Words: 1 in Indexed Literal Offset Addressing Cycles: 2 mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Q Cycle Activity: Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4 Literal Offset Mode” for details. Decode No Process POP PC operation Data from stack C register f No No No No operation operation operation operation Words: 1 Cycles: 1 Q Cycle Activity: Example: RETURN Q1 Q2 Q3 Q4 After Instruction: Decode Read Process Write to PC = TOS register ‘f’ Data destination Example: RLCF REG, 0, 0 Before Instruction REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 1100 1100 C = 1 © 2008 Microchip Technology Inc. DS39646C-page 353

PIC18F8722 FAMILY RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry Syntax: RLNCF f {,d {,a}} Syntax: RRCF f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f<n>) → dest<n + 1>, Operation: (f<n>) → dest<n – 1>, (f<7>) → dest<0> (f<0>) → C, (C) → dest<7> Status Affected: N, Z Status Affected: C, N, Z Encoding: 0100 01da ffff ffff Encoding: 0011 00da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result Description: The contents of register ‘f’ are rotated is placed in W. If ‘d’ is ‘1’, the result is one bit to the right through the Carry stored back in register ‘f’ (default). flag. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in If ‘a’ is ‘0’, the Access Bank is selected. register ‘f’ (default). If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’ and the extended instruction GPR bank (default). set is enabled, this instruction operates in Indexed Literal Offset Addressing If ‘a’ is ‘0’ and the extended instruction mode whenever f ≤ 95 (5Fh). See set is enabled, this instruction operates Section26.2.3 “Byte-Oriented and in Indexed Literal Offset Addressing Bit-Oriented Instructions in Indexed mode whenever f ≤ 95 (5Fh). See Literal Offset Mode” for details. Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed register f Literal Offset Mode” for details. Words: 1 C register f Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Decode Read Process Write to Q Cycle Activity: register ‘f’ Data destination Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: RLNCF REG, 1, 0 Before Instruction REG = 1010 1011 Example: RRCF REG, 0, 0 After Instruction Before Instruction REG = 0101 0111 REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 0111 0011 C = 0 DS39646C-page 354 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY RRNCF Rotate Right f (no carry) SETF Set f Syntax: RRNCF f {,d {,a}} Syntax: SETF f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: FFh → f Operation: (f<n>) → dest<n – 1>, Status Affected: None (f<0>) → dest<7> Encoding: 0110 100a ffff ffff Status Affected: N, Z Description: The contents of the specified register Encoding: 0100 00da ffff ffff are set to FFh. Description: The contents of register ‘f’ are rotated If ‘a’ is ‘0’, the Access Bank is selected. one bit to the right. If ‘d’ is ‘0’, the result If ‘a’ is ‘1’, the BSR is used to select the is placed in W. If ‘d’ is ‘1’, the result is GPR bank (default). placed back in register ‘f’ (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank will be set is enabled, this instruction operates selected, overriding the BSR value. If ‘a’ in Indexed Literal Offset Addressing is ‘1’, then the bank will be selected as mode whenever f ≤ 95 (5Fh). See per the BSR value (default). Section26.2.3 “Byte-Oriented and If ‘a’ is ‘0’ and the extended instruction Bit-Oriented Instructions in Indexed set is enabled, this instruction operates Literal Offset Mode” for details. in Indexed Literal Offset Addressing Words: 1 mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 register f Decode Read Process Write register ‘f’ Data register ‘f’ Words: 1 Cycles: 1 Example: SETF REG,1 Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 REG = 5Ah After Instruction Decode Read Process Write to REG = FFh register ‘f’ Data destination Example 1: RRNCF REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = 1110 1011 Example 2: RRNCF REG, 0, 0 Before Instruction W = ? REG = 1101 0111 After Instruction W = 1110 1011 REG = 1101 0111 © 2008 Microchip Technology Inc. DS39646C-page 355

PIC18F8722 FAMILY SLEEP Enter Sleep Mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB f {,d {,a}} Operands: None Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: 00h → WDT, a ∈ [0,1] 0 → WDT postscaler, 1 → TO, Operation: (W) – (f) – (C) → dest 0 → PD Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0101 01da ffff ffff Encoding: 0000 0000 0000 0011 Description: Subtract register ‘f’ and Carry flag Description: The Power-Down status bit (PD) is (borrow) from W (2’s complement cleared. The Time-out status bit (TO) method). If ‘d’ is ‘0’, the result is stored in is set. The Watchdog Timer and its W. If ‘d’ is ‘1’, the result is stored in postscaler are cleared. register ‘f’ (default). The processor is put into Sleep mode If ‘a’ is ‘0’, the Access Bank is selected. If with the oscillator stopped. ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 1 set is enabled, this instruction operates in Q Cycle Activity: Indexed Literal Offset Addressing mode Q1 Q2 Q3 Q4 whenever f ≤ 95 (5Fh). See Decode No Process Go to Section26.2.3 “Byte-Oriented and operation Data Sleep Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Example: SLEEP Words: 1 Before Instruction Cycles: 1 TO = ? Q Cycle Activity: PD = ? Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to TO = 1 † register ‘f’ Data destination PD = 0 Example 1: SUBFWB REG, 1, 0 † If WDT causes wake-up, this bit is cleared. Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 DS39646C-page 356 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY SUBLW Subtract W from literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: k – (W) → W a ∈ [0,1] Status Affected: N, OV, C, DC, Z Operation: (f) – (W) → dest Encoding: 0000 1000 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: W is subtracted from the eight-bit Encoding: 0101 11da ffff ffff literal ‘k’. The result is placed in W. Description: Subtract W from register ‘f’ (2’s Words: 1 complement method). If ‘d’ is ‘0’, the Cycles: 1 result is stored in W. If ‘d’ is ‘1’, the result Q Cycle Activity: is stored back in register ‘f’ (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is selected. Decode Read Process Write to If ‘a’ is ‘1’, the BSR is used to select the literal ‘k’ Data W GPR bank (default). If ‘a’ is ‘0’ and the extended instruction Example 1: SUBLW 02h set is enabled, this instruction operates Before Instruction in Indexed Literal Offset Addressing W = 01h mode whenever f ≤ 95 (5Fh). See C = ? Section26.2.3 “Byte-Oriented and After Instruction Bit-Oriented Instructions in Indexed W = 01h Literal Offset Mode” for details. C = 1 ; result is positive Z = 0 Words: 1 N = 0 Cycles: 1 Example 2: SUBLW 02h Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 W = 02h C = ? Decode Read Process Write to After Instruction register ‘f’ Data destination W = 00h C = 1 ; result is zero Example 1: SUBWF REG, 1, 0 Z = 1 Before Instruction N = 0 REG = 3 W = 2 Example 3: SUBLW 02h C = ? Before Instruction After Instruction W = 03h REG = 1 C = ? W = 2 After Instruction C = 1 ; result is positive W = FFh ; (2’s complement) Z = 0 C = 0 ; result is negative N = 0 Z = 0 Example 2: SUBWF REG, 0, 0 N = 1 Before Instruction REG = 2 W = 2 C = ? After Instruction REG = 2 W = 0 C = 1 ; result is zero Z = 1 N = 0 Example 3: SUBWF REG, 1, 0 Before Instruction REG = 1 W = 2 C = ? After Instruction REG = FFh ;(2’s complement) W = 2 C = 0 ; result is negative Z = 0 N = 1 © 2008 Microchip Technology Inc. DS39646C-page 357

PIC18F8722 FAMILY SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB f {,d {,a}} Syntax: SWAPF f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) – (C) → dest Operation: (f<3:0>) → dest<7:4>, Status Affected: N, OV, C, DC, Z (f<7:4>) → dest<3:0> Encoding: 0101 10da ffff ffff Status Affected: None Description: Subtract W and the Carry flag (borrow) Encoding: 0011 10da ffff ffff from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is stored Description: The upper and lower nibbles of register in W. If ‘d’ is ‘1’, the result is stored back ‘f’ are exchanged. If ‘d’ is ‘0’, the result in register ‘f’ (default). is placed in W. If ‘d’ is ‘1’, the result is placed in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See in Indexed Literal Offset Addressing Section26.2.3 “Byte-Oriented and mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to Example 1: SUBWFB REG, 1, 0 register ‘f’ Data destination Before Instruction REG = 19h (0001 1001) Example: SWAPF REG, 1, 0 W = 0Dh (0000 1101) C = 1 Before Instruction After Instruction REG = 53h REG = 0Ch (0000 1011) After Instruction W = 0Dh (0000 1101) REG = 35h C = 1 Z = 0 N = 0 ; result is positive Example 2: SUBWFB REG, 0, 0 Before Instruction REG = 1Bh (0001 1011) W = 1Ah (0001 1010) C = 0 After Instruction REG = 1Bh (0001 1011) W = 00h C = 1 Z = 1 ; result is zero N = 0 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 03h (0000 0011) W = 0Eh (0000 1101) C = 1 After Instruction REG = F5h (1111 0100) ; [2’s comp] W = 0Eh (0000 1101) C = 0 Z = 0 N = 1 ; result is negative DS39646C-page 358 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD *+ ; Operands: None Before Instruction TABLAT = 55h Operation: if TBLRD *, TBLPTR = 00A356h (Prog Mem (TBLPTR)) → TABLAT; MEMORY(00A356h) = 34h TBLPTR – No Change After Instruction if TBLRD *+, TABLAT = 34h (Prog Mem (TBLPTR)) → TABLAT; TBLPTR = 00A357h (TBLPTR) + 1 → TBLPTR Example 2: TBLRD +* ; if TBLRD *-, (Prog Mem (TBLPTR)) → TABLAT; Before Instruction (TBLPTR) – 1 → TBLPTR TABLAT = AAh TBLPTR = 01A357h if TBLRD +*, MEMORY(01A357h) = 12h (TBLPTR) + 1 → TBLPTR; MEMORY(01A358h) = 34h (Prog Mem (TBLPTR)) → TABLAT After Instruction Status Affected: None TABLAT = 34h TBLPTR = 01A358h Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR<0> = 0:Least Significant Byte of Program Memory Word TBLPTR<0> = 1:Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No operation No No operation operation (Read Program operation (Write Memory) TABLAT) © 2008 Microchip Technology Inc. DS39646C-page 359

PIC18F8722 FAMILY TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Before Instruction Operation: if TBLWT*, TABLAT = 55h (TABLAT) → Holding Register; TBLPTR = 00A356h HOLDING REGISTER TBLPTR – No Change (00A356h) = FFh if TBLWT*+, After Instructions (table write completion) (TABLAT) → Holding Register; TABLAT = 55h (TBLPTR) + 1 → TBLPTR TBLPTR = 00A357h if TBLWT*-, HOLDING REGISTER (TABLAT) → Holding Register; (00A356h) = 55h (TBLPTR) – 1 → TBLPTR Example 2: TBLWT +*; if TBLWT+*, Before Instruction (TBLPTR) + 1 → TBLPTR; TABLAT = 34h (TABLAT) → Holding Register TBLPTR = 01389Ah Status Affected: None HOLDING REGISTER (01389Ah) = FFh Encoding: 0000 0000 0000 11nn HOLDING REGISTER nn=0 * (01389Bh) = FFh =1 *+ After Instruction (table write completion) =2 *- TABLAT = 34h =3 +* TBLPTR = 01389Bh HOLDING REGISTER Description: This instruction uses the 3 LSBs of (01389Ah) = FFh TBLPTR to determine which of the HOLDING REGISTER 8 holding registers the TABLAT is written (01389Bh) = 34h to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section5.0 “Memory Organization” for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR<0> = 0:Least Significant Byte of Program Memory Word TBLPTR<0> = 1:Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operationoperation operation No No No No operationoperationoperation operation (Read (Write to TABLAT) Holding Register) DS39646C-page 360 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255 a ∈ [0,1] Operation: (W) .XOR. k → W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: 0000 1010 kkkk kkkk Encoding: 0110 011a ffff ffff Description: The contents of W are XORed with Description: If ‘f’ = 0, the next instruction fetched the 8-bit literal ‘k’. The result is placed during the current instruction execution in W. is discarded and a NOP is executed, Words: 1 making this a two-cycle instruction. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode Read Process Write to set is enabled, this instruction operates literal ‘k’ Data W in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Example: XORLW 0AFh Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Before Instruction Literal Offset Mode” for details. W = B5h After Instruction Words: 1 W = 1Ah Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE TSTFSZ CNT, 1 NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction If CNT = 00h, PC = Address (ZERO) If CNT ≠ 00h, PC = Address (NZERO) © 2008 Microchip Technology Inc. DS39646C-page 361

PIC18F8722 FAMILY XORWF Exclusive OR W with f Syntax: XORWF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: N, Z Encoding: 0001 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: XORWF REG, 1, 0 Before Instruction REG = AFh W = B5h After Instruction REG = 1Ah W = B5h DS39646C-page 362 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 26.2 Extended Instruction Set A summary of the instructions in the extended instruc- tion set is provided in Table26-3. Detailed descriptions In addition to the standard 75 instructions of the PIC18 are provided in Section26.2.2 “Extended Instruction instruction set, the PIC18F8722 family of devices also Set”. The opcode field descriptions in Table26-1 provide an optional extension to the core CPU function- (page322) apply to both the standard and extended ality. The added features include eight additional PIC18 instruction sets. instructions that augment Indirect and Indexed Addressing operations and the implementation of Note: The instruction set extension and the Indexed Literal Offset Addressing for many of the Indexed Literal Offset Addressing mode standard PIC18 instructions. were designed for optimizing applications written in C; the user may likely never use The additional features of the extended instruction set these instructions directly in assembler. are enabled by default. To enable them, users must set The syntax for these commands is the XINST Configuration bit. provided as a reference for users who may The instructions in the extended set can all be be reviewing code that has been classified as literal operations, which either manipulate generated by a compiler. the File Select Registers, or use them for Indexed Addressing. Two of the instructions, ADDFSR and 26.2.1 EXTENDED INSTRUCTION SYNTAX SUBFSR, each have an additional special instantiation Most of the extended instructions use indexed argu- for using FSR2. These versions (ADDULNK and ments, using one of the File Select Registers and some SUBULNK) allow for automatic return after execution. offset to specify a source or destination register. When The extended instructions are specifically implemented an argument for an instruction serves as part of to optimize re-entrant program code (that is, code that Indexed Addressing, it is enclosed in square brackets is recursive or that uses a software stack) written in (“[ ]”). This is done to indicate that the argument is used high-level languages, particularly C. Among other as an index or offset. The MPASM™ Assembler will things, they allow users working in high-level flag an error if it determines that an index or offset value languages to perform certain operations on data is not bracketed. structures more efficiently. These include: When the extended instruction set is enabled, brackets • dynamic allocation and deallocation of software are also used to indicate index arguments in stack space when entering and leaving byte-oriented and bit-oriented instructions. This is in subroutines addition to other changes in their syntax. For more • function pointer invocation details, see Section26.2.3.1 “Extended Instruction • software Stack Pointer manipulation Syntax with Standard PIC18 Commands”. • manipulation of variables located in a software Note: In the past, square brackets have been stack used to denote optional arguments in the PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces (“{ }”). TABLE 26-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Operands Affected MSb LSb ADDFSR f, k Add Literal to FSR 1 1110 1000 ffkk kkkk None ADDULNK k Add Literal to FSR2 and Return 2 1110 1000 11kk kkkk None CALLW Call Subroutine using WREG 2 0000 0000 0001 0100 None MOVSF zs, fd Move zs (source) to 1st word 2 1110 1011 0zzz zzzz None fd (destination) 2nd word 1111 ffff ffff ffff MOVSS zs, zd Move zs (source) to 1st word 2 1110 1011 1zzz zzzz None zd (destination) 2nd word 1111 xxxx xzzz zzzz PUSHL k Store Literal at FSR2, 1 1110 1010 kkkk kkkk None Decrement FSR2 SUBFSR f, k Subtract Literal from FSR 1 1110 1001 ffkk kkkk None SUBULNK k Subtract Literal from FSR2 and 2 1110 1001 11kk kkkk None Return © 2008 Microchip Technology Inc. DS39646C-page 363

PIC18F8722 FAMILY 26.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operation: FSR2 + k → FSR2, Operation: FSR(f) + k → FSR(f) (TOS) → PC Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk Description: The 6-bit literal ‘k’ is added to the Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’. contents of FSR2. A RETURN is then Words: 1 executed by loading the PC with the Cycles: 1 TOS. Q Cycle Activity: The instruction takes two cycles to Q1 Q2 Q3 Q4 execute; a NOP is performed during the second cycle. Decode Read Process Write to literal ‘k’ Data FSR This may be thought of as a special case of the ADDFSR instruction, where f = 3 (binary ‘11’); it operates Example: ADDFSR 2, 23h only on FSR2. Before Instruction Words: 1 FSR2 = 03FFh Cycles: 2 After Instruction Q Cycle Activity: FSR2 = 0422h Q1 Q2 Q3 Q4 Decode Read Process Write to literal ‘k’ Data FSR No No No No Operation Operation Operation Operation Example: ADDULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 0422h PC = (TOS) Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). DS39646C-page 364 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY CALLW Subroutine Call using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [z ], f s d Operands: None Operands: 0 ≤ z ≤ 127 s 0 ≤ f ≤ 4095 Operation: (PC + 2) → TOS, d (W) → PCL, Operation: ((FSR2) + z ) → f s d (PCLATH) → PCH, Status Affected: None (PCLATU) → PCU Encoding: Status Affected: None 1st word (source) 1110 1011 0zzz zzzzs Encoding: 0000 0000 0001 0100 2nd word (destin.) 1111 ffff ffff ffffd Description First, the return address (PC + 2) is Description: The contents of the source register are pushed onto the return stack. Next, the moved to destination register ‘f ’. The d contents of W are written to PCL; the actual address of the source register is existing value is discarded. Then, the determined by adding the 7-bit literal contents of PCLATH and PCLATU are offset ‘z ’, in the first word, to the value s latched into PCH and PCU, of FSR2. The address of the destination respectively. The second cycle is register is specified by the 12-bit literal executed as a NOP instruction while the ‘fd’ in the second word. Both addresses new next instruction is fetched. can be anywhere in the 4096-byte data space (000h to FFFh). Unlike CALL, there is no option to update W, STATUS or BSR. The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the Words: 1 destination register. Cycles: 2 If the resultant source address points to Q Cycle Activity: an indirect addressing register, the Q1 Q2 Q3 Q4 value returned will be 00h. Decode Read Push PC to No Words: 2 WREG stack operation Cycles: 2 No No No No operation operation operation operation Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine Determine Read Example: HERE CALLW source addr source addr source reg Before Instruction Decode No No Write PC = address (HERE) operation operation register ‘f’ PCLATH = 10h No dummy (dest) PCLATU = 00h W = 06h read After Instruction PC = 001006h TOS = address (HERE + 2) Example: MOVSF [05h], REG2 PCLATH = 10h PCLATU = 00h Before Instruction W = 06h FSR2 = 80h Contents of 85h = 33h REG2 = 11h After Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 33h © 2008 Microchip Technology Inc. DS39646C-page 365

PIC18F8722 FAMILY MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0 ≤ zs ≤ 127 Operands: 0 ≤ k ≤ 255 0 ≤ z ≤ 127 d Operation: k → (FSR2), Operation: ((FSR2) + zs) → ((FSR2) + zd) FSR2 – 1→ FSR2 Status Affected: None Status Affected: None Encoding: Encoding: 1111 1010 kkkk kkkk 1st word (source) 1110 1011 1zzz zzzzs 2nd word (dest.) 1111 xxxx xzzz zzzzd Description: The 8-bit literal ‘k’ is written to the data memory address specified by FSR2. Description The contents of the source register are FSR2 is decremented by 1 after the moved to the destination register. The operation. addresses of the source and destination registers are determined by adding the This instruction allows users to push 7-bit literal offsets ‘z ’ or ‘z ’, values onto a software stack. s d respectively, to the value of FSR2. Both Words: 1 registers can be located anywhere in the 4096-byte data memory space Cycles: 1 (000h to FFFh). Q Cycle Activity: The MOVSS instruction cannot use the Q1 Q2 Q3 Q4 PCL, TOSU, TOSH or TOSL as the Decode Read ‘k’ Process Write to destination register. data destination If the resultant source address points to an Indirect Addressing register, the value returned will be 00h. If the Example: PUSHL 08h resultant destination address points to Before Instruction an Indirect Addressing register, the FSR2H:FSR2L = 01ECh instruction will execute as a NOP. Memory (01ECh) = 00h Words: 2 After Instruction Cycles: 2 FSR2H:FSR2L = 01EBh Memory (01ECh) = 08h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine Determine Read source addr source addr source reg Decode Determine Determine Write dest addr dest addr to dest reg Example: MOVSS [05h], [06h] Before Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 11h After Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 33h DS39646C-page 366 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operation: FSR2 – k → FSR2 Operation: FSRf – k → FSRf (TOS) → PC Status Affected: None Status Affected: None Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk Description: The 6-bit literal ‘k’ is subtracted from Description: The 6-bit literal ‘k’ is subtracted from the the contents of the FSR specified contents of the FSR2. A RETURN is then by ‘f’. executed by loading the PC with the Words: 1 TOS. Cycles: 1 The instruction takes two cycles to Q Cycle Activity: execute; a NOP is performed during the second cycle. Q1 Q2 Q3 Q4 Decode Read Process Write to This may be thought of as a special case register ‘f’ Data destination of the SUBFSR instruction, where f = 3 (binary ‘11’); it operates only on FSR2. Words: 1 Example: SUBFSR 2, 23h Cycles: 2 Before Instruction Q Cycle Activity: FSR2 = 03FFh Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to FSR2 = 03DCh register ‘f’ Data destination No No No No Operation Operation Operation Operation Example: SUBULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 03DCh PC = (TOS) © 2008 Microchip Technology Inc. DS39646C-page 367

PIC18F8722 FAMILY 26.2.3 BYTE-ORIENTED AND 26.2.3.1 Extended Instruction Syntax with BIT-ORIENTED INSTRUCTIONS IN Standard PIC18 Commands INDEXED LITERAL OFFSET MODE When the extended instruction set is enabled, the file Note: Enabling the PIC18 instruction set exten- register argument ‘f’ in the standard byte-oriented and sion may cause legacy applications to bit-oriented commands is replaced with the literal offset behave erratically or fail entirely. value ‘k’. As already noted, this occurs only when ‘f’ is less than or equal to 5Fh. When an offset value is used, In addition to eight new commands in the extended set, it must be indicated by square brackets (“[ ]”). As with enabling the extended instruction set also enables the extended instructions, the use of brackets indicates Indexed Literal Offset Addressing (Section5.5.1 to the compiler that the value is to be interpreted as an “Indexed Addressing with Literal Offset”). This has index or an offset. Omitting the brackets, or using a a significant impact on the way that many commands of value greater than 5Fh within the brackets, will the standard PIC18 instruction set are interpreted. generate an error in the MPASM Assembler. When the extended set is disabled, addresses embed- If the index argument is properly bracketed for Indexed ded in opcodes are treated as literal memory locations: Literal Offset Addressing, the Access RAM argument is either as a location in the Access Bank (a = 0) or in a never specified; it will automatically be assumed to be GPR bank designated by the BSR (a = 1). When the ‘0’. This is in contrast to standard operation (extended extended instruction set is enabled and a = 0, however, instruction set disabled), when ‘a’ is set on the basis of a file register argument of 5Fh or less is interpreted as the target address. Declaring the Access RAM bit in an offset from the pointer value in FSR2 and not as a this mode will also generate an error in the MPASM literal address. For practical purposes, this means that Assembler. all instructions that use the Access RAM bit as an argument – that is, all byte-oriented and bit-oriented The destination argument ‘d’ functions as before. instructions, or almost half of the core PIC18 instruc- In the latest versions of the MPASM Assembler, tions – may behave differently when the extended language support for the extended instruction set must instruction set is enabled. be explicitly invoked. This is done with either the When the content of FSR2 is 00h, the boundaries of the command line option, /y, or the PE directive in the source listing. Access RAM are essentially remapped to their original values. This may be useful in creating 26.2.4 CONSIDERATIONS WHEN backward-compatible code. If this technique is used, it ENABLING THE EXTENDED may be necessary to save the value of FSR2 and INSTRUCTION SET restore it when moving back and forth between C and assembly routines in order to preserve the Stack It is important to note that the extensions to the instruc- Pointer. Users must also keep in mind the syntax tion set may not be beneficial to all users. In particular, requirements of the extended instruction set (see users who are not writing code that uses a software Section26.2.3.1 “Extended Instruction Syntax with stack may not benefit from using the extensions to the Standard PIC18 Commands”). instruction set. Although the Indexed Literal Offset Addressing mode Additionally, the Indexed Literal Offset Addressing can be very useful for dynamic stack and pointer mode may create issues with legacy applications manipulation, it can also be very annoying if a simple written to the PIC18 assembler. This is because arithmetic operation is carried out on the wrong instructions in the legacy code may attempt to address register. Users who are accustomed to the PIC18 pro- registers in the Access Bank below 5Fh. Since these gramming must keep in mind that, when the extended addresses are interpreted as literal offsets to FSR2 instruction set is enabled, register addresses of 5Fh or when the instruction set extension is enabled, the less are used for Indexed Literal Offset Addressing. application may read or write to the wrong data Representative examples of typical byte-oriented and addresses. bit-oriented instructions in the Indexed Literal Offset When porting an application to the PIC18F8722 family, Addressing mode are provided on the following page to it is very important to consider the type of code. A large, show how execution is affected. The operand condi- re-entrant application that is written in C and would tions shown in the examples are applicable to all benefit from efficient compilation will do well when instructions of these types. using the instruction set extensions. Legacy applica- tions that heavily use the Access Bank will most likely not benefit from using the extended instruction set. DS39646C-page 368 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY ADD W to Indexed Bit Set Indexed ADDWF BSF (Indexed Literal Offset mode) (Indexed Literal Offset mode) Syntax: ADDWF [k] {,d} Syntax: BSF [k], b Operands: 0 ≤ k ≤ 95 Operands: 0 ≤ f ≤ 95 d ∈ [0,1] 0 ≤ b ≤ 7 Operation: (W) + ((FSR2) + k) → dest Operation: 1 → ((FSR2) + k)<b> Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: 0010 01d0 kkkk kkkk Encoding: 1000 bbb0 kkkk kkkk Description: The contents of W are added to the Description: Bit ‘b’ of the register indicated by FSR2, contents of the register indicated by offset by the value ‘k’, is set. FSR2, offset by the value ‘k’. Words: 1 If ‘d’ is ‘0’, the result is stored in W. If ‘d’ Cycles: 1 is ‘1’, the result is stored back in register ‘f’ (default). Q Cycle Activity: Q1 Q2 Q3 Q4 Words: 1 Decode Read Process Write to Cycles: 1 register ‘f’ Data destination Q Cycle Activity: Q1 Q2 Q3 Q4 Example: BSF [FLAG_OFST], 7 Decode Read ‘k’ Process Write to Before Instruction Data destination FLAG_OFST = 0Ah FSR2 = 0A00h Contents Example: ADDWF [OFST],0 of 0A0Ah = 55h Before Instruction After Instruction W = 17h Contents OFST = 2Ch of 0A0Ah = D5h FSR2 = 0A00h Contents of 0A2Ch = 20h After Instruction Set Indexed SETF W = 37h (Indexed Literal Offset mode) Contents of 0A2Ch = 20h Syntax: SETF [k] Operands: 0 ≤ k ≤ 95 Operation: FFh → ((FSR2) + k) Status Affected: None Encoding: 0110 1000 kkkk kkkk Description: The contents of the register indicated by FSR2, offset by ‘k’, are set to FFh. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read ‘k’ Process Write Data register Example: SETF [OFST] Before Instruction OFST = 2Ch FSR2 = 0A00h Contents of 0A2Ch = 00h After Instruction Contents of 0A2Ch = FFh © 2008 Microchip Technology Inc. DS39646C-page 369

PIC18F8722 FAMILY 26.2.5 SPECIAL CONSIDERATIONS WITH To develop software for the extended instruction set, MICROCHIP MPLAB® IDE TOOLS the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). The latest versions of Microchip’s software tools have Depending on the environment being used, this may be been designed to fully support the extended instruction done in several ways: set for the PIC18F8722 family. This includes the • A menu option or dialog box within the MPLAB C18 C Compiler, MPASM assembly language environment that allows the user to configure the and MPLAB Integrated Development Environment language tool and its settings for the project (IDE). • A command line option When selecting a target device for software • A directive in the source code development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for These options vary between different compilers, the XINST Configuration is ‘0’, disabling the extended assemblers and development environments. Users are instruction set and Indexed Literal Offset Addressing encouraged to review the documentation accompany- mode. For proper execution of applications developed ing their development systems for the appropriate to take advantage of the extended instruction set, information. XINST must be set during programming. DS39646C-page 370 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 27.0 DEVELOPMENT SUPPORT 27.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers are supported with a full range of hardware and software development tools: The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- • Integrated Development Environment - MPLAB® IDE Software controller market. The MPLAB IDE is a Windows® operating system-based application that contains: • Assemblers/Compilers/Linkers - MPASMTM Assembler • A single graphical interface to all debugging tools - MPLAB C18 and MPLAB C30 C Compilers - Simulator - MPLINKTM Object Linker/ - Programmer (sold separately) MPLIBTM Object Librarian - Emulator (sold separately) - MPLAB ASM30 Assembler/Linker/Library - In-Circuit Debugger (sold separately) • Simulators • A full-featured editor with color-coded context - MPLAB SIM Software Simulator • A multiple project manager • Emulators • Customizable data windows with direct edit of - MPLAB ICE 2000 In-Circuit Emulator contents - MPLAB REAL ICE™ In-Circuit Emulator • High-level source code debugging • In-Circuit Debugger • Visual device initializer for easy register - MPLAB ICD 2 initialization • Device Programmers • Mouse over variable inspection - PICSTART® Plus Development Programmer • Drag and drop variables from source to watch windows - MPLAB PM3 Device Programmer • Extensive on-line help - PICkit™ 2 Development Programmer • Integration of select third party tools, such as • Low-Cost Demonstration and Development HI-TECH Software C Compilers and IAR Boards and Evaluation Kits C Compilers The MPLAB IDE allows you to: • Edit your source files (either assembly or C) • One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2008 Microchip Technology Inc. DS39646C-page 371

PIC18F8722 FAMILY 27.2 MPASM Assembler 27.5 MPLAB ASM30 Assembler, Linker and Librarian The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. MPLAB ASM30 Assembler produces relocatable The MPASM Assembler generates relocatable object machine code from symbolic assembly language for files for the MPLINK Object Linker, Intel® standard HEX dsPIC30F devices. MPLAB C30 C Compiler uses the files, MAP files to detail memory usage and symbol assembler to produce its object file. The assembler reference, absolute LST files that contain source lines generates relocatable object files that can then be and generated machine code and COFF files for archived or linked with other relocatable object files and debugging. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler features include: • Support for the entire dsPIC30F instruction set • Integration into MPLAB IDE projects • Support for fixed-point and floating-point data • User-defined macros to streamline • Command line interface assembly code • Rich directive set • Conditional assembly for multi-purpose • Flexible macro language source files • MPLAB IDE compatibility • Directives that allow complete control over the assembly process 27.6 MPLAB SIM Software Simulator 27.3 MPLAB C18 and MPLAB C30 The MPLAB SIM Software Simulator allows code C Compilers development in a PC-hosted environment by simulat- ing the PIC MCUs and dsPIC® DSCs on an instruction The MPLAB C18 and MPLAB C30 Code Development level. On any given instruction, the data areas can be Systems are complete ANSI C compilers for examined or modified and stimuli can be applied from Microchip’s PIC18 and PIC24 families of microcon- a comprehensive stimulus controller. Registers can be trollers and the dsPIC30 and dsPIC33 family of digital logged to files for further run-time analysis. The trace signal controllers. These compilers provide powerful buffer and logic analyzer display extend the power of integration capabilities, superior code optimization and the simulator to record and track program execution, ease of use not found with other compilers. actions on I/O, most peripherals and internal registers. For easy source level debugging, the compilers provide The MPLAB SIM Software Simulator fully supports symbol information that is optimized to the MPLAB IDE symbolic debugging using the MPLAB C18 and debugger. MPLAB C30 CCompilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator 27.4 MPLINK Object Linker/ offers the flexibility to develop and debug code outside MPLIB Object Librarian of the hardware laboratory environment, making it an excellent, economical software development tool. The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS39646C-page 372 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 27.7 MPLAB ICE 2000 27.9 MPLAB ICD 2 In-Circuit Debugger High-Performance Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a In-Circuit Emulator powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed The MPLAB ICE 2000 In-Circuit Emulator is intended USB interface. This tool is based on the Flash PIC to provide the product development engineer with a MCUs and can be used to develop for these and other complete microcontroller design tool set for PIC PIC MCUs and dsPIC DSCs. The MPLAB ICD2 utilizes microcontrollers. Software control of the MPLAB ICE the in-circuit debugging capability built into theFlash 2000 In-Circuit Emulator is advanced by the MPLAB devices. This feature, along with Microchip’s In-Circuit Integrated Development Environment, which allows Serial ProgrammingTM (ICSPTM) protocol, offers cost- editing, building, downloading and source debugging effective, in-circuit Flash debugging from the graphical from a single environment. user interface of the MPLAB Integrated Development The MPLAB ICE 2000 is a full-featured emulator Environment. This enables a designer to develop and system with enhanced trace, trigger and data monitor- debug source code by setting breakpoints, single step- ing features. Interchangeable processor modules allow ping and watching variables, and CPU status and the system to be easily reconfigured for emulation of peripheral registers. Running at full speed enables different processors. The architecture of the MPLAB testing hardware and applications in real time. MPLAB ICE 2000 In-Circuit Emulator allows expansion to ICD2 also serves as a development programmer for support new PIC microcontrollers. selected PIC devices. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with 27.10 MPLAB PM3 Device Programmer advanced features that are typically found on more The MPLAB PM3 Device Programmer is a universal, expensive development tools. The PC platform and Microsoft® Windows® 32-bit operating system were CE compliant device programmer with programmable chosen to best make these features available in a voltage verification at VDDMIN and VDDMAX for simple, unified application. maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various 27.8 MPLAB REAL ICE In-Circuit package types. The ICSP™ cable assembly is included Emulator System as a standard item. In Stand-Alone mode, the MPLAB MPLAB REAL ICE In-Circuit Emulator System is PM3 Device Programmer can read, verify and program Microchip’s next generation high-speed emulator for PIC devices without a PC connection. It can also set Microchip Flash DSC and MCU devices. It debugs and code protection in this mode. The MPLAB PM3 programs PIC® Flash MCUs and dsPIC® Flash DSCs connects to the host PC via an RS-232 or USB cable. with the easy-to-use, powerful graphical user interface of The MPLAB PM3 has high-speed communications and the MPLAB Integrated Development Environment (IDE), optimized algorithms for quick programming of large included with each kit. memory devices and incorporates an SD/MMC card for file storage and secure data applications. The MPLAB REAL ICE probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high-speed, noise tolerant, Low- Voltage Differential Signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software break- points and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2008 Microchip Technology Inc. DS39646C-page 373

PIC18F8722 FAMILY 27.11 PICSTART® Plus Development 27.13 Demonstration, Development and Programmer Evaluation Boards The PICSTART® Plus Development Programmer is an A wide variety of demonstration, development and easy-to-use, low-cost, prototype programmer. It evaluation boards for various PIC MCUs and dsPIC connects to the PC via a COM (RS-232) port. MPLAB DSCs allows quick application development on fully func- Integrated Development Environment software makes tional systems. Most boards include prototyping areas for using the programmer simple and efficient. The adding custom circuitry and provide application firmware PICSTART Plus Development Programmer supports and source code for examination and modification. most PIC devices in DIP packages up to 40 pins. The boards support a variety of features, including LEDs, Larger pin count devices, such as the PIC16C92X and temperature sensors, switches, speakers, RS-232 PIC17C76X, may be supported with an adapter socket. interfaces, LCD displays, potentiometers and additional The PICSTART Plus Development Programmer is CE EEPROM memory. compliant. The demonstration and development boards can be used in teaching environments, for prototyping custom 27.12 PICkit™ 2 Development circuits and for learning about various microcontroller Programmer applications. The PICkit™ 2 Development Programmer is a low-cost In addition to the PICDEM™ and dsPICDEM™ demon- programmer and selected Flash device debugger with stration/development board series of circuits, Microchip an easy-to-use interface for programming many of has a line of evaluation kits and demonstration software Microchip’s baseline, mid-range and PIC18F families of for analog filter design, KEELOQ® security ICs, CAN, Flash memory microcontrollers. The PICkit 2 Starter Kit IrDA®, PowerSmart battery management, SEEVAL® includes a prototyping development board, twelve evaluation system, Sigma-Delta ADC, flow rate sequential lessons, software and HI-TECH’s PICC™ sensing, plus many more. Lite C compiler, and is designed to help get up to speed Check the Microchip web page (www.microchip.com) quickly using PIC® microcontrollers. The kit provides for the complete list of demonstration, development everything needed to program, evaluate and develop and evaluation kits. applications using Microchip’s powerful, mid-range Flash memory family of microcontrollers. DS39646C-page 374 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 28.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR)...................................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2).........................................................................................0V to +13.25V Total power dissipation (Note 1)...............................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300mA Maximum current into VDD pin..............................................................................................................................250mA Input clamp current, IIK (VI < 0 or VI > VDD)......................................................................................................................±20mA Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................±20mA Maximum output current sunk by any I/O pin..........................................................................................................25mA Maximum output current sourced by any I/O pin....................................................................................................25mA Maximum current sunk by all ports.......................................................................................................................200mA Maximum current sourced by all ports..................................................................................................................200mA Note1: Power dissipation is calculated as follows: Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL) 2: Voltage spikes below VSS at the RG5/MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the RG5/MCLR/ VPP pin, rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2008 Microchip Technology Inc. DS39646C-page 375

PIC18F8722 FAMILY FIGURE 28-1: PIC18F8722 DEVICE FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18F6627/6622/6627/6722 PIC18F8527/8622/8627/8722 4.5V e g 4.2V a 4.0V t l o 3.5V V 3.0V 2.5V 2.0V FMAX Frequency FMAX = 20MHz in 8-bit External Memory mode. FMAX = 40MHz in all other modes. FIGURE 28-2: PIC18F8722 DEVICE FAMILY VOLTAGE-FREQUENCY GRAPH (EXTENDED) 6.0V 5.5V PIC18F6627/6622/6627/6722 5.0V PIC18F8527/8622/8627/8722 4.5V e g 4.2V a 4.0V t l o 3.5V V 3.0V 2.5V 2.0V FMAX Frequency FMAX = 20MHz in 8-bit External Memory mode. FMAX = 25MHz in all other modes. DS39646C-page 376 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 28-3: PIC18LF8722 DEVICE FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V PIC18LF6627/6622/6627/6722 5.0V PIC18LF8527/8622/8627/8722 4.5V e g 4.2V 4.0V a t l o 3.5V V 3.0V 2.5V 2.0V 4 MHz FMAX Frequency In 8-bit External Memory mode: FMAX = (9.55 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN ≤ 4.2V; FMAX = 25MHz, if VDDAPPMIN > 4.2V. In all other modes: FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz; FMAX = 40MHz, if VDDAPPMIN > 4.2V. Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application. © 2008 Microchip Technology Inc. DS39646C-page 377

PIC18F8722 FAMILY 28.1 DC Characteristics: Supply Voltage PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) PIC18LF6X27/6X22/8X27/8X22 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6X27/6X22/8X27/8X22 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Symbol Characteristic Min Typ Max Units Conditions No. D001 VDD Supply Voltage PIC18LF6X27/6X22/8X27/8X22 2.0 — 5.5 V PIC18F6X27/6X22/8X27/8X22 4.2 — 5.5 V D002 VDR RAM Data Retention 1.5 — — V Voltage(1) D003 VPOR VDD Start Voltage — — 0.7 V See Section4.3 “Power-on Reset (POR)” for to Ensure Internal details Power-on Reset Signal D004 SVDD VDD Rise Rate 0.05 — — V/ms See Section4.3 “Power-on Reset (POR)” for to Ensure Internal details Power-on Reset Signal D005 VBOR Brown-out Reset Voltage BORV<1:0> = 11 2.00 2.05 2.16 V PIC18LF6627/6722/8627/8722 BORV<1:0> = 11 2.00 2.11 2.22 V PIC18LF6527/6622/8527/8622 BORV<1:0> = 10 2.65 2.79 2.93 V PIC18LF6X27/6X22/8X27/8X22 BORV<1:0> = 01(2) 4.11 4.33 4.55 V All devices BORV<1:0> = 00 4.36 4.59 4.82 V All devices Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. 2: With BOR enabled, full-speed operation (FOSC = 40MHz) is supported until a BOR occurs. The VDD may be below the minimum voltage for this frequency. DS39646C-page 378 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) PIC18LF6X27/6X22/8X27/8X22 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6X27/6X22/8X27/8X22 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Power-Down Current (IPD)(1) PIC18LF6X27/6X22/8X27/8X22 120 700 nA -40°C VDD = 2.0V 120 700 nA +25°C (Sleep mode) 0.24 3.0 μA +85°C PIC18LF6X27/6X22/8X27/8X22 120 900 nA -40°C VDD = 3.0V 120 900 nA +25°C (Sleep mode) 0.36 6 μA +85°C All devices 0.12 2 μA -40°C 0.12 2 μA +25°C VDD = 5.0V 0.48 9 μA +85°C (Sleep mode) Extended devices only 12 100 μA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: When operation below -10°C is expected, use T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. When operation will always be above -10°C, then the low-power Timer1 oscillator may be selected. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. © 2008 Microchip Technology Inc. DS39646C-page 379

PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) PIC18LF6X27/6X22/8X27/8X22 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6X27/6X22/8X27/8X22 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) PIC18LF6X27/6X22/8X27/8X22 18 25 μA -40°C 18 22 μA +25°C VDD = 2.0V 18 25 μA +85°C PIC18LF6X27/6X22/8X27/8X22 48 70 μA -40°C 42 50 μA +25°C VDD = 3.0V FOSC = 31kHz (RC_RUN mode, 36 47 μA +85°C Internal oscillator source) All devices 126 180 μA -40°C 108 150 μA +25°C VDD = 5.0V 96 140 μA +85°C Extended devices only 96 230 μA +125°C PIC18LF6X27/6X22/8X27/8X22 380 440 μA -40°C 380 440 μA +25°C VDD = 2.0V 380 440 μA +85°C PIC18LF6X27/6X22/8X27/8X22 720 800 μA -40°C 700 740 μA +25°C VDD = 3.0V FOSC = 1MHz (RC_RUN mode, 720 740 μA +85°C Internal oscillator source) All devices 1.2 1.4 mA -40°C 1.2 1.3 mA +25°C VDD = 5.0V 1.2 1.3 mA +85°C Extended devices only 1.2 1.4 mA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: When operation below -10°C is expected, use T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. When operation will always be above -10°C, then the low-power Timer1 oscillator may be selected. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39646C-page 380 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) PIC18LF6X27/6X22/8X27/8X22 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6X27/6X22/8X27/8X22 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) PIC18LF6X27/6X22/8X27/8X22 1.0 1.3 mA -40°C 1.0 1.3 mA +25°C VDD = 2.0V 1.0 1.3 mA +85°C PIC18LF6X27/6X22/8X27/8X22 1.6 1.9 mA -40°C 1.6 1.9 mA +25°C VDD = 3.0V FOSC = 4MHz (RC_RUN mode, 1.6 1.9 mA +85°C Internal oscillator source) All devices 3.0 3.5 mA -40°C 3.0 3.4 mA +25°C VDD = 5.0V 3.0 3.4 mA +85°C Extended devices only 3.0 3.4 mA +125°C PIC18LF6X27/6X22/8X27/8X22 3.5 5 μA -40°C 3.7 5 μA +25°C VDD = 2.0V 4.3 9.5 μA +85°C PIC18LF6X27/6X22/8X27/8X22 5.4 7 μA -40°C 5.7 8 μA +25°C VDD = 3.0V FOSC = 31kHz (RC_IDLE mode, 7.0 15 μA +85°C Internal oscillator source) All devices 11 15 μA -40°C 11.8 15 μA +25°C VDD = 5.0V 13.5 35 μA +85°C Extended devices only 25 200 μA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: When operation below -10°C is expected, use T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. When operation will always be above -10°C, then the low-power Timer1 oscillator may be selected. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. © 2008 Microchip Technology Inc. DS39646C-page 381

PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) PIC18LF6X27/6X22/8X27/8X22 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6X27/6X22/8X27/8X22 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) PIC18LF6X27/6X22/8X27/8X22 200 250 μA -40°C 210 250 μA +25°C VDD = 2.0V 228 270 μA +85°C PIC18LF6X27/6X22/8X27/8X22 300 360 μA -40°C 324 360 μA +25°C VDD = 3.0V FOSC = 1MHz (RC_IDLE mode, 350 380 μA +85°C Internal oscillator source) All devices 500 600 μA -40°C 520 600 μA +25°C VDD = 5.0V 550 620 μA +85°C Extended devices only 720 800 μA +125°C PIC18LF6X27/6X22/8X27/8X22 410 500 μA -40°C 420 490 μA +25°C VDD = 2.0V 430 490 μA +85°C PIC18LF6X27/6X22/8X27/8X22 630 800 μA -40°C 650 790 μA +25°C VDD = 3.0V FOSC = 4MHz (RC_IDLE mode, 690 800 μA +85°C Internal oscillator source) All devices 1.2 1.4 mA -40°C 1.3 1.4 mA +25°C VDD = 5.0V 1.2 1.4 mA +85°C Extended devices only 1.2 1.6 mA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: When operation below -10°C is expected, use T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. When operation will always be above -10°C, then the low-power Timer1 oscillator may be selected. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39646C-page 382 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) PIC18LF6X27/6X22/8X27/8X22 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6X27/6X22/8X27/8X22 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) PIC18LF6X27/6X22/8X27/8X22 300 350 μA -40°C 310 350 μA +25°C VDD = 2.0V 300 350 μA +85°C PIC18LF6X27/6X22/8X27/8X22 660 800 μA -40°C 580 700 μA +25°C VDD = 3.0V FOSC = 1MHZ (PRI_RUN mode, 550 670 μA +85°C EC oscillator) All devices 1.2 1.75 mA -40°C 1.1 1.4 mA +25°C VDD = 5.0V 1.0 1.3 mA +85°C Extended devices only 1.0 1.4 mA +125°C PIC18LF6X27/6X22/8X27/8X22 0.86 1.2 mA -40°C 0.88 1.2 mA +25°C VDD = 2.0V 0.88 1.2 mA +85°C PIC18LF6X27/6X22/8X27/8X22 1.6 1.9 mA -40°C 1.6 1.8 mA +25°C VDD = 3.0V FOSC = 4MHz (PRI_RUN mode, 1.6 1.8 mA +85°C EC oscillator) All devices 3.2 3.6 mA -40°C 3.1 3.5 mA +25°C VDD = 5.0V 3.0 3.5 mA +85°C Extended devices only 3.1 3.5 mA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: When operation below -10°C is expected, use T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. When operation will always be above -10°C, then the low-power Timer1 oscillator may be selected. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. © 2008 Microchip Technology Inc. DS39646C-page 383

PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) PIC18LF6X27/6X22/8X27/8X22 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6X27/6X22/8X27/8X22 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) Extended devices only 10 15 mA +125°C VDD = 4.2V FOSC = 25MHz 13 18 mA +125°C (PRI_RUN mode, VDD = 5.0V EC oscillator) All devices 18 23.5 mA -40°C 19 23.5 mA +25°C VDD = 4.2V 19 23.5 mA +85°C FOSC = 40MHZ (PRI_RUN mode, All devices 25 29 mA -40°C EC oscillator) 25 29 mA +25°C VDD = 5.0V 25 29 mA +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: When operation below -10°C is expected, use T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. When operation will always be above -10°C, then the low-power Timer1 oscillator may be selected. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39646C-page 384 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) PIC18LF6X27/6X22/8X27/8X22 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6X27/6X22/8X27/8X22 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) All devices 9.0 13 mA -40°C 9.0 13 mA +25°C FOSC = 4MHZ, VDD = 4.2V 16 MHz internal 9.0 13 mA +85°C (PRI_RUN HS+PLL) Extended devices only 9.6 15 mA +125°C All devices 12 15 mA -40°C 12 15 mA +25°C FOSC = 4MHZ, VDD = 5.0V 16 MHz internal 12 15 mA +85°C (PRI_RUN HS+PLL) Extended devices only 12 17 mA +125°C All devices 18 23.5 mA -40°C FOSC = 10MHZ, 19 23.5 mA +25°C VDD = 4.2V 40 MHz internal 19 23.5 mA +85°C (PRI_RUN HS+PLL) All devices 25 29 mA -40°C FOSC = 10MHZ, 25 29 mA +25°C VDD = 5.0V 40 MHz internal 25 29 mA +85°C (PRI_RUN HS+PLL) Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: When operation below -10°C is expected, use T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. When operation will always be above -10°C, then the low-power Timer1 oscillator may be selected. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. © 2008 Microchip Technology Inc. DS39646C-page 385

PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) PIC18LF6X27/6X22/8X27/8X22 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6X27/6X22/8X27/8X22 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) PIC18LF6X27/6X22/8X27/8X22 78 100 μA -40°C 78 100 μA +25°C VDD = 2.0V 84 110 μA +85°C PIC18LF6X27/6X22/8X27/8X22 130 150 μA -40°C 130 150 μA +25°C VDD = 3.0V FOSC = 1MHz (PRI_IDLE mode, 140 160 μA +85°C EC oscillator) All devices 230 280 μA -40°C 235 290 μA +25°C VDD = 5.0V 240 300 μA +85°C Extended devices only 260 500 μA +125°C PIC18LF6X27/6X22/8X27/8X22 312 375 μA -40°C 305 385 μA +25°C VDD = 2.0V 324 380 μA +85°C PIC18LF6X27/6X22/8X27/8X22 500 660 μA -40°C 600 670 μA +25°C VDD = 3.0V FOSC = 4MHz (PRI_IDLE mode, 600 680 μA +85°C EC oscillator) All devices 1.1 1.2 mA -40°C 1.1 1.2 mA +25°C VDD = 5.0V 1.1 1.2 mA +85°C Extended devices only 1.2 1.3 mA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: When operation below -10°C is expected, use T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. When operation will always be above -10°C, then the low-power Timer1 oscillator may be selected. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39646C-page 386 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) PIC18LF6X27/6X22/8X27/8X22 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6X27/6X22/8X27/8X22 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) Extended devices only 3.4 5.8 mA +125°C VDD = 4.2V FOSC = 25MHz 5.2 7 mA +125°C VDD = 5.0V (PRI_IDLE mode, EC oscillator) All devices 7.2 10 mA -40°C 7.4 10 mA +25°C VDD = 4.2 V 7.8 10 mA +85°C FOSC = 40MHz (PRI_IDLE mode, All devices 9.7 12 mA -40°C EC oscillator) 11 12 mA +25°C VDD = 5.0V 10 12 mA +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: When operation below -10°C is expected, use T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. When operation will always be above -10°C, then the low-power Timer1 oscillator may be selected. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. © 2008 Microchip Technology Inc. DS39646C-page 387

PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) PIC18LF6X27/6X22/8X27/8X22 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6X27/6X22/8X27/8X22 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) PIC18LF6X27/6X22/8X27/8X22 17 28 μA -40°C 18 25 μA +25°C VDD = 2.0V 19 28 μA +70°C PIC18LF6X27/6X22/8X27/8X22 48 70 μA -40°C FOSC = 32kHz(3) 42 52 μA +25°C VDD = 3.0V (SEC_RUN mode, 37 48 μA +70°C Timer1 as clock) All devices 120 180 μA -40°C 97 130 μA +25°C VDD = 5.0V 90 125 μA +70°C PIC18LF6X27/6X22/8X27/8X22 3.0 10 μA -40°C 4.4 6.8 μA +25°C VDD = 2.0V 5.4 10 μA +70°C PIC18LF6X27/6X22/8X27/8X22 6.0 15 μA -40°C FOSC = 32kHz(3) 6.5 10 μA +25°C VDD = 3.0V (SEC_IDLE mode, 7.6 15 μA +70°C Timer1 as clock) All devices 10.0 25 μA -40°C 10.5 15 μA +25°C VDD = 5.0V 11.0 25 μA +70°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: When operation below -10°C is expected, use T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. When operation will always be above -10°C, then the low-power Timer1 oscillator may be selected. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39646C-page 388 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) PIC18LF6X27/6X22/8X27/8X22 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6X27/6X22/8X27/8X22 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. Module Differential Currents (ΔIWDT, ΔIBOR, ΔILVD, ΔIOSCB, ΔIAD) D022 Watchdog Timer 1.5 2.2 μA -40°C (ΔIWDT) 1.6 2.2 μA +25°C VDD = 2.0V 1.7 2.3 μA +85°C 2.3 3.5 μA -40°C 2.4 3.5 μA +25°C VDD = 3.0V 3.4 3.5 μA +85°C 4.8 7.5 μA -40°C 6.0 7.5 μA +25°C VDD = 5.0V 6.1 7.8 μA +85°C 8 10 μA +125°C D022A Brown-out Reset(4) 4.2 50 μA -40°C to +85°C VDD = 3.0V (ΔIBOR) 48 55 μA -40°C to +85°C 66 55 μA -40°C to +125°C VDD = 5.0V 0 2.4 μA -40°C to +85°C Sleep mode, 0 6.0 μA -40°C to +125°C BOREN<1:0> = 10 D022B High/Low-Voltage Detect(4) 2.7 38 μA -40°C to +85°C VDD = 2.0V (ΔILVD) 30 40 μA -40°C to +85°C VDD = 3.0V 35 45 μA -40°C to +85°C VDD = 5.0V 36 45 μA -40°C to +125°C D025 Timer1 Oscillator 4.5 9 μA -40°C(3) (ΔIOSCB) .9 1.7 μA -10°C VDD = 2.0V 32kHz on Timer1 .9 2.2 μA +25°C .9 2.2 μA +85°C 4.8 10 μA -40°C(3) 1 1.8 μA -10°C VDD = 3.0V 32kHz on Timer1 1 2.3 μA +25°C 1 2.3 μA +85°C 6 11 μA -40°C(3) 1.6 6 μA -10°C VDD = 5.0V 32kHz on Timer1 1.6 6 μA +25°C 1.6 6 μA +85°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: When operation below -10°C is expected, use T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. When operation will always be above -10°C, then the low-power Timer1 oscillator may be selected. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. © 2008 Microchip Technology Inc. DS39646C-page 389

PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) PIC18LF6X27/6X22/8X27/8X22 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6X27/6X22/8X27/8X22 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Typ Max Units Conditions No. D026 A/D Converter 0.2 1 μA -40°C to +85°C VDD = 2.0V (ΔIAD) 0.2 1 μA -40°C to +85°C VDD = 3.0V A/D on, not converting, 0.2 1 μA -40°C to +85°C Sleep mode VDD = 5.0V 0.5 4 μA -40°C to +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. 3: When operation below -10°C is expected, use T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. When operation will always be above -10°C, then the low-power Timer1 oscillator may be selected. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39646C-page 390 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 28.3 DC Characteristics: PIC18F8722 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Characteristic Min Max Units Conditions No. VIL Input Low Voltage I/O Ports: D030 with TTL Buffer VSS 0.15 VDD V VDD < 4.5V D030A — 0.8 V 4.5V ≤ VDD ≤ 5.5V D031 with Schmitt Trigger Buffer VSS 0.2 VDD V D032 MCLR VSS 0.2 VDD V D033 OSC1 VSS 0.3 VDD V HS, HSPLL modes D033A OSC1 VSS 0.2 VDD V RC, EC modes(1) D033B OSC1 VSS 0.3 V XT, LP modes D034 T13CKI VSS 0.3 V VIH Input High Voltage I/O Ports: D040 with TTL Buffer 0.25 VDD + 0.8V VDD V VDD < 4.5V D040A 2.0 VDD V 4.5V ≤ VDD ≤ 5.5V D041 with Schmitt Trigger Buffer 0.8 VDD VDD V D042 MCLR 0.8 VDD VDD V D043 OSC1 0.7 VDD VDD V HS, HSPLL modes D043A OSC1 0.8 VDD VDD V EC mode D043B OSC1 0.9 VDD VDD V RC mode(1) D043C OSC1 1.6 VDD V XT, LP modes D044 T13CKI 1.6 VDD V IIL Input Leakage Current(2,3) D060 I/O Ports — ±200 nA VDD < 5.5V VSS ≤ VPIN ≤ VDD, Pin at high-impedance — ±50 nA VDD < 3V VSS ≤ VPIN ≤ VDD, Pin at high-impedance D061 MCLR — ±1 μA Vss ≤ VPIN ≤ VDD D063 OSC1 — ±1 μA Vss ≤ VPIN ≤ VDD IPU Weak Pull-up Current D070 IPURB PORTB Weak Pull-up Current 50 400 μA VDD = 5V, VPIN = VSS Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. © 2008 Microchip Technology Inc. DS39646C-page 391

PIC18F8722 FAMILY 28.3 DC Characteristics: PIC18F8722 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Characteristic Min Max Units Conditions No. VOL Output Low Voltage D080 I/O Ports — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C D083 OSC2/CLKO — 0.6 V IOL = 1.6 mA, VDD = 4.5V, (RC, RCIO, EC, ECIO modes) -40°C to +85°C VOH Output High Voltage(3) D090 I/O Ports VDD – 0.7 — V IOH = -3.0 mA, VDD = 4.5V, -40°C to +85°C D092 OSC2/CLKO VDD – 0.7 — V IOH = -1.3 mA, VDD = 4.5V, (RC, RCIO, EC, ECIO modes) -40°C to +85°C Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 Pin — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O Pins and OSC2 — 50 pF To meet the AC Timing (in RC mode) Specifications D102 CB SCLx, SDAx — 400 pF I2C™ Specification Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS39646C-page 392 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 28-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Sym Characteristic Min Typ† Max Units Conditions No. Data EEPROM Memory D120 ED Byte Endurance 100K 1M — E/W -40°C to +85°C D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write VMIN = Minimum operating voltage D122 TDEW Erase/Write Cycle Time — 4 — ms D123 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated D124 TREF Number of Total Erase/Write 1M 10M — E/W -40°C to +85°C Cycles before Refresh(1) D125 IDDP Supply Current during — 10 — mA Programming Program Flash Memory D130 EP Cell Endurance 10K 100K — E/W -40°C to +85°C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132B VPEW VDD for Self-Timed Write and VMIN — 5.5 V VMIN = Minimum operating Row Erase voltage D133A TIW Self-Timed Write Cycle Time — 2 — ms D134 TRETD Characteristic Retention 40 100 — Year Provided no other specifications are violated D135 IDDP Supply Current during — 10 — mA Programming † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Refer to Section8.8 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance. © 2008 Microchip Technology Inc. DS39646C-page 393

PIC18F8722 FAMILY TABLE 28-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. D300 VIOFF Input Offset Voltage — ±5.0 ±10 mV D301 VICM Input Common Mode Voltage 0 — VDD – 1.5 V D302 CMRR Common Mode Rejection Ratio 55 — — dB 300 TRESP Response Time(1) — 150 400 ns PIC18FXXXX 300A — 150 600 ns PIC18LFXXXX, VDD = 2.0V 301 TMC2OV Comparator Mode Change to — — 10 μs Output Valid Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. TABLE 28-3: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. D310 VRES Resolution VDD/24 — VDD/32 LSb D311 VRAA Absolute Accuracy — — 1/2 LSb D312 VRUR Unit Resistor Value (R) — 2k — Ω 310 TSET Settling Time(1) — — 10 μs Note 1: Settling time measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’. DS39646C-page 394 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 28-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS For VDIRMAG = 1: VDD VHLVD (HLVDIF set by hardware) (HLVDIF can be cleared in software) VHLVD For VDIRMAG = 0: VDD HLVDIF TABLE 28-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Sym Characteristic Min Typ Max Units Conditions No. D420 HLVD Voltage on VDD HLVDL<3:0> = 0000 2.06 2.17 2.28 V Transition High-to-Low HLVDL<3:0> = 0001 2.12 2.23 2.34 V HLVDL<3:0> = 0010 2.24 2.36 2.48 V HLVDL<3:0> = 0011 2.32 2.44 2.56 V HLVDL<3:0> = 0100 2.47 2.60 2.73 V HLVDL<3:0> = 0101 2.65 2.79 2.93 V HLVDL<3:0> = 0110 2.74 2.89 3.04 V HLVDL<3:0> = 0111 2.96 3.12 3.28 V HLVDL<3:0> = 1000 3.22 3.39 3.56 V HLVDL<3:0> = 1001 3.37 3.55 3.73 V HLVDL<3:0> = 1010 3.52 3.71 3.90 V HLVDL<3:0> = 1011 3.70 3.90 4.10 V HLVDL<3:0> = 1100 3.90 4.11 4.32 V HLVDL<3:0> = 1101 4.11 4.33 4.55 V HLVDL<3:0> = 1110 4.36 4.59 4.82 V © 2008 Microchip Technology Inc. DS39646C-page 395

PIC18F8722 FAMILY 28.4 AC (Timing) Characteristics 28.4.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C™ specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T13CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-Impedance) V Valid L Low Z High-Impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO Stop condition STA Start condition DS39646C-page 396 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 28.4.2 TIMING CONDITIONS Note: Because of space limitations, the generic The temperature and voltages specified in Table28-5 terms “PIC18FXXXX” and “PIC18LFXXXX” apply to all timing specifications unless otherwise are used throughout this section to refer to noted. Figure28-5 specifies the load conditions for the the PIC18F6X27/6X22/8X27/8X22 and timing specifications. PIC18LF6X27/6X22/8X27/8X22 families of devices specifically and only those devices. TABLE 28-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended AC CHARACTERISTICS Operating voltage VDD range as described in the DC specifications in Section28.1 and Section28.3. LF parts operate for industrial temperatures only. FIGURE 28-5: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 Load Condition 2 VDD/2 RL Pin CL VSS CL Pin RL = 464Ω VSS CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports © 2008 Microchip Technology Inc. DS39646C-page 397

PIC18F8722 FAMILY 28.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 28-6: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO TABLE 28-6: EXTERNAL CLOCK TIMING REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 1A FOSC External CLKI Frequency(1) DC 1 MHz XT, RC Oscillator mode DC 25 MHz HS Oscillator mode DC 31.25 kHz LP Oscillator mode DC 40 MHz EC Oscillator mode Oscillator Frequency(1) DC 4 MHz RC Oscillator mode 0.1 4 MHz XT Oscillator mode 4 25 MHz HS Oscillator mode 4 10 MHz HS + PLL Oscillator mode 5 200 kHz LP Oscillator mode 1 TOSC External CLKI Period(1) 1000 — ns XT, RC Oscillator mode 40 — ns HS Oscillator mode 32 — μs LP Oscillator mode 25 — ns EC Oscillator mode Oscillator Period(1) 250 — ns RC Oscillator mode 250 1 μs XT Oscillator mode 40 250 ns HS Oscillator mode 100 250 ns HS + PLL Oscillator mode 5 200 μs LP Oscillator mode 2 TCY Instruction Cycle Time(1) 100 — ns TCY = 4/FOSC, Industrial 160 — ns TCY = 4/FOSC, Extended 3 TOSL, External Clock in (OSC1) 30 — ns XT Oscillator mode TOSH High or Low Time 2.5 — μs LP Oscillator mode 10 — ns HS Oscillator mode 4 TOSR, External Clock in (OSC1) — 20 ns XT Oscillator mode TOSF Rise or Fall Time — 50 ns LP Oscillator mode — 7.5 ns HS Oscillator mode Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. DS39646C-page 398 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 28-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V) Param Sym Characteristic Min Typ† Max Units Conditions No. F10 FOSC Oscillator Frequency Range 4 — 10 MHz HS mode only F11 FSYS On-Chip VCO System Frequency 16 — 40 MHz HS mode only F12 t PLL Start-up Time (Lock Time) — — 2 ms rc F13 ΔCLK CLKO Stability (Jitter) -2 — +2 % † Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 28-8: AC CHARACTERISTICS:INTERNAL RC ACCURACY PIC18F6X27/6X22/8X27/8X22 (INDUSTRIAL, EXTENDED) PIC18LF6X27/6X22/8X27/8X22 (INDUSTRIAL) PIC18LF6X27/6X22/8X27/8X22 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6X27/6X22/8X27/8X22 Operating temperature -40°C ≤ TA ≤ +85°C for industrial (Industrial, Extended) -40°C ≤ TA ≤ +125°C for extended Param Device Min Typ Max Units Conditions No. INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1) PIC18LF6X27/6X22/8X27/8X22 -2 +/-1 2 % +25°C VDD = 2.7-3.3V -5 +/-1 5 % -40°C to +85°C VDD = 2.7-3.3V PIC18F6X27/6X22/8X27/8X22 -2 +/-1 2 % +25°C VDD = 4.5-5.5V -5 +/-1 5 % -40°C to +85°C VDD = 4.5-5.5V INTRC Accuracy @ Freq = 31 kHz PIC18LF6X27/6X22/8X27/8X22 26.562 — 35.938 kHz -40°C to +85°C VDD = 2.7-3.3V PIC18F6X27/6X22/8X27/8X22 26.562 +/-8 35.938 kHz -40°C to +85°C VDD = 4.5-5.5V Legend: Shading of rows is to assist in readability of the table. Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift. © 2008 Microchip Technology Inc. DS39646C-page 399

PIC18F8722 FAMILY FIGURE 28-7: CLKO AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKO 13 12 14 19 18 16 I/O pin (Input) 17 15 I/O pin Old Value New Value (Output) 20, 21 Note: Refer to Figure28-5 for load conditions. TABLE 28-9: CLKO AND I/O TIMING REQUIREMENTS Param Symbol Characteristic Min Typ Max Units Conditions No. 10 TOSH2CKL OSC1 ↑ to CLKO ↓ — 75 200 ns (Note 1) 11 TOSH2CKH OSC1 ↑ to CLKO ↑ — 75 200 ns (Note 1) 12 TCKR CLKO Rise Time — 35 100 ns (Note 1) 13 TCKF CLKO Fall Time — 35 100 ns (Note 1) 14 TCKL2IOV CLKO ↓ to Port Out Valid — — 0.5 TCY + 20 ns (Note 1) 15 TIOV2CKH Port In Valid before CLKO ↑ 0.25 TCY + 25 — — ns (Note 1) 16 TCKH2IOI Port In Hold after CLKO ↑ 0 — — ns (Note 1) 17 TOSH2IOV OSC1 ↑ (Q1 cycle) to Port Out Valid — 50 150 ns 18 TOSH2IOI OSC1 ↑ (Q2 cycle) to PIC18FXXXX 100 — — ns 18A Port Input Invalid PIC18LFXXXX 200 — — ns VDD = 2.0V (I/O in hold time) 19 TIOV2OSH Port Input Valid to OSC1 ↑ (I/O in setup 0 — — ns time) 20 TIOR Port Output Rise Time PIC18FXXXX — 10 25 ns 20A PIC18LFXXXX — — 60 ns VDD = 2.0V 21 TIOF Port Output Fall Time PIC18FXXXX — 10 25 ns 21A PIC18LFXXXX — — 60 ns VDD = 2.0V 22† TINP INTx pin High or Low Time TCY — — ns 23† TRBP RB<7:4> Change INTx High or Low Time TCY — — ns † These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC. DS39646C-page 400 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 28-8: PROGRAM MEMORY READ TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> Address Address BA0 AD<15:0> Address Data from External Address 150 160 163 151 162 161 155 166 167 168 ALE 164 169 171 CE 171A OE 165 Operating Conditions: 2.0V < VCC < 5.5V, -40°C < TA < +125°C unless otherwise stated. TABLE 28-10: CLKO AND I/O TIMING REQUIREMENTS Param. Symbol Characteristics Min Typ Max Units No 150 TadV2alL Address Out Valid to ALE ↓ (address 0.25 TCY – 10 — — ns setup time) 151 TalL2adl ALE ↓ to Address Out Invalid (address 5 — — ns hold time) 155 TalL2oeL ALE ↓ to OE ↓ 10 0.125 TCY — ns 160 TadZ2oeL AD high-Z to OE ↓ (bus release to OE) 0 — — ns 161 ToeH2adD OE ↑ to AD Driven 0.125 TCY – 5 — — ns 162 TadV2oeH LS Data Valid before OE ↑ (data setup time) 20 — — ns 163 ToeH2adl OE ↑ to Data In Invalid (data hold time) 0 — — ns 164 TalH2alL ALE Pulse Width — TCY — ns 165 ToeL2oeH OE Pulse Width 0.5 TCY – 5 0.5 TCY — ns 166 TalH2alH ALE ↑ to ALE ↑ (cycle time) — 0.25 TCY — ns 167 Tacc Address Valid to Data Valid 0.75 TCY – 25 — — ns 168 Toe OE ↓ to Data Valid — 0.5 TCY – 25 ns 169 TalL2oeH ALE ↓ to OE ↑ 0.625 TCY – 10 — 0.625 TCY + 10 ns 171 TalH2csL Chip Enable Active to ALE ↓ 0.25 TCY – 20 — — ns 171A TubL2oeH AD Valid to Chip Enable Active — — 10 ns © 2008 Microchip Technology Inc. DS39646C-page 401

PIC18F8722 FAMILY FIGURE 28-9: PROGRAM MEMORY WRITE TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> Address Address BA0 166 AD<15:0> Address Data Address 153 150 156 151 ALE 171 CE 171A 154 WRH or WRL 157 157A UB or LB Operating Conditions: 2.0V < VCC < 5.5V, -40°C < TA < +125°C unless otherwise stated. TABLE 28-11: PROGRAM MEMORY WRITE TIMING REQUIREMENTS Param. Symbol Characteristics Min Typ Max Units No 150 TadV2alL Address Out Valid to ALE ↓ (address setup time) 0.25 TCY – 10 — — ns 151 TalL2adl ALE ↓ to Address Out Invalid (address hold time) 5 — — ns 153 TwrH2adl WRn ↑ to Data Out Invalid (data hold time) 5 — — ns 154 TwrL WRn Pulse Width 0.5 TCY – 5 0.5 TCY — ns 156 TadV2wrH Data Valid before WRn ↑ (data setup time) 0.5 TCY – 10 — — ns 157 TbsV2wrL Byte Select Valid before WRn ↓ (byte select setup 0.25 TCY — — ns time) 157A TwrH2bsI WRn ↑ to Byte Select Invalid (byte select hold time) 0.125 TCY – 5 — — ns 166 TalH2alH ALE ↑ to ALE ↑ (cycle time) — 0.25 TCY — ns 171 TalH2csL Chip Enable Active to ALE ↓ 0.25 TCY – 20 — — ns 171A TubL2oeH AD Valid to Chip Enable Active — — 10 ns DS39646C-page 402 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 28-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure28-5 for load conditions. FIGURE 28-11: BROWN-OUT RESET TIMING BVDD VDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference 36 Voltage Stable TABLE 28-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol Characteristic Min Typ Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2 — — μs 31 TWDT Watchdog Timer Time-out Period 3.4 4.0 4.6 ms (no postscaler) 32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period 33 TPWRT Power-up Timer Period 55.6 64 75 ms 34 TIOZ I/O High-Impedance from MCLR — 2 — μs Low or Watchdog Timer Reset 35 TBOR Brown-out Reset Pulse Width 200 — — μs VDD ≤ BVDD (see D005) 36 TIRVST Time for Internal Reference — 20 50 μs Voltage to become Stable 37 TLVD High/Low-Voltage Detect Pulse Width 200 — — μs VDD ≤ VHLVD 38 TCSD CPU Start-up Time — 10 — μs 39 TIOBST Time for INTOSC to Stabilize — 1 — μs © 2008 Microchip Technology Inc. DS39646C-page 403

PIC18F8722 FAMILY FIGURE 28-12: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1OSO/T13CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure28-5 for load conditions. TABLE 28-13: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 40 TT0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 41 TT0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 42 TT0P T0CKI Period No prescaler TCY + 10 — ns With prescaler Greater of: — ns N = prescale 20ns or value (TCY + 40)/N (1, 2, 4,..., 256) 45 TT1H T13CKI Synchronous, no prescaler 0.5 TCY + 20 — ns High Time Synchronous, PIC18FXXXX 10 — ns with prescaler PIC18LFXXXX 25 — ns VDD = 2.0V Asynchronous PIC18FXXXX 30 — ns PIC18LFXXXX 50 — ns VDD = 2.0V 46 TT1L T13CKI Synchronous, no prescaler 0.5 TCY + 5 — ns Low Time Synchronous, PIC18FXXXX 10 — ns with prescaler PIC18LFXXXX 25 — ns VDD = 2.0V Asynchronous PIC18FXXXX 30 — ns PIC18LFXXXX 50 — ns VDD = 2.0V 47 TT1P T13CKI Synchronous Greater of: — ns N = prescale Input 20ns or value Period (TCY + 40)/N (1, 2, 4, 8) Asynchronous 60 — ns FT1 T13CKI Oscillator Input Frequency Range DC 50 kHz 48 TCKE2TMRI Delay from External T13CKI Clock Edge to 2 TOSC 7 TOSC — Timer Increment DS39646C-page 404 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 28-13: CAPTURE/COMPARE/PWM TIMINGS (ALL ECCP/CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 Note: Refer to Figure28-5 for load conditions. TABLE 28-14: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL ECCP/CCP MODULES) Param Symbol Characteristic Min Max Units Conditions No. 50 TCCL CCPx Input Low No prescaler 0.5 TCY + 20 — ns Time With PIC18FXXXX 10 — ns prescaler PIC18LFXXXX 20 — ns VDD = 2.0V 51 TCCH CCPx Input No prescaler 0.5 TCY + 20 — ns High Time With PIC18FXXXX 10 — ns prescaler PIC18LFXXXX 20 — ns VDD = 2.0V 52 TCCP CCPx Input Period 3 TCY + 40 — ns N = prescale N value (1, 4 or 16) 53 TCCR CCPx Output Fall Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 54 TCCF CCPx Output Fall Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V © 2008 Microchip Technology Inc. DS39646C-page 405

PIC18F8722 FAMILY FIGURE 28-14: PARALLEL SLAVE PORT TIMING (PIC18F8527/8622/8627/8722) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure28-5 for load conditions. TABLE 28-15: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F8527/8622/8627/8722) Param. Symbol Characteristic Min Max Units Conditions No. 62 TdtV2wrH Data In Valid before WR ↑ or CS ↑ (setup time) 20 — ns 63 TwrH2dtI WR ↑ or CS ↑ to Data–In PIC18FXXXX 20 — ns Invalid (hold time) PIC18LFXXXX 35 — ns VDD = 2.0V 64 TrdL2dtV RD ↓ and CS ↓ to Data–Out Valid — 80 ns 65 TrdH2dtI RD ↑ or CS ↓ to Data–Out Invalid 10 30 ns 66 TibfINH Inhibit of the IBF Flag bit being Cleared from — 3 TCY WR ↑ or CS ↑ DS39646C-page 406 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 28-15: EXAMPLE SPI MASTER MODE TIMING (CKE=0) SSx 70 SCKx (CKP = 0) 71 72 78 79 SCKx (CKP = 1) 79 78 80 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure28-5 for load conditions. TABLE 28-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input TCY — ns TSSL2SCL 71 TSCH SCKx Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TSCL SCKx Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 20 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns (Note 2) of Byte 2 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 40 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 76 TDOF SDOx Data Output Fall Time — 25 ns 78 TSCR SCKx Output Rise Time PIC18FXXXX — 25 ns (Master mode) PIC18LFXXXX — 45 ns VDD = 2.0V 79 TSCF SCKx Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDOx Data Output Valid after PIC18FXXXX — 50 ns TSCL2DOV SCKx Edge PIC18LFXXXX — 100 ns VDD = 2.0V Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. © 2008 Microchip Technology Inc. DS39646C-page 407

PIC18F8722 FAMILY FIGURE 28-16: EXAMPLE SPI MASTER MODE TIMING (CKE=1) SSx 81 SCKx (CKP = 0) 71 72 79 73 SCKx (CKP = 1) 80 78 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 Note: Refer to Figure28-5 for load conditions. TABLE 28-17: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=1) Param. Symbol Characteristic Min Max Units Conditions No. 71 TSCH SCKx Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TSCL SCKx Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 20 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns (Note 2) of Byte 2 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 40 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 76 TDOF SDOx Data Output Fall Time — 25 ns 78 TSCR SCKx Output Rise Time PIC18FXXXX — 25 ns (Master mode) PIC18LFXXXX — 45 ns VDD = 2.0V 79 TSCF SCKx Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDOx Data Output Valid after PIC18FXXXX — 50 ns TSCL2DOV SCKx Edge PIC18LFXXXX — 100 ns VDD = 2.0V 81 TDOV2SCH, SDOx Data Output Setup to SCKx Edge TCY — ns TDOV2SCL Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. DS39646C-page 408 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 28-17: EXAMPLE SPI SLAVE MODE TIMING (CKE=0) SSx 70 SCKx (CKP = 0) 83 71 72 78 79 SCKx (CKP = 1) 79 78 80 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 77 SSDDIIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure28-5 for load conditions. TABLE 28-18: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input 3 TCY — ns TSSL2SCL 71 TSCH SCKx Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TSCL SCKx Input Low Time Continuous 1.25 TCY + 30 — ns (Slave mode) 72A Single Byte 40 — ns (Note 1) 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 20 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 40 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 76 TDOF SDOx Data Output Fall Time — 25 ns 77 TSSH2DOZ SSx ↑ to SDOx Output High-Impedance 10 50 ns 78 TSCR SCKx Output Rise Time (Master mode) PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 79 TSCF SCKx Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx PIC18FXXXX — 50 ns TSCL2DOV Edge PIC18LFXXXX — 100 ns VDD = 2.0V 83 TSCH2SSH, SSx ↑ after SCKx Edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. © 2008 Microchip Technology Inc. DS39646C-page 409

PIC18F8722 FAMILY FIGURE 28-18: EXAMPLE SPI SLAVE MODE TIMING (CKE=1) 82 SSx 70 SCKx 83 (CKP = 0) 71 72 SCKx (CKP = 1) 80 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 77 SSDDIIx MSb In bit 6 - - - - 1 LSb In 74 Note: Refer to Figure28-5 for load conditions. TABLE 28-19: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE=1) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input 3 TCY — ns TSSL2SCL 71 TSCH SCKx Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TSCL SCKx Input Low Time Continuous 1.25 TCY + 30 — ns (Slave mode) 72A Single Byte 40 — ns (Note 1) 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 40 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 76 TDOF SDOx Data Output Fall Time — 25 ns 77 TSSH2DOZ SSx ↑ to SDOx Output High-Impedance 10 50 ns 78 TSCR SCKx Output Rise Time PIC18FXXXX — 25 ns (Master mode) PIC18LFXXXX — 45 ns VDD = 2.0V 79 TSCF SCKx Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx PIC18FXXXX — 50 ns TSCL2DOV Edge PIC18LFXXXX — 100 ns VDD = 2.0V 82 TSSL2DOV SDOx Data Output Valid after SSx ↓ PIC18FXXXX — 50 ns Edge PIC18LFXXXX — 100 ns VDD = 2.0V 83 TSCH2SSH, SSx ↑ after SCKx Edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. DS39646C-page 410 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 28-19: I2C™ BUS START/STOP BITS TIMING SCLx 91 93 90 92 SDAx Start Stop Condition Condition Note: Refer to Figure28-5 for load conditions. TABLE 28-20: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated Setup Time 400 kHz mode 600 — Start condition 91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first Hold Time 400 kHz mode 600 — clock pulse is generated 92 TSU:STO Stop Condition 100 kHz mode 4700 — ns Setup Time 400 kHz mode 600 — 93 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — FIGURE 28-20: I2C™ BUS DATA TIMING 103 100 102 101 SCLx 90 106 107 91 92 SDAx In 110 109 109 SDAx Out Note: Refer to Figure28-5 for load conditions. © 2008 Microchip Technology Inc. DS39646C-page 411

PIC18F8722 FAMILY TABLE 28-21: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 4.0 — μs PIC18FXXXX must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs PIC18FXXXX must operate at a minimum of 10 MHz SSP Module 1.5 TCY — 101 TLOW Clock Low Time 100 kHz mode 4.7 — μs PIC18FXXXX must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — μs PIC18FXXXX must operate at a minimum of 10 MHz SSP Module 1.5 TCY — 102 TR SDAx and SCLx Rise Time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDAx and SCLx Fall Time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 90 TSU:STA Start Condition Setup Time 100 kHz mode 4.7 — μs Only relevant for Repeated 400 kHz mode 0.6 — μs Start condition 91 THD:STA Start Condition Hold Time 100 kHz mode 4.0 — μs After this period, the first clock 400 kHz mode 0.6 — μs pulse is generated 106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 μs 107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns (Note 2) 400 kHz mode 100 — ns 92 TSU:STO Stop Condition Setup Time 100 kHz mode 4.7 — μs 400 kHz mode 0.6 — μs 109 TAA Output Valid from Clock 100 kHz mode — 3500 ns (Note 1) 400 kHz mode — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free 400 kHz mode 1.3 — μs before a new transmission can start D102 CB Bus Capacitive Loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions. 2: A Fast mode I2C™ bus device can be used in a Standard mode I2C bus system, but the requirement, TSU:DAT≥250ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, TR max. + TSU:DAT=1000+250=1250ns (according to the Standard mode I2C bus specification), before the SCLx line is released. DS39646C-page 412 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 28-21: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCLx 91 93 90 92 SDAx Start Stop Condition Condition Note: Refer to Figure28-5 for load conditions. TABLE 28-22: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — first clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins. FIGURE 28-22: MASTER SSP I2C™ BUS DATA TIMING 103 100 102 101 SCLx 90 106 91 107 92 SDAx In 109 109 110 SDAx Out Note: Refer to Figure28-5 for load conditions. © 2008 Microchip Technology Inc. DS39646C-page 413

PIC18F8722 FAMILY TABLE 28-23: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 102 TR SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns 103 TF SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — ms clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 106 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 ms 1 MHz mode(1) TBD — ns 107 TSU:DAT Data Input 100 kHz mode 250 — ns (Note 2) Setup Time 400 kHz mode 100 — ns 1 MHz mode(1) TBD — ns 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 109 TAA Output Valid 100 kHz mode — 3500 ns from Clock 400 kHz mode — 1000 ns 1 MHz mode(1) — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — ms Time the bus must be free 400 kHz mode 1.3 — ms before a new transmission can start 1 MHz mode(1) TBD — ms D102 CB Bus Capacitive Loading — 400 pF Legend: TBD = To Be Determined Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107≥250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, parameter #102 + parameter #107=1000+250=1250ns (for 100 kHz mode,) before the SCLx line is released. DS39646C-page 414 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY FIGURE 28-23: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CKx/TXx pin 121 121 DTx/RXx pin 122 120 Note: Refer to Figure28-5 for load conditions. TABLE 28-24: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 120 TCKH2DTV SYNC XMIT (MASTER and SLAVE) Clock High to Data Out Valid PIC18FXXXX — 40 ns PIC18LFXXXX — 100 ns VDD = 2.0V 121 TCKRF Clock Out Rise Time and Fall Time PIC18FXXXX — 20 ns (Master mode) PIC18LFXXXX — 50 ns VDD = 2.0V 122 TDTRF Data Out Rise Time and Fall Time PIC18FXXXX — 20 ns PIC18LFXXXX — 50 ns VDD = 2.0V FIGURE 28-24: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CKx/TXx pin 125 DTx/RXx pin 126 Note: Refer to Figure28-5 for load conditions. TABLE 28-25: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 125 TDTV2CKL SYNC RCV (MASTER and SLAVE) Data Hold before CKx ↓ (DTx hold time) 10 — ns 126 TCKL2DTL Data Hold after CKx ↓ (DTx hold time) 15 — ns © 2008 Microchip Technology Inc. DS39646C-page 415

PIC18F8722 FAMILY TABLE 28-26: A/D CONVERTER CHARACTERISTICS: PIC18F6X27/6X22/8X27/8X22 (INDUSTRIAL) PIC18LF6X27/6X22/8X27/8X22 (INDUSTRIAL) Param Symbol Characteristic Min Typ Max Units Conditions No. A01 NR Resolution — — 10 bit ΔVREF ≥ 3.0V A03 EIL Integral Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A04 EDL Differential Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A06 EOFF Offset Error — — <±2 LSb ΔVREF ≥ 3.0V A07 EGN Gain Error — — <±1 LSb ΔVREF ≥ 3.0V A10 — Monotonicity Guaranteed(1) — VSS ≤ VAIN ≤ VREF A20 ΔVREF Reference Voltage Range 1.8 — — V VDD < 3.0V (VREFH – VREFL) 3 — — V VDD ≥ 3.0V A21 VREFH Reference Voltage High VSS — VREFH V A22 VREFL Reference Voltage Low VSS – 0.3V — VDD – 3.0V V A25 VAIN Analog Input Voltage VREFL — VREFH V A30 ZAIN Recommended Impedance of — — 2.5 kΩ Analog Voltage Source A40 IAD A/D Current PIC18FXXXX — 180 — μA Average current during from VDD PIC18LFXXXX — 90 — μA conversion A50 IREF VREF Input Current(2) — — 5 μA During VAIN acquisition. — — 150 μA During A/D conversion cycle. Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF- pin or VSS, whichever is selected as the VREFL source. FIGURE 28-25: A/D CONVERSION TIMING BSF ADCON0, GO (Note 1, 2) 131 Q4 130 A/D CLK 132 . . . . . . A/D DATA 9 8 7 2 1 0 ADRES OLD_DATA NEW_DATA ADIF TCY GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. DS39646C-page 416 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY TABLE 28-27: A/D CONVERSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 130 TAD A/D Clock Period PIC18FXXXX 0.7 25.0(1) μs TOSC based, VREF ≥ 3.0V PIC18LFXXXX 1.4 25.0(1) μs VDD = 2.0V; TOSC based, VREF full range PIC18FXXXX — 1 μs A/D RC mode PIC18LFXXXX — 3 μs VDD = 2.0V; A/D RC mode 131 TCNV Conversion Time 11 12 TAD (not including acquisition time) (Note 2) 132 TACQ Acquisition Time (Note 3) 1.4 — μs -40°C to +85°C 135 TSWC Switching Time from Convert → Sample — (Note 4) 137 TDIS Discharge Time 0.2 — μs Legend: TBD = To Be Determined Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. 2: ADRES register may be read on the following TCY cycle. 3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω. 4: On the following cycle of the device clock. © 2008 Microchip Technology Inc. DS39646C-page 417

PIC18F8722 FAMILY NOTES: DS39646C-page 418 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY 29.0 PACKAGING INFORMATION 29.1 Package Marking Information 64-Lead TQFP Example XXXXXXXXXX PIC18F6722 XXXXXXXXXX -I/PTe3 XXXXXXXXXX 0810017 YYWWNNN 80-Lead TQFP Example XXXXXXXXXXXX PIC18F8722-E XXXXXXXXXXXX /PTe3 YYWWNNN 0810017 Legend: XX...X Product-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2008 Microchip Technology Inc. DS39646C-page 419

PIC18F8722 FAMILY 29.2 Package Details The following sections give the technical details of the packages. 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(cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)?(cid:20)#&(cid:24) .(cid:15) (cid:15)(cid:4)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2)(cid:15) (cid:15)(cid:4)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 7(cid:13)(cid:11)#(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! 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PIC18F8722 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)(cid:28)(cid:29)(cid:27)(cid:28)(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) © 2008 Microchip Technology Inc. DS39646C-page 421

PIC18F8722 FAMILY )(cid:28)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)#(cid:29)(cid:27)#(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) D D1 E e E1 b N NOTE1 123 NOTE2 α A c φ β A1 A2 L L1 6(cid:26)(cid:20)&! (cid:19)(cid:29)77(cid:29)(cid:19).(cid:25).(cid:8)(cid:3) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:14)7(cid:20)’(cid:20)&! (cid:19)(cid:29)8 89(cid:19) (cid:19)(cid:7): 8"’)(cid:13)(cid:22)(cid:14)(cid:23)%(cid:14)7(cid:13)(cid:11)#! 8 @(cid:4) 7(cid:13)(cid:11)#(cid:14)(cid:31)(cid:20)&(cid:21)(cid:24) (cid:13) (cid:4)(cid:30)/(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)<(cid:13)(cid:20)(cid:12)(cid:24)& (cid:7) = = (cid:15)(cid:30)(cid:17)(cid:4) (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:7)(cid:17) (cid:4)(cid:30)(cid:6)/ (cid:15)(cid:30)(cid:4)(cid:4) (cid:15)(cid:30)(cid:4)/ (cid:3)&(cid:11)(cid:26)#(cid:23)%%(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:30)(cid:4)/ = (cid:4)(cid:30)(cid:15)/ 3(cid:23)(cid:23)&(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) 7 (cid:4)(cid:30)(cid:5)/ (cid:4)(cid:30);(cid:4) (cid:4)(cid:30)(cid:18)/ 3(cid:23)(cid:23)&(cid:10)(cid:22)(cid:20)(cid:26)& 7(cid:15) (cid:15)(cid:30)(cid:4)(cid:4)(cid:14)(cid:8).3 3(cid:23)(cid:23)&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13) (cid:3) (cid:4)> (cid:16)(cid:30)/> (cid:18)> 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)?(cid:20)#&(cid:24) . (cid:15)(cid:5)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:15)(cid:5)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)?(cid:20)#&(cid:24) .(cid:15) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2)(cid:15) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 7(cid:13)(cid:11)#(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:21) (cid:4)(cid:30)(cid:4)(cid:6) = (cid:4)(cid:30)(cid:17)(cid:4) 7(cid:13)(cid:11)#(cid:14)?(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:15)(cid:18) (cid:4)(cid:30)(cid:17)(cid:17) (cid:4)(cid:30)(cid:17)(cid:18) (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)(cid:25)(cid:23)(cid:10) (cid:4) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)1(cid:23)&&(cid:23)’ (cid:5) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> ’ (cid:13)(cid:6)(cid:12)( (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) +(cid:24)(cid:11)’%(cid:13)(cid:22)!(cid:14)(cid:11)&(cid:14)(cid:21)(cid:23)(cid:22)(cid:26)(cid:13)(cid:22)!(cid:14)(cid:11)(cid:22)(cid:13)(cid:14)(cid:23)(cid:10)&(cid:20)(cid:23)(cid:26)(cid:11)(cid:27),(cid:14)!(cid:20)-(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)(cid:30) (cid:16)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)!(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:26)#(cid:14).(cid:15)(cid:14)#(cid:23)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:20)(cid:26)(cid:21)(cid:27)"#(cid:13)(cid:14)’(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:30)(cid:14)(cid:19)(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:14)!(cid:24)(cid:11)(cid:27)(cid:27)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:13)$(cid:21)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:30)(cid:17)/(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)!(cid:20)#(cid:13)(cid:30) (cid:5)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19).(cid:14)0(cid:15)(cid:5)(cid:30)/(cid:19)(cid:30) 1(cid:3)+2 1(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8).32 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)+(cid:4)(cid:5)(cid:9)(cid:4)(cid:6)(cid:17)1 DS39646C-page 422 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY )(cid:28)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)#(cid:29)(cid:27)#(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) © 2008 Microchip Technology Inc. DS39646C-page 423

PIC18F8722 FAMILY NOTES: DS39646C-page 424 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY APPENDIX A: REVISION HISTORY Revision C (October 2008) Updated some specifications in Section28.0 “Electrical Revision A (September 2004) Characteristics”, package and land pattern illustrations Original data sheet for the PIC18F8722 family of in Section29.0 “Packaging Information” and the devices. format of all register tables. Revision B (December 2004) APPENDIX B: DEVICE This revision includes updates to the Electrical Specifica- DIFFERENCES tions in Section28.0 “Electrical Characteristics”, minor corrections to the data sheet text and information The differences between the devices listed in this data to support the following devices has been added: sheet are shown in TableB-1. • PIC18F6527 • PIC18LF6527 • PIC18F6622 • PIC18LF6622 • PIC18F8527 • PIC18LF8527 • PIC18F8622 • PIC18LF8622 TABLE B-1: DEVICE DIFFERENCES (PIC18F6527/6622/6627/6722) Features PIC18F6527 PIC18F6622 PIC18F6627 PIC18F6722 Program Memory (Bytes) 48K 64K 96K 128K Program Memory (Instructions) 24576 32768 49152 65536 Interrupt Sources 28 28 28 28 I/O Ports Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, F, G F, G F, G F, G Capture/Compare/PWM Modules 2 2 2 2 Enhanced 3 3 3 3 Capture/Compare/PWM Modules Parallel Communications (PSP) Yes Yes Yes Yes External Memory Bus No No No No 10-bit Analog-to-Digital Module 12 input channels 12 input channels 12 input channels 12 input channels Packages 64-pin TQFP 64-pin TQFP 64-pin TQFP 64-pin TQFP TABLE B-2: DEVICE DIFFERENCES (PIC18F8527/8622/8627/8722) Features PIC18F8527 PIC18F8622 PIC18F8627 PIC18F8722 Program Memory (Bytes) 48K 64K 96K 128K Program Memory (Instructions) 24576 32768 49152 65536 Interrupt Sources 29 29 29 29 I/O Ports Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, F, G, H, J F, G, H, J F, G, H, J F, G, H, J Capture/Compare/PWM Modules 2 2 2 2 Enhanced 3 3 3 3 Capture/Compare/PWM Modules Parallel Communications (PSP) Yes Yes Yes Yes External Memory Bus Yes Yes Yes Yes 10-bit Analog-to-Digital Module 16 input channels 16 input channels 16 input channels 16 input channels Packages 80-pin TQFP 80-pin TQFP 80-pin TQFP 80-pin TQFP © 2008 Microchip Technology Inc. DS39646C-page 425

PIC18F8722 FAMILY APPENDIX C: CONVERSION APPENDIX D: MIGRATION FROM CONSIDERATIONS BASELINE TO ENHANCED DEVICES This appendix discusses the considerations for converting from previous versions of a device to the This section discusses how to migrate from a Baseline ones listed in this data sheet. Typically, these changes device (i.e., PIC16C5X) to an Enhanced MCU device are due to the differences in the process technology (i.e., PIC18FXXX). used. An example of this type of conversion is from a The following are the list of modifications over the PIC16C74A to a PIC16C74B. PIC16C5X microcontroller family: Not Applicable Not Currently Available DS39646C-page 426 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY APPENDIX E: MIGRATION FROM APPENDIX F: MIGRATION FROM MID-RANGE TO HIGH-END TO ENHANCED DEVICES ENHANCED DEVICES A detailed discussion of the differences between the A detailed discussion of the migration pathway and mid-range MCU devices (i.e., PIC16CXXX) and the differences between the high-end MCU devices (i.e., enhanced devices (i.e., PIC18FXXX) is provided in PIC17CXXX) and the enhanced devices (i.e., AN716, “Migrating Designs from PIC16C74A/74B to PIC18FXXX) is provided in AN726, “PIC17CXXX to PIC18C442”. The changes discussed, while device PIC18CXXX Migration”. specific, are generally applicable to all mid-range to This Application Note is available on our web site, enhanced device migrations. www.microchip.com, as Literature Number DS00726. This Application Note is available on our web site, www.microchip.com, as Literature Number DS00716. © 2008 Microchip Technology Inc. DS39646C-page 427

PIC18F8722 FAMILY NOTES: DS39646C-page 428 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY INDEX A Analog Input Model ..................................................275 Baud Rate Generator ..............................................232 A/D ...................................................................................271 Capture Mode Operation .........................................181 A/D Converter Interrupt, Configuring .......................275 Comparator Analog Input Model ..............................285 Acquisition Requirements ........................................276 Comparator I/O Operating Modes ...........................282 ADCON0 Register ....................................................271 Comparator Output ..................................................284 ADCON1 Register ....................................................271 Comparator Voltage Reference ...............................288 ADCON2 Register ....................................................271 Comparator Voltage Reference Output ADRESH Register ............................................271, 274 Buffer Example ................................................289 ADRESL Register ....................................................271 Compare Mode Operation .......................................182 Analog Port Pins ......................................................158 Device Clock ..............................................................37 Analog Port Pins, Configuring ..................................278 Enhanced PWM .......................................................193 Associated Registers ...............................................280 EUSART Receive ....................................................260 Configuring the Module ............................................275 EUSART Transmit ...................................................258 Conversion Clock (TAD) ...........................................277 External Power-on Reset Circuit Conversion Status (GO/DONE Bit) ..........................274 Conversions .............................................................279 (Slow VDD Power-up) ........................................51 Fail-Safe Clock Monitor (FSCM) ..............................315 Converter Characteristics ........................................416 Generic I/O Port Operation ......................................135 Discharge .................................................................279 High/Low-Voltage Detect with External Input ..........292 Operation in Power-Managed Modes ......................278 HSPLL .......................................................................33 Selecting and Configuring Acquisition Time ............277 Interrupt Logic ..........................................................120 Special Event Trigger (ECCP) .................................192 INTOSC and PLL .......................................................34 Special Event Trigger (ECCP2) ...............................280 MSSP (I2C Master Mode) ........................................230 Use of the ECCP2 Trigger .......................................280 MSSP (I2C Mode) ....................................................215 Absolute Maximum Ratings .............................................375 MSSP (SPI Mode) ...................................................205 AC (Timing) Characteristics .............................................396 On-Chip Reset Circuit ................................................49 Load Conditions for Device PIC18F6527/6622/6627/6722 ...................................11 Timing Specifications .......................................397 PIC18F8527/8622/8627/8722 ...................................12 Parameter Symbology .............................................396 PORTD and PORTE (Parallel Slave Port) ...............158 Temperature and Voltage Specifications .................397 PWM Operation (Simplified) ....................................184 Timing Conditions ....................................................397 Reads from Flash Program Memory .........................91 Access Bank Single Comparator ...................................................283 Mapping in Indexed Literal Offset Mode ....................85 Table Read Operation ...............................................87 ACKSTAT ........................................................................236 Table Write Operation ...............................................88 ACKSTAT Status Flag .....................................................236 Table Writes to Flash Program Memory ....................93 ADCON0 Register ............................................................271 Timer0 in 16-Bit Mode .............................................162 GO/DONE Bit ...........................................................274 Timer0 in 8-Bit Mode ...............................................162 ADCON1 Register ............................................................271 Timer1 .....................................................................166 ADCON2 Register ............................................................271 Timer1 (16-Bit Read/Write Mode) ............................166 ADDFSR ..........................................................................364 Timer2 .....................................................................172 ADDLW ............................................................................327 Timer3 .....................................................................174 ADDULNK ........................................................................364 Timer3 (16-Bit Read/Write Mode) ............................174 ADDWF ............................................................................327 Timer4 .....................................................................178 ADDWFC .........................................................................328 Watchdog Timer ......................................................312 ADRESH Register ............................................................271 BN ....................................................................................330 ADRESL Register ....................................................271, 274 BNC .................................................................................331 Analog-to-Digital Converter. See A/D. BNN .................................................................................331 ANDLW ............................................................................328 BNOV ..............................................................................332 ANDWF ............................................................................329 BNZ .................................................................................332 Assembler BOR. See Brown-out Reset. MPASM Assembler ..................................................372 BOV .................................................................................335 Auto-Wake-up on Sync Break Character .........................262 BRA .................................................................................333 B Break Character (12-Bit) Transmit and Receive ..............263 Bank Select Register (BSR) ...............................................72 BRG. See Baud Rate Generator. Baud Rate Generator .......................................................232 Brown-out Reset (BOR) .....................................................52 BC ....................................................................................329 Detecting ...................................................................52 BCF ..................................................................................330 Disabling in Sleep Mode ............................................52 BF ....................................................................................236 Software Enabled ......................................................52 BF Status Flag .................................................................236 BSF ..................................................................................333 Block Diagrams BTFSC .............................................................................334 16-Bit Byte Select Mode ..........................................103 BTFSS .............................................................................334 16-Bit Byte Write Mode ............................................101 BTG .................................................................................335 16-Bit Word Write Mode ...........................................102 BZ ....................................................................................336 A/D ...........................................................................274 © 2008 Microchip Technology Inc. DS39646C-page 429

PIC18F8722 FAMILY C Operation .................................................................283 Operation During Sleep ...........................................284 C Compilers Outputs ....................................................................283 MPLAB C18 .............................................................372 Reference ................................................................283 MPLAB C30 .............................................................372 External Signal ................................................283 CALL ................................................................................336 Internal Signal ..................................................283 CALLW .............................................................................365 Response Time ........................................................283 Capture (CCP Module) .....................................................181 Comparator Specifications ...............................................394 Associated Registers ...............................................183 Comparator Voltage Reference .......................................287 CCPRxH:CCPRxL Registers ...................................181 Accuracy and Error ..................................................288 CCPx Pin Configuration ...........................................181 Associated Registers ...............................................289 Prescaler ..................................................................181 Configuring ..............................................................287 Software Interrupt ....................................................181 Connection Considerations ......................................288 Timer1/Timer3 Mode Selection ................................181 Effects of a Reset ....................................................288 Capture (ECCP Module) ..................................................192 Operation During Sleep ...........................................288 Capture/Compare/PWM (CCP) ........................................179 Comparator Voltage Reference Specifications ................394 Capture Mode. See Capture. Compare (CCP Module) ..................................................182 CCP Mode and Timer Resources ............................180 Associated Registers ...............................................183 CCPRxH Register ....................................................180 CCPRx Registers .....................................................182 CCPRxL Register .....................................................180 Pin Configuration .....................................................182 Compare Mode. See Compare. Software Interrupt ....................................................182 Interconnect Configurations .....................................180 Special Event Trigger ..............................................182 Module Configuration ...............................................180 Timer1/Timer3 Mode Selection ................................182 Clock Sources ....................................................................37 Compare (CCP Modules) Selecting the 31 kHz Source ......................................38 Special Event Trigger ..............................................175 Selection Using OSCCON Register ...........................38 Compare (ECCP Module) ................................................192 CLRF ................................................................................337 Special Event Trigger ..............................................192 CLRWDT ..........................................................................337 Compare (ECCP2 Module) Code Examples Special Event Trigger ..............................................280 16 x 16 Signed Multiply Routine ..............................118 Computed GOTO ...............................................................68 16 x 16 Unsigned Multiply Routine ..........................118 Configuration Bits ............................................................297 8 x 8 Signed Multiply Routine ..................................117 Configuration Register Protection ....................................320 8 x 8 Unsigned Multiply Routine ..............................117 Context Saving During Interrupts .....................................134 Changing Between Capture Prescalers ...................181 Conversion Considerations ..............................................426 Computed GOTO Using an Offset Value ...................68 CPFSEQ ..........................................................................338 Data EEPROM Read ...............................................113 CPFSGT ..........................................................................339 Data EEPROM Refresh Routine ..............................114 CPFSLT ...........................................................................339 Data EEPROM Write ...............................................113 Crystal Oscillator/Ceramic Resonator ................................31 Erasing a Flash Program Memory Row .....................92 Customer Change Notification Service ............................439 Fast Register Stack ....................................................68 Customer Notification Service .........................................439 How to Clear RAM (Bank 1) Using Customer Support ............................................................439 Indirect Addressing ............................................81 Implementing a Real-Time Clock D Using a Timer1 Interrupt Service .....................169 Data Addressing Modes ....................................................81 Initializing PORTA ....................................................135 Comparing Addressing Modes with the Initializing PORTB ....................................................137 Extended Instruction Set Enabled .....................84 Initializing PORTC ....................................................140 Direct .........................................................................81 Initializing PORTD ....................................................143 Indexed Literal Offset ................................................83 Initializing PORTE ....................................................146 Instructions Affected ..........................................83 Initializing PORTF ....................................................149 Indirect .......................................................................81 Initializing PORTG ...................................................151 Inherent and Literal ....................................................81 Initializing PORTH ....................................................154 Data EEPROM Initializing PORTJ ....................................................156 Code Protection .......................................................320 Loading the SSP1BUF (SSP1SR) Register .............208 Data EEPROM Memory ...................................................111 Reading a Flash Program Memory Word ..................91 Associated Registers ...............................................115 Saving STATUS, WREG and BSR EEADR and EEADRH Registers .............................111 Registers in RAM .............................................134 EECON1 and EECON2 Registers ...........................111 Writing to Flash Program Memory .......................94–95 Operation During Code-Protect ...............................114 Code Protection ...............................................................297 Protection Against Spurious Write ...........................114 COMF ...............................................................................338 Reading ...................................................................113 Comparator ......................................................................281 Using .......................................................................114 Analog Input Connection Considerations .................285 Write Verify ..............................................................113 Associated Registers ...............................................285 Writing .....................................................................113 Configuration ............................................................282 Effects of a Reset .....................................................284 Interrupts ..................................................................284 DS39646C-page 430 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY Data Memory .....................................................................72 Baud Rate Generator (BRG) ...................................251 Access Bank ..............................................................74 Associated Registers .......................................252 and the Extended Instruction Set ...............................83 Auto-Baud Rate Detect ....................................255 Bank Select Register (BSR) .......................................72 Baud Rate Error, Calculating ...........................252 General Purpose Registers ........................................74 Baud Rates, Asynchronous Modes .................253 Map for PIC18F8722 Family ......................................73 High Baud Rate Select (BRGH Bit) .................251 Special Function Registers ........................................75 Sampling .........................................................251 DAW .................................................................................340 Synchronous Master Mode ......................................264 DC Characteristics ...........................................................391 Associated Registers, Receive ........................267 Power-Down and Supply Current ............................379 Associated Registers, Transmit .......................265 Supply Voltage .........................................................378 Reception ........................................................266 DCFSNZ ..........................................................................341 Transmission ...................................................264 DECF ...............................................................................340 Synchronous Slave Mode ........................................268 DECFSZ ...........................................................................341 Associated Registers, Receive ........................269 Development Support ......................................................371 Associated Registers, Transmit .......................268 Device Differences ...........................................................425 Reception ........................................................269 Device Overview ..................................................................7 Transmission ...................................................268 Details on Individual Family Members .........................9 Extended Instruction Set Features (table) ......................................................9, 10 ADDFSR ..................................................................364 New Core Features ......................................................7 ADDULNK ...............................................................364 Device Reset Timers ..........................................................53 CALLW ....................................................................365 Oscillator Start-up Timer (OST) .................................53 MOVSF ....................................................................365 PLL Lock Time-out .....................................................53 MOVSS ....................................................................366 Power-up Timer (PWRT) ...........................................53 PUSHL .....................................................................366 Time-out Sequence ....................................................53 SUBFSR ..................................................................367 Direct Addressing ...............................................................82 SUBULNK ................................................................367 Extended Microcontroller Mode .......................................100 E External Clock Input ...........................................................32 ECCP External Memory Bus ........................................................97 Capture and Compare Modes ..................................192 16-Bit Byte Select Mode ..........................................103 Standard PWM Mode ...............................................192 16-Bit Byte Write Mode ............................................101 Effect on Standard PIC MCU Instructions ........................368 16-Bit Data Width Modes .........................................100 Effects of Power-Managed Modes on Various 16-Bit Mode Timing .................................................104 Clock Sources ............................................................40 16-Bit Word Write Mode ..........................................102 Electrical Characteristics ..................................................375 8-Bit Data Width Modes ...........................................106 Enhanced Capture/Compare/PWM (ECCP) ....................187 8-Bit Mode Timing ...................................................107 and Program Memory Modes ..................................188 I/O Port Functions ......................................................97 Capture Mode. See Capture (ECCP Module). Operation in Power-Managed Modes ......................109 Outputs and Configuration .......................................188 F Pin Configurations for ECCP1 .................................189 Pin Configurations for ECCP2 .................................190 Fail-Safe Clock Monitor ...........................................297, 315 Pin Configurations for ECCP3 .................................191 Exiting Operation .....................................................315 PWM Mode. See PWM (ECCP Module). Interrupts in Power-Managed Modes ......................316 Timer Resources ......................................................192 POR or Wake from Sleep ........................................316 Enhanced PWM Mode. See PWM (ECCP Module). WDT During Oscillator Failure .................................315 Enhanced Universal Synchronous Asynchronous Fast Register Stack ...........................................................68 Receiver Transmitter (EUSART). See EUSART. Firmware Instructions ......................................................321 Equations Flash Program Memory .....................................................87 A/D Acquisition Time ................................................276 Associated Registers .................................................95 A/D Minimum Charging Time ...................................276 Control Registers .......................................................88 A/D, Calculating the Minimum Required EECON1 and EECON2 .....................................88 Acquisition Time ..............................................276 TABLAT (Table Latch) Register ........................90 Errata ...................................................................................5 TBLPTR (Table Pointer) Register ......................90 EUSART Erase Sequence ........................................................92 Asynchronous Mode ................................................257 Erasing ......................................................................92 12-Bit Break Transmit and Receive .................263 Operation During Code-Protect .................................95 Associated Registers, Receive ........................261 Reading .....................................................................91 Associated Registers, Transmit .......................259 Table Pointer Auto-Wake-up on Sync Break .........................262 Boundaries Based on Operation .......................90 Receiver ...........................................................260 Table Pointer Boundaries ..........................................90 Setting up 9-Bit Mode with Table Reads and Table Writes ..................................87 Address Detect ........................................260 Write Sequence .........................................................93 Transmitter .......................................................257 Writing To ..................................................................93 Baud Rate Generator Protection Against Spurious Writes ...................95 Operation in Power-Managed Modes ..............251 Unexpected Termination ...................................95 Write Verify ........................................................95 FSCM. See Fail-Safe Clock Monitor. © 2008 Microchip Technology Inc. DS39646C-page 431

PIC18F8722 FAMILY G Indexed Literal Offset Addressing and Standard PIC18 Instructions .............................368 General Call Address Support .........................................229 Indexed Literal Offset Mode .............................................368 GOTO ...............................................................................342 Indirect Addressing ............................................................82 H INFSNZ ............................................................................343 Hardware Multiplier ..........................................................117 Initialization Conditions for all Registers ......................57–61 Introduction ..............................................................117 Instruction Cycle ................................................................69 Operation .................................................................117 Clocking Scheme .......................................................69 Performance Comparison ........................................117 Instruction Flow/Pipelining .................................................69 High/Low-Voltage Detect .................................................291 Instruction Set ..................................................................321 Applications ..............................................................294 ADDLW ....................................................................327 Associated Registers ...............................................295 ADDWF ....................................................................327 Characteristics .........................................................395 ADDWF (Indexed Literal Offset Mode) ....................369 Current Consumption ...............................................293 ADDWFC .................................................................328 Effects of a Reset .....................................................295 ANDLW ....................................................................328 Operation .................................................................292 ANDWF ....................................................................329 During Sleep ....................................................295 BC ............................................................................329 Setup ........................................................................293 BCF .........................................................................330 Start-up Time ...........................................................293 BN ............................................................................330 Typical Application ...................................................294 BNC .........................................................................331 HLVD. See High/Low-Voltage Detect. .............................291 BNN .........................................................................331 BNOV ......................................................................332 I BNZ .........................................................................332 I/O Ports ...........................................................................135 BOV .........................................................................335 I2C Mode (MSSP) BRA .........................................................................333 Acknowledge Sequence Timing ...............................239 BSF ..........................................................................333 Associated Registers ...............................................245 BSF (Indexed Literal Offset Mode) ..........................369 Baud Rate Generator ...............................................232 BTFSC .....................................................................334 Bus Collision BTFSS .....................................................................334 During a Repeated Start Condition ..................243 BTG .........................................................................335 During a Stop Condition ...................................244 BZ ............................................................................336 Clock Arbitration .......................................................233 CALL ........................................................................336 Clock Stretching .......................................................225 CLRF .......................................................................337 10-Bit Slave Receive Mode (SEN = 1) .............225 CLRWDT .................................................................337 10-Bit Slave Transmit Mode .............................225 COMF ......................................................................338 7-Bit Slave Receive Mode (SEN = 1) ...............225 CPFSEQ ..................................................................338 7-Bit Slave Transmit Mode ...............................225 CPFSGT ..................................................................339 Clock Synchronization and the CKP bit ...................226 CPFSLT ...................................................................339 Effects of a Reset .....................................................240 DAW ........................................................................340 General Call Address Support .................................229 DCFSNZ ..................................................................341 I2C Clock Rate w/BRG .............................................232 DECF .......................................................................340 Master Mode ............................................................230 DECFSZ ..................................................................341 Operation .........................................................231 Extended Instructions ..............................................363 Reception .........................................................236 Considerations when Enabling ........................368 Repeated Start Condition Timing .....................235 Syntax ..............................................................363 Start Condition Timing .....................................234 Use with MPLAB IDE Tools .............................370 Transmission ....................................................236 General Format ........................................................323 Multi-Master Communication, Bus Collision GOTO ......................................................................342 and Arbitration ..................................................240 INCF ........................................................................342 Multi-Master Mode ...................................................240 INCFSZ ....................................................................343 Operation .................................................................219 INFSNZ ....................................................................343 Read/Write Bit Information (R/W Bit) ...............219, 220 IORLW .....................................................................344 Registers ..................................................................215 IORWF .....................................................................344 Serial Clock (RC3/SCKx/SCLx) ...............................220 LFSR .......................................................................345 Slave Mode ..............................................................219 MOVF ......................................................................345 Addressing .......................................................219 MOVFF ....................................................................346 Reception .........................................................220 MOVLB ....................................................................346 Transmission ....................................................220 MOVLW ...................................................................347 Sleep Operation .......................................................240 MOVWF ...................................................................347 Stop Condition Timing ..............................................239 MULLW ....................................................................348 ID Locations .............................................................297, 320 MULWF ....................................................................348 INCF .................................................................................342 NEGF .......................................................................349 INCFSZ ............................................................................343 NOP .........................................................................349 In-Circuit Debugger ..........................................................320 POP .........................................................................350 In-Circuit Serial Programming (ICSP) ......................297, 320 PUSH .......................................................................350 DS39646C-page 432 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY RCALL .....................................................................351 L RESET .....................................................................351 LFSR ...............................................................................345 RETFIE ....................................................................352 Low-Voltage ICSP Programming. See Single-Supply RETLW ....................................................................352 ICSP Programming RETURN ..................................................................353 RLCF ........................................................................353 M RLNCF .....................................................................354 Master Clear (MCLR) .........................................................51 RRCF .......................................................................354 Master Synchronous Serial Port (MSSP). See MSSP. RRNCF ....................................................................355 Memory SETF ........................................................................355 Mode Memory Access ...............................................64 SETF (Indexed Literal Offset Mode) ........................369 Memory Maps for PIC18F8722 Family SLEEP .....................................................................356 Program Memory Modes ...........................................65 Standard Instructions ...............................................321 Memory Organization ........................................................63 SUBFWB ..................................................................356 Data Memory .............................................................72 SUBLW ....................................................................357 Program Memory .......................................................63 SUBWF ....................................................................357 Modes ................................................................63 SUBWFB ..................................................................358 Memory Programming Requirements ..............................393 SWAPF ....................................................................358 Microchip Internet Web Site .............................................439 TBLRD .....................................................................359 Microcontroller Mode .......................................................100 TBLWT .....................................................................360 Microprocessor Mode ......................................................100 TSTFSZ ...................................................................361 Microprocessor with Boot Block Mode .............................100 XORLW ....................................................................361 Migration from Baseline to Enhanced Devices ................426 XORWF ....................................................................362 Migration from High-End to Enhanced Devices ...............427 INTCON Register Migration from Mid-Range to Enhanced Devices ............427 RBIF Bit ....................................................................137 MOVF ..............................................................................345 INTCON Registers ...........................................................121 MOVFF ............................................................................346 Inter-Integrated Circuit. See I2C. MOVLB ............................................................................346 Internal Oscillator Block .....................................................34 MOVLW ...........................................................................347 Adjustment .................................................................34 MOVSF ............................................................................365 INTIO Modes ..............................................................34 MOVSS ............................................................................366 INTOSC Frequency Drift ............................................35 MOVWF ...........................................................................347 INTOSC Output Frequency ........................................34 MPLAB ASM30 Assembler, Linker, Librarian ..................372 OSCTUNE Register ...................................................34 MPLAB ICD 2 In-Circuit Debugger ..................................373 PLL in INTOSC Modes ..............................................35 MPLAB ICE 2000 High-Performance Internal RC Oscillator Universal In-Circuit Emulator ...................................373 Use with WDT ..........................................................312 MPLAB Integrated Development Internet Address ...............................................................439 Environment Software .............................................371 Interrupt Sources .............................................................297 MPLAB PM3 Device Programmer ...................................373 A/D Conversion Complete .......................................275 MPLAB REAL ICE In-Circuit Emulator System ...............373 Capture Complete (CCP) .........................................181 MPLINK Object Linker/MPLIB Object Librarian ...............372 Compare Complete (CCP) .......................................182 MSSP Interrupt-on-Change (RB7:RB4) ..............................137 ACK Pulse .......................................................219, 220 INTx Pin ...................................................................134 Control Registers (general) .....................................205 PORTB, Interrupt-on-Change ..................................134 I2C Mode. See I2C Mode. TMR0 .......................................................................134 Module Overview .....................................................205 TMR0 Overflow ........................................................163 SPI Master/Slave Connection ..................................209 TMR1 Overflow ........................................................165 TMR4 Output for Clock Shift ....................................178 TMR2 to PR2 Match (PWM) ............................184, 192 MULLW ............................................................................348 TMR3 Overflow ................................................173, 175 MULWF ............................................................................348 TMR4 to PR4 Match ................................................178 TMR4 to PR4 Match (PWM) ....................................177 N Interrupts ..........................................................................119 NEGF ...............................................................................349 Interrupts, Flag Bits NOP .................................................................................349 Interrupt-on-Change (RB7:RB4) Flag O (RBIF Bit) ........................................................137 INTOSC, INTRC. See Internal Oscillator Block. Opcode Field Descriptions ...............................................322 IORLW .............................................................................344 Oscillator Configuration .....................................................31 IORWF .............................................................................344 EC ..............................................................................31 IPR Registers ...................................................................130 ECIO ..........................................................................31 HS ..............................................................................31 K HSPLL .......................................................................31 Key Features Internal Oscillator Block .............................................34 Easy Migration .............................................................8 INTIO1 .......................................................................31 Expanded Memory .......................................................7 INTIO2 .......................................................................31 External Memory Interface ...........................................8 LP ..............................................................................31 © 2008 Microchip Technology Inc. DS39646C-page 433

PIC18F8722 FAMILY RC ..............................................................................31 RD7/AD7/PSP7/SS2 ..................................................25 RCIO ..........................................................................31 RD7/PSP7/SS2 .........................................................17 XT ..............................................................................31 RE0/AD8/RD/P2D ......................................................26 Oscillator Selection ..........................................................297 RE0/RD/P2D ..............................................................18 Oscillator Start-up Timer (OST) ...................................40, 53 RE1/AD9/WR/P2C .....................................................26 Oscillator Switching ............................................................37 RE1/WR/P2C .............................................................18 Oscillator Transitions ..........................................................38 RE2/AD10/CS/P2B ....................................................26 Oscillator, Timer1 .....................................................165, 175 RE2/CS/P2D ..............................................................18 Oscillator, Timer3 .............................................................173 RE3/AD11/P3C ..........................................................26 RE3/P3C ....................................................................18 P RE4/AD12/P3B ..........................................................26 Packaging ........................................................................419 RE4/P3B ....................................................................18 Details ......................................................................420 RE5/AD13/P1C ..........................................................26 Marking ....................................................................419 RE5/P1C ....................................................................18 Parallel Slave Port (PSP) .................................................158 RE6/AD14/P1B ..........................................................26 Associated Registers ...............................................160 RE6/P1B ....................................................................18 RE0/RD Pin ..............................................................158 RE7/AD15/ECCP2/P2A .............................................26 RE1/WR Pin .............................................................158 RE7/ECCP2/P2A .......................................................18 RE2/CS Pin ..............................................................158 RF0/AN5 ..............................................................19, 27 Select (PSPMODE Bit) ............................................158 RF1/AN6/C2OUT .................................................19, 27 PICSTART Plus Development Programmer ....................374 RF2/AN7/C1OUT .................................................19, 27 PIE Registers ...................................................................127 RF3/AN8 ..............................................................19, 27 Pin Functions RF4/AN9 ..............................................................19, 27 AVDD ..........................................................................20 RF5/AN10/CVREF ................................................19, 27 AVDD ..........................................................................30 RF6/AN11 ............................................................19, 27 AVSS ..........................................................................20 RF7/SS1 ..............................................................19, 27 AVSS ..........................................................................30 RG0/ECCP3/P3A .................................................20, 28 OSC1/CLKI/RA7 ..................................................13, 21 RG1/TX2/CK2 ......................................................20, 28 OSC2/CLKO/RA6 ................................................13, 21 RG2/RX2/DT2 ......................................................20, 28 RA0/AN0 ..............................................................14, 22 RG3/CCP4/P3D ...................................................20, 28 RA1/AN1 ..............................................................14, 22 RG4/CCP5/P1D ...................................................20, 28 RA2/AN2/VREF- ....................................................14, 22 RG5 .....................................................................20, 28 RA3/AN3/VREF+ ...................................................14, 22 RG5/MCLR/VPP ...................................................13, 21 RA4/T0CKI ...........................................................14, 22 RH0/A16 ....................................................................29 RA5/AN4/HLVDIN ................................................14, 22 RH1/A17 ....................................................................29 RB0/INT0/FLT0 ....................................................15, 23 RH2/A18 ....................................................................29 RB1/INT1 .............................................................15, 23 RH3/A19 ....................................................................29 RB2/INT2 .............................................................15, 23 RH4/AN12/P3C ..........................................................29 RB3/INT3 ...................................................................15 RH5/AN13/P3B ..........................................................29 RB3/INT3/ECCP2/P2A ..............................................23 RH6/AN14/P1C ..........................................................29 RB4/KBI0 .............................................................15, 23 RH7/AN15/P1B ..........................................................29 RB5/KBI1/PGM ....................................................15, 23 RJ0/ALE ....................................................................30 RB6/KBI2/PGC ....................................................15, 23 RJ1/OE ......................................................................30 RB7/KBI3/PGD ....................................................15, 23 RJ2/WRL ...................................................................30 RC0/T1OSO/T13CKI ...........................................16, 24 RJ3/WRH ...................................................................30 RC1/T1OSI/ECCP2/P2A ......................................16, 24 RJ4/BA0 ....................................................................30 RC2/ECCP1/P1A .................................................16, 24 RJ5/CE ......................................................................30 RC3/SCK1/SCL1 .................................................16, 24 RJ6/LB .......................................................................30 RC4/SDI1/SDA1 ..................................................16, 24 RJ7/UB ......................................................................30 RC5/SDO1 ...........................................................16, 24 VDD ............................................................................20 RC6/TX1/CK1 ......................................................16, 24 VDD ............................................................................30 RC7/RX1/DT1 ......................................................16, 24 VSS ............................................................................20 RD0/AD0/PSP0 ..........................................................25 VSS ............................................................................30 RD0/PSP0 ..................................................................17 Pinout I/O Descriptions RD1/AD1/PSP1 ..........................................................25 PIC18F6527/6622/6627/6722 ...................................13 RD1/PSP1 ..................................................................17 PIC18F8527/8622/8627/8722 ...................................21 RD2/AD2/PSP2 ..........................................................25 PIR Registers ...................................................................124 RD2/PSP2 ..................................................................17 PLL Frequency Multiplier ...................................................33 RD3/AD3/PSP3 ..........................................................25 HSPLL Oscillator Mode .............................................33 RD3/PSP3 ..................................................................17 Use with INTOSC ......................................................33 RD4/AD4/PSP4/SDO2 ...............................................25 POP .................................................................................350 RD4/PSP4/SDO2 .......................................................17 POR. See Power-on Reset. RD5/AD5/PSP5/SDI2/SDA2 ......................................25 RD5/PSP5/SDI2/SDA2 ..............................................17 RD6/AD6/PSP6/SCK2/SCL2 .....................................25 RD6/PSP6/SCK2/SCL2 .............................................17 DS39646C-page 434 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY PORTA Power-Managed Modes .....................................................41 Associated Registers ...............................................136 and A/D Operation ...................................................278 Functions .................................................................136 and EUSART Operation ..........................................251 LATA Register ..........................................................135 and Multiple Sleep Commands ..................................42 PORTA Register ......................................................135 and PWM Operation ................................................203 TRISA Register ........................................................135 and SPI Operation ...................................................213 PORTB Associated Registers ...............................................109 Associated Registers ...............................................139 Clock Transitions and Status Indicators ....................42 Functions .................................................................138 Effects on Clock Sources ..........................................40 LATB Register ..........................................................137 Entering .....................................................................41 PORTB Register ......................................................137 Exiting Idle and Sleep Modes ....................................47 RB7:RB4 Interrupt-on-Change Flag by Interrupt ........................................................47 (RBIF Bit) .........................................................137 by Reset ............................................................47 TRISB Register ........................................................137 by WDT Time-out ..............................................47 PORTC Without a Start-up Delay ...................................48 Associated Registers ...............................................142 Idle Modes .................................................................45 Functions .................................................................141 PRI_IDLE ..........................................................46 LATC Register .........................................................140 RC_IDLE ...........................................................47 PORTC Register ......................................................140 SEC_IDLE .........................................................46 RC3/SCKx/SCLx Pin ................................................220 Run Modes ................................................................42 TRISC Register ........................................................140 PRI_RUN ...........................................................42 PORTD ............................................................................158 RC_RUN ............................................................43 Associated Registers ...............................................145 SEC_RUN .........................................................42 Functions .................................................................144 Selecting ....................................................................41 LATD Register .........................................................143 Sleep Mode ...............................................................45 PORTD Register ......................................................143 Summary (table) ........................................................41 TRISD Register ........................................................143 Power-on Reset (POR) ......................................................51 PORTE Power-up Timer (PWRT) ...........................................53 Analog Port Pins ......................................................158 Time-out Sequence ...................................................53 Associated Registers ...............................................148 Power-up Delays ...............................................................40 Functions .................................................................147 Power-up Timer (PWRT) ...................................................40 LATE Register ..........................................................146 Prescaler PORTE Register ......................................................146 Timer2 .....................................................................193 PSP Mode Select (PSPMODE Bit) ..........................158 Prescaler, Timer0 ............................................................163 RE0/RD Pin ..............................................................158 Prescaler, Timer2 ............................................................185 RE1/WR Pin .............................................................158 PRI_IDLE Mode .................................................................46 RE2/CS Pin ..............................................................158 PRI_RUN Mode .................................................................42 TRISE Register ........................................................146 Program Counter ...............................................................66 PORTF PCL, PCH and PCU Registers ..................................66 Associated Registers ...............................................150 PCLATH and PCLATU Registers ..............................66 Functions .................................................................150 Program Memory LATF Register ..........................................................149 and Extended Instruction Set ....................................85 PORTF Register ......................................................149 Code Protection .......................................................318 TRISF Register ........................................................149 Extended Microcontroller Mode .................................63 PORTG Instructions ................................................................70 Associated Registers ...............................................153 Two-Word ..........................................................71 Functions .................................................................152 Interrupt Vector ..........................................................63 LATG Register .........................................................151 Look-up Tables ..........................................................68 PORTG Register ......................................................151 Map and Stack (diagram) ..........................................64 TRISG Register ........................................................151 Microcontroller Mode .................................................63 PORTH Microprocessor Mode ................................................63 Associated Registers ...............................................155 Microprocessor with Boot Block Mode ......................63 Functions .................................................................155 Reset Vector ..............................................................63 LATH Register .........................................................154 Program Verification and Code Protection ......................317 PORTH Register ......................................................154 Associated Registers ...............................................318 TRISH Register ........................................................154 Programming, Device Instructions ...................................321 PORTJ PSP.See Parallel Slave Port. Associated Registers ...............................................157 Pulse-Width Modulation. See PWM (CCP Module) Functions .................................................................157 and PWM (ECCP Module). LATJ Register ..........................................................156 PUSH ...............................................................................350 PORTJ Register .......................................................156 PUSH and POP Instructions ..............................................67 TRISJ Register .........................................................156 PUSHL .............................................................................366 © 2008 Microchip Technology Inc. DS39646C-page 435

PIC18F8722 FAMILY PWM (CCP Module) DEVID2 (Device ID 2) ..............................................311 Associated Registers ...............................................186 ECCPxDEL (Enhanced PWM Duty Cycle ................................................................184 Dead-Band Delay) ...........................................200 Example Frequencies/Resolutions ..........................185 EECON1 (Data EEPROM Control 1) .......................112 Period .......................................................................184 EECON1 (EEPROM Control 1) .................................89 Setup for PWM Operation ........................................185 HLVDCON (High/Low-Voltage Detect Control) .......291 TMR2 to PR2 Match ................................................184 INTCON (Interrupt Control) ......................................121 TMR4 to PR4 Match ................................................177 INTCON2 (Interrupt Control 2) .................................122 PWM (ECCP Module) ......................................................192 INTCON3 (Interrupt Control 3) .................................123 Associated Registers ...............................................204 IPR1 (Peripheral Interrupt Priority 1) .......................130 CCPR1H:CCPR1L Registers ...................................192 IPR2 (Peripheral Interrupt Priority 2) .......................131 Direction Change in Full-Bridge Output Mode .........198 MEMCON (External Memory Bus Control) ................98 Duty Cycle ................................................................193 OSCCON (Oscillator Control) ....................................39 Effects of a Reset .....................................................203 OSCTUNE (Oscillator Tuning) ...................................35 Enhanced PWM Auto-Shutdown .............................200 PIR1 (Peripheral Interrupt Request (Flag) 1) ...........124 Example Frequencies/Resolutions ..........................193 PIR2 (Peripheral Interrupt Request (Flag) 2) ...........125 Full-Bridge Application Example ..............................198 PSPCON (Parallel Slave Port Control) ....................159 Full-Bridge Mode ......................................................197 RCON (Reset Control) .......................................50, 133 Half-Bridge Mode .....................................................196 RCSTAx (Receive Status and Control) ....................249 Half-Bridge Output Mode SSPxCON1 (MSSPx Control 1, I2C Mode) ..............217 Applications Example .......................................196 SSPxCON1 (MSSPx Control 1, SPI Mode) .............207 Operation in Power-Managed Modes ......................203 SSPxCON2 (MSSPx Control 2, I2C Mode) ..............219 Operation with Fail-Safe Clock Monitor ...................203 SSPxSTAT (MSSPx Status, I2C Mode) ...................216 Output Configurations ..............................................194 SSPxSTAT (MSSPx Status, SPI Mode) ..................206 Output Relationships (Active-High) ..........................194 STATUS (Arithmetic Status) ......................................80 Output Relationships (Active-Low) ...........................195 STKPTR (Stack Pointer) ............................................67 Period .......................................................................192 T0CON (Timer0 Control) .........................................161 Programmable Dead-Band Delay ............................200 T1CON (Timer1 Control) .........................................165 Setup for PWM Operation ........................................203 T2CON (Timer2 Control) .........................................171 Start-up Considerations ...........................................202 T3CON (Timer3 Control) .........................................173 TMR2 to PR2 Match ................................................192 T4CON (Timer 4 Control) ........................................177 TXSTAx (Transmit Status and Control) ...................248 Q WDTCON (Watchdog Timer Control) ......................313 Q Clock ....................................................................185, 193 RESET .............................................................................351 Reset State of Registers ....................................................56 R Resets ........................................................................49, 297 RAM. See Data Memory. Brown-out Reset (BOR) ...........................................297 RC Oscillator ......................................................................33 Oscillator Start-up Timer (OST) ...............................297 RCIO Oscillator Mode ................................................33 Power-on Reset (POR) ............................................297 RC_IDLE Mode ..................................................................47 Power-up Timer (PWRT) .........................................297 RC_RUN Mode ..................................................................43 RETFIE ............................................................................352 RCALL ..............................................................................351 RETLW ............................................................................352 RCON Register RETURN ..........................................................................353 Bit Status During Initialization ....................................56 Return Address Stack ........................................................66 Reader Response ............................................................440 Return Stack Pointer (STKPTR) ........................................67 Register File .......................................................................74 Revision History ...............................................................425 Registers RLCF ...............................................................................353 ADCON0 (A/D Control 0) .........................................271 RLNCF .............................................................................354 ADCON1 (A/D Control 1) .........................................272 RRCF ...............................................................................354 ADCON2 (A/D Control 2) .........................................273 RRNCF ............................................................................355 BAUDCONx (Baud Rate Control) ............................250 S CCPxCON (CCPx Control, CCP4 and CCP5) .........179 CMCON (Comparator Control) ................................281 SCKx ................................................................................205 CONFIG1H (Configuration 1 High) ..........................299 SDIx .................................................................................205 CONFIG2H (Configuration 2 High) ..........................301 SDOx ...............................................................................205 CONFIG2L (Configuration 2 Low) ............................300 SEC_IDLE Mode ...............................................................46 CONFIG3H (Configuration 3 High) ..........................303 SEC_RUN Mode ................................................................42 CONFIG3L (Configuration 3 Low) ............................302 Serial Clock, SCKx ..........................................................205 CONFIG4L (Configuration 4 Low) ............................304 Serial Data In (SDIx) ........................................................205 CONFIG5H (Configuration 5 High) ..........................306 Serial Data Out (SDOx) ...................................................205 CONFIG5L (Configuration 5 Low) ............................305 Serial Peripheral Interface. See SPI Mode. CONFIG6H (Configuration 6 High) ..........................308 SETF ................................................................................355 CONFIG6L (Configuration 6 Low) ............................307 Single-Supply ICSP Programming. CONFIG7H (Configuration 7 High) ..........................310 Slave Select (SSx) ...........................................................205 CONFIG7L (Configuration 7 Low) ............................309 Slave Select Synchronization ..........................................211 DEVID1 (Device ID 1) ..............................................311 SLEEP .............................................................................356 DS39646C-page 436 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY Sleep Timer1 .............................................................................165 OSC1 and OSC2 Pin States ......................................40 16-Bit Read/Write Mode ..........................................167 Sleep Mode ........................................................................45 Associated Registers ...............................................169 Software Simulator (MPLAB SIM) ....................................372 Interrupt ...................................................................168 Special Event Trigger. See Compare (CCP Mode). Operation .................................................................166 Special Event Trigger. See Compare (ECCP Module). Oscillator ..........................................................165, 167 Special Features of the CPU ...........................................297 Layout Considerations .....................................168 Special Function Registers ................................................75 Overflow Interrupt ....................................................165 Map ............................................................................75 Resetting, Using the CCP SPI Mode (MSSP) ............................................................205 Special Event Trigger ......................................168 Associated Registers ...............................................214 Special Event Trigger (ECCP) .................................192 Bus Mode Compatibility ...........................................213 TMR1H Register ......................................................165 Clock Speed, Interactions ........................................213 TMR1L Register ......................................................165 Effects of a Reset .....................................................213 Use as a Real-Time Clock .......................................168 Enabling SPI I/O ......................................................209 Timer2 .............................................................................171 Master Mode ............................................................210 Associated Registers ...............................................172 Master/Slave Connection .........................................209 Interrupt ...................................................................172 Operation .................................................................208 Operation .................................................................171 Operation in Power-Managed Modes ......................213 Output ......................................................................172 Serial Clock ..............................................................205 PR2 Register ...................................................184, 192 Serial Data In ...........................................................205 TMR2 to PR2 Match Interrupt ..........................184, 192 Serial Data Out ........................................................205 Timer3 .............................................................................173 Slave Mode ..............................................................211 16-Bit Read/Write Mode ..........................................175 Slave Select .............................................................205 Associated Registers ...............................................175 Slave Select Synchronization ..................................211 Operation .................................................................174 SPI Clock .................................................................210 Oscillator ..........................................................173, 175 SSPxBUF Register ..................................................210 Overflow Interrupt ............................................173, 175 SSPxSR Register .....................................................210 Special Event Trigger (CCP) ...................................175 Typical Connection ..................................................209 TMR3H Register ......................................................173 SSPOV .............................................................................236 TMR3L Register ......................................................173 SSPOV Status Flag .........................................................236 Timer4 .............................................................................177 SSPxSTAT Register Associated Registers ...............................................178 R/W Bit .............................................................219, 220 MSSP Clock Shift ....................................................178 SSx ..................................................................................205 Operation .................................................................177 Stack Full/Underflow Resets ..............................................68 Postscaler. See Postscaler, Timer4. SUBFSR ..........................................................................367 PR4 Register ...........................................................177 SUBFWB ..........................................................................356 Prescaler. See Prescaler, Timer4. SUBLW ............................................................................357 TMR4 Register ........................................................177 SUBULNK ........................................................................367 TMR4 to PR4 Match Interrupt ..........................177, 178 SUBWF ............................................................................357 Timing Diagrams SUBWFB ..........................................................................358 A/D Conversion .......................................................416 SWAPF ............................................................................358 Asynchronous Reception .........................................261 Asynchronous Transmission ...................................258 T Asynchronous Transmission (Back to Back) ...........258 Table Pointer Operations (table) ........................................90 Automatic Baud Rate Calculation ............................256 Table Reads/Table Writes .................................................69 Auto-Wake-up Bit (WUE) During TBLRD .............................................................................359 Normal Operation ............................................262 TBLWT .............................................................................360 Auto-Wake-up Bit (WUE) During Sleep ...................262 Time-out in Various Situations (table) ................................53 Baud Rate Generator with Clock Arbitration ............233 Timer0 ..............................................................................161 BRG Overflow Sequence ........................................256 Associated Registers ...............................................163 BRG Reset Due to SDAx Arbitration Operation .................................................................162 During Start Condition .....................................242 Overflow Interrupt ....................................................163 Brown-out Reset (BOR) ...........................................403 Prescaler ..................................................................163 Bus Collision During a Repeated Start Prescaler Assignment (PSA Bit) ..............................163 Condition (Case 1) ...........................................243 Prescaler Select (T0PS2:T0PS0 Bits) .....................163 Bus Collision During a Repeated Start Prescaler. See Prescaler, Timer0. Condition (Case 2) ...........................................243 Reads and Writes in 16-Bit Mode ............................162 Bus Collision During a Start Source Edge Select (T0SE Bit) ................................162 Condition (SCLx = 0) .......................................242 Source Select (T0CS Bit) .........................................162 Bus Collision During a Stop Switching Prescaler Assignment ..............................163 Condition (Case 1) ...........................................244 Bus Collision During a Stop Condition (Case 2) ...........................................244 © 2008 Microchip Technology Inc. DS39646C-page 437

PIC18F8722 FAMILY Bus Collision During Start Reset, Watchdog Timer (WDT), Oscillator Start-up Condition (SDAx Only) .....................................241 Timer (OST) and Power-up Timer (PWRT) .....403 Bus Collision for Transmit and Acknowledge ...........240 Send Break Character Sequence ............................263 Capture/Compare/PWM (All ECCP/CCP Slave Synchronization .............................................211 Modules) ..........................................................405 Slow Rise Time (MCLR Tied to VDD, CLKO and I/O ..........................................................400 VDD Rise > TPWRT) ............................................55 Clock Synchronization .............................................226 SPI Mode (Master Mode) .........................................210 Clock/Instruction Cycle ..............................................69 SPI Mode (Slave Mode, CKE = 0) ...........................212 EUSART Synchronous Receive SPI Mode (Slave Mode, CKE = 1) ...........................212 (Master/Slave) ..................................................415 Synchronous Reception (Master Mode, SREN) ......266 EUSART Synchronous Transmission Synchronous Transmission .....................................264 (Master/Slave) ..................................................415 Synchronous Transmission (Through TXEN) ..........265 Example SPI Master Mode (CKE = 0) .....................407 Time-out Sequence on POR w/PLL Enabled Example SPI Master Mode (CKE = 1) .....................408 (MCLR Tied to VDD) ..........................................55 Example SPI Slave Mode (CKE = 0) .......................409 Time-out Sequence on Power-up Example SPI Slave Mode (CKE = 1) .......................410 (MCLR Not Tied to VDD, Case 1) ......................54 External Clock (All Modes Except PLL) ...................398 Time-out Sequence on Power-up External Memory Bus for Sleep (MCLR Not Tied to VDD, Case 2) ......................54 (Microprocessor Mode) ............................105, 108 Time-out Sequence on Power-up External Memory Bus for TBLRD (Extended (MCLR Tied to VDD, VDD Rise < TPWRT) ...........54 Microcontroller Mode) ..............................104, 107 Timer0 and Timer1 External Clock ..........................404 External Memory Bus for TBLRD Transition for Entry to Idle Mode ................................46 (Microprocessor Mode) ....................................107 Transition for Entry to SEC_RUN Mode ....................43 External Memory Bus for TBLRD with 1 TCY Transition for Entry to Sleep Mode ............................45 Wait State (Microprocessor Mode) ..................104 Transition for Two-Speed Start-up Fail-Safe Clock Monitor (FSCM) ..............................316 (INTOSC to HSPLL) ........................................314 First Start Bit Timing ................................................234 Transition for Wake from Idle to Run Mode ...............46 Full-Bridge PWM Output ..........................................197 Transition for Wake from Sleep (HSPLL) ..................45 Half-Bridge PWM Output .........................................196 Transition from RC_RUN Mode to High/Low-Voltage Detect Characteristics ................395 PRI_RUN Mode .................................................44 High-Voltage Detect Operation Transition from SEC_RUN Mode to (VDIRMAG = 1) ................................................294 PRI_RUN Mode (HSPLL) ..................................43 I2C Acknowledge Sequence ....................................239 Transition to RC_RUN Mode .....................................44 I2C Bus Data ............................................................411 Typical Opcode Fetch, 8-Bit Mode ..........................108 I2C Bus Start/Stop Bits .............................................411 Timing Diagrams and Specifications I2C Master Mode (7 or 10-Bit Transmission) ...........237 A/D Conversion Requirements ................................417 I2C Master Mode (7-Bit Reception) ..........................238 AC Characteristics I2C Slave Mode (10-Bit Reception, SEN = 0) ..........223 Internal RC Accuracy .......................................399 I2C Slave Mode (10-Bit Reception, SEN = 1) ..........228 Capture/Compare/PWM Requirements I2C Slave Mode (10-Bit Transmission) .....................224 (All ECCP/CCP Modules) ................................405 I2C Slave Mode (7-bit Reception, SEN = 0) .............221 CLKO and I/O Requirements ...........................400, 401 I2C Slave Mode (7-Bit Reception, SEN = 1) ............227 EUSART Synchronous Receive I2C Slave Mode (7-Bit Transmission) .......................222 Requirements ..................................................415 I2C Slave Mode General Call Address EUSART Synchronous Transmission Sequence (7 or 10-Bit Address Mode) .............229 Requirements ..................................................415 I2C Stop Condition Receive or Transmit Mode ........239 Example SPI Mode Requirements Low-Voltage Detect Operation (VDIRMAG = 0) .......293 (Master Mode, CKE = 0) ..................................407 Master SSP I2C Bus Data ........................................413 Example SPI Mode Requirements Master SSP I2C Bus Start/Stop Bits ........................413 (Master Mode, CKE = 1) ..................................408 Parallel Slave Port Example SPI Mode Requirements (PIC18F8527/8622/8627/8722) .......................406 (Slave Mode, CKE = 0) ....................................409 Parallel Slave Port (PSP) Read ...............................160 Example SPI Slave Mode Requirements Parallel Slave Port (PSP) Write ...............................160 (CKE = 1) .........................................................410 Program Memory Read ............................................401 External Clock Requirements ..................................398 Program Memory Write ............................................402 I2C Bus Data Requirements (Slave Mode) ..............412 PWM Auto-Shutdown (P1RSEN = 0, I2C Bus Start/Stop Bits Requirements Auto-Restart Disabled) .....................................202 (Slave Mode) ...................................................411 PWM Auto-Shutdown (P1RSEN = 1, Master SSP I2C Bus Data Requirements ................414 Auto-Restart Enabled) .....................................202 Master SSP I2C Bus Start/Stop Bits PWM Direction Change ...........................................199 Requirements ..................................................413 PWM Direction Change at Near Parallel Slave Port Requirements 100% Duty Cycle .............................................199 (PIC18F8527/8622/8627/8722) .......................406 PWM Output ............................................................184 PLL Clock ................................................................399 Repeated Start Condition .........................................235 Program Memory Write Requirements ....................402 DS39646C-page 438 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY Reset, Watchdog Timer, Oscillator Start-up W Timer, Power-up Timer and Brown-out Watchdog Timer (WDT) ...........................................297, 312 Reset Requirements ........................................403 Associated Registers ...............................................313 Timer0 and Timer1 External Clock Control Register .......................................................312 Requirements .................................................404 During Oscillator Failure ..........................................315 Top-of-Stack Access ..........................................................66 Programming Considerations ..................................312 TRISE Register WCOL ......................................................234, 235, 236, 239 PSPMODE Bit ..........................................................158 WCOL Status Flag ...................................234, 235, 236, 239 TSTFSZ ...........................................................................361 WWW Address ................................................................439 Two-Speed Start-up .................................................297, 314 WWW, On-Line Support ......................................................5 IESO (CONFIG1H, Internal/External Oscillator Switchover Bit ..................................299 X Two-Word Instructions XORLW ...........................................................................361 Example Cases ..........................................................71 XORWF ...........................................................................362 TXSTAx Register BRGH Bit .................................................................251 © 2008 Microchip Technology Inc. DS39646C-page 439

PIC18F8722 FAMILY NOTES: DS39646C-page 440 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following informa- • Field Application Engineer (FAE) tion: • Technical Support • Product Support – Data sheets and errata, appli- • Development Systems Information Line cation notes and sample programs, design Customers should contact their distributor, representa- resources, user’s guides and hardware support tive or field application engineer (FAE) for support. documents, latest software releases and archived Local sales offices are also available to help custom- software ers. A listing of sales offices and locations is included in • General Technical Support – Frequently Asked the back of this document. Questions (FAQ), technical support requests, online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Micro- chip sales offices, distributors and factory repre- sentatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notifi- cation and follow the registration instructions. © 2008 Microchip Technology Inc. DS39646C-page 441

PIC18F8722 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC18F8722 Family Literature Number: DS39646C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39646C-page 442 © 2008 Microchip Technology Inc.

PIC18F8722 FAMILY PIC18F8722 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC18LF6622-I/PT 301 = Industrial temp., Range TQFP package, Extended VDD limits, QTP pattern #301. b) PIC18LF6722-E/PT = Extended temp., Device PIC18F6527/6622/6627/6722(1), PIC18F8527/8622/8627/8722(1), TQFP package, standard VDD limits. PIC18F6527/6622/6627/6722T(2), PIC18F8527/8622/8627/8722T(2); VDD range 4.2V to 5.5V PIC18LF6627/6722(1), PIC18LF8627/8722(1), PIC18LF6627/6722T(2), PIC18LF8627/8722T(2); VDD range 2.0V to 5.5V Temperature I = -40°C to +85°C (Industrial) Range E = -40°C to +125°C (Extended) Package PT = TQFP (Thin Quad Flatpack) Note1: F = Standard Voltage Range LF = Wide Voltage Range 2: T = in tape and reel TQFP Pattern QTP, SQTP, Code or Special Requirements packages only. (blank otherwise) © 2008 Microchip Technology Inc. DS39646C-page 443

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC18F6722-I/PT PIC18F6527-I/PT PIC18F6527T-I/PT PIC18F6622-I/PT PIC18F6622T-I/PT PIC18F6627-E/PT PIC18F6627-I/PT PIC18F6627T-E/PT PIC18F6627T-I/PT PIC18F6722-E/PT PIC18F6722T-E/PT PIC18F6722T-I/PT PIC18F8527-I/PT PIC18F8527T-I/PT PIC18F8622-I/PT PIC18F8622T-I/PT PIC18F8627-E/PT PIC18F8627-I/PT PIC18F8627T-E/PT PIC18F8627T-I/PT PIC18F8722-E/PT PIC18F8722-I/PT PIC18F8722T-E/PT PIC18F8722T-I/PT PIC18LF6527-I/PT PIC18LF6527T-I/PT PIC18LF6622-I/PT PIC18LF6622T-I/PT PIC18LF6627-I/PT PIC18LF6627T-I/PT PIC18LF6722-I/PT PIC18LF6722T-I/PT PIC18LF8527-I/PT PIC18LF8527T-I/PT PIC18LF8622- I/PT PIC18LF8622T-I/PT PIC18LF8627-I/PT PIC18LF8627T-I/PT PIC18LF8722-I/PT PIC18LF8722T-I/PT PIC18F6622-E/PT PIC18F8622-E/PT