PIC18F6310/6410/8310/8410 Data Sheet 64/80-Pin Flash Microcontrollers with nanoWatt XLP Technology  2010 Microchip Technology Inc. DS39635C

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Omniscient Code conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-582-4 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39635C-page 2  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 64/80-Pin Flash Microcontrollers with nanoWatt Technology Power-Managed Modes: Peripheral Highlights (Continued): • Run: CPU on, Peripherals on • Master Synchronous Serial Port (MSSP) module • Idle: CPU off, Peripherals on Supporting 3-Wire SPI (all 4 modes) and I2C™ • Sleep: CPU off, Peripherals off Master and Slave modes • Ultra Low 50 nA Input Leakage • Addressable USART module: • Idle mode Currents Down to 2.3A Typical - Supports RS-485 and RS-232 • Ultra Low 50 nA Input Leakage • Enhanced Addressable USART module: • Sleep mode Currents Down to 0.1A Typical - Supports RS-485, RS-232 and LIN/J2602 • Timer1 Oscillator: 1.0A, 32kHz, 2V Typical - Auto-Wake-up on Start bit • Watchdog Timer: 1.7A Typical - Auto-Baud Detect • Two-Speed Oscillator Start-up • 10-Bit, up to 12-Channel Analog-to-Digital (A/D) Converter module: Flexible Oscillator Structure: - Auto-acquisition capability • Four Crystal modes up to 40 MHz - Conversion available during Sleep • 4x Phase Lock Loop (available for crystal and • Dual Analog Comparators with Input Multiplexing internal oscillators) • Programmable 16-Level High/Low-Voltage • Two External RC modes, up to 4 MHz Detection (HLVD) module: • Two External Clock modes, up to 40 MHz - Supports interrupt on High/Low-Voltage Detection • Internal Oscillator Block: Special Microcontroller Features: - Fast wake from Sleep and Idle, 1 s typical - 8 user-selectable frequencies, from 31kHz to • C Compiler Optimized Architecture: 8MHz - Optional extended instruction set designed to - Provides a complete range of clock speeds, optimize re-entrant code from 31kHz to 32MHz, when used with PLL • 1000 Erase/Write Cycle Flash Program Memory - User-tunable to compensate for frequency drift Typical • Secondary Oscillator using Timer1 @ 32 kHz • Flash Retention: 100 Years Typical • Fail-Safe Clock Monitor: • Priority Levels for Interrupts - Allows for safe shutdown if peripheral clock stops • 8 x 8 Single-Cycle Hardware Multiplier • Extended Watchdog Timer (WDT): External Memory Interface - Programmable period from 4ms to 131s (PIC18F8310/8410 Devices only): - 2% stability over VDD and temperature • In-Circuit Serial Programming™ (ICSP™) via • Address Capability of up to 2 Mbytes Two Pins • 16-Bit/8-Bit Interface • In-Circuit Debug (ICD) via Two Pins Peripheral Highlights: • Wide Operating Voltage Range: 2.0V to 5.5V • Programmable Brown-out Reset (BOR) with • High-Current Sink/Source 25mA/25mA Software Enable Option • Four External Interrupts • Four Input Change Interrupts • Four 8-Bit/16-Bit Timer/Counter modules • Up to 3 Capture/Compare/PWM (CCP) modules Program Memory Data s Device (Fb(lyOatsenhs-B)oa#rI dnS/siEntrxgutleecr-tWnioanol)srd M (SbeyRmtAeosMr)y I/O A1/D0- B(ciht) (PCWCPM) SPIMSSMIP2aCs™ter EUSART/AUSART omparator 8T/i1m6e-Brsit BExuts. C PIC18F6310 8K/0 4096/0 768 54 12 3 Y Y 1/1 2 1/3 N PIC18F6410 16K/0 8192/0 768 54 12 3 Y Y 1/1 2 1/3 N PIC18F8310 8K/2M 4096/1M 768 70 12 3 Y Y 1/1 2 1/3 Y PIC18F8410 16K/2M 8192/1M 768 70 12 3 Y Y 1/1 2 1/3 Y  2010 Microchip Technology Inc. DS39635C-page 3

PIC18F6310/6410/8310/8410 Pin Diagrams 64-Pin TQFP 1) (2 0 1 2 3 4 5 6 7 P P P P P P P P P S C S S S S S S S S C C P P P P P P P P E2/ E3 E4 E5 E6 E7/ D0/ DD SS D1/ D2/ D3/ D4/ D5/ D6/ D7/ R R R R R R R V V R R R R R R R 64636261 60 59 58 57 56 55 54 535251 50 49 RE1/WR 1 48 RB0/INT0 RE0/RD 2 47 RB1/INT1 RG0/CCP3 3 46 RB2/INT2 RG1/TX2/CK2 4 45 RB3/INT3 RG2/RX2/DT2 5 44 RB4/KBI0 RG3 6 43 RB5/KBI1 RG5/MCLR/VPP 7 PIC18F6310 42 RB6/KBI2/PGC RG4 8 PIC18F6410 41 VSS VSS 9 40 OSC2/CLKO/RA6 VDD 10 39 OSC1/CLKI/RA7 RF7/SS 11 38 VDD RF6/AN11 12 37 RB7/KBI3/PGD RF5/AN10/CVREF 13 36 RC5/SDO RF4/AN9 14 35 RC4/SDI/SDA RF3/AN8 15 34 RC3/SCK/SCL RF2/AN7/C1OUT 16 33 RC2/CCP1 17 18 1920 21 22 23 24 25 26 27 28 29 30 31 32 RF1/AN6/C2OUT RF0/AN5 AVDD AVSS RA3/AN3/V+REF RA2/AN2/V-REF RA1/AN1 RA0/AN0 VSS VDD RA5/AN4/HLVDIN RA4/T0CKI(1)1/T1OSI/CCP2 0/T1OSO/T13CKI RC6/TX1/CK1 RC7/RX1/DT1 C C R R Note 1: RE7 is the alternate pin for CCP2 multiplexing. DS39635C-page 4  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 Pin Diagrams (Continued) 80-Pin TQFP 5 1 D A17 A16 AD10/CS AD11 AD12 AD13 AD14(1)CCP2/A AD0/PSP0 AD1/PSP1 AD2/PSP2 AD3/PSP3 AD4/PSP4 AD5/PSP5 AD6/PSP6 AD7/PSP7 ALE OE H1/ H0/ E2/ E3/ E4/ E5/ E6/ E7/ D0/ DD SS D1/ D2/ D3/ D4/ D5/ D6/ D7/ J0/ J1/ R R R R R R R R R V V R R R R R R R R R 8079787776 75 74 73 72 71 70 69 68676665 64 63 62 61 RH2/A18 1 60 RJ2/WRL RH3/A19 2 59 RJ3/WRH RE1/AD9/WR 3 58 RB0/INT0 RE0/AD8/RD 4 57 RB1/INT1 RG0/CCP3 5 56 RB2/INT2 RG1/TX2/CK2 6 55 RB3/INT3/CCP2(1) RG2/RX2/DT2 7 54 RB4/KBI0 RG3 8 53 RB5/KBI1 RG5/MCLR/VPP 9 PIC18F8310 52 RB6/KBI2/PGC RG4 10 51 VSS VSS 11 PIC18F8410 50 OSC2/CLKO/RA6 VDD 12 49 OSC1/CLKI/RA7 RF7/SS 13 48 VDD RF6/AN11 14 47 RB7/KBI3/PGD RF5/AN10/CVREF 15 46 RC5/SDO RF4/AN9 16 45 RC4/SDI/SDA RF3/AN8 17 44 RC3/SCK/SCL RF2/AN7/C1OUT 18 43 RC2/CCP1 RH7 19 42 RJ7/UB RH6 20 41 RJ6/LB 21 2223 24 25 26 27 28 2930 31 32 33 34 3536 37 38 3940 RH5 RH4 RF1/AN6/C2OUT RF0/AN5 AVDD AVSS RA3/AN3/V+REF RA2/AN2/V-REF RA1/AN1 RA0/AN0 VSS VDD RA5/AN4/HLVDIN RA4/T0CKI(1)C1/T1OSI/CCP2 C0/T1OSO/T13CKI RC6/TX1/CK1 RC7/RX1/DT1 RJ4/BA0 RJ5/CE R R Note 1: RE7 is the alternate pin for CCP2 multiplexing.  2010 Microchip Technology Inc. DS39635C-page 5

PIC18F6310/6410/8310/8410 Table of Contents 1.0 Device Overview..........................................................................................................................................................................9 2.0 Guidelines for Getting Started with PIC18F Microcontrollers.....................................................................................................31 3.0 Oscillator Configurations............................................................................................................................................................35 4.0 Power-Managed Modes.............................................................................................................................................................45 5.0 Reset..........................................................................................................................................................................................55 6.0 Memory Organization.................................................................................................................................................................67 7.0 Program Memory........................................................................................................................................................................89 8.0 External Memory Interface.........................................................................................................................................................95 9.0 8 x 8 Hardware Multiplier..........................................................................................................................................................107 10.0 Interrupts..................................................................................................................................................................................109 11.0 I/O Ports...................................................................................................................................................................................125 12.0 Timer0 Module.........................................................................................................................................................................151 13.0 Timer1 Module.........................................................................................................................................................................155 14.0 Timer2 Module.........................................................................................................................................................................161 15.0 Timer3 Module.........................................................................................................................................................................163 16.0 Capture/Compare/PWM (CCP) Modules.................................................................................................................................167 17.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................177 18.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)...............................................................217 19.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART)...........................................................241 20.0 10-Bit Analog-to-Digital Converter (A/D) Module.....................................................................................................................255 21.0 Comparator Module..................................................................................................................................................................265 22.0 Comparator Voltage Reference Module...................................................................................................................................271 23.0 High/Low-Voltage Detect (HLVD).............................................................................................................................................275 24.0 Special Features of the CPU....................................................................................................................................................281 25.0 Instruction Set Summary..........................................................................................................................................................297 26.0 Development Support...............................................................................................................................................................347 27.0 Electrical Characteristics..........................................................................................................................................................351 28.0 Packaging Information..............................................................................................................................................................389 Appendix A: Revision History.............................................................................................................................................................395 Appendix B: Device Differences.........................................................................................................................................................395 Appendix C: Conversion Considerations...........................................................................................................................................396 Appendix D: Migration from Baseline to Enhanced Devices..............................................................................................................396 Appendix E: Migration from Mid-Range to Enhanced Devices..........................................................................................................397 Appendix F: Migration from High-End to Enhanced Devices.............................................................................................................397 Index..................................................................................................................................................................................................399 The Microchip Web Site.....................................................................................................................................................................409 Customer Change Notification Service..............................................................................................................................................409 Customer Support..............................................................................................................................................................................409 Reader Response..............................................................................................................................................................................410 PIC18F6310/6410/8310/8410 Product Identification System............................................................................................................411 DS39635C-page 6  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) • The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.  2010 Microchip Technology Inc. DS39635C-page 7

PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 8  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 1.0 DEVICE OVERVIEW 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES This document contains device specific information for the following devices: All of the devices in the PIC18F6310/6410/8310/8410 family offer nine different oscillator options, allowing • PIC18F6310 • PIC18LF6310 users a wide range of choices in developing application • PIC18F6410 • PIC18LF6410 hardware. These include: • PIC18F8310 • PIC18LF8310 • Four Crystal modes, using crystals or ceramic resonators. • PIC18F8410 • PIC18LF8410 • Two External Clock modes, offering the option of This family offers the advantages of all PIC18 using two pins (oscillator input and a divide-by-4 microcontrollers – namely, high computational clock output) or one pin (oscillator input, with the performance at an economical price. In addition to second pin reassigned as general I/O). these features, the PIC18F6310/6410/8310/8410 • Two External RC Oscillator modes, with the same family introduces design enhancements that make pin options as the External Clock modes. these microcontrollers a logical choice for many • An internal oscillator block which provides an high-performance, power-sensitive applications. 8MHz clock (±2% accuracy) and an INTRC source (approximately 31kHz, stable over 1.1 New Core Features temperature and VDD), as well as a range of sixuser-selectable clock frequencies between 1.1.1 nanoWatt TECHNOLOGY 125kHz to 4MHz for a total of eight clock All of the devices in the PIC18F6310/6410/8310/8410 frequencies. This option frees the two oscillator family incorporate a range of features that can pins for use as additional general purpose I/O. significantly reduce power consumption during • A Phase Lock Loop (PLL) frequency multiplier, operation. Key items include: available to both the High-Speed Crystal and • Alternate Run Modes: By clocking the controller Internal Oscillator modes, which allows clock from the Timer1 source or the internal oscillator speeds of up to 40MHz. Used with the internal block, power consumption during code execution oscillator, the PLL gives users a complete can be reduced by as much as 90%. selection of clock speeds from 31kHz to 32MHz • Multiple Idle Modes: The controller can also run – all without using an external crystal or clock with its CPU core disabled, but the peripherals still circuit. active. In these states, power consumption can be Besides its availability as a clock source, the internal reduced even further – to as little as 4% of normal oscillator block provides a stable reference source that operation requirements. gives the family additional features for robust • On-the-Fly Mode Switching: The operation: power-managed modes are invoked by user code • Fail-Safe Clock Monitor: This option constantly during operation, allowing the user to incorporate monitors the main clock source against a power-saving ideas into their application’s reference signal provided by the internal software design. oscillator. If a clock failure occurs, the controller is • Lower Consumption in Key Modules: The switched to the internal oscillator block, allowing power requirements for both Timer1 and the for continued low-speed operation or a safe Watchdog Timer have been reduced by up to application shutdown. 80%, with typical values of 1.1 A and 2.1A, • Two-Speed Start-up: This option allows the respectively. internal oscillator to serve as the clock source from Power-on Reset or wake-up from Sleep mode until the primary clock source is available.  2010 Microchip Technology Inc. DS39635C-page 9

PIC18F6310/6410/8310/8410 1.2 Other Special Features 1.3 Details on Individual Family Members • Memory Endurance: The Flash cells for program memory are rated to last for approximately a Devices in the PIC18F6310/6410/8310/8410 family are thousand erase/write cycles. Data retention available in 64-pin (PIC18F6310/8310) and 80-pin without refresh is conservatively estimated to be (PIC18F6410/8410) packages. Block diagrams for the greater than 100 years. two groups are shown in Figure1-1 and Figure1-2, • External Memory Interface: For those respectively. applications where more program or data storage The devices are differentiated from each other in three is needed, the PIC18F8310/8410 devices provide ways: the ability to access external memory devices. The memory interface is configurable for both 1. Flash Program Memory: 8 Kbytes in PIC18FX310 8-bit and 16-bit data widths and uses a standard devices, 16Kbytes in PIC18FX410 devices. range of control signals to enable communication 2. I/O Ports: 7 bidirectional ports on 64-pin with a wide range of memory devices. With their devices, 9 bidirectional ports on 80-pin devices. 21-bit program counters, the 80-pin devices can 3. External Memory Interface: present on 80-pin access a linear memory space of up to 2Mbytes. devices only. • Extended Instruction Set: The All other features for devices in this family are identical. PIC18F6310/6410/8310/8410 family introduces These are summarized in Table1-1. an optional extension to the PIC18 instruction set, The pinouts for all devices are listed in Table1-2 and which adds 8 new instructions and an Indexed Table1-3. Addressing mode. This extension, enabled as a device configuration option, has been specifically Like all Microchip PIC18 devices, members of the designed to optimize re-entrant application code PIC18F6310/6410/8310/8410 family are available as originally developed in high-level languages such both standard and low-voltage devices. Standard as ‘C’. devices with Flash memory, designated with an “F” in • Enhanced Addressable USART: This serial the part number (such as PIC18F6310), accommodate communication module is capable of standard an operating VDD range of 4.2V to 5.5V. Low-voltage RS-232 operation and provides support for the parts, designated by “LF” (such as PIC18LF6410), LIN/J2602 bus protocol. Other enhancements function over an extended VDD range of 2.0V to 5.5V. include Automatic Baud Rate Detection (ABD) and a 16-bit Baud Rate Generator for improved resolution. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world, without using an external crystal (or its accompanying power requirement). • 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, and thus, reduces code overhead. • Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing a time-out range from 4ms to over 2 minutes that is stable across operating voltage and temperature. DS39635C-page 10  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 1-1: DEVICE FEATURES Features PIC18F6310 PIC18F6410 PIC18F8310 PIC18F8410 Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz Program Memory (Bytes) 8K 16K 8K 16K Program Memory (Instructions) 4096 8192 4096 8192 Data Memory (Bytes) 768 768 768 768 External Memory Interface No No Yes Yes Interrupt Sources 22 22 22 22 I/O Ports Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, F, G F, G F, G, H, J F, G, H, J Timers 4 4 4 4 Capture/Compare/PWM Modules 3 3 3 3 Serial Communications MSSP, AUSART MSSP, AUSART MSSP, AUSART MSSP, AUSART Enhanced USART Enhanced USART Enhanced USART Enhanced USART Parallel Communications PSP PSP PSP PSP 10-Bit Analog-to-Digital Module 12 Input Channels 12 Input Channels 12 Input Channels 12 Input Channels Resets (and Delays) POR, BOR, POR, BOR, POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction, Stack Full, Stack Full, Stack Full, Stack Full, Stack Underflow Stack Underflow Stack Underflow Stack Underflow (PWRT, OST), (PWRT, OST), (PWRT, OST), (PWRT, OST), MCLR (optional), MCLR (optional), MCLR (optional), MCLR (optional), WDT WDT WDT WDT Programmable Low-Voltage Detect Yes Yes Yes Yes Programmable Brown-out Reset Yes Yes Yes Yes Instruction Set 75 Instructions; 75 Instructions; 75 Instructions; 75 Instructions; 83 with Extended 83 with Extended 83 with Extended 83 with Extended Instruction Set Instruction Set Instruction Set Instruction Set enabled enabled enabled enabled Packages 64-Pin TQFP 64-Pin TQFP 80-Pin TQFP 80-Pin TQFP  2010 Microchip Technology Inc. DS39635C-page 11

PIC18F6310/6410/8310/8410 FIGURE 1-1: PIC18F6310/6410 (64-PIN) BLOCK DIAGRAM Data Bus<8> PORTA Table Pointer<21> RA0/AN0 RA1/AN1 inc/dec logic 8 8 Data Latch RA2/AN2/VREF- RA3/AN3/VREF+ Data Memory RA4/T0CKI 21 PCLAT U PCLATH (8/16Kbytes) RA5/AN4/HLVDIN 20 Address Latch OSC2/CLKO(3)/RA6 PCU PCH PCL OSC1/CLKI(3)/RA7 Program Counter 12 PORTB Data Address<12> RB0/INT0 RB1/INT1 31 Level Stack RB2/INT2 Address Latch 4 12 4 RB3/INT3 Program Memory STKPTR BSR FSR0 ABcacensks RB4/KBI0 8/16Kbytes) FSR1 RB5/KBI1 Data Latch FSR2 12 RRBB67//KKBBII23//PPGGCD inc/dec PORTC 8 logic Table Latch RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1) RC2/CCP1 ROM Latch Address RC3/SCK/SCL Instruction Bus <16> Decode RC4/SDI/SDA RC5/SDO IR RC6/TX1/CK1 RC7/RX1/DT1 8 PORTD Instruction State Machine Decode and Control Signals Control RD7/PSP7:RD0/PSP0 PRODH PRODL 8 x 8 Multiply 3 8 PORTE RE0/RD BITOP W RE1/WR 8 8 8 RE2/CS RE3 OSC1(3) OInsBtcleoilrlcnakatolr PoTwimere-rup 8 8 RREE45 OSC2(3) Oscillator ALU<8> RE6 INTRC Start-up Timer RE7/CCP2(1) T1OSI Oscillator PoRweesre-otn 8 PORTF 8 MHz RF0/AN5 T1OSO Oscillator Watchdog RF1/AN6/C2OUT Timer Precision RF2/AN7/C1OUT MCLR(2) Single-Supply Brown-out Band Gap RF3/AN8 Programming Reset Reference RF4/AN9 VDD,VSS DIne-bCuirgcgueitr CloFcakil -MSoanfeitor RRFF56//AANN1110/CVREF RF7/SS BOR ADC HLVD 10-Bit Timer0 Timer1 Timer2 Timer3 PORTG RG0/CCP3 RG1/TX2/CK2 RG2/RX2/DT2 RG3 RG4 RG5(2)/MCLR/VPP Comparators CCP1 CCP2 CCP3 MSSP EUSART1 AUSART2 Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set or RE7 when CCP2MX is not set. 2: RG5 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section3.0 “Oscillator Configurations” for additional information. DS39635C-page 12  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 1-2: PIC18F8310/8410 (80-PIN) BLOCK DIAGRAM PORTA RA0/AN0 Data Bus<8> RA1/AN1 RA2/AN2/VREF- Table Pointer<21> 8 8 Data Latch RRAA43//TA0NC3K/VIREF+ Data Memory RA5/AN4/HLVDIN inc/dec logic PCLAT U PCLATH (8/16Kbytes) OOSSCC21//CCLLKKOI(3()3/)R/RAA76 21 20 Address Latch PORTB PCU PCH PCL RB0/INT0 Program Counter 12 RB1/INT1 Data Address<12> RB2/INT2 RB3/INT3/CCP2(1) 31 Level Stack RB4/KBI0 e Address Latch 4 12 4 RB5/KBI1 nterfac Pr(o8g/1ra6mK Mbyetemso)ry STKPTR BSR FFSSRR01 ABcacensks RRBB67//KKBBII23//PPGGCD Bus I Data Latch FSR2 12 PORTC RC0/T1OSO/T13CKI m RC1/T1OSI/CCP2(1) ste 8 inloc/gdiecc RC2/CCP1 Sy TABLE LATCH RC3/SCK/SCL RC4/SDI/SDA RC5/SDO Address ROM LATCH RC6/TX1/CK1 Decode Instruction Bus <16> RC7/RX1/DT1 PORTD IR AD<15:0>, A<19:16> RD7/AD7/PSP7: (Multiplexed with PORTD, 8 RD0/AD0/PSP0 PORTE and PORTH) PORTE RE0/AD8/RD PRODH PRODL State Machine Instruction RE1/AD9/WR Control Signals Decode & RE2/AD10/CS Control 8 x 8 Multiply 3 8 RE3/AD11 RE4/AD12 BITOP W RE5/AD13 8 8 8 RE6/AD14 RE7/CCP2(1)/AD15 OSC1(3) OInstceilrlanatolr PoTwimere-rup 8 8 PORTF RF0/AN5 Block OSC2(3) Oscillator ALU<8> RF1/AN6/C2OUT INTRC Start-up Timer RF2/AN7/C1OUT T1OSI Oscillator Power-on 8 RF3/AN8 Reset RF4/AN9 T1OSO O8s cMillHatzor WaTticmhedrog RRFF56//AANN1110/CVREF Precision RF7/SS MCLR(2) Single-Supply Brown-out Band Gap PORTG Programming Reset Reference RG0/CCP3 VDD,VSS DIne-bCuirgcgueitr CloFcakil -MSoanfeitor RRGG12//TRXX22//CDKT22 RG3 RG4 RG5(2)/MCLR/VPP PORTH RH3/AD19:RH0/AD16 BOR ADC HLVD 10-Bit Timer0 Timer1 Timer2 Timer3 RH<7:4> PORTJ RJ0/ALE RJ1/OE RJ2/WRL RJ3/WRH Comparators CCP1 CCP2 CCP3 MSSP EUSART1 AUSART2 RJ4/BA0 RJ5/CE RJ6/LB RJ7/UB Note 1: CCP2 multiplexing is determined by the settings of the CCP2MX and PM<1:0> Configuration bits. 2: RG5 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section3.0 “Oscillator Configurations” for additional information.  2010 Microchip Technology Inc. DS39635C-page 13

PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type TQFP RG5/MCLR/VPP 7 Master Clear (input) or programming voltage (input). RG5 I ST Digital input. MCLR I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. VPP P Programming voltage input. OSC1/CLKI/RA7 39 Oscillator crystal or external clock input. OSC1 I ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode, CMOS otherwise. CLKI I CMOS External clock source input. Always associated with pin function, OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) RA7 I/O TTL General purpose I/O pin. OSC2/CLKO/RA6 40 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2C = ST with I2C™ or SMB levels Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39635C-page 14  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTA is a bidirectional I/O port. RA0/AN0 24 RA0 I/O TTL Digital I/O. AN0 I Analog Analog Input 0. RA1/AN1 23 RA1 I/O TTL Digital I/O. AN1 I Analog Analog Input 1. RA2/AN2/VREF- 22 RA2 I/O TTL Digital I/O. AN2 I Analog Analog Input 2. VREF- I Analog A/D reference voltage (low) input. RA3/AN3/VREF+ 21 RA3 I/O TTL Digital I/O. AN3 I Analog Analog Input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI 28 RA4 I/O ST Digital I/O. T0CKI I ST Timer0 external clock input. RA5/AN4/HLVDIN 27 RA5 I/O TTL Digital I/O. AN4 I Analog Analog Input 4. HLVDIN I Analog High/Low-Voltage Detect input. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2C = ST with I2C™ or SMB levels Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.  2010 Microchip Technology Inc. DS39635C-page 15

PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0 48 RB0 I/O TTL Digital I/O. INT0 I ST External Interrupt 0. RB1/INT1 47 RB1 I/O TTL Digital I/O. INT1 I ST External Interrupt 1. RB2/INT2 46 RB2 I/O TTL Digital I/O. INT2 I ST External Interrupt 2. RB3/INT3 45 RB3 I/O TTL Digital I/O. INT3 I ST External Interrupt 3. RB4/KBI0 44 RB4 I/O TTL Digital I/O. KBI0 I TTL Interrupt-on-change pin. RB5/KBI1 43 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. RB6/KBI2/PGC 42 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin. RB7/KBI3/PGD 37 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2C = ST with I2C™ or SMB levels Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39635C-page 16  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 30 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/CCP2 29 RC1 I/O ST Digital I/O. T1OSI I Analog Timer1 oscillator input. CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM2 output. RC2/CCP1 33 RC2 I/O ST Digital I/O. CCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. RC3/SCK/SCL 34 RC3 I/O ST Digital I/O. SCK I/O ST Synchronous serial clock input/output for SPI mode. SCL I/O I2C Synchronous serial clock input/output for I2C mode. RC4/SDI/SDA 35 RC4 I/O ST Digital I/O. SDI I ST SPI data in. SDA I/O I2C I2C data I/O. RC5/SDO 36 RC5 I/O ST Digital I/O. SDO O — SPI data out. RC6/TX1/CK1 31 RC6 I/O ST Digital I/O. TX1 O — EUSART1 asynchronous transmit. CK1 I/O ST EUSART1 synchronous clock (see related RX1/DT1). RC7/RX1/DT1 32 RC7 I/O ST Digital I/O. RX1 I ST EUSART1 asynchronous receive. DT1 I/O ST EUSART1 synchronous data (see related TX1/CK1). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2C = ST with I2C™ or SMB levels Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.  2010 Microchip Technology Inc. DS39635C-page 17

PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTD is a bidirectional I/O port. RD0/PSP0 58 RD0 I/O ST Digital I/O. PSP0 I/O TTL Parallel Slave Port data. RD1/PSP1 55 RD1 I/O ST Digital I/O. PSP1 I/O TTL Parallel Slave Port data. RD2/PSP2 54 RD2 I/O ST Digital I/O. PSP2 I/O TTL Parallel Slave Port data. RD3/PSP3 53 RD3 I/O ST Digital I/O. PSP3 I/O TTL Parallel Slave Port data. RD4/PSP4 52 RD4 I/O ST Digital I/O. PSP4 I/O TTL Parallel Slave Port data. RD5/PSP5 51 RD5 I/O ST Digital I/O. PSP5 I/O TTL Parallel Slave Port data. RD6/PSP6 50 RD6 I/O ST Digital I/O. PSP6 I/O TTL Parallel Slave Port data. RD7/PSP7 49 RD7 I/O ST Digital I/O. PSP7 I/O TTL Parallel Slave Port data. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2C = ST with I2C™ or SMB levels Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39635C-page 18  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTE is a bidirectional I/O port. RE0/RD 2 RE0 I/O ST Digital I/O. RD I TTL Read control for Parallel Slave Port. RE1/WR 1 RE1 I/O ST Digital I/O. WR I TTL Write control for Parallel Slave Port. RE2/CS 64 RE2 I/O ST Digital I/O. CS I TTL Chip select control for Parallel Slave Port. RE3 63 I/O ST Digital I/O. RE4 62 I/O ST Digital I/O. RE5 61 I/O ST Digital I/O. RE6 60 I/O ST Digital I/O. RE7/CCP2 59 RE7 I/O ST Digital I/O. CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM2 output. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2C = ST with I2C™ or SMB levels Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.  2010 Microchip Technology Inc. DS39635C-page 19

PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTF is a bidirectional I/O port. RF0/AN5 18 RF0 I/O ST Digital I/O. AN5 I Analog Analog Input 5. RF1/AN6/C2OUT 17 RF1 I/O ST Digital I/O. AN6 I Analog Analog Input 6. C2OUT O — Comparator 2 output. RF2/AN7/C1OUT 16 RF2 I/O ST Digital I/O. AN7 I Analog Analog Input 7. C1OUT O — Comparator 1 output. RF3/AN8 15 RF3 I/O ST Digital I/O. AN8 I Analog Analog Input 8. RF4/AN9 14 RF4 I/O ST Digital I/O. AN9 I Analog Analog Input 9. RF5/AN10/CVREF 13 RF5 I/O ST Digital I/O. AN10 I Analog Analog Input 10. CVREF O Analog Comparator reference voltage output. RF6/AN11 12 RF6 I/O ST Digital I/O. AN11 I Analog Analog Input 11. RF7/SS 11 RF7 I/O ST Digital I/O. SS I TTL SPI slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2C = ST with I2C™ or SMB levels Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39635C-page 20  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 1-2: PIC18F6310/6410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTG is a bidirectional I/O port. RG0/CCP3 3 RG0 I/O ST Digital I/O. CCP3 I/O ST Capture 3 input/Compare 3 output/PWM3 output. RG1/TX2/CK2 4 RG1 I/O ST Digital I/O. TX2 O — AUSART2 asynchronous transmit. CK2 I/O ST AUSART2 synchronous clock (see related RX2/DT2). RG2/RX2/DT2 5 RG2 I/O ST Digital I/O. RX2 I ST AUSART2 asynchronous receive. DT2 I/O ST AUSART2 synchronous data (see related TX2/CK2). RG3 6 I/O ST Digital I/O. RG4 8 I/O ST Digital I/O. RG5 See RG5/MCLR/VPP pin. VSS 9, 25, 41, 56 P — Ground reference for logic and I/O pins. VDD 10, 26, 38, 57 P — Positive supply for logic and I/O pins. AVSS 20 P — Ground reference for analog modules. AVDD 19 P — Positive supply for analog modules. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2C = ST with I2C™ or SMB levels Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.  2010 Microchip Technology Inc. DS39635C-page 21

PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description Type Type TQFP RG5/MCLR/VPP 9 Master Clear (input) or programming voltage (input). RG5 I ST Digital input. MCLR I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. VPP P Programming voltage input. OSC1/CLKI/RA7 49 Oscillator crystal or external clock input. OSC1 I ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode, CMOS otherwise. CLKI I CMOS External clock source input. Always associated with pin function, OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) RA7 I/O TTL General purpose I/O pin. OSC2/CLKO/RA6 50 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RA6 I/O TTL General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2C = ST with I2C™ or SMB levels Note 1: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Microcontroller mode). 2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only). DS39635C-page 22  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTA is a bidirectional I/O port. RA0/AN0 30 RA0 I/O TTL Digital I/O. AN0 I Analog Analog Input 0. RA1/AN1 29 RA1 I/O TTL Digital I/O. AN1 I Analog Analog Input 1. RA2/AN2/VREF- 28 RA2 I/O TTL Digital I/O. AN2 I Analog Analog Input 2. VREF- I Analog A/D reference voltage (low) input. RA3/AN3/VREF+ 27 RA3 I/O TTL Digital I/O. AN3 I Analog Analog Input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/T0CKI 34 RA4 I/O ST Digital I/O. T0CKI I ST Timer0 external clock input. RA5/AN4/HLVDIN 33 RA5 I/O TTL Digital I/O. AN4 I Analog Analog Input 4. HLVDIN I Analog High/Low-Voltage Detect input. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2C = ST with I2C™ or SMB levels Note 1: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Microcontroller mode). 2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only).  2010 Microchip Technology Inc. DS39635C-page 23

PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0 58 RB0 I/O TTL Digital I/O. INT0 I ST External Interrupt 0. RB1/INT1 57 RB1 I/O TTL Digital I/O. INT1 I ST External Interrupt 1. RB2/INT2 56 RB2 I/O TTL Digital I/O. INT2 I ST External Interrupt 2. RB3/INT3/CCP2 55 RB3 I/O TTL Digital I/O. INT3 I ST External Interrupt 3. CCP2(1) O Analog Capture 2 input/Compare 2 output/PWM2 output. RB4/KBI0 54 RB4 I/O TTL Digital I/O. KBI0 I TTL Interrupt-on-change pin. RB5/KBI1 53 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. RB6/KBI2/PGC 52 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin. RB7/KBI3/PGD 47 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2C = ST with I2C™ or SMB levels Note 1: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Microcontroller mode). 2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only). DS39635C-page 24  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI 36 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T13CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/CCP2 35 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM2 output. RC2/CCP1 43 RC2 I/O ST Digital I/O. CCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. RC3/SCK/SCL 44 RC3 I/O ST Digital I/O. SCK I/O ST Synchronous serial clock input/output for SPI mode. SCL I/O I2C Synchronous serial clock input/output for I2C mode. RC4/SDI/SDA 45 RC4 I/O ST Digital I/O. SDI I ST SPI data in. SDA I/O I2C I2C data I/O. RC5/SDO 46 RC5 I/O ST Digital I/O. SDO O — SPI data out. RC6/TX1/CK1 37 RC6 I/O ST Digital I/O. TX1 O — EUSART1 asynchronous transmit. CK1 I/O ST EUSART1 synchronous clock (see related RX1/DT1). RC7/RX1/DT1 38 RC7 I/O ST Digital I/O. RX1 I ST EUSART1 asynchronous receive. DT1 I/O ST EUSART1 synchronous data (see related TX1/CK1). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2C = ST with I2C™ or SMB levels Note 1: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Microcontroller mode). 2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only).  2010 Microchip Technology Inc. DS39635C-page 25

PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTD is a bidirectional I/O port. RD0/AD0/PSP0 72 RD0 I/O ST Digital I/O. AD0 I/O TTL External Memory Address/Data 0. PSP0 I/O TTL Parallel Slave Port data. RD1/AD1/PSP1 69 RD1 I/O ST Digital I/O. AD1 I/O TTL External Memory Address/Data 1. PSP1 I/O TTL Parallel Slave Port data. RD2/AD2/PSP2 68 RD2 I/O ST Digital I/O. AD2 I/O TTL External Memory Address/Data 2. PSP2 I/O TTL Parallel Slave Port data. RD3/AD3/PSP3 67 RD3 I/O ST Digital I/O. AD3 I/O TTL External Memory Address/Data 3. PSP3 I/O TTL Parallel Slave Port data. RD4/AD4/PSP4 66 RD4 I/O ST Digital I/O. AD4 I/O TTL External Memory Address/Data 4. PSP4 I/O TTL Parallel Slave Port data. RD5/AD5/PSP5 65 RD5 I/O ST Digital I/O. AD5 I/O TTL External Memory Address/Data 5. PSP5 I/O TTL Parallel Slave Port data. RD6/AD6/PSP6 64 RD6 I/O ST Digital I/O. AD6 I/O TTL External Memory Address/Data 6. PSP6 I/O TTL Parallel Slave Port data. RD7/AD7/PSP7 63 RD7 I/O ST Digital I/O. AD7 I/O TTL External Memory Address/Data 7. PSP7 I/O TTL Parallel Slave Port data. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2C = ST with I2C™ or SMB levels Note 1: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Microcontroller mode). 2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only). DS39635C-page 26  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTE is a bidirectional I/O port. RE0/AD8/RD 4 RE0 I/O ST Digital I/O. AD8 I/O TTL External Memory Address/Data 8. RD I TTL Read control for Parallel Slave Port. RE1/AD9/WR 3 RE1 I/O ST Digital I/O. AD9 I/O TTL External Memory Address/Data 9. WR I TTL Write control for Parallel Slave Port. RE2/AD10/CS 78 RE2 I/O ST Digital I/O. AD10 I/O TTL External Memory Address/Data 10. CS I TTL Chip Select control for Parallel Slave Port. RE3/AD11 77 RE3 I/O ST Digital I/O. AD11 I/O TTL External Memory Address/Data 11. RE4/AD12 76 RE4 I/O ST Digital I/O. AD12 I/O TTL External Memory Address/Data 12. RE5/AD13 75 RE5 I/O ST Digital I/O. AD13 I/O TTL External Memory Address/Data 13. RE6/AD14 74 RE6 I/O ST Digital I/O. AD14 I/O TTL External Memory Address/Data 14. RE7/CCP2/AD15 73 RE7 I/O ST Digital I/O. CCP2(3) I/O ST Capture 2 input/Compare 2 output/PWM2 output. AD15 I/O TTL External Memory Address/Data 15. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2C = ST with I2C™ or SMB levels Note 1: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Microcontroller mode). 2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only).  2010 Microchip Technology Inc. DS39635C-page 27

PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTF is a bidirectional I/O port. RF0/AN5 24 RF0 I/O ST Digital I/O. AN5 I Analog Analog Input 5. RF1/AN6/C2OUT 23 RF1 I/O ST Digital I/O. AN6 I Analog Analog Input 6. C2OUT O — Comparator 2 output. RF2/AN7/C1OUT 18 RF2 I/O ST Digital I/O. AN7 I Analog Analog Input 7. C1OUT O — Comparator 1 output. RF3/AN8 17 RF3 I/O ST Digital I/O. AN8 I Analog Analog Input 8. RF4/AN9 16 RF4 I/O ST Digital I/O. AN9 I Analog Analog Input 9. RF5/AN10/CVREF 15 RF5 I/O ST Digital I/O. AN10 I Analog Analog Input 10. CVREF O Analog Comparator reference voltage output. RF6/AN11 14 RF6 I/O ST Digital I/O. AN11 I Analog Analog Input 11. RF7/SS 13 RF7 I/O ST Digital I/O. SS I TTL SPI slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2C = ST with I2C™ or SMB levels Note 1: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Microcontroller mode). 2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only). DS39635C-page 28  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTG is a bidirectional I/O port. RG0/CCP3 5 RG0 I/O ST Digital I/O. CCP3 I/O ST Capture 3 input/Compare 3 output/PWM3 output. RG1/TX2/CK2 6 RG1 I/O ST Digital I/O. TX2 O — AUSART2 asynchronous transmit. CK2 I/O ST AUSART2 synchronous clock (see related RX2/DT2). RG2/RX2/DT2 7 RG2 I/O ST Digital I/O. RX2 I ST AUSART2 asynchronous receive. DT2 I/O ST AUSART2 synchronous data (see related TX2/CK2). RG3 8 I/O ST Digital I/O. RG4 10 I/O ST Digital I/O. RG5 See RG5/MCLR/VPP pin. PORTH is a bidirectional I/O port. RH0/AD16 79 RH0 I/O ST Digital I/O. AD16 I/O TTL External Memory Address/Data 16. RH1/AD17 80 RH1 I/O ST Digital I/O. AD17 I/O TTL External Memory Address/Data 17. RH2/AD18 1 RH2 I/O ST Digital I/O. AD18 I/O TTL External Memory Address/Data 18. RH3/AD19 2 RH3 I/O ST Digital I/O. AD19 I/O TTL External Memory Address/Data 19. RH4 22 I/O ST Digital I/O. RH5 21 I/O ST Digital I/O. RH6 20 I/O ST Digital I/O. RH7 19 I/O ST Digital I/O. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2C = ST with I2C™ or SMB levels Note 1: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Microcontroller mode). 2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only).  2010 Microchip Technology Inc. DS39635C-page 29

PIC18F6310/6410/8310/8410 TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description Type Type TQFP PORTJ is a bidirectional I/O port. RJ0/ALE 62 RJ0 I/O ST Digital I/O. ALE O — External memory address latch enable. RJ1/OE 61 RJ1 I/O ST Digital I/O. OE O — External memory output enable. RJ2/WRL 60 RJ2 I/O ST Digital I/O. WRL O — External memory write low control. RJ3/WRH 59 RJ3 I/O ST Digital I/O. WRH O — External memory write high control. RJ4/BA0 39 RJ4 I/O ST Digital I/O. BA0 O — External Memory Byte Address 0 control. RJ5/CE 40 RJ4 I/O ST Digital I/O CE O — External memory chip enable control. RJ6/LB 41 RJ6 I/O ST Digital I/O. LB O — External memory low byte control. RJ7/UB 42 RJ7 I/O ST Digital I/O. UB O — External memory high byte control. VSS 11, 31, 51, 70 P — Ground reference for logic and I/O pins. VDD 12, 32, 48, 71 P — Positive supply for logic and I/O pins. AVSS 26 P — Ground reference for analog modules. AVDD 25 P — Positive supply for analog modules. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2C = ST with I2C™ or SMB levels Note 1: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Microcontroller mode). 2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only). DS39635C-page 30  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 2.0 GUIDELINES FOR GETTING FIGURE 2-1: RECOMMENDED STARTED WITH PIC18F MINIMUM CONNECTIONS MICROCONTROLLERS C2(1) 2.1 Basic Connection Requirements VDD Getting started with the PIC18F6310/6410/8310/8410 R1 DD SS family of 8-bit microcontrollers requires attention to a V V R2 minimal set of device pin connections before MCLR proceeding with development. C1 VDD The following pins must always be connected: PIC18FXXXX C3(1) • All VDD and VSS pins VSS (see Section2.2 “Power Supply Pins”) VSS C6(1) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used VDD D S D S D S (see Section2.2 “Power Supply Pins”) V V D S A A V V • MCLR pin (see Section2.3 “Master Clear (MCLR) Pin”) C5(1) C4(1) These pins must also be connected if they are being used in the end application: • PGC/PGD pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes Key (all values are recommendations): (see Section2.4 “ICSP Pins”) C1 through C6: 0.1 µF, 20V ceramic • OSCI and OSCO pins when an external oscillator R1: 10 kΩ source is used R2: 100Ω to 470Ω (see Section2.5 “External Oscillator Pins”) Note 1: The example shown is for a PIC18F device Additionally, the following pins may be required: with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; • VREF+/VREF- pins are used when external voltage adjust the number of decoupling capacitors reference for analog modules is implemented appropriately. Note: The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure2-1.  2010 Microchip Technology Inc. DS39635C-page 31

PIC18F6310/6410/8310/8410 2.2 Power Supply Pins 2.2.2 TANK CAPACITORS On boards with power traces running longer than 2.2.1 DECOUPLING CAPACITORS sixinches in length, it is suggested to use a tank capac- The use of decoupling capacitors on every pair of itor for integrated circuits, including microcontrollers, to power supply pins, such as VDD, VSS, AVDD and supply a local power source. The value of the tank AVSS, is required. capacitor should be determined based on the trace resistance that connects the power supply source to Consider the following criteria when using decoupling the device, and the maximum current drawn by the capacitors: device in the application. In other words, select the tank • Value and type of capacitor: A 0.1 F (100 nF), capacitor so that it meets the acceptable voltage sag at 10-20V capacitor is recommended. The capacitor the device. Typical values range from 4.7F to 47F. should be a low-ESR device, with a resonance frequency in the range of 200MHz and higher. 2.2.3 CONSIDERATIONS WHEN USING Ceramic capacitors are recommended. BOR • Placement on the printed circuit board: The When the Brown-out Reset (BOR) feature is enabled, decoupling capacitors should be placed as close a sudden change in VDD may result in a spontaneous to the pins as possible. It is recommended to BOR event. This can happen when the microcontroller place the capacitors on the same side of the is operating under normal operating conditions, regard- board as the device. If space is constricted, the less of what the BOR set point has been programmed capacitor can be placed on another layer on the to, and even if VDD does not approach the set point. PCB using a via; however, ensure that the trace The precipitating factor in these BOR events is a rise or length from the pin to the capacitor is no greater fall in VDD with a slew rate faster than 0.15V/s. than 0.25inch (6mm). An application that incorporates adequate decoupling • Handling high-frequency noise: If the board is between the power supplies will not experience such experiencing high-frequency noise (upward of rapid voltage changes. Additionally, the use of an tens of MHz), add a second ceramic type capaci- tor in parallel to the above described decoupling electrolytic tank capacitor across VDD and VSS, as described above, will be helpful in preventing high slew capacitor. The value of the second capacitor can rate transitions. be in the range of 0.01F to 0.001F. Place this second capacitor next to each primary decoupling If the application has components that turn on or off, capacitor. In high-speed circuit designs, consider and share the same VDD circuit as the microcontroller, implementing a decade pair of capacitances as the BOR can be disabled in software by using the close to the power and ground pins as possible SBOREN bit before switching the component. After- (e.g., 0.1F in parallel with 0.001F). wards, allow a small delay before re-enabling the BOR. • Maximizing performance: On the board layout By doing this, it is ensured that the BOR is disabled from the power supply circuit, run the power and during the interval that might cause high slew rate return traces to the decoupling capacitors first, changes of VDD. and then to the device pins. This ensures that the Note: Not all devices incorporate software BOR decoupling capacitors are first in the power chain. control. See Section5.0 “Reset” for Equally important is to keep the trace length device-specific information. between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. DS39635C-page 32  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 2.3 Master Clear (MCLR) Pin 2.4 ICSP Pins The MCLR pin provides two specific device The PGC and PGD pins are used for In-Circuit Serial functions: Device Reset, and Device Programming Programming™ (ICSP™) and debugging purposes. It and Debugging. If programming and debugging are is recommended to keep the trace length between the not required in the end application, a direct ICSP connector and the ICSP pins on the device as connection to VDD may be all that is required. The short as possible. If the ICSP connector is expected to addition of other components, to help increase the experience an ESD event, a series resistor is recom- application’s resistance to spurious Resets from mended, with the value in the range of a few tens of voltage sags, may be beneficial. A typical ohms, not to exceed 100Ω. configuration is shown in Figure2-1. Other circuit Pull-up resistors, series diodes, and capacitors on the designs may be implemented, depending on the PGC and PGD pins are not recommended as they will application’s requirements. interfere with the programmer/debugger communica- During programming and debugging, the resistance tions to the device. If such discrete components are an and capacitance that can be added to the pin must be application requirement, they should be removed from considered. Device programmers and debuggers drive the circuit during programming and debugging. Alter- the MCLR pin. Consequently, specific voltage levels natively, refer to the AC/DC characteristics and timing (VIH and VIL) and fast signal transitions must not be requirements information in the respective device adversely affected. Therefore, specific values of R1 Flash programming specification for information on and C1 will need to be adjusted based on the capacitive loading limits and pin input voltage high (VIH) application and PCB requirements. For example, it is and input low (VIL) requirements. recommended that the capacitor, C1, be isolated from For device emulation, ensure that the “Communication the MCLR pin during programming and debugging Channel Select” (i.e., PGCx/PGDx pins) programmed operations by using a jumper (Figure2-2). The jumper into the device matches the physical connections for is replaced for normal run-time operations. the ICSP to the Microchip debugger/emulator tool. Any components associated with the MCLR pin For more information on available Microchip should be placed within 0.25 inch (6mm) of the pin. development tools connection requirements, refer to Section26.0 “Development Support”. FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS VDD R1 R2 MCLR JP PIC18FXXXX C1 Note 1: R1 10k is recommended. A suggested starting value is 10k. Ensure that the MCLR pin VIH and VIL specifications are met. 2: R2 470 will limit any current flowing into MCLR from the external capacitor, C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met.  2010 Microchip Technology Inc. DS39635C-page 33

PIC18F6310/6410/8310/8410 2.5 External Oscillator Pins FIGURE 2-3: SUGGESTED PLACEMENT OF THE OSCILLATOR Many microcontrollers have options for at least two CIRCUIT oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Single-Sided and In-Line Layouts: Section3.0 “Oscillator Configurations” for details). Copper Pour Primary Oscillator The oscillator circuit should be placed on the same (tied to ground) Crystal side of the board as the device. Place the oscillator DEVICE PINS circuit close to the respective oscillator pins with no more than 0.5inch (12mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side Primary OSC1 Oscillator of the board. C1 ` OSC2 Use a grounded copper pour around the oscillator cir- cuit to isolate it from surrounding circuits. The C2 GND grounded copper pour should be routed directly to the ` MCU ground. Do not run any signal traces or power T1OSO traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board T1OS I Timer1 Oscillator where the crystal is placed. Crystal ` Layout suggestions are shown in Figure 2-4. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With T1 Oscillator: C1 T1 Oscillator: C2 fine-pitch packages, it is not always possible to com- pletely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored Fine-Pitch (Dual-Sided) Layouts: ground layer. In all cases, the guard trace(s) must be returned to ground. Top Layer Copper Pour (tied to ground) In planning the application’s routing and I/O assign- ments, ensure that adjacent port pins and other signals Bottom Layer in close proximity to the oscillator are benign (i.e., free Copper Pour of high frequencies, short rise and fall times, and other (tied to ground) similar noise). OSCO For additional information and design guidance on oscillator circuits, please refer to these Microchip C2 Application Notes, available at the corporate web site Oscillator (www.microchip.com): GND Crystal • AN826, “Crystal Oscillator Basics and Crystal C1 Selection for rfPIC™ and PICmicro® Devices” • AN849, “Basic PICmicro® Oscillator Design” OSCI • AN943, “Practical PICmicro® Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” 2.6 Unused I/Os DEVICE PINS Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1kΩ to 10kΩ resistor to VSS on unused pins and drive the output to logic low. DS39635C-page 34  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 3.0 OSCILLATOR FIGURE 3-1: CRYSTAL/CERAMIC CONFIGURATIONS RESONATOR OPERATION (XT, LP, HS OR HSPLL 3.1 Oscillator Types CONFIGURATION) PIC18F6310/6410/8310/8410 devices can be operated C1(1) OSC1 in ten different oscillator modes. The user can program To the Configuration bits, FOSC<3:0>, in Configuration Internal Register 1H to select one of these ten modes: XTAL (3) Logic RF 1. LP Low-Power Crystal Sleep 2. XT Crystal/Resonator RS(2) 3. HS High-Speed Crystal/Resonator C2(1) OSC2 PIC18FXXXX 4. HSPLL High-Speed Crystal/Resonator with PLL enabled Note 1: See Table3-1 and Table3-2 for initial values of 5. RC External Resistor/Capacitor with C1 and C2. FOSC/4 output on RA6 2: A series resistor (RS) may be required for AT 6. RCIO External Resistor/Capacitor with I/O strip cut crystals. on RA6 3: RF varies with the oscillator mode chosen. 7. INTIO1 Internal Oscillator with FOSC/4 output on RA6 and I/O on RA7 TABLE 3-1: CAPACITOR SELECTION FOR 8. INTIO2 Internal Oscillator with I/O on RA6 CERAMIC RESONATORS and RA7 9. EC External Clock with FOSC/4 output Typical Capacitor Values Used: 10. ECIO External Clock with I/O on RA6 Mode Freq OSC1 OSC2 3.2 Crystal Oscillator/Ceramic XT 455 kHz 56 pF 56 pF 2.0 MHz 47 pF 47 pF Resonators 4.0 MHz 33 pF 33 pF In XT, LP, HS or HSPLL Oscillator modes, a crystal or HS 8.0 MHz 27 pF 27 pF ceramic resonator is connected to the OSC1 and 16.0 MHz 22 pF 22 pF OSC2 pins to establish oscillation. Figure3-1 shows Capacitor values are for design guidance only. the pin connections. These capacitors were tested with the resonators The oscillator design requires the use of a parallel listed below for basic start-up and operation. These resonant crystal. values are not optimized. Note: Use of a series resonant crystal may give a Different capacitor values may be required to produce frequency out of the crystal manufacturer’s acceptable oscillator operation. The user should test specifications. the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following Table3-2 for additional information. Resonators Used: 455 kHz 4.0 MHz 2.0 MHz 8.0 MHz 16.0 MHz  2010 Microchip Technology Inc. DS39635C-page 35

PIC18F6310/6410/8310/8410 TABLE 3-2: CAPACITOR SELECTION FOR An external clock source may also be connected to the CRYSTAL OSCILLATOR OSC1 pin in the HS mode, as shown in Figure3-2. Typical Capacitor Values FIGURE 3-2: EXTERNAL CLOCK Crystal Tested: Osc Type INPUT OPERATION Freq C1 C2 (HS OSCILLATOR CONFIGURATION) LP 32 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF XT 1 MHz 33 pF 33 pF Clock from OSC1 Ext. System PIC18FXXXX 4 MHz 27 pF 27 pF (HS Mode) HS 4 MHz 27 pF 27 pF Open OSC2 8 MHz 22 pF 22 pF 20 MHz 15 pF 15 pF 3.3 External Clock Input Capacitor values are for design guidance only. These capacitors were tested with the crystals listed The EC and ECIO Oscillator modes require an external below for basic start-up and operation. These values clock source to be connected to the OSC1 pin. There is are not optimized. no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. Different capacitor values may be required to produce acceptable oscillator operation. The user should test In the EC Oscillator mode, the oscillator frequency the performance of the oscillator over the expected divided by 4 is available on the OSC2 pin. This signal VDD and temperature range for the application. may be used for test purposes or to synchronize other logic. Figure3-3 shows the pin connections for the EC See the notes following this table for additional Oscillator mode. information. Crystals Used: FIGURE 3-3: EXTERNAL CLOCK INPUT OPERATION 32 kHz 4 MHz (EC CONFIGURATION) 200 kHz 8 MHz 1 MHz 20 MHz Clock from OSC1/CLKI Ext. System PIC18FXXXX Note 1: Higher capacitance increases the stability FOSC/4 OSC2/CLKO of oscillator, but also increases the start-up time. 2: When operating below 3V VDD, or when The ECIO Oscillator mode functions like the EC mode, using certain ceramic resonators at any except that the OSC2 pin becomes an additional gen- voltage, it may be necessary to use the eral purpose I/O pin. The I/O pin becomes bit 6 of HS mode or switch to a crystal oscillator. PORTA (RA6). Figure3-4 shows the pin connections 3: Since each resonator/crystal has its own for the ECIO Oscillator mode. characteristics, the user should consult the resonator/crystal manufacturer for FIGURE 3-4: EXTERNAL CLOCK appropriate values of external INPUT OPERATION components. (ECIO CONFIGURATION) 4: Rs may be required to avoid overdriving crystals with low drive level specification. Clock from OSC1/CLKI 5: Always verify oscillator performance over Ext. System PIC18FXXXX the VDD and temperature range that is expected for the application. RA6 I/O (OSC2) DS39635C-page 36  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 3.4 RC Oscillator 3.5 PLL Frequency Multiplier For timing-insensitive applications, the “RC” and A Phase Locked Loop (PLL) circuit is provided as an “RCIO” device options offer additional cost savings. option for users who want to use a lower frequency The actual oscillator frequency is a function of several oscillator circuit, or to clock the device up to its highest factors: rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due • Supply voltage to high-frequency crystals, or users who require higher • Values of the external resistor (REXT) and clock speeds from an internal oscillator. capacitor (CEXT) • Operating temperature 3.5.1 HSPLL OSCILLATOR MODE Given the same device, operating voltage and The HSPLL mode makes use of the HS Oscillator temperature and component values, there will also be mode for frequencies up to 10 MHz. A PLL then unit-to-unit frequency variations. These are due to multiplies the oscillator output frequency by 4 to factors such as: produce an internal clock frequency up to 40 MHz. • Normal manufacturing variation The PLL is only available to the crystal oscillator when • Difference in lead frame capacitance between the FOSC<3:0> Configuration bits are programmed for package types (especially for low CEXT values) HSPLL mode (= 0110). • Variations within the tolerance of limits of REXT and CEXT FIGURE 3-7: PLL BLOCK DIAGRAM (HS MODE) In the RC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal HS Oscillator Enable may be used for test purposes or to synchronize other PLL Enable logic. Figure3-5 shows how the R/C combination is (from Configuration Register 1H) connected. OSC2 FIGURE 3-5: RC OSCILLATOR MODE Phase HS Mode FIN Comparator VDD Crystal OSC1 Oscillator FOUT REXT Internal OSC1 Loop Clock Filter CEXT PIC18FXXXX VSS 4 VCO OSC2/CLKO SYSCLK FOSC/4 X U M Recommended values: 3 k  REXT  100 k CEXT > 20 pF The RCIO Oscillator mode (Figure3-6) functions like 3.5.2 PLL AND INTOSC the RC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin The PLL is also available to the internal oscillator block becomes bit 6 of PORTA (RA6). in selected oscillator modes. In this configuration, the PLL is enabled in software and generates a clock out- FIGURE 3-6: RCIO OSCILLATOR MODE put of up to 32MHz. The operation of INTOSC with the PLL is described in Section3.6.4 “PLL in INTOSC VDD Modes”. REXT Internal OSC1 Clock CEXT PIC18FXXXX VSS RA6 I/O (OSC2) Recommended values: 3 k  REXT  100 k CEXT > 20 pF  2010 Microchip Technology Inc. DS39635C-page 37

PIC18F6310/6410/8310/8410 3.6 Internal Oscillator Block When the OSCTUNE register is modified, the INTOSC frequency will begin shifting to the new frequency. The The PIC18F6310/6410/8310/8410 devices include an INTOSC clock will stabilize within 1ms. Code execu- internal oscillator block, which generates two different tion continues during this shift. There is no indication clock signals; either can be used as the micro- that the shift has occurred. controller’s clock source. This may eliminate the need The OSCTUNE register also implements the INTSRC for external oscillator circuits on the OSC1 and/or and PLLEN bits, which control certain features of the OSC2 pins. internal oscillator block. The INTSRC bit allows users The main output (INTOSC) is an 8MHz clock source, to select which internal oscillator provides the clock which can be used to directly drive the device clock. It source when the 31kHz frequency option is selected. also drives a postscaler, which can provide a range of This is covered in greater detail in Section3.7.1 clock frequencies from 31kHz to 4MHz. The INTOSC “Oscillator Control Register”. output is enabled when a clock frequency from 125kHz The PLLEN bit controls the operation of the frequency to 8MHz is selected. multiplier, PLL, in internal oscillator modes. The other clock source is the internal RC oscillator (INTRC), which provides a nominal 31kHz output. 3.6.4 PLL IN INTOSC MODES INTRC is enabled if it is selected as the device clock The 4x frequency multiplier can be used with the source; it is also enabled automatically when any of the internal oscillator block to produce faster device clock following are enabled: speeds than are normally possible with an internal • Power-up Timer oscillator. When enabled, the PLL produces a clock • Fail-Safe Clock Monitor speed of up to 32MHz. • Watchdog Timer Unlike HSPLL mode, the PLL is controlled through • Two-Speed Start-up software. The control bit, PLLEN (OSCTUNE<6>), is used to enable or disable its operation. These features are discussed in greater detail in Section24.0 “Special Features of the CPU”. The PLL is available when the device is configured to use the internal oscillator block as its primary clock source The clock source frequency (INTOSC direct, INTRC (FOSC<3:0> = 1001 or 1000). Additionally, the PLL will direct or INTOSC postscaler) is selected by configuring only function when the selected output frequency is the IRCF bits of the OSCCON register (Register3-2). either 4MHz or 8MHz (OSCCON<6:4> = 111 or 110). If 3.6.1 INTIO MODES both of these conditions are not met, the PLL is disabled. Using the internal oscillator as the clock source elimi- The PLLEN control bit is only functional in those inter- nates the need for up to two external oscillator pins, nal oscillator modes where the PLL is available. In all which can then be used for digital I/O. Two distinct other modes, it is forced to ‘0’ and is effectively configurations are available: unavailable. • In INTIO1 mode, the OSC2 pin outputs FOSC/4, 3.6.5 INTOSC FREQUENCY DRIFT while OSC1 functions as RA7 for digital input and The factory calibrates the internal oscillator block out- output. put (INTOSC) for 8 MHz. However, this frequency may • In INTIO2 mode, OSC1 functions as RA7 and drift as VDD or temperature changes, which can affect OSC2 functions as RA6, both for digital input and the controller operation in a variety of ways. It is output. possible to adjust the INTOSC frequency by modifying the value in the OSTUNE register. This has no effect on 3.6.2 INTOSC OUTPUT FREQUENCY the INTRC clock source frequency. The internal oscillator block is calibrated at the factory Tuning the INTOSC source requires knowing when to to produce an INTOSC output frequency of 8.0MHz. make the adjustment, in which direction it should be The INTRC oscillator operates independently of the made and in some cases, how large a change is INTOSC source. Any changes in INTOSC across needed. Three examples follow, but other techniques voltage and temperature are not necessarily reflected may be used. Three compensation techniques are dis- by changes in INTRC and vice versa. cussed in Section3.6.5.1 “Compensating with the AUSART”, Section3.6.5.2 “Compensating with the 3.6.3 OSCTUNE REGISTER Timers”” and Section3.6.5.3 “Compensating with The internal oscillator’s output has been calibrated at the Timers”, but other techniques may be used. the factory, but can be adjusted in the user’s applica- tion. This is done by writing to the OSCTUNE register (Register3-1). DS39635C-page 38  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 3.6.5.1 Compensating with the AUSART is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement An adjustment may be required when the AUSART the OSCTUNE register. begins to generate framing errors or receives data with errors while in Asynchronous mode. Framing errors 3.6.5.3 Compensating with the Timers indicate that the device clock frequency is too high; to adjust for this, decrement the value in OSTUNE to A CCP module can use free running Timer1 (or reduce the clock frequency. On the other hand, errors Timer3), clocked by the internal oscillator block and an in data may suggest that the clock speed is too low; to external event with a known period (i.e., AC power compensate, increment OSTUNE to increase the clock frequency). The time of the first event is captured in the frequency. CCPRxH:CCPRxL registers and is recorded. When the second event causes a capture, the time of the first 3.6.5.2 Compensating with the Timers event is subtracted from the time of the second event. Since the period of the external event is known, the This technique compares device clock speed to some time difference between events can be calculated. reference clock. Two timers may be used; one timer is clocked by the peripheral clock, while the other is If the measured time is much greater than the clocked by a fixed reference source, such as the calculated time, then the internal oscillator block is Timer1 oscillator. running too fast; to compensate, decrement the OSTUNE register. If the measured time is much less Both timers are cleared, but the timer clocked by the than the calculated time, then the internal oscillator reference generates interrupts. When an interrupt block is running too slow; to compensate, increment occurs, the internally clocked timer is read and both the OSTUNE register. timers are cleared. If the internally clocked timer value REGISTER 3-1: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN(1) — TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25kHz device clock derived from 8MHz INTOSC source (divide-by-256 enabled) 0 = 31kHz device clock derived directly from INTRC internal oscillator bit 6 PLLEN: Frequency Multiplier PLL for INTOSC Enable bit(1) 1 = PLL enabled for INTOSC (4MHz and 8MHz only) 0 = PLL disabled bit 5 Unimplemented: Read as ‘0’ bit 4-0 TUN<4:0>: Frequency Tuning bits 01111 = Maximum frequency • • • • 00001 00000 = Center frequency. Oscillator module is running at the calibrated frequency. 11111 • • • • 10000 = Minimum frequency Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as ‘0’. See Section3.6.4 “PLL in INTOSC Modes” for details.  2010 Microchip Technology Inc. DS39635C-page 39

PIC18F6310/6410/8310/8410 3.7 Clock Sources and The secondary oscillators are those external sources Oscillator Switching not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the Like previous PIC18 devices, the controller is placed in a power-managed mode. PIC18F6310/6410/8310/8410 family includes a feature PIC18F6310/6410/8310/8410 devices offer the Timer1 that allows the device clock source to be switched from oscillator as a secondary oscillator. This oscillator, in all the main oscillator to an alternate low-frequency clock power-managed modes, is often the time base for source. PIC18F6310/6410/8310/8410 devices offer two functions such as a Real-Time Clock (RTC). alternate clock sources. When an alternate clock source is enabled, the various power-managed operating Most often, a 32.768 kHz watch crystal is connected modes are available. between the RC0/T1OSO/T13CKI and RC1/T1OSI/CCP2 pins. Like the LP mode oscillator Essentially, there are three clock sources for these circuit, loading capacitors are also connected from devices: each pin to ground. • Primary oscillators The Timer1 oscillator is discussed in greater detail in • Secondary oscillators Section13.3 “Timer1 Oscillator”. • Internal oscillator block In addition to being a primary clock source, the internal The primary oscillators include the External Crystal oscillator block is available as a power-managed and Resonator modes, the External RC modes, the mode clock source. The INTRC source is also used as External Clock modes and the internal oscillator block. the clock source for several special features, such as The particular mode is defined by the FOSC<3:0> the WDT and Fail-Safe Clock Monitor. Configuration bits. The details of these modes are The clock sources for the PIC18F6310/6410/8310/8410 covered earlier in this chapter. devices are shown in Figure3-8. See Section24.0 “Special Features of the CPU” for Configuration register details. FIGURE 3-8: PIC18F6310/6410/8310/8410 CLOCK DIAGRAM Primary Oscillator LP, XT, HS, RC, EC OSC2 Sleep HSPLL, INTOSC/PLL 4 x PLL OSC1 OSCTUNE<6> Secondary Oscillator T1OSC X Peripherals T1OSO U M T1OSCEN Enable T1OSI Oscillator OSCCON<6:4> Internal Oscillator OSCCON<6:4> 8 MHz CPU 111 4 MHz Internal 110 Oscillator 2 MHz IDLEN Block er 1 MHz 101 Clock S8o MurHcze 8 MHz stscal 500 kHz 100101MUX Control INTRC (INTOSC) Po 250 kHz 010 FOSC<3:0> OSCCON< 1:0> Source 125 kHz 001 Clock Source Option 1 31 kHz 31 kHz (INTRC) 000 for other Modules 0 OSCTUNE<7> WDT, PWRT, FSCM and Two-Speed Start-up DS39635C-page 40  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 3.7.1 OSCILLATOR CONTROL REGISTER device clock in primary clock modes. The IOFS bit indicates when the internal oscillator block has stabi- The OSCCON register (Register3-2) controls several lized and is providing the device clock in RC Clock aspects of the device clock’s operation, both in modes. The T1RUN bit (T1CON<6>) indicates when full-power operation and in power-managed modes. the Timer1 oscillator is providing the device clock in The System Clock Select bits, SCS<1:0>, select the secondary clock modes. In power-managed modes, clock source. The available clock sources are the pri- only one of these three bits will be set at any time. If mary clock (defined by the FOSC<3:0> Configuration none of these bits are set, the INTRC is providing the bits), the secondary clock (Timer1 oscillator) and the clock, or the internal oscillator block has just started internal oscillator block. The clock source changes and is not yet stable. immediately after one or more of the bits is written to, The IDLEN bit determines if the device goes into Sleep following a brief clock transition interval. The SCS bits mode or one of the Idle modes when the SLEEP are cleared on all forms of Reset. instruction is executed. The Internal Oscillator Frequency Select bits, The use of the flag and control bits in the OSCCON IRCF<2:0>, select the frequency output of the internal register is discussed in more detail in Section4.0 oscillator block to drive the device clock. The choices “Power-Managed Modes”. are the INTRC source, the INTOSC source (8MHz) or one of the frequencies derived from the INTOSC post- Note 1: The Timer1 oscillator must be enabled to scaler (31.25 kHz to 4 MHz). If the internal oscillator select the secondary clock source. The block is supplying the device clock, changing the states Timer1 oscillator is enabled by setting the of these bits will have an immediate change on the T1OSCEN bit in the Timer1 Control regis- internal oscillator’s output. Resets, the default output ter (T1CON<3>). If the Timer1 oscillator is frequency of the internal oscillator block, are set at not enabled, then any attempt to select a 1MHz. secondary clock source when executing a When an output frequency of 31kHz is selected SLEEP instruction will be ignored. (IRCF<2:0> = 000), users may choose which internal 2: It is recommended that the Timer1 oscillator acts as the source. This is done with the oscillator be operating and stable before INTSRC bit in the OSCTUNE register (OSCTUNE<7>). executing the SLEEP instruction or a very Setting this bit selects INTOSC as a 31.25kHz clock long delay may occur while the Timer1 source by enabling the divide-by-256 output of the oscillator starts. INTOSC postscaler. Clearing INTSRC selects INTRC (nominally 31kHz) as the clock source. 3.7.2 OSCILLATOR TRANSITIONS This option allows users to select the tunable and more PIC18F6310/6410/8310/8410 devices contain circuitry precise INTOSC as a clock source, while maintaining to prevent clock “glitches” when switching between power savings with a very low clock speed. Regardless clock sources. A short pause in the device clock occurs of the setting of INTSRC, INTRC always remains the during the clock switch. The length of this pause is the clock source for features such as the Watchdog Timer sum of two cycles of the old clock source and three to and the Fail-Safe Clock Monitor. four cycles of the new clock source. This formula The OSTS, IOFS and T1RUN bits indicate which clock assumes that the new clock source is stable. source is currently providing the device clock. The Clock transitions are discussed in greater detail in OSTS bit indicates that the Oscillator Start-up Timer Section4.1.2 “Entering Power-Managed Modes”. has timed out and the primary clock is providing the  2010 Microchip Technology Inc. DS39635C-page 41

PIC18F6310/6410/8310/8410 REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits 111 = 8MHz (INTOSC drives clock directly) 110 = 4MHz 101 = 2MHz 100 = 1MHz(3) 011 = 500kHz 010 = 250kHz 001 = 125kHz 000 = 31kHz (from either INTOSC/256 or INTRC directly)(2) bit 3 OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready bit 2 IOFS: INTOSC Frequency Stable bit 1 = INTOSC frequency is stable 0 = INTOSC frequency is not stable bit 1-0 SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Secondary (Timer1) oscillator 00 = Primary oscillator Note 1: Depends on the state of the IESO Configuration bit. 2: Source selected by the INTSRC bit (OSCTUNE<7>), see Section3.6.3 “OSCTUNE Register”. 3: Default output frequency of INTOSC on Reset. DS39635C-page 42  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 3.8 Effects of Power-Managed Modes 3.9 Power-up Delays on the Various Clock Sources Power-up delays are controlled by two timers, so that no When PRI_IDLE mode is selected, the designated external Reset circuitry is required for most applications. primary oscillator continues to run without interruption. The delays ensure that the device is kept in Reset until For all other power-managed modes, the oscillator the device power supply is stable under normal using the OSC1 pin is disabled. The OSC1 pin (and circumstances and the primary clock is operating and OSC2 pin, if used by the oscillator) will stop oscillating. stable. For additional information on power-up delays, see Section5.5 “Device Reset Timers”. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and The first timer is the Power-up Timer (PWRT), which providing the device clock. The Timer1 oscillator may provides a fixed delay on power-up (Parameter 33, also run in all power-managed modes if required to Table27-12). It is enabled by clearing (= 0) the clock Timer1 or Timer3. PWRTEN Configuration bit. In internal oscillator modes (RC_RUN and RC_IDLE), The second timer is the Oscillator Start-up Timer the internal oscillator block provides the device clock (OST), intended to keep the chip in Reset until the source. The 31kHz INTRC output can be used directly crystal oscillator is stable (LP, XT and HS modes). The to provide the clock and may be enabled to support var- OST does this by counting 1024 oscillator cycles ious special features, regardless of the power-managed before allowing the oscillator to clock the device. mode (see Section24.2 “Watchdog Timer (WDT)” When the HSPLL Oscillator mode is selected, the through Section24.4 “Fail-Safe Clock Monitor” for device is kept in Reset for an additional 2ms, following more information on WDT, Fail-Safe Clock Monitor and the HS mode OST delay, so the PLL can lock to the Two-Speed Start-up). The INTOSC output at 8MHz may incoming clock frequency. be used directly to clock the device, or may be divided There is a delay of interval, TCSD (Parameter 38, down by the postscaler. The INTOSC output is disabled Table27-12), following POR while the controller if the clock is provided directly from the INTRC output. becomes ready to execute instructions. This delay runs If the Sleep mode is selected, all clock sources are concurrently with any other delays. This may be the stopped. Since all the transistor switching currents only delay that occurs when any of the EC, RC or INTIO have been stopped, Sleep mode achieves the lowest modes are used as the primary clock source. current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The INTRC is required to support WDT operation. The Timer1 oscillator may be operating to support a real-time clock. Other features may be operating that do not require a device clock source (i.e., MSSP slave, PSP, INTx pins and others). Peripherals that may add significant current consumption are listed in Section27.2 “DC Characteristics: Power-Down and Supply Current”. TABLE 3-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE(1) Oscillator Mode OSC1 Pin OSC2 Pin RC, INTIO1 Floating, external resistor should pull high At logic low (clock/4 output) RCIO, INTIO2 Floating, external resistor should pull high Configured as PORTA, bit 6 ECIO Floating, pulled by external clock Configured as PORTA, bit 6 EC Floating, pulled by external clock At logic low (clock/4 output) LP, XT and HS Feedback inverter disabled at quiescent Feedback inverter disabled at quiescent voltage level voltage level Note 1: See Table5-2 in Section5.0 “Reset” for time-outs due to Sleep and MCLR Reset.  2010 Microchip Technology Inc. DS39635C-page 43

PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 44  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 4.0 POWER-MANAGED MODES 4.1.1 CLOCK SOURCES The SCS<1:0> bits allow the selection of one of three PIC18F6310/6410/8310/8410 devices offer a total of clock sources for power-managed modes. They are: seven operating modes for more efficient power management. These modes provide a variety of • The primary clock, as defined by the FOSC<3:0> options for selective power conservation in applications Configuration bits where resources may be limited (i.e., battery-powered • The secondary clock (the Timer1 oscillator) devices). • The internal oscillator block (for RC modes) There are three categories of power-managed modes: 4.1.2 ENTERING POWER-MANAGED • Sleep mode MODES • Idle modes Entering power-managed Run mode, or switching from • Run modes one power-managed mode to another, begins by These categories define which portions of the device loading the OSCCON register. The SCS<1:0> bits are clocked and sometimes, what speed. The Run and select the clock source and determine which Run or Idle modes may use any of the three available clock Idle mode is being used. Changing these bits causes sources (primary, secondary or INTOSC multiplexer); an immediate switch to the new clock source, the Sleep mode does not use a clock source. assuming that it is running. The switch may also be The power-managed modes include several subject to clock transition delays. These are discussed power-saving features. One of these is the clock in Section4.1.3 “Clock Transitions and Status switching feature, offered in other PIC18 devices, Indicators” and subsequent sections. allowing the controller to use the Timer1 oscillator in Entry to the power-managed Idle or Sleep modes is place of the primary oscillator. Also included is the triggered by the execution of a SLEEP instruction. The Sleep mode, offered by all PIC® devices, where all actual mode that results depends on the status of the device clocks are stopped. IDLEN bit. Depending on the current mode and the mode being 4.1 Selecting Power-Managed Modes switched to, a change to a power-managed mode does Selecting a power-managed mode requires deciding if not always require setting all of these bits. Many transi- the CPU is to be clocked or not and selecting a clock tions may be done by changing the oscillator select source. The IDLEN bit controls CPU clocking, while the bits, or changing the IDLEN bit prior to issuing a SLEEP SCS<1:0> bits select a clock source. The individual instruction. If the IDLEN bit is already configured modes, bit settings, clock sources and affected correctly, it may only be necessary to perform a SLEEP modules are summarized in Table4-1. instruction to switch to the desired mode. TABLE 4-1: POWER-MANAGED MODES OSCCON<7,1:0> Bits Module Clocking Mode Available Clock and Oscillator Source IDLEN(1) SCS<1:0> CPU Peripherals Sleep 0 N/A Off Off None – All clocks are disabled. PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC, INTRC(2) This is the normal Full-Power Execution mode SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2) PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC SEC_IDLE 1 01 Off Clocked Secondary – Timer1 Oscillator RC_IDLE 1 1x Off Clocked Internal Oscillator Block(2) Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.  2010 Microchip Technology Inc. DS39635C-page 45

PIC18F6310/6410/8310/8410 4.1.3 CLOCK TRANSITIONS AND Upon resuming normal operation, after waking from STATUS INDICATORS Sleep or Idle, the internal state machines require at least one TCY delay before another SLEEP instruction The length of the transition between clock sources is can be executed. If two back to back SLEEP instruc- the sum of two cycles of the old clock source and three tions will be executed, the process shown in to four cycles of the new clock source. This formula Example4-1 should be used: assumes that the new clock source is stable. Three bits indicate the current clock source and its EXAMPLE 4-1: EXECUTING BACK TO status. They are: BACK SLEEP • OSTS (OSCCON<3>) INSTRUCTIONS • IOFS (OSCCON<2>) SLEEP • T1RUN (T1CON<6>) NOP ;Wait at least 1 Tcy before executing another sleep instruction In general, only one of these bits will be set while in a SLEEP given power-managed mode. When the OSTS bit is set, the primary clock is providing the device clock. When the IOFS bit is set, the INTOSC output is provid- 4.2 Run Modes ing a stable, 8MHz clock source to a divider that In the Run modes, clocks to both the core and actually drives the device clock. When the T1RUN bit is peripherals are active. The difference between these set, the Timer1 oscillator is providing the clock. If none modes is the clock source. of these bits are set, then either the INTRC clock source is clocking the device or the INTOSC source is 4.2.1 PRI_RUN MODE not yet stable. The PRI_RUN mode is the normal full-power execution If the internal oscillator block is configured as the primary mode of the microcontroller. This is also the default clock source by the FOSC<3:0> Configuration bits, then mode upon a device Reset unless Two-Speed Start-up both the OSTS and IOFS bits may be set when in is enabled (see Section24.3 “Two-Speed Start-up” PRI_RUN or PRI_IDLE modes. This indicates that the for details). In this mode, the OSTS bit is set. The IOFS primary clock (INTOSC output) is generating a stable bit may be set if the internal oscillator block is the 8MHz output. Entering another power-managed RC primary clock source (see Section3.7.1 “Oscillator mode at the same frequency would clear the OSTS bit. Control Register”). Note1: Caution should be used when modifying 4.2.2 SEC_RUN MODE a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed The SEC_RUN mode is the compatible mode to the than is supported by the low VDD. “clock switching” feature offered in other PIC18 Improper device operation may result if devices. In this mode, the CPU and peripherals are the VDD/FOSC specifications are violated. clocked from the Timer1 oscillator. This gives users the option of lower power consumption while still using a 2: Executing a SLEEP instruction does not high-accuracy clock source. necessarily place the device into Sleep mode. It acts as the trigger to place the SEC_RUN mode is entered by setting the SCS<1:0> controller into either the Sleep mode or bits to ‘01’. The device clock source is switched to the one of the Idle modes, depending on the Timer1 oscillator (see Figure4-1), the primary setting of the IDLEN bit. oscillator is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. 4.1.4 MULTIPLE SLEEP COMMANDS Note: The Timer1 oscillator should already be The power-managed mode that is invoked with the running prior to entering SEC_RUN SLEEP instruction is determined by the setting of the mode. If the T1OSCEN bit is not set when IDLEN bit at the time the instruction is executed. If the SCS<1:0> bits are set to ‘01’, entry to another SLEEP instruction is executed, the device will SEC_RUN mode will not occur. If the enter the power-managed mode specified by IDLEN at Timer1 oscillator is enabled, but not yet that time. If IDLEN has changed, the device will enter running, peripheral clocks will be delayed the new power-managed mode specified by the new until the oscillator has started; in such setting. situations, initial oscillator operation is far from stable and unpredictable operation may result. DS39635C-page 46  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 On transitions from SEC_RUN mode to PRI_RUN, the When the clock switch is complete, the T1RUN bit is peripherals and CPU continue to be clocked from the cleared, the OSTS bit is set and the primary clock is Timer1 oscillator while the primary clock is started. providing the clock. The IDLEN and SCS bits are not When the primary clock becomes ready, a clock switch affected by the wake-up; the Timer1 oscillator back to the primary clock occurs (see Figure4-2). continues to run. FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI 1 2 3 n-1 n Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 FIGURE 4-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI OSC1 TOST(1) TPLL(1) PLL Clock 1 2 Output n-1 n Clock Transition CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 Counter SCS<1:0> bits Changed OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale.  2010 Microchip Technology Inc. DS39635C-page 47

PIC18F6310/6410/8310/8410 4.2.3 RC_RUN MODE If the IRCF bits and the INTSRC bit are all clear, the INTOSC output is not enabled and the IOFS bit will In RC_RUN mode, the CPU and peripherals are remain clear; there will be no indication of the current clocked from the internal oscillator block using the clock source. The INTRC source is providing the INTOSC multiplexer and the primary clock is shut device clocks. down. When using the INTRC source, this mode provides the best power conservation of all the Run If the IRCF bits are changed from all clear (thus, modes, while still executing code. It works well for user enabling the INTOSC output), or if INTSRC is set, the applications which are not highly timing-sensitive, or do IOFS bit becomes set after the INTOSC output not require high-speed clocks at all times. becomes stable. Clocks to the device continue while If the primary clock source is the internal oscillator the INTOSC source stabilizes after an interval of block (either INTRC or INTOSC), there are no distin- TIOBST. guishable differences between PRI_RUN and If the IRCF bits were previously at a non-zero value, or RC_RUN modes during execution. However, a clock if INTSRC was set before setting SCS1 and the switch delay will occur during entry to and exit from INTOSC source was already stable, the IOFS bit will RC_RUN mode. Therefore, if the primary clock source remain set. is the internal oscillator block, the use of RC_RUN mode is not recommended. On transitions from RC_RUN mode to PRI_RUN, the device continues to be clocked from the INTOSC This mode is entered by setting the SCS1 bit to ‘1’. multiplexer while the primary clock is started. When the Although it is ignored, it is recommended that the SCS0 primary clock becomes ready, a clock switch to the bit also be cleared; this is to maintain software primary clock occurs (see Figure4-4). When the clock compatibility with future devices. When the clock switch is complete, the IOFS bit is cleared, the OSTS source is switched to the INTOSC multiplexer (see bit is set and the primary clock is providing the device Figure4-3), the primary oscillator is shut down and the clock. The IDLEN and SCS bits are not affected by the OSTS bit is cleared.The IRCF bits may be modified at switch. The INTRC source will continue to run if either any time to immediately change the clock speed. the WDT or the Fail-Safe Clock Monitor is enabled. Note: Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated. DS39635C-page 48  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 4-3: TRANSITION TIMING TO RC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTRC 1 2 3 n-1 n Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 FIGURE 4-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 Counter SCS<1:0> bits Changed OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale.  2010 Microchip Technology Inc. DS39635C-page 49

PIC18F6310/6410/8310/8410 4.3 Sleep Mode 4.4 Idle Modes The power-managed Sleep mode in the The Idle modes allow the controller’s CPU to be PIC18F6310/6410/8310/8410 devices is identical to selectively shut down while the peripherals continue to the legacy Sleep mode offered in all other PIC® operate. Selecting a particular Idle mode allows users devices. It is entered by clearing the IDLEN bit (the to further manage power consumption. default state on device Reset) and executing the If the IDLEN bit is set to a ‘1’ when a SLEEP instruction SLEEP instruction. This shuts down the selected is executed, the peripherals will be clocked from the oscillator (see Figure4-5). All clock source status bits clock source selected using the SCS<1:0> bits; are cleared. however, the CPU will not be clocked. The clock source Entering the Sleep mode from any other mode does not status bits are not affected. Setting IDLEN and execut- require a clock switch. This is because no clocks are ing SLEEP provides a quick method of switching from a needed once the controller has entered Sleep. If the given Run mode to its corresponding Idle mode. WDT is selected, the INTRC source will continue to If the WDT is selected, the INTRC source will continue operate. If the Timer1 oscillator is enabled, it will also to operate. If the Timer1 oscillator is enabled, it will also continue to run. continue to run. When a wake event occurs in Sleep mode (by interrupt, Since the CPU is not executing instructions, the only Reset or WDT time-out), the device will not be clocked exits from any of the Idle modes are by interrupt, WDT until the primary clock source becomes ready (see time-out or a Reset. When a wake event occurs, CPU Figure4-6), or it will be clocked from the internal execution is delayed by an interval of TCSD oscillator block if either the Two-Speed Start-up or the (Parameter38, Table27-12), while it becomes ready to Fail-Safe Clock Monitor are enabled (see Section24.0 execute code. When the CPU begins executing code, “Special Features of the CPU”). In either case, the it resumes with the same clock source for the current OSTS bit is set when the primary clock is providing the Idle mode. For example, when waking from RC_IDLE device clocks. The IDLEN and SCS bits are not mode, the internal oscillator block will clock the CPU affected by the wake-up. and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS<1:0> bits. FIGURE 4-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC PC + 2 FIGURE 4-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(1) TPLL(1) PLL Clock Output CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 PC + 6 Counter Wake Event OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. DS39635C-page 50  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 4.4.1 PRI_IDLE MODE When a wake event occurs, the CPU is clocked from the primary clock source. A delay of interval, TCSD, is This mode is unique among the three low-power Idle required between the wake event and when code modes, in that it does not disable the primary device execution starts. This is required to allow the CPU to clock. For timing-sensitive applications, this allows for become ready to execute instructions. After the the fastest resumption of device operation with its more wake-up, the OSTS bit remains set. The IDLEN and accurate primary clock source, since the clock source SCS bits are not affected by the wake-up (see does not have to “warm up” or transition from another Figure4-8). oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruc- tion. If the device is in another Run mode, set IDLEN first, then clear the SCS bits and execute SLEEP. Although the CPU is disabled, the peripherals continue to be clocked from the primary clock source specified by the FOSC<3:0> Configuration bits. The OSTS bit remains set (see Figure4-7). FIGURE 4-7: TRANSITION TIMING FOR ENTRY TO PRI_IDLE MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Program PC PC + 2 Counter FIGURE 4-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 TCSD CPU Clock Peripheral Clock Program PC Counter Wake Event  2010 Microchip Technology Inc. DS39635C-page 51

PIC18F6310/6410/8310/8410 4.4.2 SEC_IDLE MODE 4.4.3 RC_IDLE MODE In SEC_IDLE mode, the CPU is disabled, but the In RC_IDLE mode, the CPU is disabled, but the periph- peripherals continue to be clocked from the Timer1 erals continue to be clocked from the internal oscillator oscillator. This mode is entered from SEC_RUN by set- block using the INTOSC multiplexer. This mode allows ting the IDLEN bit and executing a SLEEP instruction. If for controllable power conservation during Idle periods. the device is in another Run mode, set IDLEN first, then From RC_RUN, this mode is entered by setting the set SCS<1:0> to ‘01’ and execute SLEEP. When the IDLEN bit and executing a SLEEP instruction. If the clock source is switched to the Timer1 oscillator, the device is in another Run mode, first set IDLEN, then set primary oscillator is shut down, the OSTS bit is cleared the SCS1 bit and execute SLEEP. Although its value is and the T1RUN bit is set. ignored, it is recommended that SCS0 also be cleared; When a wake event occurs, the peripherals continue to this is to maintain software compatibility with future be clocked from the Timer1 oscillator. After an interval devices. The INTOSC multiplexer may be used to of TCSD following the wake event, the CPU begins exe- select a higher clock frequency by modifying the IRCF cuting code being clocked by the Timer1 oscillator. The bits before executing the SLEEP instruction. When the IDLEN and SCS bits are not affected by the wake-up; clock source is switched to the INTOSC multiplexer, the the Timer1 oscillator continues to run (see Figure4-8). primary oscillator is shut down and the OSTS bit is cleared. Note: The Timer1 oscillator should already be If the IRCF bits are set to any non-zero value, or the running prior to entering SEC_IDLE INTSRC bit is set, the INTOSC output is enabled. The mode. If the T1OSCEN bit is not set when IOFS bit becomes set after the INTOSC output the SLEEP instruction is executed, the becomes stable, after an interval of TIOBST SLEEP instruction will be ignored and (Parameter39, Table27-12). Clocks to the peripherals entry to SEC_IDLE mode will not occur. If continue while the INTOSC source stabilizes. If the the Timer1 oscillator is enabled, but not IRCF bits were previously at a non-zero value, or yet running, peripheral clocks will be INTSRC was set before the SLEEP instruction was delayed until the oscillator has started. In executed and the INTOSC source was already stable, such situations, initial oscillator operation the IOFS bit will remain set. If the IRCF bits and is far from stable and unpredictable INTSRC are all clear, the INTOSC output will not be operation may result. enabled; the IOFS bit will remain clear and there will be no indication of the current clock source. When a wake event occurs, the peripherals continue to be clocked from the INTOSC multiplexer. After a delay of TCSD following the wake event, the CPU begins exe- cuting code, being clocked by the INTOSC multiplexer. The IDLEN and SCS bits are not affected by the wake-up. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. DS39635C-page 52  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 4.5 Exiting Idle and Sleep Modes 4.5.3 EXIT BY RESET An exit from Sleep mode or any of the Idle modes is Normally, the device is held in Reset by the Oscillator triggered by an interrupt, a Reset or a WDT time-out. Start-up Timer (OST) until the primary clock becomes This section discusses the triggers that cause exits ready. At that time, the OSTS bit is set and the device from power-managed modes. The clocking subsystem begins executing code. If the internal oscillator block is actions are discussed in each of the power-managed the new clock source, the IOFS bit is set instead. modes (see Section4.2 “Run Modes” through The exit delay time from Reset to the start of code Section4.4 “Idle Modes”). execution depends on both the clock sources before and after the wake-up and the type of oscillator if the 4.5.1 EXIT BY INTERRUPT new clock source is the primary clock. Exit delays are Any of the available interrupt sources can cause the summarized in Table4-2. device to exit from an Idle or Sleep mode to a Run Code execution can begin before the primary clock mode. To enable this functionality, an interrupt source becomes ready. If either the Two-Speed Start-up (see must be enabled by setting its enable bit in one of the Section24.3 “Two-Speed Start-up”) or Fail-Safe INTCON or PIE registers. The exit sequence is initiated Clock Monitor (see Section24.4 “Fail-Safe Clock when the corresponding interrupt flag bit is set. Monitor”) is enabled, the device may begin execution On all exits from Idle or Sleep modes by interrupt, code as soon as the Reset source has cleared. Execution is execution branches to the interrupt vector if the clocked by the INTOSC multiplexer driven by the GIE/GIEH bit (INTCON<7>) is set. Otherwise, code internal oscillator block. Execution is clocked by the execution continues or resumes without branching internal oscillator block until either the primary clock (see Section10.0 “Interrupts”). becomes ready, or a power-managed mode is entered before the primary clock becomes ready; the primary A fixed delay of interval, TCSD, following the wake clock is then shut down. event, is required when leaving Sleep and Idle modes. This delay is required for the CPU to prepare for execu- 4.5.4 EXIT WITHOUT AN OSCILLATOR tion. Instruction execution resumes on the first clock START-UP DELAY cycle following this delay. Certain exits from power-managed modes do not 4.5.2 EXIT BY WDT TIME-OUT invoke the OST at all. There are two cases: A WDT time-out will cause different actions depending • PRI_IDLE mode, where the primary clock source on which power-managed mode the device is in when is not stopped; and the time-out occurs. • the primary clock source is not any of the LP, XT, HS or HSPLL modes. If the device is not executing code (all Idle modes and Sleep mode), the time-out will result in an exit from the In these instances, the primary clock source either power-managed mode (see Section4.2 “Run does not require an oscillator start-up delay since it is Modes” and Section4.3 “Sleep Mode”). If the device already running (PRI_IDLE), or normally does not is executing code (all Run modes), the time-out will require an oscillator start-up delay (RC, EC and INTIO result in a WDT Reset (see Section24.2 “Watchdog Oscillator modes). However, a fixed delay of interval, Timer (WDT)”). TCSD, following the wake event, is still required when leaving Sleep and Idle modes to allow the CPU to The WDT timer and postscaler are cleared by execut- prepare for execution. Instruction execution resumes ing a SLEEP or CLRWDT instruction, losing a currently on the first clock cycle following this delay. selected clock source (if the Fail-Safe Clock Monitor is enabled) and modifying the IRCF bits in the OSCCON register if the internal oscillator block is the device clock source.  2010 Microchip Technology Inc. DS39635C-page 53

PIC18F6310/6410/8310/8410 TABLE 4-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Clock Source Clock Source Clock Ready Status Bit Exit Delay Before Wake-up After Wake-up (OSCCON) LP, XT, HS OSTS Primary Device Clock HSPLL TCSD(2) (PRI_IDLE mode) EC, RC, INTRC(1) — INTOSC(3) IOFS LP, XT, HS TOST(4) OSTS T1OSC or INTRC(1) HSPLL TOST + trc(4) EC, RC, INTRC(1) TCSD(2) — INTOSC(2) TIOBST(5) IOFS LP, XT, HS TOST(5) OSTS INTOSC(3) HSPLL TOST + trc(4) EC, RC, INTRC(1) TCSD(2) — INTOSC(2) None IOFS LP, XT, HS TOST(4) OSTS None HSPLL TOST + trc(4) (Sleep mode) EC, RC, INTRC(1) TCSD(2) — INTOSC(2) TIOBST(5) IOFS Note 1: In this instance, refers specifically to the 31kHz INTRC clock source. 2: TCSD (Parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other required delays (see Section4.4 “Idle Modes”). 3: Includes both the INTOSC 8MHz source and postscaler derived frequencies. 4: TOST is the Oscillator Start-up Timer (Parameter 32). trc is the PLL Lock-out Timer (Parameter F12); it is also designated as TPLL. 5: Execution continues during TIOBST (Parameter 39), the INTOSC stabilization period. DS39635C-page 54  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 5.0 RESET 5.1 RCON Register The PIC18F6310/6410/8310/8410 devices differentiate Device Reset events are tracked through the RCON between various kinds of Reset: register (Register5-1). The lower five bits of the register indicate that a specific Reset event has a) Power-on Reset (POR) occurred. In most cases, these bits can only be set by b) MCLR Reset during normal operation the event and must be cleared by the application after c) MCLR Reset during power-managed modes the event. The state of these flag bits, taken together, d) Watchdog Timer (WDT) Reset (during can be read to indicate the type of Reset that just execution) occurred. This is described in more detail in e) Programmable Brown-out Reset (BOR) Section5.6 “Reset State of Registers”. f) RESET Instruction The RCON register also has control bits for setting g) Stack Full Reset interrupt priority (IPEN) and software control of the BOR (SBOREN). Interrupt priority is discussed in h) Stack Underflow Reset Section10.0 “Interrupts”. BOR is covered in This section discusses Resets generated by MCLR, Section5.4 “Brown-out Reset (BOR)”. POR and BOR and covers the operation of the various start-up timers. Stack Reset events are covered in Section6.1.3.4 “Stack Full and Underflow Resets”. WDT Resets are covered in Section24.2 “Watchdog Timer (WDT)”. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure5-1. FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Stack Full/Underflow Reset Pointer External Reset MCLRE MCLR ( )_IDLE Sleep WDT Time-out VDD Rise POR Pulse Detect VDD Brown-out Reset BOREN S OST/PWRT OST 1024 Cycles Chip_Reset 10-Bit Ripple Counter R Q OSC1 32 s PWRT 65.5 ms INTRC 11-Bit Ripple Counter Enable PWRT Enable OST(1) Note 1: See Table5-2 for time-out situations.  2010 Microchip Technology Inc. DS39635C-page 55

PIC18F6310/6410/8310/8410 REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0(1) U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN SBOREN — RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit(1) If BOREN<1:0> = 01: 1 = BOR is enabled 0 = BOR is disabled If BOREN<1:0> = 00, 10 or 11: Bit is disabled and read as ‘0’. bit 5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Timer Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-Down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’. Note1: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. 2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39635C-page 56  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 5.2 Master Clear (MCLR) POR events are captured by the POR bit (RCON<1>). The state of the bit is set to ‘0’ whenever a POR occurs; The MCLR pin provides a method for triggering a hard it does not change for any other Reset event. POR is external Reset of the device. A Reset is generated by not reset to ‘1’ by any hardware event. To capture holding the pin low. PIC18 Extended MCU devices multiple events, the user manually resets the bit to ‘1’ have a noise filter in the MCLR Reset path which in software following any POR. detects and ignores small pulses. The MCLR pin is not driven low by any internal Resets, FIGURE 5-2: EXTERNAL POWER-ON including the WDT. RESET CIRCUIT (FOR In PIC18F6310/6410/8310/8410 devices, the MCLR SLOW VDD POWER-UP) input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section11.7 “PORTG, TRISG and LATG VDD VDD Registers” for more information. D(1) R(2) 5.3 Power-on Reset (POR) R1(3) MCLR A Power-on Reset pulse is generated on-chip C PIC18FXXXX whenever VDD rises above a certain threshold. This allows the device to start in the initialized state when VDD is adequate for operation. Note 1: External Power-on Reset circuit is required To take advantage of the POR circuitry, tie the MCLR only if the VDD power-up slope is too slow. pin through a resistor (1k to 10k) to VDD. This will The diode, D, helps discharge the capacitor eliminate external RC components usually needed to quickly when VDD powers down. create a Power-on Reset delay. A minimum rise rate for 2: R < 40k is recommended to make sure that VDD is specified (Parameter D004). For a slow rise the voltage drop across R does not violate time, see Figure5-2. the device’s electrical specification. When the device starts normal operation (i.e., exits the 3: R1  1 k will limit any current flowing into Reset condition), device operating parameters MCLR from external capacitor, C, in the event (voltage, frequency, temperature, etc.) must be met to of MCLR/VPP pin breakdown, due to ensure operation. If these conditions are not met, the Electrostatic Discharge (ESD) or Electrical device must be held in Reset until the operating Overstress (EOS). conditions are met.  2010 Microchip Technology Inc. DS39635C-page 57

PIC18F6310/6410/8310/8410 5.4 Brown-out Reset (BOR) Placing the BOR under software control gives the user the additional flexibility of tailoring the application to its PIC18F6310/6410/8310/8410 devices implement a environment without having to reprogram the device to BOR circuit that provides the user with a number of change the BOR configuration. It also allows the user configuration and power-saving options. The BOR is to tailor device power consumption in software by controlled by the BORV<1:0> and BOREN<1:0> eliminating the incremental current that the BOR Configuration bits. There are a total of four BOR consumes. While the BOR current is typically very configurations, which are summarized in Table5-1. small, it may have some impact in low-power The BOR threshold is set by the BORV<1:0> bits. If BOR applications. is enabled (any values of BOREN<1:0> except ‘00’), Note: Even when BOR is under software con- any drop of VDD below VBOR (ParameterD005) for trol, the Brown-out Reset voltage level is greater than TBOR (Parameter35) will reset the device. still set by the BORV<1:0> Configuration A Reset may or may not occur if VDD falls below VBOR bits. It cannot be changed in software. for less than TBOR. The chip will remain in Brown-out Reset until VDD rises above VBOR. 5.4.2 DETECTING BOR If the Power-up Timer is enabled, it will be invoked after When Brown-out Reset is enabled, the BOR bit always VDD rises above VBOR; it then will keep the chip in resets to ‘0’ on any BOR or POR event. This makes it Reset for an additional time delay, TPWRT difficult to determine if a Brown-out Reset event has (Parameter33). If VDD drops below VBOR while the occurred just by reading the state of BOR alone. A Power-up Timer is running, the chip will go back into a more reliable method is to simultaneously check the Brown-out Reset and the Power-up Timer will be state of both POR and BOR. This assumes that the initialized. Once VDD rises above VBOR, the Power-up POR bit is reset to ‘1’ in software immediately after any Timer will execute the additional time delay. POR event. If BOR is ‘0’ while POR is ‘1’, it can be BOR and the Power-up Timer (PWRT) are reliably assumed that a BOR event has occurred. independently configured. Enabling the Brown-out Reset does not automatically enable the PWRT. 5.4.3 DISABLING BOR IN SLEEP MODE When BOREN<1:0> = 10, the BOR remains under 5.4.1 SOFTWARE ENABLED BOR hardware control and operates as previously When BOREN<1:0> = 01, the BOR can be enabled or described. Whenever the device enters Sleep mode, disabled by the user in software. This is done with the however, the BOR is automatically disabled. When the control bit, SBOREN (RCON<6>). Setting SBOREN device returns to any other operating mode, BOR is enables the BOR to function as previously described. automatically re-enabled. Clearing SBOREN disables the BOR entirely. The This mode allows for applications to recover from SBOREN bit operates only in this mode; otherwise, it is brown-out situations, while actively executing code, read as ‘0’. when the device requires BOR protection the most. At the same time, it saves additional power in Sleep mode by eliminating the small incremental BOR current. TABLE 5-1: BOR CONFIGURATIONS BOR Configuration Status of SBOREN BOR Operation BOREN1 BOREN0 (RCON<6>) 0 0 Unavailable BOR is disabled; must be enabled by reprogramming the Configuration bits. 0 1 Available BOR is enabled in software; operation controlled by SBOREN. 1 0 Unavailable BOR is enabled in hardware and active during the Run and Idle modes; disabled during Sleep mode. 1 1 Unavailable BOR is enabled in hardware; must be disabled by reprogramming the Configuration bits. DS39635C-page 58  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 5.5 Device Reset Timers 5.5.3 PLL LOCK TIME-OUT PIC18F6310/6410/8310/8410 devices incorporate With the PLL enabled in its PLL mode, the time-out three separate on-chip timers that help regulate the sequence following a Power-on Reset is slightly Power-on Reset process. Their main function is to different from other oscillator modes. A separate timer ensure that the device clock is stable before code is is used to provide a fixed time-out that is sufficient for executed. These timers are: the PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows • Power-up Timer (PWRT) the oscillator start-up time-out. • Oscillator Start-up Timer (OST) • PLL Lock Time-out 5.5.4 TIME-OUT SEQUENCE On power-up, the time-out sequence is as follows: 5.5.1 POWER-UP TIMER (PWRT) 1. After the POR pulse has cleared, PWRT The Power-up Timer (PWRT) of the time-out is invoked (if enabled). PIC18F6310/6410/8310/8410 devices is an 11-bit 2. Then, the OST is activated. counter which uses the INTRC source as the clock input. This yields an approximate time interval of The total time-out will vary based on oscillator 2048x32s=65.6ms. While the PWRT is counting, configuration and the status of the PWRT. Figure5-3, the device is held in Reset. Figure5-4, Figure5-5, Figure5-6 and Figure5-7 all depict time-out sequences on power-up, with the The power-up time delay depends on the INTRC clock Power-up Timer enabled and the device operating in and will vary from chip to chip due to temperature and HS Oscillator mode. Figures5-3 through5-6 also apply process variation. See DC Parameter33 for details. to devices operating in XT or LP modes. For devices in The PWRT is enabled by clearing the PWRTEN RC mode and with the PWRT disabled, on the other Configuration bit. hand, there will be no time-out at all. 5.5.2 OSCILLATOR START-UP Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire. TIMER (OST) Bringing MCLR high will begin execution immediately The Oscillator Start-up Timer (OST) provides a (Figure5-5). This is useful for testing purposes or to 1024oscillator cycle (from OSC1 input) delay after the synchronize more than one PIC18FXXXX device PWRT delay is over (Parameter 33). This ensures that operating in parallel. the crystal oscillator or resonator has started and is stabilized. The OST time-out is invoked only for XT, LP, HS and HSPLL modes, and only on Power-on Reset or on exit from most power-managed modes. TABLE 5-2: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) and Brown-out Oscillator Exit from Configuration Power-Managed Mode PWRTEN = 0 PWRTEN = 1 HSPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC EC, ECIO 66 ms(1) — — RC, RCIO 66 ms(1) — — INTIO1, INTIO2 66 ms(1) — — Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2: 2 ms is the nominal time required for the PLL to lock.  2010 Microchip Technology Inc. DS39635C-page 59

PIC18F6310/6410/8310/8410 FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS39635C-page 60  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL  2 ms max. First three stages of the PWRT timer.  2010 Microchip Technology Inc. DS39635C-page 61

PIC18F6310/6410/8310/8410 5.6 Reset State of Registers Table5-4 describes the Reset states for all of the Special Function Registers. These are categorized by Most registers are unaffected by a Reset. Their status Power-on and Brown-out Resets, Master Clear and is unknown on POR and unchanged by all other WDT Resets and WDT wake-ups. Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table5-3. These bits are used in software to determine the nature of the Reset. TABLE 5-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER RCON Register STKPTR Register Program Condition Counter SBOREN RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 1 1 1 1 0 0 0 0 RESET Instruction 0000h u(2) 0 u u u u u u Brown-out Reset 0000h u(2) 1 1 1 u 0 u u MCLR Reset during 0000h u(2) u 1 u u u u u Power-Managed Run Modes MCLR Reset during 0000h u(2) u 1 0 u u u u Power-Managed Idle Modes and Sleep Mode WDT Time-out during 0000h u(2) u 0 u u u u u Full-Power or Power-Managed Run Modes MCLR Reset during Full-Power 0000h u(2) u u u u u u u Execution Stack Full Reset (STVREN = 1) 0000h u(2) u u u u u 1 u Stack Underflow Reset 0000h u(2) u u u u u u 1 (STVREN = 1) Stack Underflow Error (not an 0000h u(2) u u u u u u 1 actual Reset, STVREN = 0) WDT Time-out during PC + 2 u(2) u 0 0 u u u u Power-Managed Idle or Sleep Modes Interrupt Exit from PC + 2(1) u(2) u u 0 u u u u Power-Managed Modes Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (008h or 0018h). 2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled (BOREN<1:0> Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is ‘0’. DS39635C-page 62  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS MCLR Resets Applicable Power-on Reset, WDT Reset Wake-up via WDT Register Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets TOSU 6X10 8X10 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 6X10 8X10 0000 0000 0000 0000 uuuu uuuu(3) TOSL 6X10 8X10 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 6X10 8X10 uu-0 0000 00-0 0000 uu-u uuuu(3) PCLATU 6X10 8X10 ---0 0000 ---0 0000 ---u uuuu PCLATH 6X10 8X10 0000 0000 0000 0000 uuuu uuuu PCL 6X10 8X10 0000 0000 0000 0000 PC + 2(2) TBLPTRU 6X10 8X10 --00 0000 --00 0000 --uu uuuu TBLPTRH 6X10 8X10 0000 0000 0000 0000 uuuu uuuu TBLPTRL 6X10 8X10 0000 0000 0000 0000 uuuu uuuu TABLAT 6X10 8X10 0000 0000 0000 0000 uuuu uuuu PRODH 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu PRODL 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu INTCON 6X10 8X10 0000 000x 0000 000u uuuu uuuu(1) INTCON2 6X10 8X10 1111 1111 1111 1111 uuuu uuuu(1) INTCON3 6X10 8X10 1100 0000 1100 0000 uuuu uuuu(1) INDF0 6X10 8X10 N/A N/A N/A POSTINC0 6X10 8X10 N/A N/A N/A POSTDEC0 6X10 8X10 N/A N/A N/A PREINC0 6X10 8X10 N/A N/A N/A PLUSW0 6X10 8X10 N/A N/A N/A FSR0H 6X10 8X10 ---- xxxx ---- uuuu ---- uuuu FSR0L 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu WREG 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 6X10 8X10 N/A N/A N/A POSTINC1 6X10 8X10 N/A N/A N/A POSTDEC1 6X10 8X10 N/A N/A N/A PREINC1 6X10 8X10 N/A N/A N/A PLUSW1 6X10 8X10 N/A N/A N/A FSR1H 6X10 8X10 ---- xxxx ---- uuuu ---- uuuu FSR1L 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu BSR 6X10 8X10 ---- 0000 ---- 0000 ---- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific condition. 5: Bits, 6 and 7 of PORTA, LATA and TRISA, are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’.  2010 Microchip Technology Inc. DS39635C-page 63

PIC18F6310/6410/8310/8410 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Applicable Power-on Reset, WDT Reset Wake-up via WDT Register Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets INDF2 6X10 8X10 N/A N/A N/A POSTINC2 6X10 8X10 N/A N/A N/A POSTDEC2 6X10 8X10 N/A N/A N/A PREINC2 6X10 8X10 N/A N/A N/A PLUSW2 6X10 8X10 N/A N/A N/A FSR2H 6X10 8X10 ---- xxxx ---- uuuu ---- uuuu FSR2L 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu STATUS 6X10 8X10 ---x xxxx ---u uuuu ---u uuuu TMR0H 6X10 8X10 0000 0000 0000 0000 uuuu uuuu TMR0L 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu T0CON 6X10 8X10 1111 1111 1111 1111 uuuu uuuu OSCCON 6X10 8X10 0100 q000 0100 00q0 uuuu uuqu HLVDCON 6X10 8X10 0-00 0101 0-00 0101 u-uu uuuu WDTCON 6X10 8X10 ---- ---0 ---- ---0 ---- ---u RCON(4) 6X10 8X10 0q-1 11q0 0q-q qquu uq-u qquu TMR1H 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L 6X10 8X10 0000 0000 uuuu uuuu uuuu uuuu T1CON 6X10 8X10 0000 0000 u0uu uuuu uuuu uuuu TMR2 6X10 8X10 1111 1111 0000 0000 uuuu uuuu PR2 6X10 8X10 -000 0000 -111 1111 -111 1111 T2CON 6X10 8X10 -000 0000 -000 0000 -uuu uuuu SSPBUF 6X10 8X10 0000 0000 uuuu uuuu uuuu uuuu SSPADD 6X10 8X10 0000 0000 0000 0000 uuuu uuuu SSPSTAT 6X10 8X10 0000 0000 0000 0000 uuuu uuuu SSPCON1 6X10 8X10 0000 0000 0000 0000 uuuu uuuu SSPCON2 6X10 8X10 0000 0000 0000 0000 uuuu uuuu ADRESH 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL 6X10 8X10 0000 0000 uuuu uuuu uuuu uuuu ADCON0 6X10 8X10 --00 0000 --00 0000 --uu uuuu ADCON1 6X10 8X10 --00 qqqq --00 0000 --uu uuuu ADCON2 6X10 8X10 0-00 0000 0-00 0000 u-uu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific condition. 5: Bits, 6 and 7 of PORTA, LATA and TRISA, are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. DS39635C-page 64  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Applicable Power-on Reset, WDT Reset Wake-up via WDT Register Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets CCPR1H 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 6X10 8X10 --00 0000 --00 0000 --uu uuuu CCPR2H 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L 6X10 8X10 0000 0000 uuuu uuuu uuuu uuuu CCP2CON 6X10 8X10 --00 0000 --00 0000 --uu uuuu CCPR3H 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu CCPR3L 6X10 8X10 0000 0000 uuuu uuuu uuuu uuuu CCP3CON 6X10 8X10 --00 0000 --00 0000 --uu uuuu CVRCON 6X10 8X10 0000 0000 0000 0000 uuuu uuuu CMCON 6X10 8X10 0000 0111 0000 0111 uuuu uuuu TMR3H 6X10 8X10 0000 0000 uuuu uuuu uuuu uuuu TMR3L 6X10 8X10 0000 0000 uuuu uuuu uuuu uuuu T3CON 6X10 8X10 0000 0000 uuuu uuuu uuuu uuuu PSPCON 6X10 8X10 0000 ---- 0000 ---- uuuu ---- SPBRG1 6X10 8X10 0000 0000 0000 0000 uuuu uuuu RCREG1 6X10 8X10 0000 0000 0000 0000 uuuu uuuu TXREG1 6X10 8X10 xxxx xxxx 0000 0000 uuuu uuuu TXSTA1 6X10 8X10 0000 0010 0000 0010 uuuu uuuu RCSTA1 6X10 8X10 0000 000x 0000 000x uuuu uuuu IPR3 6X10 8X10 --11 ---1 --11 ---1 --uu ---u PIR3 6X10 8X10 --00 ---0 --00 ---0 --uu ---u(1) PIE3 6X10 8X10 --00 ---0 --00 ---0 --uu ---u IPR2 6X10 8X10 11-- 1111 11-- 1111 uu-- uuuu PIR2 6X10 8X10 00-- 0000 00-- 0000 uu-- uuuu(1) PIE2 6X10 8X10 00-- 0000 00-- 0000 uu-- uuuu IPR1 6X10 8X10 1111 1111 1111 1111 uuuu uuuu PIR1 6X10 8X10 0000 0000 0000 0000 uuuu uuuu(1) PIE1 6X10 8X10 0000 0000 0000 0000 uuuu uuuu MEMCON 6X10 8X10 0-00 --00 0-00 --00 u-uu --uu OSCTUNE 6X10 8X10 00-0 0000 00-0 0000 uu-u uuuu TRISJ 6X10 8X10 1111 1111 1111 1111 uuuu uuuu TRISH 6X10 8X10 1111 1111 1111 1111 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific condition. 5: Bits, 6 and 7 of PORTA, LATA and TRISA, are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’.  2010 Microchip Technology Inc. DS39635C-page 65

PIC18F6310/6410/8310/8410 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets Applicable Power-on Reset, WDT Reset Wake-up via WDT Register Devices Brown-out Reset RESET Instruction or Interrupt Stack Resets TRISG 6X10 8X10 ---1 1111 ---1 1111 ---u uuuu TRISF 6X10 8X10 1111 1111 1111 1111 uuuu uuuu TRISE 6X10 8X10 1111 1111 1111 1111 uuuu uuuu TRISD 6X10 8X10 1111 1111 1111 1111 uuuu uuuu TRISC 6X10 8X10 1111 1111 1111 1111 uuuu uuuu TRISB 6X10 8X10 1111 1111 1111 1111 uuuu uuuu TRISA(5) 6X10 8X10 1111 1111(5) 1111 1111(5) uuuu uuuu(5) LATJ 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu LATH 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu LATG 6X10 8X10 ---x xxxx ---u uuuu ---u uuuu LATF 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu LATE 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu LATD 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu LATC 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu LATB 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu LATA(5) 6X10 8X10 xxxx xxxx(5) uuuu uuuu(5) uuuu uuuu(5) PORTJ 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu PORTH 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu PORTG 6X10 8X10 --xx xxxx --uu uuuu --uu uuuu PORTF 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu PORTE 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu PORTD 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu PORTC 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu PORTB 6X10 8X10 xxxx xxxx uuuu uuuu uuuu uuuu PORTA(5) 6X10 8X10 xx0x 0000(5) uu0u 0000(5) uuuu uuuu(5) SPBRGH1 6X10 8X10 0000 0000 0000 0000 uuuu uuuu BAUDCON1 6X10 8X10 0100 0-00 0100 0-00 uuuu u-uu SPBRG2 6X10 8X10 0000 0000 0000 0000 uuuu uuuu RCREG2 6X10 8X10 0000 0000 0000 0000 uuuu uuuu TXREG2 6X10 8X10 xxxx xxxx 0000 0000 uuuu uuuu TXSTA2 6X10 8X10 0000 -010 0000 -010 uuuu -uuu RCSTA2 6X10 8X10 0000 000x 0000 000x uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table5-3 for Reset value for specific condition. 5: Bits, 6 and 7 of PORTA, LATA and TRISA, are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. DS39635C-page 66  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 6.0 MEMORY ORGANIZATION 6.1 Program Memory Organization There are two types of memory in PIC18 Flash PIC18 microcontrollers implement a 21-bit program microcontroller devices: counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between • Program Memory the upper boundary of the physically implemented • Data RAM memory and the 2-Mbyte address will return all ‘0’s (a As Harvard architecture devices, the data and program NOP instruction). memories use separate busses; this allows for The PIC18F6310 and PIC18F8310 each have 8Kbytes concurrent access of the two memory spaces. of Flash memory and can store up to 4,096 single-word Additional detailed information on the operation of the instructions. The PIC18F6410 and PIC18F8410 each Flash program memory is provided in Section7.0 have 16Kbytes of Flash memory and can store up to “Program Memory”. 8,192 single-word instructions. PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. The program memory maps for the PIC18F6310/6410/8310/8410 devices are shown in Figure6-1. FIGURE 6-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F6310/6410/8310/8410 DEVICES PIC18FX310 PIC18FX410 PC<20:0> PC<20:0> CALL,RCALL,RETURN 21 CALL,RCALL,RETURN 21 RETFIE,RETLW RETFIE,RETLW Stack Level 1 Stack Level 1       Stack Level 31 Stack Level 31 Reset Vector 0000h Reset Vector 0000h High-Priority Interrupt Vector 0008h High-Priority Interrupt Vector 0008h Low-Priority Interrupt Vector 0018h Low-Priority Interrupt Vector 0018h On-Chip Program Memory On-Chip 1FFFh Program Memory 2000h e e c c a a p p S S y y or or m 3FFFh m e e M 4000h M er er s s U U Read ‘0’ Read ‘0’ 1FFFFFh 1FFFFFh  2010 Microchip Technology Inc. DS39635C-page 67

PIC18F6310/6410/8310/8410 6.1.1 PIC18F8310/8410 PROGRAM • The Extended Microcontroller Mode allows MEMORY MODES access to both internal and external program memories as a single block. The device can In addition to available on-chip Flash program memory, access its entire on-chip Flash memory; above 80-pin devices in this family can also address up to this, the device accesses external program 2Mbytes of external program memory through an memory up to the 2-Mbyte program space limit. external memory interface. There are four distinct As with Boot Block mode, execution automatically operating modes available to the controllers: switches between the two memories as required. • Microprocessor (MP) • The Microprocessor Mode permits access only • Microprocessor with Boot Block (MPBB) to external program memory; the contents of the • Extended Microcontroller (EMC) on-chip Flash memory is ignored. The 21-bit • Microcontroller (MC) program counter permits access to the entire 2-Mbyte linear program memory space. The program memory mode is determined by setting • The Microprocessor with Boot Block Mode the two Least Significant bits of the CONFIG3L Config- accesses on-chip Flash memory from addresses uration byte, as shown in Register6-1. (See also 000000h to 0007FFh. Above this, external program Section24.1 “Configuration Bits” for additional memory is accessed all the way up to the 2-Mbyte details on the device Configuration bits.) limit. Program execution automatically switches The program memory modes operate as follows: between the two memories as required. • The Microcontroller Mode accesses only on-chip In all modes, the microcontroller has complete access Flash memory. Attempts to read above the physical to data RAM. limit of the on-chip Flash (3FFFh) causes a read of Figure6-2 compares the memory maps of the different all ‘0’s (a NOP instruction). The Microcontroller mode program memory modes. The differences between is also the only operating mode available to on-chip and external memory access limitations are PIC18F6310 and PIC18F6410 devices. more fully explained in Table6-1. REGISTER 6-1: CONFIG3L: CONFIGURATION BYTE REGISTER LOW R/P-1 R/P-1 U-0 U-0 U-0 U-0 R/P-1 R/P-1 WAIT BW — — — — PM1 PM0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value after erase bit ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WAIT: External Bus Data Wait Enable bit 1 = Wait selections unavailable, device will not wait 0 = Wait programmed by WAIT1 and WAIT0 bits of MEMCOM register (MEMCOM<5:4>) bit 6 BW: External Bus Data Width Select bit 1 = 16-bit external bus data width 0 = 8-bit external bus data width bit 5-2 Unimplemented: Read as ‘0’ bit 1-0 PM<1:0>: Processor Data Memory Mode Select bits 11 = Microcontroller mode 10 = Microprocessor mode(1) 01 = Microcontroller with Boot Block mode(1) 00 = Extended Microcontroller mode(1) Note 1: This mode is available only on PIC18F8410 devices. DS39635C-page 68  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 6-2: MEMORY MAPS FOR PIC18FX310/X410 PROGRAM MEMORY MODES Microcontroller Mode(1) Extended Microcontroller Mode(2) 000000h 000000h On-Chip On-Chip Program Program Memory Memory (Top of Memory) (Top of Memory) (Top of Memory) + 1 (Top of Memory) + 1 Reads ‘0’s External Program Memory 1FFFFFh 1FFFFFh On-Chip External On-Chip Flash Memory Flash Microprocessor Mode(2) Microprocessor with Boot Block Mode(2) On-Chip Program Memory 000000h 000000h On-Chip 0007FFh Program 000800h Memory (No (No access) access) (Top of Memory) + 1 External External Program Program Memory Memory 1FFFFFh 1FFFFFh External On-Chip External On-Chip Memory Flash Memory Flash Legend: (Top of Memory) represents upper boundary of on-chip program memory space (1FFFh for PIC18FX310, 3FFFh for PIC18FX410). Shaded areas represent unimplemented or inaccessible areas, depending on the mode. Note 1: This mode is the only available mode on 64-pin devices and the default on 80-pin devices. 2: These modes are only available on 80-pin devices. TABLE 6-1: MEMORY ACCESS FOR PIC18F8310/8410 PROGRAM MEMORY MODES Internal Program Memory External Program Memory Operating Mode Execution Table Read Execution Table Read Table Write Table Write To From From From From To Microcontroller Yes Yes Yes No Access No Access No Access Extended Yes Yes Yes Yes Yes Yes Microcontroller Microprocessor No Access No Access No Access Yes Yes Yes Microprocessor Yes Yes Yes Yes Yes Yes w/Boot Block  2010 Microchip Technology Inc. DS39635C-page 69

PIC18F6310/6410/8310/8410 6.1.2 PROGRAM COUNTER The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer register, STKPTR. The stack space The Program Counter (PC) specifies the address of the is not part of either program or data space. The Stack instruction to fetch for execution. The PC is 21 bits wide Pointer is readable and writable and the address on the and is contained in three separate 8-bit registers. The top of the stack is readable and writable through the low byte, known as the PCL register, is both readable Top-of-Stack (TOS) Special File Registers. Data can and writable. The high byte, or PCH register, contains also be pushed to or popped from the stack using these the PC<15:8> bits; it is not directly readable or writable. registers. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This A CALL type instruction causes a push onto the stack; register contains the PC<20:16> bits; it is also not the Stack Pointer is first incremented and the location directly readable or writable. Updates to the PCU pointed to by the Stack Pointer is written with the register are performed through the PCLATU register. contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes The contents of PCLATH and PCLATU are transferred a pop from the stack; the contents of the location to the program counter by any operation that writes pointed to by the STKPTR are transferred to the PC PCL. Similarly, the upper two bytes of the program and then the Stack Pointer is decremented. counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed The Stack Pointer is initialized to ‘00000’ after all offsets to the PC (see Section6.1.5.1 “Computed Resets. There is no RAM associated with the location GOTO”). corresponding to a Stack Pointer value of ‘00000’; this is only a Reset value. Status bits indicate if the stack is The PC addresses bytes in the program memory. To full, has overflowed or has underflowed. prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to 6.1.3.1 Top-of-Stack Access a value of ‘0’. The PC increments by 2 to address sequential instructions in the program memory. Only the top of the Return Address Stack (TOS) is readable and writable. A set of three registers, The CALL, RCALL, GOTO and program branch TOSU:TOSH:TOSL, hold the contents of the stack instructions write to the program counter directly. For location pointed to by the STKPTR register these instructions, the contents of PCLATH and (Figure6-3). This allows users to implement a software PCLATU are not transferred to the program counter. stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the 6.1.3 RETURN ADDRESS STACK TOSU:TOSH:TOSL registers. These values can be The Return Address Stack allows any combination of placed on a user-defined software stack. At return time, up to 31 program calls and interrupts to occur. The PC the software can return these values to is pushed onto the stack when a CALL or RCALL TOSU:TOSH:TOSL and do a return. instruction is executed, or an interrupt is Acknowl- The user must disable the global interrupt enable bits edged. The PC value is pulled off the stack on a while accessing the stack to prevent inadvertent stack RETURN, RETLW or a RETFIE instruction. PCLATU and corruption. PCLATH are not affected by any of the RETURN or CALL instructions. FIGURE 6-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack<20:0> Top-of-Stack Registers Stack Pointer 11111 TOSU TOSH TOSL 11110 STKPTR<4:0> 00h 1Ah 34h 11101 00010 00011 Top-of-Stack 001A34h 00010 000D58h 00001 00000 DS39635C-page 70  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 6.1.3.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next pop will return a value of zero The STKPTR register (Register6-2) contains the Stack to the PC and sets the STKUNF bit, while the Stack Pointer value, the STKFUL (Stack Full) status bit and Pointer remains at zero. The STKUNF bit will remain the STKUNF (Stack Underflow) status bit. The value of set until cleared by software, or until a POR occurs. the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the Note: Returning a value of zero to the PC on an stack and decrements after values are popped off the underflow has the effect of vectoring the stack. On Reset, the Stack Pointer value will be zero. program to the Reset vector where the The user may read and write the Stack Pointer value. stack conditions can be verified and This feature can be used by a Real-Time Operating appropriate actions can be taken. This is System for return stack maintenance. not the same as a Reset, as the contents of the SFRs are not affected. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a 6.1.3.3 PUSH and POP Instructions POR. Since the Top-of-Stack is readable and writable, the The action that takes place when the stack becomes ability to push values onto the stack and pull values off full depends on the state of the STVREN (Stack the stack, without disturbing normal program execu- Overflow Reset Enable) Configuration bit. (Refer to tion, is a desirable feature. The PIC18 instruction set Section24.1 “Configuration Bits” for a description of includes two instructions, PUSH and POP, that permit the device Configuration bits.) If STVREN is set the TOS to be manipulated under software control. (default), the 31st push will push the (PC + 2) value TOSU, TOSH and TOSL can be modified to place data onto the stack, set the STKFUL bit and reset the or a return address on the stack. device. The STKFUL bit will remain set and the Stack The PUSH instruction places the current PC value onto Pointer will be set to zero. the stack. This increments the Stack Pointer and loads If STVREN is cleared, the STKFUL bit will be set on the the current PC value onto the stack. 31st push and the Stack Pointer will increment to 31. The POP instruction discards the current TOS by Any additional pushes will not overwrite the 31st push decrementing the Stack Pointer. The previous value and STKPTR will remain at 31. pushed onto the stack then becomes the TOS value. REGISTER 6-2: STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ C = Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP<4:0>: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.  2010 Microchip Technology Inc. DS39635C-page 71

PIC18F6310/6410/8310/8410 6.1.3.4 Stack Full and Underflow Resets 6.1.5 LOOK-UP TABLES IN PROGRAM MEMORY Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in There may be programming situations that require the Configuration Register 4L. When STVREN is set, a full creation of data structures, or look-up tables, in or underflow condition will set the appropriate STKFUL program memory. For PIC18 devices, look-up tables or STKUNF bit and then cause a device Reset. When can be implemented in two ways: STVREN is cleared, a full or underflow condition will set • Computed GOTO the appropriate STKFUL or STKUNF bit, but not cause • Table Reads a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a Power-on Reset. 6.1.5.1 Computed GOTO 6.1.4 FAST REGISTER STACK A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in A Fast Register Stack is provided for the STATUS, Example6-2. WREG and BSR registers to provide a “fast return” option for interrupts. This stack is only one level deep A look-up table can be formed with an ADDWF PCL and is neither readable nor writable. It is loaded with the instruction and a group of RETLW nn instructions. The current value of the corresponding register when the W register is loaded with an offset into the table before processor vectors for an interrupt. All interrupt sources executing a call to that table. The first instruction of the will push values into the stack registers. The values in called routine is the ADDWF PCL instruction. The next the registers are then loaded back into the working instruction executed will be one of the RETLW nn registers if the RETFIE, FAST instruction is used to instructions that returns the value ‘nn’ to the calling return from the interrupt. function. If both low and high-priority interrupts are enabled, the The offset value (in WREG) specifies the number of stack registers cannot be used reliably to return from bytes that the program counter should advance and low-priority interrupts. If a high-priority interrupt occurs should be multiples of 2 (LSb = 0). while servicing a low-priority interrupt, the stack In this method, only one data byte may be stored in register values stored by the low-priority interrupt will each instruction location and room on the Return be overwritten. In these cases, users must save the key Address Stack is required. registers in software during a low-priority interrupt. If interrupt priority is not used, all interrupts may use the EXAMPLE 6-2: COMPUTED GOTO USING Fast Register Stack for returns from interrupt. If no AN OFFSET VALUE interrupts are used, the Fast Register Stack can be MOVF OFFSET, W used to restore the STATUS, WREG and BSR registers CALL TABLE at the end of a subroutine call. To use the Fast Register ORG nn00h Stack for a subroutine call, a CALL label, FAST TABLE ADDWF PCL instruction must be executed to save the STATUS, RETLW nnh WREG and BSR registers to the Fast Register Stack. A RETLW nnh RETURN, FAST instruction is then executed to restore RETLW nnh these registers from the Fast Register Stack. . . Example6-1 shows a source code example that uses . the Fast Register Stack during a subroutine call and return. 6.1.5.2 Table Reads EXAMPLE 6-1: FAST REGISTER STACK A better method of storing data in program memory CODE EXAMPLE allows two bytes of data to be stored in each instruction location. CALL SUB1, FAST ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER Look-up table data may be stored two bytes per ;STACK program word while programming. The Table Pointer  (TBLPTR) register specifies the byte address and the  Table Latch (TABLAT) register contains the data that is read from the program memory. Data is transferred SUB1  from program memory one byte at a time.  RETURN FAST ;RESTORE VALUES SAVED Table read operation is discussed further in ;IN FAST REGISTER STACK Section7.1 “Table Reads and Table Writes”. DS39635C-page 72  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 6.2 PIC18 Instruction Cycle 6.2.2 INSTRUCTION FLOW/PIPELINING An “Instruction Cycle” consists of four Q cycles, Q1 6.2.1 CLOCKING SCHEME through Q4. The instruction fetch and execute are The microcontroller clock input, whether from an pipelined in such a manner that a fetch takes one internal or external source, is internally divided by four instruction cycle, while the decode and execute take to generate four non-overlapping quadrature clocks another instruction cycle. However, due to the pipe- (Q1, Q2, Q3 and Q4). Internally, the program counter is lining, each instruction effectively executes in one incremented on every Q1; the instruction is fetched cycle. If an instruction causes the program counter to from the program memory and latched into the instruc- change (e.g., GOTO), then two cycles are required to tion register during Q4. The instruction is decoded and complete the instruction (Example6-3). executed during the following Q1 through Q4. The A fetch cycle begins with the Program Counter (PC) clocks and instruction execution flow are shown in incrementing in Q1. Figure6-4. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 6-4: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Q3 Phase Clock Q4 PC PC PC + 2 PC + 4 OSC2/CLKO (RC mode) Execute INST (PC – 2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 2) Fetch INST (PC + 4) EXAMPLE 6-3: INSTRUCTION PIPELINE FLOW TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP) 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed.  2010 Microchip Technology Inc. DS39635C-page 73

PIC18F6310/6410/8310/8410 6.2.3 INSTRUCTIONS IN PROGRAM The CALL and GOTO instructions have the absolute MEMORY program memory address embedded into the instruc- tion. Since instructions are always stored on word The program memory is addressed in bytes. Instruc- boundaries, the data contained in the instruction is a tions are stored as two bytes or four bytes in program word address. The word address is written to PC<20:1>, memory. The Least Significant Byte of an instruction which accesses the desired byte address in program word is always stored in a program memory location memory. Instruction #2 in Figure6-5 shows how the with an even address (LSb = 0). To maintain alignment instruction, GOTO 0006h, is encoded in the program with instruction boundaries, the PC increments in steps memory. Program branch instructions, which encode a of 2 and the LSb will always read ‘0’ (see Section6.1.2 relative address offset, operate in the same manner. The “Program Counter”). offset value stored in a branch instruction represents the Figure6-5 shows an example of how instruction words number of single-word instructions that the PC will be are stored in the program memory. offset by. Section25.0 “Instruction Set Summary” provides further details of the instruction set. FIGURE 6-5: INSTRUCTIONS IN PROGRAM MEMORY Word Address LSB = 1 LSB = 0  Program Memory 000000h Byte Locations  000002h 000004h 000006h Instruction 1: MOVLW 055h 0Fh 55h 000008h Instruction 2: GOTO 0006h EFh 03h 00000Ah F0h 00h 00000Ch Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh F4h 56h 000010h 000012h 000014h 6.2.4 TWO-WORD INSTRUCTIONS and used by the instruction sequence. If the first word is skipped for some reason and the second word is The standard PIC18 instruction set has four two-word executed by itself, a NOP is executed instead. This is instructions: CALL, MOVFF, GOTO and LSFR. In all necessary for cases when the two-word instruction is cases, the second word of the instructions always has preceded by a conditional instruction that changes the ‘1111’ as its four Most Significant bits; the other 12 bits PC. Example6-4 shows how this works. are literal data, usually a data memory address. The use of ‘1111’ in the 4 MSbs of an instruction Note: See Section6.5 “Data Memory and the specifies a special form of NOP. If the instruction is Extended Instruction Set” for information on two-word instructions in executed in proper sequence – immediately after the first word – the data in the second word is accessed the extended instruction set. EXAMPLE 6-4: TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word 1111 0100 0101 0110 ; Execute this word as a NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 ADDWF REG3 ; continue code DS39635C-page 74  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 6.3 Data Memory Organization 6.3.1 BANK SELECT REGISTER Large areas of data memory require an efficient Note: The operation of some aspects of data addressing scheme to make rapid access to any memory are changed when the PIC18 address possible. Ideally, this means that an entire extended instruction set is enabled. See address does not need to be provided for each read or Section6.5 “Data Memory and the write operation. For PIC18 devices, this is accom- Extended Instruction Set” for more plished with a RAM banking scheme. This divides the information. memory space into16 contiguous banks of 256 bytes. The data memory in PIC18 devices is implemented as Depending on the instruction, each location can be static RAM. Each register in the data memory has a addressed directly by its full 12-bit address, or an 8-bit 12-bit address, allowing up to 4096 bytes of data low-order address and a 4-bit Bank Pointer. memory. The memory space is divided into as many Most instructions in the PIC18 instruction set make use as 16 banks that contain 256 bytes each. of the Bank Pointer, known as the Bank Select Register PIC18F6310/6410/8310/8410 devices implement (BSR). This SFR holds the 4 Most Significant bits of a only 3complete banks, for a total of 768 bytes. location’s address; the instruction itself includes the Figure6-6 shows the data memory organization for 8Least Significant bits. Only the four lower bits of the the devices. BSR are implemented (BSR<3:0>). The upper four bits The data memory contains Special Function Registers are unused; they will always read ‘0’ and cannot be (SFRs) and General Purpose Registers (GPRs). The written to. The BSR can be loaded directly by using the SFRs are used for control and status of the controller MOVLB instruction. and peripheral functions, while GPRs are used for data The value of the BSR indicates the bank in data storage and scratchpad operations in the user’s memory; the 8 bits in the instruction show the location application. Any read of an unimplemented location will in the bank and can be thought of as an offset from the read as ‘0’s. bank’s lower boundary. The relationship between the The instruction set and architecture allow operations BSR’s value and the bank division in data memory is across all banks. The entire data memory may be shown in Figure6-7. accessed by Direct, Indirect or Indexed Addressing Since up to 16 registers may share the same low-order modes. Addressing modes are discussed later in this address, the user must always be careful to ensure that section. the proper bank is selected before performing a data To ensure that commonly used registers (SFRs and read or write. For example, writing what should be select GPRs) can be accessed in a single cycle, PIC18 program data to an 8-bit address of F9h while the BSR devices implement an Access Bank. This is a 256-byte is 0Fh will end up resetting the program counter. memory space that provides fast access to SFRs and While any bank can be selected, only those banks that the lower portion of GPR Bank 0 without using the are actually implemented can be read or written to. BSR. Section6.3.2 “Access Bank” provides a Writes to unimplemented banks are ignored, while detailed description of the Access RAM. reads from unimplemented banks will return ‘0’s. Even so, the STATUS register will still be affected as if the operation was successful. The data memory map in Figure6-6 indicates which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers.  2010 Microchip Technology Inc. DS39635C-page 75

PIC18F6310/6410/8310/8410 FIGURE 6-6: DATA MEMORY MAP FOR PIC18F6310/6410/8310/8410 DEVICES When a = 0: BSR<3:0> Data Memory Map The BSR is ignored and the 00h 000h Access Bank is used. Access RAM = 0000 05Fh The first 128 bytes are Bank 0 GPR 060h general purpose RAM FFh 0FFh (from Bank 0). 00h 100h = 0001 The second 128 bytes are Bank 1 GPR Special Function Registers FFh 1FFh (from Bank 15). = 0010 00h 200h Bank 2 GPR When a = 1: FFh 2FFh The BSR specifies the bank 00h 300h used by the instruction. = 0011 Bank 3 Access Bank 00h Unused Access RAM Low to 5Fh Read as 00h 60h Access RAM High (SFRs) FFh = 1110 Bank 14 FFh EFFh = 1111 00h Unused F00h F3Fh Bank 15 F40h FFh SFR FFFh DS39635C-page 76  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 6-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) 7 BSR(1) 0 000h Data Memory 00h 7 From Opcode(2) 0 0 0 0 0 0 0 1 0 Bank 0 11 11 11 11 11 11 11 11 FFh 100h 00h Bank 1 Bank Select(2) FFh 200h 00h Bank 2 300h FFh 00h Bank 3 through Bank 13 FFh E00h 00h Bank 14 F00h FFh 00h Bank 15 FFFh FFh Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. 6.3.2 ACCESS BANK Using this “forced” addressing allows the instruction to operate on a data address in a single cycle without While the use of the BSR with an embedded 8-bit updating the BSR first. For 8-bit addresses of 80h and address allows users to address the entire range of above, this means that users can evaluate and operate data memory, it also means that the user must always on SFRs more efficiently. The Access RAM below 60h ensure that the correct bank is selected. Otherwise, is a good place for data values that the user might need data may be read from or written to the wrong location. to access rapidly, such as immediate computational This can be disastrous if a GPR is the intended target results or common program variables. Access RAM of an operation but an SFR is written to instead. also allows for faster and more code efficient context Verifying and/or changing the BSR for each read or saving and switching of variables. write to data memory can become very inefficient. The mapping of the Access Bank is slightly different To streamline access for the most commonly used data when the extended instruction set is enabled (XINST memory locations, the data memory is configured with Configuration bit = 1). This is discussed in more detail an Access Bank, which allows users to access a in Section6.5.3 “Mapping the Access Bank in mapped block of memory without specifying a BSR. Indexed Literal Offset Mode”. The Access Bank consists of the first 96 bytes of memory (00h-5Fh) in Bank 0 and the last 160 bytes of 6.3.3 GENERAL PURPOSE memory (60h-FFh) in Block 15. The lower half is known REGISTER FILE as the “Access RAM” and is composed of GPRs. This upper half is where the device’s SFRs are mapped. PIC18 devices may have banked memory in the GPR These two areas are mapped contiguously in the area. This is data RAM, which is available for use by all Access Bank and can be addressed in a linear fashion instructions. GPRs start at the bottom of Bank 0 by an 8-bit address (Figure6-6). (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a The Access Bank is used by core PIC18 instructions Power-on Reset and are unchanged on all other that include the Access RAM bit (the ‘a’ parameter in Resets. the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely.  2010 Microchip Technology Inc. DS39635C-page 77

PIC18F6310/6410/8310/8410 6.3.4 SPECIAL FUNCTION REGISTERS The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, The Special Function Registers (SFRs) are registers Resets and interrupts) and those related to the used by the CPU and peripheral modules for controlling peripheral functions. The Reset and interrupt registers the desired operation of the device. These registers are are described in their respective chapters, while the implemented as static RAM. SFRs start at the top of ALU’s STATUS register is described later in this data memory (FFFh) and extend downward to occupy section. Registers related to the operation of the more than the top half of Bank 15 (F60h to FFFh). A list peripheral features are described in the chapter for that of these registers is given in Table6-2 and Table6-3. peripheral. The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR locations are unimplemented and read as ‘0’s. TABLE 6-2: SPECIAL FUNCTION REGISTER MAP FOR PIC18F6310/6410/8310/8410 DEVICES Address Name Address Name Address Name Address Name Address Name FFFh TOSU FDFh INDF2(1) FBFh CCPR1H F9Fh IPR1 F7Fh SPBRGH1 FFEh TOSH FDEh POSTINC2(1) FBEh CCPR1L F9Eh PIR1 F7Eh BAUDCON1 FFDh TOSL FDDh POSTDEC2(1) FBDh CCP1CON F9Dh PIE1 F7Dh —(2) FFCh STKPTR FDCh PREINC2(1) FBCh CCPR2H F9Ch MEMCON(3) F7Ch —(2) FFBh PCLATU FDBh PLUSW2(1) FBBh CCPR2L F9Bh OSCTUNE F7Bh —(2) FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah TRISJ(3) F7Ah —(2) FF9h PCL FD9h FSR2L FB9h CCPR3H F99h TRISH(3) F79h —(2) FF8h TBLPTRU FD8h STATUS FB8h CCPR3L F98h TRISG F78h —(2) FF7h TBLPTRH FD7h TMR0H FB7h CCP3CON F97h TRISF F77h —(2) FF6h TBLPTRL FD6h TMR0L FB6h —(2) F96h TRISE F76h —(2) FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD F75h —(2) FF4h PRODH FD4h —(2) FB4h CMCON F94h TRISC F74h —(2) FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB F73h —(2) FF2h INTCON FD2h HLVDCON FB2h TMR3L F92h TRISA F72h —(2) FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h LATJ(3) F71h —(2) FF0h INTCON3 FD0h RCON FB0h PSPCON F90h LATH(3) F70h —(2) FEFh INDF0(1) FCFh TMR1H FAFh SPBRG1 F8Fh LATG F6Fh SPBRG2 FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG1 F8Eh LATF F6Eh RCREG2 FEDh POSTDEC0(1) FCDh T1CON FADh TXREG1 F8Dh LATE F6Dh TXREG2 FECh PREINC0(1) FCCh TMR2 FACh TXSTA1 F8Ch LATD F6Ch TXSTA2 FEBh PLUSW0(1) FCBh PR2 FABh RCSTA1 F8Bh LATC F6Bh RCSTA2 FEAh FSR0H FCAh T2CON FAAh —(2) F8Ah LATB F6Ah —(2) FE9h FSR0L FC9h SSPBUF FA9h —(2) F89h LATA F69h —(2) FE8h WREG FC8h SSPADD FA8h —(2) F88h PORTJ(3) F68h —(2) FE7h INDF1(1) FC7h SSPSTAT FA7h —(2) F87h PORTH(3) F67h —(2) FE6h POSTINC1(1) FC6h SSPCON1 FA6h —(2) F86h PORTG F66h —(2) FE5h POSTDEC1(1) FC5h SSPCON2 FA5h IPR3 F85h PORTF F65h —(2) FE4h PREINC1(1) FC4h ADRESH FA4h PIR3 F84h PORTE F64h —(2) FE3h PLUSW1(1) FC3h ADRESL FA3h PIE3 F83h PORTD F63h —(2) FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC F62h —(2) FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB F61h —(2) FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA F60h —(2) Note 1: This is not a physical register. 2: Unimplemented registers are read as ‘0’. 3: This register is not available on 64-pin devices. DS39635C-page 78  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 6-3: REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 63, 70 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 63, 70 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 63, 70 STKPTR STKFUL(6) STKUNF(6) — Return Stack Pointer 00-0 0000 63, 71 PCLATU — — — Holding Register for PC<20:16> ---0 0000 63, 70 PCLATH Holding Register for PC<15:8> 0000 0000 63, 70 PCL PC Low Byte (PC<7:0>) 0000 0000 63, 70 TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 63, 93 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 63, 93 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 63, 93 TABLAT Program Memory Table Latch 0000 0000 63, 93 PRODH Product Register High Byte xxxx xxxx 63, 107 PRODL Product Register Low Byte xxxx xxxx 63, 107 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 63, 111 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 63, 112 INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 63, 113 INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 63, 85 POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 63, 85 POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 63, 85 PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 63, 85 PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register), N/A 63, 85 value of FSR0 offset by W FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- xxxx 63, 85 FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 63, 85 WREG Working Register xxxx xxxx 63 INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 63, 85 POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 63, 85 POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 63, 85 PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 63, 85 PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register), N/A 63, 85 value of FSR1 offset by W FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- xxxx 63, 85 FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 63, 85 BSR — — — — Bank Select Register ---- 0000 63, 75 INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 64, 85 POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 64, 85 POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 64, 85 PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 64, 85 PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register), N/A 64, 85 value of FSR2 offset by W FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- xxxx 64, 85 FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 64, 85 STATUS — — — N OV Z DC C ---x xxxx 64, 83 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded locations are unimplemented, read as ‘0’. Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. 2: These registers and/or bits are not implemented on 64-pin devices, read as ‘0’. 3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section3.6.4 “PLL in INTOSC Modes”. 4: The RG5 bit is only available when Master Clear is disabled (MCLRE Configuration bit=0); otherwise, RG5 reads as ‘0’. This bit is read-only. 5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: STKFUL and STKUNF bits are cleared by user software or by a POR.  2010 Microchip Technology Inc. DS39635C-page 79

PIC18F6310/6410/8310/8410 TABLE 6-3: REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: TMR0H Timer0 Register High Byte 0000 0000 64, 153 TMR0L Timer0 Register Low Byte xxxx xxxx 64, 153 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 64, 151 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 42, 64 HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 64, 275 WDTCON — — — — — — — SWDTEN ---- ---0 64, 291 RCON IPEN SBOREN(1) — RI TO PD POR BOR 0q-1 11q0 56, 64, 123 TMR1H Timer1 Register High Byte xxxx xxxx 64, 159 TMR1L Timer1 Register Low Byte 0000 0000 64, 159 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 64, 155 TMR2 Timer2 Register 1111 1111 64, 162 PR2 Timer2 Period Register -000 0000 64, 162 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 64, 161 SSPBUF MSSP Receive Buffer/Transmit Register 0000 0000 64, 178, 186 SSPADD MSSP Address Register in I2C™ Slave Mode. MSSP Baud Rate Reload Register in I2C Master Mode. 0000 0000 64, 186 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 64, 178, 188 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 64, 179, 179 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 64, 189 ADRESH A/D Result Register High Byte xxxx xxxx 64, 264 ADRESL A/D Result Register Low Byte 0000 0000 64, 264 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 64, 255 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 qqqq 64, 256 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 64, 257 CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 65, 168 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 65, 168 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 65, 167 CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 65, 168 CCPR2L Capture/Compare/PWM Register 2 Low Byte 0000 0000 65, 168 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 65, 167 CCPR3H Capture/Compare/PWM Register 3 High Byte xxxx xxxx 65, 168 CCPR3L Capture/Compare/PWM Register 3 Low Byte 0000 0000 65, 168 CCP3CON — — DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 65, 167 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 65, 271 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 65, 265 TMR3H Timer3 Register High Byte 0000 0000 65, 163 TMR3L Timer3 Register Low Byte 0000 0000 65, 165 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 65, 163 PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- 65, 149 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded locations are unimplemented, read as ‘0’. Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. 2: These registers and/or bits are not implemented on 64-pin devices, read as ‘0’. 3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section3.6.4 “PLL in INTOSC Modes”. 4: The RG5 bit is only available when Master Clear is disabled (MCLRE Configuration bit=0); otherwise, RG5 reads as ‘0’. This bit is read-only. 5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: STKFUL and STKUNF bits are cleared by user software or by a POR. DS39635C-page 80  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 6-3: REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: SPBRG1 EUSART1 Baud Rate Generator Low Byte 0000 0000 65, 221 RCREG1 EUSART1 Receive Register 0000 0000 65, 229 TXREG1 EUSART1 Transmit Register xxxx xxxx 65, 226 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 65, 218 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 65, 219 IPR3 — — RC2IP TX2IP — — — CCP3IP --11 ---1 65, 122 PIR3 — — RC2IF TX2IF — — — CCP3IF --00 ---0 65, 116 PIE3 — — RC2IE TX2IE — — — CCP3IE --00 ---0 65, 119 IPR2 OSCFIP CMIP — — BCLIP HLVDIP TMR3IP CCP2IP 11-- 1111 65, 121 PIR2 OSCFIF CMIF — — BCLIF HLVDIF TMR3IF CCP2IF 00-- 0000 65, 115 PIE2 OSCFIE CMIE — — BCLIE HLVDIE TMR3IE CCP2IE 00-- 0000 65, 118 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 65, 120 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 65, 114 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 65, 117 MEMCON(2) EBDIS — WAIT1 WAIT0 — — WM1 WM0 0-00 --00 65, 95 OSCTUNE INTSRC PLLEN(3) — TUN4 TUN3 TUN2 TUN1 TUN0 00-0 0000 39, 65 TRISJ(2) PORTJ Data Direction Register 1111 1111 65, 147 TRISH(2) PORTH Data Direction Register 1111 1111 65, 145 TRISG — — — PORTG Data Direction Register ---1 1111 66, 143 TRISF PORTF Data Direction Register 1111 1111 66, 141 TRISE PORTE Data Direction Register 1111 1111 66, 139 TRISD PORTD Data Direction Register 1111 1111 66, 136 TRISC PORTC Data Direction Register 1111 1111 66, 133 TRISB PORTB Data Direction Register 1111 1111 66, 130 TRISA TRISA7(5) TRISA6(5) PORTA Data Direction Register 1111 1111 66, 127 LATJ(2) LATJ Output Latch Register xxxx xxxx 66, 147 LATH(2) LATH Output Latch Register xxxx xxxx 66, 145 LATG — — — LATG Output Latch Register ---x xxxx 66, 143 LATF LATF Output Latch Register xxxx xxxx 66, 141 LATE LATE Output Latch Register xxxx xxxx 66, 139 LATD LATD Output Latch Register xxxx xxxx 66, 136 LATC LATC Output Latch Register xxxx xxxx 66, 133 LATB LATB Output Latch Register xxxx xxxx 66, 130 LATA LATA7(5) LATA6(5) LATA Output Latch Register xxxx xxxx 66, 127 PORTJ(2) Read PORTJ pins, Write PORTJ Data Latch xxxx xxxx 66, 147 PORTH(2) Read PORTH pins, Write PORTH Data Latch xxxx xxxx 66, 145 PORTG — — RG5(4) Read PORTG pins<4:0>, Write PORTG Data Latch<4:0> --xx xxxx 66, 143 PORTF Read PORTF pins, Write PORTF Data Latch xxxx xxxx 66, 141 PORTE Read PORTE pins, Write PORTE Data Latch xxxx xxxx 66, 139 PORTD Read PORTD pins, Write PORTD Data Latch xxxx xxxx 66, 136 PORTC Read PORTC pins, Write PORTC Data Latch xxxx xxxx 66, 133 PORTB Read PORTB pins, Write PORTB Data Latch xxxx xxxx 66, 130 PORTA RA7(5) RA6(5) Read PORTA pins, Write PORTA Data Latch xx0x 0000 66, 127 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded locations are unimplemented, read as ‘0’. Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. 2: These registers and/or bits are not implemented on 64-pin devices, read as ‘0’. 3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section3.6.4 “PLL in INTOSC Modes”. 4: The RG5 bit is only available when Master Clear is disabled (MCLRE Configuration bit=0); otherwise, RG5 reads as ‘0’. This bit is read-only. 5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: STKFUL and STKUNF bits are cleared by user software or by a POR.  2010 Microchip Technology Inc. DS39635C-page 81

PIC18F6310/6410/8310/8410 TABLE 6-3: REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: SPBRGH1 EUSART1 Baud Rate Generator High Byte 0000 0000 66, 221 BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 0100 0-00 66, 220 SPBRG2 AUSART2 Baud Rate Generator 0000 0000 66, 234 RCREG2 AUSART2 Receive Register 0000 0000 66, 248 TXREG2 AUSART2 Transmit Register xxxx xxxx 66, 246 TXSTA2 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 66, 242 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 66, 243 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded locations are unimplemented, read as ‘0’. Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits=01; otherwise, it is disabled and reads as ‘0’. See Section5.4 “Brown-out Reset (BOR)”. 2: These registers and/or bits are not implemented on 64-pin devices, read as ‘0’. 3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section3.6.4 “PLL in INTOSC Modes”. 4: The RG5 bit is only available when Master Clear is disabled (MCLRE Configuration bit=0); otherwise, RG5 reads as ‘0’. This bit is read-only. 5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: STKFUL and STKUNF bits are cleared by user software or by a POR. DS39635C-page 82  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 6.3.5 STATUS REGISTER intended. As an example, CLRF STATUS, will set the Z bit and leave the remaining Status bits unchanged The STATUS register, shown in Register6-3, contains (‘000u u1uu’). the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS If the STATUS register is the destination for an instruc- register, because these instructions do not affect the Z, tion that affects the Z, DC, C, OV or N bits, the results C, DC, OV or N bits in the STATUS register. of the instruction are not written; instead, the status is updated according to the instruction performed. There- For other instructions that do not affect Status bits, see fore, the result of an instruction with the STATUS the instruction set summaries in Table25-2 and register as its destination may be different than Table25-3. Note: The C and DC bits operate as a Borrow and Digit Borrow bit, respectively, in subtraction. REGISTER 6-3: STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC(1) C(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude, which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit(1) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(2) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’scomplement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. 2: For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’scomplement of the sec- ond operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register.  2010 Microchip Technology Inc. DS39635C-page 83

PIC18F6310/6410/8310/8410 6.4 Data Addressing Modes Purpose Register File”), or a location in the Access Bank (Section6.3.2 “Access Bank”) as the data Note: The execution of some instructions in the source for the instruction. core PIC18 instruction set are changed The Access RAM bit, ‘a’, determines how the address when the PIC18 extended instruction set is is interpreted. When ‘a’ is ‘1’, the contents of the BSR enabled. See Section6.5 “Data Memory (Section6.3.1 “Bank Select Register”) are used with and the Extended Instruction Set” for the address to determine the complete 12-bit address more information. of the register. When ‘a’ is ‘0’, the address is interpreted While the program memory can be addressed in only as being a register in the Access Bank. Addressing that one way – through the program counter – information uses the Access RAM is sometimes also known as in the data memory space can be addressed in several Direct Forced Addressing mode. ways. For most instructions, the addressing mode is A few instructions, such as MOVFF, include the entire fixed. Other instructions may use up to three modes, 12-bit address (either source or destination) in their depending on which operands are used and whether or opcodes. In these cases, the BSR is ignored entirely. not the extended instruction set is enabled. The destination of the operation’s results is determined The addressing modes are: by the destination bit, ‘d’. When ‘d’ is ‘1’, the results are • Inherent stored back in the source register, overwriting its origi- nal contents. When ‘d’ is ‘0’, the results are stored in • Literal the W register. Instructions without the ‘d’ argument • Direct have a destination that is implicit in the instruction; their • Indirect destination is either the target register being operated An additional addressing mode, Indexed Literal Offset, on, or the W register. is available when the extended instruction set is 6.4.3 INDIRECT ADDRESSING enabled (XINST Configuration bit = 1). Its operation is discussed in greater detail in Section6.5.1 “Indexed Indirect Addressing allows the user to access a location Addressing with Literal Offset”. in data memory without giving a fixed address in the instruction. This is done by using File Select Registers 6.4.1 INHERENT AND LITERAL (FSRs) as pointers to the locations to be read or written ADDRESSING to. Since the FSRs are themselves located in RAM as Many PIC18 control instructions do not need any Special File Registers, they can also be directly manip- argument at all; they either perform an operation that ulated under program control. This makes FSRs very globally affects the device, or they operate implicitly on useful in implementing data structures, such as tables one register. This addressing mode is known as and arrays in data memory. Inherent Addressing. Examples include SLEEP, RESET The registers for Indirect Addressing are also and DAW. implemented with Indirect File Operands (INDFs) that Other instructions work in a similar way but require an permit automatic manipulation of the pointer value with additional explicit argument in the opcode. This is auto-incrementing, auto-decrementing or offsetting known as Literal Addressing mode, because they with another value. This allows for efficient code using require some literal value as an argument. Examples loops, such as the example of clearing an entire RAM include ADDLW and MOVLW, which respectively, add or bank in Example6-5. It also enables users to perform move a literal value to the W register. Other examples Indexed Addressing and other Stack Pointer include CALL and GOTO, which include a 20-bit operations for program memory in data memory. program memory address. EXAMPLE 6-5: HOW TO CLEAR RAM 6.4.2 DIRECT ADDRESSING (BANK 1) USING INDIRECT ADDRESSING Direct Addressing specifies all or part of the source and/or destination address of the operation within the LFSR FSR0, 100h ; opcode itself. The options are specified by the NEXT CLRF POSTINC0 ; Clear INDF arguments accompanying the instruction. ; register then ; inc pointer In the core PIC18 instruction set, bit-oriented and BTFSS FSR0H, 1 ; All done with byte-oriented instructions use some version of Direct ; Bank1? Addressing by default. All of these instructions include BRA NEXT ; NO, clear next some 8-bit literal address as their Least Significant CONTINUE ; YES, continue Byte. This address specifies either a register address in one of the banks of data RAM (Section6.3.3 “General DS39635C-page 84  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 6.4.3.1 FSR Registers and the mapped in the SFR space but are not physically imple- INDF Operand mented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. At the core of Indirect Addressing are three sets of A read from INDF1, for example, reads the data at the registers: FSR0, FSR1 and FSR2. Each represents a address indicated by FSR1H:FSR1L. Instructions that pair of 8-bit registers, FSRnH and FSRnL. The four use the INDF registers as operands actually use the upper bits of the FSRnH register are not used, so each contents of their corresponding FSR as a pointer to the FSR pair holds a 12-bit value. This represents a value instruction’s target. The INDF operand is just a that can address the entire range of the data memory convenient way of using the pointer. in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. Because Indirect Addressing uses a full 12-bit address, data RAM banking is not necessary. Thus, the current Indirect Addressing is accomplished with a set of contents of the BSR and the Access RAM bit have no Indirect File Operands, INDF0 through INDF2. These effect on determining the target address. can be thought of as “virtual” registers”; they are FIGURE 6-8: INDIRECT ADDRESSING 000h Using an instruction with one of the ADDWF, INDF1, 1 Bank 0 indirect addressing registers as the 100h operand.... Bank 1 200h Bank 2 300h ...uses the 12-bit address stored in FSR1H:FSR1L the FSR pair associated with that 7 0 7 0 register.... Bank 3 x x x x 1 1 1 1 1 1 0 0 1 1 0 0 through Bank 13 ...to determine the data memory location to be used in that operation. E00h In this case, the FSR1 pair contains FCCh. This means the contents of Bank 14 location FCCh will be added to that F00h of the W register and stored back in Bank 15 FCCh. FFFh Data Memory 6.4.3.2 FSR Registers and POSTINC, In this context, accessing an INDF register uses the POSTDEC, PREINC and PLUSW value in the FSR registers without changing them. Similarly, accessing a PLUSW register gives the FSR In addition to the INDF operand, each FSR register pair value offset by the value in the W register; neither value also has four additional indirect operands. Like INDF, is actually changed in the operation. Accessing the these are “virtual” registers that cannot be indirectly other virtual registers changes the value of the FSR read or written to. Accessing these registers actually registers. accesses the associated FSR register pair, but also performs a specific action on its stored value. They are: Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is, • POSTDEC: accesses the FSR value, then rollovers of the FSRnL register from FFh to 00h carry automatically decrements it by ‘1’ afterwards over to the FSRnH register. On the other hand, results • POSTINC: accesses the FSR value, then of these operations do not change the value of any automatically increments it by ‘1’ afterwards flags in the STATUS register (e.g., Z, N, OV, etc.). • PREINC: increments the FSR value by ‘1’, then uses it in the operation • PLUSW: adds the signed value of the W register (range of -127 to 128) to that of the FSR and uses the new value in the operation.  2010 Microchip Technology Inc. DS39635C-page 85

PIC18F6310/6410/8310/8410 The PLUSW register can be used to implement a form 6.5.1 INDEXED ADDRESSING WITH of Indexed Addressing in the data memory space. By LITERAL OFFSET manipulating the value in the W register, users can Enabling the PIC18 extended instruction set changes reach addresses that are fixed offsets from pointer the behavior of Indirect Addressing using the FSR2 addresses. In some applications, this can be used to register pair and its associated file operands. Under the implement some powerful program control structure, proper conditions, instructions that use the Access such as software stacks, inside of data memory. Bank – that is, most bit-oriented and byte-oriented 6.4.3.3 Operations by FSRs on FSRs instructions – can invoke a form of Indexed Addressing using an offset specified in the instruction. This special Indirect Addressing operations that target other FSRs or addressing mode is known as Indexed Addressing with virtual registers represent special cases. For example, Literal Offset, or Indexed Literal Offset mode. using an FSR to point to one of the virtual registers will When using the extended instruction set, this not result in successful operations. As a specific case, addressing mode requires the following: assume that FSR0H:FSR0L contains FE7h, the address of INDF1. Attempts to read the value of the INDF1, using • The use of the Access Bank is forced (‘a’ = 0); INDF0 as an operand, will return 00h. Attempts to write and to INDF1, using INDF0 as the operand, will result in a • The file address argument is less than or equal to NOP. 5Fh. On the other hand, using the virtual registers to write to Under these conditions, the file address of the an FSR pair may not occur as planned. In these cases, instruction is not interpreted as the lower byte of an the value will be written to the FSR pair, but without any address (used with the BSR in Direct Addressing), or incrementing or decrementing. Thus, writing to INDF2 as an 8-bit address in the Access Bank. Instead, the or POSTDEC2 will write the same value to the value is interpreted as an offset value to an Address FSR2H:FSR2L. Pointer specified by FSR2. The offset and the contents Since the FSRs are physical registers mapped in the of FSR2 are added to obtain the target address of the SFR space, they can be manipulated through all direct operation. operations. Users should proceed cautiously when 6.5.2 INSTRUCTIONS AFFECTED BY working on these registers, particularly if their code INDEXED LITERAL OFFSET MODE uses Indirect Addressing. Similarly, operations by Indirect Addressing are gener- Any of the core PIC18 instructions that can use Direct ally permitted on all other SFRs. Users should exercise Addressing are potentially affected by the Indexed the appropriate caution that they do not inadvertently Literal Offset Addressing mode. This includes all change settings that might affect the operation of the byte-oriented and bit-oriented instructions, or almost device. one-half of the standard PIC18 instruction set. Instruc- tions that only use Inherent or Literal Addressing 6.5 Data Memory and the Extended modes are unaffected. Instruction Set Additionally, byte-oriented and bit-oriented instructions are not affected if they do not use the Access Bank Enabling the PIC18 extended instruction set (XINST (Access RAM bit is ‘1’), or include a file address of 60h or Configuration bit = 1) significantly changes certain above. Instructions meeting these criteria will continue to aspects of data memory and its addressing. Specifi- execute as before. A comparison of the different possible cally, the use of the Access Bank for many of the core addressing modes when the extended instruction set is PIC18 instructions is different; this is due to the enabled is shown in Figure6-9. introduction of a new addressing mode for the data Those who desire to use byte-oriented or bit-oriented memory space. instructions in the Indexed Literal Offset mode should What does not change is just as important. The size of note the changes to assembler syntax for this mode. the data memory space is unchanged, as well as its lin- This is described in more detail in Section25.2.1 ear addressing. The SFR map remains the same. Core “Extended Instruction Syntax”. PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instruc- tions do not change at all. Indirect Addressing with FSR0 and FSR1 also remain unchanged. DS39635C-page 86  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 6-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) 000h When a = 0 and f  60h: The instruction executes in 060h Direct Forced mode. ‘f’ is Bank 0 interpreted as a location in the 100h Access RAM between 060h 00h and FFFh. This is the same as Bank 1 through 60h locations F60h to FFFh Bank 14 (Bank15) of data memory. Valid Range for ‘f’ Locations below 060h are not FFh available in this addressing F00h Access RAM mode. Bank 15 F40h SFRs FFFh Data Memory When a = 0 and f5Fh: 000h The instruction executes in Bank 0 Indexed Literal Offset mode. ‘f’ 060h is interpreted as an offset to the address value in FSR2. The 100h 001001da ffffffff two are added together to Bank 1 obtain the address of the target through register for the instruction. The Bank 14 address can be anywhere in FSR2H FSR2L the data memory space. F00h Note that in this mode, the Bank 15 correct syntax is now: F40h ADDWF [k], d SFRs where ‘k’ is the same as ‘f’. FFFh Data Memory BSR When a = 1 (all values of f): 000h 00000000 The instruction executes in Bank 0 060h Direct mode (also known as Direct Long mode). ‘f’ is 100h interpreted as a location in one of the 16 banks of the data Bank 1 001001da ffffffff memory space. The bank is through Bank 14 designated by the Bank Select Register (BSR). The address can be in any implemented F00h bank in the data memory Bank 15 space. F40h SFRs FFFh Data Memory  2010 Microchip Technology Inc. DS39635C-page 87

PIC18F6310/6410/8310/8410 6.5.3 MAPPING THE ACCESS BANK IN Remapping of the Access Bank applies only to opera- INDEXED LITERAL OFFSET MODE tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue The use of Indexed Literal Offset Addressing mode to use Direct Addressing as before. effectively changes how the lower part of Access RAM (00h to 5Fh) is mapped. Rather than containing just the 6.6 PIC18 Instruction Execution and contents of the bottom part of Bank 0, this mode maps the Extended Instruction Set the contents from Bank 0 and a user-defined “window” that can be located anywhere in the data memory Enabling the extended instruction set adds eight addi- space. The value of FSR2 establishes the lower bound- tional commands to the existing PIC18 instruction set. ary of the addresses mapped into the window, while the These instructions are executed as described in upper boundary is defined by FSR2 plus 95 (5Fh). Section25.2 “Extended Instruction Set”. Addresses in the Access RAM above 5Fh are mapped as previously described (see Section6.3.2 “Access Bank”). An example of Access Bank remapping in this addressing mode is shown in Figure6-10. FIGURE 6-10: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Example Situation: 000h ADDWF f, d, a Bank 0 05Fh FSR2H:FSR2L = 120h 07Fh Locations in the region Bank 0 from the FSR2 Pointer 100h Bank 1 (120h) to the pointer plus 120h 05Fh (17Fh) are mapped Window 17Fh 00h to the bottom of the Bank 1 Bank 1 “Window” Access RAM (000h-05Fh). 200h 5Fh Locations in Bank 0 from Bank 0 060h to 07Fh are mapped, 7Fh as usual, to the middle of Bank 2 80h the Access Bank. through SFRs Special Function Registers Bank 14 at F80h through FFFh are FFh mapped to 80h through Access Bank FFh, as usual. F00h Bank 0 addresses below Bank 15 5Fh can still be addressed F80h by using the BSR. SFRs FFFh Data Memory DS39635C-page 88  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 7.0 PROGRAM MEMORY The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table For PIC18FX310/X410 devices, the on-chip program writes move data between these two memory spaces memory is implemented as read-only memory. It is through an 8-bit register (TABLAT). readable over the entire VDD range during normal Table read operations retrieve data from program operation; it cannot be written to or erased. Reads from memory and places it into the data RAM space. Table program memory are executed one byte at a time. write operations place data from the data memory PIC18F8410 devices also implement the ability to read, space on the external data bus. The actual process of write to and execute code from external memory writing the data to the particular memory device is devices using the external memory interface. In this determined by the requirements of the device itself. implementation, external memory is used as all or part Figure7-1 shows the table operations as they relate to of the program memory space. The operation of the program memory and data RAM. physical interface is discussed in Section8.0 “External Table operations work with byte entities. A table block Memory Interface”. containing data, rather than program instructions, is not In all devices, a value written to the program memory required to be word-aligned. Therefore, a table block space does not need to be a valid instruction. can start and end at any byte address. If a table write is Executing a program memory location that forms an being used to write executable code into an external invalid instruction results in a NOP. program memory, program instructions will need to be word-aligned. 7.1 Table Reads and Table Writes Note: Although it cannot be used in PIC18F6310 To read and write to the program memory space, there devices in normal operation, the TBLWT are two operations that allow the processor to move instruction is still implemented in the bytes between the program memory space and the instruction set. Executing the instruction data RAM: table read (TBLRD) and table write (TBLWT). takes two instruction cycles, but effectively results in a NOP. The TBLWT instruction is available in programming modes and is used during In-Circuit Serial Programming (ICSP). FIGURE 7-1: TABLE READ AND TABLE WRITE OPERATIONS Instruction: TBLRD* Program Memory Space Data Memory Space Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL Table Latch (8-bit) TABLAT Instruction: TBLWT* Program Memory Space Data Memory Space Table Pointer(1) Table Latch (8-bit)(2) TBLPTRU TBLPTRH TBLPTRL TABLAT Note 1: The Table Pointer register points to a byte in the program memory space. 2: Data is actually written to the memory location by the memory write algorithm. See Section7.4 “Writing to Program Memory Space (PIC18F8310/8410 only)” for more information.  2010 Microchip Technology Inc. DS39635C-page 89

PIC18F6310/6410/8310/8410 7.2 Control Registers TABLE 7-1: TABLE POINTER OPERATIONS WITH TBLRD Two control registers are used in conjunction with the AND TBLWT INSTRUCTIONS TBLRD and TBLWT instructions: the TABLAT register and the TBLPTR register set. Example Operation on Table Pointer TBLRD* 7.2.1 TABLAT – TABLE LATCH REGISTER TBLPTR is not modified TBLWT* The Table Latch (TABLAT) is an 8-bit register mapped TBLRD*+ TBLPTR is incremented after the into the SFR space. The Table Latch register is used to TBLWT*+ read/write hold 8-bit data during data transfers between the program memory space and data RAM. TBLRD*- TBLPTR is decremented after the TBLWT*- read/write 7.2.2 TBLPTR – TABLE POINTER TBLRD+* TBLPTR is incremented before the REGISTER TBLWT+* read/write The Table Pointer register (TBLPTR) addresses a byte within the program memory. It is comprised of three 7.3 Reading the Flash Program SFR registers: Table Pointer Upper Byte, Table Pointer Memory High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). Only the lower six The TBLRD instruction is used to retrieve data from the bits of TBLPTRU are used with TBLPTRH and TBLPTRL program memory space and places it into data RAM. to form a 22-bit wide pointer. Table reads from program memory are performed one byte at a time. The contents of TBLPTR indicate a location in program memory space. The low-order 21bits allow the device TBLPTR points to a byte address in program space. to address the full 2 Mbytes of program memory space. Executing TBLRD places the byte pointed to into The 22nd bit allows access to the configuration space, TABLAT. including the device ID, user ID locations and the The internal program memory is typically organized by Configuration bits. words. The Least Significant bit of the address selects The TBLPTR register set is updated when executing a between the high and low bytes of the word. Figure7-2 TBLRD or TBLWT operation in one of four ways, based shows the interface between the internal program on the instruction’s arguments. These are detailed in memory and the TABLAT. Table7-1. These operations on the TBLPTR only affect A typical method for reading data from program memory the low-order 21bits. is shown in Example7-1. When a TBLRD or TBLWT is executed, all 22 bits of the TBLPTR determine which address in the program memory space is to be read or written to. DS39635C-page 90  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 7-2: READS FROM PROGRAM MEMORY Program Memory Space (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register TABLAT FETCH TBLRD (IR) Read Register EXAMPLE 7-1: READING A FLASH PROGRAM MEMORY WORD MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_WORD TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_EVEN TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVF WORD_ODD  2010 Microchip Technology Inc. DS39635C-page 91

PIC18F6310/6410/8310/8410 7.4 Writing to Program Memory Space 7.4.2 UNEXPECTED TERMINATION OF (PIC18F8310/8410 only) WRITE OPERATION If a write is terminated by an unplanned event, such as The table write operation outputs the contents of the loss of power or an unexpected Reset, the memory TBLPTR and TABLAT registers to the external address location just programmed should be verified and repro- and data busses of the external memory interface. grammed if needed. If the application writes to external Depending on the program memory mode selected, the operation may target any byte address in the device’s memory on a frequent basis, it may be necessary to memory space. What happens to this data depends implement an error trapping routine to handle these largely on the external memory device being used. unplanned events. For PIC18 devices with Enhanced Flash memory, a 7.5 Erasing External Memory single algorithm is used for writing to the on-chip program array. In the case of external devices, however, (PIC18F8310/8410 only) the algorithm is determined by the type of memory Erasure is implemented in different ways on different device and its requirements. In some cases, a specific devices. In many cases, it is possible to erase all or part instruction sequence must be sent before data can be of the memory by issuing a specific command. In some written or erased. Address and data demultiplexing, devices, it may be necessary to write ‘0’s to the locations chip select operation and write time requirements must to be erased. For specific information, consult the all be considered in creating the appropriate code. external memory device’s data sheet for clarification. The connection of the data and address busses to the memory device are dictated by the interface being 7.6 Writing and Erasing On-Chip used, the data bus width and the target device. When Program Memory (ICSP Mode) using a 16-bit data path, the algorithm must take into account the width of the target memory. While the on-chip program memory is read-only in Another important consideration is the write time normal operating mode, it can be written to and erased requirement of the target device. If this is longer than as a function of In-Circuit Serial Programming (ICSP). In the time that a TBLWT operation makes data available this mode, the TBLWT operation is used in all devices to on the interface, the algorithm must be adjusted to write to blocks of 64 bytes (32 words) at one time. Write lengthen this time. It may be possible, for example, to blocks are boundary-aligned with the code protection buy enough time by increasing the length of the wait blocks. Special commands are used to erase one or state on table operations. more code blocks of the program memory, or the entire In all cases, it is important to remember that instruc- device. tions in the program memory space are word-aligned, The TBLWT operation on write blocks is somewhat with the Least Significant bit always being written to an different than the word write operations for even-numbered address (LSb = 0). If data is being PIC18F8310/8410 devices described here. A more stored in the program memory space, word alignment complete description of block write operations is of the data is not required. provided in the Microchip document “Programming A complete overview of interface algorithms is beyond Specifications for PIC18FX410/X490 Flash MCUs” the scope of this data sheet. The best place for timing (DS39624). and instruction sequence requirements is the data sheet of the memory device in question. For additional 7.7 Flash Program Operation During information on algorithm design for the external Code Protection memory interface, refer to Microchip application note AN869, “External Memory Interfacing Techniques for See Section24.5 “Program Verification and Code the PIC18F8XXX” (DS00869). Protection” for details on code protection of Flash program memory. 7.4.1 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. DS39635C-page 92  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 7-2: REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 63 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 63 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 63 TABLAT Program Memory Table Latch 63 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.  2010 Microchip Technology Inc. DS39635C-page 93

PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 94  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 8.0 EXTERNAL MEMORY As implemented here, the interface is similar to that INTERFACE introduced on PIC18F8X20 microcontrollers. The most notable difference is that the interface on Note: The external memory interface is not PIC18F8310/8410 devices supports both 16-Bit and implemented on PIC18F6310 and Multiplexed 8-Bit Data Width modes; it does not sup- PIC18F6410 (64-pin) devices. port the 8-Bit Demultiplexed mode. The Bus Width mode is set by the BW Configuration bit when the The external memory interface allows the device to device is programmed and cannot be changed in access external memory devices (such as Flash, software. EPROM, SRAM, etc.) as program or data memory. It is The operation of the interface is controlled by the implemented with 28 pins, multiplexed across four I/O MEMCON register (Register8-1). Clearing the EBDIS ports. Three ports (PORTD, PORTE and PORTH) are bit (MEMCON<7>) enables the interface and disables multiplexed with the address/data bus for a total of 20 the I/O functions of the ports, as well as any other mul- available lines, while PORTJ is multiplexed with the tiplexed functions. Setting the bit disables the interface bus control signals. A list of the pins and their functions and enables the ports. is provided in Table8-1. For a more complete discussion of the operating modes that use the external memory interface, refer to Section8.1 “Program Memory Modes and the External Memory Interface”. REGISTER 8-1: MEMCON: MEMORY CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EBDIS — WAIT1 WAIT0 — — WM1 WM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EBDIS: External Bus Disable bit 1 = External system bus disabled, all external bus drivers are mapped as I/O ports 0 = External system bus enabled, I/O ports are disabled bit 6 Unimplemented: Read as ‘0’ bit 5-4 WAIT<1:0>: Table Reads and Writes Bus Cycle Wait Count bits 11 = Table reads and writes will wait 0 TCY 10 = Table reads and writes will wait 1 TCY 01 = Table reads and writes will wait 2 TCY 00 = Table reads and writes will wait 3 TCY bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 WM<1:0>: TBLWRT Operation with 16-Bit Bus Width bits 1x = Word Write mode: TABLAT0 and TABLAT1 word output; WRH active when TABLAT1 is written 01 = Byte Select mode: TABLAT data copied on both MSB and LSB; WRH and (UB or LB) will activate 00 = Byte Write mode: TABLAT data copied on both MSB and LSB; WRH or WRL will activate Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.  2010 Microchip Technology Inc. DS39635C-page 95

PIC18F6310/6410/8310/8410 TABLE 8-1: PIC18F8310/8410 EXTERNAL BUS – I/O PORT FUNCTIONS Name Port Bit Function RD0/AD0/PSP0 PORTD 0 Input/Output or System Bus Address bit 0 or Data bit 0 or Parallel Slave Port bit 0 RD1/AD1/PSP1 PORTD 1 Input/Output or System Bus Address bit 1 or Data bit 1 or Parallel Slave Port bit 1 RD2/AD2/PSP2 PORTD 2 Input/Output or System Bus Address bit 2 or Data bit 2 or Parallel Slave Port bit 2 RD3/AD3/PSP3 PORTD 3 Input/Output or System Bus Address bit 3 or Data bit 3 or Parallel Slave Port bit 3 RD4/AD4/PSP4 PORTD 4 Input/Output or System Bus Address bit 4 or Data bit 4 or Parallel Slave Port bit 4 RD5/AD5/PSP5 PORTD 5 Input/Output or System Bus Address bit 5 or Data bit 5 or Parallel Slave Port bit 5 RD6/AD6/PSP6 PORTD 6 Input/Output or System Bus Address bit 6 or Data bit 6 or Parallel Slave Port bit 6 RD7/AD7/PSP7 PORTD 7 Input/Output or System Bus Address bit 7 or Data bit 7 or Parallel Slave Port bit 7 RE0/AD8/RD PORTE 0 Input/Output or System Bus Address bit 8 or Data bit 8 or Parallel Slave Port Read Control pin RE1/AD9/WR PORTE 1 Input/Output or System Bus Address bit 9 or Data bit 9 or Parallel Slave Port Write Control pin RE2/AD10/CS PORTE 2 Input/Output or System Bus Address bit 10 or Data bit 10 or Parallel Slave Port Chip Select pin RE3/AD11 PORTE 3 Input/Output or System Bus Address bit 11 or Data bit 11 RE4/AD12 PORTE 4 Input/Output or System Bus Address bit 12 or Data bit 12 RE5/AD13 PORTE 5 Input/Output or System Bus Address bit 13 or Data bit 13 RE6/AD14 PORTE 6 Input/Output or System Bus Address bit 14 or Data bit 14 RE7/CCP2(1)/AD15 PORTE 7 Input/Output or Capture 2 Input/Compare 2 Output/PWM 2 Output pin or System Bus Address bit 15 or Data bit 15 RH0/AD16 PORTH 0 Input/Output or System Bus Address bit 16 RH1/AD17 PORTH 1 Input/Output or System Bus Address bit 17 RH2/AD18 PORTH 2 Input/Output or System Bus Address bit 18 RH3/AD19 PORTH 3 Input/Output or System Bus Address bit 19 RJ0/ALE PORTJ 0 Input/Output or System Bus Address Latch Enable (ALE) Control pin RJ1/OE PORTJ 1 Input/Output or System Bus Output Enable (OE) Control pin RJ2/WRL PORTJ 2 Input/Output or System Bus Write Low (WRL) Control pin RJ3/WRH PORTJ 3 Input/Output or System Bus Write High (WRH) Control pin RJ4/BA0 PORTJ 4 Input/Output or System Bus Byte Address bit 0 RJ5/CE PORTJ 5 Input/Output or System Bus Chip Enable (CE) Control pin RJ6/LB PORTJ 6 Input/Output or System Bus Lower Byte Enable (LB) Control pin RJ7/UB PORTJ 7 Input/Output or System Bus Upper Byte Enable (UB) Control pin Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared (all devices in Microcontroller mode). 8.1 Program Memory Modes and the In Microprocessor with Boot Block or Extended External Memory Interface Microcontroller mode, the external program memory bus shares I/O port functions on the pins. When the As previously noted, PIC18F8310/8410 devices are device is fetching or doing table read/table write capable of operating in any one of four program mem- operations on the external program memory space, the ory modes, using combinations of on-chip and external pins will have the external bus function. If the device is program memory. The functions of the multiplexed port fetching and accessing internal program memory pins depends on the program memory mode selected, locations only, the EBDIS control bit will change the as well as the setting of the EBDIS bit. pins from external memory to I/O port functions. When In Microcontroller mode, the bus is not active and the EBDIS = 0, the pins function as the external bus. When pins have their port functions only. Writes to the EBDIS = 1, the pins function as I/O ports. MEMCOM register are not permitted. If the device fetches or accesses external memory while In Microprocessor mode, the external bus is always EBDIS = 1, the pins will switch to external bus. If the active and the port pins have only the external bus EBDIS bit is set by a program executing from external function. memory, the action of setting the bit will be delayed until the program branches into the internal memory. At that time, the pins will change from external bus to I/O ports. DS39635C-page 96  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 When the device is executing out of internal memory For all 16-bit modes, the Address Latch Enable (ALE) (EBDIS = 0) in Microprocessor with Boot Block mode or pin indicates that the address bits, A<15:0>, are avail- Extended Microcontroller mode, the control signals will able on the external memory interface bus. Following the NOT be active. They will go to a state where the address latch, the Output Enable signal (OE) will enable AD<15:0> and A<19:16> are tri-state; the CE, OE, WRH, both bytes of program memory at once to form a 16-bit WRL, UB and LB signals are ‘1’; ALE and BA0 are ‘0’. instruction word. The Chip Enable signal (CE) is active Note that only those pins associated with the current at any time that the microcontroller accesses external address width are forced to tri-state; the other pins con- memory, whether reading or writing; it is inactive tinue to function as I/O. In the case of a 16-bit address (asserted high) whenever the device is in Sleep mode. width, for example, only AD<15:0> (PORTD and In Byte Select mode, JEDEC standard Flash memories PORTE) are affected; A<19:16> (PORTH<3:0>) con- will require BA0 for the byte address line and one I/O line tinue to function as I/O. In all external memory modes, to select between Byte and Word mode. The other 16-bit the bus takes priority over any other peripherals that modes do not need BA0. JEDEC standard static RAM may share pins with it. This includes the Parallel Slave memories will use the UB or LB signals for byte selection. Port and serial communications modules which would otherwise take priorityover the I/O port. 8.2.1 16-BIT BYTE WRITE MODE Figure8-1 shows an example of 16-Bit Byte Write 8.2 16-Bit Mode mode for PIC18F8310/8410 devices. This mode is In 16-bit mode, the external memory interface can be used for two separate 8-bit memories connected for connected to external memories in three different 16-bit operation. This generally includes basic EPROM configurations: and Flash devices. It allows table writes to byte-wide external memories. • 16-Bit Byte Write During a TBLWT instruction cycle, the TABLAT data is • 16-Bit Word Write presented on the upper and lower bytes of the • 16-Bit Byte Select AD<15:0> bus. The appropriate WRH or WRL control The configuration to be used is determined by the line is strobed on the LSb of the TBLPTR. WM<1:0> bits in the MEMCON register (MEMCON<1:0>). These three different configurations allow the designer maximum flexibility in using both 8-bit and 16-bit devices with 16-bit data. FIGURE 8-1: 16-BIT BYTE WRITE MODE EXAMPLE D<7:0> PIC18F8410 (MSB) (LSB) A<19:0> AD<7:0> 373 A<x:0> A<x:0> D<15:8> D<7:0> D<7:0> D<7:0> CE CE AD<15:8> 373 OE WR(1) OE WR(1) ALE A<19:16> CE OE WRH WRL Address Bus Data Bus Control Lines Note 1: This signal only applies to table writes. See Section7.1 “Table Reads and Table Writes”.  2010 Microchip Technology Inc. DS39635C-page 97

PIC18F6310/6410/8310/8410 8.2.2 16-BIT WORD WRITE MODE During a TBLWT cycle to an odd address (TBLPTR<0>= 1), the TABLAT data is presented on Figure8-2 shows an example of 16-Bit Word Write the upper byte of the AD<15:0> bus. The contents of mode for PIC18F8410 devices. This mode is used for the holding latch are presented on the lower byte of the word-wide memories, which includes some of the AD<15:0> bus. EPROM and Flash type memories. This mode allows opcode fetches and table reads from all forms of 16-bit The WRH signal is strobed for each write cycle; the memory and table writes to any type of word-wide WRL pin is unused. The signal on the BA0 pin indicates external memories. This method makes a distinction the LSb of TBLPTR, but it is left unconnected. Instead, between TBLWT cycles to even or odd addresses. the UB and LB signals are active to select both bytes. The obvious limitation to this method is that the table During a TBLWT cycle to an even address write must be done in pairs on a specific word boundary (TBLPTR<0>= 0), the TABLAT data is transferred to a to correctly write a word location. holding latch and the external address data bus is tri-stated for the data portion of the bus cycle. No write signals are activated. FIGURE 8-2: 16-BIT WORD WRITE MODE EXAMPLE PIC18F8410 AD<7:0> 373 A<20:1> A<x:0> JEDEC Word EPROM Memory D<15:0> D<15:0> CE OE WR(1) AD<15:8> 373 ALE A<19:16> CE OE WRH Address Bus Data Bus Control Lines Note 1: This signal only applies to table writes. See Section7.1 “Table Reads and Table Writes”. DS39635C-page 98  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 8.2.3 16-BIT BYTE SELECT MODE Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC Figure8-3 shows an example of 16-Bit Byte Select standard Flash memories require that a controller I/O mode. This mode allows table write operations to port pin be connected to the memory’s BYTE/WORD word-wide external memories with byte selection pin to provide the select signal. They also use the BA0 capability. This generally includes both word-wide signal from the controller as a byte address. JEDEC Flash and SRAM devices. standard static RAM memories, on the other hand, use During a TBLWT cycle, the TABLAT data is presented the UB or LB signals to select the byte. on the upper and lower byte of the AD<15:0> bus. The WRH signal is strobed for each write cycle; the WRL pin is not used. The BA0 or UB/LB signals are used to select the byte to be written, based on the Least Significant bit of the TBLPTR register. FIGURE 8-3: 16-BIT BYTE SELECT MODE EXAMPLE PIC18F8410 A<20:1> AD<7:0> 373 A<x:1> JEDEC Word Flash Memory D<15:0> D<15:0> AD<15:8> 138(2) CE 373 A0 ALE BYTE/WORD OE WR(1) A<19:16> OE WRH WRL A<20:1> A<x:1> JEDEC Word BA0 SRAM Memory I/O D<15:0> CE D<15:0> LB LB UB UB OE WR(1) Address Bus Data Bus Control Lines Note 1: This signal only applies to table writes. See Section7.1 “Table Reads and Table Writes”. 2: Demultiplexing is only required when multiple memory devices are accessed.  2010 Microchip Technology Inc. DS39635C-page 99

PIC18F6310/6410/8310/8410 8.2.4 16-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure8-4 through Figure8-6. FIGURE 8-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD (MICROPROCESSOR MODE) Apparent Q Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q4 Q4 Q4 Q4 Actual Q Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:16> 00h 0Ch AD<15:0> 3AABh 0E55h CF33h 9256h BA0 ALE OE WRH ‘1’ ‘1’ WRL ‘1’ ‘1’ CE ‘0’ ‘0’ 1 TCY Wait Memory Opcode Fetch Table Read Cycle MOVLW 55h of 92h from 007556h from 199E67h Instruction TBLRD Cycle 1 TBLRD Cycle 2 Execution FIGURE 8-5: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:16> 0Ch AD<15:0> CF33h 9256h CE ALE OE Memory Opcode Fetch Opcode Fetch TBLRD 92h Opcode Fetch Cycle TBLRD * MOVLW 55h from 199E67h ADDLW 55h from 000100h from 000102h from 000104h Instruction INST(PC – 2) TBLRD Cycle 1 TBLRD Cycle 2 MOVLW Execution DS39635C-page 100  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 8-6: EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 A<19:16> 00h 00h AD<15:0> 3AAAh 0003h 3AABh 0E55h CE ALE OE Memory Opcode Fetch Opcode Fetch Sleep Mode, Bus Inactive(1) Cycle SLEEP MOVLW 55h from 007554h from 007556h Instruction Execution INST(PC – 2) SLEEP Note 1: Bus becomes inactive regardless of power-managed mode entered when SLEEP is executed.  2010 Microchip Technology Inc. DS39635C-page 101

PIC18F6310/6410/8310/8410 8.3 8-Bit Mode The Address Latch Enable (ALE) pin indicates that the address bits, A<15:0>, are available on the external The external memory interface implemented in memory interface bus. The Output Enable signal (OE) PIC18F8410 devices operates only in 8-Bit Multiplexed will enable one byte of program memory for a portion of mode; data shares the 8 Least Significant bits of the the instruction cycle, then BA0 will change and the address bus. second byte will be enabled to form the 16-bit instruc- Figure8-1 shows an example of 8-Bit Multiplexed tion word. The Least Significant bit of the address, BA0, mode for PIC18F8410 devices. This mode is used for must be connected to the memory devices in this a single 8-bit memory connected for 16-bit operation. mode. The Chip Enable signal (CE) is active at any The instructions will be fetched as two 8-bit bytes on a time that the microcontroller accesses external shared data/address bus. The two bytes are sequen- memory, whether reading or writing; it is inactive tially fetched within one instruction cycle (TCY). (asserted high) whenever the device is in Sleep mode. Therefore, the designer must choose external memory This generally includes basic EPROM and Flash devices. devices according to timing calculations based on It allows table writes to byte-wide external memories. 1/2TCY (2 times the instruction rate). For proper mem- During a TBLWT instruction cycle, the TABLAT data is ory speed selection, glue logic propagation delay times presented on the upper and lower bytes of the must be considered along with setup and hold times. AD<15:0> bus. The appropriate level of the BA0 control line is strobed on the LSb of the TBLPTR. FIGURE 8-7: 8-BIT MULTIPLEXED MODE EXAMPLE D<7:0> PIC18F8410 A<19:0> AD<7:0> 373 A<x:1> ALE D<15:8> A0 D<7:0> AD<15:8> CE A<19:16> OE WR(2) BA0 CE OE WRL Address Bus Data Bus Control Lines Note 1: Upper order address bits are used only for 20-bit address width. The upper AD byte is used for all address widths except 8-bit. 2: This signal only applies to table writes. See Section7.1 “Table Reads and Table Writes”. DS39635C-page 102  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 8.3.1 8-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure8-4 through Figure8-6. FIGURE 8-8: EXTERNAL MEMORY BUS TIMING FOR TBLRD (MICROPROCESSOR MODE) Apparent Q Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q4 Q4 Q4 Q4 Actual Q Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:16> 00h 0Ch AD<15:8> 3Ah CFh AD<7:0> ABh 0Eh 55h 33h 92h BA0 ALE OE WRL ‘1’ ‘1’ CE ‘0’ ‘0’ 1 TCY Wait Memory Opcode Fetch Table Read Cycle MOVLW 55h of 92h from 007556h from 199E67h Instruction Execution TBLRD Cycle 1 TBLRD Cycle 2 FIGURE 8-9: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:16> 0Ch AD<15:8> CFh AD<7:0> 33h 92h CE ALE OE Memory Opcode Fetch Opcode Fetch TBLRD 92h Opcode Fetch Cycle TBLRD * MOVLW 55h from 199E67h ADDLW 55h from 000100h from 000102h from 000104h Instruction Execution INST(PC – 2) TBLRD Cycle 1 TBLRD Cycle 2 MOVLW  2010 Microchip Technology Inc. DS39635C-page 103

PIC18F6310/6410/8310/8410 FIGURE 8-10: EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 A<19:16> 00h 00h AD<15:8> 3Ah 3Ah AD<7:0> AAh 00h 03h ABh 0Eh 55h CE ALE OE Memory Opcode Fetch Opcode Fetch Sleep Mode, Bus Inactive(1) Cycle SLEEP MOVLW 55h from 007554h from 007556h Instruction Execution INST(PC – 2) SLEEP Note 1: Bus becomes inactive regardless of power-managed mode entered when SLEEP is executed. DS39635C-page 104  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 8.4 Operation in Power-Managed If operations in a lower power Run mode are antici- Modes pated, users should provide in their applications for adjusting memory access times at the lower clock In alternate, power-managed Run modes, the external speeds. bus continues to operate normally. If a clock source In Sleep and Idle modes, the microcontroller core does with a lower speed is selected, bus operations will run not need to access data; bus operations are sus- at that speed. In these cases, excessive access times pended. The state of the external bus is frozen with the for the external memory may result if wait states have address/data pins and most of the control pins holding been enabled and added to external memory at the same state they were in when the mode was operations. invoked. The only potential changes are the CE, LB and UB pins which are held at logic high. TABLE 8-2: REGISTERS ASSOCIATED WITH THE EXTERNAL MEMORY INTERFACE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page MEMCON EBDIS — WAIT1 WAIT0 — — WM1 WM0 65 CONFIG3L WAIT BW — — — — PM1 PM0 285 CONFIG3H MCLRE — — — — LPT1OSC — CCP2MX 286 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for the external memory interface.  2010 Microchip Technology Inc. DS39635C-page 105

PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 106  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 9.0 8 x 8 HARDWARE MULTIPLIER EXAMPLE 9-1: 8 x 8 UNSIGNED MULTIPLY ROUTINE 9.1 Introduction MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 -> All PIC18 devices include an 8 x 8 hardware multiplier ; PRODH:PRODL as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair PRODH:PRODL. The multiplier’s EXAMPLE 9-2: 8 x 8 SIGNED MULTIPLY operation does not affect any flags in the STATUS ROUTINE register. MOVF ARG1, W Making multiplication a hardware operation allows it to MULWF ARG2 ; ARG1 * ARG2 -> be completed in a single instruction cycle. This has the ; PRODH:PRODL advantages of higher computational throughput and BTFSC ARG2, SB ; Test Sign Bit reduced code size for multiplication algorithms and SUBWF PRODH, F ; PRODH = PRODH allows the PIC18 devices to be used in many applica- ; - ARG1 tions previously reserved for digital signal processors. MOVF ARG2, W A comparison of various hardware and software BTFSC ARG1, SB ; Test Sign Bit multiply operations, along with the savings in memory SUBWF PRODH, F ; PRODH = PRODH and execution time, is shown in Table9-1. ; - ARG2 9.2 Operation Example9-1 shows the instruction sequence for an 8x8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example9-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 9-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Program Time Cycles Routine Multiply Method Memory (Max) (Words) @ 40 MHz @ 10 MHz @ 4 MHz Without Hardware Multiply 13 69 6.9 s 27.6 s 69 s 8 x 8 Unsigned Hardware Multiply 1 1 100 ns 400 ns 1 s Without Hardware Multiply 33 91 9.1 s 36.4 s 91 s 8 x 8 Signed Hardware Multiply 6 6 600 ns 2.4 s 6 s Without Hardware Multiply 21 242 24.2 s 96.8 s 242 s 16 x 16 Unsigned Hardware Multiply 28 28 2.8 s 11.2 s 28 s Without Hardware Multiply 52 254 25.4 s 102.6 s 254 s 16 x 16 Signed Hardware Multiply 35 40 4.0 s 16.0 s 40 s  2010 Microchip Technology Inc. DS39635C-page 107

PIC18F6310/6410/8310/8410 Example9-3 shows the sequence to do a 16 x 16 EQUATION 9-2: 16 x 16 SIGNED unsigned multiplication. Equation9-1 shows the MULTIPLICATION algorithm that is used. The 32-bit result is stored in four ALGORITHM registers (RES3:RES0). RES3:RES0=ARG1H:ARG1L  ARG2H:ARG2L =(ARG1H  ARG2H  216) + EQUATION 9-1: 16 x 16 UNSIGNED (ARG1H  ARG2L  28) + MULTIPLICATION (ARG1L  ARG2H  28) + ALGORITHM (ARG1L  ARG2L) + RES3:RES0 = ARG1H:ARG1L  ARG2H:ARG2L (-1  ARG2H<7>  ARG1H:ARG1L  216) + = (ARG1H  ARG2H  216) + (-1  ARG1H<7>  ARG2H:ARG2L  216) (ARG1H  ARG2L  28) + (ARG1L  ARG2H  28) + EXAMPLE 9-4: 16 x 16 SIGNED (ARG1L  ARG2L) MULTIPLY ROUTINE MOVF ARG1L, W MULWF ARG2L ; ARG1L * ARG2L -> EXAMPLE 9-3: 16 x 16 UNSIGNED ; PRODH:PRODL MULTIPLY ROUTINE MOVFF PRODH, RES1 ; MOVF ARG1L, W MOVFF PRODL, RES0 ; MULWF ARG2L ; ARG1L * ARG2L-> ; ; PRODH:PRODL MOVF ARG1H, W MOVFF PRODH, RES1 ; MULWF ARG2H ; ARG1H * ARG2H -> MOVFF PRODL, RES0 ; ; PRODH:PRODL ; MOVFF PRODH, RES3 ; MOVF ARG1H, W MOVFF PRODL, RES2 ; MULWF ARG2H ; ARG1H * ARG2H-> ; ; PRODH:PRODL MOVF ARG1L, W MOVFF PRODH, RES3 ; MULWF ARG2H ; ARG1L * ARG2H -> MOVFF PRODL, RES2 ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1L, W ADDWF RES1, F ; Add cross MULWF ARG2H ; ARG1L * ARG2H-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; MOVF ARG1H, W ; CLRF WREG ; MULWF ARG2L ; ARG1H * ARG2L -> ADDWFC RES3, F ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1H, W ; ADDWF RES1, F ; Add cross MULWF ARG2L ; ARG1H * ARG2L-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? CLRF WREG ; BRA SIGN_ARG1 ; no, check ARG1 ADDWFC RES3, F ; MOVF ARG1L, W ; SUBWF RES2 ; Example9-4 shows the sequence to do a 16 x 16 MOVF ARG1H, W ; signed multiply. Equation9-2 shows the algorithm SUBWFB RES3 used. The 32-bit result is stored in four registers ; SIGN_ARG1 (RES3:RES0). To account for the sign bits of the BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? arguments, the MSb for each argument pair is tested BRA CONT_CODE ; no, done and the appropriate subtractions are done. MOVF ARG2L, W ; SUBWF RES2 ; MOVF ARG2H, W ; SUBWFB RES3 ; CONT_CODE DS39635C-page 108  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 10.0 INTERRUPTS When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are The PIC18F6310/6410/8310/8410 devices have compatible with PIC® mid-range devices. In multiple interrupt sources and an interrupt priority Compatibility mode, the interrupt priority bits for each feature that allows most interrupt sources to be source have no effect. INTCON<6> is the PEIE bit, assigned a high-priority level or a low-priority level. The which enables/disables all peripheral interrupt sources. high-priority interrupt vector is at 0008h and the low- INTCON<7> is the GIE bit, which enables/disables all priority interrupt vector is at 0018h. High-priority interrupt sources. All interrupts branch to address interrupt events will interrupt any low-priority interrupts 0008h in Compatibility mode. that may be in progress. When an interrupt is responded to, the global interrupt There are ten registers which are used to control enable bit is cleared to disable further interrupts. If the interrupt operation. These registers are: IPEN bit is cleared, this is the GIE bit. If interrupt priority • RCON levels are used, this will either be the GIEH or GIEL bit. High-priority interrupt sources can interrupt a low- • INTCON priority interrupt. Low-priority interrupts are not • INTCON2 processed while high-priority interrupts are in progress. • INTCON3 The return address is pushed onto the stack and the • PIR1, PIR2, PIR3 PC is loaded with the interrupt vector address (0008h • PIE1, PIE2, PIE3 or 0018h). Once in the Interrupt Service Routine, the • IPR1, IPR2, IPR3 source(s) of the interrupt can be determined by polling It is recommended that the Microchip header files sup- the interrupt flag bits. The interrupt flag bits must be plied with MPLAB® IDE be used for the symbolic bit cleared in software before re-enabling interrupts to names in these registers. This allows the assembler/ avoid recursive interrupts. compiler to automatically take care of the placement of The “return from interrupt” instruction, RETFIE, exits these bits within the specified register. the interrupt routine and sets the GIE bit (GIEH or GIEL In general, interrupt sources have three bits to control if priority levels are used), which re-enables interrupts. their operation. They are: For external interrupt events, such as the INTx pins or • Flag bit to indicate that an interrupt event the PORTB input change interrupt, the interrupt latency occurred will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. • Enable bit that allows program execution to Individual interrupt flag bits are set, regardless of the branch to the interrupt vector address when the status of their corresponding enable bit or the GIE bit. flag bit is set • Priority bit to select high priority or low priority Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while The interrupt priority feature is enabled by setting the any interrupt is enabled. Doing so may IPEN bit (RCON<7>). When interrupt priority is cause erratic microcontroller behavior. enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 0008h or 0018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits.  2010 Microchip Technology Inc. DS39635C-page 109

PIC18F6310/6410/8310/8410 FIGURE 10-1: PIC18F6310/6410/8310/8410 INTERRUPT LOGIC TMR0IF Wake-up if in TMR0IE Idle or Sleep modes TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE Interrupt to CPU INT1IP Vector to Location INT2IF PIR1<7:0> INT2IE 0008h PIE1<7:0> INT2IP IPR1<7:0> INT3IF INT3IE INT3IP GIEH/GIE PIR2<7:6, 3:0> PIE2<7:6, 3:0> IPR2<7:6, 3:0> IPE PIR3<5:4, 0> IPEN PIE3<5:4, 0> IPR3<5:4, 0> GIEL/PEIE IPEN High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 3:0> PIE2<7:6, 3:0> IPR2<7:6, 3:0> Interrupt to CPU PIR3<5:4, 0> TTMMRR00IIEF IPEN V00e1c8tohr to Location PIE3<5:4, 0> TMR0IP IPR3<5:4, 0> RBIF RBIE RBIP GIEH/GIE GIEL/PEIE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP DS39635C-page 110  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 10.1 INTCON Registers Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of The INTCON registers are readable and writable its corresponding enable bit or the global registers which contain various enable, priority and flag interrupt enable bit. User software should bits. ensure that the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. REGISTER 10-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high-priority interrupts 0 = Disables all interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low-priority peripheral interrupts 0 = Disables all low-priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit(1) 1 = At least one of the RB<7:4> pins changed state (must be cleared in software) 0 = None of the RB<7:4> pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared.  2010 Microchip Technology Inc. DS39635C-page 111

PIC18F6310/6410/8310/8410 REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 INTEDG3: External Interrupt 3 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 INT3IP: INT3 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39635C-page 112  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 REGISTER 10-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 INT3IE: INT3 External Interrupt Enable bit 1 = Enables the INT3 external interrupt 0 = Disables the INT3 external interrupt bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 INT3IF: INT3 External Interrupt Flag bit 1 = The INT3 external interrupt occurred (must be cleared in software) 0 = The INT3 external interrupt did not occur bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.  2010 Microchip Technology Inc. DS39635C-page 113

PIC18F6310/6410/8310/8410 10.2 PIR Registers Note1: Interrupt flag bits are set when an inter- rupt condition occurs, regardless of the The PIR registers contain the individual flag bits for the state of its corresponding enable bit or the peripheral interrupts. Due to the number of peripheral Global Interrupt Enable bit, GIE interrupt sources, there are three Peripheral Interrupt (INTCON<7>). Request (Flag) registers (PIR1, PIR2, PIR3). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. REGISTER 10-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RC1IF: EUSART Receive Interrupt Flag bit 1 = The EUSART receive buffer, RCREG1, is full (cleared when RCREG1 is read) 0 = The EUSART receive buffer is empty bit 4 TX1IF: EUSART Transmit Interrupt Flag bit 1 = The EUSART transmit buffer, TXREG1, is empty (cleared when TXREG1 is written) 0 = The EUSART transmit buffer is full bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow DS39635C-page 114  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 REGISTER 10-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF CMIF — — BCLIF HLVDIF TMR3IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = Device clock operating bit 6 CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed bit 5-4 Unimplemented: Read as ‘0’ bit 3 BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred bit 2 HLVDIF: High/Low-Voltage Detect Interrupt Flag bit 1 = A low-voltage condition occurred (must be cleared in software) 0 = The device voltage is above the Low-Voltage Detect trip point bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow bit 0 CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode.  2010 Microchip Technology Inc. DS39635C-page 115

PIC18F6310/6410/8310/8410 REGISTER 10-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 U-0 U-0 R-0 R-0 U-0 U-0 U-0 U-0 — — RC2IF TX21F — — — CCP3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IF: AUSART Receive Interrupt Flag bit 1 = The AUSART receive buffer, RCREG2, is full (cleared when RCREG2 is read) 0 = The AUSART receive buffer is empty bit 4 TX2IF: AUSART Transmit Interrupt Flag bit 1 = The AUSART transmit buffer, TXREG2, is empty (cleared when TXREG2 is written) 0 = The AUSART transmit buffer is full bit 3-1 Unimplemented: Read as ‘0’ bit 0 CCP3IF: CCP3 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. DS39635C-page 116  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 10.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 10-7: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RC1IE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt bit 4 TX1IE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt  2010 Microchip Technology Inc. DS39635C-page 117

PIC18F6310/6410/8310/8410 REGISTER 10-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE CMIE — — BCLIE HLVDIE TMR3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5-4 Unimplemented: Read as ‘0’ bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS39635C-page 118  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 REGISTER 10-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 U-0 R-0 R-0 U-0 U-0 U-0 R/W-0 — — RC2IE TX2IE — — — CCP3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IE: AUSART Receive Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 TX2IE: AUSART Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3-1 Unimplemented: Read as ‘0’ bit 0 CCP3IE: CCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled  2010 Microchip Technology Inc. DS39635C-page 119

PIC18F6310/6410/8310/8410 10.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 10-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RC1IP: EUSART Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX1IP: EUSART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority’ bit 2 CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS39635C-page 120  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 REGISTER 10-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP CMIP — — BCLIP HLVDIP TMR3IP CCP2IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority bit 5-4 Unimplemented: Read as ‘0’ bit 3 BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 HLVDIP: High/Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority  2010 Microchip Technology Inc. DS39635C-page 121

PIC18F6310/6410/8310/8410 REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 U-0 R-1 R-1 U-0 U-0 U-0 R/W-1 — — RC2IP TX21P — — — CCP3IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IP: AUSART Receive Priority Flag bit 1 = High priority 0 = Low priority bit 4 TX2IP: AUSART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3-1 Unimplemented: Read as ‘0’ bit 0 CCP3IP: CCP3 Interrupt Priority bit 1 = High priority 0 = Low priority DS39635C-page 122  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 10.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN). REGISTER 10-13: RCON REGISTER R/W-0 R/W-1 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN SBOREN — RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: Software BOR Enable bit For details of bit operation and Reset state, see Register5-1. bit 5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register5-1. bit 3 TO: Watchdog Timer Time-out Flag bit For details of bit operation, see Register5-1. bit 2 PD: Power-Down Detection Flag bit For details of bit operation, see Register5-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register5-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register5-1.  2010 Microchip Technology Inc. DS39635C-page 123

PIC18F6310/6410/8310/8410 10.6 INTx Pin Interrupts 10.7 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1, RB2/ In 8-bit mode (which is the default), an overflow in the INT2 and RB3/INT3 pins are edge-triggered. If the TMR0 register (FFh00h) will set flag bit, TMR0IF. In corresponding INTEDGx bit in the INTCON2 register is 16-bit mode, an overflow in the TMR0H:TMR0L register set (= 1), the interrupt is triggered by a rising edge; if pair (FFFFh 0000h) will set TMR0IF. The interrupt can the bit is clear, the trigger is on the falling edge. When be enabled/disabled by setting/clearing enable bit, a valid edge appears on the RBx/INTx pin, the TMR0IE (INTCON<5>). Interrupt priority for Timer0 is corresponding flag bit, INTxIF, is set. This interrupt can determined by the value contained in the interrupt prior- be disabled by clearing the corresponding enable bit, ity bit, TMR0IP (INTCON2<2>). See Section12.0 INTxIE. Flag bit, INTxIF, must be cleared in software in “Timer0 Module” for further details on the Timer0 the Interrupt Service Routine before re-enabling the module. interrupt. 10.8 PORTB Interrupt-on-Change All external interrupts (INT0, INT1, INT2 and INT3) can wake-up the processor from the power-managed An input change on PORTB<7:4> sets flag bit, RBIF modes if bit, INTxIE, was set prior to going into power- (INTCON<0>). The interrupt can be enabled/disabled managed modes. If the Global Interrupt Enable bit, by setting/clearing enable bit, RBIE (INTCON<3>). GIE, is set, the processor will branch to the interrupt Interrupt priority for PORTB interrupt-on-change is vector following wake-up. determined by the value contained in the interrupt Interrupt priority for INT1, INT2 and INT3 is determined priority bit, RBIP (INTCON2<0>). by the value contained in the interrupt priority bits, INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and 10.9 Context Saving During Interrupts INT3IP (INTCON2<1>). There is no priority bit associated with INT0. It is always a high-priority During interrupts, the return PC address is saved on interrupt source. the stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (see Section6.3 “Data Memory Organization”), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user’s application, other registers may also need to be saved. Example10-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 10-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in virtual bank MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR ; Restore BSR MOVF W_TEMP, W ; Restore WREG MOVFF STATUS_TEMP, STATUS ; Restore STATUS DS39635C-page 124  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 11.0 I/O PORTS 11.1 PORTA, TRISA and LATA Registers Depending on the device selected and features enabled, there are up to nine ports available. Some PORTA is an 8-bit wide, bidirectional port. The corre- pins of the I/O ports are multiplexed with an alternate sponding Data Direction register is TRISA. Setting a function from the peripheral features on the device. In TRISA bit (= 1) will make the corresponding PORTA pin general, when a peripheral is enabled, that pin may not an input (i.e., put the corresponding output driver in a be used as a general purpose I/O pin. High-Impedance mode). Clearing a TRISA bit (= 0) will Each port has three registers for its operation. These make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). registers are: • TRIS register (Data Direction register) Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. • PORT register (reads the levels on the pins of the device) The Output Latch register (LATA) is also memory • LAT register (Output Latch register) mapped. Read-modify-write operations on the LATA register read and write the latched output value for The Output Latch (LAT register) is useful for PORTA. read-modify-write operations on the value that the I/O The RA4 pin is multiplexed with the Timer0 module pins are driving. clock input to become the RA4/T0CKI pin. Pins, RA6 A simplified model of a generic I/O port, without the and RA7, are multiplexed with the main oscillator pins. interfaces to other peripherals, is shown in Figure11-1. They are enabled as oscillator or I/O pins by the selec- tion of the main oscillator in the Configuration register FIGURE 11-1: GENERIC I/O PORT (see Section24.1 “Configuration Bits” for details). OPERATION When they are not used as port pins, RA6 and RA7 and their associated TRIS and LAT bits are read as ‘0’. RD LAT The other PORTA pins are multiplexed with the analog VREF+ and VREF- inputs. The operation of pins, Data RA<5:0>, as A/D Converter inputs is selected by Bus D Q clearing or setting the PCFG<3:0> control bits in the WR LAT I/O pin(1) ADCON1 register. or Port CK Note: On a Power-on Reset, RA5 and RA<3:0> Data Latch are configured as analog inputs and read D Q as ‘0’. RA4 is configured as a digital input. The RA4/T0CKI pin is a Schmitt Trigger input and an WR TRIS CK open-drain output. All other PORTA pins have TTL TRIS Latch Input input levels and full CMOS output drivers. Buffer The TRISA register controls the direction of the PORTA RD TRIS pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are Q D maintained set when using them as analog inputs. ENEN EXAMPLE 11-1: INITIALIZING PORTA RD Port CLRF PORTA ; Initialize PORTA by ; clearing output ; data latches Note1: I/O pins have diode protection to VDD and VSS. CLRF LATA ; Alternate method ; to clear output ; data latches MOVLW 07h ; Configure A/D MOVWF ADCON1 ; for digital inputs MOVWF 07h ; Configure comparators MOVWF CMCON ; for digital input MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs  2010 Microchip Technology Inc. DS39635C-page 125

PIC18F6310/6410/8310/8410 TABLE 11-1: PORTA FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RA0/AN0 RA0 0 O DIG LATA<0> data output; not affected by analog input. 1 I TTL PORTA<0> data input; disabled when analog input enabled. AN0 1 I ANA A/D Input Channel 0. Default input configuration on POR; does not affect digital output. RA1/AN1 RA1 0 O DIG LATA<1> data output; not affected by analog input. 1 I TTL PORTA<1> data input; disabled when analog input enabled. AN1 1 I ANA A/D Input Channel 1. Default input configuration on POR; does not affect digital output. RA2/AN2/VREF- RA2 0 O DIG LATA<2> data output; not affected by analog input. Disabled when CVREF output enabled. 1 I TTL PORTA<2> data input. Disabled when analog functions enabled; disabled when CVREF output enabled. AN2 1 I ANA A/D Input Channel 2. Default input configuration on POR; not affected by analog output. VREF- 1 I ANA Comparator voltage reference low input and A/D voltage reference low input. RA3/AN3/VREF+ RA3 0 O DIG LATA<3> data output; not affected by analog input. 1 I TTL PORTA<3> data input; disabled when analog input enabled. AN3 1 I ANA A/D Input Channel 3. Default input configuration on POR. VREF+ 1 I ANA Comparator voltage reference high input and A/D voltage reference high input. RA4/T0CKI RA4 0 O DIG LATA<4> data output 1 I ST PORTA<4> data input; default configuration on POR. T0CKI x I ST Timer0 clock input. RA5/AN4/HLVDIN RA5 0 O DIG LATA<5> data output; not affected by analog input. 1 I TTL PORTA<5> data input; disabled when analog input enabled. AN4 1 I ANA A/D Input Channel 4. Default configuration on POR. HLVDIN 1 I ANA High/Low-Voltage Detect external trip point input. OSC2/CLKO/RA6 OSC2 x O ANA Main oscillator feedback output connection (XT, HS and LP modes). CLKO x O DIG System cycle clock output (FOSC/4) in all oscillator modes except RCIO, INTIO2 and ECIO. RA6 0 O DIG LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only. 1 I TTL PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only. OSC1/CLKI/RA7 OSC1 x I ANA Main oscillator input connection. CLKI x I ANA Main clock input connection. RA7 0 O DIG LATA<7> data output. Disabled in External Oscillator modes. 1 I TTL PORTA<7> data input. Disabled in External Oscillator modes. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST= Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). DS39635C-page 126  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 11-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 66 LATA LATA7(1) LATA6(1) LATA Output Latch Register 66 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Register 66 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 64 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA<7:6> and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’.  2010 Microchip Technology Inc. DS39635C-page 127

PIC18F6310/6410/8310/8410 11.2 PORTB, TRISB and Four of the PORTB pins (RB<7:4>) have an LATB Registers interrupt-on-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any PORTB is an 8-bit wide, bidirectional port. The corre- RB<7:4> pin configured as an output is excluded from sponding Data Direction register is TRISB. Setting a the interrupt-on-change comparison). The input pins (of TRISB bit (= 1) will make the corresponding PORTB RB<7:4>) are compared with the old value latched on pin an input (i.e., put the corresponding output driver in the last read of PORTB. The “mismatch” outputs of a High-Impedance mode). Clearing a TRISB bit (= 0) RB<7:4> are ORed together to generate the RB Port will make the corresponding PORTB pin an output (i.e., Change Interrupt with Flag bit, RBIF (INTCON<0>). put the contents of the output latch on the selected pin). This interrupt can wake the device from The Output Latch register (LATB) is also memory power-managed modes. The user, in the Interrupt mapped. Read-modify-write operations on the LATB Service Routine, can clear the interrupt in the following register read and write the latched output value for manner: PORTB. a) Any read or write of PORTB (except with the MOVFF (ANY), PORTB instruction). This will EXAMPLE 11-2: INITIALIZING PORTB end the mismatch condition. CLRF PORTB ; Initialize PORTB by b) Wait one TCY delay (for example, execute one ; clearing output NOP instruction). ; data latches c) Clear flag bit, RBIF. CLRF LATB ; Alternate method ; to clear output A mismatch condition will continue to set flag bit, RBIF. ; data latches Reading PORTB will end the mismatch condition and MOVLW 0CFh ; Value used to allow flag bit, RBIF, to be cleared after a one TCY delay. ; initialize data ; direction The interrupt-on-change feature is recommended for MOVWF TRISB ; Set RB<3:0> as inputs wake-up on key depression operation and operations ; RB<5:4> as outputs where PORTB is only used for the interrupt-on-change ; RB<7:6> as inputs feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. Each of the PORTB pins has a weak internal pull-up. A For 80-pin devices, RB3 can be configured as the single control bit can turn on all the pull-ups. This is alternate peripheral pin for the CCP2 module by performed by clearing bit, RBPU (INTCON2<7>). The clearing the CCP2MX Configuration bit. This applies weak pull-up is automatically turned off when the port only when the device is in one of the operating modes pin is configured as an output. The pull-ups are other than the default Microcontroller mode. If the disabled on a Power-on Reset. device is in Microcontroller mode, the alternate assignment for CCP2 is RE7. As with other CCP2 con- figurations, the user must ensure that the TRISB<3> bit is set appropriately for the intended operation. DS39635C-page 128  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 11-3: PORTB FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RB0/INT0 RB0 0 O DIG LATB<0> data output. 1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. INT0 1 I ST External Interrupt 0 input. RB1/INT1 RB1 0 O DIG LATB<1> data output. 1 I TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared. INT1 1 I ST External Interrupt 1 input. RB2/INT2 RB2 0 O DIG LATB<2> data output. 1 I TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared. INT2 1 I ST External Interrupt 2 input. RB3/INT3/ RB3 0 O DIG LATB<3> data output. CCP2 1 I TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared. INT3 1 I ST External Interrupt 3 input. CCP2(1) 0 O DIG CCP2 compare output and CCP2 PWM output; takes priority over port data. 1 I ST CCP2 capture input. RB4/KBI0 RB4 0 O DIG LATB<4> data output. 1 I TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared. KBI0 1 I TTL Interrupt-on-change pin. RB5/KBI1 RB5 0 O DIG LATB<5> data output 1 I TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared. KBI1 1 I TTL Interrupt-on-change pin. RB6/KBI2/PGC RB6 0 O DIG LATB<6> data output 1 I TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared. KBI2 1 I TTL Interrupt-on-change pin. PGC x I ST Serial execution (ICSP™) clock input for ICSP and ICD operation.(2) RB7/KBI3/PGD RB7 0 O DIG LATB<7> data output. 1 I TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared. KBI3 1 I TTL Interrupt-on-change pin. PGD x O DIG Serial execution data output for ICSP and ICD operation.(2) x I ST Serial execution data input for ICSP and ICD operation.(2) Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared (Microprocessor, Extended Microcontroller and Microcontroller with Boot Block modes, 80-pin devices only); default assignment is RC1. 2: All other pin functions are disabled when ICSP or ICD operations are enabled.  2010 Microchip Technology Inc. DS39635C-page 129

PIC18F6310/6410/8310/8410 TABLE 11-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 66 LATB LATB Output Latch Register 66 TRISB PORTB Data Direction Register 66 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 63 INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 63 Legend: Shaded cells are not used by PORTB. DS39635C-page 130  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 11.3 PORTC, TRISC and Note: On a Power-on Reset, these pins are LATC Registers configured as digital inputs. PORTC is an 8-bit wide, bidirectional port. The corre- The contents of the TRISC register are affected by sponding Data Direction register is TRISC. Setting a peripheral overrides. Reading TRISC always returns TRISC bit (= 1) will make the corresponding PORTC the current contents, even though a peripheral device pin an input (i.e., put the corresponding output driver in may be overriding one or more of the pins. a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., EXAMPLE 11-3: INITIALIZING PORTC put the contents of the output latch on the selected pin). CLRF PORTC ; Initialize PORTC by The Output Latch register (LATC) is also memory ; clearing output mapped. Read-modify-write operations on the LATC ; data latches register read and write the latched output value for CLRF LATC ; Alternate method PORTC. ; to clear output ; data latches PORTC is multiplexed with several peripheral functions MOVLW 0CFh ; Value used to (Table11-5). The pins have Schmitt Trigger input ; initialize data buffers. RC1 is normally configured by Configuration ; direction bit, CCP2MX, as the default peripheral pin of the CCP2 MOVWF TRISC ; Set RC<3:0> as inputs module (default/erased state, CCP2MX = 1). ; RC<5:4> as outputs ; RC<7:6> as inputs When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings.  2010 Microchip Technology Inc. DS39635C-page 131

PIC18F6310/6410/8310/8410 TABLE 11-5: PORTC FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RC0/T1OSO/T13CKI RC0 0 O DIG LATC<0> data output. 1 I ST PORTC<0> data input. T1OSO x O ANA Timer1 oscillator output; enabled when Timer1 oscillator is enabled. Disables digital I/O. T13CKI 1 I ST Timer1/Timer3 counter input. RC1/T1OSI/CCP2 RC1 0 O DIG LATC<1> data output. 1 I ST PORTC<1> data input. T1OSI x I ANA Timer1 oscillator input; enabled when Timer1 oscillator is enabled. Disables digital I/O. CCP2(1) 0 O DIG CCP2 compare output and CCP2 PWM output; takes priority over port data. 1 I ST CCP2 capture input RC2/CCP1 RC2 0 O DIG LATC<2> data output. 1 I ST PORTC<2> data input. CCP1 0 O DIG CCP1 compare output and CCP1 PWM output; takes priority over port data. 1 I ST CCP1 capture input. RC3/SCK/SCL RC3 0 O DIG LATC<3> data output. 1 I ST PORTC<3> data input. SCK 0 O DIG SPI clock output (MSSP module); takes priority over port data. 1 I ST SPI clock input (MSSP module). SCL 0 O DIG I2C™ clock output (MSSP module); takes priority over port data. 1 I ST I2C clock input (MSSP module); input type depends on module setting. RC4/SDI/SDA RC4 0 O DIG LATC<4> data output. 1 I ST PORTC<4> data input. SDI 1 I ST SPI data input (MSSP module). SDA 1 O DIG I2C data output (MSSP module); takes priority over port data. 1 I ST I2C data input (MSSP module); input type depends on module setting. RC5/SDO RC5 0 O DIG LATC<5> data output. 1 I ST PORTC<5> data input. SDO 0 O DIG SPI data output (MSSP module); takes priority over port data. RC6/TX1/CK1 RC6 0 O DIG LATC<6> data output. 1 I ST PORTC<6> data input. TX1 1 O DIG Synchronous serial data output (EUSART module); takes priority over port data. CK1 1 O DIG Synchronous serial data input (EUSART module). User must configure as an input. 1 I ST Synchronous serial clock input (EUSART module). RC7/RX1/DT1 RC7 0 O DIG LATC<7> data output. 1 I ST PORTC<7> data input. RX1 1 I ST Asynchronous serial receive data input (EUSART module) DT1 1 O DIG Synchronous serial data output (EUSART module); takes priority over port data. 1 I ST Synchronous serial data input (EUSART module). User must configure as an input. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for CCP2 when CCP2MX Configuration bit is set. DS39635C-page 132  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 11-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 66 LATC LATC Output Latch Register 66 TRISC PORTC Data Direction Register 66  2010 Microchip Technology Inc. DS39635C-page 133

PIC18F6310/6410/8310/8410 11.4 PORTD, TRISD and PORTD can also be configured to function as an 8-bit LATD Registers wide parallel microprocessor port by setting the PSPMODE Control bit (PSPCON<4>). In this mode, PORTD is an 8-bit wide, bidirectional port. The corre- parallel port data takes priority over other digital I/O (but sponding Data Direction register is TRISD. Setting a not the external memory interface). When the parallel TRISD bit (= 1) will make the corresponding PORTD port is active, the input buffers are TTL. For more pin an input (i.e., put the corresponding output driver in information, refer to Section11.10 “Parallel Slave a High-Impedance mode). Clearing a TRISD bit (= 0) Port”. will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). EXAMPLE 11-4: INITIALIZING PORTD The Output Latch register (LATD) is also memory CLRF PORTD ; Initialize PORTD by mapped. Read-modify-write operations on the LATD ; clearing output register read and write the latched output value for ; data latches PORTD. CLRF LATD ; Alternate method ; to clear output All pins on PORTD are implemented with Schmitt ; data latches Trigger input buffers. Each pin is individually MOVLW 0CFh ; Value used to configurable as an input or output. ; initialize data ; direction Note: On a Power-on Reset, these pins are MOVWF TRISD ; Set RD<3:0> as inputs configured as digital inputs. ; RD<5:4> as outputs In 80-pin devices, PORTD is multiplexed with the ; RD<7:6> as inputs system bus as part of the external memory interface. I/O port and other functions are only available when the interface is disabled by setting the EBDIS bit (MEMCON<7>). When the interface is enabled, PORTD is the low-order byte of the multiplexed address/data bus (AD<7:0>). The TRISD bits are also overridden. DS39635C-page 134  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 11-7: PORTD FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RD0/AD0/PSP0 RD0 0 O DIG LATD<0> data output. 1 I ST PORTD<0> data input. AD0(2) x O DIG External memory interface, Address/Data Bit 0 output.(1) x I TTL External memory interface, Data Bit 0 input.(1) PSP0 x O DIG PSP read data output (LATD<0>); takes priority over port data. x I TTL PSP write data input. RD1/AD1/PSP1 RD1 0 O DIG LATD<1> data output. 1 I ST PORTD<1> data input. AD1(2) x O DIG External memory interface, Address/Data Bit 1 output.(1) x I TTL External memory interface, Data Bit 1 input.(1) PSP1 x O DIG PSP read data output (LATD<1>); takes priority over port data. x I TTL PSP write data input. RD2/AD2/PSP2 RD2 0 O DIG LATD<2> data output. 1 I ST PORTD<2> data input. AD2(2) x O DIG External memory interface, Address/Data Bit 2 output.(1) x I TTL External memory interface, Data Bit 2 input.(1) PSP2 x O DIG PSP read data output (LATD<2>); takes priority over port data. x I TTL PSP write data input. RD3/AD3/PSP3 RD3 0 O DIG LATD<3> data output. 1 I ST PORTD<3> data input. AD3(2) x O DIG External memory interface, Address/Data Bit 3 output.(1) x I TTL External memory interface, Data Bit 3 input.(1) PSP3 x O DIG PSP read data output (LATD<3>); takes priority over port data. x I TTL PSP write data input. RD4/AD4/PSP4 RD4 0 O DIG LATD<4> data output. 1 I ST PORTD<4> data input. AD4(2) x O DIG External memory interface, Address/Data Bit 4 output.(1) x I TTL External memory interface, Data Bit 4 input.(1) PSP4 x O DIG PSP read data output (LATD<4>); takes priority over port data. x I TTL PSP write data input. RD5/AD5/PSP5 RD5 0 O DIG LATD<5> data output. 1 I ST PORTD<5> data input. AD5(2) x O DIG External memory interface, Address/Data Bit 5 output.(1) x I TTL External memory interface, Data Bit 5 input.(1) PSP5 x O DIG PSP read data output (LATD<5>); takes priority over port data. x I TTL PSP write data input. RD6/AD6/PSP6 RD6 0 O DIG LATD<6> data output. 1 I ST PORTD<6> data input. AD6(2) x O DIG-3 External memory interface, Address/Data Bit 6 output.(1) x I TTL External memory interface, Data Bit 6 input.(1) PSP6 x O DIG PSP read data output (LATD<6>); takes priority over port data. x I TTL PSP write data input. Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: External memory interface I/O takes priority over all other digital and PSP I/O. 2: Implemented on 80-pin devices only.  2010 Microchip Technology Inc. DS39635C-page 135

PIC18F6310/6410/8310/8410 TABLE 11-7: PORTD FUNCTIONS (CONTINUED) TRIS I/O Pin Name Function I/O Description Setting Type RD7/AD7/PSP7 RD7 0 O DIG LATD<7> data output. 1 I ST PORTD<7> data input. AD7(2) x O DIG External memory interface, Address/Data Bit 7 output(1). x I TTL External memory interface, Data Bit 7 input(1). PSP7 x O DIG PSP read data output (LATD<7>); takes priority over port data. x I TTL PSP write data input. Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: External memory interface I/O takes priority over all other digital and PSP I/O. 2: Implemented on 80-pin devices only. TABLE 11-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 66 LATD LATD Output Latch Register 66 TRISD PORTD Data Direction Register 66 DS39635C-page 136  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 11.5 PORTE, TRISE and When the Parallel Slave Port is active on PORTD, three LATE Registers of the PORTE pins (RE0/AD8/RD, RE1/AD9/WR and RE2/AD10/CS) are configured as digital control inputs PORTE is an 8-bit wide, bidirectional port. The for the port. The control functions are summarized in corresponding Data Direction register is TRISE. Setting Table11-9. The reconfiguration occurs automatically a TRISE bit (= 1) will make the corresponding PORTE when the PSPMODE Control bit (PSPCON<4>) is set. pin an input (i.e., put the corresponding output driver in Users must still make certain the corresponding TRISE a High-Impedance mode). Clearing a TRISE bit (= 0) bits are set to configure these pins as digital inputs. will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). EXAMPLE 11-5: INITIALIZING PORTE The Output Latch register (LATE) is also memory CLRF PORTE ; Initialize PORTE by mapped. Read-modify-write operations on the LATE ; clearing output register read and write the latched output value for ; data latches PORTE. CLRF LATE ; Alternate method ; to clear output All pins on PORTE are implemented with Schmitt ; data latches Trigger input buffers. Each pin is individually MOVLW 03h ; Value used to configurable as an input or output. ; initialize data ; direction Note: On a Power-on Reset, these pins are MOVWF TRISE ; Set RE<1:0> as inputs configured as digital inputs. ; RE<7:2> as outputs When the device is operating in Microcontroller mode, pin RE7 can be configured as the alternate peripheral pin for the CCP2 module. This is done by clearing the CCP2MX Configuration bit. In 80-pin devices, PORTE is multiplexed with the system bus as part of the external memory interface. I/O port and other functions are only available when the interface is disabled by setting the EBDIS bit (MEMCON<7>). When the interface is enabled (80-pin devices only), PORTE is the high-order byte of the multiplexed address/data bus (AD<15:8>). The TRISE bits are also overridden.  2010 Microchip Technology Inc. DS39635C-page 137

PIC18F6310/6410/8310/8410 TABLE 11-9: PORTE FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RE0/AD8/RD RE0 0 O DIG LATE<0> data output. 1 I ST PORTE<0> data input. AD8(3) x O DIG External memory interface, Address/Data Bit 8 output.(2) x I TTL External memory interface, Data Bit 8 input.(2) RD 1 I TTL Parallel Slave Port read enable control input. RE1/AD9/WR RE1 0 O DIG LATE<1> data output. 1 I ST PORTE<1> data input. AD9(3) x O DIG External memory interface, Address/Data Bit 9 output.(2) x I TTL External memory interface, Data Bit 9 input.(2) WR 1 I TTL Parallel Slave Port write enable control input. RE2/AD10/CS RE2 0 O DIG LATE<2> data output. 1 I ST PORTE<2> data input. AD10(3) x O DIG External memory interface, Address/Data Bit 10 output.(2) x I TTL External memory interface, Data Bit 10 input.(2) CS 1 I TTL Parallel Slave Port chip select control input. RE3/AD11 RE3 0 O DIG LATE<3> data output. 1 I ST PORTE<3> data input. AD11(3) x O DIG External memory interface, Address/Data Bit 11 output.(2) x I TTL External memory interface, Data Bit 11 input.(2) RE4/AD12 RE4 0 O DIG LATE<4> data output. 1 I ST PORTE<4> data input. AD12(3) x O DIG External memory interface, Address/Data Bit 12 output.(2) x I TTL External memory interface, Data Bit 12 input.(2) RE5/AD13 RE5 0 O DIG LATE<5> data output. 1 I ST PORTE<5> data input. AD13(3) x O DIG External memory interface, Address/Data Bit 13 output.(2) x I TTL External memory interface, Data Bit 13 input.(2) RE6/AD14 RE6 0 O DIG LATE<6> data output. 1 I ST PORTE<6> data input. AD14(3) x O DIG External memory interface, Address/Data Bit 14 output.(2) x I TTL External memory interface, Data Bit 14 input.(2) RE7/CCP2/AD15 RE7 0 O DIG LATE<7> data output. 1 I ST PORTE<7> data input. CCP2(1) 0 O DIG CCP2 compare output and CCP2 PWM output; takes priority over port data. 1 I ST CCP2 capture input. AD15(3) x O DIG External memory interface, Address/Data Bit 15 output.(2) x I TTL External memory interface, Data Bit 15 input.(2) Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared (all devices in Microcontroller mode). 2: External memory interface I/O takes priority over all other digital and PSP I/O. 3: Implemented on 80-pin devices only. DS39635C-page 138  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 66 LATE LATE Output Latch Register 66 TRISE PORTE Data Direction Register 66  2010 Microchip Technology Inc. DS39635C-page 139

PIC18F6310/6410/8310/8410 11.6 PORTF, LATF and TRISF Registers Note 1: On a Power-on Reset, the RF<6:0> pins PORTF is an 8-bit wide, bidirectional port. The corre- are configured as inputs and read as ‘0’. sponding Data Direction register is TRISF. Setting a 2: To configure PORTF as a digital I/O, turn TRISF bit (= 1) will make the corresponding PORTF pin off the comparators and set the ADCON1 an input (i.e., put the corresponding output driver in a value. High-Impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i.e., put the contents of the output latch on the selected pin). EXAMPLE 11-6: INITIALIZING PORTF The Output Latch register (LATF) is also memory CLRF PORTF ; Initialize PORTF by mapped. Read-modify-write operations on the LATF ; clearing output ; data latches register read and write the latched output value for CLRF LATF ; Alternate method PORTF. ; to clear output All pins on PORTF are implemented with Schmitt ; data latches Trigger input buffers. Each pin is individually MOVLW 0x07 ; configurable as an input or output. MOVWF CMCON ; Turn off comparators MOVLW 0x0F ; PORTF is multiplexed with several analog peripheral MOVWF ADCON1 ; Set PORTF as digital I/O functions, including the A/D Converter and comparator MOVLW 0xCF ; Value used to inputs, as well as the comparator outputs. Pins, RF2 ; initialize data through RF6, may be used as comparator inputs or ; direction outputs by setting the appropriate bits in the CMCON MOVWF TRISF ; Set RF3:RF0 as inputs register. To use RF<6:3> as digital inputs, it is also ; RF5:RF4 as outputs necessary to turn off the comparators. ; RF7:RF6 as inputs Note: On a Power-on Reset, RA5 and RA<3:0> are configured as analog inputs and read as ‘0’. RA4 is configured as a digital input. DS39635C-page 140  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 11-11: PORTF FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RF0/AN5 RF0 0 O DIG LATF<0> data output; not affected by analog input. 1 I ST PORTF<0> data input; disabled when analog input is enabled. AN5 1 I ANA A/D Input Channel 5. Default configuration on POR. RF1/AN6/C2OUT RF1 0 O DIG LATF<1> data output; not affected by analog input. 1 I ST PORTF<1> data input; disabled when analog input is enabled. AN6 1 I ANA A/D Input Channel 6. Default configuration on POR. C2OUT 0 O DIG Comparator 2 output; takes priority over port data. RF2/AN7/C1OUT RF2 0 O DIG LATF<2> data output; not affected by analog input. 1 I ST PORTF<2> data input; disabled when analog input is enabled. AN7 1 I ANA A/D Input Channel 7. Default configuration on POR. C1OUT 0 O TTL Comparator 1 output; takes priority over port data. RF3/AN8 RF3 0 O DIG LATF<3> data output; not affected by analog input. 1 I ST PORTF<3> data input; disabled when analog input is enabled. AN8 1 I ANA A/D Input Channel 8 and Comparator C2+ input. Default input configuration on POR; not affected by analog output. RF4/AN9 RF4 0 O DIG LATF<4> data output; not affected by analog input. 1 I ST PORTF<4> data input; disabled when analog input is enabled. AN9 1 I ANA A/D Input Channel 9 and Comparator C2- input. Default input configuration on POR; does not affect digital output. RF5/AN10/CVREF RF5 0 O DIG LATF<5> data output; not affected by analog input. Disabled when CVREF output is enabled. 1 I ST PORTF<5> data input; disabled when analog input is enabled. Disabled when CVREF output is enabled AN10 1 I ANA A/D Input Channel 10 and Comparator C1+ input. Default input configuration on POR. CVREF x O ANA Comparator voltage reference output. Enabling this feature disables digital I/O. RF6/AN11 RF6 0 O DIG LATF<6> data output; not affected by analog input. 1 I ST PORTF<6> data input; disabled when analog input is enabled. AN11 1 I ANA A/D Input Channel 11 and Comparator C1- input. Default input configuration on POR; does not affect digital output. RF7/SS RF7 0 O DIG LATF<7> data output. 1 I ST PORTF<7> data input. SS 1 I TTL Slave select input for MSSP (MSSP module). Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). TABLE 11-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page TRISF PORTF Data Direction Register 66 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 66 LATF LATF Output Latch Register 66 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 64 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 65 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 65 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF.  2010 Microchip Technology Inc. DS39635C-page 141

PIC18F6310/6410/8310/8410 11.7 PORTG, TRISG and The sixth pin of PORTG (RG5/MCLR/VPP) is an input LATG Registers only pin. Its operation is controlled by the MCLRE Configuration bit. When selected as a port pin PORTG is a 6-bit wide, bidirectional port. The corre- (MCLRE=0), it functions as a digital input only pin; as sponding Data Direction register is TRISG. Setting a such, it does not have TRIS or LAT bits associated with TRISG bit (= 1) will make the corresponding PORTG its operation. Otherwise, it functions as the device’s pin an input (i.e., put the corresponding output driver in Master Clear input. In either configuration, RG5 also a High-Impedance mode). Clearing a TRISG bit (= 0) functions as the programming voltage input during programming. will make the corresponding PORTG pin an output (i.e., put the contents of the output latch on the selected pin). Note: On a Power-on Reset, RG5 is enabled as The Output Latch register (LATG) is also memory a digital input only if Master Clear mapped. Read-modify-write operations on the LATG functionality is disabled. All other 5 pins register, read and write the latched output value for are configured as digital inputs. PORTG. PORTG is multiplexed with USART functions EXAMPLE 11-7: INITIALIZING PORTG (Table11-13). PORTG pins have Schmitt Trigger input CLRF PORTG ; Initialize PORTG by buffers. ; clearing output ; data latches When enabling peripheral functions, care should be CLRF LATG ; Alternate method taken in defining TRIS bits for each PORTG pin. Some ; to clear output peripherals override the TRIS bit to make a pin an ; data latches output, while other peripherals override the TRIS bit to MOVLW 0x04 ; Value used to make a pin an input. The user should refer to the ; initialize data corresponding peripheral section for the correct TRIS ; direction bit settings. The pin override value is not loaded into MOVWF TRISG ; Set RG1:RG0 as outputs the TRIS register. This allows read-modify-write of the ; RG2 as input TRIS register without concern due to peripheral ; RG4:RG3 as inputs overrides. DS39635C-page 142  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 11-13: PORTG FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RG0/CCP3 RG0 0 O DIG LATG<0> data output. 1 I ST PORTG<0> data input. CCP3 0 O DIG CCP3 compare and PWM output; takes priority over port data. 1 I ST CCP3 capture input. RG1/TX2/CK2 R21 0 O DIG LATG<1> data output. 1 I ST PORTG<1> data input. TX2 1 O DIG Synchronous serial data output (AUSART module); takes priority over port data. CK2 1 O DIG Synchronous serial data input (AUSART module). User must configure as an input. 1 I ST Synchronous serial clock input (AUSART module). RG2/RX2/DT2 RG2 0 O DIG LATG<2> data output. 1 I ST PORTG<2> data input. RX2 1 I ST Asynchronous serial receive data input (AUSART module). DT2 1 O DIG Synchronous serial data output (AUSART module); takes priority over port data. 1 I ST Synchronous serial data input (AUSART module). User must configure as an input. RG3 RG3 0 O DIG LATG<3> data output. 1 I ST PORTG<3> data input. RG4 RG4 0 O DIG LATG<4> data output. 1 I ST PORTG<4> data input. RG5/MCLR/VPP RG5 —(1) I ST PORTG<5> data input; enabled when MCLRE Configuration bit is clear. MCLR — I ST External Master Clear input; enabled when MCLRE Configuration bit is set. VPP — I ANA High-Voltage Detection; used for ICSP™ mode entry detection. Always available, regardless of pin mode. Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: RG5 does not have a corresponding TRISG bit. TABLE 11-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page PORTG — — RG5(1) RG4 RG3 RG2 RG1 RG0 66 LATG — — — LATG Output Latch Register 66 TRISG — — — PORTG Data Direction Register 66 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG. Note 1: RG5 is available as an input only when MCLR is disabled.  2010 Microchip Technology Inc. DS39635C-page 143

PIC18F6310/6410/8310/8410 11.8 PORTH, LATH and When the external memory interface is enabled, four of TRISH Registers the PORTH pins function as the high-order address lines for the interface. The address output from the Note: PORTH is only available on interface takes priority over other digital I/O. The PIC18F8310/8410 devices. corresponding TRISH bits are also overridden. PORTH is an 8-bit wide, bidirectional I/O port. The cor- EXAMPLE 11-8: INITIALIZING PORTH responding Data Direction register is TRISH. Setting a TRISH bit (= 1) will make the corresponding PORTH CLRF PORTH ; Initialize PORTH by ; clearing output pin an input (i.e., put the corresponding output driver in ; data latches a High-Impedance mode). Clearing a TRISH bit (= 0) CLRF LATH ; Alternate method will make the corresponding PORTH pin an output (i.e., ; to clear output put the contents of the output latch on the selected pin). ; data latches The Output Latch register (LATH) is also memory MOVLW 0CFh ; Value used to mapped. Read-modify-write operations on the LATH ; initialize data ; direction register, read and write the latched output value for MOVWF TRISH ; Set RH3:RH0 as inputs PORTH. ; RH5:RH4 as outputs All pins on PORTH are implemented with Schmitt ; RH7:RH6 as inputs Trigger input buffers. Each pin is individually configurable as an input or output. Note: On a Power-on Reset, these pins are configured as digital inputs. DS39635C-page 144  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 11-15: PORTH FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RH0/AD16 RH0 0 O DIG LATH<0> data output. 1 I ST PORTH<0> data input. AD16 x O DIG External memory interface, Address Line 16. Takes priority over port data. RH1/AD17 RH1 0 O DIG LATH<1> data output. 1 I ST PORTH<1> data input. AD17 x O DIG External memory interface, Address Line 17. Takes priority over port data. RH2/AD18 RH2 0 O DIG LATH<2> data output. 1 I ST PORTH<2> data input. AD18 x O DIG External memory interface, Address Line 18. Takes priority over port data. RH3/AD19 RH3 0 O DIG LATH<3> data output. 1 I ST PORTH<3> data input. AD19 x O DIG External memory interface, Address Line 19. Takes priority over port data. RH4 RH4 0 O DIG LATH<4> data output. 1 I ST PORTH<4> data input. RH5 RH5 0 O DIG LATH<5> data output. 1 I ST PORTH<5> data input. RH6 RH6 0 O DIG LATH<6> data output. 1 I ST PORTH<6> data input. RH7 RH7 0 O DIG LATH<7> data output. 1 I ST PORTH<7> data input. Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). TABLE 11-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page TRISH PORTH Data Direction Register 65 PORTH RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 66 LATH PORTH Output Latch Register 66  2010 Microchip Technology Inc. DS39635C-page 145

PIC18F6310/6410/8310/8410 11.9 PORTJ, TRISJ and When the external memory interface is enabled, all of LATJ Registers the PORTJ pins function as control outputs for the interface. This occurs automatically when the interface Note: PORTJ is available only on is enabled by clearing the EBDIS control bit PIC18F8310/8410 devices. (MEMCON<7>). The TRISJ bits are also overridden. PORTJ is an 8-bit wide, bidirectional port. The corre- EXAMPLE 11-9: INITIALIZING PORTJ sponding Data Direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding PORTJ pin CLRF PORTJ ; Initialize PORTG by ; clearing output an input (i.e., put the corresponding output driver in a ; data latches High-Impedance mode). Clearing a TRISJ bit (= 0) will CLRF LATJ ; Alternate method make the corresponding PORTJ pin an output (i.e., put ; to clear output the contents of the output latch on the selected pin). ; data latches The Output Latch register (LATJ) is also memory MOVLW 0xCF ; Value used to mapped. Read-modify-write operations on the LATJ ; initialize data register, read and write the latched output value for ; direction MOVWF TRISJ ; Set RJ3:RJ0 as inputs PORTJ. ; RJ5:RJ4 as output All pins on PORTJ are implemented with Schmitt ; RJ7:RJ6 as inputs Trigger input buffers. Each pin is individually configurable as an input or output. Note: On a Power-on Reset, these pins are configured as digital inputs. DS39635C-page 146  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 11-17: PORTJ FUNCTIONS TRIS I/O Pin Name Function I/O Description Setting Type RJ0/ALE RJ0 0 O DIG LATJ<0> data output. 1 I ST PORTJ<0> data input. ALE x O DIG External memory interface address latch enable control output; takes priority over digital I/O. RJ1/OE RJ1 0 O DIG LATJ<1> data output. 1 I ST PORTJ<1> data input. OE x O DIG External memory interface output enable control output; takes priority over digital I/O. RJ2/WRL RJ2 0 O DIG LATJ<2> data output. 1 I ST PORTJ<2> data input. WRL x O DIG External memory bus write low byte control; takes priority over digital I/O. RJ3/WRH RJ3 0 O DIG LATJ<3> data output. 1 I ST PORTJ<3> data input. WRH x O DIG External memory interface write high byte control output; takes priority over digital I/O. RJ4/BA0 RJ4 0 O DIG LATJ<4> data output. 1 I ST PORTJ<4> data input. BA0 x O DIG External Memory Interface Byte Address 0 control output; takes prior- ity over digital I/O. RJ5/CE RJ5 0 O DIG LATJ<5> data output. 1 I ST PORTJ<5> data input. CE x O DIG External memory interface chip enable control output; takes priority over digital I/O. RJ6/LB RJ6 0 O DIG LATJ<6> data output. 1 I ST PORTJ<6> data input. LB x O DIG External memory interface lower byte enable control output; takes priority over digital I/O. RJ7/UB RJ7 0 O DIG LATJ<7> data output. 1 I ST PORTJ<7> data input. UB x O DIG External memory interface upper byte enable control output; takes priority over digital I/O. Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). TABLE 11-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page PORTJ RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 66 LATJ LATJ Output Latch Register 66 TRISJ PORTJ Data Direction Register 65  2010 Microchip Technology Inc. DS39635C-page 147

PIC18F6310/6410/8310/8410 11.10 Parallel Slave Port FIGURE 11-2: PORTD AND PORTE BLOCK DIAGRAM PORTD can also function as an 8-bit wide Parallel (PARALLEL SLAVE Slave Port (PSP), or microprocessor port, when control PORT) bit, PSPMODE (PSPCON<4>), is set. It is asynchro- nously readable and writable by the external world through RD control input pin, RE0/RD and WR control Data Bus input pin, RE1/WR. D Q RDx Note: For PIC18F8310/8410 devices, the Parallel WR LATD CK Pin or Slave Port is available only in PORTD Data Latch TTL Microcontroller mode. The PSP can directly interface to an 8-bit micro- Q D processor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting RD PORTD ENEN bit, PSPMODE, enables port pin, RE0/RD, to be the TRIS Latch RD input, RE1/WR to be the WR input and RE2/CS to be the CS (Chip Select) input. For this functionality, the corresponding data direction bits of the TRISE register RD LATD (TRISE<2:0>) must be configured as inputs (set). A write to the PSP occurs when both the CS and WR lines are first detected low and ends when either are One bit of PORTD detected high. The PSPIF and IBF flag bits are both set Set Interrupt Flag when the write ends. PSPIF (PIR1<7>) A read from the PSP occurs when both the CS and RD lines are first detected low. The data in PORTD is read out and the OBF bit is set. If the user writes new data to PORTD to set OBF, the data is immediately read out; however, the OBF bit is not set. When either the CS or RD lines are detected high, the Read TTL RD PORTD pins return to the input state and the PSPIF bit is set. User applications should wait for PSPIF to be set Chip Select before servicing the PSP; when this happens, the IBF TTL CS and OBF bits can be polled and the appropriate action Write taken. TTL WR The timing for the control signals in Write and Read Note: I/O pin has protection diodes to VDD and VSS. modes is shown in Figure11-3 and Figure11-4, respectively. DS39635C-page 148  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 REGISTER 11-1: PSPCON: PARALLEL SLAVE PORT CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IBF OBF IBOV PSPMODE — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode bit 3-0 Unimplemented: Read as ‘0’ FIGURE 11-3: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF  2010 Microchip Technology Inc. DS39635C-page 149

PIC18F6310/6410/8310/8410 FIGURE 11-4: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 11-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 66 LATD LATD Output Latch Register 66 TRISD PORTD Data Direction Register 66 PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 66 LATE LATE Output Latch Register 66 TRISE PORTE Data Direction Register 66 PSPCON IBF OBF IBOV PSPMODE — — — — 65 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 65 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 65 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. DS39635C-page 150  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 12.0 TIMER0 MODULE The T0CON register (Register12-1) controls all aspects of the module’s operation, including the The Timer0 module incorporates the following features: prescale selection. It is both readable and writable. • Software-selectable operation as a timer or coun- A simplified block diagram of the Timer0 module in ter in both 8-bit or 16-bit modes 8-bit mode is shown in Figure12-1. Figure12-2 • Readable and writable registers shows a simplified block diagram of the Timer0 • Dedicated 8-bit software-programmable prescaler module in 16-bit mode. • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow REGISTER 12-1: T0CON: TIMER0 CONTROL REGISTER REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS TOSE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin input edge 0 = Internal clock (FOSC/4) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is not assigned; Timer0 clock input bypasses prescaler 0 = Timer0 prescaler is assigned; Timer0 clock input comes from prescaler output bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value  2010 Microchip Technology Inc. DS39635C-page 151

PIC18F6310/6410/8310/8410 12.1 Timer0 Operation internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the Timer0 can operate as either a timer or a counter; the timer/counter. mode is selected by clearing the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on 12.2 Timer0 Reads and Writes in every clock by default, unless a different prescaler value 16-Bit Mode is selected (see Section12.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the fol- TMR0H is not the actual high byte of Timer0 in 16-bit lowing two instruction cycles. The user can work around mode; it is actually a buffered version of the real high this by writing an adjusted value to the TMR0 register. byte of Timer0, which is not directly readable nor writable (refer to Figure12-2). TMR0H is updated with The Counter mode is selected by setting the T0CS bit the contents of the high byte of Timer0 during a read of (= 1). In Counter mode, Timer0 increments either on TMR0L. This provides the ability to read all 16 bits of every rising or falling edge of pin, RA4/T0CKI. The Timer0, without having to verify that the read of the high incrementing edge is determined by the Timer0 Source and low byte were valid, due to a rollover between Edge Select bit, T0SE (T0CON<4>); clearing this bit successive reads of the high and low byte. selects the rising edge. Restrictions on the external clock input are discussed below. Similarly, a write to the high byte of Timer0 must also take place through the TMR0H Buffer register. The high An external clock source can be used to drive Timer0; byte is updated with the contents of TMR0H when a however, it must meet certain requirements to ensure write occurs to TMR0L. This allows all 16 bits of Timer0 that the external clock can be synchronized with the to be updated at once. FIGURE 12-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 0 Sync with Set 1 Internal TMR0L TMR0IF T0CKI pin Programmable 1 Clocks on Overflow Prescaler T0SE (2 TCY Delay) 8 T0CS 3 T0PS<2:0> 8 Internal Data Bus PSA Note: Upon Reset, Timer0 is enabled in 8-bit mode with the clock input from T0CKI maximum prescale. FIGURE 12-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 0 Sync with TMR0 Set 1 Internal TMR0L High Byte TMR0IF T0CKI pin ProPgrreasmcamlearble 1 Clocks 8 on Overflow T0SE (2 TCY Delay) T0CS 3 Read TMR0L T0PS<2:0> Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with the clock input from T0CKI maximum prescale. DS39635C-page 152  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 12.3 Prescaler 12.3.1 SWITCHING PRESCALER ASSIGNMENT An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable; The prescaler assignment is fully under software its value is set by the PSA and T0PS<2:0> bits control and can be changed “on-the-fly” during program (T0CON<3:0>), which determine the prescaler execution. assignment and prescale ratio. 12.4 Timer0 Interrupt Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values The TMR0 interrupt is generated when the TMR0 from 1:2 through 1:256 in power-of-2 increments are register overflows from FFh to 00h in 8-bit mode, or selectable. from FFFFh to 0000h in 16-bit mode. This overflow sets When assigned to the Timer0 module, all instructions the TMR0IF flag bit. The interrupt can be masked by writing to the TMR0 register (e.g., CLRF TMR0, MOVWF clearing the TMR0IE bit (INTCON<5>). Before re- TMR0, BSF TMR0,etc.) clear the prescaler count. enabling the interrupt, the TMR0IF bit must be cleared in software by the Interrupt Service Routine. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler Since Timer0 is shut down in Sleep mode, the TMR0 count, but will not change the prescaler interrupt cannot awaken the processor from Sleep. assignment. TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER0 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page TMR0L Timer0 Module Low Byte Register 64 TMR0H Timer0 Module High Byte Register 64 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 64 TRISA PORTA Data Direction Register 66 Legend: Shaded cells are not used by Timer0.  2010 Microchip Technology Inc. DS39635C-page 153

PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 154  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 13.0 TIMER1 MODULE A simplified block diagram of the Timer1 module is shown in Figure13-1. A block diagram of the module’s The Timer1 timer/counter module incorporates these operation in Read/Write mode is shown in Figure13-2. features: The module incorporates its own low-power oscillator • Software-selectable operation as a 16-bit timer or to provide an additional clocking option. The Timer1 counter oscillator can also be used as a low-power clock source • Readable and writable 8-bit registers (TMR1H for the microcontroller in power-managed operation. and TMR1L) Timer1 can also be used to provide Real-Time Clock • Selectable clock source (internal or external) with (RTC) functionality to applications with only a minimal device clock or Timer1 oscillator internal options addition of external components and code overhead. • Interrupt-on-overflow Timer1 is controlled through the T1CON Control • Reset on CCP Special Event Trigger register (Register13-1). It also contains the Timer1 • Device clock status flag (T1RUN) Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>). REGISTER 13-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of TImer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 6 T1RUN: Timer1 System Clock Status bit 1 = Device clock is derived from Timer1 oscillator 0 = Device clock is derived from another source bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1  2010 Microchip Technology Inc. DS39635C-page 155

PIC18F6310/6410/8310/8410 13.1 Timer1 Operation cycle (FOSC/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input Timer1 can operate in one of these modes: or the Timer1 oscillator, if enabled. • Timer When Timer1 is enabled, the RC1/T1OSI and RC0/ • Synchronous Counter T1OSO/T13CKI pins become inputs. This means the • Asynchronous Counter values of TRISC<1:0> are ignored and the pins are read as ‘0’. The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 13-1: TIMER1 BLOCK DIAGRAM Timer1 Oscillator On/Off 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR1CS Timer1 On/Off T1CKPS<1:0> T1SYNC TMR1ON Set Clear TMR1 TMR1L HTigMh RB1yte TMR1IF (CCP Special Event Trigger) on Overflow Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 13-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR1CS Timer1 T1CKPS<1:0> On/Off T1SYNC TMR1ON Set Clear TMR1 TMR1L HTigMh RB1yte TMR1IF (CCP Special Event Trigger) on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39635C-page 156  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 13.2 Timer1 16-Bit Read/Write Mode TABLE 13-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Timer1 can be configured for 16-bit reads and writes (see Figure13-2). When the RD16 control bit Osc Type Freq C1 C2 (T1CON<7>) is set, the address for TMR1H is mapped LP 32kHz 27pF(1) 27pF(1) to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Note1: Microchip suggests these values as a Timer1 into the Timer1 high byte buffer. This provides starting point in validating the oscillator the user with the ability to accurately read all 16 bits of circuit. Timer1 without having to determine whether a read of 2: Higher capacitance increases the stabil- the high byte, followed by a read of the low byte, has ity of the oscillator, but also increases the become invalid due to a rollover between reads. start-up time. A write to the high byte of Timer1 must also take place 3: Since each resonator/crystal has its own through the TMR1H Buffer register. The Timer1 high characteristics, the user should consult byte is updated with the contents of TMR1H when a the resonator/crystal manufacturer for write occurs to TMR1L. This allows a user to write all appropriate values of external 16 bits to both the high and low bytes of Timer1 at once. components. The high byte of Timer1 is not directly readable or 4: Capacitor values are for design guidance writable in this mode. All reads and writes must take only. place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. 13.3.1 USING TIMER1 AS A CLOCK The prescaler is only cleared on writes to TMR1L. SOURCE 13.3 Timer1 Oscillator The Timer1 oscillator is also available as a clock source in power-managed modes. By setting the clock select An on-chip crystal oscillator circuit is incorporated bits, SCS<1:0> (OSCCON<1:0>), to ‘01’, the device between pins, T1OSI (input) and T1OSO (amplifier switches to SEC_RUN mode; both the CPU and output). It is enabled by setting the Timer1 Oscillator peripherals are clocked from the Timer1 oscillator. If the Enable bit, T1OSCEN (T1CON<3>). The oscillator is a IDLEN bit (OSCCON<7>) is cleared and a SLEEP low-power circuit rated for 32kHz crystals. It will instruction is executed, the device enters SEC_IDLE continue to run during all power-managed modes. The mode. Additional details are available in Section4.0 circuit for a typical LP oscillator is shown in Figure13-3. “Power-Managed Modes”. Table13-1 shows the capacitor selection for the Timer1 Whenever the Timer1 oscillator is providing the clock oscillator. source, the Timer1 System Clock Status Flag, T1RUN The user must provide a software time delay to ensure (T1CON<6>), is set. This can be used to determine the proper start-up of the Timer1 oscillator. controller’s current clocking mode. It can also indicate the clock source being currently used by the Fail-Safe FIGURE 13-3: EXTERNAL Clock Monitor. If the Clock Monitor is enabled and the COMPONENTS FOR THE Timer1 oscillator fails while providing the clock, polling TIMER1 LP OSCILLATOR the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source. C1 PIC18FXXXX 27 pF 13.3.2 LOW-POWER TIMER1 OPTION T1OSI The Timer1 oscillator can operate at two distinct levels of power consumption based on device configuration. XTAL 32.768 kHz When the LPT1OSC Configuration bit is set, the Timer1 oscillator operates in a low-power mode. When T1OSO LPT1OSC is not set, Timer1 operates at a higher power C2 level. Power consumption for a particular mode is rela- 27 pF tively constant, regardless of the device’s operating mode. The default Timer1 configuration is the higher Note: See the Notes with Table13-1 for additional power mode. information about capacitor selection. As the Low-Power Timer1 mode tends to be more sensitive to interference, high noise environments may cause some oscillator instability. The low-power option is therefore best suited for low noise applications where power conservation is an important design consideration.  2010 Microchip Technology Inc. DS39635C-page 157

PIC18F6310/6410/8310/8410 13.3.3 TIMER1 OSCILLATOR LAYOUT 13.6 Using Timer1 as a CONSIDERATIONS Real-Time Clock The Timer1 oscillator circuit draws very little power Adding an external LP oscillator to Timer1 (such as the during operation. Due to the low-power nature of the one described in Section13.3 “Timer1 Oscillator”, oscillator, it may also be sensitive to rapidly changing above), gives users the option to include RTC function- signals in close proximity. ality to their applications. This is accomplished with an The oscillator circuit, shown in Figure13-3, should be inexpensive watch crystal to provide an accurate time located as close as possible to the microcontroller. base and several lines of application code to calculate There should be no circuits passing within the oscillator the time. When operating in Sleep mode and using a circuit boundaries other than VSS or VDD. battery or supercapacitor as a power source, it can completely eliminate the need for a separate RTC If a high-speed circuit must be located near the oscilla- device and battery backup. tor (such as the CCP1 pin in Output Compare or PWM mode, or the primary oscillator using the OSC2 pin), a The application code routine, RTCisr, shown in grounded guard ring around the oscillator circuit may Example13-1, demonstrates a simple method to be helpful when used on a single sided PCB, or in increment a counter at one-second intervals using an addition to a ground plane. Interrupt Service Routine. Incrementing the TMR1 reg- ister pair to overflow triggers the interrupt and calls the 13.4 Timer1 Interrupt routine, which increments the seconds counter by one; additional counters for minutes and hours are The TMR1 register pair (TMR1H:TMR1L) increments incremented as the previous counter overflow. from 0000h to FFFFh and rolls over to 0000h. The Since the register pair is 16 bits wide, counting up to Timer1 interrupt, if enabled, is generated on overflow, overflow the register directly from a 32.768kHz clock which is latched in interrupt flag bit, TMR1IF would take 2 seconds. To force the overflow at the (PIR1<0>). This interrupt can be enabled or disabled required one-second intervals, it is necessary to by setting or clearing the Timer1 Interrupt Enable bit, preload it; the simplest method is to set the Most Sig- TMR1IE (PIE1<0>). nificant bit of TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered; doing 13.5 Resetting Timer1 Using the CCP so may introduce cumulative error over many cycles. Special Event Trigger For this method to be accurate, Timer1 must operate in If CCP1 or CCP2 is configured in Compare mode to Asynchronous mode and the Timer1 overflow interrupt generate a Special Event Trigger (CCP1M<3:0> or must be enabled (PIE1<0> = 1), as shown in the CCP2M<3:0>=1011), this signal will reset Timer1. routine RTCinit. The Timer1 oscillator must also be The trigger from CCP2 will also start an A/D conversion enabled and running at all times. if the A/D module is enabled (see Section16.3.4 “Special Event Triggers” for more information.). The module must be configured as either a timer or a synchronous counter to take advantage of this feature. When used this way, the CCPRH:CCPRL register pair effectively becomes a period register for Timer1. If Timer1 is running in Asynchronous Counter ‘mode, this Reset operation may not work. In the event that a write to Timer1 coincides with a Special Event Trigger, the write operation will take precedence. Note: The special event triggers from the CCP2 module will not set the TMR1IF interrupt flag bit (PIR1<0>). DS39635C-page 158  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 EXAMPLE 13-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW 80h ; Preload TMR1 register pair MOVWF TMR1H ; for 1 second overflow CLRF TMR1L MOVLW b‘00001111’ ; Configure for external clock, MOVWF T1CON ; Asynchronous operation, external oscillator CLRF secs ; Initialize timekeeping registers CLRF mins ; MOVLW .12 MOVWF hours BSF PIE1, TMR1IE ; Enable Timer1 interrupt RETURN RTCisr BSF TMR1H, 7 ; Preload for 1 sec overflow BCF PIR1, TMR1IF ; Clear interrupt flag INCF secs, F ; Increment seconds MOVLW .59 ; 60 seconds elapsed? CPFSGT secs RETURN ; No, done CLRF secs ; Clear seconds INCF mins, F ; Increment minutes MOVLW .59 ; 60 minutes elapsed? CPFSGT mins RETURN ; No, done CLRF mins ; clear minutes INCF hours, F ; Increment hours MOVLW .23 ; 24 hours elapsed? CPFSGT hours RETURN ; No, done MOVLW .01 ; Reset hours to 1 MOVWF hours RETURN ; Done TABLE 13-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 65 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 65 TMR1L Holding Register for the Least Significant Byte of the 16-Bit TMR1 Register 64 TMR1H Holding Register for the Most Significant Byte of the 16-Bit TMR1 Register 64 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 64 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.  2010 Microchip Technology Inc. DS39635C-page 159

PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 160  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 14.0 TIMER2 MODULE 14.1 Timer2 Operation The Timer2 timer module incorporates the following In normal operation, TMR2 is incremented from 00h on features: each clock (FOSC/4). A 2-bit counter/prescaler on the clock input gives direct input, divide-by-4 and divide-by-16 • 8-bit Timer and Period registers (TMR2 and PR2, prescale options; these are selected by the prescaler respectively) control bits, T2CKPS<1:0> (T2CON<1:0>). The value • Readable and writable (both registers) of TMR2 is compared to that of the period register, • Software-programmable prescaler (1:1, 1:4 and PR2, on each clock cycle. When the two values match, 1:16) the comparator generates a match signal as the timer • Software-programmable postscaler (1:1 through output. This signal also resets the value of TMR2 to 00h 1:16) on the next cycle and drives the output counter/ • Interrupt on TMR2-to-PR2 match postscaler (see Section14.2 “Timer2 Interrupt”). • Optional use as the shift clock for the MSSP The TMR2 and PR2 registers are both directly readable module and writable. The TMR2 register is cleared on any device Reset, while the PR2 register initializes at FFh. The module is controlled through the T2CON register Both the prescaler and postscaler counters are cleared (Register14-1), which enables or disables the timer on the following events: and configures the prescaler and postscaler. Timer2 can be shut off by clearing control bit, TMR2ON • a write to the TMR2 register (T2CON<2>), to minimize power consumption. • a write to the T2CON register A simplified block diagram of the module is shown in • any device Reset (Power-on Reset, MCLR Reset, Figure14-1. Watchdog Timer Reset, or Brown-out Reset) TMR2 is not cleared when T2CON is written. REGISTER 14-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16  2010 Microchip Technology Inc. DS39635C-page 161

PIC18F6310/6410/8310/8410 14.2 Timer2 Interrupt 14.3 TMR2 Output Timer2 also can generate an optional device interrupt. The unscaled output of TMR2 is available primarily to The Timer2 output signal (TMR2-to-PR2 match) pro- the CCP modules, where it is used as a time base for vides the input for the 4-bit output counter/postscaler. operations in PWM mode. This counter generates the TMR2 match interrupt flag Timer2 can be optionally used as the shift clock source which is latched in TMR2IF (PIR1<1>). The interrupt is for the MSSP module operating in SPI mode. Addi- enabled by setting the TMR2 Match Interrupt Enable tional information is provided in Section17.0 “Master bit, TMR2IE (PIE1<1>). Synchronous Serial Port (MSSP) Module”. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0> (T2CON<6:3>). FIGURE 14-1: TIMER2 BLOCK DIAGRAM 4 1:1 to 1:16 T2OUTPS<3:0> Set TMR2IF Postscaler 2 T2CKPS<1:0> TMR2 Output (to PWM or MSSP) TMR2/PR2 Reset Match 1:1, 1:4, 1:16 FOSC/4 TMR2 Comparator PR2 Prescaler 8 8 8 Internal Data Bus TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 65 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 65 TMR2 Timer2 Register 64 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 64 PR2 Timer2 Period Register 64 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. DS39635C-page 162  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 15.0 TIMER3 MODULE A simplified block diagram of the Timer3 module is shown in Figure15-1. A block diagram of the module’s The Timer3 timer/counter module incorporates these operation in Read/Write mode is shown in Figure15-2. features: The Timer3 module is controlled through the T3CON • Software-selectable operation as a 16-bit timer or register (Register15-1). It also selects the clock source counter options for the CCP modules (see Section16.1.1 • Readable and writable 8-bit registers (TMR3H “CCP Modules and Timer Resources” for more and TMR3L) information). • Selectable clock source (internal or external), with device clock or Timer1 oscillator internal options • Interrupt-on-overflow • Module Reset on CCP Special Event Trigger REGISTER 15-1: T3CON: TIMER3 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations bit 6, 3 T3CCP<2:1>: Timer3 and Timer1 to CCPx Enable bits 11 = Timer3 is the clock source for compare/capture of all CCP modules 10 = Timer3 is the clock source for compare/capture of CCP3, Timer1 is the clock source for compare/capture of CCP1 and CCP2 01 = Timer3 is the clock source for compare/capture of CCP2 and CCP3, Timer1 is the clock source for compare/capture of CCP1 00 = Timer1 is the clock source for compare/capture of all CCP modules bit 5-4 T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the device clock comes from Timer1/Timer3.) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3  2010 Microchip Technology Inc. DS39635C-page 163

PIC18F6310/6410/8310/8410 15.1 Timer3 Operation cycle (FOSC/4). When the bit is set, Timer3 increments on every rising edge of the Timer1 external clock input Timer3 can operate in one of three modes: or the Timer1 oscillator, if enabled. • Timer As with Timer1, the RC1/T1OSI and RC0/T1OSO/ • Synchronous counter T13CKI pins become inputs when the Timer1 oscillator • Asynchronous counter is enabled. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’. The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction FIGURE 15-1: TIMER3 BLOCK DIAGRAM Timer1 Oscillator 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR3CS Timer3 On/Off T3CKPS<1:0> T3SYNC TMR3ON CCP1/CCP2 Special Event Trigger Clear TMR3 TMR3 Set TCCPx TMR3L High Byte TMR3IF on Overflow Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 15-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator Timer1 clock input 1 T1OSO/T13CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR3CS Timer3 T3CKPS<1:0> On/Off T3SYNC TMR3ON CCP1/CCP2 Special Event Trigger Clear TMR3 TMR3 Set TCCPx TMR3L High Byte TMR3IF on Overflow 8 Read TMR3L Write TMR3L 8 8 TMR3H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39635C-page 164  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 15.2 Timer3 16-Bit Read/Write Mode 15.4 Timer3 Interrupt Timer3 can be configured for 16-bit reads and writes The TMR3 register pair (TMR3H:TMR3L) increments (see Figure15-2). When the RD16 control bit from 0000h to FFFFh and overflows to 0000h. The (T3CON<7>) is set, the address for TMR3H is mapped Timer3 interrupt, if enabled, is generated on overflow to a buffer register for the high byte of Timer3. A read and is latched in interrupt flag bit, TMR3IF (PIR2<1>). from TMR3L will load the contents of the high byte of This interrupt can be enabled or disabled by setting or Timer3 into the Timer3 High Byte Buffer register. This clearing the Timer3 Interrupt Enable bit, TMR3IE provides the user with the ability to accurately read all (PIE2<1>). 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low 15.5 Resetting Timer3 Using the CCP byte, has become invalid due to a rollover between Special Event Trigger reads. If either the CCP1 or CCP2 modules is configured to A write to the high byte of Timer3 must also take place generate a Special Event Trigger in Compare mode through the TMR3H Buffer register. The Timer3 high (CCP1M<3:0> or CCP2M<3:0> = 1011), this signal will byte is updated with the contents of TMR3H when a reset Timer3. The trigger of CCP2 will also start an A/D write occurs to TMR3L. This allows a user to write all conversion if the A/D module is enabled (see 16 bits to both the high and low bytes of Timer3 at once. Section16.3.4 “Special Event Triggers” for more The high byte of Timer3 is not directly readable or information). writable in this mode. All reads and writes must take The module must be configured as either a timer or place through the Timer3 High Byte Buffer register. synchronous counter to take advantage of this feature. Writes to TMR3H do not clear the Timer3 prescaler. When used this way, the CCPR2H:CCPR2L register The prescaler is only cleared on writes to TMR3L. pair effectively becomes a period register for Timer3. If Timer3 is running in Asynchronous Counter mode, 15.3 Using the Timer1 Oscillator as the the Reset operation may not work. Timer3 Clock Source In the event that a write to Timer3 coincides with a The Timer1 internal oscillator may be used as the clock Special Event Trigger from a CCP module, the write will source for Timer3. The Timer1 oscillator is enabled by take precedence. setting the T1OSCEN (T1CON<3>) bit. To use it as the Note: The special event triggers from the CCP2 Timer3 clock source, the TMR3CS bit must also be set. module will not set the TMR3IF interrupt As previously noted, this also configures Timer3 to flag bit (PIR1<0>). increment on every rising edge of the oscillator source. The Timer1 oscillator is described in Section13.0 “Timer1 Module”. TABLE 15-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR2 OSCFIF CMIF — — BCLIF HLVDIF TMR3IF CCP2IF 65 PIE2 OSCFIE CMIE — — BCLIE HLVDIE TMR3IE CCP2IE 65 IPR2 OSCFIP CMIP — — BCLIP HLVDIP TMR3IP CCP2IP 65 TMR3L Holding Register for the Least Significant Byte of the 16-Bit TMR3 Register 65 TMR3H Holding Register for the Most Significant Byte of the 16-Bit TMR3 Register 65 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 64 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 65 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.  2010 Microchip Technology Inc. DS39635C-page 165

PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 166  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 16.0 CAPTURE/COMPARE/PWM Each CCP module contains a 16-bit register which can (CCP) MODULES operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. PIC18F6310/6410/8310/8410 devices have three CCP For the sake of clarity, all CCP module operation in the (Capture/Compare/PWM) modules, labelled CCP1, following sections is described with respect to CCP2, CCP2 and CCP3. All modules implement standard but are equally applicable to CCP1 and CCP3. Capture, Compare and Pulse-Width Modulation (PWM) modes. REGISTER 16-1: CCPxCON: CCP1/CCP2/CCP3 CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCP Module x Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM Duty Cycle register. The eight Most Significant bits (DCx<9:2>) of the PWM Duty Cycle are found in CCPRxL. bit 3-0 CCPxM<3:0>: CCP Module x Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0001 = Reserved 0010 = Compare mode, toggle output on match (CCPxIF bit is set) 0011 = Reserved 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set) 1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set) 1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin reflects I/O state) 1011 = Compare mode: trigger special event, reset timer, start A/D conversion on CCPx match (CCPxIF bit is set)(1,2) 11xx = PWM mode Note 1: The Special Event Trigger on CCP1 will reset the timer but not start an A/D conversion on a CCP1 match. 2: For CCP3, the Special Event Trigger is not available. This mode functions the same as Compare Generate Interrupt mode (CCP3M<3:0> = 1010).  2010 Microchip Technology Inc. DS39635C-page 167

PIC18F6310/6410/8310/8410 16.1 CCP Module Configuration timer resource if they are configured to operate in the same mode (Capture/Compare or PWM) at the same Each Capture/Compare/PWM module is associated time. with a control register (generically, CCPxCON) and a Depending on the configuration selected, up to three data register (CCPRx). The data register, in turn, is timers may be active at once, with modules in the same comprised of two 8-bit registers: CCPRxL (low byte) configuration (Capture/Compare or PWM) sharing and CCPRxH (high byte). All registers are both timer resources. The possible configurations are readable and writable. shown in Figure16-1. 16.1.1 CCP MODULES AND TIMER 16.1.2 CCP2 PIN ASSIGNMENT RESOURCES The CCP2MX Configuration bit determines if CCP2 is The CCP modules utilize Timers 1, 2 or 3, depending multiplexed to its default or alternate assignment. By on the mode selected. Timer1 and Timer3 are available default, CCP2 is assigned to RC1 (CCP2MX = 1). If to modules in Capture or Compare modes, while CCP2MX is cleared, CCP2 is multiplexed with either Timer2 is available for modules in PWM mode. RE7 or RB3 (RE7 is the only alternative assignment for 64-pin devices). TABLE 16-1: CCP MODE – TIMER RESOURCE For any device in Microcontroller mode, the alternate CCP2 assignment is RE7. For 80-pin devices in CCP Mode Timer Resource Microcprocessor, Extended Microcontroller or Microcon- troller with Boot Block mode, the alternate assignment is Capture Timer1 or Timer3 RB3. Note that RE7 is the only alternative assignment for Compare Timer1 or Timer3 64-pin devices. PWM Timer2 Changing the pin assignment of CCP2 does not auto- The assignment of a particular timer to a module is matically change any requirements for configuring the determined by the Timer-to-CCP enable bits in the port pin. Users must always verify that the appropriate T3CON register (Register15-1). All three modules may TRIS register is configured correctly for CCP2 be active at any given time and may share the same operation, regardless of where it is located. FIGURE 16-1: CCP AND TIMER INTERCONNECT CONFIGURATIONS T3CCP<2:1> = 00 T3CCP<2:1> = 01 T3CCP<2:1> = 10 T3CCP<2:1> = 11 TMR1 TMR3 TMR1 TMR3 TMR1 TMR3 TMR1 TMR3 CCP1 CCP1 CCP1 CCP1 CCP2 CCP2 CCP2 CCP2 CCP3 CCP3 CCP3 CCP3 TMR2 TMR2 TMR2 TMR2 Timer1 is used for all Timer1 is used for Timer1 is used for Timer3 is used for all Capture and Compare Capture and Compare Capture and Compare Capture and Compare operations for all three operations for CCP1 operations for CCP1 operations for all three CCP modules. Timer2 and Timer 3 is used for and CCP2. Timer 3 is CCP modules. Timer2 is used for PWM oper- CCP2 and CCP3. used for CCP3. is used for PWM oper- ations for all three CCP All three modules All three modules ations for all three CCP modules. Timer3 is not share Timer2 as a share Timer2 as a modules. Timer1 is not used. common time base for common time base for used. All modules may share PWM operation. PWM operation. All modules may share Timer1 and Timer2 Timer2 and Timer3 resources as common resources as common time bases. time bases. DS39635C-page 168  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 16.2 Capture Mode 16.2.1 CCP PIN CONFIGURATION In Capture mode, the CCPR2H:CCPR2L register pair In Capture mode, the appropriate CCPx pin should be captures the 16-bit value of the TMR1 or TMR3 configured as an input by setting the corresponding registers when an event occurs on the CCP2 pin (RC1 TRIS direction bit. or RE7, depending on device configuration). An event Note: If RC1/CCP2 or RE7/CCP2 is configured is defined as one of the following: as an output, a write to the port can cause • every falling edge a capture condition. • every rising edge 16.2.2 TIMER1/TIMER3 MODE SELECTION • every 4th rising edge • every 16th rising edge The timers that are to be used with the capture feature (Timer1 and/or Timer3) must be running in Timer mode or The event is selected by the mode select bits, Synchronized Counter mode. In Asynchronous Counter CCP2M<3:0> (CCP2CON<3:0>). When a capture is mode, the capture operation may not work. The timer to made, the interrupt request flag bit, CCP2IF (PIR2<1>), be used with each CCP module is selected in the T3CON is set; it must be cleared in software. If another capture register (see Section16.1.1 “CCP Modules and Timer occurs before the value in register CCPR2 is read, the Resources”). old captured value is overwritten by the new captured value. FIGURE 16-2: CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H TMR3L Set CCP1IF T3CCP2 TMR3 Enable CCP1 Pin Prescaler and CCPR1H CCPR1L  1, 4, 16 Edge Detect TMR1 T3CCP2 Enable 4 TMR1H TMR1L CCP1CON<3:0> Set CCP2IF 4 Q1:Q4 4 CCP2CON<3:0> TMR3H TMR3L T3CCP1 TMR3 Enable CCP2 Pin Prescaler and CCPR2H CCPR2L  1, 4, 16 Edge Detect TMR1 T3CCP1 Enable TMR1H TMR1L Set CCP3IF 4 Q1:Q4 4 CCP3CON<3:0> T3CCP1 TMR3H TMR3L T3CCP2 TMR3 Enable CCP3 Pin Prescaler and CCPR3H CCPR3L  1, 4, 16 Edge Detect TMR1 Enable T3CCP2 TMR1H TMR1L T3CCP1  2010 Microchip Technology Inc. DS39635C-page 169

PIC18F6310/6410/8310/8410 16.2.3 SOFTWARE INTERRUPT 16.3.1 CCP PIN CONFIGURATION When the Capture mode is changed, a false capture The user must configure the CCPx pin as an output by interrupt may be generated. The user should keep bit, clearing the appropriate TRIS bit. CCP2IE (PIE2<1>), clear to avoid false interrupts and Note: Clearing the CCPxCON register will force should clear the flag bit, CCP2IF, following any such the RC1 or RE7 compare output latch change in operating mode. (depending on device configuration) to the 16.2.4 CCP PRESCALER default low level. This is not the PORTC or PORTE I/O data latch. There are four prescaler settings in Capture mode; they are specified as part of the operating mode selected by 16.3.2 TIMER1/TIMER3 MODE SELECTION the mode select bits (CCP2M<3:0>). Whenever the CCP module is turned off, or the CCP module is not in Timer1 and/or Timer3 must be running in Timer mode, Capture mode, the prescaler counter is cleared. This or Synchronized Counter mode, if the CCP module is using the compare feature. In Asynchronous Counter means that any Reset will clear the prescaler counter. mode, the compare operation may not work. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will 16.3.3 SOFTWARE INTERRUPT MODE not be cleared, therefore, the first capture may be from When the Generate Software Interrupt mode is chosen a non-zero prescaler. Example16-1 shows the (CCP2M<3:0> = 1010), the CCP2 pin is not affected. recommended method for switching between capture Only a CCP interrupt is generated if enabled and the prescalers. This example also clears the prescaler CCP2IE bit is set. counter and will not generate the “false” interrupt. 16.3.4 SPECIAL EVENT TRIGGERS EXAMPLE 16-1: CHANGING BETWEEN CAPTURE PRESCALERS CCP1 and CCP2 are both equipped with a Special Event Trigger. This is an internal hardware signal, CLRF CCP2CON ; Turn CCP module off generated in Compare mode, to trigger actions by other MOVLW NEW_CAPT_PS ; Load WREG with the modules. The Special Event Trigger is enabled by ; new prescaler mode selecting the Compare Special Event Trigger mode ; value and CCP ON (CCP2M<3:0> = 1011). MOVWF CCP2CON ; Load CCP2CON with ; this value For either CCP module, the Special Event Trigger resets the Timer register pair for whichever timer resource is currently assigned as the module’s time base. This 16.3 Compare Mode allows the CCPRx registers to serve as a programmable period register for either timer. In Compare mode, the 16-bit CCPR2 register value is constantly compared against either the TMR1 or TMR3 The Special Event Trigger for CCP2 can also start an register pair value. When a match occurs, the CCP2 A/D conversion. In order to do this, the A/D Converter pin can be: must already be enabled. • driven high Note: The Special Event Trigger of CCP1 only • driven low resets Timer1/Timer3 and cannot start an • toggled (high-to-low or low-to-high) A/D conversion even when the A/D Converter is enabled. • remain unchanged (that is, reflects the state of the I/O latch) CCP3 is not equipped with a Special Event Trigger. The action on the pin is based on the value of the mode Selecting the Compare Special Event Trigger mode for select bits (CCP2M<3:0>). At the same time, the this device (CCP3M<3:0> = 1011) is functionally the interrupt flag bit, CCP2IF, is set. same as selecting the Generate Software Interrupt mode (CCP3M<3:0> = 1010). DS39635C-page 170  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 16-3: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger T3CCP2 (Timer1/Timer3 Reset) Set CCP1IF CCP1 Pin 0 Compare Output S Q Comparator Match Logic 1 R TRIS 4 CCPR1H CCPR1L CCP1CON<3:0> Output Enable Special Event Trigger (Timer1/Timer3 Reset, A/D Trigger) TMR1H TMR1L T3CCP1 Set CCP2IF CCP2 Pin TMR3H TMR3L 0 Compare Output S Q Comparator Match Logic 1 R 4 TRIS Output Enable CCPR2H CCPR2L CCP2CON<3:0> T3CCP1 T3CCP2 Set CCP3IF CCP3 Pin 0 Compare Output S Q Comparator Match Logic 1 R TRIS 4 Output Enable CCPR3H CCPR3L CCP3CON<3:0>  2010 Microchip Technology Inc. DS39635C-page 171

PIC18F6310/6410/8310/8410 TABLE 16-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 RCON IPEN SBOREN — RI TO PD POR BOR 64 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 65 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 65 PIR2 OSCFIF CMIF — — BCLIF HLVDIF TMR3IF CCP2IF 65 PIE2 OSCFIE CMIE — — BCLIE HLVDIE TMR3IE CCP2IE 65 IPR2 OSCFIP CMIP — — BCLIP HLVDIP TMR3IP CCP2IP 65 PIR3 — — RC2IF TX2IF — — — CCP3IF 65 PIE3 — — RC2IE TX2IE — — — CCP3IE 65 IPR3 — — RC2IP TX2IP — — — CCP3IP 65 TRISB PORTB Data Direction Register 66 TRISC PORTC Data Direction Register 66 TRISE PORTE Data Direction Register 66 TMR1L Holding Register for the Least Significant Byte of the 16-Bit TMR1 Register 64 TMR1H Holding Register for the Most Significant Byte of the 16-Bit TMR1 Register 64 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 64 TMR3H Timer3 Register High Byte 65 TMR3L Timer3 Register Low Byte 65 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 65 CCPR1L Capture/Compare/PWM Register 1 (LSB) 65 CCPR1H Capture/Compare/PWM Register 1 (MSB) 65 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 65 CCPR2L Capture/Compare/PWM Register 2 (LSB) 65 CCPR2H Capture/Compare/PWM Register 2 (MSB) 65 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 65 CCPR3L Capture/Compare/PWM Register 3 (LSB) 65 CCPR3H Capture/Compare/PWM Register 3 (MSB) 65 CCP3CON — — DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 65 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3. DS39635C-page 172  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 16.4 PWM Mode A PWM output (Figure16-5) has a time base (period) and a time that the output stays high (duty cycle). The In Pulse-Width Modulation (PWM) mode, the CCP2 pin frequency of the PWM is the inverse of the period produces up to a 10-bit resolution PWM output. Since (1/period). the CCP2 pin is multiplexed with a PORTC or PORTE data latch, the appropriate TRIS bit must be cleared to FIGURE 16-5: PWM OUTPUT make the CCP2 pin an output. Period Note: Clearing the CCP2CON register will force the RC1 or RE7 output latch (depending on device configuration) to the default low level. This is not the PORTC or PORTE Duty Cycle I/O data latch. TMR2 = PR2 Figure16-4 shows a simplified block diagram of the TMR2 = Duty Cycle CCP module in PWM mode. For a step-by-step procedure on how to set up the CCP TMR2 = PR2 module for PWM operation, see Section16.4.3 “Setup for Pwm Operation”. 16.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 FIGURE 16-4: SIMPLIFIED PWM BLOCK register. The PWM period can be calculated using the DIAGRAM following formula: CCP1CON<5:4> Duty Cycle Registers EQUATION 16-1: CCPR1L PWM Period = (PR2) + 1] • 4 • TOSC • (TMR2 Prescale Value) PWM frequency is defined as 1/[PWM period]. CCPR1H (Slave) When TMR2 is equal to PR2, the following three events Comparator R Q occur on the next increment cycle: RC2/CCP1 • TMR2 is cleared TMR2 (Note 1) • The CCP2 pin is set (exception: if PWM duty S cycle=0%, the CCP2 pin will not be set) • The PWM duty cycle is latched from CCPR2L into Comparator TRISC<2> CCPR2H Clear Timer, CCP1 pin and Note: The Timer2 postscalers (see latch D.C. PR2 Section14.0 “Timer2 Module”) are not used in the determination of the PWM Note1: The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the frequency. The postscaler could be used 10-bit time base. to have a servo update rate at a different frequency than the PWM output.  2010 Microchip Technology Inc. DS39635C-page 173

PIC18F6310/6410/8310/8410 16.4.2 PWM DUTY CYCLE The maximum PWM resolution (bits) for a given PWM frequency is given by the equation: The PWM duty cycle is specified by writing to the CCPR2L register and to the CCP2CON<5:4> bits. Up EQUATION 16-3: to 10-bit resolution is available. The CCPR2L contains the eight MSbs and the CCP2CON<5:4> contains the FOSC log --------------- two LSbs. This 10-bit value is represented by FPWM PWM Resolution (max) = -----------------------------bits CCPR2L:CCP2CON<5:4>. The following equation is log2 used to calculate the PWM duty cycle in time: EQUATION 16-2: Note: If the PWM duty cycle value is longer than the PWM period, the CCP2 pin will not be PWM Duty Cycle = (CCPR2L:CCP2CON<5:4>) • cleared. TOSC • (TMR2 Prescale Value) CCPR2L and CCP2CON<5:4> can be written to at any 16.4.3 SETUP FOR PWM OPERATION time, but the duty cycle value is not latched into The following steps should be taken when configuring CCPR2H until after a match between PR2 and TMR2 the CCP module for PWM operation: occurs (i.e., the period is complete). In PWM mode, 1. Set the PWM period by writing to the PR2 CCPR2H is a read-only register. register. The CCPR2H register and a 2-bit internal latch are 2. Set the PWM duty cycle by writing to the used to double-buffer the PWM duty cycle. This CCPR2L register and CCP2CON<5:4> bits. double-buffering is essential for glitchless PWM 3. Make the CCP2 pin an output by clearing the operation. appropriate TRIS bit. When the CCPR2H and 2-bit latch match TMR2, 4. Set the TMR2 prescale value, then enable concatenated with an internal 2-bit Q clock or 2 bits of Timer2 by writing to T2CON. the TMR2 prescaler, the CCP2 pin is cleared. 5. Configure the CCP2 module for PWM operation. TABLE 16-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 DS39635C-page 174  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 16-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 RCON IPEN SBOREN — RI TO PD POR BOR 64 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 65 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 65 TRISB PORTB Data Direction Register 66 TRISC PORTC Data Direction Register 66 TRISE PORTE Data Direction Register 66 TMR2 Timer2 Register 64 PR2 Timer2 Period Register 64 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 64 CCPR1L Capture/Compare/PWM Register 1 (LSB) 65 CCPR1H Capture/Compare/PWM Register 1 (MSB) 65 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 65 CCPR2L Capture/Compare/PWM Register 2 (LSB) 65 CCPR2H Capture/Compare/PWM Register 2 (MSB) 65 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 65 CCPR3L Capture/Compare/PWM Register 3 (LSB) 65 CCPR3H Capture/Compare/PWM Register 3 (MSB) 65 CCP3CON — — DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 65 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.  2010 Microchip Technology Inc. DS39635C-page 175

PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 176  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 17.0 MASTER SYNCHRONOUS 17.3 SPI Mode SERIAL PORT (MSSP) The SPI mode allows 8 bits of data to be synchronously MODULE transmitted and received simultaneously. All four modes of SPI are supported. To accomplish 17.1 Master SSP (MSSP) Module communication, typically three pins are used: Overview • Serial Data Out (SDO) • Serial Data In (SDI) The Master Synchronous Serial Port (MSSP) module is • Serial Clock (SCK) a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral Additionally, a fourth pin may be used when in a Slave devices may be serial EEPROMs, shift registers, dis- mode of operation: play drivers, A/D converters, etc. The MSSP module • Slave Select (SS) can operate in one of two modes: Figure17-1 shows the block diagram of the MSSP • Serial Peripheral Interface (SPI) module when operating in SPI mode. • Inter-Integrated Circuit (I2C) - Full Master mode FIGURE 17-1: MSSP BLOCK DIAGRAM - Slave mode (with general address call) (SPI MODE) The I2C interface supports the following modes in Internal hardware: Data Bus • Master mode Read Write • Multi-Master mode SSPBUF reg • Slave mode 17.2 Control Registers SDI The MSSP module has three associated registers. SSPSR reg These include a status register (SSPSTAT) and two SDO bit 0 Shift Clock control registers (SSPCON1 and SSPCON2). The use of these registers and their individual configuration bits differ significantly depending on whether the MSSP module is operated in SPI or I2C mode. Additional details are provided under the individual SS SS Control sections. Enable Edge Select 2 Clock Select SSPM<3:0> SMP:CKE ( ) 4 TMR2 Output SCK 2 2 Edge Select Prescaler TOSC 4, 16, 64 Data to TXx/RXx in SSPSR TRIS bit  2010 Microchip Technology Inc. DS39635C-page 177

PIC18F6310/6410/8310/8410 17.3.1 REGISTERS SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes The MSSP module has four registers for SPI mode are written to or read from. operation. These are: In receive operations, SSPSR and SSPBUF together • MSSP Control Register 1 (SSPCON1) create a double-buffered receiver. When SSPSR • MSSP Status Register (SSPSTAT) receives a complete byte, it is transferred to SSPBUF • Serial Receive/Transmit Buffer Register (SSPBUF) and the SSPIF interrupt is set. • MSSP Shift Register (SSPSR) – Not directly During transmission, the SSPBUF is not double- accessible buffered. A write to SSPBUF will write to both SSPBUF SSPCON1 and SSPSTAT are the control and status and SSPSR. registers in SPI mode operation. The SSPCON1 register is readable and writable. The lower 6 bits of the SSPSTAT are read-only. The upper 2 bits of the SSPSTAT are read/write. REGISTER 17-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Edge Select bit When CKP = 0: 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK When CKP = 1: 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK bit 5 D/A: Data/Address bit Used in I2C mode only. bit 4 P: Stop bit Used in I2C™ mode only. This bit is cleared when the MSSP module is disabled; SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write bit Information Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty DS39635C-page 178  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow bit 5 SSPEN: Master Synchronous Serial Port Enable bit(2) 1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(3) 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note 1: In Master mode, the overflow bit is not set, since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as inputs or outputs. 3: Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only.  2010 Microchip Technology Inc. DS39635C-page 179

PIC18F6310/6410/8310/8410 17.3.2 OPERATION reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data When initializing the SPI, several options need to be will be ignored and the write collision detect bit, WCOL specified. This is done by programming the appropriate (SSPCON1<7>), will be set. User software must clear control bits (SSPCON1<5:0> and SSPSTAT<7:6>). the WCOL bit so that it can be determined if the follow- These control bits allow the following to be specified: ing write(s) to the SSPBUF register completed • Master mode (SCK is the clock output) successfully. • Slave mode (SCK is the clock input) When the application software is expecting to receive • Clock Polarity (Idle state of SCK) valid data, the SSPBUF should be read before the next • Data Input Sample Phase (middle or end of data byte of data to transfer is written to the SSPBUF. The output time) Buffer Full bit, BF (SSPSTAT<0>), indicates when • Clock Edge (output data on rising/falling edge of SSPBUF has been loaded with the received data SCK) (transmission is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the • Clock Rate (Master mode only) SPI is only a transmitter. Generally, the MSSP interrupt • Slave Select mode (Slave mode only) is used to determine when the transmission/reception The MSSP consists of a transmit/receive shift register has completed. The SSPBUF must be read and/or (SSPSR) and a buffer register (SSPBUF). The SSPSR written. If the interrupt method is not going to be used, shifts the data in and out of the device, MSb first. The then software polling can be done to ensure that a write SSPBUF holds the data that was written to the SSPSR collision does not occur. Example17-1 shows the until the received data is ready. Once the 8bits of data loading of the SSPBUF (SSPSR) for data transmission. have been received, that byte is moved to the SSPBUF The SSPSR is not directly readable or writable and can register. Then, the Buffer Full detect bit, BF only be accessed by addressing the SSPBUF register. (SSPSTAT<0>), and the interrupt flag bit, SSPIF, are Additionally, the MSSP Status register (SSPSTAT) set. This double-buffering of the received data indicates the various status conditions. (SSPBUF) allows the next byte to start reception before EXAMPLE 17-1: LOADING THE SSPBUF (SSPSR) REGISTER LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)? BRA LOOP ;No MOVF SSPBUF, W ;WREG reg = contents of SSPBUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSPBUF ;New data to xmit Note 1: The SSPBUF register cannot be used with read-modify-write instructions, such as BCF, BTFSC and COMF, etc. 2: To avoid lost data in Master mode, a read of the SSPBUF must be performed to clear the Buffer Full (BF) detect bit (SSPSTAT<0>) between each transmission. DS39635C-page 180  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 17.3.3 ENABLING SPI I/O 17.3.4 TYPICAL CONNECTION To enable the serial port, MSSP Enable bit, SSPEN Figure17-2 shows a typical connection between two (SSPCON1<5>), must be set. To reset or reconfigure microcontrollers. The master controller (Processor 1) SPI mode, clear the SSPEN bit, reinitialize the initiates the data transfer by sending the SCK signal. SSPCON registers and then set the SSPEN bit. This Data is shifted out of both shift registers on their pro- configures the SDI, SDO, SCK and SS pins as serial grammed clock edge and latched on the opposite edge port pins. For the pins to behave as the serial port func- of the clock. Both processors should be programmed to tion, some must have their data direction bits (in the the same Clock Polarity (CKP), then both controllers TRIS register) appropriately programmed as follows: would send and receive data at the same time. Whether the data is meaningful (or dummy data) • SDI must have TRISC<4> bit cleared depends on the application software. This leads to • SDO must have TRISC<5> bit cleared three scenarios for data transmission: • SCK (Master mode) must have TRISC<3> bit • Master sends data–Slave sends dummy data cleared • Master sends data–Slave sends data • SCK (Slave mode) must have TRISC<3> bit set • Master sends dummy data–Slave sends data • SS must have TRISF<7> bit set Any serial port function that is not desired may be overridden by programming the corresponding Data Direction (TRIS) register to the opposite value. FIGURE 17-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xxb SPI Slave SSPM<3:0> = 010xb SDO SDI Serial Input Buffer Serial Input Buffer (SSPBUF) (SSPBUF) SDI SDO Shift Register Shift Register (SSPSR) (SSPSR) MSb LSb MSb LSb Serial Clock SCK SCK PROCESSOR 1 PROCESSOR 2  2010 Microchip Technology Inc. DS39635C-page 181

PIC18F6310/6410/8310/8410 17.3.5 MASTER MODE The clock polarity is selected by appropriately programming the CKP bit (SSPCON1<4>). This then, The master can initiate the data transfer at any time would give waveforms for SPI communication as because it controls the SCK. The master determines shown in Figure17-3, Figure17-5 and Figure17-6, when the slave (Processor 2, Figure17-2) is to where the MSB is transmitted first. In Master mode, the broadcast data by the software protocol. SPI clock rate (bit rate) is user programmable to be one In Master mode, the data is transmitted/received as of the following: soon as the SSPBUF register is written to. If the SPI is • FOSC/4 (or TCY) only going to receive, the SDO output could be dis- abled (programmed as an input). The SSPSR register • FOSC/16 (or 4 • TCY) will continue to shift in the signal present on the SDI pin • FOSC/64 (or 16 • TCY) at the programmed clock rate. As each byte is • Timer2 output/2 received, it will be loaded into the SSPBUF register as Figure17-3 shows the waveforms for Master mode. if a normal received byte (interrupts and status bits When the CKE bit is set, the SDO data is valid before appropriately set). This could be useful in receiver there is a clock edge on SCK. The change of the input applications as a “Line Activity Monitor” mode. sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown. FIGURE 17-3: SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPIF Next Q4 Cycle SSPSR to after Q2 SSPBUF DS39635C-page 182  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 17.3.6 SLAVE MODE even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors In Slave mode, the data is transmitted and received as may be desirable, depending on the application. the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. Note 1: When the SPI is in Slave mode with SS pin While in Slave mode, the external clock is supplied by control enabled (SSPCON<3:0> = 0100), the external clock source on the SCK pin. This external the SPI module will reset if the SS pin is clock must meet the minimum high and low times as set to VDD. specified in the electrical specifications. 2: If the SPI is used in Slave mode with CKE While in Sleep mode, the slave can transmit/receive set, then the SS pin control must be data. When a byte is received, the device will wake-up enabled from Sleep. When the SPI module resets, the bit counter is forced 17.3.7 SLAVE SELECT to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. SYNCHRONIZATION To emulate two-wire communication, the SDO pin can The SS pin allows a Synchronous Slave mode. The be connected to the SDI pin. When the SPI needs to SPI must be in Slave mode with SS pin control enabled operate as a receiver, the SDO pin can be configured (SSPCON1<3:0> = 04h). The pin must not be driven as an input. This disables transmissions from the SDO. low for the SS pin to function as an input. The data latch The SDI can always be left as an input (SDI function) must be high. When the SS pin is low, transmission and since it cannot create a bus conflict. reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, FIGURE 17-4: SLAVE SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 7 bit 0 SDI bit 0 (SMP = 0) bit 7 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle SSPSR to after Q2 SSPBUF  2010 Microchip Technology Inc. DS39635C-page 183

PIC18F6310/6410/8310/8410 FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle SSPSR to after Q2 SSPBUF FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2 SSPSR to SSPBUF DS39635C-page 184  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 17.3.8 SLEEP OPERATION 17.3.9 EFFECTS OF A RESET In SPI Master mode, module clocks may be operating A Reset disables the MSSP module and terminates the at a different speed than when in Full-Power mode; in current transfer. the case of the Sleep mode, all clocks are halted. 17.3.10 BUS MODE COMPATIBILITY In most power-managed modes, a clock is provided to the peripherals. That clock should be from the primary Table17-1 shows the compatibility between the clock source, the secondary clock (Timer1 oscillator at standard SPI modes and the states of the CKP and 32.768 kHz) or the INTOSC source. See Section3.7 CKE control bits. “Clock Sources and Oscillator Switching” for additional information. TABLE 17-1: SPI BUS MODES In most cases, the speed that the master clocks SPI Control Bits State Standard SPI Mode data is not important; however, this should be Terminology evaluated for each system. CKP CKE If MSSP interrupts are enabled, they can wake the con- 0, 0 0 1 troller from Sleep mode, or one of the Idle modes, when 0, 1 0 0 the master completes sending data. If an exit from 1, 0 1 1 Sleep or Idle mode is not desired, MSSP interrupts should be disabled. 1, 1 1 0 If the Sleep mode is selected, all module clocks are There is also an SMP bit which controls when the data halted and the transmission/reception will remain in is sampled. that state until the devices wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in any power-managed mode and data to be shifted into the SPI Transmit/ Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. TABLE 17-2: REGISTERS ASSOCIATED WITH SPI OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 65 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 65 TRISC PORTC Data Direction Register 66 TRISF PORTF Data Direction Register 66 SSPBUF Master Synchronous Serial Port Receive Buffer/Transmit Register 64 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 64 SSPSTAT SMP CKE D/A P S R/W UA BF 64 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.  2010 Microchip Technology Inc. DS39635C-page 185

PIC18F6310/6410/8310/8410 17.4 I2C Mode 17.4.1 REGISTERS The MSSP module in I2C mode fully implements all The MSSP module has six registers for I2C operation. master and slave functions (including general call These are: support) and provides interrupts on Start and Stop bits • MSSP Control Register 1 (SSPCON1) in hardware to determine a free bus (multi-master • MSSP Control Register 2 (SSPCON2) function). The MSSP module implements the standard • MSSP Status Register (SSPSTAT) mode specifications as well as 7-bit and 10-bit • Serial Receive/Transmit Buffer Register addressing. (SSPBUF) Two pins are used for data transfer: • MSSP Shift Register (SSPSR) – Not directly • Serial clock (SCL) – RC3/SCK/SCL accessible • Serial data (SDA) – RC4/SDI/SDA • MSSP Address Register (SSPADD) The user must configure these pins as inputs through SSPCON1, SSPCON2 and SSPSTAT are the control the TRISC<4:3> bits. and status registers in I2C mode operation. The SSPCON1 and SSPCON2 registers are readable and FIGURE 17-7: MSSP BLOCK DIAGRAM writable. The lower 6 bits of the SSPSTAT are read-only. (I2C™ MODE) The upper 2 bits of the SSPSTAT are read/write. SSPSR is the shift register used for shifting data in or Internal out. SSPBUF is the buffer register to which data bytes Data Bus are written to, or read from. Read Write SSPADD register holds the slave device address when the MSSP is configured in I2C Slave mode. SCL SSPBUF reg When the MSSP is configured in Master mode, the lower 7 bits of SSPADD act as the Baud Rate Shift Generator reload value. Clock In receive operations, SSPSR and SSPBUF together SSPSR reg create a double-buffered receiver. When SSPSR SDA MSb LSb receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. Match Detect Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. SSPADD reg Start and Set, Reset Stop bit Detect S, P bits (SSPSTAT reg) DS39635C-page 186  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 REGISTER 17-3: SSPSTAT: MSSP STATUS REGISTER (I2C™ MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P(1) S(1) R/W(2,3) UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit(1) 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last bit 3 S: Start bit(1) 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last bit 2 R/W: Read/Write bit Information (I2C mode only) In Slave mode:(2) 1 = Read 0 = Write In Master mode:(3) 1 = Transmit is in progress 0 = Transmit is not in progress bit 1 UA: Update Address bit (10-Bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty In Receive mode: 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I2C mode only.  2010 Microchip Technology Inc. DS39635C-page 187

PIC18F6310/6410/8310/8410 REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SMP CKE D/A P(1) S(1) R/W(2,3) UA BF bit 7 bit 0 bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit(1) 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last bit 3 S: Start bit(1) 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last bit 2 R/W: Read/Write bit Information (I2C mode only) In Slave mode:(2) 1 = Read 0 = Write In Master mode:(3) 1 = Transmit is in progress 0 = Transmit is not in progress bit 1 UA: Update Address bit (10-Bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty In Receive mode: 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty Note 1: This bit is cleared on Reset and when SSPEN is cleared. 2: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. DS39635C-page 188  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(1) 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)(2) 1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit; automatically cleared by hardware 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (Master mode only)(2) 1 = Enables Receive mode for I2C 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit (Master mode only)(2) 1 = Initiate Stop condition on SDA and SCL pins; automatically cleared by hardware 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit (Master mode only)(2) 1 = Initiate Repeated Start condition on SDA and SCL pins; automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable/Stretch Enable bit(2) In Master mode: 1 = Initiate Start condition on SDA and SCL pins; automatically cleared by hardware 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. 2: If the I2C module is not in Idle mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).  2010 Microchip Technology Inc. DS39635C-page 189

PIC18F6310/6410/8310/8410 17.4.2 OPERATION 17.4.3.1 Addressing The MSSP module functions are enabled by setting Once the MSSP module has been enabled, it waits for MSSP Enable bit, SSPEN (SSPCON<5>). a Start condition to occur. Following the Start condition, The SSPCON1 register allows control of the I2C the 8 bits are shifted into the SSPSR register. All incom- ing bits are sampled with the rising edge of the clock operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I2C modes to be selected: (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The • I2C Master mode, Clock = (FOSC/4) x (SSPADD+1) address is compared on the falling edge of the eighth • I2C Slave mode (7-bit address) clock (SCL) pulse. If the addresses match and the BF • I2C Slave mode (10-bit address) and SSPOV bits are clear, the following events occur: • I2C Slave mode (7-bit address) with Start and 1. The SSPSR register value is loaded into the Stop bit interrupts enabled SSPBUF register. • I2C Slave mode (10-bit address) with Start and 2. The Buffer Full bit, BF, is set. Stop bit interrupts enabled 3. An ACK pulse is generated. • I2C Firmware Controlled Master mode, slave is 4. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is Idle set (interrupt is generated, if enabled) on the Selection of any I2C mode with the SSPEN bit set, falling edge of the ninth SCL pulse. forces the SCL and SDA pins to be open-drain, In 10-Bit Addressing mode, two address bytes need to provided these pins are programmed to inputs by be received by the slave. The five Most Significant bits setting the appropriate TRISC bits. To ensure proper (MSbs) of the first address byte specify if this is a 10-bit operation of the module, pull-up resistors must be address. Bit, R/W (SSPSTAT<2>), must specify a write provided externally to the SCL and SDA pins. so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal 17.4.3 SLAVE MODE ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two In Slave mode, the SCL and SDA pins must be config- MSbs of the address. The sequence of events for 10-bit ured as inputs (TRISC<4:3> set). The MSSP module addressing is as follows, with Steps 7 through 9 for the will override the input state with the output data when slave-transmitter: required (slave-transmitter). 1. Receive first (high) byte of address (bits, SSPIF, The I2C Slave mode hardware will always generate an BF and UA (SSPSTAT<1>), are set). interrupt on an address match. Through the mode 2. Update the SSPADD register with second (low) select bits, the user can also choose to interrupt on byte of address (clears bit, UA, and releases the Start and Stop bits SCL line). When an address is matched, or the data transfer after 3. Read the SSPBUF register (clears bit, BF) and an address match is received, the hardware automati- clear flag bit, SSPIF. cally will generate the Acknowledge (ACK) pulse and 4. Receive second (low) byte of address (SSPIF, load the SSPBUF register with the received value BF and UA bits are set). currently in the SSPSR register. 5. Update the SSPADD register with the first (high) Any combination of the following conditions will cause byte of address. If match releases SCL line, this the MSSP module not to give this ACK pulse: will clear bit, UA. • The Buffer Full bit, BF (SSPSTAT<0>), was set 6. Read the SSPBUF register (clears bit, BF) and before the transfer was received. clear flag bit, SSPIF. • The overflow bit, SSPOV (SSPCON<6>), was set 7. Receive Repeated Start condition. before the transfer was received. 8. Receive first (high) byte of address (bits, SSPIF and BF, are set). In this case, the SSPSR register value is not loaded into the SSPBUF, but bit, SSPIF (PIR1<3>), is set. The 9. Read the SSPBUF register (clears bit, BF) and BF bit is cleared by reading the SSPBUF register, while clear flag bit, SSPIF. bit, SSPOV, is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing Parameter #100 and Parameter #101. DS39635C-page 190  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 17.4.3.2 Reception 17.4.3.3 Transmission When the R/W bit of the address byte is clear and an When the R/W bit of the incoming address byte is set address match occurs, the R/W bit of the SSPSTAT and an address match occurs, the R/W bit of the register is cleared. The received address is loaded into SSPSTAT register is set. The received address is loaded the SSPBUF register and the SDA line is held low into the SSPBUF register. The ACK pulse will be sent on (ACK). the ninth bit and pin, RC3/SCK/SCL, is held low regard- less of SEN (see Section17.4.4 “Clock Stretching” When the address byte overflow condition exists, then for more detail). By stretching the clock, the master will the no Acknowledge (ACK) pulse is given. An overflow be unable to assert another clock pulse until the slave is condition is defined as either bit, BF (SSPSTAT<0>), is done preparing the transmit data. The transmit data set or bit, SSPOV (SSPCON1<6>), is set. must be loaded into the SSPBUF register which also An MSSP interrupt is generated for each data transfer loads the SSPSR register. Then, the RC3/SCK/SCL pin byte. Flag bit, SSPIF (PIR1<3>), must be cleared in should be enabled by setting bit, CKP (SSPCON1<4>). software. The SSPSTAT register is used to determine The 8 data bits are shifted out on the falling edge of the the status of the byte. SCL input. This ensures that the SDA signal is valid If SEN is enabled (SSPCON2<0> = 1), RC3/SCK/SCL during the SCL high time (Figure17-9). will be held low (clock stretch) following each data The ACK pulse from the master-receiver is latched on transfer. The clock must be released by setting bit, the rising edge of the ninth SCL input pulse. If the SDA CKP (SSPCON<4>). See Section17.4.4 “Clock line is high (not ACK), then the data transfer is Stretching” for more details. complete. In this case, when the ACK is latched by the slave, the slave monitors for another occurrence of the Start bit. If the SDA line was low (ACK), the next trans- mit data must be loaded into the SSPBUF register. Again, pin, RC3/SCK/SCL, must be enabled by setting bit, CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse.  2010 Microchip Technology Inc. DS39635C-page 191

PIC18F6310/6410/8310/8410 2 FIGURE 17-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 D6 2 7 D 1 K C A 9 0 D 8 1 D 7 D2 6 a 3 at D 5 D e Receiving D6D5D4 234 Cleared in softwarSSPBUF is read 7 D 1 K 9 = 0 AC W 8 R/ A1 7 A2 6 = )0 ddress A3 5 n SEN A e Receiving A5A4 34 set to ‘’ wh0 e ot r A6 2 s n e A7 1 0>) ON1<6>) (CKP do SDA SCLS SSPIF (PIR1<3>) BF (SSPSTAT< SSPOV (SSPC CKP DS39635C-page 192  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 2 FIGURE 17-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) P R S ACK 9 PIF I S D0 8 m S o Data D1 7 Fr Transmitting D6D5D4D3D2 23456 Cleared in software SSPBUF is written in software KP is set in software C D7 1 R ACK 9 PIF IS S D0 8 m S o 1 Fr D 7 a g Dat D2 6 ware Transmittin D6D5D4D3 2345 Cleared in software SSPBUF is written in soft ding CKP is set in software D7 1 SCL held lowwhile CPUresponds to SSPIF Clear by rea K C A 9 1 = W 8 R/ 1 A 7 2 ess A 6 Addr A3 5 g eivin A4 4 ec R A5 3 A6A7 12 Data in sampled >) 0>) 1<4>) 3 < N DA CL S SPIF (PIR1< F (SSPSTAT KP (SSPCO S S S B C  2010 Microchip Technology Inc. DS39635C-page 193

PIC18F6310/6410/8310/8410 FIGURE 17-10: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. 0 D 8 1 D 7 e Byte 3D2 6 softwar a D 5 n ceive Dat D5D4 34 Cleared i e R 6 D 2 7 D 1 K AC 9 0 D 8 untilD has Receive Data Byte D6D5D4D3D1D2 234576 Cleared in software Cleared by hardware whenSSPADD is updated with highbyte of address d low SPAD D7 1 Clock is helupdate of Staken place ACK0 89 Clock is held low untilupdate of SSPADD has taken place Receive First Byte of AddressReceive Second Byte of AddressR/W = 0 ACK11110A9A8A7A6A5A4A3A2A1A 1234567891234567 Cleared in softwareCleared in software AT<0>) SSPBUF is written withDummy read of SSPBUFcontents of SSPSRto clear BF flag PCON1<6>) AT<1>) UA is set indicating thatCleared by hardwarethe SSPADD needs to bewhen SSPADD is updatedupdatedwith low byte of address UA is set indicating thatSSPADD needs to beupdated (CKP does not reset to ‘’ when SEN = )00 SDA SCLS SSPIF (PIR1<3>) BF (SSPST SSPOV (SS UA (SSPST KP C DS39635C-page 194  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 2 FIGURE 17-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) Bus masterterminatestransfer ACK D0 89P Completion ofdata transmissionclears BF flag are, holding SCL low w Clock is held low untilupdate of SSPADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive First Byte of AddressTransmitting Data ByteR/W = 1 ACK11110A8A9D7D6D5D4D3D1D2ACK 91234578961234576Sr Cleared in softwareCleared in software Dummy read of SSPBUFWrite of SSPBUFBF flag is clearto clear BF flaginitiates transmitat the end of thethird address sequence Cleared by hardware whenSSPADD is updated with highbyte of address. CKP is set in software CKP is automatically cleared in hard Clock is held low untilupdate of SSPADD has taken place W = 0Receive Second Byte of Address A7A6A5A4A3A2A1A0ACK 912345678 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with lowbyte of address UA is set indicating thatSSPADD needs to beupdated R/e First Byte of Address 110A9A8 345678 SSPBUF is written withcontents of SSPSR UA is set indicating thatthe SSPADD needs to beupdated Receiv 11 12 AT<0>) AT<1>) ON1<4>) SDA SCLS SSPIF (PIR1<3>) BF (SSPST UA (SSPST CKP (SSPC  2010 Microchip Technology Inc. DS39635C-page 195

PIC18F6310/6410/8310/8410 17.4.4 CLOCK STRETCHING 17.4.4.3 Clock Stretching for 7-Bit Slave Transmit Mode Both 7 and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. 7-Bit Slave Transmit mode implements clock stretching The SEN bit (SSPCON2<0>) allows clock stretching to by clearing the CKP bit after the falling edge of the ninth clock, if the BF bit is clear. This occurs regardless of the be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data state of the SEN bit. receive sequence. The user’s ISR must set the CKP bit before transmis- sion is allowed to continue. By holding the SCL line 17.4.4.1 Clock Stretching for 7-Bit Slave low, the user has time to service the ISR and load the Receive Mode (SEN = 1) contents of the SSPBUF before the master device can In 7-Bit Slave Receive mode, on the falling edge of the initiate another transmit sequence (see Figure17-9). ninth clock at the end of the ACK sequence, if the BF Note1: If the user loads the contents of SSPBUF, bit is set, the CKP bit in the SSPCON1 register is setting the BF bit before the falling edge automatically cleared, forcing the SCL output to be of the ninth clock, the CKP bit will not be held low. The CKP being cleared to ‘0’ will assert the cleared and clock stretching will not SCL line low. The CKP bit must be set in the user’s occur. ISR before reception is allowed to continue. By holding the SCL line low, the user has time to service the ISR 2: The CKP bit can be set in software regardless of the state of the BF bit. and read the contents of the SSPBUF before the master device can initiate another receive sequence. 17.4.4.4 Clock Stretching for 10-Bit Slave This will prevent buffer overruns from occurring (see Transmit Mode Figure17-13). In 10-Bit Slave Transmit mode, clock stretching is Note1: If the user reads the contents of the controlled during the first two address sequences by SSPBUF before the falling edge of the the state of the UA bit, just as it is in 10-Bit Slave ninth clock, thus clearing the BF bit, the Receive mode. The first two addresses are followed CKP bit will not be cleared and clock by a third address sequence which contains the high- stretching will not occur. order bits of the 10-bit address and the R/W bit set to 2: The CKP bit can be set in software ‘1’. After the third address sequence is performed, the regardless of the state of the BF bit. The UA bit is not set, the module is now configured in user should be careful to clear the BF bit Transmit mode and clock stretching is controlled by in the ISR before the next receive the BF flag as in 7-Bit Slave Transmit mode (see sequence in order to prevent an overflow Figure17-11). condition. 17.4.4.2 Clock Stretching for 10-Bit Slave Receive Mode (SEN = 1) In 10-Bit Slave Receive mode during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to ‘0’. The release of the clock line occurs upon updating SSPADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPADD register before the falling edge of the ninth clock occurs and if the user hasn’t cleared the BF bit by read- ing the SSPBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. DS39635C-page 196  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 17.4.4.5 Clock Synchronization and already asserted the SCL line. The SCL output will the CKP bit remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL. This When the CKP bit is cleared, the SCL output is forced ensures that a write to the CKP bit will not violate the to ‘0’. However, setting the CKP bit will not assert the minimum high time requirement for SCL (see SCL output low until the SCL output is already Figure17-12). sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has FIGURE 17-12: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX – 1 SCL Master device CKP asserts clock Master device deasserts clock WR SSPCON  2010 Microchip Technology Inc. DS39635C-page 197

PIC18F6310/6410/8310/8410 2 FIGURE 17-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) w Clock is not held lobecause ACK = 1 ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 e Clock is held low untilCKP is set to ‘’1 ACK D0D7D6 8912 CKPwrittento ‘’ in1softwarBF is set after falling edge of the 9th clock,CKP is reset to ‘’ and0clock stretching occurs 1 D 7 D2 6 Clock is not held lowbecause buffer full bit is clear prior to falling edge of 9th clock Receiving Data D7D6D5D4D3 12345 Cleared in software SPBUF is read If BF is clearedprior to the fallingedge of the 9th clock,CKP will not be resetto ‘’ and no clock0stretching will occur S K 9 0 C = A W 8 R/ A1 7 A2 6 s s e ddr A3 5 A g eivin A4 4 c e R A5 3 A6 2 >) 6 A7 1 0>) ON1< SDA SCLS SSPIF (PIR1<3>) BF (SSPSTAT< SSPOV (SSPC CKP DS39635C-page 198  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 17-14: I2C™ SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS) w ent. Clock is not held lobecause ACK = 1 ACK 0 9P Bus masterterminatestransfer SSPOV is setbecause SSPBUF isstill full. ACK is not s D 8 1 D 7 e Clock is held low untilupdate of SSPADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive Data ByteReceive Data Byte ACKD7D6D5D4D3D1D0D2D7D6D5D4D3D2 123457896123456 Cleared in softwareCleared in softwar Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with highbyte of address after falling edgeof ninth clock CKP written to ‘’1in software Note:An update of the SSPADD register beforethe falling edge of the ninth clock will haveno effect on UA and UA will remain set. K C 9 A Clock is held low untilupdate of SSPADD has taken place Receive Second Byte of AddressW = 0 A7A6A5A4A3A2A1A0ACK 912345678 Cleared in software Dummy read of SSPBUFto clear BF flag Cleared by hardware whenSSPADD is updated with lowbyte of address after falling edgeof ninth clock UA is set indicating thatSSPADD needs to beupdated Note:An update of the SSPADDregister before the fallingedge of the ninth clock willhave no effect on UA andUA will remain set. Receive First Byte of AddressR/ 1110A9A8 2345678 Cleared in software >) SSPBUF is written withcontents of SSPSR N1<6>) >) UA is set indicating thatthe SSPADD needs to beupdated 1 1 AT<0 PCO AT<1 SDA SCLS SSPIF (PIR1<3>) BF (SSPST SSPOV (SS UA (SSPST KP C  2010 Microchip Technology Inc. DS39635C-page 199

PIC18F6310/6410/8310/8410 17.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPSR is SUPPORT transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the The addressing procedure for the I2C bus is such that SSPIF interrupt flag bit is set. the first byte after the Start condition usually deter- mines which device will be the slave addressed by the When the interrupt is serviced, the source for the inter- master. The exception is the general call address which rupt can be checked by reading the contents of the can address all devices. When this address is used, all SSPBUF. The value can be used to determine if the devices should, in theory, respond with an address was device specific or a general call address. Acknowledge. In 10-bit mode, the SSPADD is required to be updated The general call address is one of eight addresses for the second half of the address to match and the UA reserved for specific purposes by the I2C protocol. It bit is set (SSPSTAT<1>). If the general call address is consists of all ‘0’s with R/W = 0. sampled when the GCEN bit is set, while the slave is configured in 10-Bit Addressing mode, then the second The general call address is recognized when the Gen- half of the address is not necessary, the UA bit will not eral Call Enable bit (GCEN) is enabled (SSPCON2<7> be set and the slave will begin receiving data after the set). Following a Start bit detect, 8 bits are shifted into Acknowledge (Figure17-15). the SSPSR and the address is compared against the SSPADD. It is also compared to the general call address and fixed in hardware. FIGURE 17-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESSING MODE) Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPIF BF (SSPSTAT<0>) Cleared in software SSPBUF is read SSPOV (SSPCON1<6>) ‘0’ GCEN (SSPCON2<7>) ‘1’ DS39635C-page 200  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 17.4.6 MASTER MODE Note: The MSSP module, when configured in Master mode is enabled by setting and clearing the I2C Master mode, does not allow queueing appropriate SSPM bits in SSPCON1 and by setting the of events. For instance, the user is not SSPEN bit. In Master mode, the SCL and SDA lines allowed to initiate a Start condition and are manipulated by the MSSP hardware. immediately write the SSPBUF register to initiate transmission before the Start Master mode of operation is supported by interrupt condition is complete. In this case, the generation on the detection of the Start and Stop con- SSPBUF will not be written to and the ditions. The Stop (P) and Start (S) bits are cleared from WCOL bit will be set, indicating that a write a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is set or the to the SSPBUF did not occur. bus is Idle, with both the S and P bits clear. The following events will cause MSSP Interrupt Flag In Firmware Controlled Master mode, user code bit, SSPIF, to be set (MSSP interrupt, if enabled): conducts all I2C bus operations based on Start and • Start condition Stop bit conditions. • Stop condition Once Master mode is enabled, the user has six • Data transfer byte transmitted/received options. • Acknowledge transmit 1. Assert a Start condition on SDA and SCL. • Repeated Start 2. Assert a Repeated Start condition on SDA and SCL. 3. Write to the SSPBUF register initiating transmission of data/address. 4. Configure the I2C port to receive data. 5. Generate an Acknowledge condition at the end of a received byte of data. 6. Generate a Stop condition on SDA and SCL. 2 FIGURE 17-16: MSSP BLOCK DIAGRAM (I C™ MASTER MODE) Internal SSPM<3:0> Data Bus SSPADD<6:0> Read Write SSPBUF Baud Rate Generator SDA Shift SDA In Clock SSPSR ect MSb LSb Detce) ble OL our a Cs En Start bit, Stop bit, Wck SCL Receive AcGkennoewrlaetdege Clock Cntl k Arbitrate/hold off clo c( o Cl Start bit Detect Stop bit Detect SCL In Write Collision Detect Set/Reset, S, P, WCOL (SSPSTAT); Clock Arbitration Set SSPIF, BCLIF; Bus Collision State Counter for Reset ACKSTAT, PEN (SSPCON2) end of XMIT/RCV  2010 Microchip Technology Inc. DS39635C-page 201

PIC18F6310/6410/8310/8410 17.4.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock 1. The user generates a Start condition by setting pulses and the Start and Stop conditions. A transfer is the Start Enable bit, SEN (SSPCON2<0>). ended with a Stop condition or with a Repeated Start 2. SSPIF is set. The MSSP module will wait the condition. Since the Repeated Start condition is also required start time before any other operation the beginning of the next serial transfer, the I2C bus will takes place. not be released. 3. The user loads the SSPBUF with the slave In Master Transmitter mode, serial data is output address to transmit. through SDA, while SCL outputs the serial clock. The 4. Address is shifted out the SDA pin until all 8 bits first byte transmitted contains the slave address of the are transmitted. receiving device (7 bits) and the Read/Write (R/W) bit. 5. The MSSP module shifts in the ACK bit from the In this case, the R/W bit will be logic ‘0’. Serial data is slave device and writes its value into the transmitted, 8 bits at a time. After each byte is transmit- SSPCON2 register (SSPCON2<6>). ted, an Acknowledge bit is received. Start and Stop 6. The MSSP module generates an interrupt at the conditions are output to indicate the beginning and the end of the ninth clock cycle by setting the SSPIF end of a serial transfer. bit. In Master Receive mode, the first byte transmitted 7. The user loads the SSPBUF with 8 bits of data. contains the slave address of the transmitting device 8. Data is shifted out the SDA pin until all 8 bits are (7bits) and the R/W bit. In this case, the R/W bit will be transmitted. logic ‘1’. Thus, the first byte transmitted is a 7-bit slave 9. The MSSP module shifts in the ACK bit from the address, followed by a ‘1’ to indicate the receive bit. slave device and writes its value into the Serial data is received via SDA, while SCL outputs the SSPCON2 register (SSPCON2<6>). serial clock. Serial data is received 8 bits at a time. After each byte is received, an Acknowledge bit is transmit- 10. The MSSP module generates an interrupt at the ted. Start and Stop conditions indicate the beginning end of the ninth clock cycle by setting the SSPIF and end of transmission. bit. 11. The user generates a Stop condition by setting The Baud Rate Generator used for the SPI mode oper- the Stop Enable bit, PEN (SSPCON2<2>). ation is used to set the SCL clock frequency for either 100 kHz, 400 kHz or 1 MHz I2C operation. See 12. Interrupt is generated once the Stop condition is Section17.4.7 “Baud Rate” for more detail. complete. DS39635C-page 202  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 17.4.7 BAUD RATE Once the given operation is complete (i.e., transmis- In I2C Master mode, the Baud Rate Generator (BRG) sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin reload value is placed in the lower 7 bits of the will remain in its last state. SSPADD register (Figure17-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically Table17-3 demonstrates clock rates based on begin counting. The BRG counts down to ‘0’ and stops instruction cycles and the BRG value loaded into until another reload has taken place. The BRG count is SSPADD. Table17-3 demonstrates clock rates based decremented twice per instruction cycle (TCY) on the on instruction cycles and the BRG value loaded into Q2 and Q4 clocks. In I2C Master mode, the BRG is SSPADD. The SSPADD BRG value of ‘0x00’ is not reloaded automatically. supported. FIGURE 17-17: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPADD<6:0> SSPM<3:0> Reload Reload SCL Control CLKO BRG Down Counter FOSC/4 TABLE 17-3: I2C™ CLOCK RATE W/BRG FSCL FCY FCY*2 BRG Value (2 Rollovers of BRG) 10 MHz 20 MHz 19h 400 kHz 10 MHz 20 MHz 20h 312.5 kHz 10 MHz 20 MHz 3Fh 100 kHz 4 MHz 8 MHz 0Ah 400 kHz 4 MHz 8 MHz 0Dh 308 kHz 4 MHz 8 MHz 28h 100 kHz 1 MHz 2 MHz 03h 333 kHz 1 MHz 2 MHz 0Ah 100 kHz  2010 Microchip Technology Inc. DS39635C-page 203

PIC18F6310/6410/8310/8410 17.4.7.1 Clock Arbitration SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and Clock arbitration occurs when the master, during any begins counting. This ensures that the SCL high time receive, transmit or Repeated Start/Stop condition, will always be at least one BRG rollover count in the deasserts the SCL pin (SCL allowed to float high). event that the clock is held low by an external device When the SCL pin is allowed to float high, the Baud (Figure17-18). Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the FIGURE 17-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX – 1 SCL deasserted but slave holds SCL allowed to transition high SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCL is sampled high, reload takes place and BRG starts its count BRG Reload DS39635C-page 204  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 17.4.8 I2C MASTER MODE START Note: If, at the beginning of the Start condition, CONDITION TIMING the SDA and SCL pins are already To initiate a Start condition, the user sets the Start sampled low, or if during the Start condi- Enable bit, SEN (SSPCON2<0>). If the SDA and SCL tion, the SCL line is sampled low before pins are sampled high, the Baud Rate Generator is the SDA line is driven low, a bus collision reloaded with the contents of SSPADD<6:0> and starts occurs, the Bus Collision Interrupt Flag, its count. If SCL and SDA are both sampled high when BCLIF, is set, the Start condition is aborted the Baud Rate Generator times out (TBRG), the SDA and the I2C module is reset into its Idle pin is driven low. The action of the SDA being driven state. low while SCL is high is the Start condition and causes 17.4.8.1 WCOL Status Flag the S bit (SSPSTAT<3>) to be set. Following this, the Baud Rate Generator is reloaded with the contents of If the user writes the SSPBUF when a Start sequence SSPADD<6:0> and resumes its count. When the Baud is in progress, the WCOL is set and the contents of the Rate Generator times out (TBRG), the SEN bit buffer are unchanged (the write doesn’t occur). (SSPCON2<0>) will be automatically cleared by hard- Note: Because queueing of events is not ware, the Baud Rate Generator is suspended, leaving allowed, writing to the lower 5 bits of the SDA line held low and the Start condition is SSPCON2 is disabled until the Start complete. condition is complete. FIGURE 17-19: FIRST START BIT TIMING Set S bit (SSPSTAT<3>) Write to SEN bit occurs here SDA = 1, At completion of Start bit, SCL = 1 hardware clears SEN bit and sets SSPIF bit TBRG TBRG Write to SSPBUF occurs here 1st bit 2nd bit SDA TBRG SCL TBRG S  2010 Microchip Technology Inc. DS39635C-page 205

PIC18F6310/6410/8310/8410 17.4.9 I2C MASTER MODE REPEATED Note1: If RSEN is programmed while any other START CONDITION TIMING event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit 2: A bus collision during the Repeated Start (SSPCON2<1>) is programmed high and the I2C logic condition occurs if: module is in the Idle state. When the RSEN bit is set, • SDA is sampled low when SCL goes the SCL pin is asserted low. When the SCL pin is sam- from low-to-high. pled low, the Baud Rate Generator is loaded with the • SCL goes low before SDA is contents of SSPADD<5:0> and begins counting. The asserted low. This may indicate that SDA pin is released (brought high) for one Baud Rate another master is attempting to Generator count (TBRG). When the Baud Rate Genera- transmit a data ‘1’. tor times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled Immediately following the SSPIF bit getting set, the user high, the Baud Rate Generator is reloaded with the may write the SSPBUF with the 7-bit address in 7-bit contents of SSPADD<6:0> and begins counting. SDA mode, or the default first address in 10-bit mode. After and SCL must be sampled high for one TBRG. This the first 8 bits are transmitted and an ACK is received, action is then followed by assertion of the SDA pin the user may then transmit an additional eight bits of (SDA = 0) for one TBRG while SCL is high. Following address (10-bit mode) or 8 bits of data (7-bit mode). this, the RSEN bit (SSPCON2<1>) will be automatically 17.4.9.1 WCOL Status Flag cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a If the user writes the SSPBUF when a Repeated Start Start condition is detected on the SDA and SCL pins, sequence is in progress, the WCOL is set and the con- the S bit (SSPSTAT<3>) will be set. The SSPIF bit will tents of the buffer are unchanged (the write doesn’t not be set until the Baud Rate Generator has timed out. occur). Note: Because queueing of events is not allowed, writing of the lower 5 bits of SSPCON2 is disabled until the Repeated Start condition is complete. FIGURE 17-20: REPEATED START CONDITION WAVEFORM Set S (SSPSTAT<3>) Write to SSPCON2 occurs here. SDA = 1, At completion of Start bit, SDA = 1, SCL = 1 hardware clears RSEN bit SCL (no change). and sets SSPIF TBRG TBRG TBRG SDA 1st bit Falling edge of ninth clock, Write to SSPBUF occurs here end of Xmit TBRG SCL TBRG Sr = Repeated Start DS39635C-page 206  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 17.4.10 I2C MASTER MODE TRANSMISSION 17.4.10.3 ACKSTAT Status Flag Transmission of a data byte, a 7-bit address or the In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is other half of a 10-bit address is accomplished by simply cleared when the slave has sent an Acknowledge writing a value to the SSPBUF register. This action will (ACK=0) and is set when the slave does not Acknowl- set the Buffer Full flag bit, BF, and allow the Baud Rate edge (ACK = 1). A slave sends an Acknowledge when Generator to begin counting and start the next trans- it has recognized its address (including a general call), mission. Each bit of address/data will be shifted out or when the slave has properly received its data. onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification 17.4.11 I2C MASTER MODE RECEPTION Parameter#106). SCL is held low for one Baud Rate Master mode reception is enabled by programming the Generator rollover count (TBRG). Data should be valid Receive Enable bit, RCEN (SSPCON2<3>). before SCL is released high (see data setup time spec- ification Parameter #107). When the SCL pin is Note: The MSSP module must be in an Idle released high, it is held that way for TBRG. The data on state before the RCEN bit is set or the the SDA pin must remain stable for that duration and RCEN bit will be disregarded. some hold time after the next falling edge of SCL. After The Baud Rate Generator begins counting and on each the eighth bit is shifted out (the falling edge of the eighth rollover, the state of the SCL pin changes (high-to-low/ clock), the BF flag is cleared and the master releases low-to-high) and data is shifted into the SSPSR. After SDA. This allows the slave device being addressed to the falling edge of the eighth clock, the receive enable respond with an ACK bit during the ninth bit time if an flag is automatically cleared, the contents of the address match occurred, or if data was received SSPSR are loaded into the SSPBUF, the BF flag bit is properly. The status of ACK is written into the ACKDT set, the SSPIF flag bit is set and the Baud Rate bit on the falling edge of the ninth clock. If the master Generator is suspended from counting, holding SCL receives an Acknowledge, the Acknowledge Status bit, low. The MSSP is now in Idle state awaiting the next ACKSTAT, is cleared. If not, the bit is set. After the ninth command. When the buffer is read by the CPU, the BF clock, the SSPIF bit is set and the master clock (Baud flag bit is automatically cleared. The user can then Rate Generator) is suspended until the next data byte send an Acknowledge bit at the end of reception by set- is loaded into the SSPBUF, leaving SCL low and SDA ting the Acknowledge Sequence Enable bit, ACKEN unchanged (Figure17-21). (SSPCON2<4>). After the write to the SSPBUF, each bit of address will be shifted out on the falling edge of SCL until all 17.4.11.1 BF Status Flag 7address bits and the R/W bit are completed. On the In receive operation, the BF bit is set when an address falling edge of the eighth clock, the master will deassert or data byte is loaded into SSPBUF from SSPSR. It is the SDA pin, allowing the slave to respond with an cleared when the SSPBUF register is read. Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address 17.4.11.2 SSPOV Status Flag was recognized by a slave. The status of the ACK bit is In receive operation, the SSPOV bit is set when 8 bits loaded into the ACKSTAT status bit (SSPCON2<6>). are received into the SSPSR and the BF flag bit is Following the falling edge of the ninth clock transmis- already set from a previous reception. sion of the address, the SSPIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until 17.4.11.3 WCOL Status Flag another write to the SSPBUF takes place, holding SCL If the user writes the SSPBUF when a receive is low and allowing SDA to float. already in progress (i.e., SSPSR is still shifting in a data 17.4.10.1 BF Status Flag byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur). In Transmit mode, the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out. 17.4.10.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur) after 2TCY after the SSPBUF write. If SSPBUF is rewritten within 2 TCY, the WCOL bit is set and SSPBUF is updated. This may result in a corrupted transfer. The user should verify that the WCOL flag is clear after each write to SSPBUF to ensure the transfer is correct.  2010 Microchip Technology Inc. DS39635C-page 207

PIC18F6310/6410/8310/8410 FIGURE 17-21: I2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) 1 e TAT in ON2 = softwar SC P n ACKSSP ared i K e C 9 Cl A > slave, clear ACKSTAT bit SSPCON2<6 Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1D0 2345678 Cleared in software service routinefrom MSSP interrupt SSPBUF is written in software From D7 1 w SPIF o S = 0 SCL held lwhile CPUsponds to CK re W = 0 A W 9 ware R/ A1 ss and R/ 78 d by hard ave A2 ddre 6 eare PCON2<0> SEN = 1dition begins SEN = 0 Transmit Address to Sl A7A6A5A4A3 SSPBUF written with 7-bit astart transmit 12345 Cleared in software SSPBUF written After Start condition, SEN cl Sn Write SStart co S <0>) T A T S P SDA SCL SSPIF BF (SS SEN PEN R/W DS39635C-page 208  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 17-22: I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) Write to SSPCON2<4>to start Acknowledge sequenceSDA = ACKDT (SSPCON2<5>) = 0 Set ACKEN, start Acknowledge sequenceACK from Masterer configured as a receiverSDA = ACKDT = SDA = ACKDT = 10ogramming SSPCON2<3> (RCEN = )1PEN bit = 1RCEN = , startRCEN cleared1RCEN clearedwritten herenext receiveautomaticallyautomatically Receiving Data from SlaveReceiving Data from SlaveACKD0D2D5D2D5D3D4D6D7D3D4D6D7D1D1D0ACK Bus masterACK is not sentterminatestransfer987561234123456789PSet SSPIF at endData shifted in on falling edge of CLKof receiveSet SSPIF interruptat end of Acknow-Set SSPIF interruptSet SSPIF interruptledge sequenceat end of receiveat end of Acknowledgesequence Set P bit Cleared in softwareCleared in softwareCleared in software(SSPSTAT<4>)Cleared insoftwareand SSPIF Last bit is shifted into SSPSR andcontents are unloaded into SSPBUF SSPOV is set becauseSSPBUF is still full Mastby pr ACK from Slave R/W = 1A1ACK 789 Write to SSPCON2<0>(SEN = )1Begin Start Condition SEN = 0Write to SSPBUF occurs hereStart XMIT Transmit Address to Slave A7A6A5A4A3A2SDA 123456SCLS SSPIF Cleared in softwareSDA = , SCL = 01while CPU responds to SSPIF BF (SSPSTAT<0>) SSPOV ACKEN  2010 Microchip Technology Inc. DS39635C-page 209

PIC18F6310/6410/8310/8410 17.4.12 ACKNOWLEDGE SEQUENCE 17.4.13 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDA pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge Sequence Enable bit, ACKEN bit, PEN (SSPCON2<2>). At the end of a receive/ (SSPCON2<4>). When this bit is set, the SCL pin is transmit, the SCL line is held low after the falling edge of pulled low and the contents of the Acknowledge data bit the ninth clock. When the PEN bit is set, the master will are presented on the SDA pin. If the user wishes to gen- assert the SDA line low. When the SDA line is sampled erate an Acknowledge, then the ACKDT bit should be low, the Baud Rate Generator is reloaded and counts cleared. If not, the user should set the ACKDT bit before down to ‘0’. When the Baud Rate Generator times out, starting an Acknowledge sequence. The Baud Rate the SCL pin will be brought high and one TBRG (Baud Generator then counts for one rollover period (TBRG) Rate Generator rollover count) later, the SDA pin will be and the SCL pin is deasserted (pulled high). When the deasserted. When the SDA pin is sampled high while SCL pin is sampled high (clock arbitration), the Baud SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG later, Rate Generator counts for TBRG. The SCL pin is then the PEN bit is cleared and the SSPIF bit is set pulled low. Following this, the ACKEN bit is automatically (Figure17-24). cleared, the Baud Rate Generator is turned off and the 17.4.13.1 WCOL Status Flag MSSP module then goes into Idle mode (Figure17-23). If the user writes the SSPBUF when a Stop sequence 17.4.12.1 WCOL Status Flag is in progress, then the WCOL bit is set and the If the user writes the SSPBUF when an Acknowledge contents of the buffer are unchanged (the write doesn’t sequence is in progress, then WCOL is set and the occur). contents of the buffer are unchanged (the write doesn’t occur). FIGURE 17-23: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSPCON2 ACKEN = 1, ACKDT = 0 TBRG TBRG SDA D0 ACK SCL 8 9 SSPIF Cleared in Set SSPIF at the end Cleared in software of receive software Set SSPIF at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 17-24: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2, SCL = 1 for TBRG, followed by SDA = 1 for TBRG set PEN after SDA sampled high. P bit (SSPSTAT<4>) is set. Falling edge of PEN bit (SSPCON2<2>) is cleared by 9th clock hardware and the SSPIF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. DS39635C-page 210  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 17.4.14 SLEEP OPERATION 17.4.17 MULTI -MASTER COMMUNICATION, While in Sleep mode, the I2C module can receive BUS COLLISION AND BUS ARBITRATION addresses or data and when an address match or complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra- from Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master 17.4.15 EFFECT OF A RESET outputs a ‘1’ on SDA, by letting SDA float high and A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCL pin floats current transfer. high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin = 0, 17.4.16 MULTI-MASTER MODE then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF and reset the In Multi-Master mode, the interrupt generation on the I2C port to its Idle state (Figure17-25). detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is MSSP module is disabled. Control of the I2C bus may cleared, the SDA and SCL lines are deasserted and the be taken when the P bit (SSPSTAT<4>) is set, or the SSPBUF can be written to. When the user services the bus is Idle, with both the S and P bits clear. When the bus collision Interrupt Service Routine and if the I2C bus is busy, enabling the MSSP interrupt will generate bus is free, the user can resume communication by the interrupt when the Stop condition occurs. asserting a Start condition. In multi-master operation, the SDA line must be If a Start, Repeated Start, Stop or Acknowledge condi- monitored for arbitration to see if the signal level is the tion was in progress when the bus collision occurred, the expected output level. This check is performed in condition is aborted, the SDA and SCL lines are deas- hardware with the result placed in the BCLIF bit. serted and the respective control bits in the SSPCON2 register are cleared. When the user services the bus The states where arbitration can be lost are: collision Interrupt Service Routine and if the I2C bus is • Address Transfer free, the user can resume communication by asserting a • Data Transfer Start condition. • A Start Condition The master will continue to monitor the SDA and SCL • A Repeated Start Condition pins. If a Stop condition occurs, the SSPIF bit will be set. • An Acknowledge Condition A write to the SSPBUF will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the deter- mination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 17-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Sample SDA. While SCL is high, Data changes SDA line pulled low data doesn’t match what is driven while SCL = 0 by another source by the master. Bus collision has occurred. SDA released by master SDA SCL Set bus collision interrupt (BCLIF) BCLIF  2010 Microchip Technology Inc. DS39635C-page 211

PIC18F6310/6410/8310/8410 17.4.17.1 Bus Collision During a Start If the SDA pin is sampled low during this count, the Condition BRG is reset and the SDA line is asserted early (Figure17-28). If, however, a ‘1’ is sampled on the SDA During a Start condition, a bus collision occurs if: pin, the SDA pin is asserted low at the end of the BRG a) SDA or SCL are sampled low at the beginning of count. The Baud Rate Generator is then reloaded and the Start condition (Figure17-26). counts down to ‘0’ and during this time, if the SCL pins b) SCL is sampled low before SDA is asserted low are sampled as ‘0’, a bus collision does not occur. At (Figure17-27). the end of the BRG count, the SCL pin is asserted low. During a Start condition, both the SDA and the SCL Note: The reason that bus collision is not a factor pins are monitored. during a Start condition is that no two bus masters can assert a Start condition at the If the SDA pin is already low, or the SCL pin is already exact same time. Therefore, one master low, then all of the following occur: will always assert SDA before the other. • the Start condition is aborted, This condition does not cause a bus • the BCLIF flag is set and collision because the two masters must be • the MSSP module is reset to its Idle state allowed to arbitrate the first address follow- (Figure17-26). ing the Start condition. If the address is the The Start condition begins with the SDA and SCL pins same, arbitration must be allowed to deasserted. When the SDA pin is sampled high, the continue into the data portion, Repeated Baud Rate Generator is loaded from SSPADD<6:0> Start or Stop conditions. and counts down to ‘0’. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 17-26: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDA = 1, SCL = 1 MSSP module reset into Idle state. SEN SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because BCLIF SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software S SSPIF SSPIF and BCLIF are cleared in software DS39635C-page 212  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 17-27: BUS COLLISION DURING A START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start SCL sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared in software S ‘0’ ‘0’ SSPIF ‘0’ ‘0’ FIGURE 17-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Set SSPIF Less than TBRG TBRG SDA SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time-out SEN Set SEN, enable START sequence if SDA = 1, SCL = 1 BCLIF ‘0’ S SSPIF SDA = 0, SCL = 1, Interrupts cleared set SSPIF in software  2010 Microchip Technology Inc. DS39635C-page 213

PIC18F6310/6410/8310/8410 17.4.17.2 Bus Collision During a Repeated If SDA is low, a bus collision has occurred (i.e., another Start Condition master is attempting to transmit a data ‘0’, Figure17-29). If SDA is sampled high, the BRG is reloaded and begins During a Repeated Start condition, a bus collision counting. If SDA goes from high-to-low before the BRG occurs if: times out, no bus collision occurs because no two a) A low level is sampled on SDA when SCL goes masters can assert SDA at exactly the same time. from low level to high level. If SCL goes from high-to-low before the BRG times out b) SCL goes low before SDA is asserted low, and SDA has not already been asserted, a bus collision indicating that another master is attempting to occurs. In this case, another master is attempting to transmit a data ‘1’. transmit a data ‘1’ during the Repeated Start condition When the user deasserts SDA and the pin is allowed to (see Figure17-30). float high, the BRG is loaded with SSPADD<6:0> and If, at the end of the BRG time-out, both SCL and SDA counts down to ‘0’. The SCL pin is then deasserted and are still high, the SDA pin is driven low and the BRG is when sampled high, the SDA pin is sampled. reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. FIGURE 17-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software S ‘0’ SSPIF ‘0’ FIGURE 17-30: BUS COLLISION DURING A REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, BCLIF set BCLIF. Release SDA and SCL. Interrupt cleared in software RSEN S ‘0’ SSPIF DS39635C-page 214  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 17.4.17.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low. Condition When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with SSPADD<6:0> a) After the SDA pin has been deasserted and and counts down to ‘0’. After the BRG times out, SDA allowed to float high, SDA is sampled low after is sampled. If SDA is sampled low, a bus collision has the BRG has timed out. occurred. This is due to another master attempting to b) After the SCL pin is deasserted, SCL is sampled drive a data ‘0’ (Figure17-31). If the SCL pin is low before SDA goes high. sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure17-32). FIGURE 17-31: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF SDA SDA asserted low SCL PEN BCLIF P ‘0’ SSPIF ‘0’ FIGURE 17-32: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, Assert SDA set BCLIF SCL PEN BCLIF P ‘0’ SSPIF ‘0’  2010 Microchip Technology Inc. DS39635C-page 215

PIC18F6310/6410/8310/8410 TABLE 17-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 65 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 65 TRISC PORTC Data Direction Register 66 SSPBUF Master Synchronous Serial Port Receive Buffer/Transmit Register 64 SSPADD Master Synchronous Serial Port Receive Buffer/Transmit Register 64 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 64 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 64 SSPSTAT SMP CKE D/A P S R/W UA BF 64 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in I2C mode. DS39635C-page 216  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 18.0 ENHANCED UNIVERSAL The EUSART can be configured in the following SYNCHRONOUS modes: ASYNCHRONOUS RECEIVER • Asynchronous (full-duplex) with: TRANSMITTER (EUSART) - Auto-wake-up on character reception - Auto-baud calibration PIC18F6310/6410/8310/8410 devices have three - 12-bit Break character transmission serial I/O modules: the MSSP module, discussed in the • Synchronous – Master (half-duplex) with previous chapter and two Universal Synchronous selectable clock polarity Asynchronous Receiver Transmitter (USART) mod- • Synchronous – Slave (half-duplex) with selectable ules. (Generically, the USART is also known as a Serial clock polarity Communications Interface or SCI.) The USART can be configured as a full-duplex asynchronous system that The pins of the Enhanced USART are multiplexed with can communicate with peripheral devices, such as PORTC. In order to configure TX1/CK1 and RX1/DT1 CRT terminals and personal computers. It can also be as a USART: configured as a half-duplex synchronous system that • SPEN bit (RCSTA1<7>) must be set (= 1) can communicate with peripheral devices, such as A/D • TRISC<7> bit must be set (= 1) or D/A integrated circuits, serial EEPROMs, etc. • TRISC<6> bit must be set (= 1) There are two distinct implementations of the USART module in these devices: the Enhanced USART Note: The USART control will automatically (EUSART), discussed here and the Addressable reconfigure the pin from input to output as USART (AUSART), discussed in the next chapter. For needed. this device family, USART1 always refers to the The operation of the Enhanced USART module is EUSART, while USART2 is always the AUSART. controlled through three registers: The EUSART and AUSART modules implement the • Transmit Status and Control Register 1 (TXSTA1) same core features for serial communications; their • Receive Status and Control Register 1 (RCSTA1) basic operation is essentially the same. The EUSART • Baud Rate Control Register 1 (BAUDCON1) module provides additional features, including auto- matic baud rate detection and calibration, automatic The registers are described in Register18-1, wake-up on Sync Break reception and 12-bit Break Register18-2 and Register18-3. character transmit. These features make it ideally suited for use in Local Interconnect Network bus (LIN/J2602 bus) systems.  2010 Microchip Technology Inc. DS39635C-page 217

PIC18F6310/6410/8310/8410 REGISTER 18-1: TXSTA1: EUSART1 TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-Bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit is enabled 0 = Transmit is disabled bit 4 SYNC: AUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care. bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR is empty 0 = TSR is full bit 0 TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS39635C-page 218  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 REGISTER 18-2: RCSTA1: EUSART1 RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port is enabled 0 = Serial port is disabled bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care. Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave: Don’t care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-Bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> are set 0 = Disables address detection, all bytes are received and ninth bit can be used as a parity bit Asynchronous mode 8-Bit (RX9 = 0): Don’t care. bit 2 FERR: Framing Error bit 1 = Framing error (can be cleared by reading RCREG1 register and receiving next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit, CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data bit This can be address/data bit or a parity bit and must be calculated by user firmware.  2010 Microchip Technology Inc. DS39635C-page 219

PIC18F6310/6410/8310/8410 REGISTER 18-3: BAUDCON1: BAUD RATE CONTROL REGISTER 1 R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurred bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active bit 5 RXDTP: Received Data Polarity Select bit Asynchronous mode: 1 = Receive data (RXx) is inverted (active-low) 0 = Receive data (RXx) is not inverted (active-high) Synchronous mode: No affect. bit 4 TXCKP: Clock and Data Polarity Select bit Asynchronous mode: 1 = Idle state for transmit (TXx) is a low level 0 = Idle state for transmit (TXx) is a high level Synchronous mode: 1 = Idle state for clock (CKx) is a high level 0 = Idle state for clock (CKx) is a low level bit 3 BRG16: 16-Bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator – SPBRGH1 and SPBRG1 0 = 8-bit Baud Rate Generator – SPBRG1 only (Compatible mode); SPBRGH1 value ignored bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RXx pin – interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RXx pin not monitored or rising edge detected Synchronous mode: Unused in this mode. bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h); cleared in hardware upon completion. 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. DS39635C-page 220  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 18.1 EUSART Baud Rate Generator Writing a new value to the SPBRGH1:SPBRG1 (BRG) registers causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer The BRG is a dedicated, 8-bit or 16-bit generator that overflow before outputting the new baud rate. supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates Note: The BRG value of ‘0’ is not supported. in 8-bit mode; setting the BRG16 bit (BAUDCON1<3>) selects 16-bit mode. 18.1.1 OPERATION IN POWER-MANAGED The SPBRGH1:SPBRG1 register pair controls the period MODES of a free running timer. In Asynchronous mode, bits, The device clock is used to generate the desired baud BRGH (TXSTA1<2>) and BRG16 (BAUDCON1<3>), rate. When one of the power-managed modes is also control the baud rate. In Synchronous mode, BRGH entered, the new clock source may be operating at a is ignored. Table18-1 shows the formula for computation different frequency. This may require an adjustment to of the baud rate for different EUSART modes that only the value in the SPBRG1 register pair. apply in Master mode (internally generated clock). Given the desired baud rate and FOSC, the nearest 18.1.2 SAMPLING integer value for the SPBRGH1:SPBRG1 registers can be calculated using the formulas in Table18-1. From The data on the RXx pin is sampled three times by a this, the error in baud rate can be determined. An majority detect circuit to determine if a high or a low example calculation is shown in Example18-1. Typical level is present at the RXx pin when SYNC is clear or baud rates and error values for the various when both BRG16 and BRGH are not set. The data on Asynchronous modes are shown in Table18-2. It may the RXx pin is sampled once when SYNC is set or be advantageous to use the high baud rate (BRGH = 1) when BRGH16 and BRGH are both set. or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. TABLE 18-1: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n + 1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n + 1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n + 1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = Value of SPBRGH1:SPBRG1 register pair EXAMPLE 18-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGH1:SPBRG1] + 1)) Solving for SPBRGH1:SPBRG1: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.16% TABLE 18-2: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 65 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 65 BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 66 SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 66 SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 65 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.  2010 Microchip Technology Inc. DS39635C-page 221

PIC18F6310/6410/8310/8410 TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — — 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — — 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51 1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12 2.4 2.404 0.16 25 2.403 -0.16 12 — — — 9.6 8.929 -6.99 6 — — — — — — 19.2 20.833 8.51 2 — — — — — — 57.6 62.500 8.51 0 — — — — — — 115.2 62.500 -45.75 0 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — — — — — — — — — — 2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — DS39635C-page 222  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1665 1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1.201 -0.16 415 2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2.403 -0.16 207 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % % Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 0.300 -0.01 6665 1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1.200 -0.04 1665 2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2.400 -0.04 832 9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9.615 -0.16 207 19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19.230 -0.16 103 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57.142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117.647 -2.12 16 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.01 3332 0.300 -0.04 1665 0.300 -0.04 832 1.2 1.200 0.04 832 1.201 -0.16 415 1.201 -0.16 207 2.4 2.404 0.16 415 2.403 -0.16 207 2.403 -0.16 103 9.6 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25 19.2 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12 57.6 58.824 2.12 16 55.555 3.55 8 — — — 115.2 111.111 -3.55 8 — — — — — —  2010 Microchip Technology Inc. DS39635C-page 223

PIC18F6310/6410/8310/8410 18.1.3 AUTO-BAUD RATE DETECT While the ABD sequence takes place, the EUSART state machine is held in Idle. The RC1IF interrupt is set The Enhanced USART module supports the automatic once the fifth rising edge on RX1 is detected. The value detection and calibration of baud rate. This feature is in the RCREG1 needs to be read to clear the RC1IF active only in Asynchronous mode and while the WUE interrupt. The contents of RCREG1 should be bit is clear. discarded. The automatic baud rate measurement sequence Note1: If the WUE bit is set with the ABDEN bit, (Figure18-1) begins whenever a Start bit is received and the ABDEN bit is set. The calculation is Auto-Baud Rate Detection will occur on the byte following the Break character. self-averaging. In the Auto-Baud Rate Detect (ABD) mode, the clock to 2: It is up to the user to determine that the the BRG is reversed. Rather than the BRG clocking the incoming character baud rate is within the range of the selected BRG clock source. incoming RX1 signal, the RX1 signal is timing the BRG. In ABD mode, the internal Baud Rate Generator is Some combinations of oscillator frequency and EUSART baud rates are not possible used as a counter to time the bit period of the incoming serial byte stream. due to bit error rates. Overall system timing and communication baud rates must be Once the ABDEN bit is set, the state machine will clear taken into consideration when using the the BRG and look for a Start bit. The Auto-Baud Rate Auto-Baud Rate Detection feature. Detect must receive a byte with the value, 55h (ASCII “U”, which is also the LIN/J2602 bus Sync character), 3: To maximize baud rate range, it is recom- in order to calculate the proper bit rate. The measure- mended to set the BRG16 bit if the ment is taken over both a low and a high bit time in auto-baud feature is used. order to minimize any effects caused by asymmetry of the incoming signal. After a Start bit, the SPBRG1 TABLE 18-4: BRG COUNTER CLOCK begins counting up, using the preselected clock source RATES on the first rising edge of RX1. After eight bits on the RX1 pin or the fifth rising edge, an accumulated value BRG16 BRGH BRG Counter Clock totalling the proper BRG period is left in the SPBRGH1:SPBRG1 register pair. Once the 5th edge is 0 0 FOSC/512 seen (this should correspond to the Stop bit), the 0 1 FOSC/128 ABDEN bit is automatically cleared. 1 0 FOSC/128 If a rollover of the BRG occurs (an overflow from FFFFh 1 1 FOSC/32 to 0000h), the event is trapped by the ABDOVF status bit (BAUDCON1<7>). It is set in hardware by BRG rollovers 18.1.3.1 ABD and EUSART Transmission and can be set or cleared by the user in software. ABD mode remains active after rollover events and the Since the BRG clock is reversed during ABD acquisi- ABDEN bit remains set (Figure18-2). tion, the EUSART transmitter cannot be used during While calibrating the baud rate period, the BRG ABD. This means that whenever the ABDEN bit is set, registers are clocked at 1/8th the preconfigured clock TXREG1 cannot be written to. Users should also rate. Note that the BRG clock can be configured by the ensure that ABDEN does not become set during a BRG16 and BRGH bits. The BRG16 bit must be set to transmit sequence. Failing to do this may result in use both SPBRG1 and SPBRGH1 as a 16-bit counter. unpredictable EUSART operation. This allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the SPBRGH1 register. Refer to Table18-4 for counter clock rates to the BRG. DS39635C-page 224  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 18-1: AUTOMATIC BAUD RATE CALCULATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RX1 Pin Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Stop Bit BRG Clock Set by User Auto-Cleared ABDEN bit RC1IF bit (Interrupt) Read RCREG1 SPBRG1 XXXXh 1Ch SPBRGH1 XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE=0. FIGURE 18-2: BRG OVERFLOW SEQUENCE BRG Clock ABDEN bit RX1 Pin Start Bit 0 ABDOVF bit FFFFh BRG Value XXXXh 0000h 0000h  2010 Microchip Technology Inc. DS39635C-page 225

PIC18F6310/6410/8310/8410 18.2 EUSART Asynchronous Mode interrupt can be enabled or disabled by setting or clear- ing the interrupt enable bit, TX1IE (PIE1<4>). TX1IF The Asynchronous mode of operation is selected by will be set regardless of the state of TX1IE; it cannot be clearing the SYNC bit (TXSTA1<4>). In this mode, the cleared in software. TX1IF is also not cleared immedi- EUSART uses standard Non-Return-to-Zero (NRZ) for- ately upon loading TXREG1, but becomes valid in the mat (one Start bit, eight or nine data bits and one Stop bit). second instruction cycle following the load instruction. The most common data format is 8 bits. An on-chip dedi- Polling TX1IF immediately following a load of TXREG1 cated 8-bit/16-bit Baud Rate Generator can be used to will return invalid results. derive standard baud rate frequencies from the oscillator. While TX1IF indicates the status of the TXREG1 regis- The EUSART transmits and receives the LSb first. The ter, another bit, TRMT (TXSTA1<1>), shows the status EUSART’s transmitter and receiver are functionally of the TSR register. TRMT is a read-only bit which is set independent, but use the same data format and baud when the TSR register is empty. No interrupt logic is tied rate. The Baud Rate Generator produces a clock, either to this bit so the user has to poll this bit in order to deter- x16 or x64 of the bit shift rate depending on the BRGH mine if the TSR register is empty. The TXCKP bit and BRG16 bits (TXSTA1<2> and BAUDCON1<3>). (BAUDCON<4>) allows the TX signal to be inverted Parity is not supported by the hardware but can be (polarity reversed). Devices that buffer signals from TTL implemented in software and stored as the 9th data bit. to RS-232 levels also invert the signal (when TTL = 1, The TXCKP (BAUDCON<4>) and RXDTP RS-232 = negative). Inverting the polarity of the TXx pin (BAUDCON<5>) bits allow the TX and RX signals to be data by setting the TXCKP bit allows for use of circuits inverted (polarity reversed). Devices that buffer signals that provide buffering without inverting the signal. between TTL and RS-232 levels also invert the signal. Setting the TXCKP and RXDTP bits allows for the use of Note1: The TSR register is not mapped in data circuits that provide buffering without inverting the signal. memory so it is not available to the user. When operating in Asynchronous mode, the EUSART 2: Flag bit, TX1IF, is set when enable bit, module consists of the following important elements: TXEN, is set. • Baud Rate Generator To set up an Asynchronous Transmission: • Sampling Circuit 1. Initialize the SPBRGH:SPBRG registers for the • Asynchronous Transmitter appropriate baud rate. Set or clear the BRGH • Asynchronous Receiver and BRG16 bits, as required, to achieve the • Auto-Wake-up on Sync Break Character desired baud rate. • 12-Bit Break Character Transmit 2. Enable the asynchronous serial port by clearing • Auto-Baud Rate Detection bit, SYNC, and setting bit, SPEN. 18.2.1 EUSART ASYNCHRONOUS 3. If the signal from the TXx pin is to be inverted, set the TXCKP bit. TRANSMITTER 4. If interrupts are desired, set enable bit, TXIE. The EUSART transmitter block diagram is shown in 5. If 9-bit transmission is desired, set transmit bit, Figure18-3. The heart of the transmitter is the Transmit TX9. Can be used as an address/data bit. (Serial) Shift register (TSR). The Shift register obtains its data from the Read/Write Transmit Buffer register, 6. Enable the transmission by setting bit, TXEN, TXREG1. The TXREG1 register is loaded with data in which will also set bit, TXIF. software. The TSR register is not loaded until the Stop 7. If 9-bit transmission is selected, the ninth bit bit has been transmitted from the previous load. As should be loaded in bit, TX9D. soon as the Stop bit is transmitted, the TSR is loaded 8. Load data to the TXREG register (starts with new data from the TXREG1 register (if available). transmission). Once the TXREG1 register transfers the data to the 9. If using interrupts, ensure that the GIE and PEIE TSR register (occurs in one TCY), the TXREG1 register bits in the INTCON register (INTCON<7:6>) are is empty and the TX1IF flag bit (PIR1<4>) is set. This set. DS39635C-page 226  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 18-3: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TX1IF TXREG1 Register TX1IE 8 MSb LSb (8)  0 Pin Buffer and Control TSR Register TX1 pin Interrupt TXEN Baud Rate CLK TRMT SPEN BRG16 SPBRGH1 SPBRG1 TX9 Baud Rate Generator TX9D FIGURE 18-4: ASYNCHRONOUS TRANSMISSION Write to TXREG1 Word 1 BRG Output (Shift Clock) TX1 (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TX1IF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) FIGURE 18-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG1 Word 1 Word 2 BRG Output (Shift Clock) TX1 (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TX1IF bit 1 TCY Word 1 Word 2 (Interrupt Reg. Flag) 1 TCY Word 1 Word 2 TRMT bit Transmit Shift Reg. Transmit Shift Reg. (Transmit Shift Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions.  2010 Microchip Technology Inc. DS39635C-page 227

PIC18F6310/6410/8310/8410 TABLE 18-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 65 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 65 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 65 TXREG1 EUSART1 Transmit Register 65 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 65 BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 66 SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 66 SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 65 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. DS39635C-page 228  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 18.2.2 EUSART ASYNCHRONOUS 18.2.3 SETTING UP 9-BIT MODE WITH RECEIVER ADDRESS DETECT The receiver block diagram is shown in Figure18-6. This mode would typically be used in RS-485 systems. The data is received on the RX1 pin and drives the data To set up an Asynchronous Reception with Address recovery block. The data recovery block is actually a Detect Enable: high-speed shifter operating at x16 times the baud rate, 1. Initialize the SPBRGH:SPBRG registers for the whereas the main receive serial shifter operates at the appropriate baud rate. Set or clear the BRGH bit rate or at FOSC. This mode would typically be used and BRG16 bits, as required, to achieve the in RS-232 systems. desired baud rate. The RXDTP bit (BAUDCON<5>) allows the RX signal 2. Enable the asynchronous serial port by clearing to be inverted (polarity reversed). Devices that buffer the SYNC bit and setting the SPEN bit. signals from RS-232 to TTL levels also perform an 3. If the signal at the RXx pin is to be inverted, set inversion of the signal (when RS-232 = positive, the RXDTP bit. If the signal from the TXx pin is TTL=0). Inverting the polarity of the RXx pin data by to be inverted, set the TXCKP bit. setting the RXDTP bit allows for the use of circuits that 4. If interrupts are required, set the RCEN bit and provide buffering without inverting the signal. select the desired priority level with the RCIP bit. To set up an Asynchronous Reception: 5. Set the RX9 bit to enable 9-bit reception. 1. Initialize the SPBRGH:SPBRG registers for the 6. Set the ADDEN bit to enable address detect. appropriate baud rate. Set or clear the BRGH 7. Enable reception by setting the CREN bit. and BRG16 bits, as required, to achieve the 8. The RCIF bit will be set when reception is com- desired baud rate. plete. The interrupt will be Acknowledged if the 2. Enable the asynchronous serial port by clearing RCIE and GIE bits are set. bit, SYNC, and setting bit, SPEN. 9. Read the RCSTA register to determine if any 3. If the signal at the RXx pin is to be inverted, set error occurred during reception, as well as read the RXDTP bit. bit 9 of data (if applicable). 4. If interrupts are desired, set enable bit, RCIE. 10. Read RCREG to determine if the device is being 5. If 9-bit reception is desired, set bit, RX9. addressed. 6. Enable the reception by setting bit, CREN. 11. If any error occurred, clear the CREN bit. 7. Flag bit, RCIF, will be set when reception is com- 12. If the device has been addressed, clear the plete and an interrupt will be generated if enable ADDEN bit to allow all received data into the bit, RCIE, was set. receive buffer and interrupt the CPU. 8. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing enable bit, CREN. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.  2010 Microchip Technology Inc. DS39635C-page 229

PIC18F6310/6410/8310/8410 FIGURE 18-6: EUSART RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK BRG16 SPBRGH1 SPBRG1  o6r4 MSb RSR Register LSb  16 or Stop (8) 7  1 0 Start Baud Rate Generator  4 RX9 Pin Buffer Data and Control Recovery RX1 RX9D RCREG1 Register FIFO SPEN 8 Interrupt RC1IF Data Bus RC1IE FIGURE 18-7: ASYNCHRONOUS RECEPTION RX1 (pin) Start Start Start bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 RCREG1 RCREG1 RCREG1 Read Rcv Buffer Reg RC1IF (Interrupt Flag) OERR bit CREN bit Note: This timing diagram shows three words appearing on the RX1 input. The RCREG1 (Receive Buffer) is read after the third word causing the OERR (Overrun) bit to be set. DS39635C-page 230  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 18-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 65 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 65 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 65 RCREG1 EUSART1 Receive Register 65 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 65 BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 66 SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 66 SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 65 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.  2010 Microchip Technology Inc. DS39635C-page 231

PIC18F6310/6410/8310/8410 18.2.4 AUTO-WAKE-UP ON SYNC BREAK Oscillator start-up time must also be considered, CHARACTER especially in applications using oscillators with longer start-up intervals (i.e., XT or HS mode). The Sync During Sleep mode, all clocks to the EUSART are Break (or Wake-up Signal) character must be of suffi- suspended. Because of this, the Baud Rate Generator cient length and be followed by a sufficient interval to is inactive and a proper byte reception cannot be per- allow enough time for the selected oscillator to start formed. The auto-wake-up feature allows the controller and provide proper initialization of the EUSART. to wake-up, due to activity on the RX1/DT1 line while the EUSART is operating in Asynchronous mode. 18.2.4.2 Special Considerations Using The auto-wake-up feature is enabled by setting the the WUE Bit WUE bit (BAUDCON<1>). Once set, the typical receive The timing of WUE and RC1IF events may cause some sequence on RX1/DT1 is disabled and the EUSART confusion when it comes to determining the validity of remains in an Idle state, monitoring for a wake-up event received data. As noted, setting the WUE bit places the independent of the CPU mode. A wake-up event EUSART in an Idle mode. The wake-up event causes consists of a high-to-low transition on the RX1/DT1 a receive interrupt by setting the RC1IF bit. The WUE line. (This coincides with the start of a Sync Break or a bit is cleared after this when a rising edge is seen on Wake-up Signal character for the LIN/J2602 protocol.) RX1/DT1. The interrupt condition is then cleared by Following a wake-up event, the module generates an reading the RCREG1 register. Ordinarily, the data in RC1IF interrupt. The interrupt is generated synchro- RCREG1 will be dummy data and should be discarded. nously to the Q clocks in normal operating modes The fact that the WUE bit has been cleared (or is still (Figure18-8) and asynchronously, if the device is in set) and the RC1IF flag is set should not be used as an Sleep mode (Figure18-9). The interrupt condition is indicator of the integrity of the data in RCREG1. Users cleared by reading the RCREG1 register. should consider implementing a parallel method in The WUE bit is automatically cleared once a firmware to verify received data integrity. low-to-high transition is observed on the RX1 line fol- To assure that no actual data is lost, check the RCIDL lowing the wake-up event. At this point, the EUSART bit to verify that a receive operation is not in process. If module is in Idle mode and returns to normal operation. a receive operation is not occurring, the WUE bit may This signals to the user that the Sync Break event is then be set just prior to entering the Sleep mode. over. 18.2.4.1 Special Considerations Using Auto-Wake-up Since auto-wake-up functions by sensing rising edge transitions on RX1/DT1, information with any state changes before the Stop bit may signal a false End-of-Character (EOC) and cause data or framing errors. Therefore, to work properly, the initial character in the transmission must be all ‘0’s. This can be 00h (8bits) for standard RS-232 devices, or 000h (12bits) for the LIN/J2602 bus. DS39635C-page 232  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 18-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit RX1/DT1 Line RC1IF Cleared due to user read of RCREG1 Note: The EUSART remains in Idle while the WUE bit is set. FIGURE 18-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit(2) RX1/DT1 Line Note 1 RC1IF SLEEP Command Executed Sleep Ends Cleared due to user read of RCREG1 Note1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set.  2010 Microchip Technology Inc. DS39635C-page 233

PIC18F6310/6410/8310/8410 18.2.5 BREAK CHARACTER SEQUENCE 3. Load the TXREG1 with a dummy character to initiate transmission (the value is ignored). The Enhanced USART module has the capability of sending the special Break character sequences that are 4. Write ‘55h’ to TXREG1 to load the Sync required by the LIN/J2602 bus standard. The Break character into the transmit FIFO buffer. character transmit consists of a Start bit, followed by 5. After the Break has been sent, the SENDB bit is twelve ‘0’ bits and a Stop bit. The Frame Break character reset by hardware. The Sync character now is sent whenever the SENDB and TXEN bits transmits in the preconfigured mode. (TXSTA<3> and TXSTA<5>) are set while the Transmit When the TXREG1 becomes empty, as indicated by the Shift register is loaded with data. Note that the value of TX1IF bit, the next data byte can be written to TXREG1. data written to TXREG1 will be ignored and all ‘0’s will be transmitted. 18.2.6 RECEIVING A BREAK CHARACTER The SENDB bit is automatically reset by hardware after The Enhanced USART module can receive a Break the corresponding Stop bit is sent. This allows the user character in two ways. to preload the transmit FIFO with the next transmit byte The first method forces configuration of the baud rate following the Break character (typically, the Sync at a frequency of 9/13 the typical speed. This allows for character in the LIN/J2602 specification). the Stop bit transition to be at the correct sampling Note that the data value written to the TXREG1 for the location (13 bits for Break versus Start bit and 8 data Break character is ignored. The write simply serves the bits for typical data). purpose of initiating the proper sequence. The second method uses the auto-wake-up feature The TRMT bit indicates when the transmit operation is described in Section18.2.4 “Auto-Wake-up on Sync active or Idle, just as it does during normal transmis- Break Character”. By enabling this feature, the sion. See Figure18-10 for the timing of the Break EUSART will sample the next two transitions on character sequence. RX1/DT1, cause an RC1IF interrupt and receive the next data byte followed by another interrupt. 18.2.5.1 Break and Sync Transmit Sequence Note that following a Break character, the user will The following sequence will send a message frame typically want to enable the Auto-Baud Rate Detect header made up of a Break, followed by an Auto-Baud feature. For both methods, the user can set the ABD bit Sync byte. This sequence is typical of a LIN/J2602 bus once the TX1IF interrupt is observed. master. 1. Configure the EUSART for the desired mode. 2. Set the TXEN and SENDB bits to set up the Break character. FIGURE 18-10: SEND BREAK CHARACTER SEQUENCE Write to TXREG1 Dummy Write BRG Output (Shift Clock) TX1 (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TX1IF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB sampled here Auto-Cleared SENDB (Transmit Shift Reg. Empty Flag) DS39635C-page 234  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 18.3 EUSART Synchronous Once the TXREG1 register transfers the data to the Master Mode TSR register (occurs in one TCYCLE), the TXREG1 is empty and the TX1IF flag bit (PIR1<4>) is set. The The Synchronous Master mode is entered by setting interrupt can be enabled or disabled by setting or clear- the CSRC bit (TXSTA<7>). In this mode, the data is ing the interrupt enable bit, TX1IE (PIE1<4>). TX1IF is transmitted in a half-duplex manner (i.e., transmission set regardless of the state of enable bit, TX1IE; it and reception do not occur at the same time). When cannot be cleared in software. It will reset only when transmitting data, the reception is inhibited and vice new data is loaded into the TXREG1 register. versa. Synchronous mode is entered by setting bit, While flag bit, TX1IF, indicates the status of the TXREG1 SYNC (TXSTA<4>). In addition, enable bit, SPEN register, another bit, TRMT (TXSTA<1>), shows the (RCSTA1<7>), is set in order to configure the TX1 and status of the TSR register. TRMT is a read-only bit which RX1 pins to CK1 (clock) and DT1 (data) lines, is set when the TSR is empty. No interrupt logic is tied to respectively. this bit so the user has to poll this bit in order to deter- The Master mode indicates that the processor trans- mine if the TSR register is empty. The TSR is not mits the master clock on the CK1 line. Clock polarity mapped in data memory so it is not available to the user. (CK1) is selected with the TXCKP bit (BAUDCON<4>). To set up a Synchronous Master Transmission: Setting TXCKP sets the Idle state on CK1 as high, while clearing the bit sets the Idle state as low. 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRG16 18.3.1 EUSART SYNCHRONOUS MASTER bit, as required, to achieve the desired baud TRANSMISSION rate. 2. Enable the synchronous master serial port by The EUSART transmitter block diagram is shown in setting bits, SYNC, SPEN and CSRC. Figure18-3. The heart of the transmitter is the Transmit (Serial) Shift register (TSR). The Shift register obtains 3. If the signal from the CKx pin is to be inverted, its data from the Read/Write Transmit Buffer register, set the TXCKP bit. TXREG1. The TXREG1 register is loaded with data in 4. If interrupts are desired, set enable bit, TXIE. software. The TSR register is not loaded until the last 5. If 9-bit transmission is desired, set bit, TX9. bit has been transmitted from the previous load. As 6. Enable the transmission by setting bit, TXEN. soon as the last bit is transmitted, the TSR is loaded 7. If 9-bit transmission is selected, the ninth bit with new data from the TXREG1 register (if available). should be loaded in bit, TX9D. 8. Start transmission by loading data to the TXREG register. 9. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 18-11: SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 RC6/TX1/CK1 pin (TXCKP = 0) RC6/TX1/CK1 pin (TXCKP = 1) Write to TXREG1 Reg Write Word 1 Write Word 2 TX1IF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ ‘1’ Note: Sync Master mode, SPBRG1 = 0, continuous transmission of two 8-bit words.  2010 Microchip Technology Inc. DS39635C-page 235

PIC18F6310/6410/8310/8410 FIGURE 18-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX1/CK1 pin Write to TXREG1 Reg TX1IF bit TRMT bit TXEN bit TABLE 18-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 65 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 65 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 65 TXREG1 EUSART1 Transmit Register 65 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 65 BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 66 SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 66 SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 65 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. DS39635C-page 236  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 18.3.2 EUSART SYNCHRONOUS 4. If the signal from the CKx pin is to be inverted, MASTER RECEPTION set the TXCKP bit. 5. If interrupts are desired, set enable bit, RCIE. Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, 6. If 9-bit reception is desired, set bit, RX9. SREN (RCSTA1<5>), or the Continuous Receive 7. If a single reception is required, set bit, SREN. Enable bit, CREN (RCSTA1<4>). Data is sampled on For continuous reception, set bit, CREN. the RX1 pin on the falling edge of the clock. 8. Interrupt flag bit, RCIF, will be set when reception If enable bit, SREN, is set, only a single word is is complete and an interrupt will be generated if received. If enable bit, CREN, is set, the reception is the enable bit, RCIE, was set. continuous until CREN is cleared. If both bits are set, 9. Read the RCSTA register to get the 9th bit (if then CREN takes precedence. enabled) and determine if any error occurred To set up a Synchronous Master Reception: during reception. 1. Initialize the SPBRGH:SPBRG registers for the 10. Read the 8-bit received data by reading the appropriate baud rate. Set or clear the BRG16 RCREG register. bit, as required, to achieve the desired baud 11. If any error occurred, clear the error by clearing rate. bit, CREN. 2. Enable the synchronous master serial port by 12. If using interrupts, ensure that the GIE and PEIE setting bits, SYNC, SPEN and CSRC. bits in the INTCON register (INTCON<7:6>) are 3. Ensure bits, CREN and SREN, are clear. set. FIGURE 18-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RC6/TX1/CK1 pin (TXCKP = 0) RC6/TX1/CK1 pin (TXCKP = 1) Write to SREN bit SREN bit CREN bit ‘0’ ‘0’ RC1IF bit (Interrupt) Read RCREG1 Note: Timing diagram demonstrates Sync Master mode with SREN bit = 1 and BRGH bit = 0.  2010 Microchip Technology Inc. DS39635C-page 237

PIC18F6310/6410/8310/8410 TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 65 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 65 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 65 RCREG1 EUSART1 Receive Register 65 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 65 BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 66 SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 66 SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 65 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. DS39635C-page 238  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 18.4 EUSART Synchronous Slave Mode To set up a Synchronous Slave Transmission: 1. Enable the synchronous slave serial port by set- Synchronous Slave mode is entered by clearing bit, ting bits, SYNC and SPEN, and clearing bit, CSRC (TXSTA<7>). This mode differs from the CSRC. Synchronous Master mode in that the shift clock is supplied externally at the CK1 pin (instead of being 2. Clear bits, CREN and SREN. supplied internally in Master mode). This allows the 3. If interrupts are desired, set enable bit, TXIE. device to transfer or receive data while in any 4. If the signal from the CKx pin is to be inverted, low-power mode. set the TXCKP bit. 5. If 9-bit transmission is desired, set bit, TX9. 18.4.1 EUSART SYNCHRONOUS SLAVE 6. Enable the transmission by setting enable bit, TRANSMIT TXEN. The operation of the Synchronous Master and Slave 7. If 9-bit transmission is selected, the ninth bit modes are identical except in the case of the Sleep should be loaded in bit, TX9D. mode. 8. Start transmission by loading data to the If two words are written to the TXREG1 and then the TXREGx register. SLEEP instruction is executed, the following will occur: 9. If using interrupts, ensure that the GIE and PEIE a) The first word will immediately transfer to the bits in the INTCON register (INTCON<7:6>) are TSR register and transmit. set. b) The second word will remain in the TXREG1 register. c) Flag bit, TX1IF, will not be set. d) When the first word has been shifted out of TSR, the TXREG1 register will transfer the second word to the TSR and flag bit, TX1IF, will now be set. e) If enable bit, TX1IE, is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 65 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 65 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 65 TXREG1 EUSART1 Transmit Register 65 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 65 BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 66 SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 66 SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 65 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.  2010 Microchip Technology Inc. DS39635C-page 239

PIC18F6310/6410/8310/8410 18.4.2 EUSART SYNCHRONOUS SLAVE To set up a Synchronous Slave Reception: RECEPTION 1. Enable the synchronous master serial port by The operation of the Synchronous Master and Slave setting bits, SYNC and SPEN, and clearing bit, modes is identical except in the case of Sleep or any CSRC. Idle mode and bit, SREN, which is a “don’t care” in 2. If interrupts are desired, set enable bit, RCIE. Slave mode. 3. If the signal from the CKx pin is to be inverted, If receive is enabled by setting the CREN bit prior to set the TXCKP bit. entering Sleep or any Idle mode, then a word may be 4. If 9-bit reception is desired, set bit, RX9. received while in this low-power mode. Once the word 5. To enable reception, set enable bit, CREN. is received, the RSR register will transfer the data to the 6. Flag bit, RCIF, will be set when reception is RCREG1 register; if the RC1IE enable bit is set, the complete. An interrupt will be generated if interrupt generated will wake the chip from the enable bit, RCIE, was set. low-power mode. If the global interrupt is enabled, the 7. Read the RCSTA register to get the 9th bit (if program will branch to the interrupt vector. enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing bit, CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 65 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 65 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 65 RCREG1 EUSART1 Receive Register 65 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 65 BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 66 SPBRGH1 Baud Rate Generator Register High Byte 66 SPBRG1 Baud Rate Generator Register Low Byte 65 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. DS39635C-page 240  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 19.0 ADDRESSABLE UNIVERSAL The pins of the AUSART module are multiplexed with SYNCHRONOUS the functions of PORTG (RG1/TX2/CK2 and RG2/RX2/DT2, respectively). In order to configure ASYNCHRONOUS RECEIVER these pins as an AUSART: TRANSMITTER (AUSART) • SPEN bit (RCSTA2<7>) must be set (= 1) The Addressable Universal Synchronous Asynchro- • TRISG<2> bit must be set (= 1) nous Receiver Transmitter (AUSART) module is very • TRISG<1> bit must be cleared (= 0) for similar in function to the Enhanced USART module, Asynchronous and Synchronous Master modes discussed in the previous chapter. It is provided as an • TRISG<1> bit must be set (= 1) for Synchronous additional channel for serial communication with Slave mode external devices, for those situations that do not require Note: The USART control will automatically Auto-Baud Detection (ABD) or LIN/J2602 bus support. reconfigure the pin from input to output as The AUSART can be configured in the following needed. modes: The operation of the Addressable USART module is • Asynchronous (full-duplex) controlled through two registers: TXSTA2 and • Synchronous – Master (half-duplex) RXSTA2. These are detailed in Register19-1 and • Synchronous – Slave (half-duplex) Register19-2 respectively.  2010 Microchip Technology Inc. DS39635C-page 241

PIC18F6310/6410/8310/8410 REGISTER 19-1: TXSTA2: AUSART2 TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC — BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-Bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit is enabled 0 = Transmit is disabled bit 4 SYNC: AUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 Unimplemented: Read as ‘0’ bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR is empty 0 = TSR is full bit 0 TX9D: 9th bit of Transmit Data bit Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS39635C-page 242  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 REGISTER 19-2: RCSTA2: AUSART2 RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port is enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port is disabled (held in Reset) bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care. Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave: Don’t care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-Bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> are set 0 = Disables address detection, all bytes are received and ninth bit can be used as a parity bit Asynchronous mode 9-Bit (RX9 = 0): Don’t care. bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG1 register and receiving next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit, CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data bit This can be address/data bit or a parity bit and must be calculated by user firmware.  2010 Microchip Technology Inc. DS39635C-page 243

PIC18F6310/6410/8310/8410 19.1 AUSART Baud Rate Generator Writing a new value to the SPBRG2 register causes the (BRG) BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting The BRG is a dedicated, 8-bit generator that supports the new baud rate. both the Asynchronous and Synchronous modes of the AUSART. 19.1.1 OPERATION IN POWER-MANAGED MODES The SPBRG2 register controls the period of a free-running timer. In Asynchronous mode, BRGH bit The device clock is used to generate the desired baud (TXSTA<2>) also controls the baud rate. In Synchro- rate. When one of the power-managed modes is nous mode, BRGH is ignored. Table19-1 shows the entered, the new clock source may be operating at a formula for computation of the baud rate for different different frequency. This may require an adjustment to AUSART modes, which only apply in Master mode the value in the SPBRG2 register. (internally generated clock). 19.1.2 SAMPLING Given the desired baud rate and FOSC, the nearest integer value for the SPBRG2 register can be calcu- The data on the RX2 pin is sampled three times by a lated using the formulas in Table19-1. From this, the majority detect circuit to determine if a high or a low error in baud rate can be determined. An example level is present at the RX2 pin. calculation is shown in Example19-1. Typical baud rates and error values for the various Asynchronous modes are shown in Table19-2. It may be advanta- geous to use the high baud rate (BRGH = 1) to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. TABLE 19-1: BAUD RATE FORMULAS Configuration Bits BRG/AUSART Mode Baud Rate Formula SYNC BRGH 0 0 Asynchronous FOSC/[64 (n + 1)] 0 1 Asynchronous FOSC/[16 (n + 1)] 1 x Synchronous FOSC/[4 (n + 1)] Legend: x = Don’t care, n = Value of SPBRG2 register EXAMPLE 19-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, BRGH = 0: Desired Baud Rate = FOSC/(64 ([SPBRG2] + 1)) Solving for SPBRG2: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.16% TABLE 19-2: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page TXSTA2 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 66 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 66 SPBRG2 AUSART2 Baud Rate Generator Register 66 Legend: Shaded cells are not used by the BRG. DS39635C-page 244  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES BRGH = 0 FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz BAUD Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG % % % % RATE Rate value Rate value Rate value Rate value Error Error Error Error (K) (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — — 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — — 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — — BRGH = 0 FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz BAUD Actual SPBRG Actual SPBRG Actual SPBRG % % % RATE Rate value Rate value Rate value Error Error Error (K) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51 1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12 2.4 2.404 0.16 25 2.403 -0.16 12 — — — 9.6 8.929 -6.99 6 — — — — — — 19.2 20.833 8.51 2 — — — — — — 57.6 62.500 8.51 0 — — — — — — 115.2 62.500 -45.75 0 — — — — — — BRGH = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — — — — — — — — — — 2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — BRGH = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — —  2010 Microchip Technology Inc. DS39635C-page 245

PIC18F6310/6410/8310/8410 19.2 AUSART Asynchronous Mode interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TX2IE (PIE3<4>). The Asynchronous mode of operation is selected by TX2IF will be set regardless of the state of TX2IE; it clearing the SYNC bit (TXSTA2<4>). In this mode, the cannot be cleared in software. TX2IF is also not AUSART uses standard Non-Return-to-Zero (NRZ) for- cleared immediately upon loading TXREG2, but mat (one Start bit, eight or nine data bits and one Stop becomes valid in the second instruction cycle following bit). The most common data format is 8 bits. An on-chip the load instruction. Polling TX2IF immediately dedicated 8-bit Baud Rate Generator can be used to following a load of TXREG2 will return invalid results. derive standard baud rate frequencies from the While TX2IF indicates the status of the TXREG2 regis- oscillator. ter, another bit, TRMT (TXSTA2<1>), shows the status The AUSART transmits and receives the LSb first. The of the TSR register. TRMT is a read-only bit which is set AUSART’s transmitter and receiver are functionally when the TSR register is empty. No interrupt logic is independent but use the same data format and baud tied to this bit so the user has to poll this bit in order to rate. The Baud Rate Generator produces a clock, determine if the TSR register is empty. either x16 or x64 of the bit shift rate, depending on the BRGH bit (TXSTA2<2>). Parity is not supported by the Note1: The TSR register is not mapped in data hardware but can be implemented in software and memory so it is not available to the user. stored as the 9th data bit. 2: Flag bit, TX2IF, is set when enable bit, TXEN is set. When operating in Asynchronous mode, the AUSART module consists of the following important elements: To set up an Asynchronous Transmission: • Baud Rate Generator 1. Initialize the SPBRG2 register for the appropriate • Sampling Circuit baud rate. Set or clear the BRGH bit, as required, • Asynchronous Transmitter to achieve the desired baud rate. • Asynchronous Receiver 2. Enable the asynchronous serial port by clearing bit, SYNC, and setting bit, SPEN. 19.2.1 AUSART ASYNCHRONOUS 3. If interrupts are desired, set enable bit, TX2IE. TRANSMITTER 4. If 9-bit transmission is desired, set transmit bit, The AUSART transmitter block diagram is shown in TX9. Can be used as address/data bit. Figure19-1. The heart of the transmitter is the Transmit 5. Enable the transmission by setting bit, TXEN, (Serial) Shift register (TSR). The Shift register obtains which will also set bit, TX2IF. its data from the Read/Write Transmit Buffer register, 6. If 9-bit transmission is selected, the ninth bit TXREG2. The TXREG2 register is loaded with data in should be loaded in bit, TX9D. software. The TSR register is not loaded until the Stop 7. Load data to the TXREG2 register (starts bit has been transmitted from the previous load. As transmission). soon as the Stop bit is transmitted, the TSR is loaded 8. If using interrupts, ensure that the GIE and PEIE with new data from the TXREG2 register (if available). bits in the INTCON register (INTCON<7:6>) are Once the TXREG2 register transfers the data to the set. TSR register (occurs in one TCY), the TXREG2 register is empty and the TX2IF flag bit (PIR3<4>) is set. This FIGURE 19-1: AUSART TRANSMIT BLOCK DIAGRAM Data Bus TX2IF TXREG2 Register TX2IE 8 MSb LSb (8)  0 Pin Buffer and Control TSR Register TX2 Pin Interrupt TXEN Baud Rate CLK TRMT SPEN SPBRG2 TX9 Baud Rate Generator TX9D DS39635C-page 246  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 19-2: ASYNCHRONOUS TRANSMISSION Write to TXREG2 Word 1 BRG Output (Shift Clock) TX2 (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TX2IF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) FIGURE 19-3: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG2 Word 1 Word 2 BRG Output (Shift Clock) TX2 (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TX2IF bit 1 TCY Word 1 Word 2 (Interrupt Reg. Flag) 1 TCY Word 1 Word 2 TRMT bit Transmit Shift Reg. Transmit Shift Reg. (Transmit Shift Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions. TABLE 19-4: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR3 — — RC2IF TX2IF — — — CCP3IF 65 PIE3 — — RC2IE TX2IE — — — CCP3IE 65 IPR3 — — RC2IP TX2IP — — — CCP3IP 65 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 66 TXREG2 AUSART2 Transmit Register 66 TXSTA2 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 66 SPBRG2 AUSART2 Baud Rate Generator Register 66 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.  2010 Microchip Technology Inc. DS39635C-page 247

PIC18F6310/6410/8310/8410 19.2.2 AUSART ASYNCHRONOUS 19.2.3 SETTING UP 9-BIT MODE WITH RECEIVER ADDRESS DETECT The receiver block diagram is shown in Figure19-4. This mode would typically be used in RS-485 systems. The data is received on the RX2 pin and drives the data To set up an Asynchronous Reception with Address recovery block. The data recovery block is actually a Detect Enable: high-speed shifter operating at x16 times the baud rate, 1. Initialize the SPBRG2 register for the appropriate whereas the main receive serial shifter operates at the baud rate. Set or clear the BRGH and BRG16 bit rate or at FOSC. This mode would typically be used bits, as required, to achieve the desired baud in RS-232 systems. rate. To set up an Asynchronous Reception: 2. Enable the asynchronous serial port by clearing 1. Initialize the SPBRG2 register for the appropriate the SYNC bit and setting the SPEN bit. baud rate. Set or clear the BRGH bit, as required, 3. If interrupts are required, set the RCEN bit and to achieve the desired baud rate. select the desired priority level with the RC2IP 2. Enable the asynchronous serial port by clearing bit. bit, SYNC, and setting bit, SPEN. 4. Set the RX9 bit to enable 9-bit reception. 3. If interrupts are desired, set enable bit, RC2IE. 5. Set the ADDEN bit to enable address detect. 4. If 9-bit reception is desired, set bit, RX9. 6. Enable reception by setting the CREN bit. 5. Enable the reception by setting bit, CREN. 7. The RC2IF bit will be set when reception is 6. Flag bit, RC2IF, will be set when reception is complete. The interrupt will be Acknowledged if complete and an interrupt will be generated if the RC2IE and GIE bits are set. enable bit, RC2IE, was set. 8. Read the RCSTA2 register to determine if any 7. Read the RCSTA2 register to get the 9th bit (if error occurred during reception, as well as read enabled) and determine if any error occurred bit 9 of data (if applicable). during reception. 9. Read RCREG2 to determine if the device is 8. Read the 8-bit received data by reading the being addressed. RCREG2 register. 10. If any error occurred, clear the CREN bit. 9. If any error occurred, clear the error by clearing 11. If the device has been addressed, clear the enable bit, CREN. ADDEN bit to allow all received data into the 10. If using interrupts, ensure that the GIE and PEIE receive buffer and interrupt the CPU. bits in the INTCON register (INTCON<7:6>) are set. FIGURE 19-4: AUSART RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK  64 MSb RSR Register LSb SPBRG2 or  16 or Stop (8) 7  1 0 Start Baud Rate Generator  4 RX9 Pin Buffer Data and Control Recovery RX2 RX9D RCREG2 Register FIFO SPEN 8 Interrupt RC2IF Data Bus RC2IE DS39635C-page 248  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 19-5: ASYNCHRONOUS RECEPTION RX2 (pin) Start Start Start bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 Read Rcv RCREG2 RCREG2 Buffer Reg RCREG2 RC2IF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX2 input. The RCREG2 (Receive Buffer 2) is read after the third word, causing the OERR (Overrun) bit to be set. TABLE 19-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR3 — — RC2IF TX2IF — — — CCP3IF 65 PIE3 — — RC2IE TX2IE — — — CCP3IE 65 IPR3 — — RC2IP TX2IP — — — CCP3IP 65 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 66 RCREG2 AUSART2 Receive Register 66 TXSTA2 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 66 SPBRG2 AUSART2 Baud Rate Generator Register 66 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.  2010 Microchip Technology Inc. DS39635C-page 249

PIC18F6310/6410/8310/8410 19.3 AUSART Synchronous Once the TXREG2 register transfers the data to the Master Mode TSR register (occurs in one TCYCLE), the TXREG2 is empty and the TX2IF flag bit (PIR3<4>) is set. The The Synchronous Master mode is entered by setting interrupt can be enabled or disabled by setting or clear- the CSRC bit (TXSTA2<7>). In this mode, the data is ing the interrupt enable bit, TX2IE (PIE3<4>). TX2IF is transmitted in a half-duplex manner (i.e., transmission set regardless of the state of enable bit, TX2IE; it can- and reception do not occur at the same time). When not be cleared in software. It will reset only when new transmitting data, the reception is inhibited and vice data is loaded into the TXREG2 register. versa. Synchronous mode is entered by setting bit, While flag bit, TX2IF, indicates the status of the TXREG2 SYNC (TXSTA2<4>). In addition, enable bit, SPEN register, another bit, TRMT (TXSTA2<1>), shows the (RCSTA2<7>), is set in order to configure the TX2 and status of the TSR register. TRMT is a read-only bit which RX2 pins to CK2 (clock) and DT2 (data) lines, is set when the TSR is empty. No interrupt logic is tied to respectively. this bit so the user has to poll this bit in order to deter- The Master mode indicates that the processor transmits mine if the TSR register is empty. The TSR is not the master clock on the CK2 line. mapped in data memory so it is not available to the user. To set up a Synchronous Master Transmission: 19.3.1 AUSART SYNCHRONOUS MASTER TRANSMISSION 1. Initialize the SPBRG2 register for the appropriate baud rate. The AUSART transmitter block diagram is shown in 2. Enable the synchronous master serial port by Figure19-1. The heart of the transmitter is the Transmit setting bits, SYNC, SPEN and CSRC. (Serial) Shift register (TSR). The Shift register obtains its data from the Read/Write Transmit Buffer register, 3. If interrupts are desired, set enable bit, TX2IE. TXREG2. The TXREG2 register is loaded with data in 4. If 9-bit transmission is desired, set bit, TX9. software. The TSR register is not loaded until the last 5. Enable the transmission by setting bit, TXEN. bit has been transmitted from the previous load. As 6. If 9-bit transmission is selected, the ninth bit soon as the last bit is transmitted, the TSR is loaded should be loaded in bit, TX9D. with new data from the TXREG2 (if available). 7. Start transmission by loading data to the TXREG2 register. 8. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 19-6: SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RX2/DT2 Pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 TX2/CK2 Pin Write to TXREG2 Reg Write Word 1 Write Word 2 TX2IF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ ‘1’ Note: Sync Master mode, SPBRG2 = 0, continuous transmission of two 8-bit words. DS39635C-page 250  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 19-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX2/DT2 Pin bit 0 bit 1 bit 2 bit 6 bit 7 TX2/CK2 Pin Write to TXREG2 Reg TX2IF bit TRMT bit TXEN bit TABLE 19-6: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR3 — — RC2IF TX2IF — — — CCP3IF 65 PIE3 — — RC2IE TX2IE — — — CCP3IE 65 IPR3 — — RC2IP TX2IP — — — CCP3IP 65 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 66 TXREG2 AUSART2 Transmit Register 66 TXSTA2 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 66 SPBRG2 AUSART2 Baud Rate Generator Register 66 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.  2010 Microchip Technology Inc. DS39635C-page 251

PIC18F6310/6410/8310/8410 19.3.2 AUSART SYNCHRONOUS 4. If interrupts are desired, set enable bit, RC2IE. MASTER RECEPTION 5. If 9-bit reception is desired, set bit, RX9. Once Synchronous mode is selected, reception is 6. If a single reception is required, set bit, SREN. enabled by setting either the Single Receive Enable bit, For continuous reception, set bit, CREN. SREN (RCSTA2<5>), or the Continuous Receive 7. Interrupt flag bit, RC2IF, will be set when Enable bit, CREN (RCSTA2<4>). Data is sampled on reception is complete and an interrupt will be the RX2 pin on the falling edge of the clock. generated if the enable bit, RC2IE, was set. If enable bit, SREN, is set, only a single word is 8. Read the RCSTA2 register to get the 9th bit (if received. If enable bit, CREN, is set, the reception is enabled) and determine if any error occurred continuous until CREN is cleared. If both bits are set, during reception. then CREN takes precedence. 9. Read the 8-bit received data by reading the RCREG2 register. To set up a Synchronous Master Reception: 10. If any error occurred, clear the error by clearing 1. Initialize the SPBRG2 register for the appropriate bit, CREN. baud rate. 11. If using interrupts, ensure that the GIE and PEIE 2. Enable the synchronous master serial port by bits in the INTCON register (INTCON<7:6>) are setting bits, SYNC, SPEN and CSRC. set. 3. Ensure bits, CREN and SREN, are clear. FIGURE 19-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RX2/DT2 Pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX2/CK2 Pin Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RC2IF bit (Interrupt) Read RCREG2 Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 19-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR3 — — RC2IF TX2IF — — — CCP3IF 65 PIE3 — — RC2IE TX2IE — — — CCP3IE 65 IPR3 — — RC2IP TX2IP — — — CCP3IP 65 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 66 RCREG2 AUSART2 Receive Register 66 TXSTA2 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 66 SPBRG2 AUSART2 Baud Rate Generator Register Low Byte 66 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. DS39635C-page 252  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 19.4 AUSART Synchronous Slave Mode To set up a Synchronous Slave Transmission: 1. Enable the synchronous slave serial port by Synchronous Slave mode is entered by clearing bit, setting bits, SYNC and SPEN, and clearing bit, CSRC (TXSTA2<7>). This mode differs from the CSRC. Synchronous Master mode in that the shift clock is supplied externally at the CK2 pin (instead of being 2. Clear bits, CREN and SREN. supplied internally in Master mode). This allows the 3. If interrupts are desired, set enable bit, TX2IE. device to transfer or receive data while in any 4. If 9-bit transmission is desired, set bit, TX9. low-power mode. 5. Enable the transmission by setting enable bit, TXEN. 19.4.1 AUSART SYNCHRONOUS 6. If 9-bit transmission is selected, the ninth bit SLAVE TRANSMIT should be loaded in bit, TX9D. The operation of the Synchronous Master and Slave 7. Start transmission by loading data to the modes are identical except in the case of the Sleep TXREG2 register. mode. 8. If using interrupts, ensure that the GIE and PEIE If two words are written to the TXREG2 and then the bits in the INTCON register (INTCON<7:6>) are SLEEP instruction is executed, the following will occur: set. a) The first word will immediately transfer to the TSR register and transmit. b) The second word will remain in TXREG2 register. c) Flag bit, TX2IF, will not be set. d) When the first word has been shifted out of TSR, the TXREG2 register will transfer the second word to the TSR and flag bit, TX2IF, will now be set. e) If enable bit, TX2IE,is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. TABLE 19-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR3 — — RC2IF TX2IF — — — CCP3IF 65 PIE3 — — RC2IE TX2IE — — — CCP3IE 65 IPR3 — — RC2IP TX2IP — — — CCP3IP 65 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 66 TXREG2 AUSART2 Transmit Register 66 TXSTA2 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 66 SPBRG2 AUSART2 Baud Rate Generator Register Low Byte 66 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.  2010 Microchip Technology Inc. DS39635C-page 253

PIC18F6310/6410/8310/8410 19.4.2 AUSART SYNCHRONOUS To set up a Synchronous Slave Reception: SLAVE RECEPTION 1. Enable the synchronous master serial port by The operation of the Synchronous Master and Slave setting bits, SYNC and SPEN, and clearing bit, modes is identical except in the case of Sleep, or any CSRC. Idle mode and bit, SREN, which is a “don’t care” in 2. If interrupts are desired, set enable bit, RC2IE. Slave mode. 3. If 9-bit reception is desired, set bit, RX9. If receive is enabled by setting the CREN bit prior to 4. To enable reception, set enable bit, CREN. entering Sleep, or any Idle mode, then a word may be 5. Flag bit, RC2IF, will be set when reception is received while in this low-power mode. Once the word complete. An interrupt will be generated if is received, the RSR register will transfer the data to the enable bit, RC2IE, was set. RCREG2 register; if the RC2IE enable bit is set, the 6. Read the RCSTA2 register to get the 9th bit (if interrupt generated will wake the chip from low-power enabled) and determine if any error occurred mode. If the global interrupt is enabled, the program will during reception. branch to the interrupt vector. 7. Read the 8-bit received data by reading the RCREG2 register. 8. If any error occurred, clear the error by clearing bit, CREN. 9. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 19-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR3 — — RC2IF TX2IF — — — CCP3IF 65 PIE3 — — RC2IE TX2IE — — — CCP3IE 65 IPR3 — — RC2IP TX2IP — — — CCP3IP 65 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 66 RCREG2 AUSART2 Receive Register 66 TXSTA2 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 66 SPBRG2 AUSART2 Baud Rate Generator Register Low Byte 66 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. DS39635C-page 254  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 20.0 10-BIT ANALOG-TO-DIGITAL The module has five registers: CONVERTER (A/D) MODULE • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) The Analog-to-Digital (A/D) Converter module has • A/D Control Register 0 (ADCON0) 12inputs for the PIC18FX310/X410 devices. This module allows conversion of an analog input signal to • A/D Control Register 1 (ADCON1) a corresponding 10-bit digital number. • A/D Control Register 2 (ADCON2) The ADCON0 register, shown in Register20-1, controls the operation of the A/D module. The ADCON1 register, shown in Register20-2, configures the functions of the port pins. The ADCON2 register, shown in Register20-3, configures the A/D clock source, programmed acquisition time and justification. REGISTER 20-1: ADCON0: A/D CONTROL REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-2 CHS<3:0>: Analog Channel Select bits 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5) 0110 = Channel 6 (AN6) 0111 = Channel 7 (AN7) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Unimplemented(1) 1101 = Unimplemented(1) 1110 = Unimplemented(1) 1111 = Unimplemented(1) bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion is in progress 0 = A/D is Idle bit 0 ADON: A/D On bit 1 = A/D Converter module is enabled 0 = A/D Converter module is disabled Note 1: Performing a conversion on unimplemented channels will return a floating input measurement.  2010 Microchip Technology Inc. DS39635C-page 255

PIC18F6310/6410/8310/8410 REGISTER 20-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-q R/W-q R/W-q R/W-q — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 VCFG1: Voltage Reference Configuration bit (VREF- source): 1 = VREF- (AN2) 0 = AVSS bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source): 1 = VREF+ (AN3) 0 = AVDD bit 3-0 PCFG<3:0>: A/D Port Configuration Control bits: 1 0 1 1 9 8 7 6 5 4 3 2 1 0 PCFG<3:0> N N N N N N N N N N N N A A A A A A A A A A A A 0000 A A A A A A A A A A A A 0001 A A A A A A A A A A A A 0010 A A A A A A A A A A A A 0011 A A A A A A A A A A A A 0100 D A A A A A A A A A A A 0101 D D A A A A A A A A A A 0110 D D D A A A A A A A A A 0111 D D D D A A A A A A A A 1000 D D D D D A A A A A A A 1001 D D D D D D A A A A A A 1010 D D D D D D D A A A A A 1011 D D D D D D D D A A A A 1100 D D D D D D D D D A A A 1101 D D D D D D D D D D A A 1110 D D D D D D D D D D D A 1111 D D D D D D D D D D D D A = Analog input D = Digital I/O DS39635C-page 256  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 REGISTER 20-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(1) bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(1) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion.  2010 Microchip Technology Inc. DS39635C-page 257

PIC18F6310/6410/8310/8410 The analog reference voltage is software-selectable to A device Reset forces all registers to their Reset state. either the device’s positive and negative supply voltage This forces the A/D module to be turned off and any (AVDD and AVSS), or the voltage level on the conversion in progress is aborted. RA3/AN3/VREF+ and RA2/AN2/VREF- pins. Each port pin associated with the A/D Converter can be The A/D Converter has a unique feature of being able configured as an analog input or as a digital I/O. The to operate while the device is in Sleep mode. To oper- ADRESH and ADRESL registers contain the result of ate in Sleep, the A/D conversion clock must be derived the A/D conversion. When the A/D conversion is com- from the A/D’s internal RC oscillator. plete, the result is loaded into the ADRESH/ADRESL registers, the GO/DONE bit (ADCON0 register) is The output of the sample and hold is the input into the cleared and the A/D Interrupt Flag bit, ADIF, is set. The converter, which generates the result via successive block diagram of the A/D module is shown in approximation. Figure20-1. FIGURE 20-1: A/D BLOCK DIAGRAM CHS<3:0> 1011 AN11 1010 AN10 1001 AN9 1000 AN8 0111 AN7 0110 AN6 0101 AN5 0100 AN4 VAIN (Input Voltage) 0011 AN3 10-Bit A/D 0010 AN2 Converter 0001 VCFG<1:0> AN1 AVDD(1) 0000 AN0 X0 VREF+ X1 Reference 1X Voltage VREF- 0X AVSS(1) Note 1: I/O pins have diode protection to VDD and VSS. DS39635C-page 258  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 The value in the ADRESH:ADRESL registers is not 5. Wait for A/D conversion to complete, by either: modified for a Power-on Reset. The ADRESH:ADRESL • Polling for the GO/DONE bit to be cleared registers will contain unknown data after a Power-on OR Reset. • Waiting for the A/D interrupt After the A/D module has been configured as desired, 6. Read A/D Result registers (ADRESH:ADRESL); the selected channel must be acquired before the conversion is started. The analog input channels must clear bit, ADIF, if required. have their corresponding TRIS bits selected as an 7. For next conversion, go to Step 1 or Step 2, as input. To determine acquisition time, see Section20.1 required. The A/D conversion time per bit is “A/D Acquisition Requirements”. After this acquisi- defined as TAD. A minimum wait of 3 TAD is tion time has elapsed, the A/D conversion can be required before the next acquisition starts. started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual FIGURE 20-2: A/D TRANSFER FUNCTION start of the conversion. The following steps should be followed to perform an 3FFh A/D conversion: 1. Configure the A/D module: 3FEh • Configure analog pins, voltage reference and ut p digital I/O (ADCON1) ut O • Select A/D input channel (ADCON0) de o • Select A/D acquisition time (ADCON2) al C003h • Select A/D conversion clock (ADCON2) git Di 002h • Turn on A/D module (ADCON0) 2. Configure A/D interrupt (if desired): 001h • Clear ADIF bit • Set ADIE bit 000h B B B B B B B B B B • Set GIE bit S S S S S S S S S S L L L L L L L L L L 34.. WStaaritt tchoen rveeqrsuiiorend: acquisition time (if required). 0.5 1 1.5 2 2.5 3 1022 022.5 1023 023.5 1 1 Analog Input Voltage • Set GO/DONE bit (ADCON0 register) FIGURE 20-3: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V Rs ANx RIC 1k SS RSS VAIN C5 PpIFN VT = 0.6V I±L E1A0K0A nGAE CHOLD = 25 pF VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage 6V ILEAKAGE = Leakage Current at the pin due to 5V various junctions VDD 4V 3V RIC = Interconnect Resistance 2V SS = Sampling Switch CHOLD = Sample/Hold Capacitance (from DAC) 1 2 3 4 RSS = Sampling Switch Resistance SamplingSwitch(k)  2010 Microchip Technology Inc. DS39635C-page 259

PIC18F6310/6410/8310/8410 20.1 A/D Acquisition Requirements To calculate the minimum acquisition time, Equation20-1 may be used. This equation assumes For the A/D Converter to meet its specified accuracy, that 1/2 LSb error is used (1024 steps for the A/D). The the charge holding capacitor (CHOLD) must be allowed 1/2 LSb error is the maximum error allowed for the A/D to fully charge to the input channel voltage level. The to meet its specified resolution. analog input model is shown in Figure20-3. The Example20-3 shows the calculation of the minimum source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required acquisition time, TACQ. This calculation is based on the following application system required to charge the capacitor, CHOLD. The sampling assumptions: switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage CHOLD = 25 pF at the analog input (due to pin leakage current). The Rs = 2.5 k maximum recommended impedance for analog Conversion Error  1/2 LSb sources is 2.5 k. After the analog input channel is VDD = 5V  Rss = 2 k selected (changed), the channel must be sampled for Temperature = 85C (system max.) at least the minimum acquisition time before starting a conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. EQUATION 20-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 20-2: A/D MINIMUM CHARGING TIME VHOLD = (VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))) or TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) EQUATION 20-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF TAMP = 0.2 s TCOFF = (Temp – 25C)(0.02 s/C) (85C – 25C)(0.02 s/C) 1.2 s Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 ms. TC = -(CHOLD)(RIC + RSS + RS) ln(1/2047) -(25 pF) (1 k + 2 k + 2.5 k) ln(0.0004883) 1.05 s TACQ = 0.2 s + 1 s + 1.2 s 2.4 s DS39635C-page 260  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 20.2 Selecting and Configuring 20.3 Selecting the A/D Conversion Automatic Acquisition Time Clock The ADCON2 register allows the user to select an The A/D conversion time per bit is defined as TAD. The acquisition time that occurs each time the GO/DONE A/D conversion requires 11 TAD per 10-bit conversion. bit is set. It also gives users the option to use an auto- The source of the A/D conversion clock is matically determined acquisition time. Acquisition time software-selectable. There are seven possible options may be set with the ACQT<2:0> bits (ADCON2<5:3>), for TAD: which provides a range of 2 to 20 TAD. • 2 TOSC When the GO/DONE bit is set, the A/D module contin- • 4 TOSC ues to sample the input for the selected acquisition • 8 TOSC time, then automatically begins a conversion. • 16 TOSC Since the acquisition time is programmed, there may be • 32 TOSC no need to wait for an acquisition time between selecting • 64 TOSC a channel and setting the GO/DONE bit. Manual acqui- sition is selected when ACQT<2:0> = 000. When the • Internal RC Oscillator GO/DONE bit is set, sampling is stopped and a conver- For correct A/D conversions, the A/D conversion clock sion begins. The user is responsible for ensuring the (TAD) must be as short as possible, but greater than the required acquisition time has passed between selecting minimum TAD (approximately 2s, see Parameter 130 the desired input channel and setting the GO/DONE bit. for more information). This option is also the default Reset state of the Table20-1 shows the resultant TAD times derived from ACQT<2:0> bits and is compatible with devices that do the device operating frequencies and the A/D clock not offer programmable acquisition times. source selected. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended, or if the conversion has begun. TABLE 20-1: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Maximum Device Frequency Operation ADCS<2:0> PIC18F6X10/8X10 PIC18LF6X10/8X10(4) 2 TOSC 000 1.25 MHz 666 kHz 4 TOSC 100 2.50 MHz 1.33 MHz 8 TOSC 001 5.00 MHz 2.66 MHz 16 TOSC 101 10.0 MHz 5.33 MHz 32 TOSC 010 20.0 MHz 10.65 MHz 64 TOSC 110 40.0 MHz 21.33 MHz RC(3) x11 1.00 MHz(1) 1.00 MHz(2) Note 1: The RC source has a typical TAD time of 4 s. 2: The RC source has a typical TAD time of 6 s. 3: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D accuracy may be out of specification. 4: Low-power (PIC18LFXXXX) devices only.  2010 Microchip Technology Inc. DS39635C-page 261

PIC18F6310/6410/8310/8410 20.4 Operation in Power-Managed 20.5 Configuring Analog Port Pins Modes The ADCON1, TRISA and TRISF registers all The selection of the automatic acquisition time and A/D configure the A/D port pins. The port pins needed as conversion clock is determined in part by the clock analog inputs must have their corresponding TRIS bits source and frequency while in a power-managed set (input). If the TRIS bit is cleared (output), the digital mode. output level (VOH or VOL) will be converted. If the A/D is expected to operate while the device is in The A/D operation is independent of the state of the a power-managed mode, the ACQT<2:0> and CHS<3:0> bits and the TRIS bits. ADCS<2:0> bits in ADCON2 should be updated in Note1: When reading the PORT register, all pins accordance with the clock source to be used in that configured as analog input channels will mode. After entering the mode, an A/D acquisition or read as cleared (a low level). Pins config- conversion may be started. Once started, the device ured as digital inputs will convert an should continue to be clocked by the same clock analog input. Analog levels on a digitally source until the conversion has been completed. configured input will be accurately If desired, the device may be placed into the corre- converted. sponding Idle mode during the conversion. If the device 2: Analog levels on any pin defined as a clock frequency is less than 1 MHz, the A/D RC clock digital input may cause the digital input source should be selected. buffer to consume current out of the Operation in the Sleep mode requires the A/D FRC device’s specification limits. clock to be selected. If bits, ACQT<2:0>, are set to ‘000’ and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the SLEEP instruction and entry to Sleep mode. The IDLEN bit (OSCCON<7>) must have already been cleared prior to starting the conversion. DS39635C-page 262  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 20.6 A/D Conversions After the A/D conversion is completed or aborted, a 2TAD wait is required before the next acquisition can be Figure20-4 shows the operation of the A/D Converter started. After this wait, acquisition on the selected after the GO bit has been set and the ACQT<2:0> bits channel is automatically started. are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the Note: The GO/DONE bit should NOT be set in conversion begins. the same instruction that turns on the A/D. Figure20-5 shows the operation of the A/D Converter after the GO/DONE bit has been set and the 20.7 Discharge ACQT<2:0> bits are set to ‘010’, and selecting a 4 TAD The discharge phase is used to initialize the value of acquisition time before the conversion starts. the capacitor array. The array is discharged before Clearing the GO/DONE bit during a conversion will every sample. This feature helps to optimize the abort the current conversion. The A/D Result register unity-gain amplifier as the circuit always needs to pair will NOT be updated with the partially completed charge the capacitor array, rather than A/D conversion sample. This means the charge/discharge based on previous measure values. ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). FIGURE 20-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY - TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 TAD1 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Discharge Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit On the following cycle: ADRESH:ADRESL are loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. FIGURE 20-5: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) TACQT Cycles TAD Cycles 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 TAD1 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Automatic Acquisition Conversion starts Discharge Time (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues On the following cycle: acquiring input) ADRESH:ADRESL are loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input.  2010 Microchip Technology Inc. DS39635C-page 263

PIC18F6310/6410/8310/8410 20.8 Use of the CCP2 Trigger (moving ADRESH/ADRESL to the desired location). The appropriate analog input channel must be selected An A/D conversion can be started by the “Special Event and the minimum acquisition period is either timed by Trigger” of the CCP2 module. This requires that the the user, or an appropriate TACQ time selected before CCP2M<3:0> bits (CCP2CON<3:0>) be programmed the “Special Event Trigger” sets the GO/DONE bit as ‘1011’ and that the A/D module is enabled (ADON (starts a conversion). bit is set). When the trigger occurs, the GO/DONE bit If the A/D module is not enabled (ADON is cleared), the will be set, starting the A/D acquisition and conversion, “Special Event Trigger” will be ignored by the A/D and the Timer1 (or Timer3) counter will be reset to zero. module, but will still reset the Timer1 (or Timer3) Timer1 (or Timer3) is reset to automatically repeat the counter. A/D acquisition period with minimal software overhead TABLE 20-2: REGISTERS ASSOCIATED WITH A/D OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR1 PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 65 PIE1 PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 65 IPR1 PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 65 PIR2 OSCFIF CMIF — — BCLIF HLVDIF TMR3IF CCP2IF 65 PIE2 OSCFIE CMIE — — BCLIE HLVDIE TMR3IE CCP2IE 65 IPR2 OSCFIP CMIP — — BCLIP HLVDIP TMR3IP CCP2IP 65 ADRESH A/D Result Register High Byte 64 ADRESL A/D Result Register Low Byte 64 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 64 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 64 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 64 PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 66 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Register 66 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 66 TRISF PORTF Data Direction Register 66 LATF LATF Output Latch Register 66 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: These pins may be configured as port pins depending on the oscillator mode selected. DS39635C-page 264  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 21.0 COMPARATOR MODULE The CMCON register (Register21-1) selects the comparator input and output configuration. Block The analog comparator module contains two diagrams of the various comparator configurations are comparators that can be configured in a variety of shown in Figure21-1. ways. The inputs can be selected from the analog inputs multiplexed with pins RF3 through RF6, as well as the on-chip voltage reference (see Section22.0 “Comparator Voltage Reference Module”). The digi- tal outputs (normal or inverted) are available at the pin level and can also be read through the control register. REGISTER 21-1: CMCON: COMPARATOR CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN- 0 = C2 VIN+ < C2 VIN- When C2INV = 1: 1 = C2 VIN+ < C2 VIN- 0 = C2 VIN+ > C2 VIN- bit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN- 0 = C1 VIN+ < C1 VIN- When C1INV = 1: 1 = C1 VIN+ < C1 VIN- 0 = C1 VIN+ > C1 VIN-) bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 output is inverted 0 = C2 output is not inverted bit 4 C1INV: Comparator 1 Output Inversion bit 1 = C1 output is inverted 0 = C1 output is not inverted bit 3 CIS: Comparator Input Switch bit When CM<2:0> = 110: 1 = C1 VIN- connects to RF5/AN10 C2 VIN- connects to RF3/AN8 0 = C1 VIN- connects to RF6/AN11 C2 VIN- connects to RF4/AN9 bit 2-0 CM<2:0>: Comparator Mode bits Figure21-1 shows the Comparator modes and the CM<2:0> bit settings.  2010 Microchip Technology Inc. DS39635C-page 265

PIC18F6310/6410/8310/8410 21.1 Comparator Configuration mode is changed, the comparator output level may not be valid for the specified mode change delay shown in There are eight modes of operation for the compara- Section27.0 “Electrical Characteristics”. tors, shown in Figure21-1. Bits, CM<2:0>, of the CMCON register are used to select these modes. The Note: Comparator interrupts should be disabled TRISF register controls the data direction of the during a Comparator mode change; comparator pins for each mode. If the Comparator otherwise, a false interrupt may occur. FIGURE 21-1: COMPARATOR I/O OPERATING MODES Comparators Reset (POR Default Value) Comparators Off CM<2:0> = 000 CM<2:0> = 111 RF6/AN11 A VIN- RF6/AN11 D VIN- RF5/AN10/ A VIN+ C1 Off (Read as ‘0’) RF5/AN10/ D VIN+ C1 Off (Read as ‘0’) CVREF CVREF RF4/AN9 A VIN- RF4/AN9 D VIN- RF3/AN8 A VIN+ C2 Off (Read as ‘0’) RF3/AN8 D VIN+ C2 Off (Read as ‘0’) Two Independent Comparators Two Independent Comparators with Outputs CM<2:0> = 010 CM<2:0> = 011 RF6/AN11 A VIN- RF6/AN11 A VIN- RF5/AN10/ A VIN+ C1 C1OUT RF5/AN10/ A VIN+ C1 C1OUT CVREF CVREF RF2/AN7/C1OUT* RF4/AN9 A VIN- RF3/AN8 A VIN+ C2 C2OUT RF4/AN9 A VIN- RF3/AN8 A VIN+ C2 C2OUT RF1/AN6/C2OUT* Two Common Reference Comparators Two Common Reference Comparators with Outputs CM<2:0> = 100 CM<2:0> = 101 RF6/AN11 A VIN- RF6/AN11 A VIN- RF5/AN10/ A VIN+ C1 C1OUT RF5/AN10/ A VIN+ C1 C1OUT CVREF CVREF RF2/AN7/C1OUT* RF4/AN9 A VIN- RF3/AN8 D VIN+ C2 C2OUT RF4/AN9 A VIN- RF3/AN8 D VIN+ C2 C2OUT RF1/AN6/C2OUT* One Independent Comparator with Output Four Inputs Multiplexed to Two Comparators CM<2:0> = 001 CM<2:0> = 110 RF6/AN11 A VIN- RF6/AN11 A CIS = 0 VIN- RCFV5R/EAFN10/ A VIN+ C1 C1OUT RCFV5R/EAFN10/ A CIS = 1 VIN+ C1 C1OUT RF2/AN7/C1OUT* RF4/AN9 A CIS = 0 VIN- RF3/AN8 A CIS = 1 RF4/AN9 D VIN- VIN+ C2 C2OUT RF3/AN8 D VIN+ C2 Off (Read as ‘0’) CVREF From VREF Module A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch * Setting the TRISF<2:1> bits will disable the comparator outputs by configuring the pins as inputs. DS39635C-page 266  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 21.2 Comparator Operation 21.3.2 INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure21-2, along with The comparator module also allows the selection of an the relationship between the analog input levels and internally generated voltage reference from the com- the digital output. When the analog input at VIN+ is less parator voltage reference module. This module is than the analog input, VIN-, the output of the described in more detail in Section22.0 “Comparator comparator is a digital low level. When the analog input Voltage Reference Module”. at VIN+ is greater than the analog input, VIN-, the output The internal reference is only available in the mode of the comparator is a digital high level. The shaded where four inputs are multiplexed to two comparators areas of the output of the comparator, in Figure21-2, (CM<2:0>=110). In this mode, the internal voltage represent the uncertainty due to input offsets and reference is applied to the VIN+ pin of both response time. comparators. 21.3 Comparator Reference 21.4 Comparator Response Time Depending on the Comparator Operating mode, either Response time is the minimum time, after selecting a an external or internal voltage reference may be used. new reference voltage or input source, before the The analog signal present at VIN- is compared to the comparator output has a valid level. If the internal ref- signal at VIN+ and the digital output of the comparator erence is changed, the maximum delay of the internal is adjusted accordingly (Figure21-2). voltage reference must be considered when using the comparator outputs. Otherwise, the maximum delay of FIGURE 21-2: SINGLE COMPARATOR the comparators should be used (see Section27.0 “Electrical Characteristics”). 21.5 Comparator Outputs VIN+ + Output The comparator outputs are read through the CMCON VIN- – register. These bits are read-only. The comparator outputs may also be directly output to the RF2 and RF1 I/O pins. When enabled, multiplexors in the output path of the RF2 and RF1 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the VIN- comparators is related to the input offset voltage and the response time given in the specifications. VIN+ Figure21-3 shows the comparator output block diagram. The TRISF bits will still function as an output enable/ Output disable for the RF2 and RF1 pins while in this mode. The polarity of the comparator outputs can be changed using the C2INV and C1INV bits (CMCON<5:4>). 21.3.1 EXTERNAL REFERENCE SIGNAL Note1: When reading the PORT register, all pins When external voltage references are used, the configured as analog inputs will read as a comparator module can be configured to have the com- ‘0’. Pins configured as digital inputs will parators operate from the same, or different reference convert an analog input according to the sources. However, threshold detector applications may Schmitt Trigger input specification. require the same reference. The reference signal must 2: Analog levels on any pin defined as a dig- be between VSS and VDD and can be applied to either ital input may cause the input buffer to pin of the comparator(s). consume more current than is specified.  2010 Microchip Technology Inc. DS39635C-page 267

PIC18F6310/6410/8310/8410 FIGURE 21-3: COMPARATOR OUTPUT BLOCK DIAGRAM X E L + Port Pins P TI To RA4 or UL - RA5 Pin M D Q Bus CxINV Data Read CMCON EN D Q Set CMIF bit EN CL From Other Reset Comparator 21.6 Comparator Interrupts 21.7 Comparator Operation During Sleep The comparator interrupt flag is set whenever there is a change in the output value of either comparator. When a comparator is active and the device is placed Software will need to maintain information about the in Sleep mode, the comparator remains active and the status of the output bits, as read from CMCON<7:6>, to interrupt is functional, if enabled. This interrupt will determine the actual change that occurred. The CMIF wake-up the device from Sleep mode, when enabled. bit (PIR2<6>) is the Comparator Interrupt Flag. The While the comparator is powered up, higher Sleep CMIF bit must be reset by clearing it. Since it is also currents than shown in the power-down current possible to write a ‘1’ to this register, a simulated specification will occur. Each operational comparator interrupt may be initiated. will consume additional current, as shown in the Both the CMIE bit (PIE2<6>) and the PEIE bit comparator specifications. To minimize power (INTCON<6>) must be set to enable the interrupt. In consumption while in Sleep mode, turn off the addition, the GIE bit (INTCON<7>) must also be set. If comparators (CM<2:0>=111) before entering Sleep. any of these bits are clear, the interrupt is not enabled, If the device wakes up from Sleep, the contents of the though the CMIF bit will still be set if an interrupt CMCON register are not affected. condition occurs. 21.8 Effects of a Reset Note: If a change in the CMCON register (C1OUT or C2OUT) should occur when a A device Reset forces the CMCON register to its Reset read operation is being executed (start of state, causing the comparator module to be in the the Q2 cycle), then the CMIF (PIR Comparator Reset mode (CM<2:0>=000). This registers) interrupt flag may not get set. ensures that all potential inputs are analog inputs. Device current is minimized when analog inputs are The user, in the Interrupt Service Routine, can clear the present at Reset time. The comparators are powered interrupt in the following manner: down during the Reset interval. a) Any read or write of CMCON will end the mismatch condition. b) Clear flag bit, CMIF. A mismatch condition will continue to set flag bit, CMIF. Reading CMCON will end the mismatch condition and allow flag bit, CMIF, to be cleared. DS39635C-page 268  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 21.9 Analog Input Connection range by more than 0.6V in either direction, one of the Considerations diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 k is A simplified circuit for an analog input is shown in recommended for the analog sources. Any external Figure21-4. Since the analog pins are connected to a component connected to an analog input pin, such as digital output, they have reverse biased diodes to VDD a capacitor or a Zener diode, should have very little and VSS. The analog input, therefore, must be between leakage current. VSS and VDD. If the input voltage deviates from this FIGURE 21-4: COMPARATOR ANALOG INPUT MODEL VDD RS < 10k VT = 0.6V RIC Comparator AIN Input VA C5 PpIFN VT = 0.6V I±L1E0A0K AnGAE VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 65 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 65 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR2 OSCFIF CMIF — — BCLIF HLVDIF TMR3IF CCP2IF 65 PIE2 OCSFIE CMIE — — BCLIE HLVDIE TMR3IE CCP2IE 65 IPR2 OSCFIP CMIP — — BCLIP HLVDIP TMR3IP CCP2IP 65 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 66 LATF LATF Output Latch Register 66 TRISF PORTF Data Direction Register 66 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.  2010 Microchip Technology Inc. DS39635C-page 269

PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 270  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 22.0 COMPARATOR VOLTAGE voltage, each with 16 distinct levels. The range to be REFERENCE MODULE used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the The comparator voltage reference is a 16-tap resistor steps selected by the CVREF selection bits ladder network that provides a selectable reference (CVR<3:0>), with one range offering finer resolution. voltage. Although its primary purpose is to provide a The equations used to calculate the output of the reference for the analog comparators, it may also be Comparator Voltage Reference are as follows: used independently of them. If CVRR = 1: A block diagram is of the module shown in Figure22-1. CVREF = ((CVR<3:0>)/24) x CVRSRC The resistor ladder is segmented to provide two ranges If CVRR = 0: of CVREF values and has a power-down function to CVREF = (CVDD x 1/4) + (((CVR<3:0>)/32) x CVRSRC) conserve power when the reference is not being used. The module’s supply reference can be provided from The comparator reference supply voltage can come either device VDD/VSS, or an external voltage from either VDD and VSS, or the external VREF+ and reference. VREF- that are multiplexed with RA2 and RA3. The voltage source is selected by the CVRSS bit 22.1 Configuring the Comparator (CVRCON<4>). Voltage Reference The settling time of the comparator voltage reference must be considered when changing the CVREF The voltage reference module is controlled through the output (see Table27-3 in Section27.0 “Electrical CVRCON register (Register22-1). The Comparator Characteristics”). Voltage Reference provides two ranges of output REGISTER 22-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit(1) 1 = CVREF voltage level is also output on the RF5/AN10/CVREF pin 0 = CVREF voltage is disconnected from the RF5/AN10/CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = 0 CVRSRC to 0.667 CVRSRC, with CVRSRC/24 step size 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-) 0 = Comparator reference source, CVRSRC = VDD – VSS bit 3-0 CVR<3:0>: Comparator VREF Value Selection bits (0  (CVR<3:0>)  15) When CVRR = 1: CVREF = ((CVR<3:0>)/24)  (CVRSRC) When CVRR = 0: CVREF = (CVRSRC/4) + ((CVR<3:0>)/32)  (CVRSRC) Note 1: CVROE overrides the TRISF<5> bit setting if enabled for output; RF5 must also be configured as an input by setting TRISF<5> to ‘1’.  2010 Microchip Technology Inc. DS39635C-page 271

PIC18F6310/6410/8310/8410 FIGURE 22-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 VREF+ VDD CVRSS = 0 8R CVR<3:0> R CVREN R R R X U M 16 Steps 1 CVREF o- 6-t 1 R R R CVRR 8R CVRSS = 1 VREF- CVRSS = 0 22.2 Voltage Reference Accuracy/Error 22.4 Effects of a Reset The full range of voltage reference cannot be realized A device Reset disables the voltage reference by due to the construction of the module. The transistors clearing bit, CVREN (CVRCON<7>). This Reset also on the top and bottom of the resistor ladder network disconnects the reference from the RA2 pin by clearing (Figure22-1) keep CVREF from approaching the refer- bit, CVROE (CVRCON<6>), and selects the high-voltage ence source rails. The voltage reference is derived range by clearing bit, CVRR (CVRCON<5>). The CVR from the reference source; therefore, the CVREF output value select bits are also cleared. changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be 22.5 Connection Considerations found in Section27.0 “Electrical Characteristics”. The voltage reference module operates independently 22.3 Operation During Sleep of the comparator module. The output of the reference generator may be connected to the RF5 pin if the When the device wakes up from Sleep, through an TRISF<5> bit and the CVROE bit are both set. interrupt or a Watchdog Timer time-out, the contents of Enabling the voltage reference output onto the RF5 pin, the CVRCON register are not affected. To minimize with an input signal present, will increase current current consumption in Sleep mode, the voltage consumption. Connecting RF5 as a digital output with reference should be disabled. CVRSS enabled will also increase current consumption. The RF5 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage refer- ence output for external connections to VREF. Figure22-2 shows an example buffering technique. DS39635C-page 272  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 22-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18FXXXX CVREF R(1) Module + Voltage RF5 – CVREF Output Reference Output Impedance Note 1: R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>. TABLE 22-1: REGISTERS ASSOCIATED WITH THE COMPARATOR VOLTAGE REFERENCE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 65 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 65 TRISF PORTF Data Direction Register 66 Legend: Shaded cells are not used with the comparator voltage reference.  2010 Microchip Technology Inc. DS39635C-page 273

PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 274  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 23.0 HIGH/LOW-VOLTAGE The High/Low-Voltage Detect Control register DETECT (HLVD) (Register23-1) completely controls the operation of the HLVD module. This allows the circuitry to be “turned PIC18F6310/6410/8310/8410 devices have a off” by the user under software control, which High/Low-Voltage Detect module (HLVD). This is a minimizes the current consumption for the device. programmable circuit that allows the user to specify The block diagram for the HLVD module is shown in both a device voltage trip point and the direction of Figure23-1. change from that point. If the device experiences an excursion past the trip point in that direction, an inter- rupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. REGISTER 23-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 VDIRMAG — IRVST HLVDEN HLVDL3(1) HLVDL2(1) HLVDL1(1) HLVDL0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 VDIRMAG: Voltage Direction Magnitude Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>) 0 = Event occurs when voltage equals or falls below trip point (HLVDL<3:0>) bit 6 Unimplemented: Read as ‘0’ bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage range and the HLVD interrupt should not be enabled bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD is enabled 0 = HLVD is disabled bit 3-0 HLVDL<3:0>: Voltage Detection Limit bits(1) 1110 = Maximum setting • • • 0001 = Minimum setting Note 1: HLVDL<3:0> modes that result in a trip point, below the valid operating voltage of the device, are not tested.  2010 Microchip Technology Inc. DS39635C-page 275

PIC18F6310/6410/8310/8410 The module is enabled by setting the HLVDEN bit. level at which the device detects a high or low-voltage Each time that the HLVD module is enabled, the event, depending on the configuration of the module. circuitry requires some time to stabilize. The IRVST bit When the supply voltage is equal to the trip point, the is a read-only bit and is used to indicate when the circuit voltage tapped off of the resistor array is equal to the is stable. The module can only generate an interrupt internal reference voltage generated by the voltage after the circuit is stable and IRVST is set. reference module. The comparator then generates an interrupt signal by setting the HLVDIF bit. The VDIRMAG bit determines the overall operation of the module. When VDIRMAG is cleared, the module The trip point voltage is software programmable to any monitors for drops in VDD below a predetermined set one of 16 values. The trip point is selected by point. When the bit is set, the module monitors for rises programming the HLVDL<3:0> bits (HLVDCON<3:0>). in VDD above the set point. The HLVD module has an additional feature that allows the user to supply the trip voltage to the module from an 23.1 Operation external source. This mode is enabled when bits, HLVDL<3:0>, are set to ‘1111’. In this state, the compar- When the HLVD module is enabled, a comparator uses ator input is multiplexed from the external input pin, an internally generated reference voltage as the set HLVDIN. This gives users flexibility because it allows point. The set point is compared with the trip point, them to configure the High/Low-Voltage Detect interrupt where each node in the resistor divider represents a to occur at any voltage in the valid operating range. trip point voltage. The “trip point” voltage is the voltage FIGURE 23-1: HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT) Externally Generated Trip Point VDD VDD HLVDL<3:0> HLVDCON Register HLVDIN HLVDEN VDIRMAG HLVDIN X Set U M HLVDIF 1 o- 6-t 1 HLVDEN Internal Voltage BOREN Reference DS39635C-page 276  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 23.2 HLVD Setup Depending on the application, the HLVD module does not need to be operating constantly. To decrease the The following steps are needed to set up the HLVD current requirements, the HLVD circuitry may only module: need to be enabled for short periods where the voltage 1. Disable the module by clearing the HLVDEN bit is checked. After doing the check, the HLVD module (HLVDCON<4>). may be disabled. 2. Write the value to the HLVDL<3:0> bits that select the desired HLVD trip point. 23.4 HLVD Start-up Time 3. Set the VDIRMAG bit to detect high voltage The internal reference voltage of the HLVD module, (VDIRMAG = 1) or low voltage (VDIRMAG = 0). specified in electrical specification Parameter D420B, 4. Enable the HLVD module by setting the may be used by other internal circuitry, such as the HLVDEN bit. Programmable Brown-out Reset. If the HLVD or other 5. Clear the HLVD interrupt flag (PIR2<2>), which circuits using the voltage reference are disabled to may have been set from a previous interrupt. lower the device’s current consumption, the reference 6. Enable the HLVD interrupt, if interrupts are voltage circuit will require time to become stable before desired, by setting the HLVDIE and GIE bits a low or high-voltage condition can be reliably (PIE<2> and INTCON<7>). An interrupt will not detected. This start-up time, TIRVST, is an interval that be generated until the IRVST bit is set. is independent of device clock speed. It is specified in electrical specification Parameter36 (Table27-12). 23.3 Current Consumption The HLVD interrupt flag is not enabled until TIRVST has expired and a stable reference voltage is reached. For When the module is enabled, the HLVD comparator and this reason, brief excursions beyond the set point may voltage divider are enabled and will consume static cur- not be detected during this interval. Refer to rent. The total current consumption, when enabled, is Figure23-2 or Figure23-3. specified in electrical specification ParameterD022B. FIGURE 23-2: HIGH/LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0) CASE 1: HLVDIF may not be set VDD VLVD HLVDIF Enable HLVD TIRVST IRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VDD VLVD HLVDIF Enable HLVD IRVST TIRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists  2010 Microchip Technology Inc. DS39635C-page 277

PIC18F6310/6410/8310/8410 FIGURE 23-3: HIGH/LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: HLVDIF may not be set VLVD VDD HLVDIF Enable HLVD IRVST TIRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VLVD VDD HLVDIF Enable HLVD IRVST TIRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists 23.5 Applications FIGURE 23-4: TYPICAL LOW-VOLTAGE DETECT APPLICATION In many applications, the ability to detect a drop below, or rise above, a particular threshold is desirable. For example, the HLVD module could be periodically enabled to detect USB attach or detach. This assumes the device is powered by a lower voltage source than the Universal Serial Bus (USB) when detached. An VA attach would indicate a High-Voltage Detect from, for VB example, 3.3V to 5V (the voltage on USB) and vice e g versa for a detach. This feature could save a design a a t few extra components and an attach signal (input pin). ol V For general battery applications, Figure23-4 shows a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage, VA, the HLVD logic generates an interrupt at time, TA. The interrupt could cause the execution of an ISR, Time TA TB which would allow the application to perform “house- keeping tasks” and perform a controlled shutdown Legend: VA = HLVD trip point before the device voltage exits the valid operating VB = Minimum valid device range at TB. The HLVD thus, would give the application operating voltage a time window, represented by the difference between TA and TB, to safely exit. DS39635C-page 278  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 23.6 Operation During Sleep 23.7 Effects of a Reset When enabled, the HLVD circuitry continues to operate A device Reset forces all registers to their Reset state. during Sleep. If the device voltage crosses the trip This forces the HLVD module to be turned off. point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. TABLE 23-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 64 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 63 PIR2 OSCFIF CMIF — — BCLIF HLVDIF TMR3IF CCP2IF 65 PIE2 OCSFIE CMIE — — BCLIE HLVDIE TMR3IE CCP2IE 65 IPR2 OSCFIP CMIP — — BCLIP HLVDIP TMR3IP CCP2IP 65 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module.  2010 Microchip Technology Inc. DS39635C-page 279

PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 280  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 24.0 SPECIAL FEATURES OF THE A complete discussion of device Resets and interrupts CPU is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up Tim- PIC18F6310/6410/8310/8410 devices include several ers provided for Resets, PIC18F6310/6410/8310/8410 features intended to maximize reliability and minimize devices have a Watchdog Timer, which is either cost through elimination of external components. permanently enabled via the Configuration bits, or These are: software controlled (if configured as disabled). • Oscillator Selection The inclusion of an internal RC oscillator also provides • Resets: the additional benefits of a Fail-Safe Clock Monitor - Power-on Reset (POR) (FSCM) and Two-Speed Start-up. FSCM provides for - Power-up Timer (PWRT) background monitoring of the peripheral clock and automatic switchover in the event of its failure. - Oscillator Start-up Timer (OST) Two-Speed Start-up enables code to be executed - Brown-out Reset (BOR) almost immediately on start-up, while the primary clock • Interrupts source completes its start-up delays. • Watchdog Timer (WDT) All of these features are enabled and configured by • Fail-Safe Clock Monitor setting the appropriate Configuration register bits. • Two-Speed Start-up • Code Protection 24.1 Configuration Bits • ID Locations The Configuration bits can be programmed (read as • In-Circuit Serial Programming (ICSP) ‘0’) or left unprogrammed (read as ‘1’), to select various The oscillator can be configured for the application device configurations. These bits are mapped, starting depending on frequency, power, accuracy and cost. All at program memory location, 300000h. of the options are discussed in detail in Section3.0 The user will note that address, 300000h, is beyond the “Oscillator Configurations”. user program memory space. In fact, it belongs to the configuration memory space (300000h-3FFFFFh), which can only be accessed using table reads. TABLE 24-1: CONFIGURATION BITS AND DEVICE IDs Default/ File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed Value 300001h CONFIG1H IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 00-- 0111 300002h CONFIG2L — — — BORV1 BORV0 BOREN1 BOREN0 PWRTEN ---1 1111 300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111 300004h CONFIG3L WAIT BW — — — — PM1 PM0 11-- --11 300005h CONFIG3H MCLRE — — — — LPT1OSC — CCP2MX 1--- -0-1 300006h CONFIG4L DEBUG XINST — — — — — STVREN 10-- ---1 300008h CONFIG5L — — — — — — — CP ---- ---1 30000Ch CONFIG7L(1) — — — — — — — EBTR ---- ---1 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 11qx xxxx(2) 3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 qq1q(2) Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on individual device. Shaded cells are unimplemented, read as ‘0’. Note 1: Unimplemented in PIC18F6310/6410 devices; maintain this bit set. 2: See Register24-9 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.  2010 Microchip Technology Inc. DS39635C-page 281

PIC18F6310/6410/8310/8410 REGISTER 24-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-0 R/P-0 U-0 U-0 R/P-0 R/P-1 R/P-1 R/P-1 IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at erase bit ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode is enabled 0 = Oscillator Switchover mode is disabled bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 FOSC<3:0>: Oscillator Selection bits 11xx = External RC oscillator, CLKO function on RA6 101x = External RC oscillator, CLKO function on RA6 1001 = Internal oscillator block, CLKO function on RA6, port function on RA7 1000 = Internal oscillator block, port function on RA6 and RA7 0111 = External RC oscillator, port function on RA6 0110 = HS oscillator, PLL is enabled (Clock Frequency = 4 x FOSC1) 0101 = EC oscillator, CLKO function on RA6 0100 = EC oscillator, CLKO function on RA6 0011 = External RC oscillator, CLKO function on RA6 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator DS39635C-page 282  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 REGISTER 24-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — BORV1 BORV0 BOREN1(1) BOREN0(1) PWRTEN(1) bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at erase bit ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-3 BORV<1:0>: Brown-out Reset Voltage bits 11 = Minimum setting • • • 00 = Maximum setting bit 2-1 BOREN<1:0> Brown-out Reset Enable bits(1) 11 = Brown-out Reset is enabled in hardware only (SBOREN is disabled) 10 = Brown-out Reset is enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) 10 = Brown-out Reset is enabled and controlled by software (SBOREN is enabled) 10 = Brown-out Reset is disabled in hardware and software bit 0 PWRTEN: Power-up Timer Enable bit(1) 1 = PWRT is disabled 0 = PWRT is enabled Note 1: The Power-up Timer (PWRT) is decoupled from Brown-out Reset, allowing these features to be independently controlled.  2010 Microchip Technology Inc. DS39635C-page 283

PIC18F6310/6410/8310/8410 REGISTER 24-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at erase bit ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT is enabled 0 = WDT is disabled (control is placed on the SWDTEN bit) DS39635C-page 284  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 REGISTER 24-4: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h) R/P-1 R/P-1 U-0 U-0 U-0 U-0 R/P-1 R/P-1 WAIT BW — — — — PM1 PM0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at erase bit ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WAIT: External Bus Data Wait Enable bit 1 = Wait selections are unavailable, device will not wait 0 = Wait is programmed by the WAIT1 and WAIT0 bits of the MEMCOM register (MEMCOM<5:4>) bit 6 BW: External Bus Data Width Select bit 1 = 16-bit external bus data width 0 = 8-bit external bus data width bit 5-2 Unimplemented: Read as ‘0’ bit 1-0 PM<1:0>: Processor Data Memory Mode Select bits 11 = Microcontroller mode 10 = Microprocessor mode(1) 01 = Microcontroller with Boot Block mode(1) 00 = Extended Microcontroller mode(1) Note 1: This mode is only available on PIC18F8310/8410 devices.  2010 Microchip Technology Inc. DS39635C-page 285

PIC18F6310/6410/8310/8410 REGISTER 24-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U-0 U-0 U-0 U-0 R/P-0 U-0 R/P-1 MCLRE — — — — LPT1OSC — CCP2MX bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at erase bit ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin is enabled; RG5 input pin is disabled 0 = RG5 input pin is enabled; MCLR is disabled bit 6-3 Unimplemented: Read as ‘0’ bit 2 LPT1OSC: Low-Power Timer 1 Oscillator Enable bit 1 = Timer1 is configured for low-power operation 0 = Timer1 is configured for higher power operation bit 1 Unimplemented: Read as ‘0 bit 0 CCP2MX: CCP2 MUX bit In Microcontroller Mode only (all devices): 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RE7 In Microprocessor, Extended Microcontroller and Microcontroller with Boot Block Modes (PIC18F8310/8410 devices only): 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RB3 DS39635C-page 286  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 REGISTER 24-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 R/P-0 U-0 U-0 U-0 U-0 U-0 R/P-1 DEBUG XINST — — — — — STVREN bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed bit u = Unchanged from programmed state bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger is disabled, RB6 and RB7 are configured as general purpose I/O pins 0 = Background debugger is enabled, RB6 and RB7 are dedicated to In-Circuit Debug bit 6 XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode are enabled 0 = Instruction set extension and Indexed Addressing mode are disabled (Legacy mode) bit 5-1 Unimplemented: Read as ‘0 bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause a Reset 0 = Stack full/underflow will not cause a Reset REGISTER 24-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 — — — — — — — CP bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed bit u = Unchanged from programmed state bit 7-1 Unimplemented: Read as ‘0 bit 0 CP: Code Protection bit 1 = Program memory block is not code-protected 0 = Program memory block is code-protected  2010 Microchip Technology Inc. DS39635C-page 287

PIC18F6310/6410/8310/8410 REGISTER 24-8: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 — — — — — — — EBTR(2,3) bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed bit u = Unchanged from programmed state bit 7-1 Unimplemented: Read as ‘0 bit 0 EBTR: Table Read Protection bit(2,3) 1= Internal program memory block is not protected from table reads executed from external memory block 0= Internal program memory block is protected from table reads executed from external memory block Note 1: Unimplemented on PIC18F6310/6410 devices; maintain the bit set. 2: Valid for the entire internal program memory block in Extended Microcontroller mode and for only the boot block (0000h to 07FFh) in Microcontroller with Boot Block mode. This bit has no effect in Microcontroller and Microprocessor modes. 3: It is recommended to enable the CP bit to protect the block from external read operations. DS39635C-page 288  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 REGISTER 24-9: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F6310/6410/8310/8410 DEVICES R R R R R R R R DEV2(1) DEV1(1) DEV0(1) REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at erase bit ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 DEV<2:0>: Device ID bits(1) 110 = PIC18F8310, PIC18F8410 111 = PIC18F6310, PIC18F6410 bit 4-0 REV<4:0>: Revision ID bits These bits are used to indicate the device revision. Note 1: These values for DEV<2:0> may be shared with other devices. The specific device is always identified by using the entire DEV<10:0> bit sequence. REGISTER 24-10: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F6310/6410/8310/8410 DEVICES R R R R R R R R DEV10(1) DEV9(1) DEV8(1) DEV7(1) DEV6(1) DEV5(1) DEV4(1) DEV3(1) bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at erase bit ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 DEV<10:3>: Device ID bits These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number. 0000 0110 = PIC18F6410/8410 devices 0000 1011 = PIC18F6310/8310 devices Note 1: These values for DEV<10:3> may be shared with other devices. The specific device is always identified by using the entire DEV<10:0> bit sequence.  2010 Microchip Technology Inc. DS39635C-page 289

PIC18F6310/6410/8310/8410 24.2 Watchdog Timer (WDT) Note1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts For PIC18F6310/6410/8310/8410 devices, the WDT is when executed. driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal 2: Changing the setting of the IRCF bits WDT period is 4ms and has the same stability as the (OSCCON<6:4>) clears the WDT and INTRC oscillator. postscaler counts. The 4ms period of the WDT is multiplied by a 16-bit 3: When a CLRWDT instruction is executed postscaler. Any output of the WDT postscaler is the postscaler count will be cleared. selected by a multiplexer, controlled by bits in Configu- ration Register 2H. Available periods range from 4ms 24.2.1 CONTROL REGISTER to 131.072seconds (2.18 minutes). The WDT and Register24-11 shows the WDTCON register. This is a postscaler are cleared when any of the following events readable and writable register, which contains a control occur: a SLEEP or CLRWDT instruction is executed, the bit that allows software to override the WDT enable IRCF bits (OSCCON<6:4>) are changed or a clock Configuration bit, but only if the Configuration bit has failure has occurred. disabled the WDT. FIGURE 24-1: WDT BLOCK DIAGRAM SWDTEN Enable WDT INTRC Control WDTEN WDT Counter INTRC Source 128 Wake-up from Power Managed Modes Change on IRCF bits Programmable Postscaler Reset WDT CLRWDT Reset 1:1 to 1:32,768 All Device Resets WDT 4 WDTPS<3:0> Sleep DS39635C-page 290  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 REGISTER 24-11: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at erase bit ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled. TABLE 24-2: SUMMARY OF WATCHDOG TIMER REGISTERS Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page RCON IPEN SBOREN — RI TO PD POR BOR 64 WDTCON — — — — — — — SWDTEN 64 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.  2010 Microchip Technology Inc. DS39635C-page 291

PIC18F6310/6410/8310/8410 24.3 Two-Speed Start-up In all other power-managed modes, Two-Speed Start-up is not used. The device will be clocked by the currently The Two-Speed Start-up feature helps to minimize the selected clock source until the primary clock source latency period from oscillator start-up to code execution becomes available. The setting of the IESO bit is by allowing the microcontroller to use the INTRC ignored. oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO 24.3.1 SPECIAL CONSIDERATIONS FOR Configuration bit. USING TWO-SPEED START-UP Two-Speed Start-up should be enabled only if the While using the INTRC oscillator in Two-Speed primary oscillator mode is LP, XT, HS or HSPLL Start-up, the device still obeys the normal command (Crystal-Based modes). Other sources do not require a sequences for entering power-managed modes, OST start-up delay; for these, Two-Speed Start-up including serial SLEEP instructions (refer to should be disabled. Section4.1.2 “Entering Power-Managed Modes”). When enabled, Resets and wake-ups from Sleep mode In practice, this means that user code can change cause the device to configure itself to run from the inter- the SCS<1:0> bits setting or issue SLEEP nal oscillator block as the clock source, following the instructions before the OST times out. This would time-out of the Power-up Timer after a Power-on Reset allow an application to briefly wake-up, perform is enabled. This allows almost immediate code routine “housekeeping” tasks and return to Sleep execution while the primary oscillator starts and the before the device starts to operate from the primary OST is running. Once the OST times out, the device oscillator. automatically switches to PRI_RUN mode. User code can also check if the primary clock source is To use a higher clock speed on wake-up, the INTOSC or currently providing the device clocking by checking the postscaler clock sources can be selected to provide a status of the OSTS bit (OSCCON<3>). If the bit is set, higher clock speed by setting bits, IRCF<2:0>, immedi- the primary oscillator is providing the clock. Otherwise, ately after Reset. For wake-ups from Sleep, the INTOSC the internal oscillator block is providing the clock during or postscaler clock sources can be selected by setting wake-up from Reset or Sleep mode. the IRCF<2:0> bits prior to entering Sleep mode. FIGURE 24-2: TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 2 n-1 n PLL Clock Output Clock Transition CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 PC + 6 Counter Wake from Interrupt Event OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2ms (approx). These intervals are not shown to scale. DS39635C-page 292  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 24.4 Fail-Safe Clock Monitor To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide The Fail-Safe Clock Monitor (FSCM) allows the a higher clock speed by setting bits, IRCF<2:0>, imme- microcontroller to continue operation in the event of an diately after Reset. For wake-ups from Sleep, the external oscillator failure by automatically switching the INTOSC or postscaler clock sources can be selected device clock to the internal oscillator block. The FSCM by setting the IRCF<2:0> bits prior to entering Sleep function is enabled by setting the FCMEN mode. Configuration bit. The FSCM will detect failures of the primary or second- When FSCM is enabled, the INTRC oscillator runs at ary clock sources only. If the internal oscillator block all times to monitor clocks to peripherals and provide a fails, no failure would be detected, nor would any action backup clock in the event of a clock failure. Clock be possible. monitoring (shown in Figure24-3) is accomplished by creating a sample clock signal, which is the INTRC 24.4.1 FSCM AND THE WATCHDOG TIMER output divided by 64. This allows ample time between Both the FSCM and the WDT are clocked by the FSCM sample clocks for a peripheral clock edge to INTRC oscillator. Since the WDT operates with a occur. The peripheral device clock and the sample separate divider and counter, disabling the WDT has clock are presented as inputs to the Clock Monitor latch no effect on the operation of the INTRC oscillator when (CM). The CM is set on the falling edge of the device the FSCM is enabled. clock source, but cleared on the rising edge of the sample clock. As already noted, the clock source is switched to the INTOSC clock when a clock failure is detected. FIGURE 24-3: FSCM BLOCK DIAGRAM Depending on the frequency selected by the IRCF<2:0> bits, this may mean a substantial change in Clock Monitor (CM) the speed of code execution. If the WDT is enabled Latch with a small prescale value, a decrease in clock speed (edge-triggered) Peripheral allows a WDT time-out to occur and a subsequent S Q Clock device Reset. For this reason, Fail-Safe Clock events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed, and INTRC decreasing the likelihood of an erroneous time-out. ÷ 64 C Q Source 24.4.2 EXITING FAIL-SAFE OPERATION (32 s) 488 Hz (2.048 ms) The Fail-Safe condition is terminated by either a device Reset or by entering a power-managed mode. On Clock Reset, the controller starts the primary clock source Failure specified in Configuration Register 1H (with any Detected required start-up delays that are required for the oscillator mode, such as the OST or PLL timer). The Clock failure is tested for on the falling edge of the INTOSC multiplexer provides the device clock until the sample clock. If a sample clock falling edge occurs primary clock source becomes ready (similar to a while CM is still set, a clock failure has been detected Two-Speed Start-up). The clock source is then (Figure24-4). This causes the following: switched to the primary clock (indicated by the OSTS • the FSCM generates an oscillator fail interrupt by bit in the OSCCON register becoming set). The setting bit, OSCFIF (PIR2<7>); Fail-Safe Clock Monitor then resumes monitoring the • the device clock source is switched to the internal peripheral clock. oscillator block (OSCCON is not updated to show The primary clock source may never become ready the current clock source – this is the Fail-Safe during start-up. In this case, operation is clocked by the condition); and INTOSC multiplexer. The OSCCON register will remain • the WDT is reset. in its Reset state until a power-managed mode is During switchover, the postscaler frequency from the entered. internal oscillator block may not be sufficiently stable for timing-sensitive applications. In these cases, it may be desirable to select another clock configuration and enter an alternate power-managed mode. This can be done to attempt a partial recovery or execute a controlled shut- down. See Section4.1.2 “Entering Power-Managed Modes” and Section24.3.1 “Special Considerations for Using Two-Speed Start-up” for more details.  2010 Microchip Technology Inc. DS39635C-page 293

PIC18F6310/6410/8310/8410 FIGURE 24-4: FSCM TIMING DIAGRAM Sample Clock Device Oscillator Clock Failure Output CM Output (Q) Failure Detected OSCFIF CM Test CM Test CM Test Note: The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 24.4.3 FSCM INTERRUPTS IN 24.4.4 POR OR WAKE FROM SLEEP POWER-MANAGED MODES The FSCM is designed to detect oscillator failure at any By entering a power-managed mode, the clock point after the device has exited Power-on Reset multiplexer selects the clock source selected by the (POR) or low-power Sleep mode. When the primary OSCCON register. Fail-Safe Clock monitoring of the device clock is in EC, RC or INTRC modes, monitoring power-managed clock source resumes in the can begin immediately following these events. power-managed mode. For oscillator modes involving a crystal or resonator If an oscillator failure occurs during power-managed (HS, HSPLL, LP or XT), the situation is somewhat operation, the subsequent events depend on whether different. Since the oscillator may require a start-up or not the oscillator failure interrupt is enabled. If time considerably longer than the FCSM sample clock enabled (OSCFIF=1), code execution will be clocked time, a false clock failure may be detected. To prevent by the INTOSC multiplexer. An automatic transition this, the internal oscillator block is automatically config- back to the failed clock source will not occur. ured as the device clock and functions until the primary clock is stable (the OST and PLL timers have timed If the interrupt is disabled, the device will not exit the out). This is identical to Two-Speed Start-up mode. power-managed mode on oscillator failure. Instead, the Once the primary clock is stable, the INTRC returns to device will continue to operate as before, but clocked its role as the FSCM source. by the INTOSC multiplexer. While in Idle mode, subse- quent interrupts will cause the CPU to begin executing Note: The same logic that prevents false instructions while being clocked by the INTOSC oscillator failure interrupts on POR, or multiplexer. wake from Sleep, will also prevent the detection of the oscillator’s failure to start at all following these events. This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start. Even so, no oscillator failure interrupt will be flagged. As noted in Section24.3.1 “Special Considerations for Using Two-Speed Start-up”, it is also possible to select another clock configuration and enter an alternate power-managed mode while waiting for the primary clock to become stable. When the new powered-managed mode is selected, the primary clock is disabled. DS39635C-page 294  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 24.5 Program Verification and EBTR (CONFIG7L<0>), is used to protect the on-chip Code Protection program memory space from this possibility. Setting EBTR prevents table read commands from executing The overall structure of the code protection on the on any address in the on-chip program memory space. PIC18F6310/6410/8310/8410 Flash devices differs EBTR is implemented only on devices with the external from previous PIC18 devices. memory interface. Its operation also depends on the For all devices in the PIC18FX310/X410 family, the particular mode of operation selected. In Extended user program memory is made of a single block. Microcontroller mode, programming EBTR enables Figure24-5 shows the program memory organization protection from external table reads for the entire for individual devices. Code protection for this block is program memory. In Microcontroller with Boot Block controlled by a single bit, CP (CONFIG5L<0>). The CP mode, only the first 2 Kbytes of on-chip memory (000h bit inhibits external reads and writes; it has no direct to 7FFh) are protected. This is because, only this range effect in normal execution mode. of internal program memory is accessible by the microcontroller in this operating mode. 24.5.1 CODE PROTECTION FROM When the device is in Micrcontroller or Microprocessor EXTERNAL TABLE READS modes, EBTR has no effect on code protection. The program memory may be read to any location using the table read instructions. The Device ID and the 24.5.2 CONFIGURATION REGISTER Configuration registers may be read with the table read PROTECTION instructions. The Configuration registers can only be written via For devices with the external memory interface, it is ICSP using an external programmer. No separate possible to execute a table read from an external protection bit is associated with them. program memory space and read the contents of the on-chip memory. An additional code protection bit, FIGURE 24-5: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F6310/6410/8310/8410 MEMORY SIZE/DEVICE Block Code Protection 8Kbytes Address 16Kbytes Address Controlled By: (PIC18F6310/8310) Range (PIC18F6410/8410) Range Program memory 000000h Program memory 000000h CP, EBTR Block 001FFFh Block 003FFFh 002000h 004000h Unimplemented Unimplemented Read ‘0’s Read ‘0’s (Unimplemented Memory Space) 1FFFFFh 1FFFFFh TABLE 24-3: SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L — — — — — — — CP 30000Ch CONFIG7L* — — — — — — — EBTR Legend: Shaded cells are unimplemented. * Unimplemented in PIC18F6310/8310 devices; maintain this bit set.  2010 Microchip Technology Inc. DS39635C-page 295

PIC18F6310/6410/8310/8410 24.6 ID Locations 24.8 In-Circuit Debugger Eight memory locations (200000h-200007h) are When the DEBUG Configuration bit is programmed to designated as ID locations, where the user can store a ‘0’, the In-Circuit Debugger functionality is enabled. checksum or other code identification numbers. These This function allows simple debugging functions when locations are readable during normal execution through used with MPLAB® IDE. When the microcontroller has the TBLRD instruction. During program/verify, these this feature enabled, some resources are not available locations are readable and writable. The ID locations for general use. Table24-4 shows which resources are can be read when the device is code-protected. required by the background debugger. 24.7 In-Circuit Serial Programming TABLE 24-4: DEBUGGER RESOURCES I/O Pins: RB6, RB7 PIC18F6310/6410/8310/8410 microcontrollers can be serially programmed while in the end application circuit. Stack: 2 levels This is simply done with two lines for clock and data, Program Memory: <1 Kbyte and three other lines for power, ground and the Data Memory: <16 bytes programming voltage. This allows customers to manu- facture boards with unprogrammed devices and then To use the In-Circuit Debugger function of the micro- program the microcontroller just before shipping the controller, the design must implement In-Circuit Serial product. This also allows the most recent firmware or a Programming connections to MCLR/VPP, VDD, VSS, custom firmware to be programmed. RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip or one of the third party development tool companies. DS39635C-page 296  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 25.0 INSTRUCTION SET SUMMARY The literal instructions may use some of the following operands: PIC18F6310/6410/8310/8410 devices incorporate the • A literal value to be loaded into a file register standard set of 75 PIC18 core instructions, as well as (specified by ‘k’) an extended set of 8 new instructions for the optimiza- tion of code that is recursive or that utilizes a software • The desired FSR register to load the literal value stack. The extended set is discussed later in this into (specified by ‘f’) section. • No operand required (specified by ‘—’) 25.1 Standard Instruction Set The control instructions may use some of the following operands: The standard PIC18 instruction set adds many enhancements to the previous PIC® device instruction • A program memory address (specified by ‘n’) sets, while maintaining an easy migration from these • The mode of the call or return instructions PIC device instruction sets. Most instructions are a (specified by ‘s’) single program memory word (16 bits), but there are • The mode of the table read and table write four instructions that require two program memory instructions (specified by ‘m’) locations. • No operand required Each single-word instruction is a 16-bit word divided (specified by ‘—’) into an opcode, which specifies the instruction type and All instructions are a single word, except for four one or more operands, which further specify the double-word instructions. These instructions were operation of the instruction. made double-word to contain the required information The instruction set is highly orthogonal and is grouped in 32 bits. In the second word, the 4 MSbs are ‘1’s. If into four basic categories: this second word is executed as an instruction (by itself), it will execute as a NOP. • Byte-oriented operations • Bit-oriented operations All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the • Literal operations program counter is changed as a result of the instruc- • Control operations tion. In these cases, the execution takes two instruction The PIC18 instruction set summary in Table25-2 lists cycles with the additional instruction cycle(s) executed byte-oriented, bit-oriented, literal and control as a NOP. operations. Table25-1 shows the opcode field The double-word instructions execute in two instruction descriptions. cycles. Most byte-oriented instructions have three operands: One instruction cycle consists of four oscillator periods. 1. The file register (specified by ‘f’) Thus, for an oscillator frequency of 4MHz, the normal 2. The destination of the result (specified by ‘d’) instruction execution time is 1s. If a conditional test is 3. The accessed memory (specified by ‘a’) true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. The file register designator, ‘f’, specifies which file Two-word branch instructions (if true) would take 3 s. register is to be used by the instruction. The destination Figure25-1 shows the general formats that the instruc- designator, ‘d’, specifies where the result of the tions can have. All examples use the convention ‘nnh’ operation is to be placed. If ‘d’ is zero, the result is to represent a hexadecimal number. placed in the WREG register. If ‘d’ is one, the result is placed in the file register specified in the instruction. The Instruction Set Summary, shown in Table25-2, lists the standard instructions recognized by the All bit-oriented instructions have three operands: Microchip Assembler (MPASM™). 1. The file register (specified by ‘f’) Section25.1.1 “Standard Instruction Set” provides 2. The bit in the file register (specified by ‘b’) a description of each instruction. 3. The accessed memory (specified by ‘a’) The bit field designator, ‘b’, selects the number of the bit affected by the operation, while the file register desig- nator, ‘f’, represents the number of the file in which the bit is located.  2010 Microchip Technology Inc. DS39635C-page 297

PIC18F6310/6410/8310/8410 TABLE 25-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. d Destination select bit d = 0: store result in WREG d = 1: store result in file register f. dest Destination: either the WREG register or the specified register file location. f 8-bit register file address (00h to FFh), or 2-bit FSR designator (0h to 3h). f 12-bit register file address (000h to FFFh). This is the source address. s f 12-bit register file address (000h to FFFh). This is the destination address. d GIE Global interrupt enable bit. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No change to register (such as TBLPTR with table reads and writes). *+ Post-Increment register (such as TBLPTR with table reads and writes). *- Post-Decrement register (such as TBLPTR with table reads and writes). +* Pre-Increment register (such as TBLPTR with table reads and writes). n The relative address (2’s complement number) for relative branch instructions, or the direct address for call/branch and return instructions. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. PD Power-Down bit. PRODH Product of Multiply high byte. PRODL Product of Multiply low byte. s Fast Call/Return mode select bit s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) TBLPTR 21-bit Table Pointer (points to a program memory location). TABLAT 8-bit Table Latch. TO Time-out bit. TOS Top-of-Stack. u Unused or Unchanged. WDT Watchdog Timer. WREG Working register (accumulator). x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. z 7-bit offset value for indirect addressing of register files (source). s z 7-bit offset value for indirect addressing of register files (destination). d { } Optional argument. [text] Indicates an indexed address. (text) The contents of text. [expr]<n> Specifies bit n of the register indicated by the pointer expr.  Assigned to. < > Register bit field.  In the set of. italics User-defined term (font is Courier New). DS39635C-page 298  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 25-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations Example Instruction 15 10 9 8 7 0 OPCODE d a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2 15 12 11 0 1111 f (Destination FILE #) f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 0 OPCODE k (literal) MOVLW 7Fh k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 0 OPCODE n<7:0> (literal) GOTO Label 15 12 11 0 1111 n<19:8> (literal) n = 20-bit immediate value 15 8 7 0 OPCODE S n<7:0> (literal) CALL MYFUNC 15 12 11 0 1111 n<19:8> (literal) S = Fast bit 15 11 10 0 OPCODE n<10:0> (literal) BRA MYFUNC 15 8 7 0 OPCODE n<7:0> (literal) BC MYFUNC  2010 Microchip Technology Inc. DS39635C-page 299

PIC18F6310/6410/8310/8410 TABLE 25-2: PIC18FXXXX INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED OPERATIONS ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2 CLRF f, a Clear f 1 0110 101a ffff ffff Z 2 COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2 CPFSEQ f, a Compare f with WREG, Skip = 1 (2 or 3) 0110 001a ffff ffff None 4 CPFSGT f, a Compare f with WREG, Skip > 1 (2 or 3) 0110 010a ffff ffff None 4 CPFSLT f, a Compare f with WREG, Skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2 DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4 DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2 INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4 INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2 IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2 MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1 MOVFF fs, fd Movefs (source) to 1st word 2 1100 ffff ffff ffff None fd (destination) 2nd word 1111 ffff ffff ffff MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2 NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2 RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N SETF f, a Set f 1 0110 100a ffff ffff None 1, 2 SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N Borrow SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2 SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N Borrow SWAPF f, d, a Swap Nibbles in f 1 0011 10da ffff ffff None 4 TSTFSZ f, a Test f, Skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2 XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: Table write instructions are unavailable in 64-pin devices in normal operating modes. See Section7.4 “Writing to Program Memory Space (PIC18F8310/8410 only)” and Section7.6 “Writing and Erasing On-Chip Program Memory (ICSP Mode)” for more information. DS39635C-page 300  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 25-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BIT-ORIENTED OPERATIONS BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2 BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2 BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4 BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4 BTG f, d, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2 CONTROL OPERATIONS BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None CALL n, s Call Subroutine1st word 2 1110 110s kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C GOTO n Go to Address 1st word 2 1110 1111 kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk NOP — No Operation 1 0000 0000 0000 0000 None NOP — No Operation 1 1111 xxxx xxxx xxxx None 4 POP — Pop Top of Return Stack (TOS) 1 0000 0000 0000 0110 None PUSH — Push Top of Return Stack (TOS) 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 1nnn nnnn nnnn None RESET Software Device Reset 1 0000 0000 1111 1111 All RETFIE s Return from Interrupt Enable 2 0000 0000 0001 000s GIE/GIEH, PEIE/GIEL RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: Table write instructions are unavailable in 64-pin devices in normal operating modes. See Section7.4 “Writing to Program Memory Space (PIC18F8310/8410 only)” and Section7.6 “Writing and Erasing On-Chip Program Memory (ICSP Mode)” for more information.  2010 Microchip Technology Inc. DS39635C-page 301

PIC18F6310/6410/8310/8410 TABLE 25-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb LITERAL OPERATIONS ADDLW k Add Literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND Literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR Literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move Literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None to FSR(f) 1st word 1111 0000 kkkk kkkk MOVLB k Move Literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move Literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply Literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from Literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR Literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY  PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with Post-Increment 0000 0000 0000 1001 None TBLRD*- Table Read with Post-Decrement 0000 0000 0000 1010 None TBLRD+* Table Read with Pre-Increment 0000 0000 0000 1011 None TBLWT* Table Write 2 0000 0000 0000 1100 None 5 TBLWT*+ Table Write with Post-Increment 0000 0000 0000 1101 None 5 TBLWT*- Table Write with Post-Decrement 0000 0000 0000 1110 None 5 TBLWT+* Table Write with Pre-Increment 0000 0000 0000 1111 None 5 Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 5: Table write instructions are unavailable in 64-pin devices in normal operating modes. See Section7.4 “Writing to Program Memory Space (PIC18F8310/8410 only)” and Section7.6 “Writing and Erasing On-Chip Program Memory (ICSP Mode)” for more information. Note: All PIC18 instructions may take an optional label argument, preceding the instruction mnemonic, for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s) DS39635C-page 302  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 25.1.1 STANDARD INSTRUCTION SET ADDLW ADD literal to W ADDWF ADD W to f Syntax: ADDLW k Syntax: ADDWF f {,d {,a}} Operands: 0  k  255 Operands: 0  f  255 d  [0,1] Operation: (W) + k  W a  [0,1] Status Affected: N, OV, C, DC, Z Operation: (W) + (f)  dest Encoding: 0000 1111 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: The contents of W are added to the Encoding: 0010 01da ffff ffff 8-bit literal ‘k’ and the result is placed in W. Description: Add W to register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the Words: 1 result is stored back in register ‘f’. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. Q Cycle Activity: If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode Read Process Write to W set is enabled, this instruction operates literal ‘k’ Data in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section25.2.3 for details. Example: ADDLW 15h Words: 1 Before Instruction Cycles: 1 W = 10h After Instruction Q Cycle Activity: W = 25h Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWF REG, 0, 0 Before Instruction W = 17h REG = 0C2h After Instruction W = 0D9h REG = 0C2h  2010 Microchip Technology Inc. DS39635C-page 303

PIC18F6310/6410/8310/8410 ADDWFC ADD W and Carry bit to f ANDLW AND literal with W Syntax: ADDWFC f {,d {,a}} Syntax: ANDLW k Operands: 0  f  255 Operands: 0  k  255 d [0,1] Operation: (W) .AND. k  W a [0,1] Status Affected: N, Z Operation: (W) + (f) + (C)  dest Encoding: 0000 1011 kkkk kkkk Status Affected: N,OV, C, DC, Z Description: The contents of W are ANDed with the Encoding: 0010 00da ffff ffff 8-bit literal ‘k’. The result is placed in W. Description: Add W, the Carry flag and data memory Words: 1 location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is Cycles: 1 placed in data memory location ‘f’. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Decode Read literal Process Write to W If ‘a’ is ‘0’ and the extended instruction ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: ANDLW 05Fh mode whenever f 95 (5Fh). See Section25.2.3 for details. Before Instruction W = A3h Words: 1 After Instruction Cycles: 1 W = 03h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWFC REG, 0, 1 Before Instruction Carry bit = 1 REG = 02h W = 4Dh After Instruction Carry bit = 0 REG = 02h W = 50h DS39635C-page 304  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 ANDWF AND W with f BC Branch if Carry Syntax: ANDWF f {,d {,a}} Syntax: BC n Operands: 0  f  255 Operands: -128  n  127 d [0,1] Operation: if Carry bit is ‘1’, a [0,1] (PC) + 2 + 2n  PC Operation: (W) .AND. (f)  dest Status Affected: None Status Affected: N, Z Encoding: 1110 0010 nnnn nnnn Encoding: 0001 01da ffff ffff Description: If the Carry bit is ‘1’, then the program Description: The contents of W are AND’ed with will branch. register ‘f’. If ‘d’ is ‘0’, the result is stored The 2’s complement number ‘2n’ is in W. If ‘d’ is ‘1’, the result is stored back added to the PC. Since the PC will have in register ‘f’. incremented to fetch the next If ‘a’ is ‘0’, the Access Bank is selected. instruction, the new address will be If ‘a’ is ‘1’, the BSR is used to select the PC + 2 + 2n. This instruction is then a GPR bank. two-cycle instruction. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f 95 (5Fh). See Q Cycle Activity: Section25.2.3 for details. If Jump: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to PC ‘n’ Data Q Cycle Activity: No No No No Q1 Q2 Q3 Q4 operation operation operation operation Decode Read Process Write to If No Jump: register ‘f’ Data destination Q1 Q2 Q3 Q4 Decode Read literal Process No Example: ANDWF REG, 0, 0 ‘n’ Data operation Before Instruction W = 17h Example: HERE BC 5 REG = C2h Before Instruction After Instruction PC = address (HERE) W = 02h After Instruction REG = C2h If Carry = 1; PC = address (HERE + 12) If Carry = 0; PC = address (HERE + 2)  2010 Microchip Technology Inc. DS39635C-page 305

PIC18F6310/6410/8310/8410 BCF Bit Clear f BN Branch if Negative Syntax: BCF f, b {,a} Syntax: BN n Operands: 0  f  255 Operands: -128  n  127 0  b  7 Operation: if Negative bit is ‘1’, a [0,1] (PC) + 2 + 2n  PC Operation: 0  f<b> Status Affected: None Status Affected: None Encoding: 1110 0110 nnnn nnnn Encoding: 1001 bbba ffff ffff Description: If the Negative bit is ‘1’, then the Description: Bit ‘b’ in register ‘f’ is cleared. program will branch. If ‘a’ is ‘0’, the Access Bank is selected. The 2’s complement number ‘2n’ is If ‘a’ is ‘1’, the BSR is used to select the added to the PC. Since the PC will have GPR bank. incremented to fetch the next If ‘a’ is ‘0’ and the extended instruction instruction, the new address will be set is enabled, this instruction operates PC + 2 + 2n. This instruction is then a in Indexed Literal Offset Addressing two-cycle instruction. mode whenever f 95 (5Fh). See Words: 1 Section25.2.3 for details. Cycles: 1(2) Words: 1 Q Cycle Activity: Cycles: 1 If Jump: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read Process Write ‘n’ Data register ‘f’ Data register ‘f’ No No No No operation operation operation operation Example: BCF FLAG_REG, 7, 0 If No Jump: Q1 Q2 Q3 Q4 Before Instruction FLAG_REG = C7h Decode Read literal Process No After Instruction ‘n’ Data operation FLAG_REG = 47h Example: HERE BN Jump Before Instruction PC = address (HERE) After Instruction If Negative = 1; PC = address (Jump) If Negative = 0; PC = address (HERE + 2) DS39635C-page 306  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC n Syntax: BNN n Operands: -128  n  127 Operands: -128  n  127 Operation: if Carry bit is ‘0’, Operation: if Negative bit is ‘0’, (PC) + 2 + 2n  PC (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn Description: If the Carry bit is ‘0’, then the program Description: If the Negative bit is ‘0’, then the will branch. program will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to Decode Read literal Process Write to ‘n’ Data PC ‘n’ Data PC No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNC Jump Example: HERE BNN Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Carry = 0; If Negative = 0; PC = address (Jump) PC = address (Jump) If Carry = 1; If Negative = 1; PC = address (HERE + 2) PC = address (HERE + 2)  2010 Microchip Technology Inc. DS39635C-page 307

PIC18F6310/6410/8310/8410 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV n Syntax: BNZ n Operands: -128  n  127 Operands: -128  n  127 Operation: if Overflow bit is ‘0’, Operation: if Zero bit is ‘0’, (PC) + 2 + 2n  PC (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn Description: If the Overflow bit is ‘0’, then the Description: If the Zero bit is ‘0’, then the program program will branch. will branch. The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC ‘n’ Data ‘n’ Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNOV Jump Example: HERE BNZ Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Overflow = 0; If Zero = 0; PC = address (Jump) PC = address (Jump) If Overflow = 1; If Zero = 1; PC = address (HERE + 2) PC = address (HERE + 2) DS39635C-page 308  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 BRA Unconditional Branch BSF Bit Set f Syntax: BRA n Syntax: BSF f, b {,a} Operands: -1024  n  1023 Operands: 0  f  255 0  b  7 Operation: (PC) + 2 + 2n  PC a [0,1] Status Affected: None Operation: 1  f<b> Encoding: 1101 0nnn nnnn nnnn Status Affected: None Description: Add the 2’s complement number ‘2n’ to Encoding: 1000 bbba ffff ffff the PC. Since the PC will have incremented to fetch the next Description: Bit ‘b’ in register ‘f’ is set. instruction, the new address will be If ‘a’ is ‘0’, the Access Bank is selected. PC + 2 + 2n. This instruction is a If ‘a’ is ‘1’, the BSR is used to select the two-cycle instruction. GPR bank. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates Cycles: 2 in Indexed Literal Offset Addressing Q Cycle Activity: mode whenever f 95 (5Fh). See Section25.2.3 for details. Q1 Q2 Q3 Q4 Words: 1 Decode Read literal Process Write to ‘n’ Data PC Cycles: 1 No No No No Q Cycle Activity: operation operation operation operation Q1 Q2 Q3 Q4 Decode Read Process Write Example: HERE BRA Jump register ‘f’ Data register ‘f’ Before Instruction PC = address (HERE) Example: BSF FLAG_REG, 7, 1 After Instruction Before Instruction PC = address (Jump) FLAG_REG = 0Ah After Instruction FLAG_REG = 8Ah  2010 Microchip Technology Inc. DS39635C-page 309

PIC18F6310/6410/8310/8410 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0  f  255 Operands: 0  f  255 0  b  7 0  b < 7 a [0,1] a [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped. If bit ‘b’ is ‘0’, then instruction is skipped. If bit ‘b’ is ‘1’, then the next instruction fetched during the the next instruction fetched during the current instruction execution is discarded current instruction execution is discarded and a NOP is executed instead, making and a NOP is executed instead, making this a two-cycle instruction. this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the ‘a’ is ‘1’, the BSR is used to select the GPR bank . GPR bank. If ‘a’ is ‘0’ and the extended instruction set If ‘a’ is ‘0’ and the extended instruction is enabled, this instruction operates in set is enabled, this instruction operates in Indexed Literal Offset Addressing mode Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See whenever f 95 (5Fh). See Section25.2.3 for details. Section25.2.3 for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process No Decode Read Process No register ‘f’ Data operation register ‘f’ Data operation If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE BTFSC FLAG, 1, 0 Example: HERE BTFSS FLAG, 1, 0 FALSE : FALSE : TRUE : TRUE : Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If FLAG<1> = 0; If FLAG<1> = 0; PC = address (TRUE) PC = address (FALSE) If FLAG<1> = 1; If FLAG<1> = 1; PC = address (FALSE) PC = address (TRUE) DS39635C-page 310  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV n Operands: 0  f  255 Operands: -128  n  127 0  b < 7 Operation: if Overflow bit is ‘1’, a [0,1] (PC) + 2 + 2n  PC Operation: (f<b>)  f<b> Status Affected: None Status Affected: None Encoding: 1110 0100 nnnn nnnn Encoding: 0111 bbba ffff ffff Description: If the Overflow bit is ‘1’, then the Description: Bit ‘b’ in data memory location ‘f’ is program will branch. inverted. The 2’s complement number ‘2n’ is If ‘a’ is ‘0’, the Access Bank is selected. added to the PC. Since the PC will have If ‘a’ is ‘1’, the BSR is used to select the incremented to fetch the next GPR bank. instruction, the new address will be If ‘a’ is ‘0’ and the extended instruction PC + 2 + 2n. This instruction is then a set is enabled, this instruction operates two-cycle instruction. in Indexed Literal Offset Addressing Words: 1 mode whenever f 95 (5Fh). See Section25.2.3 for details. Cycles: 1(2) Words: 1 Q Cycle Activity: If Jump: Cycles: 1 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read literal Process Write to Q1 Q2 Q3 Q4 ‘n’ Data PC Decode Read Process Write No No No No register ‘f’ Data register ‘f’ operation operation operation operation If No Jump: Example: BTG PORTC, 4, 0 Q1 Q2 Q3 Q4 Before Instruction: Decode Read literal Process No PORTC = 0111 0101 [75h] ‘n’ Data operation After Instruction: PORTC = 0110 0101 [65h] Example: HERE BOV Jump Before Instruction PC = address (HERE) After Instruction If Overflow = 1; PC = address (Jump) If Overflow = 0; PC = address (HERE + 2)  2010 Microchip Technology Inc. DS39635C-page 311

PIC18F6310/6410/8310/8410 BZ Branch if Zero CALL Subroutine Call Syntax: BZ n Syntax: CALL k {,s} Operands: -128  n  127 Operands: 0  k  1048575 s [0,1] Operation: if Zero bit is ‘1’, (PC) + 2 + 2n  PC Operation: (PC) + 4  TOS, k  PC<20:1>, Status Affected: None if s = 1 Encoding: 1110 0000 nnnn nnnn (W)  WS, Description: If the Zero bit is ‘1’, then the program (STATUS)  STATUSS, will branch. (BSR)  BSRS The 2’s complement number ‘2n’ is Status Affected: None added to the PC. Since the PC will have Encoding: incremented to fetch the next 1st word (k<7:0>) 1110 110s k kkk kkkk instruction, the new address will be 7 0 2nd word(k<19:8>) 1111 k kkk kkkk kkkk PC + 2 + 2n. This instruction is then a 19 8 two-cycle instruction. Description: Subroutine call of entire 2-Mbyte memory range. First, return address Words: 1 (PC + 4) is pushed onto the return Cycles: 1(2) stack. If ‘s’ = 1, the W, STATUS and Q Cycle Activity: BSR registers are also pushed into their If Jump: respective shadow registers, WS, STATUSS and BSRS. If ‘s’ = 0, no Q1 Q2 Q3 Q4 update occurs. Then, the 20-bit value ‘k’ Decode Read literal Process Write to is loaded into PC<20:1>. CALL is a ‘n’ Data PC two-cycle instruction. No No No No Words: 2 operation operation operation operation If No Jump: Cycles: 2 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read literal Process No Q1 Q2 Q3 Q4 ‘n’ Data operation Decode Read literal Push PC to Read literal ‘k’<7:0>, stack ’k’<19:8>, Example: HERE BZ Jump Write to PC No No No No Before Instruction operation operation operation operation PC = address (HERE) After Instruction If Zero = 1; Example: HERE CALL THERE,1 PC = address (Jump) If Zero = 0; Before Instruction PC = address (HERE + 2) PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 4) WS = W BSRS = BSR STATUSS= STATUS DS39635C-page 312  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 CLRF Clear f CLRWDT Clear Watchdog Timer Syntax: CLRF f {,a} Syntax: CLRWDT Operands: 0  f  255 Operands: None a [0,1] Operation: 000h  WDT, Operation: 000h  f, 000h  WDT postscaler, 1  Z 1  TO, 1  PD Status Affected: Z Status Affected: TO, PD Encoding: 0110 101a ffff ffff Encoding: 0000 0000 0000 0100 Description: Clears the contents of the specified register. Description: CLRWDT instruction resets the If ‘a’ is ‘0’, the Access Bank is selected. Watchdog Timer. It also resets the post- If ‘a’ is ‘1’, the BSR is used to select the scaler of the WDT. Status bits, TO and GPR bank. PD, are set. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates in Indexed Literal Offset Addressing Cycles: 1 mode whenever f 95 (5Fh). See Q Cycle Activity: Section25.2.3 for details. Q1 Q2 Q3 Q4 Words: 1 Decode No Process No Cycles: 1 operation Data operation Q Cycle Activity: Q1 Q2 Q3 Q4 Example: CLRWDT Decode Read Process Write Before Instruction register ‘f’ Data register ‘f’ WDT Counter = ? After Instruction WDT Counter = 00h Example: CLRF FLAG_REG,1 WDT Postscaler = 0 Before Instruction TO = 1 FLAG_REG = 5Ah PD = 1 After Instruction FLAG_REG = 00h  2010 Microchip Technology Inc. DS39635C-page 313

PIC18F6310/6410/8310/8410 COMF Complement f CPFSEQ Compare f with W, skip if f = W Syntax: COMF f {,d {,a}} Syntax: CPFSEQ f {,a} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] a  [0,1] a  [0,1] Operation: (f) – (W), skip if (f) = (W) Operation: (f)  dest (unsigned comparison) Status Affected: N, Z Status Affected: None Encoding: 0001 11da ffff ffff Encoding: 0110 001a ffff ffff Description: The contents of register ‘f’ are Description: Compares the contents of data memory complemented. If ‘d’ is ‘0’, the result is location ‘f’ to the contents of W by stored in W. If ‘d’ is ‘1’, the result is performing an unsigned subtraction. stored back in register ‘f’. If ‘f’ = W, then the fetched instruction is If ‘a’ is ‘0’, the Access Bank is selected. discarded and a NOP is executed If ‘a’ is ‘1’, the BSR is used to select the instead, making this a two-cycle GPR bank. instruction. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank is selected. set is enabled, this instruction operates If ‘a’ is ‘1’, the BSR is used to select the in Indexed Literal Offset Addressing GPR bank. mode whenever f 95 (5Fh). See If ‘a’ is ‘0’ and the extended instruction Section25.2.3 for details. set is enabled, this instruction operates Words: 1 in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Cycles: 1 Section25.2.3 for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1(2) Decode Read Process Write to Note: 3 cycles if skip and followed register ‘f’ Data destination by a 2-word instruction. Q Cycle Activity: Example: COMF REG, 0, 0 Q1 Q2 Q3 Q4 Before Instruction Decode Read Process No REG = 13h register ‘f’ Data operation After Instruction If skip: REG = 13h Q1 Q2 Q3 Q4 W = ECh No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE CPFSEQ REG, 0 NEQUAL : EQUAL : Before Instruction PC Address = HERE W = ? REG = ? After Instruction If REG = W; PC = Address (EQUAL) If REG  W; PC = Address (NEQUAL) DS39635C-page 314  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 CPFSGT Compare f with W, skip if f > W CPFSLT Compare f with W, skip if f < W Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a} Operands: 0  f  255 Operands: 0  f  255 a  [0,1] a  [0,1] Operation: (f) W), Operation: (f) –W), skip if (f) > (W) skip if (f) < (W) (unsigned comparison) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 010a ffff ffff Encoding: 0110 000a ffff ffff Description: Compares the contents of data memory Description: Compares the contents of data memory location ‘f’ to the contents of the W by location ‘f’ to the contents of W by performing an unsigned subtraction. performing an unsigned subtraction. If the contents of ‘f’ are greater than the contents of WREG, then the fetched If the contents of ‘f’ are less than the instruction is discarded and a NOP is contents of W, then the fetched executed instead, making this a instruction is discarded and a NOP is two-cycle instruction. executed instead, making this a If ‘a’ is ‘0’, the Access Bank is selected. two-cycle instruction. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’ and the extended instruction GPR bank. set is enabled, this instruction operates Words: 1 in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f 95 (5Fh). See Note:3 cycles if skip and followed Section25.2.3 for details. by a 2-word instruction. Words: 1 Q Cycle Activity: Cycles: 1(2) Q1 Q2 Q3 Q4 Note: 3 cycles if skip and followed by a 2-word instruction. Decode Read Process No register ‘f’ Data operation Q Cycle Activity: If skip: Q1 Q2 Q3 Q4 Decode Read Process No Q1 Q2 Q3 Q4 register ‘f’ Data operation No No No No If skip: operation operation operation operation Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No Example: HERE CPFSLT REG, 1 operation operation operation operation NLESS : LESS : Example: HERE CPFSGT REG, 0 Before Instruction NGREATER : GREATER : PC = Address (HERE) W = ? Before Instruction After Instruction PC = Address (HERE) If REG < W; W = ? PC = Address (LESS) After Instruction If REG  W; If REG  W; PC = Address (NLESS) PC = Address (GREATER) If REG  W; PC = Address (NGREATER)  2010 Microchip Technology Inc. DS39635C-page 315

PIC18F6310/6410/8310/8410 DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: 0  f  255 d  [0,1] Operation: If [W<3:0> >9] or [DC = 1] then, a  [0,1] (W<3:0>) + 6  W<3:0>; else, Operation: (f) – 1  dest ( W<3:0>)  W<3:0>; Status Affected: C, DC, N, OV, Z If [W<7:4> > 9] or [C = 1] then, Encoding: 0000 01da ffff ffff ( W<7:4>) + 6  W<7:4>, Description: Decrement register ‘f’. If ‘d’ is ‘0’, the C =1; result is stored in W. If ‘d’ is ‘1’, the else, result is stored back in register ‘f’. (W<7:4>)  W<7:4> If ‘a’ is ‘0’, the Access Bank is selected. Status Affected: C If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Encoding: 0000 0000 0000 0111 If ‘a’ is ‘0’ and the extended instruction Description: DAW adjusts the eight-bit value in W, set is enabled, this instruction operates resulting from the earlier addition of two in Indexed Literal Offset addressing variables (each in packed BCD format) mode whenever f 95 (5Fh). See and produces a correct packed BCD Section25.2.3 for details. result. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write register ‘f’ Data destination register W Data W Example 1: Example: DECF CNT, 1, 0 DAW Before Instruction Before Instruction CNT = 01h Z = 0 W = A5h C = 0 After Instruction DC = 0 CNT = 00h After Instruction Z = 1 W = 05h C = 1 DC = 0 Example 2: Before Instruction W = CEh C = 0 DC = 0 After Instruction W = 34h C = 1 DC = 0 DS39635C-page 316  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 DECFSZ Decrement f, skip if 0 DCFSNZ Decrement f, skip if not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) – 1  dest, Operation: (f) – 1  dest, skip if result = 0 skip if result  0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’. placed back in register ‘f’. If the result is ‘0’, the next instruction, If the result is not ‘0’, the next which is already fetched, is discarded instruction, which is already fetched, is and a NOP is executed instead, making discarded and a NOP is executed it a two-cycle instruction. instead, making it a two-cycle If ‘a’ is ‘0’, the Access Bank is selected. instruction. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank. If ‘a’ is 1, the BSR is used to select the If ‘a’ is ‘0’ and the extended instruction GPR bank. set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction in Indexed Literal Offset Addressing set is enabled, this instruction operates mode whenever f 95 (5Fh). See in Indexed Literal Offset Addressing Section25.2.3 for details. mode whenever f 95 (5Fh). See Section25.2.3 for details. Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed Cycles: 1(2) by a 2-word instruction. Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to If skip: register ‘f’ Data destination Q1 Q2 Q3 Q4 If skip: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation No No No No operation operation operation operation Example: HERE DECFSZ CNT, 1, 1 GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0 CONTINUE ZERO : NZERO : Before Instruction PC = Address (HERE) Before Instruction After Instruction TEMP = ? CNT = CNT – 1 After Instruction If CNT = 0; TEMP = TEMP – 1, PC = Address (CONTINUE) If TEMP = 0; If CNT  0; PC = Address (ZERO) PC = Address (HERE + 2) If TEMP  0; PC = Address (NZERO)  2010 Microchip Technology Inc. DS39635C-page 317

PIC18F6310/6410/8310/8410 GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF f {,d {,a}} Operands: 0  k  1048575 Operands: 0  f  255 d  [0,1] Operation: k  PC<20:1> a  [0,1] Status Affected: None Operation: (f) + 1  dest Encoding: Status Affected: C, DC, N, OV, Z 1st word (k<7:0>) 1110 1111 k kkk kkkk 7 0 2nd word(k<19:8>) 1111 k kkk kkkk kkkk Encoding: 0010 10da ffff ffff 19 8 Description: GOTO allows an unconditional branch Description: The contents of register ‘f’ are anywhere within entire incremented. If ‘d’ is ‘0’, the result is 2-Mbyte memory range. The 20-bit placed in W. If ‘d’ is ‘1’, the result is value ‘k’ is loaded into PC<20:1>. placed back in register ‘f’. GOTO is always a two-cycle If ‘a’ is ‘0’, the Access Bank is selected. instruction. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Words: 2 If ‘a’ is ‘0’ and the extended instruction Cycles: 2 set is enabled, this instruction operates Q Cycle Activity: in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Q1 Q2 Q3 Q4 Section25.2.3 for details. Decode Read literal No Read literal ‘k’<7:0>, operation ’k’<19:8>, Words: 1 Write to PC Cycles: 1 No No No No Q Cycle Activity: operation operation operation operation Q1 Q2 Q3 Q4 Decode Read Process Write to Example: GOTO THERE register ‘f’ Data destination After Instruction PC = Address (THERE) Example: INCF CNT, 1, 0 Before Instruction CNT = FFh Z = 0 C = ? DC = ? After Instruction CNT = 00h Z = 1 C = 1 DC = 1 DS39635C-page 318  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 INCFSZ Increment f, skip if 0 INFSNZ Increment f, skip if not 0 Syntax: INCFSZ f {,d {,a}} Syntax: INFSNZ f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) + 1  dest, Operation: (f) + 1  dest, skip if result  0 skip if result = 0 Status Affected: None Status Affected: None Encoding: 0100 10da ffff ffff Encoding: 0011 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’. placed back in register ‘f’. If the result is not ‘0’, the next If the result is ‘0’, the next instruction, instruction, which is already fetched, is which is already fetched, is discarded discarded and a NOP is executed and a NOP is executed instead, making instead, making it a two-cycle it a two-cycle instruction. instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the GPR bank. GPR bank. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See mode whenever f 95 (5Fh). See Section25.2.3 for details. Section25.2.3 for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ‘f’ Data destination register ‘f’ Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE INCFSZ CNT, 1, 0 Example: HERE INFSNZ REG, 1, 0 NZERO : ZERO ZERO : NZERO Before Instruction Before Instruction PC = Address (HERE) PC = Address (HERE) After Instruction After Instruction CNT = CNT + 1 REG = REG + 1 If CNT = 0; If REG  0; PC = Address (ZERO) PC = Address (NZERO) If CNT  0; If REG = 0; PC = Address (NZERO) PC = Address (ZERO)  2010 Microchip Technology Inc. DS39635C-page 319

PIC18F6310/6410/8310/8410 IORLW Inclusive OR literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF f {,d {,a}} Operands: 0  k  255 Operands: 0  f  255 d  [0,1] Operation: (W) .OR. k  W a  [0,1] Status Affected: N, Z Operation: (W) .OR. (f)  dest Encoding: 0000 1001 kkkk kkkk Status Affected: N, Z Description: The contents of W are ORed with the Encoding: 0001 00da ffff ffff eight-bit literal ‘k’. The result is placed in W. Description: Inclusive OR W with register ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, Words: 1 the result is placed back in register ‘f’. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is selected. Q Cycle Activity: If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode Read Process Write to W set is enabled, this instruction operates literal ‘k’ Data in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Example: IORLW 35h Section25.2.3 for details. Before Instruction Words: 1 W = 9Ah Cycles: 1 After Instruction Q Cycle Activity: W = BFh Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: IORWF RESULT, 0, 1 Before Instruction RESULT = 13h W = 91h After Instruction RESULT = 13h W = 93h DS39635C-page 320  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF f {,d {,a}} Operands: 0  f  2 Operands: 0  f  255 0  k  4095 d  [0,1] a  [0,1] Operation: k  FSRf Operation: f  dest Status Affected: None Status Affected: N, Z Encoding: 1110 1110 00ff k kkk 11 1111 0000 k kkk kkkk Encoding: 0101 00da ffff ffff 7 Description: The 12-bit literal ‘k’ is loaded into the Description: The contents of register ‘f’ are moved to file select register pointed to by ‘f’. a destination dependent upon the status of ‘d’. If ‘d’ is ‘0’, the result is Words: 2 placed in W. If ‘d’ is ‘1’, the result is Cycles: 2 placed back in register ‘f’. Location ‘f’ Q Cycle Activity: can be anywhere in the 256-byte bank. If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the Decode Read literal Process Write GPR bank. ‘k’ MSB Data literal ‘k’ If ‘a’ is ‘0’ and the extended instruction MSB to set is enabled, this instruction operates FSRfH in Indexed Literal Offset Addressing Decode Read literal Process Write literal mode whenever f 95 (5Fh). See ‘k’ LSB Data ‘k’ to FSRfL Section25.2.3 for details. Words: 1 Example: LFSR 2, 3ABh Cycles: 1 After Instruction Q Cycle Activity: FSR2H = 03h FSR2L = ABh Q1 Q2 Q3 Q4 Decode Read Process Write W register ‘f’ Data Example: MOVF REG, 0, 0 Before Instruction REG = 22h W = FFh After Instruction REG = 22h W = 22h  2010 Microchip Technology Inc. DS39635C-page 321

PIC18F6310/6410/8310/8410 MOVFF Move f to f MOVLB Move literal to low nibble in BSR Syntax: MOVFF f ,f Syntax: MOVLW k s d Operands: 0  f  4095 Operands: 0  k  255 s 0  f  4095 d Operation: k  BSR Operation: (f )  f s d Status Affected: None Status Affected: None Encoding: 0000 0001 kkkk kkkk Encoding: Description: The eight-bit literal ‘k’ is loaded into the 1st word (source) 1100 ffff ffff ffffs Bank Select Register (BSR). The value 2nd word (destin.) 1111 ffff ffff ffffd of BSR<7:4> always remains ‘0’, Description: The contents of source register ‘f ’ are regardless of the value of k :k . s 7 4 moved to destination register ‘f ’. d Words: 1 Location of source ‘f ’ can be anywhere s in the 4096-byte data space (000h to Cycles: 1 FFFh) and location of destination ‘fd’ Q Cycle Activity: can also be anywhere from 000h to Q1 Q2 Q3 Q4 FFFh. Either source or destination can be W Decode Read Process Write literal (a useful special situation). literal ‘k’ Data ‘k’ to BSR MOVFF is particularly useful for transferring a data memory location to a Example: MOVLB 5 peripheral register (such as the transmit Before Instruction buffer or an I/O port). BSR Register = 02h The MOVFF instruction cannot use the After Instruction PCL, TOSU, TOSH or TOSL as the BSR Register = 05h destination register Words: 2 Cycles: 2 (3) Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation (src) Decode No No Write operation operation register ‘f’ No dummy (dest) read Example: MOVFF REG1, REG2 Before Instruction REG1 = 33h REG2 = 11h After Instruction REG1 = 33h REG2 = 33h DS39635C-page 322  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 MOVLW Move literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF f {,a} Operands: 0  k  255 Operands: 0  f  255 a  [0,1] Operation: k  W Operation: (W)  f Status Affected: None Status Affected: None Encoding: 0000 1110 kkkk kkkk Encoding: 0110 111a ffff ffff Description: The eight-bit literal ‘k’ is loaded into W. Description: Move data from W to register ‘f’. Words: 1 Location ‘f’ can be anywhere in the Cycles: 1 256-byte bank. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank. Decode Read Process Write to W If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: MOVLW 5Ah mode whenever f 95 (5Fh). See Section25.2.3 for details. After Instruction Words: 1 W = 5Ah Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: MOVWF REG, 0 Before Instruction W = 4Fh REG = FFh After Instruction W = 4Fh REG = 4Fh  2010 Microchip Technology Inc. DS39635C-page 323

PIC18F6310/6410/8310/8410 MULLW Multiply literal with W MULWF Multiply W with f Syntax: MULLW k Syntax: MULWF f {,a} Operands: 0  k  255 Operands: 0  f  255 a  [0,1] Operation: (W) x k  PRODH:PRODL Operation: (W) x (f)  PRODH:PRODL Status Affected: None Status Affected: None Encoding: 0000 1101 kkkk kkkk Encoding: 0000 001a ffff ffff Description: An unsigned multiplication is carried out between the contents of W and the Description: An unsigned multiplication is carried 8-bit literal ‘k’. The 16-bit result is out between the contents of W and the placed in PRODH:PRODL register pair. register file location ‘f’. The 16-bit PRODH contains the high byte. result is stored in the PRODH:PRODL W is unchanged. register pair. PRODH contains the None of the Status flags are affected. high byte. Both W and ‘f’ are Note that neither Overflow nor Carry is unchanged. possible in this operation. A Zero result None of the Status flags are affected. is possible but not detected. Note that neither Overflow nor Carry is possible in this operation. A Zero Words: 1 result is possible but not detected. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is Q Cycle Activity: selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode Read Process Write set is enabled, this instruction literal ‘k’ Data registers operates in Indexed Literal Offset PRODH: Addressing mode whenever f 95 PRODL (5Fh). See Section25.2.3 for details. Words: 1 Example: MULLW 0C4h Cycles: 1 Before Instruction Q Cycle Activity: W = E2h PRODH = ? Q1 Q2 Q3 Q4 PRODL = ? Decode Read Process Write After Instruction register ‘f’ Data registers W = E2h PRODH: PRODH = ADh PRODL PRODL = 08h Example: MULWF REG, 1 Before Instruction W = C4h REG = B5h PRODH = ? PRODL = ? After Instruction W = C4h REG = B5h PRODH = 8Ah PRODL = 94h DS39635C-page 324  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 NEGF Negate f NOP No Operation Syntax: NEGF f {,a} Syntax: NOP Operands: 0  f  255 Operands: None a  [0,1] Operation: No operation Operation: (f) + 1  f Status Affected: None Status Affected: N, OV, C, DC, Z Encoding: 0000 0000 0000 0000 Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx Description: Location ‘f’ is negated using two’s Description: No operation. complement. The result is placed in the Words: 1 data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. Cycles: 1 If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode No No No set is enabled, this instruction operates operation operation operation in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section25.2.3 for details. Example: Words: 1 Cycles: 1 None. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [3Ah] After Instruction REG = 1100 0110 [C6h]  2010 Microchip Technology Inc. DS39635C-page 325

PIC18F6310/6410/8310/8410 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS)  bit bucket Operation: (PC + 2)  TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return Description: The PC + 2 is pushed onto the top of stack and is discarded. The TOS value the return stack. The previous TOS then becomes the previous value that value is pushed down on the stack. was pushed onto the return stack. This instruction allows implementing a This instruction is provided to enable software stack by modifying TOS and the user to properly manage the return then pushing it onto the return stack. stack to incorporate a software stack. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode PUSH No No Decode No POP TOS No PC + 2 onto operation operation operation value operation return stack Example: POP Example: PUSH GOTO NEW Before Instruction Before Instruction TOS = 345Ah TOS = 0031A2h PC = 0124h Stack (1 level down) = 014332h After Instruction After Instruction PC = 0126h TOS = 014332h TOS = 0126h PC = NEW Stack (1 level down) = 345Ah DS39635C-page 326  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 RCALL Relative Call RESET Reset Syntax: RCALL n Syntax: RESET Operands: -1024  n  1023 Operands: None Operation: (PC) + 2  TOS, Operation: Reset all registers and flags that are (PC) + 2 + 2n  PC affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111 Description: Subroutine call with a jump up to 1K Description: This instruction provides a way to from the current location. First, return execute a MCLR Reset in software. address (PC + 2) is pushed onto the Words: 1 stack. Then, add the 2’s complement number ‘2n’ to the PC. Since the PC will Cycles: 1 have incremented to fetch the next Q Cycle Activity: instruction, the new address will be Q1 Q2 Q3 Q4 PC + 2 + 2n. This instruction is a two-cycle instruction. Decode Start No No Reset operation operation Words: 1 Cycles: 2 Example: RESET Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 Registers= Reset Value Decode Read literal Process Write to PC Flags* = Reset Value ‘n’ Data Push PC to stack No No No No operation operation operation operation Example: HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS= Address (HERE + 2)  2010 Microchip Technology Inc. DS39635C-page 327

PIC18F6310/6410/8310/8410 RETFIE Return from Interrupt RETLW Return literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s  [0,1] Operands: 0  k  255 Operation: (TOS)  PC, Operation: k  W, 1  GIE/GIEH or PEIE/GIEL; (TOS)  PC, if s = 1, PCLATU, PCLATH are unchanged (WS)  W, Status Affected: None (STATUSS)  STATUS, (BSRS)  BSR, Encoding: 0000 1100 kkkk kkkk PCLATU, PCLATH are unchanged Description: W is loaded with the eight-bit literal ‘k’. Status Affected: GIE/GIEH, PEIE/GIEL. The program counter is loaded from the top of the stack (the return address). Encoding: 0000 0000 0001 000s The high address latch (PCLATH) Description: Return from interrupt. Stack is popped remains unchanged. and Top-of-Stack (TOS) is loaded into Words: 1 the PC. Interrupts are enabled by setting either the high or low-priority Cycles: 2 global interrupt enable bit. If ‘s’ = 1, the Q Cycle Activity: contents of the shadow registers, WS, Q1 Q2 Q3 Q4 STATUSS and BSRS, are loaded into their corresponding registers, W, Decode Read Process Pop PC from STATUS and BSR. If ‘s’ = 0, no update literal ‘k’ Data stack, Write of these registers occurs. to W No No No No Words: 1 operation operation operation operation Cycles: 2 Q Cycle Activity: Example: Q1 Q2 Q3 Q4 Decode No No Pop PC from CALL TABLE ; W contains table operation operation stack ; offset value ; W now has Set GIEH or ; table value GIEL : No No No No TABLE operation operation operation operation ADDWF PCL ; W = offset RETLW k0 ; Begin table Example: RETFIE 1 RETLW k1 ; : After Interrupt : PC = TOS W = WS RETLW kn ; End of table BSR = BSRS STATUS = STATUSS GIE/GIEH, PEIE/GIEL = 1 Before Instruction W = 07h After Instruction W = value of kn DS39635C-page 328  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF f {,d {,a}} Operands: s  [0,1] Operands: 0  f  255 d  [0,1] Operation: (TOS)  PC; a  [0,1] if s = 1, (WS)  W, Operation: (f<n>)  dest<n + 1>, (STATUSS)  STATUS, (f<7>)  C, (BSRS)  BSR, (C)  dest<0> PCLATU, PCLATH are unchanged Status Affected: C, N, Z Status Affected: None Encoding: 0011 01da ffff ffff Encoding: 0000 0000 0001 001s Description: The contents of register ‘f’ are rotated Description: Return from subroutine. The stack is one bit to the left through the Carry popped and the top of the stack (TOS) flag. If ‘d’ is ‘0’, the result is placed in is loaded into the program counter. If W. If ‘d’ is ‘1’, the result is stored back ‘s’= 1, the contents of the shadow in register ‘f’. registers, WS, STATUSS and BSRS, If ‘a’ is ‘0’, the Access Bank is are loaded into their corresponding selected. If ‘a’ is ‘1’, the BSR is used to registers, W, STATUS and BSR. If select the GPR bank. ‘s’ = 0, no update of these registers If ‘a’ is ‘0’ and the extended instruction occurs. set is enabled, this instruction operates in Indexed Literal Offset Words: 1 Addressing mode whenever f 95 Cycles: 2 (5Fh). See Section25.2.3 for details. Q Cycle Activity: C register f Q1 Q2 Q3 Q4 Decode No Process Pop PC from Words: 1 operation Data stack Cycles: 1 No No No No operation operation operation operation Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: RETURN After Instruction: Example: RLCF REG, 0, 0 PC = TOS Before Instruction REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 1100 1100 C = 1  2010 Microchip Technology Inc. DS39635C-page 329

PIC18F6310/6410/8310/8410 RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry Syntax: RLNCF f {,d {,a}} Syntax: RRCF f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f<n>)  dest<n + 1>, Operation: (f<n>)  dest<n – 1>, (f<7>)  dest<0> (f<0>)  C, (C)  dest<7> Status Affected: N, Z Status Affected: C, N, Z Encoding: 0100 01da ffff ffff Encoding: 0011 00da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result Description: The contents of register ‘f’ are rotated is placed in W. If ‘d’ is ‘1’, the result is one bit to the right through the Carry stored back in register ‘f’. flag. If ‘d’ is ‘0’, the result is placed in W. If ‘a’ is ‘0’, the Access Bank is selected. If ‘d’ is ‘1’, the result is placed back in If ‘a’ is ‘1’, the BSR is used to select the register ‘f’, GPR bank. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘1’, the BSR is used to select the set is enabled, this instruction operates GPR bank. in Indexed Literal Offset Addressing If ‘a’ is ‘0’ and the extended instruction mode whenever f 95 (5Fh). See set is enabled, this instruction operates Section25.2.3 for details. in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See register f Section25.2.3 for details. Words: 1 C register f Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to register ‘f’ Data destination Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: RLNCF REG, 1, 0 Before Instruction REG = 1010 1011 Example: RRCF REG, 0, 0 After Instruction Before Instruction REG = 0101 0111 REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 0111 0011 C = 0 DS39635C-page 330  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 RRNCF Rotate Right f (no carry) SETF Set f Syntax: RRNCF f {,d {,a}} Syntax: SETF f {,a} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] a [0,1] a  [0,1] Operation: FFh  f Operation: (f<n>)  dest<n – 1>, Status Affected: None (f<0>)  dest<7> Encoding: 0110 100a ffff ffff Status Affected: N, Z Description: The contents of the specified register Encoding: 0100 00da ffff ffff are set to FFh. Description: The contents of register ‘f’ are rotated If ‘a’ is ‘0’, the Access Bank is selected. one bit to the right. If ‘d’ is ‘0’, the result If ‘a’ is ‘1’, the BSR is used to select the is placed in W. If ‘d’ is ‘1’, the result is GPR bank. placed back in register ‘f’. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank will be set is enabled, this instruction operates selected, overriding the BSR value. If ‘a’ in Indexed Literal Offset Addressing is ‘1’, then the bank will be selected as mode whenever f 95 (5Fh). See per the BSR value. Section25.2.3 for details. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates in Indexed Literal Offset Addressing Cycles: 1 mode whenever f 95 (5Fh). See Q Cycle Activity: Section25.2.3 for details. Q1 Q2 Q3 Q4 register f Decode Read Process Write register ‘f’ Data register ‘f’ Words: 1 Cycles: 1 Example: SETF REG,1 Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 REG = 5Ah After Instruction Decode Read Process Write to REG = FFh register ‘f’ Data destination Example 1: RRNCF REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = 1110 1011 Example 2: RRNCF REG, 0, 0 Before Instruction W = ? REG = 1101 0111 After Instruction W = 1110 1011 REG = 1101 0111  2010 Microchip Technology Inc. DS39635C-page 331

PIC18F6310/6410/8310/8410 SLEEP Enter Sleep mode SUBFWB Subtract f from W with borrow Syntax: SLEEP Syntax: SUBFWB f {,d {,a}} Operands: None Operands: 0 f 255 d  [0,1] Operation: 00h  WDT, a  [0,1] 0  WDT postscaler, 1  TO, Operation: (W) – (f) – (C) dest 0  PD Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0101 01da ffff ffff Encoding: 0000 0000 0000 0011 Description: Subtract register ‘f’ and Carry flag Description: The Power-Down status bit (PD) is (borrow) from W (2’s complement cleared. The Time-out status bit (TO) method). If ‘d’ is ‘0’, the result is stored is set. Watchdog Timer and its post- in W. If ‘d’ is ‘1’, the result is stored in scaler are cleared. register ‘f’. The processor is put into Sleep mode If ‘a’ is ‘0’, the Access Bank is with the oscillator stopped. selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 1 set is enabled, this instruction Q Cycle Activity: operates in Indexed Literal Offset Addressing mode whenever f 95 Q1 Q2 Q3 Q4 (5Fh). See Section25.2.3 for details. Decode No Process Go to operation Data Sleep Words: 1 Cycles: 1 Example: SLEEP Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 TO = ? Decode Read Process Write to PD = ? register ‘f’ Data destination After Instruction Example 1: SUBFWB REG, 1, 0 TO = 1 † Before Instruction PD = 0 REG = 3 W = 2 † If WDT causes wake-up, this bit is cleared. C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 DS39635C-page 332  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 SUBLW Subtract W from literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF f {,d {,a}} Operands: 0 k 255 Operands: 0 f 255 d  [0,1] Operation: k – (W) W a  [0,1] Status Affected: N, OV, C, DC, Z Operation: (f) – (W) dest Encoding: 0000 1000 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: W is subtracted from the eight-bit Encoding: 0101 11da ffff ffff literal ‘k’. The result is placed in W. Description: Subtract W from register ‘f’ (2’s Words: 1 complement method). If ‘d’ is ‘0’, the Cycles: 1 result is stored in W. If ‘d’ is V, the Q Cycle Activity: result is stored back in register ‘f’. If ‘a’ is ‘0’, the Access Bank is Q1 Q2 Q3 Q4 selected. If ‘a’ is V, the BSR is used to Decode Read Process Write to W select the GPR bank. literal ‘k’ Data If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction Example 1: SUBLW 02h operates in Indexed Literal Offset Before Instruction Addressing mode whenever f 95 W = 01h (5Fh). See Section25.2.3 for details. C = ? Words: 1 After Instruction Cycles: 1 W = 01h C = 1 ; result is positive Q Cycle Activity: Z = 0 Q1 Q2 Q3 Q4 N = 0 Decode Read Process Write to Example 2: SUBLW 02h register ‘f’ Data destination Before Instruction Example 1: SUBWF REG, 1, 0 W = 02h Before Instruction C = ? REG = 3 After Instruction W = 2 W = 00h C = ? C = 1 ; result is zero After Instruction Z = 1 N = 0 REG = 1 W = 2 Example 3: SUBLW 02h C = 1 ; result is positive Before Instruction Z = 0 N = 0 W = 03h Example 2: SUBWF REG, 0, 0 C = ? After Instruction Before Instruction REG = 2 W = FFh ; (2’s complement) W = 2 C = 0 ; result is negative Z = 0 C = ? N = 1 After Instruction REG = 2 W = 0 C = 1 ; result is zero Z = 1 N = 0 Example 3: SUBWF REG, 1, 0 Before Instruction REG = 1 W = 2 C = ? After Instruction REG = FFh ;(2’s complement) W = 2 C = 0 ; result is negative Z = 0 N = 1  2010 Microchip Technology Inc. DS39635C-page 333

PIC18F6310/6410/8310/8410 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB f {,d {,a}} Syntax: SWAPF f {,d {,a}} Operands: 0  f  255 Operands: 0  f  255 d  [0,1] d  [0,1] a  [0,1] a  [0,1] Operation: (f) – (W) – (C) dest Operation: (f<3:0>)  dest<7:4>, Status Affected: N, OV, C, DC, Z (f<7:4>)  dest<3:0> Encoding: 0101 10da ffff ffff Status Affected: None Description: Subtract W and the Carry flag (borrow) Encoding: 0011 10da ffff ffff from register ‘f’ (2’s complement Description: The upper and lower nibbles of register method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back ‘f’ are exchanged. If ‘d’ is ‘0’, the result in register ‘f’. is placed in W. If ‘d’ is ‘1’, the result is placed in register ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See mode whenever f 95 (5Fh). See Section25.2.3 for details. Section25.2.3 for details. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to Example 1: SUBWFB REG, 1, 0 register ‘f’ Data destination Before Instruction REG = 19h (0001 1001) Example: SWAPF REG, 1, 0 W = 0Dh (0000 1101) Before Instruction C = 1 REG = 53h After Instruction After Instruction REG = 0Ch (0000 1011) REG = 35h W = 0Dh (0000 1101) C = 1 Z = 0 N = 0 ; result is positive Example 2: SUBWFB REG, 0, 0 Before Instruction REG = 1Bh (0001 1011) W = 1Ah (0001 1010) C = 0 After Instruction REG = 1Bh (0001 1011) W = 00h C = 1 Z = 1 ; result is zero N = 0 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 03h (0000 0011) W = 0Eh (0000 1101) C = 1 After Instruction REG = F5h (1111 0100) ; [2’s comp] W = 0Eh (0000 1101) C = 0 Z = 0 N = 1 ; result is negative DS39635C-page 334  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD *+ ; Operands: None Before Instruction TABLAT = 55h Operation: if TBLRD *, TBLPTR = 00A356h (Prog Mem (TBLPTR))  TABLAT, MEMORY(00A356h) = 34h TBLPTR – No Change; After Instruction if TBLRD *+, TABLAT = 34h (Prog Mem (TBLPTR))  TABLAT, TBLPTR = 00A357h (TBLPTR) + 1  TBLPTR; Example 2: TBLRD +* ; if TBLRD *-, (Prog Mem (TBLPTR))  TABLAT, Before Instruction (TBLPTR) – 1  TBLPTR; TABLAT = AAh TBLPTR = 01A357h if TBLRD +*, MEMORY(01A357h) = 12h (TBLPTR) + 1  TBLPTR, MEMORY(01A358h) = 34h (Prog Mem (TBLPTR))  TABLAT After Instruction Status Affected: None TABLAT = 34h TBLPTR = 01A358h Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No operation No No operation operation (Read Program operation (Write Memory) TABLAT)  2010 Microchip Technology Inc. DS39635C-page 335

PIC18F6310/6410/8310/8410 TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Before Instruction Operation: if TBLWT*, TABLAT = 55h (TABLAT)  Holding Register, TBLPTR = 00A356h TBLPTR – No Change; HOLDING REGISTER (00A356h) = FFh if TBLWT*+, After Instructions (table write completion) (TABLAT)  Holding Register, TABLAT = 55h (TBLPTR) + 1  TBLPTR; TBLPTR = 00A357h if TBLWT*-, HOLDING REGISTER (TABLAT)  Holding Register, (00A356h) = 55h (TBLPTR) – 1  TBLPTR; Example 2: TBLWT +*; if TBLWT+*, (TBLPTR) + 1  TBLPTR, Before Instruction (TABLAT)  Holding Register TABLAT = 34h TBLPTR = 01389Ah Status Affected: None HOLDING REGISTER (01389Ah) = FFh Encoding: 0000 0000 0000 11nn HOLDING REGISTER nn=0 * (01389Bh) = FFh =1 *+ After Instruction (table write completion) =2 *- TABLAT = 34h =3 +* TBLPTR = 01389Bh HOLDING REGISTER Description: This instruction uses the 3 LSBs of (01389Ah) = FFh TBLPTR to determine which of the 8 HOLDING REGISTER holding registers the TABLAT is written to. (01389Bh) = 34h The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section7.0 “Program Memory” for additional details on programming Flash Note: The TBLWT instruction is not available in memory.) PIC18F6310/6410 devices (i.e., 64-pin The TBLPTR (a 21-bit pointer) points to devices) in normal operating modes. each byte in the program memory. TBLWT can only be used by TBLPTR has a 2-Mbyte address range. PIC18F8310/8410 devices with the The LSb of the TBLPTR selects which external memory interface and only when byte of the program memory location to writing to an external memory device. access. For more information, refer to Section7.4 TBLPTR[0] = 0: Least Significant “Writing to Program Memory Space Byte of Program Memory Word (PIC18F8310/8410 only)” and TBLPTR[0] = 1: Most Significant Section7.6 “Writing and Erasing Byte of Program Memory Word On-Chip Program Memory (ICSP The TBLWT instruction can modify the Mode)”. value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operationoperation operation No No No No operationoperationoperation operation (Read (Write to TABLAT) Holding Register ) DS39635C-page 336  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TSTFSZ Test f, skip if 0 XORLW Exclusive OR literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0  f  255 Operands: 0 k 255 a  [0,1] Operation: (W) .XOR. k W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: 0000 1010 kkkk kkkk Encoding: 0110 011a ffff ffff Description: The contents of W are XORed with Description: If ‘f’ = 0, the next instruction, fetched the 8-bit literal ‘k’. The result is placed during the current instruction execution, in W. is discarded and a NOP is executed, Words: 1 making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. Cycles: 1 If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Decode Read Process Write to W in Indexed Literal Offset Addressing literal ‘k’ Data mode whenever f 95 (5Fh). See Section25.2.3 for details. Example: XORLW 0AFh Words: 1 Before Instruction Cycles: 1(2) W = B5h Note: 3 cycles if skip and followed After Instruction by a 2-word instruction. W = 1Ah Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE TSTFSZ CNT, 1 NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction If CNT = 00h, PC = Address (ZERO) If CNT  00h, PC = Address (NZERO)  2010 Microchip Technology Inc. DS39635C-page 337

PIC18F6310/6410/8310/8410 XORWF Exclusive OR W with f Syntax: XORWF f {,d {,a}} Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section25.2.3 for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: XORWF REG, 1, 0 Before Instruction REG = AFh W = B5h After Instruction REG = 1Ah W = B5h DS39635C-page 338  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 25.2 Extended Instruction Set A summary of the instructions in the extended instruc- tion set is provided in Table25-3. Detailed descriptions In addition to the standard 75 instructions of the PIC18 are provided in Section25.2.2 “Extended Instruction instruction set, PIC18F6310/6410/8310/8410 devices Set”. The opcode field descriptions in Table25-1 also provide an optional extension to the core CPU (page298) apply to both the standard and extended functionality. The added features include eight addi- PIC18 instruction sets. tional instructions that augment Indirect and Indexed Addressing operations and the implementation of Note: The instruction set extension and the Indexed Literal Offset Addressing for many of the Indexed Literal Offset Addressing mode standard PIC18 instructions. were designed for optimizing applications written in C; the user may likely never use The additional features of the extended instruction set these instructions directly in assembler. are disabled by default. To enable them, users must set The syntax for these commands is pro- the XINST Configuration bit. vided as a reference for users who may be The instructions in the extended set can all be classi- reviewing code that has been generated fied as literal operations which either manipulate the by a compiler. File Select Registers, or use them for Indexed Address- ing. Two of the instructions, ADDFSR and SUBFSR, each 25.2.1 EXTENDED INSTRUCTION SYNTAX have an additional special instantiation for using FSR2. Most of the extended instructions use indexed argu- These versions (ADDULNK and SUBULNK) allow for ments, using one of the File Select Registers and some automatic return after execution. offset to specify a source or destination register. When The extended instructions are specifically implemented an argument for an instruction serves as part of to optimize re-entrant program code (that is, code that Indexed Addressing, it is enclosed in square brackets is recursive or that uses a software stack) written in (“[ ]”). This is done to indicate that the argument is used high-level languages, particularly C. Among other as an index or offset. The MPASM Assembler will flag things, they allow users working in high-level an error if it determines that an index or offset value is languages to perform certain operations on data not bracketed. structures more efficiently. These include: When the extended instruction set is enabled, brackets • dynamic allocation and de-allocation of software are also used to indicate index arguments in stack space when entering and leaving byte-oriented and bit-oriented instructions. This is in subroutines addition to other changes in their syntax. For more • Function Pointer invocation details, see Section25.2.3.1 “Extended Instruction • Software Stack Pointer manipulation Syntax with Standard PIC18 Commands”. • manipulation of variables located in a software Note: In the past, square brackets have been stack used to denote optional arguments in the PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces (“{ }”). TABLE 25-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET Mnemonic, 16-Bit Instruction Word Status Description Cycles Operands MSb LSb Affected ADDFSR f, k Add Literal to FSR 1 1110 1000 ffkk kkkk None ADDULNK k Add Literal to FSR2 and Return 2 1110 1000 11kk kkkk None CALLW Call Subroutine using WREG 2 0000 0000 0001 0100 None MOVSF zs, fd Move zs (source) to 1st word 2 1110 1011 0zzz zzzz None fd (destination) 2nd word 1111 ffff ffff ffff MOVSS zs, zd Move zs (source) to 1st word 2 1110 1011 1zzz zzzz None zd (destination) 2nd word 1111 xxxx xzzz zzzz PUSHL k Store Literal at FSR2, Decrement FSR2 1 1110 1010 kkkk kkkk None SUBFSR f, k Subtract Literal from FSR 1 1110 1001 ffkk kkkk None SUBULNK k Subtract Literal from FSR2 and Return 2 1110 1001 11kk kkkk None Note: All PIC18 instructions may take an optional label argument, preceding the instruction mnemonic, for use in symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s)  2010 Microchip Technology Inc. DS39635C-page 339

PIC18F6310/6410/8310/8410 25.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0  k  63 Operands: 0  k  63 f  [0, 1, 2] Operation: FSR2 + k  FSR2, Operation: FSR(f) + k  FSR(f) (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk Description: The 6-bit literal ‘k’ is added to the Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’. contents of FSR2. A RETURN is then Words: 1 executed by loading the PC with the Cycles: 1 TOS. The instruction takes two cycles to Q Cycle Activity: execute; a NOP is performed during the Q1 Q2 Q3 Q4 second cycle. Decode Read Process Write to This may be though of as a special case literal ‘k’ Data FSR of the ADDFSR instruction, where f = 3 (binary ‘11’); it operates only on FSR2. Words: 1 Example: ADDFSR 2, 23h Cycles: 2 Before Instruction Q Cycle Activity: FSR2 = 03FFh Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to FSR2 = 0422h literal ‘k’ Data FSR No No No No Operation Operation Operation Operation Example: ADDULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 0422h PC = (TOS) DS39635C-page 340  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 CALLW Subroutine Call Using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [z ], f s d Operands: None Operands: 0  z  127 s 0  f  4095 Operation: (PC + 2)  TOS, d (W)  PCL, Operation: ((FSR2) + z )  f s d (PCLATH)  PCH, Status Affected: None (PCLATU)  PCU Encoding: Status Affected: None 1st word (source) 1110 1011 0zzz zzzz s Encoding: 0000 0000 0001 0100 2nd word (destin.) 1111 ffff ffff ffffd Description First, the return address (PC + 2) is Description: The contents of the source register are pushed onto the return stack. Next, the moved to destination register ‘f ’. The d contents of W are written to PCL; the actual address of the source register is existing value is discarded. Then, the determined by adding the 7-bit literal contents of PCLATH and PCLATU are offset ‘z ’ in the first word to the value of s latched into PCH and PCU, FSR2. The address of the destination respectively. The second cycle is register is specified by the 12-bit literal executed as a NOP instruction while the ‘f ’ in the second word. Both addresses d new next instruction is fetched. can be anywhere in the 4096-byte data Unlike CALL, there is no option to space (000h to FFFh). update W, STATUS or BSR. The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the Words: 1 destination register. Cycles: 2 If the resultant source address points to Q Cycle Activity: an indirect addressing register, the value returned will be 00h. Q1 Q2 Q3 Q4 Decode Read Push PC to No Words: 2 WREG stack operation Cycles: 2 No No No No Q Cycle Activity: operation operation operation operation Q1 Q2 Q3 Q4 Decode Determine Determine Read Example: HERE CALLW source addr source addr source reg Decode No No Write Before Instruction operation operation register ‘f’ PC = address (HERE) PCLATH = 10h No dummy (dest) PCLATU = 00h read W = 06h After Instruction PC = 001006h Example: MOVSF [05h], REG2 TOS = address (HERE + 2) PCLATH = 10h Before Instruction PCLATU = 00h FSR2 = 80h W = 06h Contents of 85h = 33h REG2 = 11h After Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 33h  2010 Microchip Technology Inc. DS39635C-page 341

PIC18F6310/6410/8310/8410 MOVSS Move Indexed to Indexed Store Literal at FSR2, PUSHL Decrement FSR2 Syntax: MOVSS [z ], [z ] s d Operands: 0  z  127 Syntax: PUSHL k s 0  zd  127 Operands: 0k  255 Operation: ((FSR2) + z )  ((FSR2) + z ) s d Operation: k  (FSR2), Status Affected: None FSR2 - 1 FSR2 Encoding: Status Affected: None 1st word (source) 1110 1011 1zzz zzzz s Encoding: 1110 1010 kkkk kkkk 2nd word (dest.) 1111 xxxx xzzz zzzz d Description: The 8-bit literal ‘k’ is written to the data Description The contents of the source register are moved to the destination register. The memory address specified by FSR2. addresses of the source and destination FSR2 is decremented by ‘1’ after the registers are determined by adding the operation. 7-bit literal offsets ‘z ’ or ‘z ’, This instruction allows users to push s d respectively, to the value of FSR2. Both values onto a software stack. registers can be located anywhere in Words: 1 the 4096-byte data memory space Cycles: 1 (000h to FFFh). The MOVSS instruction cannot use the Q Cycle Activity: PCL, TOSU, TOSH or TOSL as the Q1 Q2 Q3 Q4 destination register. Decode Read ‘k’ Process Write to If the resultant source address points to data destination an indirect addressing register, the value returned will be 00h. If the resultant destination address points to Example: PUSHL 08h an indirect addressing register, the instruction will execute as a NOP. Before Instruction FSR2H:FSR2L = 01ECh Words: 2 Memory (01ECh) = 00h Cycles: 2 After Instruction Q Cycle Activity: FSR2H:FSR2L = 01EBh Q1 Q2 Q3 Q4 Memory (01ECh) = 08h Decode Determine Determine Read source addr source addr source reg Decode Determine Determine Write dest addr dest addr to dest reg Example: MOVSS [05h], [06h] Before Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 11h After Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 33h DS39635C-page 342  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 SUBFSR Subtract Literal from FSR Subtract Literal from FSR2 SUBULNK and Return Syntax: SUBFSR f, k Operands: 0  k  63 Syntax: SUBULNK k f  [ 0, 1, 2 ] Operands: 0  k  63 Operation: FSRf – k  FSRf Operation: FSR2 – k  FSR2 Status Affected: None (TOS) PC Encoding: 1110 1001 ffkk kkkk Status Affected: None Description: The 6-bit literal ‘k’ is subtracted from Encoding: 1110 1001 11kk kkkk the contents of the FSR specified by Description: The 6-bit literal ‘k’ is subtracted from ‘f’. the contents of the FSR2. A RETURN Words: 1 is then executed by loading the PC Cycles: 1 with the TOS. The instruction takes two cycles to Q Cycle Activity: execute; a NOP is performed during Q1 Q2 Q3 Q4 the second cycle. Decode Read Process Write to This may be though of as a special register ‘f’ Data destination case of the SUBFSR instruction, where f = 3 (binary ‘11’); it operates only on FSR2. Example: SUBFSR 2, 23h Words: 1 Before Instruction Cycles: 2 FSR2 = 03FFh Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 FSR2 = 03DCh Decode Read Process Write to register ‘f’ Data destination No No No No Operation Operation Operation Operation Example: SUBULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 03DCh PC = (TOS)  2010 Microchip Technology Inc. DS39635C-page 343

PIC18F6310/6410/8310/8410 25.2.3 BYTE-ORIENTED AND 25.2.3.1 Extended Instruction Syntax with BIT-ORIENTED INSTRUCTIONS IN Standard PIC18 Commands INDEXED LITERAL OFFSET MODE When the extended instruction set is enabled, the file register argument ‘f’ in the standard byte-oriented and Note: Enabling the PIC18 instruction set exten- bit-oriented commands is replaced with the literal offset sion may cause legacy applications to value ‘k’. As already noted, this occurs only when f is behave erratically or fail entirely. less than or equal to 5Fh. When an offset value is used, In addition to eight new commands in the extended set, it must be indicated by square brackets (“[ ]”). As with enabling the extended instruction set also enables the extended instructions, the use of brackets indicates Indexed Literal Offset addressing (Section6.5.1 to the compiler that the value is to be interpreted as an “Indexed Addressing with Literal Offset”). This has index or an offset. Omitting the brackets, or using a a significant impact on the way that many commands of value greater than 5Fh within brackets, will generate an the standard PIC18 instruction set are interpreted. error in the MPASM Assembler. When the extended set is disabled, addresses If the index argument is properly bracketed for Indexed embedded in opcodes are treated as literal memory Literal Offset addressing, the Access RAM argument is locations: either as a location in the Access Bank never specified; it will automatically be assumed to be (a=0) or in a GPR bank designated by the BSR ‘0’. This is in contrast to standard operation (extended (a=1). When the extended instruction set is enabled instruction set disabled), when ‘a’ is set on the basis of and a = 0, however, a file register argument of 5Fh or the target address. Declaring the Access RAM bit in less is interpreted as an offset from the pointer value in this mode will also generate an error in the MPASM FSR2 and not as a literal address. For practical assembler. purposes, this means that all instructions that use the Access RAM bit as an argument – that is, all The destination argument ‘d’ functions as before. byte-oriented and bit-oriented instructions, or almost In the latest versions of the MPASM assembler, half of the core PIC18 instructions – may behave language support for the extended instruction set must differently when the extended instruction set is be explicitly invoked. This is done with either the enabled. command line option /y, or the PE directive in the When the content of FSR2 is 00h, the boundaries of the source listing. Access RAM are essentially remapped to their original 25.2.4 CONSIDERATIONS WHEN values. This may be useful in creating backward ENABLING THE EXTENDED compatible code. If this technique is used, it may be INSTRUCTION SET necessary to save the value of FSR2 and restore it when moving back and forth between C and assembly It is important to note that the extensions to the instruc- routines in order to preserve the Stack Pointer. Users tion set may not be beneficial to all users. In particular, must also keep in mind the syntax requirements of the users who are not writing code that uses a software extended instruction set (see Section25.2.3.1 stack may not benefit from using the extensions to the “Extended Instruction Syntax with Standard PIC18 instruction set. Commands”). Additionally, the Indexed Literal Offset Addressing Although the Indexed Literal Offset mode can be very mode may create issues with legacy applications writ- useful for dynamic stack and pointer manipulation, it ten to PIC18 assembler. This is because instructions in can also be very annoying if a simple arithmetic the legacy code may attempt to address registers in the operation is carried out on the wrong register. Users Access Bank below 5Fh. Since these addresses are who are accustomed to the PIC18 programming must interpreted as literal offsets to FSR2 when the keep in mind that, when the extended instruction set is instruction set extension is enabled, the application enabled, register addresses of 5Fh or less are used for may read or write to the wrong data addresses. Indexed Literal Offset Addressing. When porting an application to the Representative examples of typical byte-oriented and PIC18F6310/6410/8310/8410, it is very important to bit-oriented instructions in the Indexed Literal Offset consider the type of code. A large, re-entrant applica- mode are provided on the following page to show how tion that is written in C and would benefit from efficient execution is affected. The operand conditions shown in compilation will do well when using the instruction set the examples are applicable to all instructions of these extensions. Legacy applications that heavily use the types. Access Bank will most likely not benefit from using the extended instruction set. DS39635C-page 344  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 ADD W to Indexed Bit Set Indexed ADDWF BSF (Indexed Literal Offset mode) (Indexed Literal Offset mode) Syntax: ADDWF [k] {,d} Syntax: BSF [k], b Operands: 0  k  95 Operands: 0  f  95 d  [0,1] 0  b  7 Operation: (W) + ((FSR2) + k)  dest Operation: 1  ((FSR2) + k)<b> Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: 0010 01d0 kkkk kkkk Encoding: 1000 bbb0 kkkk kkkk Description: The contents of W are added to the Description: Bit ‘b’ of the register indicated by FSR2, contents of the register indicated by offset by the value ‘k’, is set. FSR2, offset by the value ‘k’. Words: 1 If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in Cycles: 1 register ‘f’. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read Process Write to register ‘f’ Data destination Q Cycle Activity: Q1 Q2 Q3 Q4 Example: BSF [FLAG_OFST], 7 Decode Read ‘k’ Process Write to Before Instruction Data destination FLAG_OFST = 0Ah FSR2 = 0A00h Example: ADDWF [OFST],0 Contents of 0A0Ah = 55h Before Instruction After Instruction W = 17h Contents OFST = 2Ch of 0A0Ah = D5h FSR2 = 0A00h Contents of 0A2Ch = 20h After Instruction Set Indexed SETF W = 37h (Indexed Literal Offset mode) Contents of 0A2Ch = 20h Syntax: SETF [k] Operands: 0  k  95 Operation: FFh  ((FSR2) + k) Status Affected: None Encoding: 0110 1000 kkkk kkkk Description: The contents of the register indicated by FSR2, offset by ‘k’, are set to FFh. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read ‘k’ Process Write Data register Example: SETF [OFST] Before Instruction OFST = 2Ch FSR2 = 0A00h Contents of 0A2Ch = 00h After Instruction Contents of 0A2Ch = FFh  2010 Microchip Technology Inc. DS39635C-page 345

PIC18F6310/6410/8310/8410 25.2.5 SPECIAL CONSIDERATIONS WITH To develop software for the extended instruction set, MICROCHIP MPLAB IDE TOOLS the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). The latest versions of Microchip’s software tools have Depending on the environment being used, this may be been designed to fully support the extended instruction done in several ways: set of the PIC18F6310/6410/8310/8410 family of • A menu option or dialog box within the devices. This includes the MPLAB C18 compiler, environment that allows the user to configure the MPASM assembly language and MPLAB Integrated language tool and its settings for the project Development Environment (IDE). • A command line option When selecting a target device for software • A directive in the source code development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for These options vary between different compilers, the XINST Configuration is ‘0’, disabling the extended assemblers and development environments. Users are instruction set and Indexed Literal Offset Addressing. encouraged to review the documentation accompanying For proper execution of applications developed to take their development systems for the appropriate advantage of the extended instruction set, XINST must information. be set during programming. DS39635C-page 346  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 26.0 DEVELOPMENT SUPPORT 26.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software The MPLAB IDE software brings an ease of software and hardware development tools: development previously unseen in the 8/16/32-bit • Integrated Development Environment microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: - MPLAB® IDE Software • Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools - MPLAB C Compiler for Various Device - Simulator Families - Programmer (sold separately) - HI-TECH C for Various Device Families - In-Circuit Emulator (sold separately) - MPASMTM Assembler - In-Circuit Debugger (sold separately) - MPLINKTM Object Linker/ • A full-featured editor with color-coded context MPLIBTM Object Librarian • A multiple project manager - MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of Various Device Families contents • Simulators • High-level source code debugging - MPLAB SIM Software Simulator • Mouse over variable inspection • Emulators • Drag and drop variables from source to watch - MPLAB REAL ICE™ In-Circuit Emulator windows • In-Circuit Debuggers • Extensive on-line help - MPLAB ICD 3 • Integration of select third party tools, such as - PICkit™ 3 Debug Express IAR C Compilers • Device Programmers The MPLAB IDE allows you to: - PICkit™ 2 Programmer • Edit your source files (either C or assembly) - MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to • Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically Evaluation Kits, and Starter Kits updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.  2010 Microchip Technology Inc. DS39635C-page 347

PIC18F6310/6410/8310/8410 26.2 MPLAB C Compilers for Various 26.5 MPLINK Object Linker/ Device Families MPLIB Object Librarian The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a lers. These compilers provide powerful integration linker script. capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and use. modification of library files of precompiled code. When For easy source level debugging, the compilers provide a routine from a library is called from a source file, only symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in debugger. with the application. This allows large libraries to be used efficiently in many different applications. 26.3 HI-TECH C for Various Device The object linker/library features include: Families • Efficient linking of single libraries instead of many The HI-TECH C Compiler code development systems smaller files are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping family of microcontrollers and the dsPIC family of digital related modules together signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module integration capabilities, omniscient code generation listing, replacement, deletion and extraction and ease of use. For easy source level debugging, the compilers provide 26.6 MPLAB Assembler, Linker and symbol information that is optimized to the MPLAB IDE Librarian for Various Device debugger. Families The compilers include a macro assembler, linker, pre- MPLAB Assembler produces relocatable machine processor, and one-step driver, and can run on multiple code from symbolic assembly language for PIC24, platforms. PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler 26.4 MPASM Assembler generates relocatable object files that can then be The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data reference, absolute LST files that contain source lines • Command line interface and generated machine code and COFF files for • Rich directive set debugging. • Flexible macro language The MPASM Assembler features include: • MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS39635C-page 348  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 26.7 MPLAB SIM Software Simulator 26.9 MPLAB ICD 3 In-Circuit Debugger System The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro- ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig- examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU) a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon- logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy- buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated the simulator to record and track program execution, Development Environment (IDE). actions on I/O, most peripherals and internal registers. The MPLAB ICD 3 In-Circuit Debugger probe is con- The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed symbolic debugging using the MPLAB CCompilers, USB 2.0 interface and is connected to the target with a and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers. ronment, making it an excellent, economical software development tool. 26.10 PICkit 3 In-Circuit Debugger/ Programmer and 26.8 MPLAB REAL ICE In-Circuit PICkit 3 Debug Express Emulator System The MPLAB PICkit 3 allows debugging and program- MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected with the easy-to-use, powerful graphical user interface of to the design engineer's PC using a full speed USB the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an included with each kit. Microchip debug (RJ-11) connector (compatible with The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple- to the target with either a connector compatible with in- ment in-circuit debugging and In-Circuit Serial Pro- circuit debugger systems (RJ11) or with the new high- gramming™. speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo (LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software. MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.  2010 Microchip Technology Inc. DS39635C-page 349

PIC18F6310/6410/8310/8410 26.11 PICkit 2 Development 26.13 Demonstration/Development Programmer/Debugger and Boards, Evaluation Kits, and PICkit 2 Debug Express Starter Kits The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func- families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for Windows® programming interface supports baseline adding custom circuitry and provide application firmware (PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification. (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232 microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional products. With Microchip’s powerful MPLAB Integrated EEPROM memory. Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom steps the program while the PIC microcontroller is circuits and for learning about various microcontroller embedded in the application. When halted at a break- applications. point, the file registers can be examined and modified. In addition to the PICDEM™ and dsPICDEM™ demon- The PICkit 2 Debug Express include the PICkit 2, demo stration/development board series of circuits, Microchip board and microcontroller, hookup cables and CDROM has a line of evaluation kits and demonstration software with user’s guide, lessons, tutorial, compiler and for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® MPLAB IDE software. evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. 26.12 MPLAB PM3 Device Programmer Also available are starter kits that contain everything The MPLAB PM3 Device Programmer is a universal, needed to experience the specified device. This usually CE compliant device programmer with programmable includes a single application and debug capability, all voltage verification at VDDMIN and VDDMAX for on one board. maximum reliability. It features a large LCD display Check the Microchip web page (www.microchip.com) (128 x 64) for menus and error messages and a modu- for the complete list of demonstration, development lar, detachable socket assembly to support various and evaluation kits. package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS39635C-page 350  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 27.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR and RA4)..........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2).........................................................................................0V to +13.25V Voltage on RA4 with respect to Vss...............................................................................................................0V to +8.5V Total power dissipation (Note 1)...............................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300mA Maximum current into VDD pin..............................................................................................................................250mA Input clamp current, IIK (VI < 0 or VI > VDD)20mA Output clamp current, IOK (VO < 0 or VO > VDD)20mA Maximum output current sunk by any I/O pin..........................................................................................................25mA Maximum output current sourced by any I/O pin....................................................................................................25mA Maximum current sunk byall ports.......................................................................................................................200mA Maximum current sourced by all ports..................................................................................................................200mA Note1: Power dissipation is calculated as follows: Pdis = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOL x IOL) 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP pin, rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2010 Microchip Technology Inc. DS39635C-page 351

PIC18F6310/6410/8310/8410 FIGURE 27-1: PIC18F6310/6410/8310/8410 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18F6310/6410 PIC18F8310/8410 4.5V e g 4.2V a 4.0V t l o 3.5V V 3.0V 2.5V 2.0V FMAX Frequency FMAX = 20MHz in 8-bit External Memory mode. FMAX = 40MHz in all other modes. FIGURE 27-2: PIC18F6310/6410/8310/8410 VOLTAGE-FREQUENCY GRAPH (EXTENDED) 6.0V 5.5V PIC18F6310/6410 5.0V PIC18F8310/8410 4.5V e g 4.2V a 4.0V t l o 3.5V V 3.0V 2.5V 2.0V FMAX Frequency FMAX = 20MHz in 8-bit External Memory mode. FMAX = 25MHz in all other modes. DS39635C-page 352  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 27-3: PIC18LF6310/6410/8310/8410 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V PIC18LF6310/6410 5.0V PIC18LF8310/8410 4.5V e g 4.2V 4.0V a t l o 3.5V V 3.0V 2.5V 2.0V 4 MHz FMAX Frequency In 8-bit External Memory mode: FMAX = (9.55 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN  4.2V; FMAX = 25MHz, if VDDAPPMIN > 4.2V. In all other modes: FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz; FMAX = 40MHz, if VDDAPPMIN > 4.2V. Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.  2010 Microchip Technology Inc. DS39635C-page 353

PIC18F6310/6410/8310/8410 27.1 DC Characteristics: Supply Voltage PIC18F6310/6410/8310/8410 (Industrial, Extended) PIC18LF6310/6410/8310/8410 (Industrial) PIC18LF6310/6410/8310/8410 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6310/6410/8310/8410 Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Symbol Characteristic Min Typ Max Units Conditions No. VDD Supply Voltage D001 PIC18LFX310/X410 2.0 — 5.5 V PIC18F6310/6410/8310/8410 4.2 — 5.5 V D001B AVDD Analog Supply Voltage VDD – 0.3 VDD + 0.3 — V D001C AVSS AVSS Analog Ground VSS – 0.3 VSS + 0.3 — V Voltage D002 VDR RAM Data Retention 1.5 — — V Voltage(1) D003 VPOR VDD Start Voltage — — 0.7 V See Section5.3 “Power-on Reset (POR)” to Ensure Internal for details Power-on Reset Signal D004 SVDD VDD Rise Rate 0.05 — — V/ms See Section5.3 “Power-on Reset (POR)” to Ensure Internal for details Power-on Reset Signal VBOR Brown-out Reset Voltage D005 BORV<1:0> = 11 1.96 2.06 2.16 V BORV<1:0> = 10 2.64 2.78 2.92 V BORV<1:0> = 01(2) 4.11 4.33 4.55 V BORV<1:0> = 00 4.41 4.64 4.87 V Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. 2: With BOR enabled, full-speed operation (FOSC = 40 MHz) is supported until a BOR occurs. This is valid although VDD may be below the minimum voltage for this frequency. DS39635C-page 354  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 27.2 DC Characteristics: Power-Down and Supply Current PIC18F6310/6410/8310/8410 (Industrial, Extended) PIC18LF6310/6410/8310/8410 (Industrial) PIC18LF6310/6410/8310/8410 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6310/6410/8310/8410 Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Power-Down Current (IPD)(1) PIC18LFX310/X410 0.1 1.0 A -40°C VDD = 2.0V 0.1 1.0 A +25°C (Sleep mode) 0.3 5.0 A +85°C PIC18LFX310/X410 0.1 2.0 A -40°C VDD = 3.0V 0.1 2.0 A +25°C (Sleep mode) 0.3 8.0 A +85°C All devices 0.1 2.0 A -40°C 0.1 2.0 A +25°C VDD = 5.0V 0.4 15 A +85°C (Sleep mode) 11 50 A +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the cur- rent consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins are tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT is enabled/disabled as specified. 3: When operation below -10°C is expected, use the T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. When operation will always be above -10°C, then the low-power Timer1 oscillator may be selected. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications.  2010 Microchip Technology Inc. DS39635C-page 355

PIC18F6310/6410/8310/8410 27.2 DC Characteristics: Power-Down and Supply Current PIC18F6310/6410/8310/8410 (Industrial, Extended) PIC18LF6310/6410/8310/8410 (Industrial) (Continued) PIC18LF6310/6410/8310/8410 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6310/6410/8310/8410 Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) PIC18LFX310/X410 12 26 A -40°C 12 24 A +25°C VDD = 2.0V 12 23 A +85°C PIC18LFX310/X410 32 50 A -40°C 27 48 A +25°C VDD = 3.0V FOSC = 31kHz (RC_RUN mode, 22 46 A +85°C Internal oscillator source) All devices 84 134 A -40°C 82 128 A +25°C VDD = 5.0V 72 122 A +85°C 90 145 A 125°C PIC18LFX310/X410 .26 .8 mA -40°C .26 .8 mA +25°C VDD = 2.0V .26 .8 mA +85°C PIC18LFX310/X410 .48 1.04 mA -40°C .44 .96 mA +25°C VDD = 3.0V FOSC = 1MHz (RC_RUN mode, .48 .88 mA +85°C Internal oscillator source) All devices .88 1.84 mA -40°C .88 1.76 mA +25°C VDD = 5.0V .8 1.68 mA +85°C 1.25 2.2 mA +125°C PIC18LFX310/X410 0.6 1.7 mA -40°C 0.6 1.6 mA +25°C VDD = 2.0V 0.6 1.5 mA +85°C PIC18LFX310/X410 1.0 2.4 mA -40°C 1.0 2.4 mA +25°C VDD = 3.0V FOSC = 4MHz (RC_RUN mode, 1.0 2.4 mA +85°C Internal oscillator source) All devices 2.0 4.2 mA -40°C 2.0 4 mA +25°C VDD = 5.0V 2.0 3.8 mA +85°C 2.7 4.3 mA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the cur- rent consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins are tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT is enabled/disabled as specified. 3: When operation below -10°C is expected, use the T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. When operation will always be above -10°C, then the low-power Timer1 oscillator may be selected. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39635C-page 356  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 27.2 DC Characteristics: Power-Down and Supply Current PIC18F6310/6410/8310/8410 (Industrial, Extended) PIC18LF6310/6410/8310/8410 (Industrial) (Continued) PIC18LF6310/6410/8310/8410 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6310/6410/8310/8410 Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) PIC18LFX310/X410 2.3 6.4 A -40°C 2.5 6.4 A +25°C VDD = 2.0V 2.9 8.8 A +85°C PIC18LFX310/X410 3.6 8.8 A -40°C 3.8 8.8 A +25°C VDD = 3.0V FOSC = 31kHz (RC_IDLE mode, 4.6 12 A +85°C Internal oscillator source) All devices 7.4 16 A -40°C 7.8 13 A +25°C VDD = 5.0V 9.1 29 A +85°C 21 97 A +125°C PIC18LFX310/X410 132 450 A -40°C 140 450 A +25°C VDD = 2.0V 152 450 A +85°C PIC18LFX310/X410 200 600 A -40°C 216 600 A +25°C VDD = 3.0V FOSC = 1MHz (RC_IDLE mode, 252 600 A +85°C Internal oscillator source) All devices 400 990 A -40°C 420 990 A +25°C VDD = 5.0V 440 990 A +85°C 850 1.2 A +125°C PIC18LFX310/X410 272 690 A -40°C 280 690 A +25°C VDD = 2.0V 288 690 A +85°C PIC18LFX310/X410 416 990 A -40°C 432 990 A +25°C VDD = 3.0V FOSC = 4MHz (RC_IDLE mode, 464 990 A +85°C Internal oscillator source) All devices .8 1.9 mA -40°C .9 1.9 mA +25°C VDD = 5.0V .9 1.9 mA +85°C 1.6 2.2 mA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the cur- rent consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins are tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT is enabled/disabled as specified. 3: When operation below -10°C is expected, use the T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. When operation will always be above -10°C, then the low-power Timer1 oscillator may be selected. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications.  2010 Microchip Technology Inc. DS39635C-page 357

PIC18F6310/6410/8310/8410 27.2 DC Characteristics: Power-Down and Supply Current PIC18F6310/6410/8310/8410 (Industrial, Extended) PIC18LF6310/6410/8310/8410 (Industrial) (Continued) PIC18LF6310/6410/8310/8410 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6310/6410/8310/8410 Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) PIC18LFX310/X410 250 500 A -40°C 260 500 A +25°C VDD = 2.0V 250 500 A +85°C PIC18LFX310/X410 550 650 A -40°C 480 650 A +25°C VDD = 3.0V FOSC = 1MHZ (PRI_RUN, 460 650 A +85°C EC oscillator) All devices 1.2 1.6 mA -40°C 1.1 1.5 mA +25°C VDD = 5.0V 1.0 1.4 mA +85°C 1.5 1.9 mA +125°C PIC18LFX310/X410 0.72 2.0 mA -40°C 0.74 2.0 mA +25°C VDD = 2.0V 0.74 2.0 mA +85°C PIC18LFX310/X410 1.3 3.0 mA -40°C 1.3 3.0 mA +25°C VDD = 3.0V FOSC = 4MHz (PRI_RUN, 1.3 3.0 mA +85°C EC oscillator) All devices 2.7 6.0 mA -40°C 2.6 6.0 mA +25°C VDD = 5.0V 2.5 6.0 mA +85°C 4.2 8 mA +125°C All devices 15 35 mA -40°C 16 35 mA +25°C VDD = 4.2V 16 35 mA +85°C FOSC = 40MHZ All devices 21 40 mA -40°C (PRI_RUN, 21 40 mA +25°C EC oscillator) VDD = 5.0V 21 40 mA +85°C 30 50 mA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the cur- rent consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins are tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT is enabled/disabled as specified. 3: When operation below -10°C is expected, use the T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. When operation will always be above -10°C, then the low-power Timer1 oscillator may be selected. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39635C-page 358  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 27.2 DC Characteristics: Power-Down and Supply Current PIC18F6310/6410/8310/8410 (Industrial, Extended) PIC18LF6310/6410/8310/8410 (Industrial) (Continued) PIC18LF6310/6410/8310/8410 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6310/6410/8310/8410 Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) PIC18LFX310/X410 59 117 A -40°C 59 108 A +25°C VDD = 2.0V 63 104 A +85°C PIC18LFX310/X410 108 243 A -40°C 108 225 A +25°C VDD = 3.0V FOSC = 1MHz (PRI_IDLE mode, 117 216 A +85°C EC oscillator) All devices 270 432 A -40°C 216 405 A +25°C VDD = 5.0V 270 387 A +85°C 300 430 A +125°C PIC18LFX310/X410 234 428 A -40°C 230 405 A +25°C VDD = 2.0V 243 387 A +85°C PIC18LFX310/X410 378 810 A -40°C 387 765 A +25°C VDD = 3.0V FOSC = 4MHz (PRI_IDLE mode, 405 729 A +85°C EC oscillator) All devices 0.8 1.35 mA -40°C 0.8 1.26 mA +25°C VDD = 5.0V 0.8 1.17 mA +85°C 1 1.4 mA +125°C All devices 5.4 14.4 mA -40°C 5.6 14.4 mA +25°C VDD = 4.2 V 5.9 14.4 mA +85°C FOSC = 40MHz All devices 7.3 16.2 mA -40°C (PRI_IDLE mode, 8.2 16.2 mA +25°C EC oscillator) VDD = 5.0V 7.5 16.2 mA +85°C 19 18 mA +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the cur- rent consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins are tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT is enabled/disabled as specified. 3: When operation below -10°C is expected, use the T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. When operation will always be above -10°C, then the low-power Timer1 oscillator may be selected. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications.  2010 Microchip Technology Inc. DS39635C-page 359

PIC18F6310/6410/8310/8410 27.2 DC Characteristics: Power-Down and Supply Current PIC18F6310/6410/8310/8410 (Industrial, Extended) PIC18LF6310/6410/8310/8410 (Industrial) (Continued) PIC18LF6310/6410/8310/8410 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6310/6410/8310/8410 Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2,3) All devices 7.5 16 mA -40°C FOSC = 4MHZ, 7.4 15 mA +25°C VDD = 4.2V 16 MHz internal 7.3 14 mA +85°C (PRI_RUN HSPLL mode) All devices 10 21 mA -40°C FOSC = 4MHZ, 10 20 mA +25°C VDD = 5.0V 16 MHz internal 9.7 19 mA +85°C (PRI_RUN HSPLL mode) All devices 17 35 mA -40°C FOSC = 10MHZ, 17 35 mA +25°C VDD = 4.2V 40 MHz internal 17 35 mA +85°C (PRI_RUN HSPLL mode) All devices 23 40 mA -40°C FOSC = 10MHZ, 23 40 mA +25°C VDD = 5.0V 40 MHz internal 23 40 mA +85°C (PRI_RUN HSPLL mode) Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the cur- rent consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins are tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT is enabled/disabled as specified. 3: When operation below -10°C is expected, use the T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. When operation will always be above -10°C, then the low-power Timer1 oscillator may be selected. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39635C-page 360  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 27.2 DC Characteristics: Power-Down and Supply Current PIC18F6310/6410/8310/8410 (Industrial, Extended) PIC18LF6310/6410/8310/8410 (Industrial) (Continued) PIC18LF6310/6410/8310/8410 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6310/6410/8310/8410 Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) PIC18LFX310/X410 13 40 A -10°C 14 40 A +25°C VDD = 2.0V 16 40 A +70°C PIC18LFX310/X410 34 74 A -10°C 31 70 A +25°C VDD = 3.0V FOSC = 32kHz(4) (SEC_RUN mode, 28 67 A +70°C Timer1 as clock) All devices 72 150 A -10°C 65 150 A +25°C VDD = 5.0V 59 150 A +70°C 90 170 A +125°C PIC18LFX310/X410 5.5 15 A -10°C 5.8 15 A +25°C VDD = 2.0V 6.1 18 A +70°C PIC18LFX310/X410 8.2 30 A -10°C 8.6 30 A +25°C VDD = 3.0V FOSC = 32kHz(4) (SEC_IDLE mode, 8.8 35 A +70°C Timer1 as clock) All devices 13 80 A -10°C 13 80 A +25°C VDD = 5.0V 13 85 A +70°C 22 90 A +125°C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the cur- rent consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins are tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT is enabled/disabled as specified. 3: When operation below -10°C is expected, use the T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. When operation will always be above -10°C, then the low-power Timer1 oscillator may be selected. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications.  2010 Microchip Technology Inc. DS39635C-page 361

PIC18F6310/6410/8310/8410 27.2 DC Characteristics: Power-Down and Supply Current PIC18F6310/6410/8310/8410 (Industrial, Extended) PIC18LF6310/6410/8310/8410 (Industrial) (Continued) PIC18LF6310/6410/8310/8410 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6310/6410/8310/8410 Operating temperature -40°C  TA  +85°C for industrial (Industrial, Extended) -40°C  TA  +125°C for extended Param Device Typ Max Units Conditions No. Module Differential Currents (IWDT, IBOR, ILVD, IOSCB, IAD) D022 Watchdog Timer 1.7 4.0 A -40°C (IWDT) 2.1 4.0 A +25°C VDD = 2.0V 2.6 5.0 A +85°C 2.2 6.0 A -40°C 2.4 6.0 A +25°C VDD = 3.0V 2.8 7.0 A +85°C 2.9 10.0 A -40°C 3.1 10.0 A +25°C VDD = 5.0V 3.3 13.0 A +85°C 20 190 A +125°C D022A Brown-out Reset (4) 17 50.0 A -40C to +85C VDD = 3.0V (IBOR) 47 60.0 A -40C to +85C VDD = 5.0V 90 200 A -40C to +125C D022B High/Low-Voltage Detect (4) 14 38.0 A -40C to +85C VDD = 2.0V (ILVD) 18 40.0 A -40C to +85C VDD = 3.0V 21 45.0 A -40C to +85C VDD = 5.0V 90 2000 A -40C to +125C D025 Timer1 Oscillator 1.0 3.5 A -40C 32kHz on Timer1(4) (IOSCB) 1.1 3.5 A +25C VDD = 2.0V 1.1 4.5 A +70C 1.2 4.5 A -40C 32kHz on Timer1(4) 1.3 4.5 A +25C VDD = 3.0V 1.2 5.5 A +70C 1.8 6.0 A -40C 1.9 6.0 A +25C VDD = 5.0V 32kHz on Timer1(4) 1.9 7.0 A +85C D026 A/D Converter 1.0 3.0 A — VDD = 2.0V (IAD) 1.0 4.0 A — VDD = 3.0V A/D on, not converting, 1.0 8.0 A — 1.6s  TAD  6.4s VDD = 5.0V 15 60 A +125C Legend: Shading of rows is to assist in readability of the table. Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the cur- rent consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins are tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT is enabled/disabled as specified. 3: When operation below -10°C is expected, use the T1OSC High-Power mode, where LPT1OSC (CONFIG3H<2>) = 0. When operation will always be above -10°C, then the low-power Timer1 oscillator may be selected. 4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39635C-page 362  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 27.3 DC Characteristics: PIC18F6310/6410/8310/8410 (Industrial, Extended) PIC18LF6310/6410/8310/8410 (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for industrial -40°C TA  +125°C for extended Param Symbol Characteristic Min Max Units Conditions No. VIL Input Low Voltage I/O Ports: D030 with TTL Buffer VSS 0.15 VDD V VDD < 4.5V D030A — 0.8 V 4.5V  VDD 5.5V D031 with Schmitt Trigger Buffer VSS 0.2 VDD V D031A RC3 and RC4 VSS 0.3 VDD V I2C™ enabled D031B VSS 0.8 V SMBus enabled D032 MCLR VSS 0.2 VDD V D033 OSC1 VSS 0.3 VDD V HS, HSPLL modes D033A OSC1 VSS 0.2 VDD V RC, EC modes(1) D033B OSC1 VSS 0.3 V XT, LP modes D034 T13CKI VSS 0.3 V VIH Input High Voltage I/O Ports: D040 with TTL Buffer 0.25 VDD + 0.8V VDD V VDD < 4.5V D040A 2.0 VDD V 4.5V  VDD 5.5V D041 with Schmitt Trigger Buffer 0.8 VDD VDD V D041A RC3 and RC4 0.7 VDD VDD V I2C enabled D041B 2.1 VDD V SMBus enabled D042 MCLR 0.8 VDD VDD V D043 OSC1 0.7 VDD VDD V HS, HSPLL modes D043A OSC1 0.8 VDD VDD V EC mode D043B OSC1 0.9 VDD VDD V RC mode(1) D043C OSC1 1.6 VDD V XT, LP modes D044 T13CKI 1.6 VDD V IIL Input Leakage Current(2,3) D060 I/O Ports — 200 nA VDD < 5.5V VSS ≤ VPIN ≤ VDD, Pin at high-impedance 50 nA VDD < 3V VSS ≤ VPIN ≤ VDD, Pin at high-impedance D061 MCLR — 1 A Vss VPIN VDD D063 OSC1 — 1 A Vss VPIN VDD IPU Weak Pull-up Current D070 IPURB PORTB Weak Pull-up Current 50 400 A VDD = 5V, VPIN = VSS Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  2010 Microchip Technology Inc. DS39635C-page 363

PIC18F6310/6410/8310/8410 27.3 DC Characteristics: PIC18F6310/6410/8310/8410 (Industrial, Extended) PIC18LF6310/6410/8310/8410 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for industrial -40°C TA  +125°C for extended Param Symbol Characteristic Min Max Units Conditions No. VOL Output Low Voltage D080 I/O Ports — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C D083 OSC2/CLKO — 0.6 V IOL = 1.6 mA, VDD = 4.5V, (RC, RCIO, EC, ECIO modes) -40C to +85C VOH Output High Voltage(3) D090 I/O Ports VDD – 0.7 — V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C D092 OSC2/CLKO VDD – 0.7 — V IOH = -1.3 mA, VDD = 4.5V, (RC, RCIO, EC, ECIO modes) -40C to +85C Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O pins and OSC2 — 50 pF To meet the AC Timing (in RC mode) Specifications D102 CB SCL, SDA — 400 pF I2C™ Specification Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS39635C-page 364  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 27-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) DC Characteristics Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. Program Flash Memory D110 VPP Voltage on MCLR/VPP pin 10.0 — 12.0 V D113 IDDP Supply Current during — — 1 mA Programming D130 EP Cell Endurance — 1K — E/W -40C to +85C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132 VIE VDD for Block Erase 2.75 — 5.5 V Using ICSP port D132A VIW VDD for Externally Timed Erase 2.75 — 5.5 V Using ICSP port or Write D132B VPEW VDD for Self-timed Write VMIN — 5.5 V VMIN = Minimum operating voltage D133 TIE ICSP™ Block Erase Cycle Time — 4 — ms VDD > 4.5V D133A TIW ICSP Erase or Write Cycle Time 2 — — ms VDD > 4.5V (externally timed) D133A TIW Self-Timed Write Cycle Time — 2 — ms D134 TRETD Characteristic Retention 40 100 — Year Provided no other specifications are violated † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2010 Microchip Technology Inc. DS39635C-page 365

PIC18F6310/6410/8310/8410 TABLE 27-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C, unless otherwise stated. Param Sym Characteristics Min Typ Max Units Comments No. D300 VIOFF Input Offset Voltage — ±5.0 ±10 mV D301 VICM Input Common Mode Voltage 0 — VDD – 1.5 V D302 CMRR Common Mode Rejection Ratio 55 — — dB D303 TRESP Response Time(1) — 150 400 ns PIC18FXXXX D303A — 150 600 ns PIC18LFXXXX, VDD = 2.0V D304 TMC2OV Comparator Mode Change to — — 10 s Output Valid Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. TABLE 27-3: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C, unless otherwise stated. Param Sym Characteristics Min Typ Max Units Comments No. D310 VRES Resolution VDD/24 — VDD/32 LSb D311 VRAA Absolute Accuracy — — 1/4 LSb Low Range (CVRR = 1) — — 1/2 LSb High Range (CVRR = 0) D312 VRUR Unit Resistor Value (R) — 2k —  310 TSET Settling Time(1) — — 10 s Note 1: Settling time measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’. DS39635C-page 366  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 27-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS For VDIRMAG = 1: VDD VHLVD (HLVDIF set by hardware) (HLVDIF can be cleared in software) VHLVD For VDIRMAG = 0: VDD HLVDIF TABLE 27-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial Param Symbol Characteristic Min Typ† Max Units Conditions No. D420 HLVD Voltage on VDD LVV = 0000 1.80 1.86 1.91 V Transition LVV = 0001 1.96 2.06 2.06 V LVV = 0010 2.16 2.27 2.38 V LVV = 0011 2.35 2.47 2.59 V LVV = 0100 2.43 2.56 2.69 V LVV = 0101 2.64 2.78 2.92 V LVV = 0110 2.75 2.89 3.03 V LVV = 0111 2.95 3.10 3.26 V LVV = 1000 3.24 3.41 3.58 V LVV = 1001 3.43 3.61 3.79 V LVV = 1010 3.53 3.72 3.91 V LVV = 1011 3.72 3.92 4.12 V LVV = 1100 3.92 4.13 4.34 V LVV = 1101 4.11 4.33 4.55 V LVV = 1110 4.41 4.64 4.87 V D420B VBG Band Gap Reference LVV = 1111 — 1.20 — V HLVDIN input external Voltage Value † Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization.  2010 Microchip Technology Inc. DS39635C-page 367

PIC18F6310/6410/8310/8410 27.4 AC (Timing) Characteristics 27.4.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T13CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO Stop condition STA Start condition DS39635C-page 368  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 27.4.2 TIMING CONDITIONS Note: Because of space limitations, the generic The temperature and voltages specified in Table27-5 terms “PIC18FXXXX” and apply to all timing specifications unless otherwise “PIC18LFXXXX” are used throughout this noted. Figure27-5 specifies the load conditions for the section to refer to the PIC18F6310/6410/ timing specifications. 8310/8410 and PIC18LF6310/6410/8310/ 8410 families of devices specifically and only those devices. TABLE 27-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA +85°C for industrial -40°C  TA +125°C for extended AC CHARACTERISTICS Operating voltage VDD range as described in DC spec, Section27.1 and Section27.3. LF parts operate for industrial temperatures only. FIGURE 27-5: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 Load Condition 2 VDD/2 RL Pin CL VSS CL Pin RL = 464 VSS CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports  2010 Microchip Technology Inc. DS39635C-page 369

PIC18F6310/6410/8310/8410 27.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 27-6: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO TABLE 27-6: EXTERNAL CLOCK TIMING REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 1A FOSC External CLKI Frequency(1) DC 1 MHz XT, RC Oscillator mode DC 25 MHz HS Oscillator mode DC 31.25 kHz LP Oscillator mode DC 40 MHz EC Oscillator mode Oscillator Frequency(1) DC 4 MHz RC Oscillator mode 0.1 4 MHz XT Oscillator mode 4 25 MHz HS Oscillator mode 4 10 MHz HS + PLL Oscillator mode 5 200 kHz LP Oscillator mode 1 TOSC External CLKI Period(1) 1000 — ns XT, RC Oscillator mode 40 — ns HS Oscillator mode 32 — s LP Oscillator mode 25 — ns EC Oscillator mode Oscillator Period(1) 250 — ns RC Oscillator mode 0.25 10 s XT Oscillator mode 40 250 ns HS Oscillator mode 100 250 ns HS + PLL Oscillator mode 5 200 s LP Oscillator mode 2 TCY Instruction Cycle Time(1) 100 — ns TCY = 4/FOSC, Industrial 160 — ns TCY = 4/FOSC, Extended 3 TOSL, External Clock in (OSC1) 30 — ns XT Oscillator mode TOSH High or Low Time 2.5 — s LP Oscillator mode 10 — ns HS Oscillator mode 4 TOSR, External Clock in (OSC1) — 20 ns XT Oscillator mode TOSF Rise or Fall Time — 50 ns LP Oscillator mode — 7.5 ns HS Oscillator mode Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. DS39635C-page 370  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 27-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V) Param Sym Characteristic Min Typ† Max Units Conditions No. F10 FOSC Oscillator Frequency Range 4 — 10 MHz HS mode only F11 FSYS On-Chip VCO System Frequency 16 — 40 MHz HS mode only F12 t PLL Start-up Time (Lock Time) — — 2 ms rc F13 CLK CLKO Stability (Jitter) -2 — +2 % † Data in “Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 27-8: AC CHARACTERISTICS: INTERNAL RC ACCURACY PIC18F6310/6410/8310/8410 (INDUSTRIAL) PIC18LF6310/6410/8310/8410 (INDUSTRIAL) PIC18LF6310/6410/8310/8410 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C  TA  +85°C for industrial Standard Operating Conditions (unless otherwise stated) PIC18F6310/6410/8310/8410 Operating temperature -40°C  TA  +85°C for industrial (Industrial) -40°C  TA  +125°C for extended Param Device Min Typ Max Units Conditions No. INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1) PIC18LF6310/6410/8310/8410 -2 +/-1 2 % +25°C VDD = 2.7-3.3 V -5 — 5 % -10°C to +85°C VDD = 2.7-3.3 V -10 +/-1 10 % -40°C to +85°C VDD = 2.7-3.3 V PIC18F6310/6410/8310/8410 -2 +/-1 2 % +25°C VDD = 4.5-5.5 V -5 — 5 % -10°C to +85°C VDD = 4.5-5.5 V -10 +/-1 10 % -40°C to +85°C VDD = 4.5-5.5 V INTRC Accuracy @ Freq = 31 kHz(2) PIC18LF6310/6410/8310/8410 26.562 — 35.938 kHz -40°C to +85°C VDD = 2.7-3.3 V PIC18F6310/6410/8310/8410 26.562 — 35.938 kHz -40°C to +85°C VDD = 4.5-5.5 V Legend: Shading of rows is to assist in readability of the table. Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift. 2: INTRC frequency after calibration.  2010 Microchip Technology Inc. DS39635C-page 371

PIC18F6310/6410/8310/8410 FIGURE 27-7: CLKO AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKO 13 12 14 19 18 16 I/O pin (Input) 17 15 I/O pin Old Value New Value (Output) 20, 21 TABLE 27-9: CLKO AND I/O TIMING REQUIREMENTS Param Symbol Characteristic Min Typ Max Units Conditions No. 10 TOSH2CKL OSC1  to CLKO  — 75 200 ns (Note 1) 11 TOSH2CKH OSC1  to CLKO  — 75 200 ns (Note 1) 12 TCKR CLKO Rise Time — 35 100 ns (Note 1) 13 TCKF CLKO Fall Time — 35 100 ns (Note 1) 14 TCKL2IOV CLKO  to Port Out Valid — — 0.5 TCY + 20 ns (Note 1) 15 TIOV2CKH Port In Valid before CLKO  0.25 TCY + 25 — — ns (Note 1) 16 TCKH2IOI Port In Hold after CLKO  0 — — ns (Note 1) 17 TOSH2IOV OSC1 (Q1 cycle) to Port Out Valid — 50 150 ns 18 TOSH2IOI OSC1 (Q2 cycle) to PIC18FXXXX 100 — — ns Port Input Invalid 18A PIC18LFXXXX 200 — — ns VDD = 2.0V (I/O in hold time) 19 TIOV2OSH Port Input Valid to OSC1(I/O in setup time) 0 — — ns 20 TIOR Port Output Rise Time PIC18FXXXX — 10 25 ns 20A PIC18LFXXXX — — 60 ns VDD = 2.0V 21 TIOF Port Output Fall Time PIC18FXXXX — 10 25 ns 21A PIC18LFXXXX — — 60 ns VDD = 2.0V 22† TINP INTx pin High or Low Time TCY — — ns 23† TRBP RB<7:4> Change INTx High or Low Time TCY — — ns † These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC. DS39635C-page 372  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 27-8: PROGRAM MEMORY READ TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 AD<19:16> Address Address BA0 AD<15:0> Address Data from External Address 150 160 163 151 162 161 155 166 167 168 ALE 164 169 171 CE 171A OE 165 TABLE 27-10: PROGRAM MEMORY READ TIMING REQUIREMENTS Param. Symbol Characteristics Min Typ Max Units No 150 TadV2alL Address Out Valid to ALE (address 0.25 TCY – 10 — — ns setup time) 151 TalL2adl ALE  to Address Out Invalid (address hold 5 — — ns time) 155 TalL2oeL ALE to OE  10 0.125 TCY — ns 160 TadZ2oeL AD high-Z to OE (bus release to OE) 0 — — ns 161 ToeH2adD OE  to AD Driven 0.125 TCY – 5 — — ns 162 TadV2oeH LS Data Valid before OE (data setup time) 20 — — ns 163 ToeH2adl OE  to Data In Invalid (data hold time) 0 — — ns 164 TalH2alL ALE Pulse Width — TCY — ns 165 ToeL2oeH OE Pulse Width 0.5 TCY – 5 0.5 TCY — ns 166 TalH2alH ALE  to ALE  (cycle time) — 0.25 TCY — ns 167 Tacc Address Valid to Data Valid 0.75 TCY – 25 — — ns 168 Toe OE  to Data Valid — 0.5 TCY – 25 ns 169 TalL2oeH ALE to OE  0.625 TCY – 10 — 0.625 TCY + 10 ns 171 TalH2csL Chip Enable Active to ALE  0.25 TCY – 20 — — ns 171A TubL2oeH AD Valid to Chip Enable Active — — 10 ns  2010 Microchip Technology Inc. DS39635C-page 373

PIC18F6310/6410/8310/8410 FIGURE 27-9: PROGRAM MEMORY WRITE TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 AD<19:16> Address Address BA0 166 AD<15:0> Address Data Address 153 150 156 151 ALE 171 CE 171A 154 WRH or WRL 157 157A UB or LB TABLE 27-11: PROGRAM MEMORY WRITE TIMING REQUIREMENTS Param. Symbol Characteristics Min Typ Max Units No 150 TadV2alL Address Out Valid to ALE (address setup time) 0.25 TCY – 10 — — ns 151 TalL2adl ALE  to Address Out Invalid (address hold time) 5 — — ns 153 TwrH2adl WRn  to Data Out Invalid (data hold time) 5 — — ns 154 TwrL WRn Pulse Width 0.5 TCY – 5 0.5 TCY — ns 156 TadV2wrH Data Valid before WRn (data setup time) 0.5 TCY – 10 — — ns 157 TbsV2wrL Byte Select Valid before WRn (byte select setup 0.25 TCY — — ns time) 157A TwrH2bsI WRn  to Byte Select Invalid (byte select hold time) 0.125 TCY – 5 — — ns 166 TalH2alH ALE  to ALE  (cycle time) — 0.25 TCY — ns 171 TalH2csL Chip Enable Active to ALE  0.25 TCY – 20 — — ns 171A TubL2oeH AD Valid to Chip Enable Active — — 10 ns DS39635C-page 374  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 27-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins FIGURE 27-11: BROWN-OUT RESET TIMING BVDD VDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference 36 Voltage Stable TABLE 27-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol Characteristic Min Typ Max Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — s 31 TWDT Watchdog Timer Time-out Period 3.4 4.1 4.71 ms (no postscaler) 32 TOST Oscillator Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period 33 TPWRT Power-up Timer Period 55.5 65.5 75 ms 34 TIOZ I/O High-Impedance from MCLR — 2 — s Low or Watchdog Timer Reset 35 TBOR Brown-out Reset Pulse Width 200 — — s VDD  BVDD (see D005) 36 TIRVST Time for Internal Reference — 20 50 s Voltage to become stable 37 TLVD Low-Voltage Detect Pulse Width 200 — — s VDD  VLVD 38 TCSD CPU Start-up Time — 10 — s 39 TIOBST Time for INTRC Block to stabilize — 1 — ms  2010 Microchip Technology Inc. DS39635C-page 375

PIC18F6310/6410/8310/8410 FIGURE 27-12: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1OSO/T13CKI 45 46 47 48 TMR0 or TMR1 TABLE 27-13: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 40 TT0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 41 TT0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 42 TT0P T0CKI Period No prescaler TCY + 10 — ns With prescaler Greater of: — ns N = prescale 20ns or value (TCY + 40)/N (1, 2, 4,..., 256) 45 TT1H T13CKI Synchronous, no prescaler 0.5 TCY + 20 — ns High Time Synchronous, PIC18FXXXX 10 — ns with prescaler PIC18LFXXXX 25 — ns VDD = 2.0V Asynchronous PIC18FXXXX 30 — ns PIC18LFXXXX 50 — ns VDD = 2.0V 46 TT1L T13CKI Synchronous, no prescaler 0.5 TCY + 5 — ns Low Time Synchronous, PIC18FXXXX 10 — ns with prescaler PIC18LFXXXX 25 — ns VDD = 2.0V Asynchronous PIC18FXXXX 30 — ns PIC18LFXXXX 50 — ns VDD = 2.0V 47 TT1P T13CKI Synchronous Greater of: — ns N = prescale Input 20ns or value Period (TCY + 40)/N (1, 2, 4, 8) Asynchronous 60 — ns FT1 T13CKI Oscillator Input Frequency Range DC 50 kHz 48 TCKE2TMRI Delay from External T13CKI Clock Edge to 2 TOSC 7 TOSC — Timer Increment DS39635C-page 376  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 27-13: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 TABLE 27-14: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param Symbol Characteristic Min Max Units Conditions No. 50 TCCL CCPx Input Low No prescaler 0.5 TCY + 20 — ns Time With PIC18FXXXX 10 — ns prescaler PIC18LFXXXX 20 — ns VDD = 2.0V 51 TCCH CCPx Input No prescaler 0.5 TCY + 20 — ns High Time With PIC18FXXXX 10 — ns prescaler PIC18LFXXXX 20 — ns VDD = 2.0V 52 TCCP CCPx Input Period 3 TCY + 40 — ns N = prescale N value (1, 4 or 16) 53 TCCR CCPx Output Fall Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 54 TCCF CCPx Output Fall Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V  2010 Microchip Technology Inc. DS39635C-page 377

PIC18F6310/6410/8310/8410 FIGURE 27-14: EXAMPLE SPI MASTER MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 78 79 SCK (CKP = 1) 79 78 80 SDO MSb bit 6 - - - - - - 1 LSb 75, 76 SDI MSb In bit 6 - - - - 1 LSb In 74 73 TABLE 27-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SS  to SCK  or SCK  Input TCY — ns TSSL2SCL 73 TDIV2SCH, Setup Time of SDI Data Input to SCK Edge 100 — ns TDIV2SCL 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 40 — ns TSCL2DIL 75 TDOR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 76 TDOF SDO Data Output Fall Time — 25 ns 78 TSCR SCK Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 79 TSCF SCK Output Fall Time — 25 ns 80 TSCH2DOV, SDO Data Output Valid after PIC18FXXXX — 50 ns TSCL2DOV SCK Edge PIC18LFXXXX — 100 ns VDD = 2.0V DS39635C-page 378  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 27-15: EXAMPLE SPI MASTER MODE TIMING (CKE=1) SS 81 SCK (CKP = 0) 79 73 SCK (CKP = 1) 80 78 SDO MSb bit 6 - - - - - - 1 LSb 75, 76 SDI MSb In bit 6 - - - - 1 LSb In 74 TABLE 27-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=1) Param. Symbol Characteristic Min Max Units Conditions No. 73 TDIV2SCH, Setup Time of SDI Data Input to SCK Edge 20 — ns TDIV2SCL 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 40 — ns TSCL2DIL 75 TDOR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 76 TDOF SDO Data Output Fall Time — 25 ns 78 TSCR SCK Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 79 TSCF SCK Output Fall Time — 25 ns 80 TSCH2DOV, SDO Data Output Valid after PIC18FXXXX — 50 ns TSCL2DOV SCK Edge PIC18LFXXXX — 100 ns VDD = 2.0V 81 TDOV2SCH, SDO Data Output Setup to SCK Edge TCY — ns TDOV2SCL  2010 Microchip Technology Inc. DS39635C-page 379

PIC18F6310/6410/8310/8410 FIGURE 27-16: EXAMPLE SPI SLAVE MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 83 71 72 SCK (CKP = 1) 80 SDO MSb bit 6 - - - - - - 1 LSb 75, 76 77 SSDDII MSb In bit 6 - - - - 1 LSb In 74 73 TABLE 27-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SS  to SCK  or SCK  Input TCY — ns TSSL2SCL 71 TSCH SCK Input High Time Continuous 1.25 TCY + 30 — ns 71A Single Byte 40 — ns (Note 1) 72 TSCL SCK Input Low Time Continuous 1.25 TCY + 30 — ns 72A Single Byte 40 — ns (Note 1) 73 TDIV2SCH, Setup Time of SDI Data Input to SCK Edge 20 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 40 — ns TSCL2DIL 75 TDOR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 76 TDOF SDO Data Output Fall Time — 25 ns 77 TSSH2DOZ SS  to SDO Output High-impedance 10 50 ns 80 TSCH2DOV, SDO Data Output Valid after SCK Edge PIC18FXXXX — 50 ns TSCL2DOV PIC18LFXXXX — 100 ns VDD = 2.0V 83 TSCH2SSH, SS  after SCK Edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. DS39635C-page 380  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 FIGURE 27-17: EXAMPLE SPI SLAVE MODE TIMING (CKE=1) 82 SS 70 SCK 83 (CKP = 0) 71 72 SCK (CKP = 1) 80 SDO MSb bit 6 - - - - - - 1 LSb 75, 76 77 SSDDII MSb In bit 6 - - - - 1 LSb In 74 TABLE 27-18: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE=1) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SS  to SCK  or SCK  Input TCY — ns TSSL2SCL 71 TSCH SCK Input High Time Continuous 1.25 TCY + 30 — ns 71A Single Byte 40 — ns (Note 1) 72 TSCL SCK Input Low Time Continuous 1.25 TCY + 30 — ns 72A Single Byte 40 — ns (Note 1) 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 40 — ns TSCL2DIL 75 TDOR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 76 TDOF SDO Data Output Fall Time — 25 ns 77 TSSH2DOZ SS to SDO Output High-Impedance 10 50 ns 80 TSCH2DOV, SDO Data Output Valid after SCK PIC18FXXXX — 50 ns TSCL2DOV Edge PIC18LFXXXX — 100 ns VDD = 2.0V 82 TSSL2DOV SDO Data Output Valid after SS  PIC18FXXXX — 50 ns Edge PIC18LFXXXX — 100 ns VDD = 2.0V 83 TSCH2SSH, SS  after SCK Edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used.  2010 Microchip Technology Inc. DS39635C-page 381

PIC18F6310/6410/8310/8410 FIGURE 27-18: I2C™ BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Start Stop Condition Condition TABLE 27-19: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated Setup Time 400 kHz mode 600 — Start condition 91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first Hold Time 400 kHz mode 600 — clock pulse is generated 92 TSU:STO Stop Condition 100 kHz mode 4700 — ns Setup Time 400 kHz mode 600 — 93 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — FIGURE 27-19: I2C™ BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out DS39635C-page 382  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 27-20: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 4.0 — s PIC18FXXXX must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s PIC18FXXXX must operate at a minimum of 10 MHz MSSP Module 1.5 TCY — 101 TLOW Clock Low Time 100 kHz mode 4.7 — s PIC18FXXXX must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s PIC18FXXXX must operate at a minimum of 10 MHz MSSP Module 1.5 TCY — 102 TR SDA and SCL Rise Time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDA and SCL Fall Time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 90 TSU:STA Start Condition Setup Time 100 kHz mode 4.7 — s Only relevant for Repeated 400 kHz mode 0.6 — s Start condition 91 THD:STA Start Condition Hold Time 100 kHz mode 4.0 — s After this period, the first clock 400 kHz mode 0.6 — s pulse is generated 106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns (Note 2) 400 kHz mode 100 — ns 92 TSU:STO Stop Condition Setup Time 100 kHz mode 4.7 — s 400 kHz mode 0.6 — s 109 TAA Output Valid from Clock 100 kHz mode — 3500 ns (Note 1) 400 kHz mode — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start D102 CB Bus Capacitive Loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement, TSU:DAT250ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, TR max. + TSU:DAT=1000+250=1250ns (according to the Standard mode I2C bus specification), before the SCL line is released.  2010 Microchip Technology Inc. DS39635C-page 383

PIC18F6310/6410/8310/8410 FIGURE 27-20: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCL 91 93 90 92 SDA Start Stop Condition Condition TABLE 27-21: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — first clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — Note 1: Maximum pin capacitance = 10 pF for all I2C pins. FIGURE 27-21: MASTER SSP I2C™ BUS DATA TIMING 103 100 102 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out DS39635C-page 384  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 27-22: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 102 TR SDA and SCL 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns 103 TF SDA and SCL 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — ms clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 106 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 ms 107 TSU:DAT Data Input 100 kHz mode 250 — ns (Note 2) Setup Time 400 kHz mode 100 — ns 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 109 TAA Output Valid 100 kHz mode — 3500 ns from Clock 400 kHz mode — 1000 ns 1 MHz mode(1) — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — ms Time the bus must be free before a new transmission 400 kHz mode 1.3 — ms can start D102 CB Bus Capacitive Loading — 400 pF Note 1: Maximum pin capacitance = 10 pF for all I2C pins. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but Parameter #107250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, Parameter #102 + Parameter #107=1000+250=1250ns (for 100 kHz mode,) before the SCL line is released.  2010 Microchip Technology Inc. DS39635C-page 385

PIC18F6310/6410/8310/8410 FIGURE 27-22: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX1/CK1 pin 121 121 RC7/RX1/DT1 pin 120 122 TABLE 27-23: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 120 TCKH2DTV SYNC XMIT (MASTER and SLAVE) Clock High to Data Out Valid PIC18FXXXX — 40 ns PIC18LFXXXX — 100 ns VDD = 2.0V 121 TCKRF Clock Out Rise Time and Fall Time PIC18FXXXX — 20 ns (Master mode) PIC18LFXXXX — 50 ns VDD = 2.0V 122 TDTRF Data Out Rise Time and Fall Time PIC18FXXXX — 20 ns PIC18LFXXXX — 50 ns VDD = 2.0V FIGURE 27-23: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX1/CK1 Pin 125 RC7/RX1/DT1 Pin 126 TABLE 27-24: USART SYNCHRONOUS RECEIVE REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 125 TDTV2CKL SYNC RCV (MASTER and SLAVE) Data Hold before CKx  (DTx hold time) 10 — ns 126 TCKL2DTL Data Hold after CKx  (DTx hold time) 15 — ns DS39635C-page 386  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TABLE 27-25: A/D CONVERTER CHARACTERISTICS: PIC18F6310/6410/8310/8410 (INDUSTRIAL) PIC18LF6310/6410/8310/8410 (INDUSTRIAL) Param Sym Characteristic Min Typ Max Units Conditions No. A01 NR Resolution — — 10 bit VREF  3.0V A03 EIL Integral Linearity Error — — <±1 LSb VREF  3.0V A04 EDL Differential Linearity Error — — <±1 LSb VREF  3.0V A06 EOFF Offset Error — — <±1 LSb VREF  3.0V A07 EGN Gain Error — — <±1 LSb VREF  3.0V A10 — Monotonicity Guaranteed(1) — A20 VREF Reference Voltage Range 3 — AVDD – AVSS V VDD  3.0V (VREFH – VREFL) 1.8 — VDD – VSS V VDD < 3.0V A21 VREFH Reference Voltage High AVSS + VREF — AVDD V For 10-bit resolution A22 VREFL Reference Voltage Low AVSS — AVDD – VREF V For 10-bit resolution A25 VAIN Analog Input Voltage VREFL — VREFH V A28 AVDD Analog Supply Voltage VDD – 0.3 — VDD + 0.3 V A29 AVSS Analog Supply Voltage VSS – 0.3 — VSS + 0.3 V A30 ZAIN Recommended Impedance of — — 2.5 k Analog Voltage Source A40 IAD A/D Conversion PIC18FXXXX — 180 — A Average current Current (VDD) consumption when A/D is on (Note 2) PIC18LFXXXX — 90 — A VDD = 2.0V; Average current consumption when A/D is on (Note 2) A50 IREF VREF Input Current (Note 3) — — ±5 A During VAIN acquisition. — — ±150 A During A/D conversion cycle. Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2: When A/D is off, it will not consume any current other than minor leakage current. The power-down current specification includes any such leakage from the A/D module. 3: VREFH current is from the RA3/AN3/VREF+ pin or AVDD, whichever is selected as the VREFH source. VREFL current is from the RA2/AN2/VREF- pin or AVSS, whichever is selected as the VREFL source.  2010 Microchip Technology Inc. DS39635C-page 387

PIC18F6310/6410/8310/8410 FIGURE 27-24: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK(1) 132 . . . . . . A/D DATA 9 8 7 2 1 0 ADRES OLD_DATA NEW_DATA ADIF TCY GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. TABLE 27-26: A/D CONVERSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 130 TAD A/D Clock Period PIC18FXXXX 0.7 25.0(1) s TOSC based, VREF  3.0V PIC18LFXXXX 1.4 25.0(1) s VDD = 2.0V; TOSC based, VREF full range PIC18FXXXX — 1 s A/D RC mode PIC18LFXXXX — 3 s VDD = 2.0V; A/D RC mode 131 TCNV Conversion Time 11 12 TAD (not including acquisition time) (Note 2) 132 TACQ Acquisition Time (Note 3) 1.4 — s -40C to +85C 135 TSWC Switching Time from Convert  Sample — (Note 4) 137 TDIS Discharge Time 0.2 — s Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. 2: ADRES register may be read on the following TCY cycle. 3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (AVDD to AVSS or AVSS to AVDD). The source impedance (RS) on the input channels is 50. 4: On the following cycle of the device clock. DS39635C-page 388  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 64-Lead TQFP Example XXXXXXXXXX PIC18F6410 XXXXXXXXXX -I/PTe3 XXXXXXXXXX 1010017 YYWWNNN 80-Lead TQFP Example XXXXXXXXXXXX PIC18F8410 XXXXXXXXXXXX -E/PTe3 YYWWNNN 1010017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010 Microchip Technology Inc. DS39635C-page 389

PIC18F6310/6410/8310/8410 28.2 Package Details The following sections give the technical details of the packages. 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(cid:21) (cid:4)(cid:30)(cid:4)(cid:6) = (cid:4)(cid:30)(cid:17)(cid:4) 7(cid:13)(cid:11)#(cid:14)?(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:15)(cid:18) (cid:4)(cid:30)(cid:17)(cid:17) (cid:4)(cid:30)(cid:17)(cid:18) (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)(cid:25)(cid:23)(cid:10) (cid:4) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)1(cid:23)&&(cid:23)’ (cid:5) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> ’ (cid:13)(cid:6)(cid:12)( (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) +(cid:24)(cid:11)’%(cid:13)(cid:22)!(cid:14)(cid:11)&(cid:14)(cid:21)(cid:23)(cid:22)(cid:26)(cid:13)(cid:22)!(cid:14)(cid:11)(cid:22)(cid:13)(cid:14)(cid:23)(cid:10)&(cid:20)(cid:23)(cid:26)(cid:11)(cid:27),(cid:14)!(cid:20)-(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)(cid:30) (cid:16)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)!(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:26)#(cid:14).(cid:15)(cid:14)#(cid:23)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:20)(cid:26)(cid:21)(cid:27)"#(cid:13)(cid:14)’(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:30)(cid:14)(cid:19)(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:14)!(cid:24)(cid:11)(cid:27)(cid:27)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:13)$(cid:21)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:30)(cid:17)/(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)!(cid:20)#(cid:13)(cid:30) (cid:5)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19).(cid:14)0(cid:15)(cid:5)(cid:30)/(cid:19)(cid:30) 1(cid:3)+2 1(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8).32 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)+(cid:4)(cid:5)(cid:9)(cid:4)@/1 DS39635C-page 390  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)(cid:28)(cid:29)(cid:27)(cid:28)(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)  2010 Microchip Technology Inc. DS39635C-page 391

PIC18F6310/6410/8310/8410 )(cid:28)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)#(cid:29)(cid:27)#(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) D D1 E e E1 b N NOTE1 123 NOTE2 α A c φ β A1 A2 L L1 6(cid:26)(cid:20)&! (cid:19)(cid:29)77(cid:29)(cid:19).(cid:25).(cid:8)(cid:3) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:14)7(cid:20)’(cid:20)&! (cid:19)(cid:29)8 89(cid:19) (cid:19)(cid:7): 8"’)(cid:13)(cid:22)(cid:14)(cid:23)%(cid:14)7(cid:13)(cid:11)#! 8 @(cid:4) 7(cid:13)(cid:11)#(cid:14)(cid:31)(cid:20)&(cid:21)(cid:24) (cid:13) (cid:4)(cid:30)/(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)<(cid:13)(cid:20)(cid:12)(cid:24)& (cid:7) = = (cid:15)(cid:30)(cid:17)(cid:4) (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:7)(cid:17) (cid:4)(cid:30)(cid:6)/ (cid:15)(cid:30)(cid:4)(cid:4) (cid:15)(cid:30)(cid:4)/ (cid:3)&(cid:11)(cid:26)#(cid:23)%%(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:30)(cid:4)/ = (cid:4)(cid:30)(cid:15)/ 3(cid:23)(cid:23)&(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) 7 (cid:4)(cid:30)(cid:5)/ (cid:4)(cid:30);(cid:4) (cid:4)(cid:30)(cid:18)/ 3(cid:23)(cid:23)&(cid:10)(cid:22)(cid:20)(cid:26)& 7(cid:15) (cid:15)(cid:30)(cid:4)(cid:4)(cid:14)(cid:8).3 3(cid:23)(cid:23)&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13) (cid:3) (cid:4)> (cid:16)(cid:30)/> (cid:18)> 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)?(cid:20)#&(cid:24) . (cid:15)(cid:5)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 9 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:15)(cid:5)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)?(cid:20)#&(cid:24) .(cid:15) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)7(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2)(cid:15) (cid:15)(cid:17)(cid:30)(cid:4)(cid:4)(cid:14)1(cid:3)+ 7(cid:13)(cid:11)#(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)4(cid:26)(cid:13)!! (cid:21) (cid:4)(cid:30)(cid:4)(cid:6) = (cid:4)(cid:30)(cid:17)(cid:4) 7(cid:13)(cid:11)#(cid:14)?(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:15)(cid:18) (cid:4)(cid:30)(cid:17)(cid:17) (cid:4)(cid:30)(cid:17)(cid:18) (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)(cid:25)(cid:23)(cid:10) (cid:4) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> (cid:19)(cid:23)(cid:27)#(cid:14)(cid:2)(cid:22)(cid:11)%&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13)(cid:14)1(cid:23)&&(cid:23)’ (cid:5) (cid:15)(cid:15)> (cid:15)(cid:17)> (cid:15)(cid:16)> ’ (cid:13)(cid:6)(cid:12)( (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) +(cid:24)(cid:11)’%(cid:13)(cid:22)!(cid:14)(cid:11)&(cid:14)(cid:21)(cid:23)(cid:22)(cid:26)(cid:13)(cid:22)!(cid:14)(cid:11)(cid:22)(cid:13)(cid:14)(cid:23)(cid:10)&(cid:20)(cid:23)(cid:26)(cid:11)(cid:27),(cid:14)!(cid:20)-(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)(cid:30) (cid:16)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)!(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:26)#(cid:14).(cid:15)(cid:14)#(cid:23)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:20)(cid:26)(cid:21)(cid:27)"#(cid:13)(cid:14)’(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:30)(cid:14)(cid:19)(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:14)!(cid:24)(cid:11)(cid:27)(cid:27)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:13)$(cid:21)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:30)(cid:17)/(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)!(cid:20)#(cid:13)(cid:30) (cid:5)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19).(cid:14)0(cid:15)(cid:5)(cid:30)/(cid:19)(cid:30) 1(cid:3)+2 1(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8).32 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)+(cid:4)(cid:5)(cid:9)(cid:4)(cid:6)(cid:17)1 DS39635C-page 392  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 )(cid:28)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)#(cid:29)(cid:27)#(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)#$(cid:28)(cid:28)(cid:9)(cid:30)(cid:30)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’ (cid:13)(cid:6)( 3(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)255***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’5(cid:10)(cid:11)(cid:21)4(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)  2010 Microchip Technology Inc. DS39635C-page 393

PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 394  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 APPENDIX A: REVISION HISTORY APPENDIX B: DEVICE DIFFERENCES Revision A (June 2004) The differences between the devices listed in this data Original data sheet for PIC18F6310/6410/8310/8410 sheet are shown in TableB-1. devices. Revision B (May 2007) Updated Electrical Characteristics and packaging diagrams. Revision C (October 2010) Changes to electricals in Section 27.0 “Electrical Characteristics” and minor text edits throughout document. TABLE B-1: DEVICE DIFFERENCES Features PIC18F6310 PIC18F6410 PIC18F8310 PIC18F8410 Program Memory (Bytes) 8K 16K 8K 16K Program Memory (Instructions) 4096 8192 4096 8192 External Memory Interface No No Yes Yes I/O Ports Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, F, G F, G F, G, H, J F, G, H, J Packages 64-Pin TQFP 64-Pin TQFP 80-Pin TQFP 80-Pin TQFP  2010 Microchip Technology Inc. DS39635C-page 395

PIC18F6310/6410/8310/8410 APPENDIX C: CONVERSION APPENDIX D: MIGRATION FROM CONSIDERATIONS BASELINE TO ENHANCED DEVICES This appendix discusses the considerations for converting from previous versions of a device to the This section discusses how to migrate from a Baseline ones listed in this data sheet. Typically, these changes device (i.e., PIC16C5X) to an Enhanced MCU device are due to the differences in the process technology (i.e., PIC18FXXX). used. An example of this type of conversion is from a The following are the list of modifications over the PIC16C74A to a PIC16C74B. PIC16C5X microcontroller family: Not Applicable Not Currently Available DS39635C-page 396  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 APPENDIX E: MIGRATION FROM APPENDIX F: MIGRATION FROM MID-RANGE TO HIGH-END TO ENHANCED DEVICES ENHANCED DEVICES A detailed discussion of the differences between the A detailed discussion of the migration pathway and mid-range MCU devices (i.e., PIC16CXXX) and the differences between the high-end MCU devices (i.e., enhanced devices (i.e., PIC18FXXX) is provided in PIC17CXXX) and the enhanced devices (i.e., AN716, “Migrating Designs from PIC16C74A/74B to PIC18FXXX) is provided in AN726, “PIC17CXXX to PIC18C442”. The changes discussed, while device PIC18CXXX Migration”. This Application Note is specific, are generally applicable to all mid-range to available as Literature Number DS00726. enhanced device migrations. This Application Note is available as Literature Number DS00716.  2010 Microchip Technology Inc. DS39635C-page 397

PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 398  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 INDEX Baud Rate Generator (BRG) ...................................244 Associated Registers .......................................244 A Baud Rate Error, Calculating ...........................244 Baud Rates, Asynchronous Modes .................245 A/D ...................................................................................255 High Baud Rate Select (BRGH Bit) .................244 A/D Converter Interrupt, Configuring .......................259 Operation in Power-Managed Modes ..............244 Acquisition Requirements ........................................260 Sampling .........................................................244 ADCON0 Register ....................................................255 Synchronous Master Mode ......................................250 ADCON1 Register ....................................................255 Associated Registers, Receive ........................252 ADCON2 Register ....................................................255 Associated Registers, Transmit .......................251 ADRESH Register ............................................255, 258 Reception ........................................................252 ADRESL Register ....................................................255 Transmission ...................................................250 Analog Port Pins ......................................................148 Synchronous Slave Mode ........................................253 Analog Port Pins, Configuring ..................................262 Associated Registers, Receive ........................254 Associated Registers ...............................................264 Associated Registers, Transmit .......................253 Calculating the Minimum Required Reception ........................................................254 Acquisition Time ..............................................260 Transmission ...................................................253 Configuring the Module ............................................259 Auto-Wake-up on Sync Break Character .........................232 Conversion Clock (TAD) ...........................................261 Conversion Status (GO/DONE Bit) ..........................258 B Conversions .............................................................263 Bank Select Register (BSR) ..............................................75 Converter Characteristics ........................................387 Baud Rate Generator ......................................................203 Discharge .................................................................263 BC ....................................................................................305 Operation in Power-Managed Modes ......................262 BCF .................................................................................306 Selecting, Configuring Automatic BF ....................................................................................207 Acquisition Time ..............................................261 BF Status Flag .................................................................207 Special Event Trigger (CCP) ....................................264 Block Diagrams Use of the CCP2 Trigger ..........................................264 16-Bit Byte Select Mode ............................................99 Absolute Maximum Ratings .............................................351 16-Bit Byte Write Mode ..............................................97 AC (Timing) Characteristics .............................................368 16-Bit Word Write Mode ............................................98 Load Conditions for Device Timing 8-Bit Multiplexed Mode ............................................102 Specifications ...................................................369 A/D ...........................................................................258 Parameter Symbology .............................................368 Analog Input Model ..................................................259 Temperature and Voltage Specifications .................369 AUSART Receive ....................................................248 Timing Conditions ....................................................369 AUSART Transmit ...................................................246 Access Bank ......................................................................77 Baud Rate Generator ..............................................203 ACKSTAT ........................................................................207 Capture Mode Operation .........................................169 ACKSTAT Status Flag .....................................................207 Comparator ADCON0 Register ............................................................255 I/O Operating Modes .......................................266 GO/DONE Bit ...........................................................258 Comparator Analog Input Model ..............................269 ADCON1 Register ............................................................255 Comparator Output ..................................................268 ADCON2 Register ............................................................255 Comparator Voltage Reference ...............................272 ADDFSR ..........................................................................340 Comparator Voltage Reference ADDLW ............................................................................303 Output Buffer Example ....................................273 Addressable Universal Synchronous Asynchronous Compare Mode Operation .......................................171 Receiver Transmitter (AUSART). See AUSART. Device Clock ..............................................................40 ADDULNK ........................................................................340 EUSART Receive ....................................................230 ADDWF ............................................................................303 EUSART Transmit ...................................................227 ADDWFC .........................................................................304 External Clock Input, EC Oscillator ...........................36 ADRESH Register ............................................................255 External Clock Input, HS Oscillator ...........................36 ADRESL Register ....................................................255, 258 External Power-on Reset Circuit Analog-to-Digital Converter. See A/D. (Slow VDD Power-up) ........................................57 ANDLW ............................................................................304 Fail-Safe Clock Monitor ...........................................293 ANDWF ............................................................................305 Generic I/O Port Operation ......................................125 Assembler High/Low-Voltage Detect with External Input ..........276 MPASM Assembler ..................................................348 Interrupt Logic ..........................................................110 AUSART MSSP (I2C Master Mode) ........................................201 Asynchronous Mode ................................................246 MSSP (I2C Mode) ....................................................186 Associated Registers, Receive ........................249 MSSP (SPI Mode) ...................................................177 Associated Registers, Transmit .......................247 On-Chip Reset Circuit ................................................55 Receiver ...........................................................248 PIC18F6310/6410 .....................................................12 Setting up 9-Bit Mode with PIC18F8310/8410 .....................................................13 Address Detect ........................................248 PLL (HS Mode) ..........................................................37 Transmitter .......................................................246 PORTD and PORTE (Parallel Slave Port) ...............148 PWM Operation (Simplified) ....................................173 RC Oscillator Mode ...................................................37  2010 Microchip Technology Inc. DS39635C-page 399

PIC18F6310/6410/8310/8410 RCIO Oscillator Mode ................................................37 Initializing PORTB ....................................................128 Reads From Program Memory ..................................91 Initializing PORTC ...................................................131 Single Comparator ...................................................267 Initializing PORTD ...................................................134 Table Read and Table Write Operations ...................89 Initializing PORTE ....................................................137 Timer0 in 16-Bit Mode ..............................................152 Initializing PORTF ....................................................140 Timer0 in 8-Bit Mode ................................................152 Initializing PORTG ...................................................142 Timer1 ......................................................................156 Initializing PORTH ...................................................144 Timer1 (16-Bit Read/Write Mode) ............................156 Initializing PORTJ ....................................................146 Timer2 ......................................................................162 Loading the SSPBUF (SSPSR) Register .................180 Timer3 ......................................................................164 Reading a Flash Program Memory Word ..................91 Timer3 (16-Bit Read/Write Mode) ............................164 Saving STATUS, WREG and BSR Watchdog Timer .......................................................290 Registers in RAM .............................................124 BN ....................................................................................306 Code Protection ...............................................................281 BNC ..................................................................................307 COMF ..............................................................................314 BNN ..................................................................................307 Comparator ......................................................................265 BNOV ...............................................................................308 Analog Input Connection Considerations ................269 BNZ ..................................................................................308 Associated Registers ...............................................269 BOR. See Brown-out Reset. Configuration ...........................................................266 BOV ..................................................................................311 Effects of a Reset ....................................................268 BRA ..................................................................................309 Interrupts .................................................................268 Break Character (12-Bit) Transmit and Receive ..............234 Operation .................................................................267 BRG. See Baud Rate Generator. Operation During Sleep ...........................................268 Brown-out Reset (BOR) .............................................58, 281 Outputs ....................................................................267 Detecting ....................................................................58 Reference ................................................................267 Disabling in Sleep Mode ............................................58 External Signal ................................................267 Software Enabled .......................................................58 Internal Signal ..................................................267 BSF ..................................................................................309 Response Time ........................................................267 BTFSC .............................................................................310 Comparator Specifications ...............................................366 BTFSS ..............................................................................310 Comparator Voltage Reference .......................................271 BTG ..................................................................................311 Accuracy and Error ..................................................272 BZ .....................................................................................312 Associated Registers ...............................................273 Configuring ..............................................................271 C Connection Considerations ......................................272 C Compilers Effects of a Reset ....................................................272 MPLAB C18 .............................................................348 Operation During Sleep ...........................................272 CALL ................................................................................312 Compare (CCP Module) ..................................................170 Capture (CCP Module) .....................................................169 Associated Registers ...............................................172 Associated Registers ...............................................172 CCP Pin Configuration .............................................170 CCP Pin Configuration .............................................169 CCPR2 Register ......................................................170 CCPR2H:CCPR2L Registers ...................................169 Software Interrupt Mode ..........................................170 Software Interrupt ....................................................170 Special Event Trigger ..............................165, 170, 264 Timer1/Timer3 Mode Selection ................................169 Timer1/Timer3 Mode Selection ................................170 Capture/Compare/PWM (CCP) ........................................167 Computed GOTO ...............................................................72 Capture Mode. See Capture. CONFIG2L (Configuration 2 Low) ...................................283 CCP Mode and Timer Resources ............................168 Configuration Bits ............................................................281 CCPRxH Register ....................................................168 Configuration Register Protection ....................................295 CCPRxL Register .....................................................168 Conversion Considerations ..............................................396 Compare Mode. See Compare. CPFSEQ ..........................................................................314 Interconnect Configurations .....................................168 CPFSGT ..........................................................................315 Module Configuration ...............................................168 CPFSLT ...........................................................................315 CLRF ................................................................................313 Crystal Oscillator/Ceramic Resonator ................................35 CLRWDT ..........................................................................313 Customer Change Notification Service ............................409 Code Examples Customer Notification Service .........................................409 16 x 16 Signed Multiply Routine ..............................108 Customer Support ............................................................409 16 x 16 Unsigned Multiply Routine ..........................108 D 8 x 8 Signed Multiply Routine ..................................107 8 x 8 Unsigned Multiply Routine ..............................107 Data Addressing Modes ....................................................84 Changing Between Capture Prescalers ...................170 Comparing Addressing Modes with the Computed GOTO Using an Offset Value ...................72 Extended Instruction Set Enabled .....................87 Executing Back to Back Sleep Instructions ................46 Direct .........................................................................84 Fast Register Stack ....................................................72 Indexed Literal Offset ................................................86 How to Clear RAM (Bank 1) Using Indirect Indirect .......................................................................84 Addressing .........................................................84 Inherent and Literal ....................................................84 Implementing a Real-Time Clock Using a Timer1 Interrupt Service ..................................159 Initializing PORTA ....................................................125 DS39635C-page 400  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 Data Memory .....................................................................75 Extended Instruction Set Access Bank ..............................................................77 ADDFSR ..................................................................340 and the Extended Instruction Set ...............................86 ADDULNK ...............................................................340 Bank Select Register (BSR) .......................................75 and Using MPLAB IDE Tools ..................................346 General Purpose Registers ........................................77 CALLW ....................................................................341 Map for PIC18F6310/6410/8310/8410 Devices .........76 Considerations for Use ............................................344 Special Function Registers ........................................78 MOVSF ....................................................................341 DAW .................................................................................316 MOVSS ....................................................................342 DC Characteristics ...........................................................363 PUSHL .....................................................................342 Power-Down and Supply Current ............................355 SUBFSR ..................................................................343 Supply Voltage .........................................................354 SUBULNK ................................................................343 DCFSNZ ..........................................................................317 External Memory Interface .................................................95 DECF ...............................................................................316 16-Bit Byte Select Mode ............................................99 DECFSZ ...........................................................................317 16-Bit Byte Write Mode ..............................................97 Development Support ......................................................347 16-Bit Mode ...............................................................97 Device Differences ...........................................................395 16-Bit Mode Timing .................................................100 Device Overview ..................................................................9 16-Bit Word Write Mode ............................................98 Features (table) ..........................................................11 8-Bit Mode ...............................................................102 New Core Features ......................................................9 8-Bit Mode Timing ...................................................103 Device Reset Timers ..........................................................59 and the Program Memory Modes ..............................96 PLL Lock Time-out .....................................................59 Associated Registers ...............................................105 Power-up Timer (PWRT) ...........................................59 PIC18F8310/8410 External Bus, Time-out Sequence ....................................................59 I/O Port Functions ..............................................96 Device Reset Timer Oscillator Start-up Timer (OST) .........59 F Direct Addressing ...............................................................85 Fail-Safe Clock Monitor ...........................................281, 293 E Interrupts in Power-Managed Modes ......................294 Effect on Standard PIC Instructions .................................344 POR or Wake from Sleep ........................................294 Effects of Power-Managed Modes on WDT During Oscillator Failure .................................293 Various Clock Sources ...............................................43 Fast Register Stack ...........................................................72 Electrical Characteristics ..................................................351 Firmware Instructions ......................................................297 Enhanced Universal Synchronous Asynchronous Flash Program Memory Receiver Transmitter (EUSART). See EUSART. Associated Registers .................................................93 Equations Operation During Code-Protect .................................92 16 x 16 Signed Multiplication Algorithm ...................108 Reading .....................................................................90 16 x 16 Unsigned Multiplication Algorithm ...............108 FSCM. See Fail-Safe Clock Monitor. A/D Acquisition Time ................................................260 G A/D Minimum Charging Time ...................................260 Errata ...................................................................................7 GOTO ..............................................................................318 EUSART H Asynchronous Mode ................................................226 12-Bit Break Transmit and Receive .................234 Hardware Multiplier ..........................................................107 Associated Registers, Receive ........................231 Introduction ..............................................................107 Associated Registers, Transmit .......................228 Operation .................................................................107 Auto-Wake-up on Sync Break .........................232 Performance Comparison ........................................107 Receiver ...........................................................229 High/Low-Voltage Detect .................................................275 Setting up 9-Bit Mode with Address Detect .....229 Applications .............................................................278 Transmitter .......................................................226 Associated Registers ...............................................279 Baud Rate Generator (BRG) ....................................221 Characteristics .........................................................367 Associated Registers .......................................221 Current Consumption ..............................................277 Auto-Baud Rate Detect ....................................224 Effects of a Reset ....................................................279 Baud Rate Error, Calculating ...........................221 Operation .................................................................276 Baud Rates, Asynchronous Modes .................222 During Sleep ....................................................279 High Baud Rate Select (BRGH Bit) .................221 Start-up Time ...................................................277 Operation in Power-Managed Modes ..............221 Setup .......................................................................277 Sampling ..........................................................221 Typical Application ...................................................278 Synchronous Master Mode ......................................235 HLVD. See High/Low-Voltage Detect. .............................275 Associated Registers, Receive ........................238 Associated Registers, Transmit .......................236 Reception .........................................................237 Transmission ...................................................235 Synchronous Slave Mode ........................................239 Associated Registers, Receive ........................240 Associated Registers, Transmit .......................239 Reception .........................................................240 Transmission ...................................................239  2010 Microchip Technology Inc. DS39635C-page 401

PIC18F6310/6410/8310/8410 I BNC .........................................................................307 BNN .........................................................................307 I/O Ports ...........................................................................125 I2C Mode (MSSP) BNOV ......................................................................308 BNZ .........................................................................308 Acknowledge Sequence Timing ...............................210 BOV .........................................................................311 Associated Registers ...............................................216 BRA .........................................................................309 Baud Rate Generator ...............................................203 BSF ..........................................................................309 Bus Collision BSF (Indexed Literal Offset mode) ..........................345 During a Repeated Start Condition ..................214 BTFSC .....................................................................310 During a Start Condition ...................................212 BTFSS .....................................................................310 During a Stop Condition ...................................215 BTG .........................................................................311 Clock Arbitration .......................................................204 BZ ............................................................................312 Clock Stretching .......................................................196 CALL ........................................................................312 10-Bit Slave Receive Mode (SEN = 1) .............196 CLRF .......................................................................313 7-Bit Slave Receive Mode (SEN = 1) ...............196 CLRWDT .................................................................313 Effect of a Reset ......................................................211 COMF ......................................................................314 General Call Address Support .................................200 I2C Clock Rate w/BRG .............................................203 CPFSEQ ..................................................................314 CPFSGT ..................................................................315 Master Mode ............................................................201 CPFSLT ...................................................................315 Operation .........................................................202 DAW ........................................................................316 Reception .........................................................207 DCFSNZ ..................................................................317 Repeated Start Condition Timing .....................206 DECF .......................................................................316 Start Condition .................................................205 DECFSZ ..................................................................317 Transmission ....................................................207 Extended Instructions ..............................................339 Transmit Sequence ..........................................202 Syntax ..............................................................339 Multi-Master Communication, Bus Collision General Format ........................................................299 and Arbitration ..................................................211 GOTO ......................................................................318 Multi-Master Mode ...................................................211 INCF ........................................................................318 Operation .................................................................190 INCFSZ ....................................................................319 Read/Write Bit Information (R/W Bit) ...............190, 191 INFSNZ ....................................................................319 Registers ..................................................................186 IORLW .....................................................................320 Serial Clock (RC3/SCK/SCL) ...................................191 IORWF .....................................................................320 Slave Mode ..............................................................190 LFSR .......................................................................321 Addressing .......................................................190 MOVF ......................................................................321 Reception .........................................................191 MOVFF ....................................................................322 Sleep Operation .......................................................211 MOVLB ....................................................................322 Stop Condition Timing ..............................................210 MOVLW ...................................................................323 Transmission ............................................................191 MOVWF ...................................................................323 ID Locations .............................................................281, 296 MULLW ....................................................................324 Idle Modes MULWF ....................................................................324 PRI_IDLE ...................................................................51 NEGF .......................................................................325 INCF .................................................................................318 NOP .........................................................................325 INCFSZ ............................................................................319 Opcode Field Descriptions .......................................298 In-Circuit Debugger ..........................................................296 POP .........................................................................326 In-Circuit Serial Programming (ICSP) ......................281, 296 PUSH .......................................................................326 Indexed Literal Offset Addressing RCALL .....................................................................327 and Standard PIC18 Instructions .............................344 RESET .....................................................................327 Indexed Literal Offset Mode .......................................86, 344 RETFIE ....................................................................328 Effect on Standard PIC18 Instructions .......................86 RETLW ....................................................................328 Mapping the Access Bank .........................................88 RETURN ..................................................................329 Indirect Addressing ............................................................85 RLCF .......................................................................329 INFSNZ ............................................................................319 RLNCF .....................................................................330 Initialization Conditions for all Registers ......................63–66 RRCF .......................................................................330 Instruction Cycle .................................................................73 RRNCF ....................................................................331 Clocking Scheme .......................................................73 SETF .......................................................................331 Instruction Flow/Pipelining .................................................73 SETF (Indexed Literal Offset mode) ........................345 Instruction Set ..................................................................297 SLEEP .....................................................................332 ADDLW ....................................................................303 SUBFWB .................................................................332 ADDWF ....................................................................303 SUBLW ....................................................................333 ADDWF (Indexed Literal Offset mode) ....................345 SUBWF ....................................................................333 ADDWFC .................................................................304 SUBWFB .................................................................334 ANDLW ....................................................................304 SWAPF ....................................................................334 ANDWF ....................................................................305 BC ............................................................................305 BCF ..........................................................................306 BN ............................................................................306 DS39635C-page 402  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 TBLRD .....................................................................335 MSSP TBLWT .....................................................................336 ACK Pulse .......................................................190, 191 TSTFSZ ...................................................................337 Control Registers (general) .....................................177 XORLW ....................................................................337 I2C Mode. See I2C Mode. XORWF ....................................................................338 Module Overview .....................................................177 Summary Table ........................................................300 SPI Master/Slave Connection ..................................181 INTCON Register SPI Mode. See SPI Mode. RBIF Bit ....................................................................128 SSPBUF ..................................................................182 INTCON Registers ...........................................................111 SSPSR ....................................................................182 Inter-Integrated Circuit. See I2C. MULLW ............................................................................324 Internal Oscillator Block .....................................................38 MULWF ............................................................................324 Adjustment .................................................................38 N INTIO Modes ..............................................................38 INTOSC Frequency Drift ............................................38 NEGF ...............................................................................325 INTOSC Output Frequency ........................................38 NOP .................................................................................325 OSCTUNE Register ...................................................38 O Internal RC Oscillator Use with WDT ..........................................................290 Oscillator Internet Address ...............................................................409 Clock Sources ...........................................................40 Interrupt Sources .............................................................281 Selecting the 31 kHz Source .............................41 A/D Conversion Complete .......................................259 Selection Using OSCCON Register ..................41 Context Saving During Interrupts .............................124 External Clock Input ..................................................36 Interrupt-on-Change (RB7:RB4) ..............................128 RC .............................................................................37 INTx Pin ...................................................................124 RCIO Mode ................................................................37 PORTB, Interrupt-on-Change ..................................124 Switching ...................................................................40 TMR0 .......................................................................124 Transitions .................................................................41 TMR0 Overflow ........................................................153 Oscillator Configuration .....................................................35 TMR1 Overflow ........................................................155 EC ..............................................................................35 TMR2 to PR2 Match (PWM) ....................................173 ECIO ..........................................................................35 TMR3 Overflow ................................................163, 165 HS ..............................................................................35 Interrupts ..........................................................................109 HSPLL .......................................................................35 Interrupts, Flag Bits Internal Oscillator Block .............................................38 Interrupt-on-Change (RB7:RB4) Flag INTIO1 .......................................................................35 (RBIF Bit) .........................................................128 INTIO2 .......................................................................35 INTOSC, INTRC. See Internal Oscillator Block. LP ..............................................................................35 IORLW .............................................................................320 RC .............................................................................35 IORWF .............................................................................320 RCIO ..........................................................................35 IPR Registers ...................................................................120 XT ..............................................................................35 Oscillator Selection ..........................................................281 L Oscillator Start-up Timer (OST) .................................43, 281 LFSR ................................................................................321 Oscillator, Timer1 .....................................................155, 165 Oscillator, Timer3 .............................................................163 M P Master Clear (MCLR) .........................................................57 Master Synchronous Serial Port (MSSP). See MSSP. Packaging ........................................................................389 Memory Organization .........................................................67 Details ......................................................................390 Data Memory .............................................................75 Marking ....................................................................389 Program Memory .......................................................67 Parallel Slave Port (PSP) .................................................148 Memory Programming Requirements ..............................365 Associated Registers ...............................................150 Microchip Internet Web Site .............................................409 RE0/RD Pin .............................................................148 Migration from Baseline to Enhanced Devices ................396 RE1/WR Pin ............................................................148 Migration from High-End to Enhanced Devices ...............397 RE2/CS Pin .............................................................148 Migration from Mid-Range to Enhanced Devices ............397 Select (PSPMODE Bit) ............................................148 MOVF ...............................................................................321 PIC18 Instruction Execution, Extended .............................88 MOVFF ............................................................................322 PIE Registers ...................................................................117 MOVLB ............................................................................322 Pin Functions MOVLW ...........................................................................323 AVDD ..........................................................................30 MOVSS ............................................................................342 AVDD ..........................................................................21 MOVWF ...........................................................................323 AVSS ..........................................................................21 MPLAB ASM30 Assembler, Linker, Librarian ..................348 AVSS ..........................................................................30 MPLAB Integrated Development Environment OSC1/CLKI/RA7 ..................................................14, 22 Software ...................................................................347 OSC2/CLKO/RA6 ................................................14, 22 MPLAB PM3 Device Programmer ...................................350 RA0/AN0 ..............................................................15, 23 MPLAB REAL ICE In-Circuit Emulator System ................349 RA1/AN1 ..............................................................15, 23 MPLINK Object Linker/MPLIB Object Librarian ...............348 RA2/AN2/VREF- ...................................................15, 23 RA3/AN3/VREF+ ..................................................15, 23  2010 Microchip Technology Inc. DS39635C-page 403

PIC18F6310/6410/8310/8410 RA4/T0CKI ...........................................................15, 23 RH0/AD16 .................................................................29 RA5/AN4/HLVDIN ................................................15, 23 RH1/AD17 .................................................................29 RB0/INT0 .............................................................16, 24 RH2/AD18 .................................................................29 RB1/INT1 .............................................................16, 24 RH3/AD19 .................................................................29 RB2/INT2 .............................................................16, 24 RH4 ...........................................................................29 RB3/INT3 ...................................................................16 RH5 ...........................................................................29 RB3/INT3/CCP2 .........................................................24 RH6 ...........................................................................29 RB4/KBI0 .............................................................16, 24 RH7 ...........................................................................29 RB5/KBI1 .............................................................16, 24 RJ0/ALE ....................................................................30 RB6/KBI2/PGC ....................................................16, 24 RJ1/OE ......................................................................30 RB7/KBI3/PGD ....................................................16, 24 RJ2/WRL ...................................................................30 RC0/T1OSO/T13CKI ...........................................17, 25 RJ3/WRH ...................................................................30 RC1/T1OSI/CCP2 ................................................17, 25 RJ4/BA0 ....................................................................30 RC2/CCP1 ...........................................................17, 25 RJ5/CE ......................................................................30 RC3/SCK/SCL .....................................................17, 25 RJ6/LB .......................................................................30 RC4/SDI/SDA ......................................................17, 25 RJ7/UB ......................................................................30 RC5/SDO .............................................................17, 25 VDD ............................................................................21 RC6/TX1/CK1 ......................................................17, 25 VDD ............................................................................30 RC7/RX1/DT1 ......................................................17, 25 VSS ............................................................................21 RD0/AD0/PSP0 ..........................................................26 VSS ............................................................................30 RD0/PSP0 ..................................................................18 Pinout I/O Descriptions RD1/AD1/PSP1 ..........................................................26 PIC18F6310/6410 .....................................................14 RD1/PSP1 ..................................................................18 PIC18F8310/8410 .....................................................22 RD2/AD2/PSP2 ..........................................................26 PIR Registers ...................................................................114 RD2/PSP2 ..................................................................18 PLL ....................................................................................37 RD3/AD3/PSP3 ..........................................................26 HSPLL Oscillator Mode .............................................37 RD3/PSP3 ..................................................................18 Use with INTOSC ................................................37, 38 RD4/AD4/PSP4 ..........................................................26 POP .................................................................................326 RD4/PSP4 ..................................................................18 POR. See Power-on Reset. RD5/AD5/PSP5 ..........................................................26 PORTA RD5/PSP5 ..................................................................18 Associated Registers ...............................................127 RD6/AD6/PSP6 ..........................................................26 Functions .................................................................126 RD6/PSP6 ..................................................................18 LATA Register .........................................................125 RD7/AD7/PSP7 ..........................................................26 PORTA Register ......................................................125 RD7/PSP7 ..................................................................18 TRISA Register ........................................................125 RE0/AD8/RD ..............................................................27 PORTB RE0/RD ......................................................................19 Associated Registers ...............................................130 RE1/AD9/WR .............................................................27 Functions .................................................................129 RE1/WR .....................................................................19 LATB Register .........................................................128 RE2/AD10/CS ............................................................27 PORTB Register ......................................................128 RE2/CS ......................................................................19 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........128 RE3 ............................................................................19 TRISB Register ........................................................128 RE3/AD11 ..................................................................27 PORTC RE4 ............................................................................19 Associated Registers ...............................................133 RE4/AD12 ..................................................................27 Functions .................................................................132 RE5 ............................................................................19 LATC Register .........................................................131 RE5/AD13 ..................................................................27 PORTC Register ......................................................131 RE6 ............................................................................19 RC3/SCK/SCL Pin ...................................................191 RE6/AD14 ..................................................................27 TRISC Register ........................................................131 RE7/CCP2 .................................................................19 PORTD ............................................................................148 RE7/CCP2/AD15 .......................................................27 Associated Registers ...............................................136 RF0/AN5 ..............................................................20, 28 Functions .................................................................135 RF1/AN6/C2OUT .................................................20, 28 LATD Register .........................................................134 RF2/AN7/C1OUT .................................................20, 28 PORTD Register ......................................................134 RF3/AN8 ..............................................................20, 28 TRISD Register ........................................................134 RF4/AN9 ..............................................................20, 28 PORTE RF5/AN10/CVREF .................................................20, 28 Analog Port Pins ......................................................148 RF6/AN11 ............................................................20, 28 Associated Registers ...............................................139 RF7/SS ................................................................20, 28 Functions .................................................................138 RG0/CCP3 ...........................................................21, 29 LATE Register .........................................................137 RG1/TX2/CK2 ......................................................21, 29 PORTE Register ......................................................137 RG2/RX2/DT2 ......................................................21, 29 PSP Mode Select (PSPMODE Bit) ..........................148 RG3 ......................................................................21, 29 RE0/RD Pin .............................................................148 RG4 ......................................................................21, 29 RE1/WR Pin .............................................................148 RG5 ......................................................................21, 29 RE2/CS Pin .............................................................148 RG5/MCLR/VPP ...................................................14, 22 TRISE Register ........................................................137 DS39635C-page 404  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 PORTF Instructions ................................................................74 Associated Registers ...............................................141 Two-Word Instructions .......................................74 Functions .................................................................141 Interrupt Vector ..........................................................67 LATF Register ..........................................................140 Look-up Tables ..........................................................72 PORTF Register ......................................................140 Map and Stack (diagram) ..........................................67 TRISF Register ........................................................140 Memory Access for PIC18F8310/8410 Modes ..........69 PORTG Memory Maps for PIC18FX310/X410 Modes ............69 Associated Registers ...............................................143 PIC18F8310/8410 Memory Modes ............................68 Functions .................................................................143 Reset Vector ..............................................................67 LATG Register .........................................................142 Table Reads and Table Writes ..................................89 PORTG Register ......................................................142 Writing and Erasing On-Chip Program TRISG Register ........................................................142 Memory (ICSP Mode) ........................................92 PORTH Writing To Associated Registers ...............................................145 Unexpected Termination ...................................92 Functions .................................................................145 Write Verify ........................................................92 LATH Register .........................................................144 Writing to Memory Space (PIC18F8X10) ..................92 PORTH Register ......................................................144 Program Memory Modes TRISH Register ........................................................144 Extended Microcontroller ...........................................96 PORTJ Microcontroller ...........................................................96 Associated Registers ...............................................147 Microprocessor ..........................................................96 Functions .................................................................147 Microprocessor with Boot Block ................................96 LATJ Register ..........................................................146 Program Verification and Code Protection ......................295 PORTJ Register .......................................................146 Associated Registers ...............................................295 TRISJ Register .........................................................146 Programming, Device Instructions ...................................297 Postscaler, WDT PSP.See Parallel Slave Port. Assignment (PSA Bit) ..............................................153 Pulse-Width Modulation. See PWM (CCP Module). Rate Select (T0PS2:T0PS0 Bits) .............................153 PUSH ...............................................................................326 Switching Between Timer0 and WDT ......................153 PUSH and POP Instructions ..............................................71 Power-Managed Modes .....................................................45 PUSHL .............................................................................342 and Multiple Sleep Commands ..................................46 PWM (CCP Module) Clock Sources ............................................................45 Associated Registers ...............................................175 Clock Transitions, Status Indicators ...........................46 Duty Cycle ...............................................................174 Entering ......................................................................45 Example Frequencies/Resolutions ..........................174 Exiting Idle and Sleep Modes ....................................53 Period ......................................................................173 by Interrupt .........................................................53 Setup for PWM Operation .......................................174 by Reset .............................................................53 TMR2 to PR2 Match ................................................173 by WDT Time-out ...............................................53 Q Without an Oscillator Start-up Delay ..................53 Idle Modes .................................................................50 Q Clock ............................................................................174 Operation .................................................................105 R Run Modes .................................................................46 Selecting ....................................................................45 RAM. See Data Memory. Sleep Mode ................................................................50 RCALL .............................................................................327 Summary (table) ........................................................45 RCON Register Power-on Reset (POR) ..............................................57, 281 Bit Status During Initialization ....................................62 Oscillator Start-up Timer (OST) .................................59 Reader Response ............................................................410 Power-up Timer (PWRT) ...........................................59 Register File .......................................................................77 Time-out Sequence ....................................................59 Register File Summary ................................................79–82 Power-up Delays ................................................................43 Registers Power-up Timer (PWRT) ...........................................43, 281 ADCON0 (A/D Control 0) .........................................255 Prescaler, Capture ...........................................................170 ADCON1 (A/D Control 1) .........................................256 Prescaler, Timer0 .............................................................153 ADCON2 (A/D Control 2) .........................................257 Assignment (PSA Bit) ..............................................153 BAUDCON1 (Baud Rate Control 1) .........................220 Rate Select (T0PS2:T0PS0 Bits) .............................153 CCPxCON (Capture/Compare/PWM Control) .........167 Switching Between Timer0 and WDT ......................153 CMCON (Comparator Control) ................................265 Prescaler, TMR2 ..............................................................174 CONFIG1H (Configuration 1 High Byte) ..................282 Program Counter ...............................................................70 CONFIG2H (Configuration 2 High) ..........................284 PCL, PCH and PCU Registers ...................................70 CONFIG3H (Configuration 3 High) ..........................286 PCLATH and PCLATU Registers ..............................70 CONFIG3L (Configuration 3 Low) ...........................285 Program Memory ...............................................................89 CONFIG4L (Configuration 4 Low) ...........................287 Code Protection, from Table Reads .........................295 CONFIG5L (Configuration 5 Low) ...........................287 Control Registers .......................................................90 CONFIG7L (Configuration 7 Low) ...........................288 TABLAT (Table Latch) Register .........................90 CVRCON (Comparator Voltage TBLPTR (Table Pointer) Register ......................90 Reference Control) ..........................................271 Erasing External Memory (PIC18F8X10) ...................92 DEVID1 (Device ID 1) ..............................................289 DEVID2 (Device ID 2) ..............................................289  2010 Microchip Technology Inc. DS39635C-page 405

PIC18F6310/6410/8310/8410 HLVDCON (HLVD Control) ......................................275 S INTCON (Interrupt Control) ......................................111 SCK .................................................................................177 INTCON2 (Interrupt Control 2) .................................112 SDI ...................................................................................177 INTCON3 (Interrupt Control 3) .................................113 SDO .................................................................................177 IPR1 (Peripheral Interrupt Priority 1) ........................120 Serial Clock, SCK ............................................................177 IPR2 (Peripheral Interrupt Priority 2) ........................121 Serial Data In (SDI) ..........................................................177 IPR3 (Peripheral Interrupt Priority 3) ........................122 Serial Data Out (SDO) .....................................................177 MEMCON (Memory Control) ......................................95 Serial Peripheral Interface. See SPI Mode. OSCCON (Oscillator Control) ....................................42 SETF ................................................................................331 OSCTUNE (Oscillator Tuning) ...................................39 Slave Select (SS) .............................................................177 PIE1 (Peripheral Interrupt Enable 1) ........................117 SLEEP .............................................................................332 PIE2 (Peripheral Interrupt Enable 2) ........................118 Sleep Mode PIE3 (Peripheral Interrupt Enable 3) ........................119 OSC1 and OSC2 Pin States ......................................43 PIR1 (Peripheral Interrupt Request (Flag) 1) ...........114 Software Simulator (MPLAB SIM) ...................................349 PIR2 (Peripheral Interrupt Request (Flag) 2) ...........115 Special Event Trigger. See Compare (CCP Module). PIR3 (Peripheral Interrupt Request (Flag) 3) ...........116 Special Features of the CPU ...........................................281 PSPCON (Parallel Slave Port Control) ....................149 Special Function Registers ................................................78 RCON (Reset Control) .......................................56, 123 Map ............................................................................78 RCSTA2 (AUSART2 Receive Status SPI Mode (MSSP) and Control) .....................................................243 Associated Registers ...............................................185 SSPCON1 (MSSP Control 1, SPI Mode) .................179 Bus Mode Compatibility ...........................................185 SSPCON2, (I2C Mode) ............................................189 Effects of a Reset ....................................................185 SSPSTAT (MSSP Status, I2C Mode) ...............187, 188 Enabling SPI I/O ......................................................181 SSPSTAT (MSSP Status, SPI Mode) ..............178, 219 Master Mode ............................................................182 T0CON (Timer0 Control) ..........................................151 Master/Slave Connection .........................................181 T1CON (Timer1 Control) ..........................................155 Operation .................................................................180 T2CON (Timer2 Control) ..........................................161 Serial Clock ..............................................................177 T3CON (Timer3 Control) ..........................................163 Serial Data In ...........................................................177 TXSTA1 (EUSART1 Transmit Status Serial Data Out ........................................................177 and Control) .....................................................218 Slave Mode ..............................................................183 TXSTA2 (AUSART2 Transmit Status Slave Select .............................................................177 and Control) .....................................................242 Slave Select Synchronization ..................................183 WDTCON (Watchdog Timer Control) .......................291 Sleep Operation .......................................................185 RESET .............................................................................327 SPI Clock .................................................................182 Reset ..................................................................................55 Typical Connection ..................................................181 MCLR Reset, Normal Operation ................................55 SS ....................................................................................177 MCLR Reset, Power Managed Modes ......................55 SSPOV ............................................................................207 Power-on Reset (POR) ..............................................55 SSPOV Status Flag .........................................................207 Programmable Brown-out Reset (BOR) ....................55 SSPSTAT Register RESET Instruction .....................................................55 R/W Bit ............................................................190, 191 Stack Full Reset .........................................................55 Stack Full/Underflow Resets ..............................................72 Stack Underflow Reset ..............................................55 Standard Instructions .......................................................297 Watchdog Timer (WDT) Reset ...................................55 SUBFSR ..........................................................................343 Resets ..............................................................................281 SUBFWB .........................................................................332 RETFIE ............................................................................328 SUBLW ............................................................................333 RETLW .............................................................................328 SUBULNK ........................................................................343 RETURN ..........................................................................329 SUBWF ............................................................................333 Return Address Stack ........................................................70 SUBWFB .........................................................................334 Return Stack Pointer (STKPTR) ........................................71 SWAPF ............................................................................334 Revision History ...............................................................395 RLCF ................................................................................329 T RLNCF .............................................................................330 T0CON Register RRCF ...............................................................................330 PSA Bit ....................................................................153 RRNCF .............................................................................331 T0CS Bit ..................................................................152 Run Modes T0PS2:T0PS0 Bits ...................................................153 PRI_RUN ...................................................................46 T0SE Bit ..................................................................152 RC_RUN ....................................................................48 Table Pointer Operations (table) ........................................90 SEC_RUN ..................................................................46 Table Reads/Table Writes .................................................72 TBLRD .............................................................................335 TBLWT .............................................................................336 Time-out in Various Situations (table) ................................59 DS39635C-page 406  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 Timer0 ..............................................................................151 Bus Collision for Transmit and Acknowledge ..........211 16-Bit Mode Timer Reads and Writes ......................152 Capture/Compare/PWM (All CCP Modules) ............377 Associated Registers ...............................................153 CLKO and I/O ..........................................................372 Clock Source Edge Select (T0SE Bit) ......................152 Clock Synchronization .............................................197 Clock Source Select (T0CS Bit) ...............................152 Clock/Instruction Cycle ..............................................73 Operation .................................................................152 Example SPI Master Mode (CKE = 0) .....................378 Overflow Interrupt ....................................................153 Example SPI Master Mode (CKE = 1) .....................379 Prescaler. See Prescaler, Timer0. Example SPI Slave Mode (CKE = 0) .......................380 Timer1 ..............................................................................155 Example SPI Slave Mode (CKE = 1) .......................381 16-Bit Read/Write Mode ...........................................157 External Clock (All Modes Except PLL) ...................370 Associated Registers ...............................................159 External Memory Bus for SLEEP (16-Bit Interrupt ....................................................................158 Microprocessor Mode) .....................................101 Low-Power Option ...................................................157 External Memory Bus for SLEEP (8-Bit Operation .................................................................156 Microprocessor Mode) .....................................104 Oscillator ..........................................................155, 157 External Memory Bus for TBLRD (16-Bit Oscillator Layout Considerations .............................158 Extended Microcontroller Mode) ......................100 Overflow Interrupt ....................................................155 External Memory Bus for TBLRD (16-Bit Resetting, Using a Special Event Trigger Microprocessor Mode) .....................................100 Output (CCP) ...................................................158 External Memory Bus for TBLRD (8-Bit TMR1H Register ......................................................155 Extended Microcontroller Mode) ......................103 TMR1L Register .......................................................155 External Memory Bus for TBLRD (8-Bit Use as a Real-Time Clock .......................................158 Microprocessor Mode) .....................................103 Using as a Clock Source ..........................................157 Fail-Safe Clock Monitor ...........................................294 Timer2 ..............................................................................161 High/Low-Voltage Detect (VDIRMAG = 1) ...............278 Associated Registers ...............................................162 High/Low-Voltage Detect Characteristics ................367 Interrupt ....................................................................162 High/Low-Voltage Detect Operation Operation .................................................................161 (VDIRMAG = 0) ...............................................277 Output ......................................................................162 I2C Bus Data ............................................................382 PR2 Register ............................................................173 I2C Bus Start/Stop Bits ............................................382 TMR2 to PR2 Match Interrupt ..................................173 I2C Master Mode (7 or 10-Bit Transmission) ...........208 Timer3 ..............................................................................163 I2C Master Mode (7-Bit Reception) .........................209 16-Bit Read/Write Mode ...........................................165 I2C Master Mode First Start Bit ................................205 Associated Registers ...............................................165 I2C Slave Mode (10-Bit Reception, SEN = 0) ..........194 Operation .................................................................164 I2C Slave Mode (10-Bit Reception, SEN = 1) ..........199 Oscillator ..........................................................163, 165 I2C Slave Mode (10-Bit Transmission) ....................195 Overflow Interrupt ............................................163, 165 I2C Slave Mode (7-bit Reception, SEN = 0) ............192 Special Event Trigger (CCP) ....................................165 I2C Slave Mode (7-Bit Reception, SEN = 1) ............198 TMR3H Register ......................................................163 I2C Slave Mode (7-Bit Transmission) ......................193 TMR3L Register .......................................................163 I2C Slave Mode General Call Address Timing Diagrams Sequence (7 or 10-Bit Address Mode) ............200 A/D Conversion ........................................................388 I2C Stop Condition Receive or Transmit Mode ........210 Acknowledge Sequence ..........................................210 Master SSP I2C Bus Data .......................................384 Asynchronous Reception .................................230, 249 Master SSP I2C Bus Start/Stop Bits ........................384 Asynchronous Transmission ............................227, 247 Parallel Slave Port (PSP) Read ...............................150 Asynchronous Transmission Parallel Slave Port (PSP) Write ...............................149 (Back to Back) .........................................227, 247 Program Memory Read ...........................................373 Automatic Baud Rate Calculation ............................225 Program Memory Write ...........................................374 Auto-Wake-up Bit (WUE) During PWM Output ............................................................173 Normal Operation ............................................233 Repeated Start Condition ........................................206 Auto-Wake-up Bit (WUE) During Sleep ...................233 Reset, Watchdog Timer (WDT), Oscillator Start-up Baud Rate Generator with Clock Arbitration ............204 Timer (OST) and Power-up Timer (PWRT) .....375 BRG Overflow Sequence .........................................225 Send Break Character Sequence ............................234 BRG Reset Due to SDA Arbitration During Slave Synchronization .............................................183 Start Condition .................................................213 Slow Rise Time (MCLR Tied to VDD, Brown-out Reset (BOR) ...........................................375 VDD Rise > TPWRT) ............................................61 Bus Collision During a Repeated Start SPI Mode (Master Mode) ........................................182 Condition (Case 1) ...........................................214 SPI Mode (Slave Mode, CKE = 0) ...........................184 Bus Collision During a Repeated Start SPI Mode (Slave Mode, CKE = 1) ...........................184 Condition (Case 2) ...........................................214 Synchronous Reception (Master Mode, Bus Collision During a Start SREN) .....................................................237, 252 Condition (SCL = 0) .........................................213 Synchronous Transmission .............................235, 250 Bus Collision During a Start Synchronous Transmission Condition (SDA Only) ......................................212 (Through TXEN) ......................................236, 251 Bus Collision During a Stop Condition (Case 1) ......215 Time-out Sequence on POR w/PLL Enabled Bus Collision During a Stop Condition (Case 2) ......215 (MCLR Tied to VDD) ..........................................61  2010 Microchip Technology Inc. DS39635C-page 407

PIC18F6310/6410/8310/8410 Time-out Sequence on Power-up Master SSP I2C Bus Data Requirements ................385 (MCLR Not Tied to VDD, Case 1) .......................60 Master SSP I2C Bus Start/Stop Bits Time-out Sequence on Power-up Requirements ..................................................384 (MCLR Not Tied to VDD, Case 2) .......................60 PLL Clock ................................................................371 Time-out Sequence on Power-up Program Memory Read Requirements ....................373 (MCLR Tied to VDD, VDD Rise TPWRT) ..............60 Program Memory Write Requirements ....................374 Timer0 and Timer1 External Clock ..........................376 Reset, Watchdog Timer, Oscillator Start-up Transition for Entry to PRI_IDLE Mode ......................51 Timer, Power-up Timer and Brown-out Transition for Entry to SEC_RUN Mode ....................47 Reset Requirements ........................................375 Transition for Entry to Sleep Mode ............................50 Timer0 and Timer1 External Clock Transition for Two-Speed Start-up Requirements ..................................................376 (INTOSC to HSPLL) .........................................292 USART Synchronous Receive Requirements .........386 Transition for Wake From Idle to Run Mode ..............51 USART Synchronous Transmission Transition for Wake From Sleep (HSPLL) .................50 Requirements ..................................................386 Transition From RC_RUN Mode to Top-of-Stack Access ..........................................................70 PRI_RUN Mode .................................................49 TRISE Register Transition From SEC_RUN Mode to PSPMODE Bit ..........................................................148 PRI_RUN Mode (HSPLL) ..................................47 TSTFSZ ...........................................................................337 Transition to RC_RUN Mode .....................................49 Two-Speed Start-up .................................................281, 292 USART Synchronous Receive (Master/Slave) ........386 Two-Word Instructions USART Synchronous Transmission Example Cases ..........................................................74 (Master/Slave) ..................................................386 TXSTA1 Register Timing Diagrams and Specifications BRGH Bit .................................................................221 A/D Conversion Requirements ................................388 TXSTA2 Register AC Characteristics BRGH Bit .................................................................244 Internal RC Accuracy .......................................371 V Capture/Compare/PWM Requirements (All CCP Modules) ...........................................377 Voltage Reference Specifications ....................................366 CLKO and I/O Requirements ...................................372 W Example SPI Mode Requirements (Master Mode, CKE = 0) ..................................378 Watchdog Timer (WDT) ...........................................281, 290 Example SPI Mode Requirements Associated Registers ...............................................291 (Master Mode, CKE = 1) ..................................379 Control Register .......................................................290 Example SPI Mode Requirements During Oscillator Failure ..........................................293 (Slave Mode, CKE = 0) ....................................380 Programming Considerations ..................................290 Example SPI Slave Mode WCOL ......................................................205, 206, 207, 210 Requirements (CKE = 1) ..................................381 WCOL Status Flag ...................................205, 206, 207, 210 External Clock Requirements ..................................370 WWW Address ................................................................409 I2C Bus Data Requirements (Slave Mode) ..............383 WWW, On-Line Support ......................................................7 I2C Bus Start/Stop Bits Requirements X (Slave Mode) ....................................................382 XORLW ............................................................................337 XORWF ...........................................................................338 DS39635C-page 408  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2010 Microchip Technology Inc. DS39635C-page 409

PIC18F6310/6410/8310/8410 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC18F6310/6410/8310/8410 Literature Number: DS39635C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39635C-page 410  2010 Microchip Technology Inc.

PIC18F6310/6410/8310/8410 PIC18F6310/6410/8310/8410 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC18LF6410-I/PT 301 = Industrial temp., Range TQFP package, Extended VDD limits, QTP pattern #301. b) PIC18F8410-I/PT = Industrial temp., TQFP package, normal VDD limits. Device PIC18F6310/6410/8310/8410(1), c) PIC18F8410-E/PT = Extended temp., TQFP PIC18F6310/6410/8310/8410T(2); package, normal VDD limits. VDD range 4.2V to 5.5V PIC18LF6310/6410/8310/8410(1), PIC18LF6310/6410/8310/8410T(2); VDD range 2.0V to 5.5V Temperature Range I = -40C to +85C (Industrial) E = -40C to +125C (Extended) Package PT = TQFP (Thin Quad Flatpack) Note1: F = Standard Voltage Range LF = Wide Voltage Range Pattern QTP, SQTP, Code or Special Requirements 2: T = in tape and reel (blank otherwise)  2010 Microchip Technology Inc. DS39635C-page 411

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC18F6310T-I/PT PIC18F6410T-I/PT PIC18LF8310T-I/PT PIC18LF8410T-I/PT PIC18F8310T-I/PT PIC18LF6410- I/PT PIC18LF6310-I/PT PIC18F8410-E/PT PIC18F8310-E/PT PIC18F6310-E/PT PIC18LF8410-I/PT PIC18F8410- I/PT PIC18F8310-I/PT PIC18F6410-I/PT PIC18F6310-I/PT PIC18LF8310-I/PT PIC18F6410-E/PT PIC18F8410T- I/PT PIC18LF6310T-I/PT PIC18LF6410T-I/PT