PIC18F45J10 Family Data Sheet 28/40/44-Pin High-Performance, RISC Microcontrollers © 2009 Microchip Technology Inc. DS39682E

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, rfPIC, SmartShunt and UNI/O are registered MICROCHIP MAKES NO REPRESENTATIONS OR trademarks of Microchip Technology Incorporated in the WARRANTIES OF ANY KIND WHETHER EXPRESS OR U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, Linear Active Thermistor, MXDEV, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXLAB, SEEVAL, SmartSensor and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB suits, or expenses resulting from such use. No licenses are Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, conveyed, implicitly or otherwise, under any Microchip PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, intellectual property rights. PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39682E-page ii © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 28/40/44-Pin High-Performance, RISC Microcontrollers Special Microcontroller Features: Peripheral Highlights: • Operating Voltage Range: 2.0V to 3.6V • High-Current Sink/Source 25mA/25mA • 5.5V Tolerant Input (digital pins only) (PORTB and PORTC) • On-Chip 2.5V Regulator • Three Programmable External Interrupts • 4x Phase Lock Loop (PLL) available for Crystal • Four Input Change Interrupts and Internal Oscillators • One Capture/Compare/PWM (CCP) module • Self-Programmable under Software Control • One Enhanced Capture/Compare/PWM (ECCP) • Low-Power, High-Speed CMOS Flash Technology module: • C Compiler Optimized Architecture: - One, two or four PWM outputs - Optional extended instruction set designed to - Selectable polarity optimize re-entrant code - Programmable dead time • Priority Levels for Interrupts - Auto-shutdown and auto-restart • 8 x 8 Single-Cycle Hardware Multiplier • Two Master Synchronous Serial Port (MSSP) • Extended Watchdog Timer (WDT): modules supporting 3-Wire SPI (all 4 modes) and I2C™ Master and Slave modes - Programmable period from 4ms to 131s • One Enhanced Addressable USART module: • Single-Supply In-Circuit Serial Programming™ (ICSP™) via Two Pins - Supports RS-485, RS-232 and LIN/J2602 • In-Circuit Debug (ICD) with Three Breakpoints via - Auto-wake-up on Start bit Two Pins - Auto-Baud Detect (ABD) • Power-Managed modes with Clock Switching: • 10-Bit, up to 13-Channel Analog-to-Digital - Run: CPU on, peripherals on Converter module (A/D): - Idle: CPU off, peripherals on - Auto-acquisition capability - Sleep: CPU off, peripherals off - Conversion available during Sleep - Self-calibration feature Flexible Oscillator Structure: • Dual Analog Comparators with Input Multiplexing • Two Crystal modes, up to 40MHz • Two External Clock modes, up to 40 MHz • Internal 31kHz Oscillator • Secondary Oscillator using Timer1 @ 32 kHz • Two-Speed Oscillator Start-up • Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock stops Program Memory MSSP rs Device (Fblyatsehs) #I nSsintrgulec-tWionosrd SRM(bAeyMmte oDsra)yta I/O A1/D0- B(ciht) (EPCCWCCPMP/) SPI MI2aCs™ter EUSART omparato Timers8/16-Bit C PIC18F24J10 16K 8192 1024 21 10 2/0 1 Y Y 1 2 1/2 PIC18F25J10 32K 16384 1024 21 10 2/0 1 Y Y 1 2 1/2 PIC18F44J10 16K 8192 1024 32 13 1/1 2 Y Y 1 2 1/2 PIC18F45J10 32K 16384 1024 32 13 1/1 2 Y Y 1 2 1/2 © 2009 Microchip Technology Inc. DS39682E-page 1

PIC18F45J10 FAMILY Pin Diagrams 28-Pin SPDIP, SOIC, SSOP (300 MIL) = Pins are up to 5.5V tolerant MCLR 1 28 RB7/KBI3/PGD RA0/AN0 2 27 RB6/KBI2/PGC RA1/AN1 3 26 RB5/KBI1/T0CKI/C1OUT RA2/AN2/VREF-/CVREF 4 00 25 RB4/KBI0/AN11 RA3/AN3/VREF+ 5 11 24 RB3/AN9/CCP2* JJ VDDCORE/VCAP 6 45 23 RB2/INT2/AN8 RA5/AN4/SS1/C2OUT 7 F2F2 22 RB1/INT1/AN10 VSS 8 1818 21 RB0/INT0/FLT0/AN12 OSC1/CLKI 9 CC 20 VDD OSC2/CLKO 10 PIPI 19 VSS RC0/T1OSO/T1CKI 11 18 RC7/RX/DT RC1/T1OSI/CCP2* 12 17 RC6/TX/CK RC2/CCP1 13 16 RC5/SDO1 RC3/SCK1/SCL1 14 15 RC4/SDI1/SDA1 * Pin feature is dependent on device configuration. . 28-Pin QFN = Pins are up to 5.5V tolerant T U O 1 C DCCKI/11 GG0N PPTA N1N0 BI3/BI2/BI1/BI0/ AARKKKK A1/A0/CLB7/B6/B5/B4/ RRMRRRR 28272625242322 RA2/AN2/VREF-/CVREF 1 21 RB3/AN9/CCP2* RA3/AN3/VREF+ 2 20 RB2/INT2/AN8 VDDCORE/VCAP 3 PIC18F24J10 19 RB1/INT1/AN10 RA5/AN4/SS1/C2OUT 4 PIC18F25J10 18 RB0/INT0/FLT0/AN12 VSS 5 17 VDD OSC1/CLKI 6 16 VSS OSC2/CLKO 7 15 RC7/RX/DT 8 91011121314 C0/T1OSO/T1CKIC1/T1OSI/CCP2*RC2/CCP1RC3/SCK1/SCL1RC4/SDI1/SDA1RC5/SDO1RC6/TX/CK RR * Pin feature is dependent on device configuration. DS39682E-page 2 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY Pin Diagrams (Continued) 40-Pin PDIP (600 MIL) = Pins are up to 5.5V tolerant MCLR 1 40 RB7/KBI3/PGD RA0/AN0 2 39 RB6/KBI2/PGC RA1/AN1 3 38 RB5/KBI1/T0CKI/C1OUT RA2/AN2/VREF-/CVREF 4 37 RB4/KBI0/AN11 RA3/AN3/VREF+ 5 36 RB3/AN9/CCP2* VDDCORE/VCAP 6 35 RB2/INT2/AN8 RA5/AN4/SS1/C2OUT 7 34 RB1/INT1/AN10 RE0/RD/AN5 8 1010 33 RB0/INT0/FLT0/AN12 RE1/WR/AN6 9 4J5J 32 VDD RE2/CS/AN7 10 44 31 VSS FF VDD 11 88 30 RD7/PSP7/P1D VSS 12 C1C1 29 RD6/PSP6/P1C OSC1/CLKI 13 PIPI 28 RD5/PSP5/P1B OSC2/CLKO 14 27 RD4/PSP4 RC0/T1OSO/T1CKI 15 26 RC7/RX/DT RC1/T1OSI/CCP2* 16 25 RC6/TX/CK RC2/CCP1/P1A 17 24 RC5/SDO1 RC3/SCK1/SCL1 18 23 RC4/SDI1/SDA1 RD0/PSP0/SCK2/SCL2 19 22 RD3/PSP3/SS2 RD1/PSP1/SDI2/SDA2 20 21 RD2/PSP2/SDO2 * Pin feature is dependent on device configuration. . 44-Pin QFN(1) X/CKDO1DI1/SDA1SP3/SS2SP2/SDO2SP1/SDI2/SDA2SP0/SCK2/SCL2CK1/SCL1CP1/P1A1OSI/CCP2*1OSO/T1CKI = Pins are up to 5.5V tolerant TSSPPPPSCTT 6/5/4/3/2/1/0/3/2/1/0/ CCCDDDDCCCC RRRRRRRRRRR 43210987654 44444333333 RC7/RX/DT 1 33 OSC2/CLKO RD4/PSP4 2 32 OSC1/CLKI RD5/PSP5/P1B 3 31 VSS RD6/PSP6/P1C 4 30 VSS RD7/PSP7/P1D 5 PIC18F44J10 29 VDD VSS 6 28 VDD VDD 7 PIC18F45J10 27 RE2/CS/AN7 VDD 8 26 RE1/WR/AN6 RB0/INT0/FLT0/AN12 9 25 RE0/RD/AN5 RB1/INT1/AN10 10 24 RA5/AN4/SS1/C2OUT RB2/INT2/AN8 11 23 VDDCORE/VCAP 23456789012 11111111222 RB3/AN9/CCP2*NCRB4/KBI0/AN11BI1/T0CKI/C1OUTRB6/KBI2/PGCRB7/KBI3/PGDMCLRRA0/AN0RA1/AN1AN2/V-/CV-REFREFRA3/AN3/V+REF 5/K A2/ B R R * Pin feature is dependent on device configuration. Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS. © 2009 Microchip Technology Inc. DS39682E-page 3

PIC18F45J10 FAMILY Pin Diagrams (Continued) 44-Pin TQFP = Pins are up to 5.5V tolerant X/CKDO1DI1/SDA1SP3/SS2SP2/SDO2SP1/SDI2/SDA2SP0/SCK2/SCL2CK1/SCL1CP1/P1A1OSI/CCP2* TSSPPPPSCT 6/5/4/3/2/1/0/3/2/1/ CCCDDDDCCCC RRRRRRRRRRN 43210987654 44444333333 RC7/RX/DT 1 33 NC RD4/PSP4 2 32 RC0/T1OSO/T1CKI RD5/PSP5/P1B 3 31 OSC2/CLKO RD6/PSP6/P1C 4 30 OSC1/CLKI RD7/PSP7/P1D 5 PIC18F44J10 29 VSS VVDSDS 67 PIC18F45J10 2278 VRDED2/CS/AN7 RB0/INT0/FLT0/AN12 8 26 RE1/WR/AN6 RB1/INT1/AN10 9 25 RE0/RD/AN5 RB2/INT2/AN8 10 24 RA5/AN4/SS1/C2OUT RB3/AN9/CCP2* 11 23 VDDCORE/VCAP 23456789012 11111111222 NCNCRB4/KBI0/AN11BI1/T0CKI/C1OUTRB6/KBI2/PGCRB7/KBI3/PGDMCLRRA0/AN0RA1/AN1AN2/V-/CV-REFREFRA3/AN3/V+REF 5/K A2/ B R R * Pin feature is dependent on device configuration. DS39682E-page 4 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY Table of Contents 1.0 Device Overview..........................................................................................................................................................................7 2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers...................................................................................................23 3.0 Oscillator Configurations............................................................................................................................................................27 4.0 Power-Managed Modes.............................................................................................................................................................35 5.0 Reset..........................................................................................................................................................................................41 6.0 Memory Organization.................................................................................................................................................................51 7.0 Flash Program Memory..............................................................................................................................................................71 8.0 8 x 8 Hardware Multiplier............................................................................................................................................................81 9.0 Interrupts....................................................................................................................................................................................83 10.0 I/O Ports.....................................................................................................................................................................................97 11.0 Timer0 Module.........................................................................................................................................................................115 12.0 Timer1 Module.........................................................................................................................................................................119 13.0 Timer2 Module.........................................................................................................................................................................125 14.0 Capture/Compare/PWM (CCP) Modules.................................................................................................................................127 15.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................135 16.0 Master Synchronous Serial Port (MSSP) Module....................................................................................................................149 17.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)...............................................................193 18.0 10-Bit Analog-to-Digital Converter (A/D) Module.....................................................................................................................215 19.0 Comparator Module..................................................................................................................................................................225 20.0 Comparator Voltage Reference Module...................................................................................................................................231 21.0 Special Features of the CPU....................................................................................................................................................235 22.0 Instruction Set Summary..........................................................................................................................................................249 23.0 Development Support...............................................................................................................................................................299 24.0 Electrical Characteristics..........................................................................................................................................................303 25.0 Packaging Information..............................................................................................................................................................337 Appendix A: Revision History.............................................................................................................................................................349 Appendix B: Migration Between High-End Device Families...............................................................................................................350 Index..................................................................................................................................................................................................353 The Microchip Web Site.....................................................................................................................................................................363 Customer Change Notification Service..............................................................................................................................................363 Customer Support..............................................................................................................................................................................363 Reader Response..............................................................................................................................................................................364 PIC18F45J10 family Product Identification System...........................................................................................................................365 © 2009 Microchip Technology Inc. DS39682E-page 5

PIC18F45J10 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39682E-page 6 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 1.0 DEVICE OVERVIEW 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES This document contains device specific information for the following devices: All of the devices in the PIC18F45J10 family offer three different oscillator options. These include: • PIC18F24J10 • PIC18LF24J10 • Two Crystal modes, using crystals or ceramic • PIC18F25J10 • PIC18LF25J10 resonators • PIC18F44J10 • PIC18LF44J10 • Two External Clock modes • PIC18F45J10 • PIC18LF45J10 • INTRC source (approximately 31kHz) This family offers the advantages of all PIC18 Besides its availability as a clock source, the internal microcontrollers – namely, high computational perfor- oscillator block provides a stable reference source that mance at an economical price. The PIC18F45J10 family gives the family additional features for robust introduces design enhancements that make these micro- operation: controllers a logical choice for many high-performance, • Fail-Safe Clock Monitor: This option constantly power sensitive applications. monitors the main clock source against a refer- ence signal provided by the internal oscillator. If a 1.1 Core Features clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued 1.1.1 LOW POWER low-speed operation or a safe application All of the devices in the PIC18F45J10 family shutdown. incorporate a range of features that can significantly • Two-Speed Start-up: This option allows the reduce power consumption during operation. Key internal oscillator to serve as the clock source items include: from Power-on Reset, or wake-up from Sleep • Alternate Run Modes: By clocking the controller mode, until the primary clock source is available. from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. • Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. • On-the-Fly Mode Switching: The power- managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application’s software design. • Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized. See Section24.0 “Electrical Characteristics” for values. © 2009 Microchip Technology Inc. DS39682E-page 7

PIC18F45J10 FAMILY 1.2 Other Special Features 1.3 Details on Individual Family Members • Communications: The PIC18F45J10 family incorporates a range of serial communication Devices in the PIC18F45J10 family are available in peripherals, including 1 independent Enhanced 28-pin and 40/44-pin packages. Block diagrams for the USART and 2 Master SSP modules capable of two groups are shown in Figure1-1 and Figure1-2. both SPI and I2C (Master and Slave) modes of The devices are differentiated from each other in five operation. Also, one of the general purpose I/O ways: ports can be reconfigured as an 8-bit Parallel Slave Port for direct processor-to-processor 1. Flash program memory (16Kbytes for communications. PIC18F24J10/44J10 devices and 32Kbytes for • Self-Programmability: These devices can write PIC18F25J10/45J10). to their own program memory spaces under 2. A/D channels (10 for 28-pin devices, 13 for internal software control. By using a bootloader 40/44-pin devices). routine, it becomes possible to create an 3. I/O ports (3 bidirectional ports on 28-pin devices, application that can update itself in the field. 5 bidirectional ports on 40/44-pin devices). • Extended Instruction Set: The PIC18F45J10 4. CCP and Enhanced CCP implementation family introduces an optional extension to the (28-pin devices have 2 standard CCP mod- PIC18 instruction set, which adds 8 new instruc- ules, 40/44-pin devices have one standard CCP tions and an Indexed Addressing mode. This module and one ECCP module). extension, enabled as a device configuration 5. Parallel Slave Port (present only on 40/44-pin option, has been specifically designed to optimize devices). re-entrant application code originally developed in 6. One MSSP module for PIC18F24J10/25J10 high-level languages, such as C. devices and 2 MSSP modules for • Enhanced CCP module: In PWM mode, this PIC18F44J10/45J10 devices module provides 1, 2 or 4 modulated outputs for 7. Parts designated with an “F” part number (i.e., controlling half-bridge and full-bridge drivers. PIC18F25J10) have a minimum VDD of 2.7 volts, Other features include Auto-Shutdown, for whereas parts designated with an “LF” part disabling PWM outputs on interrupt or other select number (i.e., PIC18LF25J10) can operate conditions and Auto-Restart, to reactivate outputs between 2.0-3.6 volts on VDD; however, once the condition has cleared. VDDCORE should never exceed VDD. • Enhanced Addressable USART: This serial All of the other features for devices in this family are communication module is capable of standard identical. These are summarized in Table1-1. RS-232 operation and provides support for the LIN/J2602 protocol. Other enhancements include The pinouts for all devices are listed in Table1-2 and automatic baud rate detection and a 16-bit Baud Table1-3. Rate Generator for improved resolution. The PIC18F45J10 family of devices provides an on-chip • 10-bit A/D Converter: This module incorporates voltage regulator to supply the correct voltage levels to programmable acquisition time, allowing for a the core. Parts designated with an “F” part number (such channel to be selected and a conversion to be as PIC18F25J10) have the voltage regulator enabled. initiated without waiting for a sampling period and These parts can run from 2.7-3.6 volts on VDD but should thus, reduce code overhead. have the VDDCORE pin connected to VSS through a low- • Extended Watchdog Timer (WDT): This ESR capacitor. Parts designated with an “LF” part enhanced version incorporates a 16-bit prescaler, number (such as PIC18LF24J10) do not enable the allowing an extended time-out range that is stable voltage regulator. An external supply of 2.0-2.7 Volts has across operating voltage and temperature. See to be supplied to the VDDCORE pin while 2.0-3.6 Volts Section24.0 “Electrical Characteristics” for can be supplied to VDD (VDDCORE should never exceed time-out periods. VDD). See Section21.3 “On-Chip Voltage Regulator” for more details about the internal voltage regulator. DS39682E-page 8 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY TABLE 1-1: DEVICE FEATURES Features PIC18F24J10 PIC18F25J10 PIC18F44J10 PIC18F45J10 Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz Program Memory (Bytes) 16384 32768 16384 32768 Program Memory 8192 16384 8192 16384 (Instructions) Data Memory (Bytes) 1024 1024 1024 1024 Interrupt Sources 19 19 20 20 I/O Ports Ports A, B, C Ports A, B, C Ports A, B, C, D, E Ports A, B, C, D, E Timers 3 3 3 3 Capture/Compare/PWM Modules 2 2 1 1 Enhanced 0 0 1 1 Capture/Compare/PWM Modules Serial Communications MSSP, MSSP, MSSP, MSSP, Enhanced USART Enhanced USART Enhanced USART Enhanced USART Parallel Communications (PSP) No No Yes Yes 10-Bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels Resets (and Delays) POR, BOR(1), POR, BOR(1), POR, BOR(1), POR, BOR(1), RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction, Stack Full, Stack Stack Full, Stack Stack Full, Stack Stack Full, Stack Underflow (PWRT, Underflow (PWRT, Underflow (PWRT, Underflow (PWRT, OST), OST), OST), OST), MCLR, WDT MCLR, WDT MCLR, WDT MCLR, WDT Programmable Brown-out Reset Yes Yes Yes Yes Instruction Set 75 Instructions; 75 Instructions; 75 Instructions; 75 Instructions; 83 with Extended 83 with Extended 83 with Extended 83 with Extended Instruction Set enabled Instruction Set enabled Instruction Set enabled Instruction Set enabled Packages 28-pin SPDIP 28-pin SPDIP 40-pin PDIP 40-pin PDIP 28-pin SOIC 28-pin SOIC 44-pin QFN 44-pin QFN 28-pin SSOP 28-pin SSOP 44-pin TQFP 44-pin TQFP 28-pin QFN 28-pin QFN Note 1: BOR is not available in PIC18LF2XJ10/4XJ10 devices. © 2009 Microchip Technology Inc. DS39682E-page 9

PIC18F45J10 FAMILY FIGURE 1-1: PIC18F24J10/25J10 (28-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> inc/dec logic 8 8 Data Latch PORTA Data Memory RA0/AN0 21 PCLAT U PCLATH (1Kbyte) RRAA21//AANN21/VREF-/CVREF 20 Address Latch RA3/AN3/VREF+ PCU PCH PCL Program Counter 12 RA5/AN4/SS1/C2OUT Data Address<12> 31 Level Stack Address Latch 4 12 4 BSR Access Program Memory STKPTR FSR0 Bank (16/32Kbytes) FSR1 Data Latch FSR2 12 PORTB RB0/INT0/FLT0/AN12 inc/dec 8 logic RB1/INT1/AN10 Table Latch RB2/INT2/AN8 RB3/AN9/CCP2(1) RB4/KBI0/AN11 Address ROM Latch RB5/KBI1/T0CKI/C1OUT Instruction Bus <16> Decode RB6/KBI2/PGC RB7/KBI3/PGD IR 8 Instruction State Machine Decode and Control Signals Control PRODH PRODL PORTC 8 x 8 Multiply RC0/T1OSO/T1CKI 3 8 RC1/T1OSI/CCP2(1) RC2/CCP1 BITOP W RC3/SCK1/SCL1 8 8 8 RC4/SDI1/SDA1 VDDCORE Internal RC5/SDO1 OSC1 OsBcloillcaktor PoTwimere-rup 8 8 RRCC76//RTXX//CDKT Oscillator ALU<8> INTRC Start-up Timer OSC2 Oscillator Power-on 8 Reset T1OSI Watchdog T1OSO Timer Single-Supply Brown-out(2) BParencdi sGioanp MCLR Programming Reset Reference In-Circuit Fail-Safe VDD,VSS Debugger Clock Monitor BOR(2) Timer0 Timer1 Timer2 1A0D-BCit Comparator CCP1 CCP2 MSSP EUSART Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set. 2: Brown-out Reset is not available in PIC18LF2XJ10/4XJ10 devices. DS39682E-page 10 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY FIGURE 1-2: PIC18F44J10/45J10 (40/44-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> PORTA RA0/AN0 Data Latch RA1/AN1 inc/dec logic 8 8 RA2/AN2/VREF-/CVREF Data Memory RA3/AN3/VREF+ 21 PCLAT U PCLATH (3.9Kbytes) RA5/AN4/SS1/C2OUT 20 Address Latch PCU PCH PCL Program Counter 12 Data Address<12> PORTB 31 Level Stack RB0/INT0/FLT0/AN12 Address Latch 4 12 4 RB1/INT1/AN10 BSR Access Program Memory STKPTR FSR0 Bank RB2/INT2/AN8 (16/32Kbytes) FSR1 RB3/AN9/CCP2(1) Data Latch FSR2 12 RB4/KBI0/AN11 RB5/KBI1/T0CKI/C1OUT RB6/KBI2/PGC inc/dec 8 logic RB7/KBI3/PGD Table Latch Address PORTC ROM Latch Instruction Bus <16> Decode RC0/T1OSO/T1CKI RC1/T1OSI/CCP2(1) RC2/CCP1/P1A IR RC3/SCK1/SCL1 RC4/SDI1/SDA1 8 RC5/SDO1 Instruction State Machine RC6/TX/CK Decode and Control Signals RC7/RX/DT Control PRODH PRODL PORTD 8 x 8 Multiply 3 8 RD0/PSP0/SCK2/SCL2 RD1/PSP1/SDI2/SDA2 BITOP W RD2/PSP2/SDO2 8 8 8 RD3/PSP3/SS2 RD4/PSP4 VDDCORE Internal OSC1 OsBcloillcaktor PoTwimere-rup 8 8 RRDD56//PPSSPP56//PP11BC Oscillator ALU<8> RD7/PSP7/P1D OSC2 INTRC Start-up Timer Oscillator Power-on 8 T1OSI Reset Watchdog PORTE T1OSO Timer RE0/RD/AN5 Single-Supply Brown-out(2) BParencdi sGioanp RE1/WR/AN6 MCLR Programming Reset Reference RE2/CS/AN7 In-Circuit Fail-Safe VDD,VSS Debugger Clock Monitor BOR(2) Timer0 Timer1 Timer2 1A0D-BCit Comparator ECCP1 CCP2 MSSP EUSART Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set. 2: Brown-out Reset is not available in PIC18LF2XJ10/4XJ10 devices. © 2009 Microchip Technology Inc. DS39682E-page 11

PIC18F45J10 FAMILY TABLE 1-2: PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS Pin Number SPDIP, Pin Buffer Pin Name Description SOIC, QFN Type Type SSOP MCLR 1 26 Master Clear (input) or programming voltage (input). MCLR I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. OSC1/CLKI 9 6 Oscillator crystal or external clock input. OSC1 I — Oscillator crystal input or external clock source input. I CMOS External clock source input. Always associated with pin CLKI function OSC1. See related OSC2/CLKO pins. OSC2/CLKO 10 7 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In EC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39682E-page 12 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY TABLE 1-2: PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number SPDIP, Pin Buffer Pin Name Description SOIC, QFN Type Type SSOP PORTA is a bidirectional I/O port. RA0/AN0 2 27 RA0 I/O TTL Digital I/O. AN0 I Analog Analog Input 0. RA1/AN1 3 28 RA1 I/O TTL Digital I/O. AN1 I Analog Analog Input 1. RA2/AN2/VREF-/CVREF 4 1 RA2 I/O TTL Digital I/O. AN2 I Analog Analog Input 2. VREF- I Analog A/D reference voltage (low) input. CVREF O Analog Comparator reference voltage output. RA3/AN3/VREF+ 5 2 RA3 I/O TTL Digital I/O. AN3 I Analog Analog Input 3. VREF+ I Analog A/D reference voltage (high) input. RA5/AN4/SS1/C2OUT 7 4 RA5 I/O TTL Digital I/O. AN4 I Analog Analog Input 4. SS1 I TTL SPI slave select input. C2OUT O — Comparator 2 output. Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. DS39682E-page 13

PIC18F45J10 FAMILY TABLE 1-2: PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number SPDIP, Pin Buffer Pin Name Description SOIC, QFN Type Type SSOP PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0/AN12 21 18 RB0 I/O TTL Digital I/O. INT0 I ST External Interrupt 0. FLT0 I ST PWM Fault input for CCP1. AN12 I Analog Analog input 12. RB1/INT1/AN10 22 19 RB1 I/O TTL Digital I/O. INT1 I ST External Interrupt 1. AN10 I Analog Analog input 10. RB2/INT2/AN8 23 20 RB2 I/O TTL Digital I/O. INT2 I ST External Interrupt 2. AN8 I Analog Analog input 8. RB3/AN9/CCP2 24 21 RB3 I/O TTL Digital I/O. AN9 I Analog Analog Input 9. CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM2 output. RB4/KBI0/AN11 25 22 RB4 I/O TTL Digital I/O. KBI0 I TTL Interrupt-on-change pin. AN11 I Analog Analog Input 11. RB5/KBI1/T0CKI/ 26 23 C1OUT I/O TTL Digital I/O. RB5 I TTL Interrupt-on-change pin. KBI1 I ST Timer0 external clock input. T0CKI O — Comparator 1 output. C1OUT RB6/KBI2/PGC 27 24 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin. RB7/KBI3/PGD 28 25 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39682E-page 14 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY TABLE 1-2: PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number SPDIP, Pin Buffer Pin Name Description SOIC, QFN Type Type SSOP PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI 11 8 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T1CKI I ST Timer1 external clock input. RC1/T1OSI/CCP2 12 9 RC1 I/O ST Digital I/O. T1OSI I Analog Timer1 oscillator input. CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM2 output. RC2/CCP1 13 10 RC2 I/O ST Digital I/O. CCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. RC3/SCK1/SCL1 14 11 RC3 I/O ST Digital I/O. SCK1 I/O ST Synchronous serial clock input/output for SPI mode. SCL1 I/O ST Synchronous serial clock input/output for I2C™ mode. RC4/SDI1/SDA1 15 12 RC4 I/O ST Digital I/O. SDI1 I ST SPI data in. SDA1 I/O ST I2C data I/O. RC5/SDO1 16 13 RC5 I/O ST Digital I/O. SDO1 O — SPI data out. RC6/TX/CK 17 14 RC6 I/O ST Digital I/O. TX O — EUSART asynchronous transmit. CK I/O ST EUSART synchronous clock (see related RX/DT). RC7/RX/DT 18 15 RC7 I/O ST Digital I/O. RX I ST EUSART asynchronous receive. DT I/O ST EUSART synchronous data (see related TX/CK). VSS 8, 19 5, 16 P — Ground reference for logic and I/O pins. VDD 20 17 P — Positive supply for logic and I/O pins. VDDCORE/VCAP 6 3 VDDCORE P — Positive supply for logic and I/O pins. VCAP P — Ground reference for logic and I/O pins. Legend: TTL= TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. DS39682E-page 15

PIC18F45J10 FAMILY TABLE 1-3: PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type Type MCLR 1 18 18 Master Clear (input) or programming voltage (input). MCLR I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. OSC1/CLKI 13 32 30 Oscillator crystal or external clock input. OSC1 I — Oscillator crystal input or external clock source input. CLKI I CMOS External clock source input. Always associated with pin function OSC1. See related OSC2/CLKO pins. OSC2/CLKO 14 33 31 Oscillator crystal or clock output. OSC2 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. CLKO O — In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39682E-page 16 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY TABLE 1-3: PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type Type PORTA is a bidirectional I/O port. RA0/AN0 2 19 19 RA0 I/O TTL Digital I/O. AN0 I Analog Analog Input 0. RA1/AN1 3 20 20 RA1 I/O TTL Digital I/O. AN1 I Analog Analog Input 1. RA2/AN2/VREF-/CVREF 4 21 21 RA2 I/O TTL Digital I/O. AN2 I Analog Analog Input 2. VREF- I Analog A/D reference voltage (low) input. CVREF O Analog Comparator reference voltage output. RA3/AN3/VREF+ 5 22 22 RA3 I/O TTL Digital I/O. AN3 I Analog Analog Input 3. VREF+ I Analog A/D reference voltage (high) input. RA5/AN4/SS1/C2OUT 7 24 24 RA5 I/O TTL Digital I/O. AN4 I Analog Analog Input 4. SS1 I TTL SPI slave select input. C2OUT O — Comparator 2 output. Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. DS39682E-page 17

PIC18F45J10 FAMILY TABLE 1-3: PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0/AN12 33 9 8 RB0 I/O TTL Digital I/O. INT0 I ST External Interrupt 0. FLT0 I ST PWM Fault input for Enhanced CCP1. AN12 I Analog Analog input 12. RB1/INT1/AN10 34 10 9 RB1 I/O TTL Digital I/O. INT1 I ST External Interrupt 1. AN10 I Analog Analog input 10. RB2/INT2/AN8 35 11 10 RB2 I/O TTL Digital I/O. INT2 I ST External Interrupt 2. AN8 I Analog Analog input 8. RB3/AN9/CCP2 36 12 11 RB3 I/O TTL Digital I/O. AN9 I Analog Analog Input 9. CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM2 output. RB4/KBI0/AN11 37 14 14 RB4 I/O TTL Digital I/O. KBI0 I TTL Interrupt-on-change pin. AN11 I Analog Analog Input 11. RB5/KBI1/C1OUT 38 15 15 RB5 I/O TTL Digital I/O. KBI1 I TTL Interrupt-on-change pin. C1OUT O — Comparator 1 output. RB6/KBI2/PGC 39 16 16 RB6 I/O TTL Digital I/O. KBI2 I TTL Interrupt-on-change pin. PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin. RB7/KBI3/PGD 40 17 17 RB7 I/O TTL Digital I/O. KBI3 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39682E-page 18 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY TABLE 1-3: PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type Type PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI 15 34 32 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T1CKI I ST Timer1 external clock input. RC1/T1OSI/CCP2 16 35 35 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. CCP2(2) I/O ST Capture 2 input/Compare 2 output/PWM2 output. RC2/CCP1/P1A 17 36 36 RC2 I/O ST Digital I/O. CCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output. P1A O — Enhanced CCP1 output. RC3/SCK1/SCL1 18 37 37 RC3 I/O ST Digital I/O. SCK1 I/O ST Synchronous serial clock input/output for SPI mode. SCL1 I/O ST Synchronous serial clock input/output for I2C™ mode. RC4/SDI1/SDA1 23 42 42 RC4 I/O ST Digital I/O. SDI1 I ST SPI data in. SDA1 I/O ST I2C data I/O. RC5/SDO1 24 43 43 RC5 I/O ST Digital I/O. SDO1 O — SPI data out. RC6/TX/CK 25 44 44 RC6 I/O ST Digital I/O. TX O — EUSART asynchronous transmit. CK I/O ST EUSART synchronous clock (see related RX/DT). RC7/RX/DT 26 1 1 RC7 I/O ST Digital I/O. RX I ST EUSART asynchronous receive. DT I/O ST EUSART synchronous data (see related TX/CK). Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. DS39682E-page 19

PIC18F45J10 FAMILY TABLE 1-3: PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type Type PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when PSP module is enabled. RD0/PSP0/SCK2/ 19 38 38 SCL2 RD0 I/O ST Digital I/O. PSP0 I/O TTL Parallel Slave Port data. SCK2 I/O ST Synchronous serial clock input/output for SPI mode. SCL2 I/O ST Synchronous serial clock input/output for I2C™ mode. RD1/PSP1/SDI2/SDA2 20 39 39 RD1 I/O ST Digital I/O. PSP1 I/O TTL Parallel Slave Port data. SDI2 I ST SPI data in. SDA2 I/O ST I2C data I/O. RD2/PSP2/SDO2 21 40 40 RD2 I/O ST Digital I/O. PSP2 I/O TTL Parallel Slave Port data. SDO2 O — SPI data out. RD3/PSP3/SS2 22 41 41 RD3 I/O ST Digital I/O. PSP3 I/O TTL Parallel Slave Port data. SS2 I TTL SPI slave select input. RD4/PSP4 27 2 2 RD4 I/O ST Digital I/O. PSP4 I/O TTL Parallel Slave Port data. RD5/PSP5/P1B 28 3 3 RD5 I/O ST Digital I/O. PSP5 I/O TTL Parallel Slave Port data. P1B O — Enhanced CCP1 output. RD6/PSP6/P1C 29 4 4 RD6 I/O ST Digital I/O. PSP6 I/O TTL Parallel Slave Port data. P1C O — Enhanced CCP1 output. RD7/PSP7/P1D 30 5 5 RD7 I/O ST Digital I/O. PSP7 I/O TTL Parallel Slave Port data. P1D O — Enhanced CCP1 output. Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. DS39682E-page 20 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY TABLE 1-3: PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type Type PORTE is a bidirectional I/O port. RE0/RD/AN5 8 25 25 RE0 I/O ST Digital I/O. RD I TTL Read control for Parallel Slave Port (see also WR and CS pins). AN5 I Analog Analog input 5. RE1/WR/AN6 9 26 26 RE1 I/O ST Digital I/O. WR I TTL Write control for Parallel Slave Port (see CS and RD pins). AN6 I Analog Analog input 6. RE2/CS/AN7 10 27 27 RE2 I/O ST Digital I/O. CS I TTL Chip Select control for Parallel Slave Port (see related RD and WR pins). AN7 I Analog Analog input 7. VSS 12, 31 6, 30, 6, 29 P — Ground reference for logic and I/O pins. 31 VDD 11, 32 7, 8, 7, 28 P — Positive supply for logic and I/O pins. 28, 29 VDDCORE/VCAP 6 23 23 VDDCORE P — Positive supply for logic and I/O pins. VCAP P — Ground reference for logic and I/O pins. NC — 13 12, 13, — — No connect. 33, 34 Legend: TTL = TTL compatible input CMOS= CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. DS39682E-page 21

PIC18F45J10 FAMILY NOTES: DS39682E-page 22 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 2.0 GUIDELINES FOR GETTING FIGURE 2-1: RECOMMENDED STARTED WITH PIC18FJ MINIMUM CONNECTIONS MICROCONTROLLERS C2(2) 2.1 Basic Connection Requirements VDD Getting started with the PIC18F45J10 family family of R1 DD SS (1) (1) 8-bit microcontrollers requires attention to a minimal V V R2 set of device pin connections before proceeding with MCLR ENVREG development. VCAP/VDDCORE C1 The following pins must always be connected: C7 PIC18FXXJXX • All VDD and VSS pins (see Section2.2 “Power Supply Pins”) VSS VDD C6(2) C3(2) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used VDD D S VSS D S D S (see Section2.2 “Power Supply Pins”) V V D S A A V V • MCLR pin (see Section2.3 “Master Clear (MCLR) Pin”) C5(2) C4(2) • ENVREG (if implemented) and VCAP/VDDCORE pins (see Section2.4 “Voltage Regulator Pins (VCAP/VDDCORE)”) Key (all values are recommendations): These pins must also be connected if they are being C1 through C6: 0.1 μF, 20V ceramic used in the end application: C7: 10 μF, 6.3V or greater, tantalum or ceramic • PGC/PGD pins used for In-Circuit Serial R1: 10 kΩ Programming™ (ICSP™) and debugging purposes R2: 100Ω to 470Ω (see Section2.5 “ICSP Pins”) Note 1: See Section2.4 “Voltage Regulator Pins • OSCI and OSCO pins when an external oscillator (VCAP/VDDCORE)” for explanation of source is used ENVREG pin connections. (see Section2.6 “External Oscillator Pins”) 2: The example shown is for a PIC18FJ device Additionally, the following pins may be required: with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; • VREF+/VREF- pins used when external voltage adjust the number of decoupling capacitors reference for analog modules is implemented appropriately. Note: The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure2-1. © 2009 Microchip Technology Inc. DS39682E-page 23

PIC18F45J10 FAMILY 2.2 Power Supply Pins 2.3 Master Clear (MCLR) Pin 2.2.1 DECOUPLING CAPACITORS The MCLR pin provides two specific device functions: device Reset, and device programming The use of decoupling capacitors on every pair of and debugging. If programming and debugging are power supply pins, such as VDD, VSS, AVDD and not required in the end application, a direct AVSS, is required. connection to VDD may be all that is required. The Consider the following criteria when using decoupling addition of other components, to help increase the capacitors: application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical • Value and type of capacitor: A 0.1 μF (100 nF), configuration is shown in Figure2-1. Other circuit 10-20V capacitor is recommended. The capacitor designs may be implemented depending on the should be a low-ESR device with a resonance application’s requirements. frequency in the range of 200MHz and higher. Ceramic capacitors are recommended. During programming and debugging, the resistance • Placement on the printed circuit board: The and capacitance that can be added to the pin must decoupling capacitors should be placed as close be considered. Device programmers and debuggers to the pins as possible. It is recommended to drive the MCLR pin. Consequently, specific voltage place the capacitors on the same side of the levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values board as the device. If space is constricted, the of R1 and C1 will need to be adjusted based on the capacitor can be placed on another layer on the application and PCB requirements. For example, it is PCB using a via; however, ensure that the trace recommended that the capacitor, C1, be isolated length from the pin to the capacitor is no greater from the MCLR pin during programming and than 0.25inch (6mm). debugging operations by using a jumper (Figure2-2). • Handling high-frequency noise: If the board is The jumper is replaced for normal run-time experiencing high-frequency noise (upward of operations. tens of MHz), add a second ceramic type capaci- tor in parallel to the above described decoupling Any components associated with the MCLR pin capacitor. The value of the second capacitor can should be placed within 0.25 inch (6mm) of the pin. be in the range of 0.01μF to 0.001μF. Place this second capacitor next to each primary decoupling FIGURE 2-2: EXAMPLE OF MCLR PIN capacitor. In high-speed circuit designs, consider CONNECTIONS implementing a decade pair of capacitances as close to the power and ground pins as possible VDD (e.g., 0.1μF in parallel with 0.001μF). • Maximizing performance: On the board layout R1 from the power supply circuit, run the power and R2 return traces to the decoupling capacitors first, MCLR and then to the device pins. This ensures that the JP PIC18FXXJXX decoupling capacitors are first in the power chain. Equally important is to keep the trace length C1 between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. Note 1: R1≤10kΩ is recommended. A suggested 2.2.2 TANK CAPACITORS starting value is 10kΩ. Ensure that the On boards with power traces running longer than six MCLR pin VIH and VIL specifications are met. inches in length, it is suggested to use a tank capacitor 2: R2≤470Ω will limit any current flowing into for integrated circuits including microcontrollers to MCLR from the external capacitor, C, in the supply a local power source. The value of the tank event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical capacitor should be determined based on the trace Overstress (EOS). Ensure that the MCLR pin resistance that connects the power supply source to VIH and VIL specifications are met. the device and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7μF to 47μF. DS39682E-page 24 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 2.4 Voltage Regulator Pins 2.5 ICSP Pins (VCAP/VDDCORE) The PGC and PGD pins are used for In-Circuit Serial When the regulator is enabled (F devices), a low-ESR Programming (ICSP) and debugging purposes. It is (<5Ω) capacitor is required on the VCAP/VDDCORE pin to recommended to keep the trace length between the stabilize the voltage regulator output voltage. The ICSP connector and the ICSP pins on the device as VCAP/VDDCORE pin must not be connected to VDD and short as possible. If the ICSP connector is expected to must use a capacitor (10 μF typical) connected to experience an ESD event, a series resistor is recom- ground. The type can be ceramic or tantalum. A suitable mended, with the value in the range of a few tens of example is the Murata GRM21BF50J106ZE01 (10 μF, ohms, not to exceed 100Ω. 6.3V) or equivalent. Designers may use Figure2-3 to Pull-up resistors, series diodes and capacitors on the evaluate ESR equivalence of candidate devices. PGC and PGD pins are not recommended as they will It is recommended that the trace length not exceed interfere with the programmer/debugger com- 0.25inch (6mm). Refer to Section24.0 “Electrical munications to the device. If such discrete components Characteristics” for additional information. are an application requirement, they should be removed from the circuit during programming and debugging. When the regulator is disabled (LF devices), the Alternatively, refer to the AC/DC characteristics and VCAP/VDDCORE pin must be tied to a voltage supply at timing requirements information in the respective device the VDDCORE level. Refer to Section24.0 “Electrical Flash programming specification for information on Characteristics” for information on VDD and capacitive loading limits and pin input voltage high (VIH) VDDCORE. and input low (VIL) requirements. FIGURE 2-3: FREQUENCY vs. ESR For device emulation, ensure that the “Communication Channel Select” (i.e., PGC/PGD pins) programmed PERFORMANCE FOR into the device matches the physical connections for SUGGESTED VCAP the ICSP to the MPLAB® ICD 2, MPLAB ICD 3 or 10 REALICE™ emulator. For more information on the ICD 2, ICD 3 and REAL ICE 1 emulator connection requirements, refer to the following documents that are available on the Microchip web site. R ()Ω 0.1 • “MPLAB® ICD 2 In-Circuit Debugger User’s S Guide” (DS51331) E • “Using MPLAB® ICD 2” (poster) (DS51265) 0.01 • “MPLAB® ICD 2 Design Advisory” (DS51566) • “Using MPLAB® ICD 3” (poster) (DS51765) 0.001 • “MPLAB® ICD 3 Design Advisory” (DS51764) 0.01 0.1 1 10 100 1000 10,000 Frequency (MHz) • “MPLAB® REAL ICE™ In-Circuit Emulator User’s Guide” (DS51616) Note: Data for Murata GRM21BF50J106ZE01 shown. Measurements at 25°C, 0V DC bias. • “Using MPLAB® REAL ICE™ In-Circuit Emulator” (poster) (DS51749) © 2009 Microchip Technology Inc. DS39682E-page 25

PIC18F45J10 FAMILY 2.6 External Oscillator Pins FIGURE 2-4: SUGGESTED PLACEMENT OF THE OSCILLATOR Many microcontrollers have options for at least two CIRCUIT oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section3.0 “Oscillator Configurations” for details). Main Oscillator The oscillator circuit should be placed on the same 13 side of the board as the device. Place the oscillator Guard Ring 14 circuit close to the respective oscillator pins with no 15 more than 0.5inch (12mm) between the circuit Guard Trace 16 components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side Secondary 17 of the board. Oscillator 18 Use a grounded copper pour around the oscillator 19 circuit to isolate it from surrounding circuits. The 20 grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a 2.7 Unused I/Os two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested Unused I/O pins should be configured as outputs and layout is shown in Figure2-4. driven to a logic low state. Alternatively, connect a 1kΩ For additional information and design guidance on to 10kΩ resistor to VSS on unused pins and drive the oscillator circuits, please refer to these Microchip output to logic low. Application Notes, available at the corporate web site (www.microchip.com): • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC™ and PICmicro® Devices” • AN849, “Basic PICmicro® Oscillator Design” • AN943, “Practical PICmicro® Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” DS39682E-page 26 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 3.0 OSCILLATOR FIGURE 3-1: CRYSTAL/CERAMIC CONFIGURATIONS RESONATOR OPERATION (HS OR HSPLL 3.1 Oscillator Types CONFIGURATION) The PIC18F45J10 family of devices can be operated in C1(1) OSC1 five different oscillator modes: To 1. HS High-Speed Crystal/Resonator Internal XTAL (3) Logic 2. HSPLL High-Speed Crystal/Resonator RF with Software PLL Control OSC2 Sleep 3. EC External Clock with FOSC/4 Output 4. ECPLL External Clock with Software PLL C2(1) RS(2) PIC18F45J10 Control 5. INTRC Internal 31kHz Oscillator Note 1: See Table3-1 and Table3-2 for initial values of C1 and C2. Four of these are selected by the user by programming 2: A series resistor (RS) may be required for AT the FOSC<2:0> Configuration bits. The fifth mode strip cut crystals. (INTRC) may be invoked under software control; it can also be configured as the default mode on device 3: RF varies with the oscillator mode chosen. Resets. TABLE 3-1: CAPACITOR SELECTION FOR 3.2 Crystal Oscillator/Ceramic CERAMIC RESONATORS Resonators (HS Modes) Typical Capacitor Values Used: In HS or HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to Mode Freq. OSC1 OSC2 establish oscillation. Figure3-1 shows the pin HS 8.0 MHz 27 pF 27 pF connections. 16.0 MHz 22 pF 22 pF The oscillator design requires the use of a parallel cut Capacitor values are for design guidance only. crystal. These capacitors were tested with the resonators Note: Use of a series cut crystal may give a fre- listed below for basic start-up and operation. These quency out of the crystal manufacturer’s values are not optimized. specifications. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following Table3-2 for additional information. Resonators Used: 4.0 MHz 8.0 MHz 16.0 MHz © 2009 Microchip Technology Inc. DS39682E-page 27

PIC18F45J10 FAMILY TABLE 3-2: CAPACITOR SELECTION FOR 3.3 External Clock Input (EC Modes) CRYSTAL OSCILLATOR The EC and ECPLL Oscillator modes require an exter- Typical Capacitor Values nal clock source to be connected to the OSC1 pin. Osc Type Crystal Tested: There is no oscillator start-up time required after a Freq. Power-on Reset or after an exit from Sleep mode. C1 C2 In the EC Oscillator mode, the oscillator frequency HS 4 MHz 27 pF 27 pF divided by 4 is available on the OSC2 pin. This signal 8 MHz 22 pF 22 pF may be used for test purposes or to synchronize other 20 MHz 15 pF 15 pF logic. Figure3-2 shows the pin connections for the EC Oscillator mode. Capacitor values are for design guidance only. These capacitors were tested with the crystals listed FIGURE 3-2: EXTERNAL CLOCK below for basic start-up and operation. These values INPUT OPERATION are not optimized. (EC CONFIGURATION) Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected Clock from OSC1/CLKI VDD and temperature range for the application. Ext. System PIC18F45J10 See the notes following this table for additional FOSC/4 OSC2/CLKO information. Crystals Used: 4 MHz An external clock source may also be connected to the 8 MHz OSC1 pin in the HS mode, as shown in Figure3-3. In this configuration, the divide-by-4 output on OSC2 is 20 MHz not available. Note1: Higher capacitance increases the stability FIGURE 3-3: EXTERNAL CLOCK INPUT of oscillator but also increases the OPERATION (HS OSC start-up time. CONFIGURATION) 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for Clock from OSC1 appropriate values of external Ext. System PIC18F45J10 components. (HS Mode) Open OSC2 3: Rs may be required to avoid overdriving crystals with low drive level specification. 4: Always verify oscillator performance over the VDD and temperature range that is expected for the application. DS39682E-page 28 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 3.4 PLL Frequency Multiplier FIGURE 3-4: PLL BLOCK DIAGRAM A Phase Locked Loop (PLL) circuit is provided as an HSPLL or ECPLL (CONFIG2L) option for users who want to use a lower frequency PLL Enable (OSCTUNE) oscillator circuit, or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due OSC2 to high-frequency crystals, or users who require higher Phase clock speeds from an internal oscillator. For these HS or EC FIN Comparator reasons, the HSPLL and ECPLL modes are available. OSC1 Mode FOUT The HSPLL and ECPLL modes provide the ability to selectively run the device at 4 times the external oscil- Loop lating source to produce frequencies up to 40MHz. Filter The PLL is enabled by setting the PLLEN bit in the OSCTUNE register (Register3-1). ÷4 VCO SYSCLK X U M REGISTER 3-1: OSCTUNE: PLL CONTROL REGISTER U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — PLLEN(1) — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 PLLEN: Frequency Multiplier PLL Enable bit(1) 1 = PLL enabled 0 = PLL disabled bit 5-0 Unimplemented: Read as ‘0’ Note 1: Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and reads as ‘0’. © 2009 Microchip Technology Inc. DS39682E-page 29

PIC18F45J10 FAMILY 3.5 Internal Oscillator Block The primary oscillators include the External Crystal and Resonator modes and the External Clock modes. The PIC18F45J10 family of devices includes an inter- The particular mode is defined by the FOSC<2:0> nal oscillator source (INTRC) which provides a nominal Configuration bits. The details of these modes are 31kHz output. The INTRC is enabled on device covered earlier in this chapter. power-up and clocks the device during its configuration The secondary oscillators are those external sources cycle until it enters operating mode. INTRC is also not connected to the OSC1 or OSC2 pins. These enabled if it is selected as the device clock source or if sources may continue to operate even after the any of the following are enabled: controller is placed in a power-managed mode. • Fail-Safe Clock Monitor PIC18F45J10 family devices offer the Timer1 oscillator • Watchdog Timer as a secondary oscillator. This oscillator, in all • Two-Speed Start-up power-managed modes, is often the time base for These features are discussed in greater detail in functions such as a Real-Time Clock (RTC). Section21.0 “Special Features of the CPU”. Most often, a 32.768kHz watch crystal is connected The INTRC can also be optionally configured as the between the RC0/T1OSO/T13CKI and RC1/T1OSI default clock source on device start-up by setting the pins. Loading capacitors are also connected from each FOSC2 Configuration bit. This is discussed in pin to ground. Section3.6.1 “Oscillator Control Register”. The Timer1 oscillator is discussed in greater detail in Section12.3 “Timer1 Oscillator”. 3.6 Clock Sources and In addition to being a primary clock source, the internal Oscillator Switching oscillator is available as a power-managed mode clock source. The INTRC source is also used as the The PIC18F45J10 family includes a feature that allows clock source for several special features, such as the the device clock source to be switched from the main WDT and Fail-Safe Clock Monitor. oscillator to an alternate clock source. PIC18F45J10 family devices offer two alternate clock sources. When The clock sources for the PIC18F45J10 family devices an alternate clock source is enabled, the various areshown in Figure3-5. See Section21.0 “Special power-managed operating modes are available. Features of the CPU” for Configuration register details. Essentially, there are three clock sources for these devices: • Primary oscillators • Secondary oscillators • Internal oscillator FIGURE 3-5: PIC18F45J10 FAMILY CLOCK DIAGRAM PIC18F45J10 Family Primary Oscillator HS, EC OSC2 Sleep HSPLL, ECPLL 4 x PLL OSC1 Secondary Oscillator T1OSC X Peripherals T1OSO U M T1OSCEN Enable T1OSI Oscillator Internal Oscillator INTRC Source CPU IDLEN Clock Control FOSC<2:0> OSCCON <1:0> Clock Source Option for Other Modules WDT, PWRT, FSCM and Two-Speed Start-up DS39682E-page 30 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 3.6.1 OSCILLATOR CONTROL REGISTER 3.6.1.1 System Clock Selection and the FOSC2 Configuration Bit The OSCCON register (Register3-2) controls several aspects of the device clock’s operation, both in The SCS bits are cleared on all forms of Reset. In the full-power operation and in power-managed modes. device’s default configuration, this means the primary oscillator defined by FOSC<1:0> (that is, one of the HC The System Clock Select bits, SCS<1:0>, select the clock source. The available clock sources are the or EC modes) is used as the primary clock source on device Resets. primary clock (defined by the FOSC<2:0> Configura- tion bits), the secondary clock (Timer1 oscillator) and The default clock configuration on Reset can be changed the internal oscillator. The clock source changes after with the FOSC2 Configuration bit. The effect of this bit is one or more of the bits are written to, following a brief to set the clock source selected when SCS<1:0>=00. clock transition interval. When FOSC2=1 (default), the oscillator source defined by FOSC<1:0> is selected whenever The OSTS (OSCCON<3>) and T1RUN (T1CON<6>) bits indicate which clock source is currently providing SCS<1:0>=00. When FOSC2=0, the INTRC oscillator the device clock. The OSTS bit indicates that the is selected whenever SCS<1:0>=00. Because the SCS Oscillator Start-up Timer (OST) has timed out and the bits are cleared on Reset, the FOSC2 setting also changes the default oscillator mode on Reset. primary clock is providing the device clock in primary clock modes. The T1RUN bit indicates when the Regardless of the setting of FOSC2, INTRC will always Timer1 oscillator is providing the device clock in sec- be enabled on device power-up. It will serve as the ondary clock modes. In power-managed modes, only clock source until the device has loaded its configura- one of these bits will be set at any time. If neither of tion values from memory. It is at this point that the these bits is set, the INTRC is providing the clock, or FOSC Configuration bits are read and the oscillator the internal oscillator has just started and is not yet selection of operational mode is made. stable. Note that either the primary clock or the internal The IDLEN bit determines if the device goes into Sleep oscillator will have two bit setting options, at any given mode or one of the Idle modes when the SLEEP time, depending on the setting of FOSC2. instruction is executed. 3.6.2 OSCILLATOR TRANSITIONS The use of the flag and control bits in the OSCCON register is discussed in more detail in Section4.0 PIC18F45J10 family devices contain circuitry to “Power-Managed Modes”. prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs dur- Note 1: The Timer1 oscillator must be enabled to ing the clock switch. The length of this pause is the sum select the secondary clock source. The of two cycles of the old clock source and three to four Timer1 oscillator is enabled by setting the cycles of the new clock source. This formula assumes T1OSCEN bit in the Timer1 Control regis- that the new clock source is stable. ter (T1CON<3>). If the Timer1 oscillator is Clock transitions are discussed in greater detail in not enabled, then any attempt to select a Section4.1.2 “Entering Power-Managed Modes”. secondary clock source when executing a SLEEP instruction will be ignored. 2: It is recommended that the Timer1 oscillator be operating and stable before executing the SLEEP instruction or a very long delay may occur while the Timer1 oscillator starts. © 2009 Microchip Technology Inc. DS39682E-page 31

PIC18F45J10 FAMILY REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 U-0 U-0 U-0 R-q(1) U-0 R/W-0 R/W-0 IDLEN — — — OSTS — SCS1 SCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters an Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 Unimplemented: Read as ‘0’ bit 3 OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready bit 2 Unimplemented: Read as ‘0’ bit 1-0 SCS<1:0>: System Clock Select bits(4) 11 = Internal oscillator 10 = Primary oscillator 01 = Timer1 oscillator When FOSC2 = 1: 00 = Primary oscillator When FOSC2 = 0: 00 = Internal oscillator Note 1: The Reset value is ‘0’ when HS mode and Two-Speed Start-up are both enabled; otherwise, it is ‘1’. 3.7 Effects of Power-Managed Modes If the Sleep mode is selected, all clock sources are on the Various Clock Sources stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest When PRI_IDLE mode is selected, the designated pri- current consumption of the device (only leakage mary oscillator continues to run without interruption. currents). For all other power-managed modes, the oscillator Enabling any on-chip feature that will operate during using the OSC1 pin is disabled. The OSC1 pin (and Sleep will increase the current consumed during Sleep. OSC2 pin if used by the oscillator) will stop oscillating. The INTRC is required to support WDT operation. The In secondary clock modes (SEC_RUN and Timer1 oscillator may be operating to support a SEC_IDLE), the Timer1 oscillator is operating and real-time clock. Other features may be operating that providing the device clock. The Timer1 oscillator may do not require a device clock source (i.e., MSSP slave, also run in all power-managed modes if required to PSP, INTx pins and others). Peripherals that may add clock Timer1 or Timer3. significant current consumption are listed in In RC_RUN and RC_IDLE modes, the internal oscilla- Section24.2 “DC Characteristics: Power-Down and tor provides the device clock source. The 31kHz Supply Current”. INTRC output can be used directly to provide the clock and may be enabled to support various special features, regardless of the power-managed mode (see Section21.2 “Watchdog Timer (WDT)” through Section21.5 “Fail-Safe Clock Monitor” for more information on WDT, Fail-Safe Clock Monitor and Two-Speed Start-up). DS39682E-page 32 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 3.8 Power-up Delays The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the Power-up delays are controlled by two timers, so that crystal oscillator is stable (HS modes). The OST does no external Reset circuitry is required for most applica- this by counting 1024 oscillator cycles before allowing tions. The delays ensure that the device is kept in the oscillator to clock the device. Reset until the device power supply is stable under nor- mal circumstances and the primary clock is operating There is a delay of interval, TCSD (parameter 38, Table24-10), following POR, while the controller and stable. For additional information on power-up becomes ready to execute instructions. delays, see Section5.6 “Power-up Timer (PWRT)”. The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up (parameter 33, Table24-10). It is always enabled. TABLE 3-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE Oscillator Mode OSC1 Pin OSC2 Pin EC, ECPLL Floating, pulled by external clock At logic low (clock/4 output) HS, HSPLL Feedback inverter disabled at quiescent Feedback inverter disabled at quiescent voltage level voltage level Note: See Table5-2 in Section5.0 “Reset” for time-outs due to Sleep and MCLR Reset. © 2009 Microchip Technology Inc. DS39682E-page 33

PIC18F45J10 FAMILY NOTES: DS39682E-page 34 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 4.0 POWER-MANAGED MODES 4.1.1 CLOCK SOURCES The SCS<1:0> bits allow the selection of one of three The PIC18F45J10 family devices provide the ability to clock sources for power-managed modes. They are: manage power consumption by simply managing clock- ing to the CPU and the peripherals. In general, a lower • the primary clock, as defined by the FOSC<1:0> clock frequency and a reduction in the number of circuits Configuration bits being clocked constitutes lower consumed power. For • the secondary clock (Timer1 oscillator) the sake of managing power in an application, there are • the internal oscillator three primary modes of operation: • Run mode 4.1.2 ENTERING POWER-MANAGED MODES • Idle mode • Sleep mode Switching from one power-managed mode to another begins by loading the OSCCON register. The These modes define which portions of the device are SCS<1:0> bits select the clock source and determine clocked and at what speed. The Run and Idle modes which Run or Idle mode is to be used. Changing these may use any of the three available clock sources bits causes an immediate switch to the new clock (primary, secondary or internal oscillator block); the source, assuming that it is running. The switch may Sleep mode does not use a clock source. also be subject to clock transition delays. These are The power-managed modes include several discussed in Section4.1.3 “Clock Transitions and power-saving features offered on previous PIC® Status Indicators” and subsequent sections. microcontrollers. One is the clock switching feature, Entry to the power-managed Idle or Sleep modes is offered in other PIC18 devices, allowing the controller triggered by the execution of a SLEEP instruction. The to use the Timer1 oscillator in place of the primary actual mode that results depends on the status of the oscillator. Also included is the Sleep mode, offered by IDLEN bit. all PIC microcontrollers, where all device clocks are stopped. Depending on the current mode and the mode being switched to, a change to a power-managed mode does 4.1 Selecting Power-Managed Modes not always require setting all of these bits. Many transitions may be done by changing the oscillator Selecting a power-managed mode requires two select bits, or changing the IDLEN bit, prior to issuing a decisions: if the CPU is to be clocked or not and which SLEEP instruction. If the IDLEN bit is already clock source is to be used. The IDLEN bit configured correctly, it may only be necessary to (OSCCON<7>) controls CPU clocking, while the perform a SLEEP instruction to switch to the desired SCS<1:0> bits (OSCCON<1:0>) select the clock mode. source. The individual modes, bit settings, clock sources and affected modules are summarized in Table4-1. TABLE 4-1: POWER-MANAGED MODES OSCCON bits Module Clocking Mode Available Clock and Oscillator Source IDLEN<7>(1) SCS<1:0> CPU Peripherals Sleep 0 N/A Off Off None – All clocks are disabled PRI_RUN N/A 10 Clocked Clocked Primary – HS, EC; this is the normal full-power execution mode SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator RC_RUN N/A 11 Clocked Clocked Internal Oscillator PRI_IDLE 1 10 Off Clocked Primary – HS, EC SEC_IDLE 1 01 Off Clocked Secondary – Timer1 Oscillator RC_IDLE 1 11 Off Clocked Internal Oscillator Note 1: IDLEN reflects its value when the SLEEP instruction is executed. © 2009 Microchip Technology Inc. DS39682E-page 35

PIC18F45J10 FAMILY 4.1.3 CLOCK TRANSITIONS AND STATUS 4.2.2 SEC_RUN MODE INDICATORS The SEC_RUN mode is the compatible mode to the The length of the transition between clock sources is “clock switching” feature offered in other PIC18 the sum of two cycles of the old clock source and three devices. In this mode, the CPU and peripherals are to four cycles of the new clock source. This formula clocked from the Timer1 oscillator. This gives users the assumes that the new clock source is stable. option of lower power consumption while still using a high-accuracy clock source. Two bits indicate the current clock source and its status: OSTS (OSCCON<3>) and T1RUN SEC_RUN mode is entered by setting the SCS<1:0> (T1CON<6>). In general, only one of these bits will be bits to ‘01’. The device clock source is switched to the set while in a given power-managed mode. When the Timer1 oscillator (see Figure4-1), the primary OSTS bit is set, the primary clock is providing the oscillator is shut down, the T1RUN bit (T1CON<6>) is device clock. When the T1RUN bit is set, the Timer1 set and the OSTS bit is cleared. oscillator is providing the clock. If neither of these bits is set, INTRC is clocking the device. Note: The Timer1 oscillator should already be running prior to entering SEC_RUN mode. Note: Executing a SLEEP instruction does not If the T1OSCEN bit is not set when the necessarily place the device into Sleep SCS<1:0> bits are set to ‘01’, entry to mode. It acts as the trigger to place the SEC_RUN mode will not occur. If the controller into either Sleep mode or one of Timer1 oscillator is enabled, but not yet the Idle modes, depending on the setting running, device clocks will be delayed until of the IDLEN bit. the oscillator has started. In such situa- tions, initial oscillator operation is far from 4.1.4 MULTIPLE SLEEP COMMANDS stable and unpredictable operation may The power-managed mode that is invoked with the result. SLEEP instruction is determined by the setting of the On transitions from SEC_RUN mode to PRI_RUN IDLEN bit at the time the instruction is executed. If mode, the peripherals and CPU continue to be clocked another SLEEP instruction is executed, the device will from the Timer1 oscillator while the primary clock is enter the power-managed mode specified by IDLEN at started. When the primary clock becomes ready, a that time. If IDLEN has changed, the device will enter the clock switch back to the primary clock occurs (see new power-managed mode specified by the new setting. Figure4-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the 4.2 Run Modes primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 In the Run modes, clocks to both the core and oscillator continues to run. peripherals are active. The difference between these modes is the clock source. 4.2.1 PRI_RUN MODE The PRI_RUN mode is the normal, full-power execu- tion mode of the microcontroller. This is also the default mode upon a device Reset unless Two-Speed Start-up is enabled (see Section21.4 “Two-Speed Start-up” for details). In this mode, the OSTS bit is set. (see Section3.6.1 “Oscillator Control Register”). FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI 1 2 3 n-1 n Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 DS39682E-page 36 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 4.2.3 RC_RUN MODE On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTRC In RC_RUN mode, the CPU and peripherals are while the primary clock is started. When the primary clocked from the internal oscillator; the primary clock is clock becomes ready, a clock switch to the primary shut down. This mode provides the best power conser- clock occurs (see Figure4-3). When the clock switch is vation of all the Run modes, while still executing code. complete, the OSTS bit is set and the primary clock is It works well for user applications which are not highly providing the device clock. The IDLEN and SCS bits timing-sensitive or do not require high-speed clocks at are not affected by the switch. The INTRC source will all times. continue to run if either the WDT or the Fail-Safe Clock This mode is entered by setting SCS<1:0> to ‘11’. Monitor is enabled. When the clock source is switched to the INTRC (see Figure4-2), the primary oscillator is shut down and the OSTS bit is cleared. FIGURE 4-2: TRANSITION TIMING TO RC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTRC 1 2 3 n-1 n Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 FIGURE 4-3: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTRC OSC1 TOST(1) CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 Counter SCS<1:0> bits Changed OSTS bit Set Note1: TOST = 1024 TOSC. These intervals are not shown to scale. © 2009 Microchip Technology Inc. DS39682E-page 37

PIC18F45J10 FAMILY 4.3 Sleep Mode 4.4 Idle Modes The power-managed Sleep mode is identical to the The Idle modes allow the controller’s CPU to be legacy Sleep mode offered in all other PIC micro- selectively shut down while the peripherals continue to controllers. It is entered by clearing the IDLEN bit (the operate. Selecting a particular Idle mode allows users default state on device Reset) and executing the to further manage power consumption. SLEEP instruction. This shuts down the selected If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is oscillator (Figure4-4). All clock source status bits are executed, the peripherals will be clocked from the clock cleared. source selected using the SCS<1:0> bits; however, the Entering the Sleep mode from any other mode does not CPU will not be clocked. The clock source status bits are require a clock switch. This is because no clocks are not affected. Setting IDLEN and executing a SLEEP needed once the controller has entered Sleep. If the instruction provides a quick method of switching from a WDT is selected, the INTRC source will continue to given Run mode to its corresponding Idle mode. operate. If the Timer1 oscillator is enabled, it will also If the WDT is selected, the INTRC source will continue continue to run. to operate. If the Timer1 oscillator is enabled, it will also When a wake event occurs in Sleep mode (by interrupt, continue to run. Reset or WDT time-out), the device will not be clocked Since the CPU is not executing instructions, the only until the clock source selected by the SCS<1:0> bits exits from any of the Idle modes are by interrupt, WDT becomes ready (see Figure4-5), or it will be clocked time-out or a Reset. When a wake event occurs, CPU from the internal oscillator if either the Two-Speed execution is delayed by an interval of TCSD Start-up or the Fail-Safe Clock Monitor are enabled (parameter38, Table24-10) while it becomes ready to (see Section21.0 “Special Features of the CPU”). In execute code. When the CPU begins executing code, either case, the OSTS bit is set when the primary clock it resumes with the same clock source for the current is providing the device clocks. The IDLEN and SCS bits Idle mode. For example, when waking from RC_IDLE are not affected by the wake-up. mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS<1:0> bits. FIGURE 4-4: TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC PC + 2 FIGURE 4-5: TRANSITION TIMING FOR WAKE FROM SLEEP Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(1) CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 PC + 6 Counter Wake Event OSTS bit Set Note1: TOST = 1024 TOSC. These intervals are not shown to scale. DS39682E-page 38 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 4.4.1 PRI_IDLE MODE 4.4.2 SEC_IDLE MODE This mode is unique among the three low-power Idle In SEC_IDLE mode, the CPU is disabled but the modes, in that it does not disable the primary device peripherals continue to be clocked from the Timer1 clock. For timing-sensitive applications, this allows for oscillator. This mode is entered from SEC_RUN by set- the fastest resumption of device operation with its more ting the IDLEN bit and executing a SLEEP instruction. If accurate primary clock source, since the clock source the device is in another Run mode, set IDLEN first, then does not have to “warm up” or transition from another set SCS<1:0> to ‘01’ and execute SLEEP. When the oscillator. clock source is switched to the Timer1 oscillator, the primary oscillator is shut-down, the OSTS bit is cleared PRI_IDLE mode is entered from PRI_RUN mode by and the T1RUN bit is set. setting the IDLEN bit and executing a SLEEP instruc- tion. If the device is in another Run mode, set IDLEN When a wake event occurs, the peripherals continue to first, then set the SCS<1:0> bits to ‘10’ and execute be clocked from the Timer1 oscillator. After an interval SLEEP. Although the CPU is disabled, the peripherals of TCSD following the wake event, the CPU begins exe- continue to be clocked from the primary clock source cuting code being clocked by the Timer1 oscillator. The specified by the FOSC0 Configuration bit. The OSTS IDLEN and SCS bits are not affected by the wake-up; bit remains set (see Figure4-6). the Timer1 oscillator continues to run (see Figure4-7). When a wake event occurs, the CPU is clocked from the Note: The Timer1 oscillator should already be primary clock source. A delay of interval, TCSD, is running prior to entering SEC_IDLE mode. required between the wake event and when code If the T1OSCEN bit is not set when the execution starts. This is required to allow the CPU to SLEEP instruction is executed, the SLEEP become ready to execute instructions. After the instruction will be ignored and entry to wake-up, the OSTS bit remains set. The IDLEN and SEC_IDLE mode will not occur. If the SCS bits are not affected by the wake-up (see Timer1 oscillator is enabled, but not yet Figure4-7). running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. FIGURE 4-6: TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Program PC PC + 2 Counter FIGURE 4-7: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 TCSD CPU Clock Peripheral Clock Program PC Counter Wake Event © 2009 Microchip Technology Inc. DS39682E-page 39

PIC18F45J10 FAMILY 4.4.3 RC_IDLE MODE 4.5.2 EXIT BY WDT TIME-OUT In RC_IDLE mode, the CPU is disabled but the periph- A WDT time-out will cause different actions depending erals continue to be clocked from the internal oscillator. on which power-managed mode the device is in when This mode allows for controllable power conservation the time-out occurs. during Idle periods. If the device is not executing code (all Idle modes and From RC_RUN, this mode is entered by setting the Sleep mode), the time-out will result in an exit from the IDLEN bit and executing a SLEEP instruction. If the power-managed mode (see Section4.2 “Run device is in another Run mode, first set IDLEN, then Modes” and Section4.3 “Sleep Mode”). If the device clear the SCS bits and execute SLEEP. When the clock is executing code (all Run modes), the time-out will source is switched to the INTRC, the primary oscillator result in a WDT Reset (see Section21.2 “Watchdog is shut down and the OSTS bit is cleared. Timer (WDT)”). When a wake event occurs, the peripherals continue to The WDT timer and postscaler are cleared by one of be clocked from the INTRC. After a delay of TCSD the following events: following the wake event, the CPU begins executing • executing a SLEEP or CLRWDT instruction code being clocked by the INTRC. The IDLEN and • the loss of a currently selected clock source (if the SCS bits are not affected by the wake-up. The INTRC Fail-Safe Clock Monitor is enabled) source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. 4.5.3 EXIT BY RESET 4.5 Exiting Idle and Sleep Modes Exiting an Idle or Sleep mode by Reset automatically forces the device to run from the INTRC. An exit from Sleep mode, or any of the Idle modes, is triggered by an interrupt, a Reset or a WDT time-out. 4.5.4 EXIT WITHOUT AN OSCILLATOR This section discusses the triggers that cause exits START-UP DELAY from power-managed modes. The clocking subsystem Certain exits from power-managed modes do not actions are discussed in each of the power-managed invoke the OST at all. There are two cases: modes sections (see Section4.2 “Run Modes”, Section4.3 “Sleep Mode” and Section4.4 “Idle • PRI_IDLE mode where the primary clock source Modes”). is not stopped; and • the primary clock source is the EC mode. 4.5.1 EXIT BY INTERRUPT In these instances, the primary clock source either Any of the available interrupt sources can cause the does not require an oscillator start-up delay, since it is device to exit from an Idle mode, or the Sleep mode, to already running (PRI_IDLE), or normally does not a Run mode. To enable this functionality, an interrupt require an oscillator start-up delay (EC). However, a source must be enabled by setting its enable bit in one fixed delay of interval, TCSD, following the wake event of the INTCON or PIE registers. The exit sequence is is still required when leaving Sleep and Idle modes to initiated when the corresponding interrupt flag bit is set. allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this On all exits from Idle or Sleep modes by interrupt, code delay. execution branches to the interrupt vector if the GIE/GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section9.0 “Interrupts”). A fixed delay of interval, TCSD, following the wake event is required when leaving Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. DS39682E-page 40 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 5.0 RESET 5.1 RCON Register The PIC18F45J10 family of devices differentiate Device Reset events are tracked through the RCON between various kinds of Reset: register (Register5-1). The lower six bits of the register indicate that a specific Reset event has occurred. In a) Power-on Reset (POR) most cases, these bits can only be set by the event and b) MCLR Reset during normal operation must be cleared by the application after the event. The c) MCLR Reset during power-managed modes state of these flag bits, taken together, can be read to d) Watchdog Timer (WDT) Reset (during indicate the type of Reset that just occurred. This is execution) described in more detail in Section5.7 “Reset State e) Configuration Mismatch (CM) of Registers”. f) Brown-out Reset (BOR) The RCON register also has a control bit for setting g) RESET Instruction interrupt priority (IPEN). Interrupt priority is discussed in Section9.0 “Interrupts”. h) Stack Full Reset i) Stack Underflow Reset This section discusses Resets generated by MCLR, POR and BOR and covers the operation of the various start-up timers. Stack Reset events are covered in Section6.1.4.4 “Stack Full and Underflow Resets”. WDT Resets are covered in Section21.2 “Watchdog Timer (WDT)”. A simplified block diagram of the on-chip Reset circuit is shown in Figure5-1. FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Configuration Word Mismatch Stack Stack Full/Underflow Reset Pointer External Reset MCLR ( )_IDLE Sleep WDT Time-out VDD Rise POR Pulse Detect VDD Brown-out Reset(1) S PWRT 32 μs PWRT 66 ms Chip_Reset R Q INTRC 11-Bit Ripple Counter Note 1: The Brown-out Reset is not available in PIC18LF2XJ10/4XJ10 devices. © 2009 Microchip Technology Inc. DS39682E-page 41

PIC18F45J10 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — CM RI TO PD POR BOR(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 Unimplemented: Read as ‘0’ bit 5 CM: Configuration Mismatch Flag bit 1 = A Configuration Mismatch Reset has not occurred 0 = A Configuration Mismatch Reset has occurred (must be set in software after a Configuration Mismatch Reset occurs) bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-Down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit(1) 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: BOR is not available on PIC18LF2XJ10/4XJ10 devices. Note1: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. 2: If the on-chip voltage regulator is disabled, BOR remains ‘0’ at all times. See Section5.4.1 “Detecting BOR” for more information. 3: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39682E-page 42 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 5.2 Master Clear (MCLR) FIGURE 5-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR The MCLR pin provides a method for triggering a hard SLOW VDD POWER-UP) external Reset of the device. A Reset is generated by holding the pin low. PIC18 extended microcontroller devices have a noise filter in the MCLR Reset path VDD VDD which detects and ignores small pulses. The MCLR pin is not driven low by any internal Resets, D R R1 including the WDT. MCLR 5.3 Power-on Reset (POR) C PIC18F45J10 A Power-on Reset condition is generated on-chip whenever VDD rises above a certain threshold. This Note 1: External Power-on Reset circuit is required allows the device to start in the initialized state when only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor VDD is adequate for operation. quickly when VDD powers down. To take advantage of the POR circuitry, tie the MCLR 2: R < 40kΩ is recommended to make sure that pin through a resistor (1kΩ to 10kΩ) to VDD. This will the voltage drop across R does not violate eliminate external RC components usually needed to the device’s electrical specification. create a Power-on Reset delay. A minimum rise rate for 3: R1 ≥ 1 kΩ will limit any current flowing into VDD is specified (parameter D004). For a slow rise MCLR from external capacitor C, in the event time, see Figure5-2. of MCLR pin breakdown, due to Electrostatic When the device starts normal operation (i.e., exits the Discharge (ESD) or Electrical Overstress (EOS). Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the 5.4.1 DETECTING BOR device must be held in Reset until the operating The BOR bit always resets to ‘0’ on any Brown-out conditions are met. Reset or Power-on Reset event. This makes it difficult Power-on Reset events are captured by the POR bit to determine if a Brown-out Reset event has occurred (RCON<1>). The state of the bit is set to ‘0’ whenever just by reading the state of BOR alone. A more reliable a Power-on Reset occurs; it does not change for any method is to simultaneously check the state of both other Reset event. POR is not reset to ‘1’ by any POR and BOR. This assumes that the POR bit is reset hardware event. To capture multiple events, the user to ‘1’ in software immediately after any Power-on Reset manually resets the bit to ‘1’ in software following any event. If BOR is ‘0’ while POR is ‘1’, it can be reliably Power-on Reset. assumed that a Brown-out Reset event has occurred. In devices designated with an “LF” part number (such 5.4 Brown-out Reset (BOR) as PIC18LF25J10), Brown-out Reset functionality is (PIC18F2XJ10/4XJ10 Devices Only) disabled. In this case, the BOR bit cannot be used to determine a Brown-out Reset event. The BOR bit is still The PIC18F45J10 family of devices incorporates a cleared by a Power-on Reset event. simple BOR function when the internal regulator is enabled (ENVREG pin is tied to VDD). Any drop of VDD below VBOR (parameter D005) for greater than time TBOR (parameter 35) will reset the device. A Reset may or may not occur if VDD falls below VBOR for less than TBOR. The chip will remain in Brown-out Reset until VDD rises above VBOR. Once a BOR has occurred, the Power-up Timer will keep the chip in Reset for TPWRT (parameter33). If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above VBOR, the Power-up Timer will execute the additional time delay. © 2009 Microchip Technology Inc. DS39682E-page 43

PIC18F45J10 FAMILY 5.5 Configuration Mismatch (CM) 5.6 Power-up Timer (PWRT) The Configuration Mismatch (CM) Reset is designed to PIC18F45J10 family devices incorporate an on-chip detect and attempt to recover from random, memory Power-up Timer (PWRT) to help regulate the Power-on corrupting events. These include Electrostatic Discharge Reset process. The PWRT is always enabled. The (ESD) events, which can cause widespread, single-bit main function is to ensure that the device voltage is changes throughout the device and result in catastrophic stable before code is executed. failure. The Power-up Timer (PWRT) of the PIC18F45J10 In PIC18FXXJ Flash devices, the device Configuration family devices is an 11-bit counter which uses the registers (located in the configuration memory space) INTRC source as the clock input. This yields an are continuously monitored during operation by approximate time interval of 2048x32μs=65.6ms. comparing their values to complimentary shadow reg- While the PWRT is counting, the device is held in isters. If a mismatch is detected between the two sets Reset. of registers, a CM Reset automatically occurs. These The power-up time delay depends on the INTRC clock events are captured by the CM bit (RCON<5>). The and will vary from chip to chip due to temperature and state of the bit is set to ‘0’ whenever a CM event occurs; process variation. See DC parameter33 for details. it does not change for any other Reset event. A CM Reset behaves similarly to a Master Clear Reset, 5.6.1 TIME-OUT SEQUENCE RESET instruction, WDT time-out or Stack Event If enabled, the PWRT time-out is invoked after the POR Resets. As with all hard and power Reset events, the pulse has cleared. The total time-out will vary based on device Configuration Words are reloaded from the the status of the PWRT. Figure5-3, Figure5-4, Flash Configuration Words in program memory as the Figure5-5 and Figure5-6 all depict time-out device restarts. sequences on power-up with the Power-up Timer enabled. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the PWRT will expire. Bringing MCLR high will begin execution immediately (Figure5-5). This is useful for testing purposes, or to synchronize more than one PIC18F device operating in parallel. FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET DS39682E-page 44 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 3.3V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET © 2009 Microchip Technology Inc. DS39682E-page 45

PIC18F45J10 FAMILY 5.7 Reset State of Registers different Reset situations, as indicated in Table5-1. These bits are used in software to determine the nature Most registers are unaffected by a Reset. Their status of the Reset. is unknown on POR and unchanged by all other Table5-2 describes the Reset states for all of the Resets. The other registers are forced to a “Reset Special Function Registers. These are categorized by state” depending on the type of Reset that occurred. Power-on and Brown-out Resets, Master Clear and Most registers are not affected by a WDT wake-up, WDT Resets and WDT wake-ups. since this is viewed as the resumption of normal operation. Status bits from the RCON register (CM, RI, TO, PD, POR and BOR) are set or cleared differently in TABLE 5-1: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER RCON Register STKPTR Register Program Condition Counter(1) CM RI TO PD POR BOR(2) STKFUL STKUNF Power-on Reset 0000h 1 1 1 1 0 0 0 0 RESET instruction 0000h u 0 u u u u u u Brown-out Reset 0000h 1 1 1 1 u 0 u u Configuration Mismatch Reset 0000h 0 u u u u u u u MCLR Reset during 0000h u u 1 u u u u u power-managed Run modes MCLR Reset during 0000h u u 1 0 u u u u power-managed Idle modes and Sleep mode MCLR Reset during full-power 0000h u u u u u u u u execution Stack Full Reset (STVREN = 1) 0000h u u u u u u 1 u Stack Underflow Reset 0000h u u u u u u u 1 (STVREN = 1) Stack Underflow Error (not an 0000h u u u u u u u 1 actual Reset, STVREN = 0) WDT time-out during full-power 0000h u u 0 u u u u u or power-managed Run modes WDT time-out during PC + 2 u u 0 0 u u u u power-managed Idle or Sleep modes Interrupt exit from PC + 2 u u u 0 u u u u power-managed modes Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 2: BOR is not available on PIC18LF2XJ10/4XJ10 devices. DS39682E-page 46 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS MCLR Resets, WDT Reset, Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction, Brown-out Reset or Interrupt Stack Resets, CM Resets TOSU PIC18F2XJ10 PIC18F4XJ10 ---0 0000 ---0 0000 ---0 uuuu(1) TOSH PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu(1) TOSL PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu(1) STKPTR PIC18F2XJ10 PIC18F4XJ10 00-0 0000 uu-0 0000 uu-u uuuu(1) PCLATU PIC18F2XJ10 PIC18F4XJ10 ---0 0000 ---0 0000 ---u uuuu PCLATH PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu PCL PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 PC + 2(2) TBLPTRU PIC18F2XJ10 PIC18F4XJ10 --00 0000 --00 0000 --uu uuuu TBLPTRH PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu TBLPTRL PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu TABLAT PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu PRODH PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu PRODL PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu INTCON PIC18F2XJ10 PIC18F4XJ10 0000 000x 0000 000u uuuu uuuu(3) INTCON2 PIC18F2XJ10 PIC18F4XJ10 1111 -1-1 1111 -1-1 uuuu -u-u(3) INTCON3 PIC18F2XJ10 PIC18F4XJ10 11-0 0-00 11-0 0-00 uu-u u-uu(3) INDF0 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A POSTINC0 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A POSTDEC0 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A PREINC0 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A PLUSW0 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A FSR0H PIC18F2XJ10 PIC18F4XJ10 ---- xxxx ---- uuuu ---- uuuu FSR0L PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu WREG PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A POSTINC1 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A POSTDEC1 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A PREINC1 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A PLUSW1 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A FSR1H PIC18F2XJ10 PIC18F4XJ10 ---- xxxx ---- uuuu ---- uuuu FSR1L PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu BSR PIC18F2XJ10 PIC18F4XJ10 ---- 0000 ---- 0000 ---- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. DS39682E-page 47

PIC18F45J10 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, WDT Reset, Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction, Brown-out Reset or Interrupt Stack Resets, CM Resets INDF2 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A POSTINC2 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A POSTDEC2 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A PREINC2 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A PLUSW2 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A FSR2H PIC18F2XJ10 PIC18F4XJ10 ---- xxxx ---- uuuu ---- uuuu FSR2L PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu STATUS PIC18F2XJ10 PIC18F4XJ10 ---x xxxx ---u uuuu ---u uuuu TMR0H PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu TMR0L PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu T0CON PIC18F2XJ10 PIC18F4XJ10 1111 1111 1111 1111 uuuu uuuu OSCCON PIC18F2XJ10 PIC18F4XJ10 0--- q-00 0--- q-00 u--- q-uu WDTCON PIC18F2XJ10 PIC18F4XJ10 ---- ---0 ---- ---0 ---- ---u RCON(4) PIC18F2XJ10 PIC18F4XJ10 0-11 11q0 0-qq qquu u-uu qquu TMR1H PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu T1CON PIC18F2XJ10 PIC18F4XJ10 0000 0000 u0uu uuuu uuuu uuuu TMR2 PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu PR2 PIC18F2XJ10 PIC18F4XJ10 1111 1111 1111 1111 1111 1111 T2CON PIC18F2XJ10 PIC18F4XJ10 -000 0000 -000 0000 -uuu uuuu SSP1BUF PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu SSP1ADD PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu SSP1STAT PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu SSP1CON1 PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu SSP1CON2 PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu ADRESH PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 PIC18F2XJ10 PIC18F4XJ10 0-00 0000 0-00 0000 u-uu uuuu ADCON1 PIC18F2XJ10 PIC18F4XJ10 --00 0qqq --00 0qqq --uu uqqq ADCON2 PIC18F2XJ10 PIC18F4XJ10 0-00 0000 0-00 0000 u-uu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition. DS39682E-page 48 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, WDT Reset, Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction, Brown-out Reset or Interrupt Stack Resets, CM Resets CCPR1H PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu CCPR2H PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON PIC18F2XJ10 PIC18F4XJ10 --00 0000 --00 0000 --uu uuuu BAUDCON PIC18F2XJ10 PIC18F4XJ10 01-0 0-00 01-0 0-00 uu-u u-uu ECCP1DEL PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu ECCP1AS PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu CVRCON PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu CMCON PIC18F2XJ10 PIC18F4XJ10 0000 0111 0000 0111 uuuu uuuu SPBRGH PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu SPBRG PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu RCREG PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu TXREG PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu TXSTA PIC18F2XJ10 PIC18F4XJ10 0000 0010 0000 0010 uuuu uuuu RCSTA PIC18F2XJ10 PIC18F4XJ10 0000 000x 0000 000x uuuu uuuu EECON2 PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu EECON1 PIC18F2XJ10 PIC18F4XJ10 ---0 x00- ---0 x00- ---u uuu- IPR3 PIC18F2XJ10 PIC18F4XJ10 11-- ---- 11-- ---- uu-- ---- PIR3 PIC18F2XJ10 PIC18F4XJ10 00-- ---- 00-- ---- uu-- ----(3) PIE3 PIC18F2XJ10 PIC18F4XJ10 00-- ---- 00-- ---- uu-- ---- IPR2 PIC18F2XJ10 PIC18F4XJ10 11-- 1--1 11-- 1--1 uu-- u--u PIR2 PIC18F2XJ10 PIC18F4XJ10 00-- 0--0 00-- 0--0 uu-- u--u(3) PIE2 PIC18F2XJ10 PIC18F4XJ10 00-- 0--0 00-- 0--0 uu-- u--u IPR1 PIC18F2XJ10 PIC18F4XJ10 1111 1111 1111 1111 uuuu uuuu PIR1 PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu(3) PIE1 PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. DS39682E-page 49

PIC18F45J10 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets, WDT Reset, Power-on Reset, Wake-up via WDT Register Applicable Devices RESET Instruction, Brown-out Reset or Interrupt Stack Resets, CM Resets TRISE PIC18F2XJ10 PIC18F4XJ10 0000 -111 1111 -111 uuuu -uuu TRISD PIC18F2XJ10 PIC18F4XJ10 1111 1111 1111 1111 uuuu uuuu TRISC PIC18F2XJ10 PIC18F4XJ10 1111 1111 1111 1111 uuuu uuuu TRISB PIC18F2XJ10 PIC18F4XJ10 1111 1111 1111 1111 uuuu uuuu TRISA PIC18F2XJ10 PIC18F4XJ10 --1- 1111 --1- 1111 --u- uuuu SSP2BUF PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu LATE PIC18F2XJ10 PIC18F4XJ10 ---- -xxx ---- -uuu ---- -uuu LATD PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu LATC PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu LATB PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu LATA PIC18F2XJ10 PIC18F4XJ10 --xx xxxx --uu uuuu --uu uuuu SSP2ADD PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu SSP2STAT PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu SSP2CON1 PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu SSP2CON2 PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu PORTE PIC18F2XJ10 PIC18F4XJ10 ---- -xxx ---- -uuu ---- -uuu PORTD PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu PORTC PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu PORTB PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu PORTA PIC18F2XJ10 PIC18F4XJ10 --0- 0000 --0- 0000 --u- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table5-1 for Reset value for specific condition. DS39682E-page 50 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 6.0 MEMORY ORGANIZATION 6.1 Program Memory Organization There are two types of memory in PIC18 Enhanced PIC18 microcontrollers implement a 21-bit program microcontroller devices: counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between • Program Memory the upper boundary of the physically implemented • Data RAM memory and the 2-Mbyte address will return all ‘0’s (a As Harvard architecture devices, the data and program NOP instruction). memories use separate busses; this allows for The PIC18F24J10 and PIC18F44J10 each have concurrent access of the two memory spaces. 16Kbytes of Flash memory and can store up to Additional detailed information on the operation of the 8,192single-word instructions. The PIC18F25J10 and Flash program memory is provided in Section7.0 PIC18F45J10 each have 32Kbytes of Flash memory “Flash Program Memory”. and can store up to 16,384 single-word instructions. PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. The program memory map for the PIC18F45J10 family devices is shown in Figure6-1. FIGURE 6-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F45J10 FAMILY DEVICES PC<20:0> CALL,RCALL,RETURN 21 RETFIE,RETLW Stack Level 1 • • • Stack Level 31 Reset Vector 0000h High-Priority Interrupt Vector 0008h Low-Priority Interrupt Vector 0018h On-Chip On-Chip Program Memory Program Memory 3FF7h 4000h e c a PIC18FX4J10 Sp y 7FF7h or 8000h m e M er PIC18FX5J10 s U Read ‘0’ Read ‘0’ 1FFFFFh 200000h © 2009 Microchip Technology Inc. DS39682E-page 51

PIC18F45J10 FAMILY 6.1.1 HARD MEMORY VECTORS 6.1.2 FLASH CONFIGURATION WORDS All PIC18 devices have a total of three hard-coded Because PIC18F45J10 family devices do not have return vectors in their program memory space. The persistent configuration memory, the top four words of Reset vector address is the default value to which the on-chip program memory are reserved for configuration program counter returns on all device Resets; it is information. On Reset, the configuration information is located at 0000h. copied into the Configuration registers. PIC18 devices also have two interrupt vector The Configuration Words are stored in their program addresses for the handling of high-priority and low- memory location in numerical order, starting with the priority interrupts. The high-priority interrupt vector is lower byte of CONFIG1 at the lowest address and end- located at 0008h and the low-priority interrupt vector is ing with the upper byte of CONFIG4. For these devices, at 0018h. Their locations in relation to the program only Configuration Words, CONFIG1 through memory map are shown in Figure6-2. CONFIG3, are used; CONFIG4 is reserved. The actual addresses of the Flash Configuration Word for devices FIGURE 6-2: HARD VECTOR AND in the PIC18F45J10 family are shown in Table6-1. CONFIGURATION WORD Their location in the memory map is shown with the LOCATIONS FOR other memory vectors in Figure6-2. PIC18F45J10 FAMILY Additional details on the device Configuration Words DEVICES are provided in Section21.1 “Configuration Bits”. TABLE 6-1: FLASH CONFIGURATION Reset Vector 0000h WORD FOR PIC18F45J10 High-Priority Interrupt Vector 0008h FAMILY DEVICES Low-Priority Interrupt Vector 0018h Program Configuration Device Memory Word (Kbytes) Addresses PIC18F24J10 On-Chip 16 3FF8h to 3FFFh PIC18F44J10 Program Memory PIC18F25J10 32 7FF8h to 7FFFh PIC18F45J10 Flash Configuration Words (Top of Memory-7) (Top of Memory) Read ‘0’ 1FFFFFh Legend: (Top of Memory) represents upper boundary of on-chip program memory space (see Figure6-1 for device-specific values). Shaded area represents unimplemented memory. Areas are not shown to scale. DS39682E-page 52 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 6.1.3 PROGRAM COUNTER The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not The Program Counter (PC) specifies the address of the part of either program or data space. The Stack Pointer instruction to fetch for execution. The PC is 21 bits wide is readable and writable and the address on the top of and is contained in three separate 8-bit registers. The the stack is readable and writable through the top-of- low byte, known as the PCL register, is both readable stack Special Function Registers. Data can also be and writable. The high byte, or PCH register, contains pushed to, or popped from the stack, using these the PC<15:8> bits; it is not directly readable or writable. registers. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This A CALL type instruction causes a push onto the stack; register contains the PC<20:16> bits; it is also not the Stack Pointer is first incremented and the location directly readable or writable. Updates to the PCU pointed to by the Stack Pointer is written with the register are performed through the PCLATU register. contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes The contents of PCLATH and PCLATU are transferred a pop from the stack; the contents of the location to the program counter by any operation that writes pointed to by the STKPTR are transferred to the PC PCL. Similarly, the upper two bytes of the program and then the Stack Pointer is decremented. counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed The Stack Pointer is initialized to ‘00000’ after all offsets to the PC (see Section6.1.6.1 “Computed Resets. There is no RAM associated with the location GOTO”). corresponding to a Stack Pointer value of ‘00000’; this is only a Reset value. Status bits indicate if the stack is The PC addresses bytes in the program memory. To full or has overflowed or has underflowed. prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to 6.1.4.1 Top-of-Stack Access a value of ‘0’. The PC increments by 2 to address sequential instructions in the program memory. Only the top of the return address stack (TOS) is readable and writable. A set of three registers, The CALL, RCALL, GOTO and program branch TOSU:TOSH:TOSL, hold the contents of the stack loca- instructions write to the program counter directly. For tion pointed to by the STKPTR register (Figure6-3). This these instructions, the contents of PCLATH and allows users to implement a software stack if necessary. PCLATU are not transferred to the program counter. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU:TOSH:TOSL 6.1.4 RETURN ADDRESS STACK registers. These values can be placed on a user-defined The return address stack allows any combination of up software stack. At return time, the software can return to 31 program calls and interrupts to occur. The PC is these values to TOSU:TOSH:TOSL and do a return. pushed onto the stack when a CALL or RCALL instruc- The user must disable the global interrupt enable bits tion is executed or an interrupt is Acknowledged. The while accessing the stack to prevent inadvertent stack PC value is pulled off the stack on a RETURN, RETLW corruption. or RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. FIGURE 6-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack<20:0> 11111 11110 Top-of-Stack Registers Stack Pointer 11101 TOSU TOSH TOSL STKPTR<4:0> 00h 1Ah 34h 00010 00011 Top-of-Stack 001A34h 00010 000D58h 00001 00000 © 2009 Microchip Technology Inc. DS39682E-page 53

PIC18F45J10 FAMILY 6.1.4.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next pop will return a value of zero The STKPTR register (Register6-1) contains the Stack to the PC and sets the STKUNF bit, while the Stack Pointer value, the STKFUL (Stack Overflow) status bit Pointer remains at zero. The STKUNF bit will remain and the STKUNF (Stack Underflow) status bits. The set until cleared by software or until a POR occurs. value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed Note: Returning a value of zero to the PC on an onto the stack and decrements after values are popped underflow has the effect of vectoring the off the stack. On Reset, the Stack Pointer value will be program to the Reset vector, where the zero. The user may read and write the Stack Pointer stack conditions can be verified and value. This feature can be used by a Real-Time appropriate actions can be taken. This is Operating System (RTOS) for return stack not the same as a Reset, as the contents maintenance. of the SFRs are not affected. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is 6.1.4.3 PUSH and POP Instructions set. The STKFUL bit is cleared by software or by a Since the Top-of-Stack is readable and writable, the POR. ability to push values onto the stack and pull values off The action that takes place when the stack becomes the stack without disturbing normal program execution full depends on the state of the STVREN (Stack Over- is a desirable feature. The PIC18 instruction set flow Reset Enable) Configuration bit. (Refer to includes two instructions, PUSH and POP, that permit Section21.1 “Configuration Bits” for a description of the TOS to be manipulated under software control. the device Configuration bits.) If STVREN is set TOSU, TOSH and TOSL can be modified to place data (default), the 31st push will push the (PC + 2) value or a return address on the stack. onto the stack, set the STKFUL bit and reset the The PUSH instruction places the current PC value onto device. The STKFUL bit will remain set and the Stack the stack. This increments the Stack Pointer and loads Pointer will be set to zero. the current PC value onto the stack. If STVREN is cleared, the STKFUL bit will be set on the The POP instruction discards the current TOS by decre- 31st push and the Stack Pointer will increment to 31. menting the Stack Pointer. The previous value pushed Any additional pushes will not overwrite the 31st push onto the stack then becomes the TOS value. and the STKPTR will remain at 31. REGISTER 6-1: STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP<4:0>: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. DS39682E-page 54 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 6.1.4.4 Stack Full and Underflow Resets 6.1.6 LOOK-UP TABLES IN PROGRAM MEMORY Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in There may be programming situations that require the Configuration Register 4L. When STVREN is set, a full creation of data structures, or look-up tables, in or underflow will set the appropriate STKFUL or program memory. For PIC18 devices, look-up tables STKUNF bit and then cause a device Reset. When can be implemented in two ways: STVREN is cleared, a full or underflow condition will set • Computed GOTO the appropriate STKFUL or STKUNF bit but not cause • Table Reads a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a Power-on Reset. 6.1.6.1 Computed GOTO 6.1.5 FAST REGISTER STACK A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in A Fast Register Stack is provided for the STATUS, Example6-2. WREG and BSR registers, to provide a “fast return” option for interrupts. The stack for each register is only A look-up table can be formed with an ADDWF PCL one level deep and is neither readable nor writable. It is instruction and a group of RETLW nn instructions. The loaded with the current value of the corresponding W register is loaded with an offset into the table before register when the processor vectors for an interrupt. All executing a call to that table. The first instruction of the interrupt sources will push values into the stack regis- called routine is the ADDWF PCL instruction. The next ters. The values in the registers are then loaded back instruction executed will be one of the RETLW nn into their associated registers if the RETFIE, FAST instructions that returns the value ‘nn’ to the calling instruction is used to return from the interrupt. function. If both low and high-priority interrupts are enabled, the The offset value (in WREG) specifies the number of stack registers cannot be used reliably to return from bytes that the program counter should advance and low-priority interrupts. If a high-priority interrupt occurs should be multiples of 2 (LSb = 0). while servicing a low-priority interrupt, the stack regis- In this method, only one data byte may be stored in ter values stored by the low-priority interrupt will be each instruction location and room on the return overwritten. In these cases, users must save the key address stack is required. registers in software during a low-priority interrupt. If interrupt priority is not used, all interrupts may use the EXAMPLE 6-2: COMPUTED GOTO USING Fast Register Stack for returns from interrupt. If no AN OFFSET VALUE interrupts are used, the Fast Register Stack can be MOVF OFFSET, W used to restore the STATUS, WREG and BSR registers CALL TABLE at the end of a subroutine call. To use the Fast Register ORG nn00h Stack for a subroutine call, a CALL label, FAST TABLE ADDWF PCL instruction must be executed to save the STATUS, RETLW nnh WREG and BSR registers to the Fast Register Stack. A RETLW nnh RETURN, FAST instruction is then executed to restore RETLW nnh these registers from the Fast Register Stack. . . Example6-1 shows a source code example that uses . the Fast Register Stack during a subroutine call and return. 6.1.6.2 Table Reads and Table Writes EXAMPLE 6-1: FAST REGISTER STACK A better method of storing data in program memory CODE EXAMPLE allows two bytes of data to be stored in each instruction location. CALL SUB1, FAST ;STATUS, WREG, BSR Look-up table data may be stored two bytes per pro- ;SAVED IN FAST REGISTER ;STACK gram word by using table reads and writes. The Table • Pointer (TBLPTR) register specifies the byte address • and the Table Latch (TABLAT) register contains the data that is read from or written to program memory. SUB1 • Data is transferred to or from program memory one • byte at a time. RETURN, FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK Table read and table write operations are discussed further in Section7.1 “Table Reads and Table Writes”. © 2009 Microchip Technology Inc. DS39682E-page 55

PIC18F45J10 FAMILY 6.2 PIC18 Instruction Cycle 6.2.2 INSTRUCTION FLOW/PIPELINING An “Instruction Cycle” consists of four Q cycles: Q1 6.2.1 CLOCKING SCHEME through Q4. The instruction fetch and execute are The microcontroller clock input, whether from an pipelined in such a manner that a fetch takes one internal or external source, is internally divided by four instruction cycle, while the decode and execute take to generate four non-overlapping quadrature clocks another instruction cycle. However, due to the pipe- (Q1, Q2, Q3 and Q4). Internally, the program counter is lining, each instruction effectively executes in one incremented on every Q1; the instruction is fetched cycle. If an instruction causes the program counter to from the program memory and latched into the instruc- change (e.g., GOTO), then two cycles are required to tion register during Q4. The instruction is decoded and complete the instruction (Example6-3). executed during the following Q1 through Q4. The A fetch cycle begins with the Program Counter (PC) clocks and instruction execution flow are shown in incrementing in Q1. Figure6-4. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 6-4: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Q3 Clock Q4 PC PC PC + 2 PC + 4 OSC2/CLKO (RC mode) Execute INST (PC – 2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 2) Fetch INST (PC + 4) EXAMPLE 6-3: INSTRUCTION PIPELINE FLOW TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. BRA SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP) 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. DS39682E-page 56 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 6.2.3 INSTRUCTIONS IN PROGRAM The CALL and GOTO instructions have the absolute pro- MEMORY gram memory address embedded into the instruction. Since instructions are always stored on word boundar- The program memory is addressed in bytes. Instruc- ies, the data contained in the instruction is a word tions are stored as two bytes or four bytes in program address. The word address is written to PC<20:1>, memory. The Least Significant Byte of an instruction which accesses the desired byte address in program word is always stored in a program memory location memory. Instruction #2 in Figure6-5 shows how the with an even address (LSB = 0). To maintain alignment instruction, GOTO 0006h, is encoded in the program with instruction boundaries, the PC increments in steps memory. Program branch instructions, which encode a of 2 and the LSB will always read ‘0’ (see Section6.1.3 relative address offset, operate in the same manner. The “Program Counter”). offset value stored in a branch instruction represents the Figure6-5 shows an example of how instruction words number of single-word instructions that the PC will be are stored in the program memory. offset by. Section22.0 “Instruction Set Summary” provides further details of the instruction set. FIGURE 6-5: INSTRUCTIONS IN PROGRAM MEMORY Word Address LSB = 1 LSB = 0 ↓ Program Memory 000000h Byte Locations → 000002h 000004h 000006h Instruction 1: MOVLW 055h 0Fh 55h 000008h Instruction 2: GOTO 0006h EFh 03h 00000Ah F0h 00h 00000Ch Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh F4h 56h 000010h 000012h 000014h 6.2.4 TWO-WORD INSTRUCTIONS the instruction sequence. If the first word is skipped for some reason and the second word is executed by itself, The standard PIC18 instruction set has four two-word a NOP is executed instead. This is necessary for cases instructions: CALL, MOVFF, GOTO and LSFR. In all when the two-word instruction is preceded by a condi- cases, the second word of the instructions always has tional instruction that changes the PC. Example6-4 ‘1111’ as its four Most Significant bits; the other 12 bits shows how this works. are literal data, usually a data memory address. The use of ‘1111’ in the 4 MSbs of an instruction spec- Note: See Section6.6 “PIC18 Instruction ifies a special form of NOP. If the instruction is executed Execution and the Extended Instruc- tion Set” for information on two-word in proper sequence – immediately after the first word – the data in the second word is accessed and used by instructions in the extended instruction set. EXAMPLE 6-4: TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word 1111 0100 0101 0110 ; Execute this word as a NOP 0010 0100 0000 0000 ADDWF REG3 ; continue code CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 ADDWF REG3 ; continue code © 2009 Microchip Technology Inc. DS39682E-page 57

PIC18F45J10 FAMILY 6.3 Data Memory Organization 6.3.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient Note: The operation of some aspects of data addressing scheme to make rapid access to any memory are changed when the PIC18 address possible. Ideally, this means that an entire extended instruction set is enabled. See address does not need to be provided for each read or Section6.5 “Data Memory and the write operation. For PIC18 devices, this is accom- Extended Instruction Set” for more plished with a RAM banking scheme. This divides the information. memory space into 16 contiguous banks of 256 bytes. The data memory in PIC18 devices is implemented as Depending on the instruction, each location can be static RAM. Each register in the data memory has a addressed directly by its full 12-bit address, or an 8-bit 12-bit address, allowing up to 4096 bytes of data low-order address and a 4-bit Bank Pointer. memory. The memory space is divided into as many as Most instructions in the PIC18 instruction set make use 16banks that contain 256 bytes each; PIC18F45J10 of the Bank Pointer, known as the Bank Select Register family devices implement all 16banks. Figure6-6 (BSR). This SFR holds the 4 Most Significant bits of a shows the data memory organization for the location’s address; the instruction itself includes the PIC18F45J10 family devices. 8Least Significant bits. Only the four lower bits of the The data memory contains Special Function Registers BSR are implemented (BSR<3:0>). The upper four bits (SFRs) and General Purpose Registers (GPRs). The are unused; they will always read ‘0’ and cannot be SFRs are used for control and status of the controller written to. The BSR can be loaded directly by using the and peripheral functions, while GPRs are used for data MOVLB instruction. storage and scratchpad operations in the user’s The value of the BSR indicates the bank in data application. Any read of an unimplemented location will memory. The 8 bits in the instruction show the location read as ‘0’s. in the bank and can be thought of as an offset from the The instruction set and architecture allow operations bank’s lower boundary. The relationship between the across all banks. The entire data memory may be BSR’s value and the bank division in data memory is accessed by Direct, Indirect or Indexed Addressing shown in Figure6-7. modes. Addressing modes are discussed later in this Since up to 16 registers may share the same low-order subsection. address, the user must always be careful to ensure that To ensure that commonly used registers (SFRs and the proper bank is selected before performing a data select GPRs) can be accessed in a single cycle, PIC18 read or write. For example, writing what should be devices implement an Access Bank. This is a 256-byte program data to an 8-bit address of F9h while the BSR memory space that provides fast access to SFRs and is 0Fh will end up resetting the program counter. the lower portion of GPR Bank 0 without using the While any bank can be selected, only those banks that BSR. Section6.3.2 “Access Bank” provides a are actually implemented can be read or written to. detailed description of the Access RAM. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return ‘0’s. Even so, the STATUS register will still be affected as if the operation was successful. The data memory map in Figure6-6 indicates which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. DS39682E-page 58 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY FIGURE 6-6: DATA MEMORY MAP FOR PIC18F45J10 FAMILY DEVICES When ‘a’ = 0: BSR<3:0> Data Memory Map The BSR is ignored and the 000h Access Bank is used. 00h Access RAM = 0000 07Fh Bank 0 080h The first 128 bytes are FFh GPR 0FFh general purpose RAM 00h 100h (from Bank 0). = 0001 Bank 1 GPR The second 128 bytes are FFh 1FFh Special Function Registers = 0010 00h 200h (from Bank 15). Bank 2 GPR FFh 2FFh When ‘a’ = 1: = 0011 Bank 3 00h 300h The BSR specifies the Bank GPR used by the instruction. FFh 3FFh 00h 400h = 0100 Bank 4 FFh 4FFh = 0101 00h 500h Bank 5 FFh 5FFh = 0110 00h 600h Bank 6 Access Bank FFh 6FFh = 0111 00h 700h 00h Bank 7 Access RAM Low 7Fh FFh 7FFh 80h Access RAM High = 1000 00h 800h (SFRs) FFh Bank 8 FFh 8FFh = 1001 00h Unused 900h Bank 9 Read 00h FFh 9FFh = 1010 00h A00h Bank 10 FFh AFFh = 1011 00h B00h Bank 11 FFh BFFh C00h = 1100 00h Bank 12 CFFh FFh D00h = 1101 00h Bank 13 DFFh FFh 00h E00h = 1110 Bank 14 FFh EFFh = 1111 00h Unused FF70F0hh Bank 15 F80h FFh SFR FFFh © 2009 Microchip Technology Inc. DS39682E-page 59

PIC18F45J10 FAMILY FIGURE 6-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) Data Memory From Opcode(2) 7 0 000h 00h 7 0 0 0 0 0 0 0 1 1 Bank 0 FFh 1 1 1 1 1 1 1 1 100h 00h Bank 1 Bank Select(2) FFh 200h 00h Bank 2 300h FFh 00h Bank 3 through Bank 13 FFh E00h 00h Bank 14 F00h FFh 00h Bank 15 FFFh FFh Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. 6.3.2 ACCESS BANK however, the instruction is forced to use the Access Bank address map; the current value of the BSR is While the use of the BSR with an embedded 8-bit ignored entirely. address allows users to address the entire range of data memory, it also means that the user must always Using this “forced” addressing allows the instruction to ensure that the correct bank is selected. Otherwise, operate on a data address in a single cycle without data may be read from or written to the wrong location. updating the BSR first. For 8-bit addresses of 80h and This can be disastrous if a GPR is the intended target above, this means that users can evaluate and operate of an operation but an SFR is written to instead. on SFRs more efficiently. The Access RAM below 80h Verifying and/or changing the BSR for each read or is a good place for data values that the user might need write to data memory can become very inefficient. to access rapidly, such as immediate computational results or common program variables. Access RAM To streamline access for the most commonly used data also allows for faster and more code efficient context memory locations, the data memory is configured with saving and switching of variables. an Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The mapping of the Access Bank is slightly different The Access Bank consists of the first 128 bytes of when the extended instruction set is enabled (XINST memory (00h-7Fh) in Bank 0 and the last 128 bytes of Configuration bit = 1). This is discussed in more detail memory (80h-FFh) in Block 15. The lower half is known in Section6.5.3 “Mapping the Access Bank in as the “Access RAM” and is composed of GPRs. This Indexed Literal Offset Mode”. upper half is also where the device’s SFRs are 6.3.3 GENERAL PURPOSE REGISTER mapped. These two areas are mapped contiguously in the Access Bank and can be addressed in a linear FILE fashion by an 8-bit address (Figure6-6). PIC18 devices may have banked memory in the GPR The Access Bank is used by core PIC18 instructions area. This is data RAM which is available for use by all that include the Access RAM bit (the ‘a’ parameter in instructions. GPRs start at the bottom of Bank 0 the instruction). When ‘a’ is equal to ‘1’, the instruction (address 000h) and grow upwards towards the bottom of uses the BSR and the 8-bit address included in the the SFR area. GPRs are not initialized by a Power-on opcode for the data memory address. When ‘a’ is ‘0’, Reset and are unchanged on all other Resets. DS39682E-page 60 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 6.3.4 SPECIAL FUNCTION REGISTERS The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, The Special Function Registers (SFRs) are registers Resets and interrupts) and those related to the periph- used by the CPU and peripheral modules for controlling eral functions. The Reset and Interrupt registers are the desired operation of the device. These registers are described in their respective chapters, while the ALU’s implemented as static RAM. SFRs start at the top of STATUS register is described later in this section. data memory (FFFh) and extend downward to occupy Registers related to the operation of a peripheral feature the top half of Bank 15 (F80h to FFFh). A list of these are described in the chapter for that peripheral. registers is given in Table6-2 and Table6-3. The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR locations are unimplemented and read as ‘0’s. TABLE 6-2: SPECIAL FUNCTION REGISTER MAP FOR PIC18F45J10 FAMILY DEVICES Address Name Address Name Address Name Address Name FFFh TOSU FDFh INDF2(1) FBFh CCPR1H F9Fh IPR1 FFEh TOSH FDEh POSTINC2(1) FBEh CCPR1L F9Eh PIR1 FFDh TOSL FDDh POSTDEC2(1) FBDh CCP1CON F9Dh PIE1 FFCh STKPTR FDCh PREINC2(1) FBCh CCPR2H F9Ch —(2) FFBh PCLATU FDBh PLUSW2(1) FBBh CCPR2L F9Bh —(2) FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah —(2) FF9h PCL FD9h FSR2L FB9h —(2) F99h —(2) FF8h TBLPTRU FD8h STATUS FB8h BAUDCON F98h —(2) FF7h TBLPTRH FD7h TMR0H FB7h ECCP1DEL(3) F97h —(2) FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS(3) F96h TRISE(3) FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD(3) FF4h PRODH FD4h —(2) FB4h CMCON F94h TRISC FF3h PRODL FD3h OSCCON FB3h —(2) F93h TRISB FF2h INTCON FD2h —(2) FB2h —(2) F92h TRISA FF1h INTCON2 FD1h WDTCON FB1h —(2) F91h —(2) FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h —(2) FEFh INDF0(1) FCFh TMR1H FAFh SPBRG F8Fh —(2) FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG F8Eh SSP2BUF FEDh POSTDEC0(1) FCDh T1CON FADh TXREG F8Dh LATE(3) FECh PREINC0(1) FCCh TMR2 FACh TXSTA F8Ch LATD(3) FEBh PLUSW0(1) FCBh PR2 FABh RCSTA F8Bh LATC FEAh FSR0H FCAh T2CON FAAh —(2) F8Ah LATB FE9h FSR0L FC9h SSP1BUF FA9h —(2) F89h LATA FE8h WREG FC8h SSP1ADD FA8h —(2) F88h SSP2ADD(3) FE7h INDF1(1) FC7h SSP1STAT FA7h EECON2(1) F87h SSP2STAT(3) FE6h POSTINC1(1) FC6h SSP1CON1 FA6h EECON1 F86h SSP2CON1(3) FE5h POSTDEC1(1) FC5h SSP1CON2 FA5h IPR3 F85h SSP2CON2(3) FE4h PREINC1(1) FC4h ADRESH FA4h PIR3 F84h PORTE(3) FE3h PLUSW1(1) FC3h ADRESL FA3h PIE3 F83h PORTD(3) FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA Note 1: This is not a physical register. 2: Unimplemented registers are read as ‘0’. 3: This register is not available in 28-pin devices. © 2009 Microchip Technology Inc. DS39682E-page 61

PIC18F45J10 FAMILY TABLE 6-3: REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 47, 53 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 47, 53 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 47, 53 STKPTR STKFUL STKUNF — Return Stack Pointer 00-0 0000 47, 54 PCLATU — — — Holding Register for PC<20:16> ---0 0000 47, 53 PCLATH Holding Register for PC<15:8> 0000 0000 47, 53 PCL PC Low Byte (PC<7:0>) 0000 0000 47, 53 TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 47, 74 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 47, 74 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 47, 74 TABLAT Program Memory Table Latch 0000 0000 47, 74 PRODH Product Register High Byte xxxx xxxx 47, 81 PRODL Product Register Low Byte xxxx xxxx 47, 81 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 47, 85 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 1111 -1-1 47, 86 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 47, 87 INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 47, 67 POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 47, 67 POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 47, 67 PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 47, 67 PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – N/A 47, 67 value of FSR0 offset by W FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- xxxx 47, 67 FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 47, 67 WREG Working Register xxxx xxxx 47 INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 47, 67 POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 47, 67 POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 47, 67 PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 47, 67 PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – N/A 47, 67 value of FSR1 offset by W FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- xxxx 47, 67 FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 47, 67 BSR — — — — Bank Select Register ---- 0000 47, 58 INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 48, 67 POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 48, 67 POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 48, 67 PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 48, 67 PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – N/A 48, 67 value of FSR2 offset by W FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- xxxx 48, 67 FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 48, 67 STATUS — — — N OV Z DC C ---x xxxx 48, 65 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: See Section5.4 “Brown-out Reset (BOR) (PIC18F2XJ10/4XJ10 Devices Only)”. 2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as ‘-’. 3: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section16.4.3.2 “Address Masking” for details. DS39682E-page 62 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY TABLE 6-3: REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10) (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: TMR0H Timer0 Register High Byte 0000 0000 48, 117 TMR0L Timer0 Register Low Byte xxxx xxxx 48, 117 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 48, 115 OSCCON IDLEN — — — OSTS — SCS1 SCS0 0--- q-00 32, 48 WDTCON — — — — — — — SWDTEN --- ---0 48, 242 RCON IPEN — CM RI TO PD POR BOR(1) 0-11 11q0 42, 46, 94 TMR1H Timer1 Register High Byte xxxx xxxx 48, 124 TMR1L Timer1 Register Low Byte xxxx xxxx 48, 124 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 48, 119 TMR2 Timer2 Register 0000 0000 48, 126 PR2 Timer2 Period Register 1111 1111 48, 126 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 48, 125 SSP1BUF MSSP1 Receive Buffer/Transmit Register xxxx xxxx 48, 158 SSP1ADD MSSP1 Address Register in I2C™ Slave mode. MSSP1 Baud Rate Reload Register in I2C Master mode. 0000 0000 48, 159 SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 48, 150, 160 SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 48, 151, 161 SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 48, 162 GCEN ACKSTAT ADMSK5(3) ADMSK4(3) ADMSK3(3) ADMSK2(3) ADMSK1(3) SEN 0000 0000 48, 163 ADRESH A/D Result Register High Byte xxxx xxxx 48, 223 ADRESL A/D Result Register Low Byte xxxx xxxx 48, 223 ADCON0 ADCAL — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0-00 0000 48, 218 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0qqq 48, 218 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 48, 218 CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 49, 128 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 49, 128 CCP1CON P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 49, 128, CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 49, 128 CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 49, 128 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 49, 128 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 49, 196 ECCP1DEL PRSEN PDC6(2) PDC5(2) PDC4(2) PDC3(2) PDC2(2) PDC1(2) PDC0(2) 0000 0000 49, 144 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(2) PSSBD0(2) 0000 0000 49, 146 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 49, 232 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 49, 226 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: See Section5.4 “Brown-out Reset (BOR) (PIC18F2XJ10/4XJ10 Devices Only)”. 2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as ‘-’. 3: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section16.4.3.2 “Address Masking” for details. © 2009 Microchip Technology Inc. DS39682E-page 63

PIC18F45J10 FAMILY TABLE 6-3: REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10) (CONTINUED) Value on Details File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR on page: SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 49, 198 SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 49, 198 RCREG EUSART Receive Register 0000 0000 49, 205 TXREG EUSART Transmit Register xxxx xxxx 49, 203 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 49, 196 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 49, 195 EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 49, 72 EECON1 — — — FREE WRERR WREN WR — ---0 x00- 49, 74 IPR3 SSP2IP BCL2IP — — — — — — 11-- ---- 49, 94 PIR3 SSP2IF BCL2IF — — — — — — 00-- ---- 49, 90 PIE3 SSP2IE BCL2IE — — — — — — 00-- ---- 49, 92 IPR2 OSCFIP CMIP — — BCL1IP — — CCP2IP 11-- 1--1 49, 93 PIR2 OSCFIF CMIF — — BCL1IF — — CCP2IF 00-- 0--0 49, 89 PIE2 OSCFIE CMIE — — BCL1IE — — CCP2IE 00-- 0--0 49, 91 IPR1 PSPIP(2) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 1111 1111 49, 92 PIR1 PSPIF(2) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 49, 88 PIE1 PSPIE(2) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 49, 91 TRISE(2) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 50, 112 TRISD(2) PORTD Data Direction Control Register 1111 1111 50, 107 TRISC PORTC Data Direction Control Register 1111 1111 50, 104 TRISB PORTB Data Direction Control Register 1111 1111 50, 101 TRISA — — TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 --1- 1111 50, 98 SSP2BUF MSSP2 Receive Buffer/Transmit Register xxxx xxxx 50, 158 LATE(2) — — — — — PORTE Data Latch Register ---- -xxx 50, 110 (Read and Write to Data Latch) LATD(2) PORTD Data Latch Register (Read and Write to Data Latch) xxxx xxxx 50, 107 LATC PORTC Data Latch Register (Read and Write to Data Latch) xxxx xxxx 50, 104 LATB PORTB Data Latch Register (Read and Write to Data Latch) xxxx xxxx 50, 101 LATA — — PORTA Data Latch Register (Read and Write to Data Latch) --xx xxxx 50, 98 SSP2ADD MSSP2 Address Register in I2C™ Slave mode. MSSP2 Baud Rate Reload Register in I2C Master mode. 0000 0000 50, 158 SSP2STAT SMP CKE D/A P S R/W UA BF 0000 0000 50, 150, 160 SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 50, 151, 161 SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 50, 164 GCEN ACKSTAT ADMSK5(3) ADMSK4(3) ADMSK3(3) ADMSK2(3) ADMSK1(3) SEN 0000 0000 48, 163 PORTE(2) — — — — — RE2(2) RE1(2) RE0(2) ---- -xxx 50, 110 PORTD(2) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 50, 107 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 50, 104 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 50, 101 PORTA — — RA5 — RA3 RA2 RA1 RA0 --0- 0000 50, 98 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: See Section5.4 “Brown-out Reset (BOR) (PIC18F2XJ10/4XJ10 Devices Only)”. 2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as ‘-’. 3: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section16.4.3.2 “Address Masking” for details. DS39682E-page 64 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 6.3.5 STATUS REGISTER It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS The STATUS register, shown in Register6-2, contains register, because these instructions do not affect the Z, the arithmetic status of the ALU. As with any other SFR, C, DC, OV or N bits in the STATUS register. it can be the operand for any instruction. For other instructions that do not affect Status bits, see If the STATUS register is the destination for an instruc- the instruction set summaries in Table22-2 and tion that affects the Z, DC, C, OV or N bits, the results Table22-3. of the instruction are not written; instead, the STATUS register is updated according to the instruction Note: The C and DC bits operate as the borrow performed. Therefore, the result of an instruction with and digit borrow bits, respectively, in the STATUS register as its destination may be different subtraction. than intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (‘000u u1uu’). REGISTER 6-2: STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC(1) C(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit(1) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(2) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’scomplement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. 2: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’scomplement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2009 Microchip Technology Inc. DS39682E-page 65

PIC18F45J10 FAMILY 6.4 Data Addressing Modes The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR Note: The execution of some instructions in the (Section6.3.1 “Bank Select Register (BSR)”) are core PIC18 instruction set are changed used with the address to determine the complete 12-bit when the PIC18 extended instruction set is address of the register. When ‘a’ is ‘0’, the address is enabled. See Section6.5 “Data Memory interpreted as being a register in the Access Bank. and the Extended Instruction Set” for Addressing that uses the Access RAM is sometimes more information. also known as Direct Forced Addressing mode. While the program memory can be addressed in only A few instructions, such as MOVFF, include the entire one way – through the program counter – information 12-bit address (either source or destination) in their in the data memory space can be addressed in several opcodes. In these cases, the BSR is ignored entirely. ways. For most instructions, the addressing mode is The destination of the operation’s results is determined fixed. Other instructions may use up to three modes, by the destination bit ‘d’. When ‘d’ is ‘1’, the results are depending on which operands are used and whether or stored back in the source register, overwriting its origi- not the extended instruction set is enabled. nal contents. When ‘d’ is ‘0’, the results are stored in The addressing modes are: the W register. Instructions without the ‘d’ argument have a destination that is implicit in the instruction; their • Inherent destination is either the target register being operated • Literal on or the W register. • Direct 6.4.3 INDIRECT ADDRESSING • Indirect An additional addressing mode, Indexed Literal Offset, Indirect Addressing allows the user to access a location is available when the extended instruction set is in data memory without giving a fixed address in the enabled (XINST Configuration bit = 1). Its operation is instruction. This is done by using File Select Registers discussed in greater detail in Section6.5.1 “Indexed (FSRs) as pointers to the locations to be read or written Addressing with Literal Offset”. to. Since the FSRs are themselves located in RAM as Special Function Registers, they can also be directly 6.4.1 INHERENT AND LITERAL manipulated under program control. This makes FSRs ADDRESSING very useful in implementing data structures, such as tables and arrays in data memory. Many PIC18 control instructions do not need any argument at all; they either perform an operation that The registers for Indirect Addressing are also globally affects the device or they operate implicitly on implemented with Indirect File Operands (INDFs) that one register. This addressing mode is known as Inherent permit automatic manipulation of the pointer value with Addressing. Examples include SLEEP, RESET and DAW. auto-incrementing, auto-decrementing or offsetting with another value. This allows for efficient code, using Other instructions work in a similar way but require an loops, such as the example of clearing an entire RAM additional explicit argument in the opcode. This is bank in Example6-5. known as Literal Addressing mode because they require some literal value as an argument. Examples EXAMPLE 6-5: HOW TO CLEAR RAM include ADDLW and MOVLW, which respectively, add or (BANK 1) USING move a literal value to the W register. Other examples INDIRECT ADDRESSING include CALL and GOTO, which include a 20-bit program memory address. LFSR FSR0, 100h ; NEXT CLRF POSTINC0 ; Clear INDF 6.4.2 DIRECT ADDRESSING ; register then Direct Addressing specifies all or part of the source ; inc pointer BTFSS FSR0H, 1 ; All done with and/or destination address of the operation within the ; Bank1? opcode itself. The options are specified by the BRA NEXT ; NO, clear next arguments accompanying the instruction. CONTINUE ; YES, continue In the core PIC18 instruction set, bit-oriented and byte- oriented instructions use some version of Direct Addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section6.3.3 “General Purpose Register File”) or a location in the Access Bank (Section6.3.2 “Access Bank”) as the data source for the instruction. DS39682E-page 66 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 6.4.3.1 FSR Registers and the INDF 6.4.3.2 FSR Registers and POSTINC, Operand POSTDEC, PREINC and PLUSW At the core of Indirect Addressing are three sets of reg- In addition to the INDF operand, each FSR register pair isters: FSR0, FSR1 and FSR2. Each represents a pair also has four additional indirect operands. Like INDF, of 8-bit registers, FSRnH and FSRnL. The four upper these are “virtual” registers that cannot be indirectly bits of the FSRnH register are not used, so each FSR read or written to. Accessing these registers actually pair holds a 12-bit value. This represents a value that accesses the associated FSR register pair, but also can address the entire range of the data memory in a performs a specific action on it stored value. They are: linear fashion. The FSR register pairs, then, serve as • POSTDEC: accesses the FSR value, then pointers to data memory locations. automatically decrements it by 1 afterwards Indirect Addressing is accomplished with a set of • POSTINC: accesses the FSR value, then Indirect File Operands, INDF0 through INDF2. These automatically increments it by 1 afterwards can be thought of as “virtual” registers; they are • PREINC: increments the FSR value by 1, then mapped in the SFR space but are not physically imple- uses it in the operation mented. Reading or writing to a particular INDF register • PLUSW: adds the signed value of the W register actually accesses its corresponding FSR register pair. (range of -127 to 128) to that of the FSR and uses A read from INDF1, for example, reads the data at the the new value in the operation. address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the In this context, accessing an INDF register uses the contents of their corresponding FSR as a pointer to the value in the FSR registers without changing them. Sim- instruction’s target. The INDF operand is just a ilarly, accessing a PLUSW register gives the FSR value convenient way of using the pointer. offset by that in the W register; neither value is actually changed in the operation. Accessing the other virtual Because Indirect Addressing uses a full 12-bit address, registers changes the value of the FSR registers. data RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no Operations on the FSRs with POSTDEC, POSTINC effect on determining the target address. and PREINC affect the entire register pair; that is, roll- overs of the FSRnL register, from FFh to 00h, carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). FIGURE 6-8: INDIRECT ADDRESSING 000h Using an instruction with one of the ADDWF, INDF1, 1 Bank 0 Indirect Addressing registers as the 100h operand.... Bank 1 200h Bank 2 300h ...uses the 12-bit address stored in FSR1H:FSR1L the FSR pair associated with that 7 0 7 0 register.... Bank 3 x x x x 1 1 1 0 1 1 0 0 1 1 0 0 through Bank 13 ...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains E00h ECCh. This means the contents of Bank 14 location ECCh will be added to that F00h of the W register and stored back in Bank 15 ECCh. FFFh Data Memory © 2009 Microchip Technology Inc. DS39682E-page 67

PIC18F45J10 FAMILY The PLUSW register can be used to implement a form 6.5.1 INDEXED ADDRESSING WITH of Indexed Addressing in the data memory space. By LITERAL OFFSET manipulating the value in the W register, users can Enabling the PIC18 extended instruction set changes reach addresses that are fixed offsets from pointer the behavior of Indirect Addressing using the FSR2 addresses. In some applications, this can be used to register pair within Access RAM. Under the proper implement some powerful program control structure, conditions, instructions that use the Access Bank – that such as software stacks, inside of data memory. is, most bit-oriented and byte-oriented instructions – 6.4.3.3 Operations by FSRs on FSRs can invoke a form of Indexed Addressing using an offset specified in the instruction. This special address- Indirect Addressing operations that target other FSRs ing mode is known as Indexed Addressing with Literal or virtual registers represent special cases. For Offset, or Indexed Literal Offset mode. example, using an FSR to point to one of the virtual When using the extended instruction set, this registers will not result in successful operations. As a addressing mode requires the following: specific case, assume that FSR0H:FSR0L contains FE7h, the address of INDF1. Attempts to read the • The use of the Access Bank is forced (‘a’ = 0) and value of the INDF1 using INDF0 as an operand will • The file address argument is less than or equal to return 00h. Attempts to write to INDF1 using INDF0 as 5Fh. the operand will result in a NOP. Under these conditions, the file address of the instruc- On the other hand, using the virtual registers to write to tion is not interpreted as the lower byte of an address an FSR pair may not occur as planned. In these cases, (used with the BSR in direct addressing), or as an 8-bit the value will be written to the FSR pair but without any address in the Access Bank. Instead, the value is incrementing or decrementing. Thus, writing to INDF2 interpreted as an offset value to an Address Pointer, or POSTDEC2 will write the same value to the specified by FSR2. The offset and the contents of FSR2H:FSR2L. FSR2 are added to obtain the target address of the Since the FSRs are physical registers mapped in the operation. SFR space, they can be manipulated through all direct 6.5.2 INSTRUCTIONS AFFECTED BY operations. Users should proceed cautiously when INDEXED LITERAL OFFSET MODE working on these registers, particularly if their code uses indirect addressing. Any of the core PIC18 instructions that can use Direct Similarly, operations by Indirect Addressing are gener- Addressing are potentially affected by the Indexed ally permitted on all other SFRs. Users should exercise Literal Offset Addressing mode. This includes all the appropriate caution that they do not inadvertently byte-oriented and bit-oriented instructions, or almost change settings that might affect the operation of the one-half of the standard PIC18 instruction set. device. Instructions that only use Inherent or Literal Addressing modes are unaffected. 6.5 Data Memory and the Extended Additionally, byte-oriented and bit-oriented instructions Instruction Set are not affected if they do not use the Access Bank (Access RAM bit is ‘1’), or include a file address of 60h Enabling the PIC18 extended instruction set (XINST or above. Instructions meeting these criteria will Configuration bit = 1) significantly changes certain continue to execute as before. A comparison of the aspects of data memory and its addressing. Specifi- different possible addressing modes when the cally, the use of the Access Bank for many of the core extended instruction set is enabled in shown in PIC18 instructions is different; this is due to the Figure6-9. introduction of a new addressing mode for the data Those who desire to use byte-oriented or bit-oriented memory space. instructions in the Indexed Literal Offset mode should What does not change is just as important. The size of note the changes to assembler syntax for this mode. the data memory space is unchanged, as well as its This is described in more detail in Section22.2.1 linear addressing. The SFR map remains the same. “Extended Instruction Syntax”. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remains unchanged. DS39682E-page 68 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY FIGURE 6-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) Example Instruction: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) 000h When ‘a’ = 0 and f ≥ 60h: The instruction executes in 060h Direct Forced mode. ‘f’ is inter- 080h Bank 0 preted as a location in the 100h Access RAM between 060h 00h and 0FFh. This is the same as Bank 1 through 60h locations 060h to 07Fh Bank 14 80h (Bank0) and F80h to FFFh Valid Range for ‘f’ (Bank 15) of data memory. FFh Locations below 60h are not F00h Access RAM available in this addressing Bank 15 mode. F80h SFRs FFFh Data Memory When ‘a’ = 0 and f ≤ 5Fh: 000h The instruction executes in Bank 0 Indexed Literal Offset mode. ‘f’ 080h is interpreted as an offset to the address value in FSR2. The 100h 001001da ffffffff two are added together to Bank 1 obtain the address of the target through register for the instruction. The Bank 14 address can be anywhere in FSR2H FSR2L the data memory space. F00h Note that in this mode, the Bank 15 correct syntax is now: F80h ADDWF [k], d SFRs where ‘k’ is the same as ‘f’. FFFh Data Memory BSR When ‘a’ = 1 (all values of f): 000h 00000000 The instruction executes in Bank 0 080h Direct mode (also known as Direct Long mode). ‘f’ is inter- 100h preted as a location in one of the 16 banks of the data Bank 1 001001da ffffffff memory space. The bank is through Bank 14 designated by the Bank Select Register (BSR). The address can be in any implemented F00h bank in the data memory Bank 15 space. F80h SFRs FFFh Data Memory © 2009 Microchip Technology Inc. DS39682E-page 69

PIC18F45J10 FAMILY 6.5.3 MAPPING THE ACCESS BANK IN Remapping of the Access Bank applies only to opera- INDEXED LITERAL OFFSET MODE tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue The use of Indexed Literal Offset Addressing mode to use Direct Addressing as before. effectively changes how the first 96 locations of Access RAM (00h to 5Fh) are mapped. Rather than containing 6.6 PIC18 Instruction Execution and just the contents of the bottom half of Bank 0, this mode the Extended Instruction Set maps the contents from Bank 0 and a user-defined “window” that can be located anywhere in the data Enabling the extended instruction set adds eight memory space. The value of FSR2 establishes the additional commands to the existing PIC18 instruction lower boundary of the addresses mapped into the set. These instructions are executed as described in window, while the upper boundary is defined by FSR2 Section22.2 “Extended Instruction Set”. plus 95 (5Fh). Addresses in the Access RAM above 5Fh are mapped as previously described (see Section6.3.2 “Access Bank”). An example of Access Bank remapping in this addressing mode is shown in Figure6-10. FIGURE 6-10: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Example Situation: 000h ADDWF f, d, a Bank 0 FSR2H:FSR2L = 120h 05Fh 07Fh Locations in the region Bank 0 from the FSR2 Pointer 100h (120h) to the pointer plus Bank 1 120h 05Fh (17Fh) are mapped Window 17Fh 00h to the bottom of the Bank 1 Bank 1 “Window” Access RAM (000h-05Fh). 200h 5Fh Locations in Bank 0 from Bank 0 060h to 07Fh are mapped, 7Fh as usual, to the middle half Bank 2 80h of the Access Bank. through SFRs Special Function Registers Bank 14 at F80h through FFFh are FFh mapped to 80h through Access Bank FFh, as usual. F00h Bank 0 addresses below Bank 15 5Fh can still be addressed F80h by using the BSR. SFRs FFFh Data Memory DS39682E-page 70 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and In order to read and write program memory, there are erasable during normal operation over the entire VDD two operations that allow the processor to move bytes range. between the program memory space and the data RAM: A read from program memory is executed on one byte • Table Read (TBLRD) at a time. A write to program memory is executed on • Table Write (TBLWT) blocks of 64 bytes at a time. Program memory is The program memory space is 16 bits wide, while the erased in blocks of 1024 bytes at a time. A Bulk Erase data RAM space is 8 bits wide. Table reads and table operation may not be issued from user code. writes move data between these two memory spaces Writing or erasing program memory will cease through an 8-bit register (TABLAT). instruction fetches until the operation is complete. The Table read operations retrieve data from program program memory cannot be accessed during the write memory and place it into the data RAM space. or erase; therefore, code cannot execute. An internal Figure7-1 shows the operation of a table read with programming timer terminates program memory writes program memory and data RAM. and erases. Table write operations store data from the data memory A value written to program memory does not need to be space into holding registers in program memory. The a valid instruction. Executing a program memory procedure to write the contents of the holding registers location that forms an invalid instruction results in a into program memory is detailed in Section7.5 “Writing NOP. to Flash Program Memory”. Figure7-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word-aligned. FIGURE 7-1: TABLE READ OPERATION Instruction: TBLRD* Table Pointer(1) Program Memory Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. DS39682E-page 71

PIC18F45J10 FAMILY FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) Table Latch (8-bit) TBLPTRU TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section7.5 “Writing to Flash Program Memory”. 7.2 Control Registers The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is Several control registers are used in conjunction with set in hardware when the WR bit is set and cleared the TBLRD and TBLWT instructions. These include the: when the internal programming timer expires and the • EECON1 register write operation is complete. • EECON2 register Note: During normal operation, the WRERR is • TABLAT register read as ‘1’. This can indicate that a write • TBLPTR registers operation was prematurely terminated by a Reset, or a write operation was 7.2.1 EECON1 AND EECON2 REGISTERS attempted improperly. The EECON1 register (Register7-1) is the control The WR control bit initiates write operations. The bit register for memory accesses. The EECON2 register is cannot be cleared, only set, in software; it is cleared in not a physical register; it is used exclusively in the hardware at the completion of the write operation. memory write and erase sequences. Reading EECON2 will read all ‘0’s. The FREE bit, when set, will allow a program memory erase operation. When FREE is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled. DS39682E-page 72 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY REGISTER 7-1: EECON1: EEPROM CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-x R/W-0 R/S-0 U-0 — — — FREE WRERR WREN WR — bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit S = Settable bit (cannot be cleared in software) -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Performs an erase operation on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: Flash Program Error Flag bit 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program Write Enable bit 1 = Allows write cycles to Flash program 0 = Inhibits write cycles to Flash program bit 1 WR: Write Control bit 1 = Initiates a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle is complete bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. DS39682E-page 73

PIC18F45J10 FAMILY 7.2.2 TABLAT – TABLE LATCH REGISTER 7.2.4 TABLE POINTER BOUNDARIES The Table Latch (TABLAT) is an 8-bit register mapped TBLPTR is used in reads, writes and erases of the into the SFR space. The Table Latch register is used to Flash program memory. hold 8-bit data during data transfers between program When a TBLRD is executed, all 22 bits of the TBLPTR memory and data RAM. determine which byte is read from program memory into TABLAT. 7.2.3 TBLPTR – TABLE POINTER REGISTER When a TBLWT is executed, the six LSbs of the Table Pointer register (TBLPTR<5:0>) determine which of The Table Pointer (TBLPTR) register addresses a byte the 64 program memory holding registers is written to. within the program memory. The TBLPTR is comprised When the timed write to program memory begins (via of three SFR registers: Table Pointer Upper Byte, Table the WR bit), the 16 MSbs of the TBLPTR Pointer High Byte and Table Pointer Low Byte (TBLPTR<20:6>) determine which program memory (TBLPTRU:TBLPTRH:TBLPTRL). These three regis- block of 64 bytes is written to. For more detail, see ters join to form a 22-bit wide pointer. The low-order Section7.5 “Writing to Flash Program Memory”. 21bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to When an erase of program memory is executed, the the device ID, the user ID and the Configuration bits. 7MSbs of the Table Pointer register (TBLPTR<20:10>) point to the 1024-byte block that will be erased. The The Table Pointer register, TBLPTR, is used by the Least Significant bits (TBLPTR<9:0>) are ignored. TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the Figure7-3 describes the relevant boundaries of table operation. These operations are shown in TBLPTR based on Flash program memory operations. Table7-1. These operations on the TBLPTR only affect the low-order 21bits. TABLE 7-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLPTR is not modified TBLWT* TBLRD*+ TBLPTR is incremented after the read/write TBLWT*+ TBLRD*- TBLPTR is decremented after the read/write TBLWT*- TBLRD+* TBLPTR is incremented before the read/write TBLWT+* FIGURE 7-3: TABLE POINTER BOUNDARIES BASED ON OPERATION 21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 Table Erase TBLPTR<20:10> Table Write Table Write TBLPTR<20:6> TBLPTR<5:0> Table Read – TBLPTR<21:0> DS39682E-page 74 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 7.3 Reading the Flash Program TBLPTR points to a byte address in program space. Memory Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified The TBLRD instruction is used to retrieve data from automatically for the next table read operation. program memory and places it into data RAM. Table The internal program memory is typically organized by reads from program memory are performed one byte at words. The Least Significant bit of the address selects a time. between the high and low bytes of the word. Figure7-4 shows the interface between the internal program memory and the TABLAT. FIGURE 7-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register TABLAT FETCH TBLRD (IR) Read Register EXAMPLE 7-1: READING A FLASH PROGRAM MEMORY WORD MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the word MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_WORD TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_EVEN TBLRD*+ ; read into TABLAT and increment MOVF TABLAT, W ; get data MOVWF WORD_ODD © 2009 Microchip Technology Inc. DS39682E-page 75

PIC18F45J10 FAMILY 7.4 Erasing Flash Program Memory 7.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The minimum erase block is 1024 bytes. Only through the use of an external programmer, or through ICSP The sequence of events for erasing a block of internal control, can larger blocks of program memory be Bulk program memory location is: Erased. Word Erase in the Flash array is not supported. 1. Load Table Pointer register with address of the When initiating an erase sequence from the micro- block being erased. controller itself, a block of 1024 bytes of program 2. Set the WREN and FREE bits (EECON1<2,4>) memory is erased. The Most Significant 7 bits of the to enable the erase operation. TBLPTR<21:10> point to the block being erased. 3. Disable interrupts. TBLPTR<9:0> are ignored. 4. Write 55h to EECON2. The EECON1 register commands the erase operation. 5. Write 0AAh to EECON2. The WREN bit must be set to enable write operations. 6. Set the WR bit. This will begin the erase cycle. The FREE bit is set to select an erase operation. 7. The CPU will stall for duration of the erase for For protection, the write initiate sequence for EECON2 TIE (see parameter D133B). must be used. 8. Re-enable interrupts. A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. EXAMPLE 7-2: ERASING A FLASH PROGRAM MEMORY BLOCK MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_ROW BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Erase operation BCF INTCON, GIE ; disable interrupts Required MOVLW 55h Sequence MOVWF EECON2 ; write 55h MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts DS39682E-page 76 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 7.5 Writing to Flash Program Memory The EEPROM on-chip timer controls the write time. The write/erase voltages are generated by an on-chip The minimum programming block is 32 words or charge pump, rated to operate over the voltage range 64bytes. Word or byte programming is not supported. of the device. Table writes are used internally to load the holding Note: Unlike previous devices, the PIC18F45J10 registers needed to program the Flash memory. There family of devices does not reset the holding are 64 holding registers used by the table writes for registers after a write occurs. The holding programming. registers must be cleared or overwritten Since the Table Latch (TABLAT) is only a single byte, the before a programming sequence. TBLWT instruction may need to be executed 64times for In order to maintain the endurance of the each programming operation. All of the table write cells, each Flash byte should not be operations will essentially be short writes because only programmed more then twice between the holding registers are written. At the end of updating erase operations. Either a Bulk or Row the 64 holding registers, the EECON1 register must be Erase of the target row is required before written to in order to start the programming operation attempting to modify the contents a third with a long write. time. The long write is necessary for programming the inter- nal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. FIGURE 7-5: TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 8 8 TBLPTR = xxxxx0 TBLPTR = xxxxx1 TBLPTR = xxxxx2 TBLPTR = xxxx3F Holding Register Holding Register Holding Register Holding Register Program Memory 7.5.1 FLASH PROGRAM MEMORY WRITE 5. Write 55h to EECON2. SEQUENCE 6. Write 0AAh to EECON2. The sequence of events for programming an internal 7. Set the WR bit. This will begin the write cycle. program memory location should be: 8. The CPU will stall for duration of the write (about 2ms using internal timer). 1. If the section of program memory to be written to has been programmed previously, then the 9. Re-enable interrupts. memory will need to be erased before the write 10. Verify the memory (table read). occurs (see Section7.4.1 “Flash Program An example of the required code is shown in Memory Erase Sequence”). Example7-3. 2. Write the 64 bytes into the holding registers with auto-increment. Note: Before setting the WR bit, the Table Pointer address needs to be within the 3. Set the EECON1 register for the write operation: intended address range of the 64 bytes in • set WREN to enable byte writes. the holding register. 4. Disable interrupts. © 2009 Microchip Technology Inc. DS39682E-page 77

PIC18F45J10 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base MOVWF TBLPTRU ; address of the memory block MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_BLOCK BSF EECON1, WREN ; enable write to memory BSF EECON1, FREE ; enable Erase operation BCF INTCON, GIE ; disable interrupts MOVLW 55h MOVWF EECON2 ; write 55h MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start erase (CPU stall) BSF INTCON, GIE ; re-enable interrupts MOVLW D'16' MOVWF WRITE_COUNTER ; Need to write 16 blocks of 64 to write ; one erase block of 1024 RESTART_BUFFER MOVLW D'64' MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH ; point to buffer MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L FILL_BUFFER ... ; read the new data from I2C, SPI, ; PSP, USART, etc. WRITE_BUFFER MOVLW D’64' ; number of bytes in holding register MOVWF COUNTER WRITE_BYTE_TO_HREGS MOVFF POSTINC0, WREG ; get low byte of buffer data MOVWF TABLAT ; present data to table latch TBLWT+* ; write data, perform a short write ; to internal TBLWT holding register. DECFSZ COUNTER ; loop until buffers are full BRA WRITE_BYTE_TO_HREGS PROGRAM_MEMORY BSF EECON1, WREN ; enable write to memory BCF INTCON, GIE ; disable interrupts MOVLW 55h Required MOVWF EECON2 ; write 55h Sequence MOVLW 0AAh MOVWF EECON2 ; write 0AAh BSF EECON1, WR ; start program (CPU stall) BSF INTCON, GIE ; re-enable interrupts BCF EECON1, WREN ; disable write to memory DECFSZ WRITE_COUNTER ; done with one write cycle BRA RESTART_BUFFER ; if not done replacing the erase block DS39682E-page 78 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 7.5.2 WRITE VERIFY 7.5.4 PROTECTION AGAINST SPURIOUS WRITES Depending on the application, good programming practice may dictate that the value written to the To protect against spurious writes to Flash program memory should be verified against the original value. memory, the write initiate sequence must also be This should be used in applications where excessive followed. See Section21.0 “Special Features of the writes can stress bits near the specification limit. CPU” for more detail. 7.5.3 UNEXPECTED TERMINATION OF 7.6 Flash Program Operation During WRITE OPERATION Code Protection If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory See Section21.6 “Program Verification and Code Protection” for details on code protection of Flash location just programmed should be verified and repro- grammed if needed. If the write operation is interrupted program memory. by a MCLR Reset or a WDT Time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed. TABLE 7-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 47 TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 47 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 47 TABLAT Program Memory Table Latch 47 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47 EECON2 EEPROM Control Register 2 (not a physical register) 49 EECON1 — — — FREE WRERR WREN WR — 49 IPR2 OSCFIP CMIP — — BCL1IP — — CCP2IP 49 PIR2 OSCFIF CMIF — — BCL1IF — — CCP2IF 49 PIE2 OSCFIE CMIE — — BCL1IE — — CCP2IE 49 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2009 Microchip Technology Inc. DS39682E-page 79

PIC18F45J10 FAMILY NOTES: DS39682E-page 80 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 8.0 8 x 8 HARDWARE MULTIPLIER EXAMPLE 8-1: 8 x 8 UNSIGNED MULTIPLY ROUTINE 8.1 Introduction MOVF ARG1, W ; MULWF ARG2 ; ARG1 * ARG2 -> All PIC18 devices include an 8 x 8 hardware multiplier ; PRODH:PRODL as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY register. ROUTINE Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the MOVF ARG1, W advantages of higher computational throughput and MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL reduced code size for multiplication algorithms and BTFSC ARG2, SB ; Test Sign Bit allows the PIC18 devices to be used in many applica- SUBWF PRODH, F ; PRODH = PRODH tions previously reserved for digital signal processors. ; - ARG1 A comparison of various hardware and software MOVF ARG2, W multiply operations, along with the savings in memory BTFSC ARG1, SB ; Test Sign Bit and execution time, is shown in Table8-1. SUBWF PRODH, F ; PRODH = PRODH ; - ARG2 8.2 Operation Example8-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example8-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 8-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Program Time Cycles Routine Multiply Method Memory (Max) (Words) @ 40 MHz @ 10 MHz @ 4 MHz Without hardware multiply 13 69 6.9 μs 27.6 μs 69 μs 8 x 8 unsigned Hardware multiply 1 1 100 ns 400 ns 1 μs Without hardware multiply 33 91 9.1 μs 36.4 μs 91 μs 8 x 8 signed Hardware multiply 6 6 600 ns 2.4 μs 6 μs Without hardware multiply 21 242 24.2 μs 96.8 μs 242 μs 16 x 16 unsigned Hardware multiply 28 28 2.8 μs 11.2 μs 28 μs Without hardware multiply 52 254 25.4 μs 102.6 μs 254 μs 16 x 16 signed Hardware multiply 35 40 4.0 μs 16.0 μs 40 μs © 2009 Microchip Technology Inc. DS39682E-page 81

PIC18F45J10 FAMILY Example8-3 shows the sequence to do a 16 x 16 EQUATION 8-2: 16 x 16 SIGNED unsigned multiplication. Equation8-1 shows the MULTIPLICATION algorithm that is used. The 32-bit result is stored in four ALGORITHM registers (RES3:RES0). RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L = (ARG1H • ARG2H • 216) + EQUATION 8-1: 16 x 16 UNSIGNED (ARG1H • ARG2L • 28) + MULTIPLICATION (ARG1L • ARG2H • 28) + ALGORITHM (ARG1L • ARG2L) + (-1 • ARG2H<7> • ARG1H:ARG1L • 216) + RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L (-1 • ARG1H<7> • ARG2H:ARG2L • 216) = (ARG1H • ARG2H • 216) + (ARG1H • ARG2L • 28) + (ARG1L • ARG2H • 28) + EXAMPLE 8-4: 16 x 16 SIGNED (ARG1L • ARG2L) MULTIPLY ROUTINE MOVF ARG1L, W EXAMPLE 8-3: 16 x 16 UNSIGNED MULWF ARG2L ; ARG1L * ARG2L -> MULTIPLY ROUTINE ; PRODH:PRODL MOVFF PRODH, RES1 ; MOVF ARG1L, W MOVFF PRODL, RES0 ; MULWF ARG2L ; ARG1L * ARG2L-> ; ; PRODH:PRODL MOVF ARG1H, W MOVFF PRODH, RES1 ; MULWF ARG2H ; ARG1H * ARG2H -> MOVFF PRODL, RES0 ; ; PRODH:PRODL ; MOVFF PRODH, RES3 ; MOVF ARG1H, W MOVFF PRODL, RES2 ; MULWF ARG2H ; ARG1H * ARG2H-> ; ; PRODH:PRODL MOVF ARG1L, W MOVFF PRODH, RES3 ; MULWF ARG2H ; ARG1L * ARG2H -> MOVFF PRODL, RES2 ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1L, W ADDWF RES1, F ; Add cross MULWF ARG2H ; ARG1L * ARG2H-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; MOVF ARG1H, W ; CLRF WREG ; MULWF ARG2L ; ARG1H * ARG2L -> ADDWFC RES3, F ; ; PRODH:PRODL ; MOVF PRODL, W ; MOVF ARG1H, W ; ADDWF RES1, F ; Add cross MULWF ARG2L ; ARG1H * ARG2L-> MOVF PRODH, W ; products ; PRODH:PRODL ADDWFC RES2, F ; MOVF PRODL, W ; CLRF WREG ; ADDWF RES1, F ; Add cross ADDWFC RES3, F ; MOVF PRODH, W ; products ; ADDWFC RES2, F ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? CLRF WREG ; BRA SIGN_ARG1 ; no, check ARG1 ADDWFC RES3, F ; MOVF ARG1L, W ; SUBWF RES2 ; Example8-4 shows the sequence to do a 16 x 16 MOVF ARG1H, W ; signed multiply. Equation8-2 shows the algorithm SUBWFB RES3 used. The 32-bit result is stored in four registers ; (RES3:RES0). To account for the sign bits of the SIGN_ARG1 arguments, the MSb for each argument pair is tested BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? and the appropriate subtractions are done. BRA CONT_CODE ; no, done MOVF ARG2L, W ; SUBWF RES2 ; MOVF ARG2H, W ; SUBWFB RES3 ; CONT_CODE : DS39682E-page 82 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 9.0 INTERRUPTS When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are Members of the PIC18F45J10 family of devices have compatible with PIC® mid-range devices. In multiple interrupt sources and an interrupt priority Compatibility mode, the interrupt priority bits for each feature that allows most interrupt sources to be source have no effect. INTCON<6> is the PEIE bit assigned a high-priority level or a low-priority level. The which enables/disables all peripheral interrupt sources. high-priority interrupt vector is at 0008h and the INTCON<7> is the GIE bit which enables/disables all low-priority interrupt vector is at 0018h. High-priority interrupt sources. All interrupts branch to address interrupt events will interrupt any low-priority interrupts 0008h in Compatibility mode. that may be in progress. When an interrupt is responded to, the global interrupt There are thirteen registers which are used to control enable bit is cleared to disable further interrupts. If the interrupt operation. These registers are: IPEN bit is cleared, this is the GIE bit. If interrupt priority • RCON levels are used, this will be either the GIEH or GIEL bit. High-priority interrupt sources can interrupt a • INTCON low-priority interrupt. Low-priority interrupts are not • INTCON2 processed while high-priority interrupts are in progress. • INTCON3 The return address is pushed onto the stack and the • PIR1, PIR2, PIR3 PC is loaded with the interrupt vector address (0008h • PIE1, PIE2, PIE3 or 0018h). Once in the Interrupt Service Routine, the • IPR1, IPR2, IPR3 source(s) of the interrupt can be determined by polling It is recommended that the Microchip header files the interrupt flag bits. The interrupt flag bits must be supplied with MPLAB® IDE be used for the symbolic bit cleared in software before re-enabling interrupts to names in these registers. This allows the avoid recursive interrupts. assembler/compiler to automatically take care of the The “return from interrupt” instruction, RETFIE, exits placement of these bits within the specified register. the interrupt routine and sets the GIE bit (GIEH or GIEL In general, interrupt sources have three bits to control if priority levels are used) which re-enables interrupts. their operation. They are: For external interrupt events, such as the INTx pins or • Flag bit to indicate that an interrupt event the PORTB input change interrupt, the interrupt latency occurred will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. • Enable bit that allows program execution to Individual interrupt flag bits are set regardless of the branch to the interrupt vector address when the status of their corresponding enable bit or the GIE bit. flag bit is set • Priority bit to select high priority or low priority Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while The interrupt priority feature is enabled by setting the any interrupt is enabled. Doing so may IPEN bit (RCON<7>). When interrupt priority is cause erratic microcontroller behavior. enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 0008h or 0018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits. © 2009 Microchip Technology Inc. DS39682E-page 83

PIC18F45J10 FAMILY FIGURE 9-1: PIC18F24J10/25J10/44J10/45J10 INTERRUPT LOGIC TMR0IF Wake-up if in TMR0IE Idle or Sleep modes TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE Interrupt to CPU IINNTT12IIPF Vector to Location INT2IE 0008h PIR1<7:0> INT2IP PIE1<7:0> IPR1<7:0> GIE/GIEH PIR2<7:6, 3, 0> PIE2<7:6, 3, 0> IPR2<7:6, 3, 0> IPEN PIR3<7:6> IPEN PIE3<7:6> IPR3<7:6> PEIE/GIEL IPEN High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 3, 0> PIE2<7:6, 3, 0> IPR2<7:6, 3, 0> Interrupt to CPU PIR3<7:6> TTMMRR00IIEF IPEN V00e1c8tohr to Location PIE3<7:6> TMR0IP IPR3<7:6> RBIF RBIE RBIP GIE/GIEH PEIE/GIEL INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP DS39682E-page 84 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 9.1 INTCON Registers Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of The INTCON registers are readable and writable its corresponding enable bit or the global registers which contain various enable, priority and flag interrupt enable bit. User software should bits. ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. REGISTER 9-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high-priority interrupts 0 = Disables all interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low-priority peripheral interrupts 0 = Disables all low-priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit(1) 1 = At least one of the RB<7:4> pins changed state (must be cleared in software) 0 = None of the RB<7:4> pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2009 Microchip Technology Inc. DS39682E-page 85

PIC18F45J10 FAMILY REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 Unimplemented: Read as ‘0’ bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 Unimplemented: Read as ‘0’ bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39682E-page 86 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY REGISTER 9-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. DS39682E-page 87

PIC18F45J10 FAMILY 9.2 PIR Registers Note1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of The PIR registers contain the individual flag bits for the its corresponding enable bit or the Global peripheral interrupts. Due to the number of peripheral Interrupt Enable bit, GIE (INTCON<7>). interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1) 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RCIF: EUSART Receive Interrupt Flag bit 1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The EUSART receive buffer is empty bit 4 TXIF: EUSART Transmit Interrupt Flag bit 1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The EUSART transmit buffer is full bit 3 SSP1IF: Master Synchronous Serial Port 1 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: ECCP1/CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: This bit is not implemented on 28-pin devices and should be read as ‘0’. DS39682E-page 88 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 OSCFIF CMIF — — BCLIF — — CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = Device clock operating bit 6 CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed bit 5-4 Unimplemented: Read as ‘0’ bit 3 BCLIF: Bus Collision Interrupt Flag bit (MSSP1 module) 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred bit 2-1 Unimplemented: Read as ‘0’ bit 0 CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 SSP2IF BCL2IF — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IF: Master Synchronous Serial Port 2 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 6 BCL2IF: Bus Collision Interrupt Flag bit (MSSP2 module) 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred bit 5-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. DS39682E-page 89

PIC18F45J10 FAMILY 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 9-7: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1) 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RCIE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt bit 4 TXIE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt bit 3 SSP1IE: Master Synchronous Serial Port 1 Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: ECCP1/CCP1 Interrupt Enable bit 1 = Enables the ECCP1/CCP1 interrupt 0 = Disables the ECCP1/CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: This bit is not implemented on 28-pin devices and should be read as ‘0’. DS39682E-page 90 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 OSCFIE CMIE — — BCL1IE — — CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5-4 Unimplemented: Read as ‘0’ bit 3 BCL1IE: Bus Collision Interrupt Enable bit (MSSP1 module) 1 = Enabled 0 = Disabled bit 2-1 Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled REGISTER 9-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 SSP2IE BCL2IE — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module) 1 = Enabled 0 = Disabled bit 5-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. DS39682E-page 91

PIC18F45J10 FAMILY 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 9-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RCIP: EUSART Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXIP: EUSART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSP1IP: Master Synchronous Serial Port 1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: ECCP1/CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: This bit is not implemented on 28-pin devices and should be read as ‘0’. DS39682E-page 92 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 U-0 U-0 R/W-1 U-0 U-0 R/W-0 OSCFIP CMIP — — BCL1IP — — CCP2IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority bit 5-4 Unimplemented: Read as ‘0’ bit 3 BCL1IP: Bus Collision Interrupt Priority bit (MSSP1 module) 1 = High priority 0 = Low priority bit 2-1 Unimplemented: Read as ‘0’ bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0 SSP2IP BCL2IP — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module) 1 = High priority 0 = Low priority bit 5-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. DS39682E-page 93

PIC18F45J10 FAMILY 9.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN). REGISTER 9-13: RCON: RESET CONTROL REGISTER R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — CM RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 Unimplemented: Read as ‘0’ bit 5 CM: Configuration Mismatch Flag bit For details of bit operation, see Register5-1. bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register5-1. bit 3 TO: Watchdog Timer Time-out Flag bit For details of bit operation, see Register5-1. bit 2 PD: Power-Down Detection Flag bit For details of bit operation, see Register5-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register5-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register5-1. DS39682E-page 94 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 9.6 INTx Pin Interrupts 9.7 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1 and In 8-bit mode (which is the default), an overflow in the RB2/INT2 pins are edge-triggered. If the corresponding TMR0 register (FFh→00h) will set flag bit, TMR0IF. In INTEDGx bit in the INTCON2 register is set (= 1), the 16-bit mode, an overflow in the TMR0H:TMR0L register interrupt is triggered by a rising edge; if the bit is clear, pair (FFFFh→0000h) will set TMR0IF. The interrupt the trigger is on the falling edge. When a valid edge can be enabled/disabled by setting/clearing enable bit, appears on the RBx/INTx pin, the corresponding flag TMR0IE (INTCON<5>). Interrupt priority for Timer0 is bit, INTxIF, is set. This interrupt can be disabled by determined by the value contained in the interrupt prior- clearing the corresponding enable bit, INTxIE. Flag bit, ity bit, TMR0IP (INTCON2<2>). See Section11.0 INTxIF, must be cleared in software in the Interrupt “Timer0 Module” for further details on the Timer0 Service Routine before re-enabling the interrupt. module. All external interrupts (INT0, INT1 and INT2) can 9.8 PORTB Interrupt-on-Change wake-up the processor from the power-managed modes if bit INTxIE was set prior to going into the An input change on PORTB<7:4> sets flag bit, RBIF power-managed modes. If the Global Interrupt Enable (INTCON<0>). The interrupt can be enabled/disabled bit, GIE, is set, the processor will branch to the interrupt by setting/clearing enable bit, RBIE (INTCON<3>). vector following wake-up. Interrupt priority for PORTB interrupt-on-change is Interrupt priority for INT1 and INT2 is determined by the determined by the value contained in the interrupt value contained in the interrupt priority bits, INT1IP priority bit, RBIP (INTCON2<0>). (INTCON3<6>) and INT2IP (INTCON3<7>). There is no priority bit associated with INT0. It is always a 9.9 Context Saving During Interrupts high-priority interrupt source. During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the Fast Return Stack. If a fast return from interrupt is not used (see Section6.3 “Data Memory Organization”), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user’s application, other registers may also need to be saved. Example9-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP ; W_TEMP is in virtual bank MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR ; Restore BSR MOVF W_TEMP, W ; Restore WREG MOVFF STATUS_TEMP, STATUS ; Restore STATUS © 2009 Microchip Technology Inc. DS39682E-page 95

PIC18F45J10 FAMILY NOTES: DS39682E-page 96 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 10.0 I/O PORTS 10.1 I/O Port Pin Capabilities Depending on the device selected and features When developing an application, the capabilities of the enabled, there are up to five ports available. Some pins port pins must be considered. Outputs on some pins of the I/O ports are multiplexed with an alternate have higher output drive strength than others. Similarly, function from the peripheral features on the device. In some pins can tolerate higher than VDD input levels. general, when a peripheral is enabled, that pin may not 10.1.1 PIN OUTPUT DRIVE be used as a general purpose I/O pin. Each port has three registers for its operation. These The output pin drive strengths vary for groups of pins registers are: intended to meet the needs for a variety of applications. PORTB and PORTC are designed to drive higher • TRIS register (Data Direction register) loads, such as LEDs. All other ports are designed for • PORT register (reads the levels on the pins of the small loads, typically indication only. Table10-1 sum- device) marizes the output capabilities. Refer to Section24.0 • LAT register (Data Latch register) “Electrical Characteristics” for more details. The Data Latch (LAT register) is useful for read-modify- write operations on the value that the I/O pins are TABLE 10-1: OUTPUT DRIVE LEVELS driving. Port Drive Description A simplified model of a generic I/O port, without the PORTA interfaces to other peripherals, is shown in Figure10-1. PORTD Minimum Intended for indication. FIGURE 10-1: GENERIC I/O PORT PORTE OPERATION PORTB Suitable for direct LED drive High PORTC levels. RD LAT 10.1.2 INPUT PINS AND VOLTAGE Data CONSIDERATIONS Bus D Q The voltage tolerance of pins used as device inputs is WR LAT I/O pin or PORT dependent on the pin’s input function. Pins that are used CK as digital only inputs are able to handle DC voltages up Data Latch to 5.5V; a level typical for digital logic circuits. In contrast, pins that also have analog input functions of any kind D Q can only tolerate voltages up to VDD. Voltage excursions WR TRIS beyond VDD on these pins should be avoided. Table10- CK 2 summarizes the input capabilities. Refer to TRIS Latch Input Section24.0 “Electrical Characteristics” for more Buffer details. RD TRIS TABLE 10-2: INPUT VOLTAGE LEVELS Q D Tolerated Port or Pin Description Input ENEN PORTA<5:0> RD PORT PORTB<5:0> Only VDD input levels VDD PORTC<1:0> tolerated. PORTE<2:0> PORTB<7:6> Tolerates input levels PORTC<7:2> 5.5V above VDD, useful for PORTD<7:0> most standard logic. © 2009 Microchip Technology Inc. DS39682E-page 97

PIC18F45J10 FAMILY 10.1.3 INTERFACING TO A 5V SYSTEM 10.2 PORTA, TRISA and LATA Registers Though the VDDMAX of the PIC18F45J10 family is 3.6V, PORTA is a 5-bit wide, bidirectional port. The corre- these devices are still capable of interfacing with 5V sponding Data Direction register is TRISA. Setting a systems, even if the VIH of the target system is above TRISA bit (= 1) will make the corresponding PORTA pin 3.6V. This is accomplished by adding a pull-up resistor an input (i.e., put the corresponding output driver in a to the port pin (Figure10-2), clearing the LAT bit for that high-impedance mode). Clearing a TRISA bit (= 0) will pin and manipulating the corresponding TRIS bit make the corresponding PORTA pin an output (i.e., put (Figure10-1) to either allow the line to be pulled high or the contents of the output latch on the selected pin). to drive the pin low. Only port pins that are tolerant of Reading the PORTA register reads the status of the voltages up to 5.5V can be used for this type of pins, whereas writing to it, will write to the port latch. interface (refer to Section10.1.2 “Input Pins and Voltage Considerations”). The Data Latch (LATA) register is also memory mapped. Read-modify-write operations on the LATA register read FIGURE 10-2: +5V SYSTEM HARDWARE and write the latched output value for PORTA. INTERFACE The other PORTA pins are multiplexed with analog inputs, the analog VREF+ and VREF- inputs and the com- PIC18F45J10 +5V +5V Device parator voltage reference output. The operation of pins RA<3:0> and RA5 as A/D converter inputs is selected by clearing or setting the control bits in the ADCON1 register (A/D Control Register 1). Pins RA0 and RA3 may also be used as comparator RD7 inputs and RA5 may be used as the C2 comparator output by setting the appropriate bits in the CMCON register. To use RA<3:0> as digital inputs, it is also necessary to turn off the comparators. Note: On a Power-on Reset, RA5 and RA<3:0> are configured as analog inputs and read EXAMPLE 10-1: COMMUNICATING WITH as ‘0’. THE +5V SYSTEM All PORTA pins have TTL input levels and full CMOS BCF LATD, 7 ; set up LAT register so output drivers. ; changing TRIS bit will The TRISA register controls the direction of the PORTA ; drive line low pins, even when they are being used as analog inputs. BCF TRISD, 7 ; send a 0 to the 5V system BCF TRISD, 7 ; send a 1 to the 5V system The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. EXAMPLE 10-2: INITIALIZING PORTA CLRF PORTA ; Initialize PORTA by ; clearing output ; data latches CLRF LATA ; Alternate method ; to clear output ; data latches MOVLW 07h ; Configure A/D MOVWF ADCON1 ; for digital inputs MOVWF 07h ; Configure comparators MOVWF CMCON ; for digital input MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs DS39682E-page 98 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY TABLE 10-3: PORTA I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RA0/AN0 RA0 0 O DIG LATA<0> data output; not affected by analog input. 1 I TTL PORTA<0> data input; disabled when analog input enabled. AN0 1 I ANA A/D Input Channel 0 and Comparator C1- input. Default input configuration on POR; does not affect digital output. RA1/AN1 RA1 0 O DIG LATA<1> data output; not affected by analog input. 1 I TTL PORTA<1> data input; disabled when analog input enabled. AN1 1 I ANA A/D Input Channel 1 and Comparator C2- input. Default input configuration on POR; does not affect digital output. RA2/AN2/ RA2 0 O DIG LATA<2> data output; not affected by analog input. Disabled when VREF-/CVREF CVREF output enabled. 1 I TTL PORTA<2> data input. Disabled when analog functions enabled; disabled when CVREF output enabled. AN2 1 I ANA A/D Input Channel 2 and Comparator C2+ input. Default input configuration on POR; not affected by analog output. VREF- 1 I ANA A/D and comparator voltage reference low input. CVREF x O ANA Comparator voltage reference output. Enabling this feature disables digital I/O. RA3/AN3/VREF+ RA3 0 O DIG LATA<3> data output; not affected by analog input. 1 I TTL PORTA<3> data input; disabled when analog input enabled. AN3 1 I ANA A/D Input Channel 3 and Comparator C1+ input. Default input configuration on POR. VREF+ 1 I ANA A/D and comparator voltage reference high input. RA5/AN4/SS1/ RA5 0 O DIG LATA<5> data output; not affected by analog input. C2OUT 1 I TTL PORTA<5> data input; disabled when analog input enabled. AN4 1 I ANA A/D Input Channel 4. Default configuration on POR. SS1 1 I TTL Slave select input for MSSP1 (MSSP1 module). C2OUT 0 O DIG Comparator 2 output; takes priority over port data. OSC2/CLKO OSC2 x O ANA Main oscillator feedback output connection (HS mode). CLKO x O DIG System cycle clock output (FOSC/4) in RC and EC Oscillator modes. OSC1/CLKI OSC1 x I ANA Main oscillator input connection. CLKI x I ANA Main clock input connection. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2009 Microchip Technology Inc. DS39682E-page 99

PIC18F45J10 FAMILY TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTA — — RA5 — RA3 RA2 RA1 RA0 50 LATA — — PORTA Data Latch Register (Read and Write to Data Latch) 50 TRISA — — TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 50 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 48 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 49 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 49 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. DS39682E-page 100 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 10.3 PORTB, TRISB and LATB Four of the PORTB pins (RB<7:4>) have an interrupt- Registers on-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB<7:4> pin PORTB is an 8-bit wide, bidirectional port. The corre- configured as an output is excluded from the interrupt- sponding Data Direction register is TRISB. Setting a on-change comparison). The input pins (of RB<7:4>) TRISB bit (= 1) will make the corresponding PORTB are compared with the old value latched on the last pin an input (i.e., put the corresponding output driver in read of PORTB. The “mismatch” outputs of RB<7:4> a high-impedance mode). Clearing a TRISB bit (= 0) are ORed together to generate the RB Port Change will make the corresponding PORTB pin an output (i.e., Interrupt with Flag bit, RBIF (INTCON<0>). put the contents of the output latch on the selected pin). This interrupt can wake the device from Sleep mode or The Data Latch register (LATB) is also memory any of the Idle modes. The user, in the Interrupt Service mapped. Read-modify-write operations on the LATB Routine, can clear the interrupt in the following manner: register read and write the latched output value for a) Any read or write of PORTB (except with the PORTB. MOVFF (ANY), PORTB instruction). b) Clear flag bit, RBIF. EXAMPLE 10-3: INITIALIZING PORTB A mismatch condition will continue to set flag bit, RBIF. CLRF PORTB ; Initialize PORTB by Reading PORTB will end the mismatch condition and ; clearing output allow flag bit, RBIF, to be cleared. ; data latches CLRF LATB ; Alternate method The interrupt-on-change feature is recommended for ; to clear output wake-up on key depression operation and operations ; data latches where PORTB is only used for the interrupt-on-change MOVLW 0Fh ; Set RB<4:0> as feature. Polling of PORTB is not recommended while MOVWF ADCON1 ; digital I/O pins using the interrupt-on-change feature. MOVLW 0CFh ; Value used to ; initialize data RB3 can be configured by the Configuration bit, ; direction CCP2MX, as the alternate peripheral pin for the CCP2 MOVWF TRISB ; Set RB<3:0> as inputs module (CCP2MX = 0). ; RB<5:4> as outputs ; RB<7:6> as inputs The RB5 pin is multiplexed with the Timer0 module clock input and one of the comparator outputs to become the RB5/KBI1/T0CKI/C1OUT pin. Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit, RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Note: On a Power-on Reset, RB<4:0> are configured as analog inputs by default and read as ‘0’; RB<7:5> are configured as digital inputs. © 2009 Microchip Technology Inc. DS39682E-page 101

PIC18F45J10 FAMILY TABLE 10-5: PORTB I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RB0/INT0/FLT0/ RB0 0 O DIG LATB<0> data output; not affected by analog input. AN12 1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) INT0 1 I ST External Interrupt 0 input. FLT0 1 I ST PWM Fault input (ECCP1/CCP1 module); enabled in software. AN12 1 I ANA A/D Input Channel 12.(1) RB1/INT1/AN10 RB1 0 O DIG LATB<1> data output; not affected by analog input. 1 I TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) INT1 1 I ST External Interrupt 1 input. AN10 1 I ANA A/D Input Channel 10.(1) RB2/INT2/AN8 RB2 0 O DIG LATB<2> data output; not affected by analog input. 1 I TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) INT2 1 I ST External Interrupt 2 input. AN8 1 I ANA A/D Input Channel 8.(1) RB3/AN9/CCP2 RB3 0 O DIG LATB<3> data output; not affected by analog input. 1 I TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) AN9 1 I ANA A/D Input Channel 9.(1) CCP2(2) 0 O DIG CCP2 compare and PWM output. 1 I ST CCP2 capture input RB4/KBI0/AN11 RB4 0 O DIG LATB<4> data output; not affected by analog input. 1 I TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) KBI0 1 I TTL Interrupt-on-change pin. AN11 1 I ANA A/D Input Channel 11.(1) RB5/KBI1/T0CKI/ RB5 0 O DIG LATB<5> data output. C1OUT 1 I TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared. KBI1 1 I TTL Interrupt-on-change pin. T0CKI 1 I ST Timer0 clock input. C1OUT 0 O DIG Comparator 1 output; takes priority over port data. RB6/KBI2/PGC RB6 0 O DIG LATB<6> data output. 1 I TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared. KBI2 1 I TTL Interrupt-on-change pin. PGC x I ST Serial execution (ICSP™) clock input for ICSP and ICD operation.(3) RB7/KBI3/PGD RB7 0 O DIG LATB<7> data output. 1 I TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared. KBI3 1 I TTL Interrupt-on-change pin. PGD x O DIG Serial execution data output for ICSP and ICD operation.(3) x I ST Serial execution data input for ICSP and ICD operation.(3) Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Pins are configured as analog inputs by default. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1. 3: All other pin functions are disabled when ICSP™ or ICD are enabled. DS39682E-page 102 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 50 LATB PORTB Data Latch Register (Read and Write to Data Latch) 50 TRISB PORTB Data Direction Control Register 50 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 47 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 47 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 48 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. © 2009 Microchip Technology Inc. DS39682E-page 103

PIC18F45J10 FAMILY 10.4 PORTC, TRISC and LATC Note: On a Power-on Reset, these pins are Registers configured as digital inputs. PORTC is an 8-bit wide, bidirectional port. The corre- The contents of the TRISC register are affected by sponding Data Direction register is TRISC. Setting a peripheral overrides. Reading TRISC always returns TRISC bit (= 1) will make the corresponding PORTC the current contents, even though a peripheral device pin an input (i.e., put the corresponding output driver in may be overriding one or more of the pins. a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., EXAMPLE 10-4: INITIALIZING PORTC put the contents of the output latch on the selected pin). CLRF PORTC ; Initialize PORTC by The Data Latch register (LATC) is also memory ; clearing output mapped. Read-modify-write operations on the LATC ; data latches register read and write the latched output value for CLRF LATC ; Alternate method PORTC. ; to clear output ; data latches PORTC is multiplexed with several peripheral functions MOVLW 0CFh ; Value used to (Table10-7). The pins have Schmitt Trigger input ; initialize data buffers. RC1 is normally configured by Configuration ; direction bit, CCP2MX, as the default peripheral pin of the CCP2 MOVWF TRISC ; Set RC<3:0> as inputs module (default/erased state, CCP2MX = 1). ; RC<5:4> as outputs ; RC<7:6> as inputs When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for additional information. DS39682E-page 104 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY TABLE 10-7: PORTC I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RC0/T1OSO/ RC0 0 O DIG LATC<0> data output. T1CKI 1 I ST PORTC<0> data input. T1OSO x O ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled. Disables digital I/O. T1CKI 1 I ST Timer1 counter input. RC1/T1OSI/CCP2 RC1 0 O DIG LATC<1> data output. 1 I ST PORTC<1> data input. T1OSI x I ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled. Disables digital I/O. CCP2(1) 0 O DIG CCP2 compare and PWM output; takes priority over port data. 1 I ST CCP2 capture input. RC2/CCP1/P1A RC2 0 O DIG LATC<2> data output. 1 I ST PORTC<2> data input. CCP1 0 O DIG ECCP1/CCP1 compare or PWM output; takes priority over port data. 1 I ST ECCP1/CCP1 capture input. P1A(2) 0 O DIG ECCP1 Enhanced PWM output, channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RC3/SCK1/SCL1 RC3 0 O DIG LATC<3> data output. 1 I ST PORTC<3> data input. SCK1 0 O DIG SPI clock output (MSSP1 module); takes priority over port data. 1 I ST SPI clock input (MSSP1 module). SCL1 0 O DIG I2C™ clock output (MSSP1 module); takes priority over port data. 1 I I2C/SMB I2C clock input (MSSP1 module); input type depends on module setting. RC4/SDI1/SDA1 RC4 0 O DIG LATC<4> data output. 1 I ST PORTC<4> data input. SDI1 1 I ST SPI data input (MSSP1 module). SDA1 1 O DIG I2C data output (MSSP1 module); takes priority over port data. 1 I I2C/SMB I2C data input (MSSP1 module); input type depends on module setting. RC5/SDO1 RC5 0 O DIG LATC<5> data output. 1 I ST PORTC<5> data input. SDO1 0 O DIG SPI data output (MSSP1 module); takes priority over port data. RC6/TX/CK RC6 0 O DIG LATC<6> data output. 1 I ST PORTC<6> data input. TX 1 O DIG Asynchronous serial transmit data output (EUSART module); takes priority over port data. User must configure as output. CK 1 O DIG Synchronous serial clock output (EUSART module); takes priority over port data. 1 I ST Synchronous serial clock input (EUSART module). RC7/RX/DT RC7 0 O DIG LATC<7> data output. 1 I ST PORTC<7> data input. RX 1 I ST Asynchronous serial receive data input (EUSART module). DT 1 O DIG Synchronous serial data output (EUSART module); takes priority over port data. 1 I ST Synchronous serial data input (EUSART module). User must configure as an input. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; I2C™/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. Alternate assignment is RB3. 2: Enhanced PWM output is available only on PIC18F44J10/45J10 devices. © 2009 Microchip Technology Inc. DS39682E-page 105

PIC18F45J10 FAMILY TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 50 LATC PORTC Data Latch Register (Read and Write to Data Latch) 50 TRISC PORTC Data Direction Control Register 50 DS39682E-page 106 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 10.5 PORTD, TRISD and LATD PORTD can also be configured as an 8-bit wide micro- Registers processor port (Parallel Slave Port) by setting control bit, PSPMODE (TRISE<4>). In this mode, the input Note: PORTD is only available in 40/44-pin buffers are TTL. See Section10.7 “Parallel Slave devices. Port” for additional information on the Parallel Slave Port (PSP). PORTD is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISD. Setting a Note: When the Enhanced PWM mode is used TRISD bit (= 1) will make the corresponding PORTD with either dual or quad outputs, the PSP pin an input (i.e., put the corresponding output driver in functions of PORTD are automatically a high-impedance mode). Clearing a TRISD bit (= 0) disabled. will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). EXAMPLE 10-5: INITIALIZING PORTD The Data Latch register (LATD) is also memory CLRF PORTD ; Initialize PORTD by mapped. Read-modify-write operations on the LATD ; clearing output register read and write the latched output value for ; data latches PORTD. CLRF LATD ; Alternate method ; to clear output All pins on PORTD are implemented with Schmitt Trigger ; data latches input buffers. Each pin is individually configurable as an MOVLW 0CFh ; Value used to input or output. ; initialize data Three of the PORTD pins are multiplexed with outputs ; direction MOVWF TRISD ; Set RD<3:0> as inputs P1B, P1C and P1D of the Enhanced CCP module. The ; RD<5:4> as outputs operation of these additional PWM output pins is ; RD<7:6> as inputs covered in greater detail in Section15.0 “Enhanced Capture/Compare/PWM (ECCP) Module”. Note: On a Power-on Reset, these pins are configured as digital inputs. © 2009 Microchip Technology Inc. DS39682E-page 107

PIC18F45J10 FAMILY TABLE 10-9: PORTD I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RD0/PSP0/SCK2/ RD0 0 O DIG LATD<0> data output. SCL2 1 I ST PORTD<0> data input. PSP0 x O DIG PSP read data output (LATD<0>); takes priority over port data. x I TTL PSP write data input. SCK2 0 O DIG SPI clock output (MSSP2 module); takes priority over port data. 1 I ST SPI clock input (MSSP2 module). SCL2 0 O DIG I2C™ clock output (MSSP2 module); takes priority over port data. 1 I I2C/SMB I2C clock input (MSSP2 module); input type depends on module setting. RD1/PSP1/SDI2/ RD1 0 O DIG LATD<1> data output. SDA2 1 I ST PORTD<1> data input. PSP1 x O DIG PSP read data output (LATD<1>); takes priority over port data. x I TTL PSP write data input. SDI2 1 I ST SPI data input (MSSP2 module). SDA2 1 O DIG I2C data output (MSSP2 module); takes priority over port data. 1 I I2C/SMB I2C data input (MSSP2 module); input type depends on module setting. RD2/PSP2/SDO2 RD2 0 O DIG LATD<2> data output. 1 I ST PORTD<2> data input. PSP2 x O DIG PSP read data output (LATD<2>); takes priority over port data. x I TTL PSP write data input. SDO2 0 O DIG SPI data output (MSSP2 module); takes priority over port data. RD3/PSP3/SS2 RD3 0 O DIG LATD<3> data output. 1 I ST PORTD<3> data input. PSP3 x O DIG PSP read data output (LATD<3>); takes priority over port data. x I TTL PSP write data input. SS2 1 I TTL Slave select input for MSSP2 (MSSP2 module). RD4/PSP4 RD4 0 O DIG LATD<4> data output. 1 I ST PORTD<4> data input. PSP4 x O DIG PSP read data output (LATD<4>); takes priority over port data. x I TTL PSP write data input. RD5/PSP5/P1B RD5 0 O DIG LATD<5> data output. 1 I ST PORTD<5> data input. PSP5 x O DIG PSP read data output (LATD<5>); takes priority over port data. x I TTL PSP write data input. P1B 0 O DIG ECCP1 Enhanced PWM output, Channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RD6/PSP6/P1C RD6 0 O DIG LATD<6> data output. 1 I ST PORTD<6> data input. PSP6 x O DIG PSP read data output (LATD<6>); takes priority over port data. x I TTL PSP write data input. P1C 0 O DIG ECCP1 Enhanced PWM output, Channel C; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RD7/PSP7/P1D RD7 0 O DIG LATD<7> data output. 1 I ST PORTD<7> data input. PSP7 x O DIG PSP read data output (LATD<7>); takes priority over port data. x I TTL PSP write data input. P1D 0 O DIG ECCP1 Enhanced PWM output, Channel D; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I2C™/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). DS39682E-page 108 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 50 LATD(1) PORTD Data Latch Register (Read and Write to Data Latch) 50 TRISD(1) PORTD Data Direction Control Register 50 TRISE(1) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 50 CCP1CON P1M1(1) P1M0(1) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 49 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. Note 1: These registers and/or bits are not available in 28-pin devices. © 2009 Microchip Technology Inc. DS39682E-page 109

PIC18F45J10 FAMILY 10.6 PORTE, TRISE and LATE The upper four bits of the TRISE register also control Registers the operation of the Parallel Slave Port. Their operation is explained in Register10-1. Note: PORTE is only available in 40/44-pin The Data Latch register (LATE) is also memory devices. mapped. Read-modify-write operations on the LATE register read and write the latched output value for Depending on the particular PIC18F45J10 family PORTE. device selected, PORTE is implemented in two different ways. EXAMPLE 10-6: INITIALIZING PORTE For 40/44-pin devices, PORTE is a 4-bit wide port. Three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/ CLRF PORTE ; Initialize PORTE by AN7) are individually configurable as inputs or outputs. ; clearing output These pins have Schmitt Trigger input buffers. When ; data latches CLRF LATE ; Alternate method selected as analog inputs, these pins will read as ‘0’s. ; to clear output The corresponding Data Direction register is TRISE. ; data latches Setting a TRISE bit (= 1) will make the corresponding MOVLW 0Ah ; Configure A/D PORTE pin an input (i.e., put the corresponding output MOVWF ADCON1 ; for digital inputs driver in a high-impedance mode). Clearing a TRISE bit MOVLW 03h ; Value used to (= 0) will make the corresponding PORTE pin an output ; initialize data ; direction (i.e., put the contents of the output latch on the selected MOVWF TRISE ; Set RE<0> as inputs pin). ; RE<1> as outputs TRISE controls the direction of the RE pins, even when ; RE<2> as inputs they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. Note: On a Power-on Reset, RE<2:0> are configured as analog inputs. DS39682E-page 110 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY REGISTER 10-1: TRISE REGISTER (40/44-PIN DEVICES ONLY) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode bit 3 Unimplemented: Read as ‘0’ bit 2 TRISE2: RE2 Direction Control bit 1 = Input 0 = Output bit 1 TRISE1: RE1 Direction Control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output © 2009 Microchip Technology Inc. DS39682E-page 111

PIC18F45J10 FAMILY TABLE 10-11: PORTE I/O SUMMARY TRIS I/O Pin Function I/O Description Setting Type RE0/RD/AN5 RE0 0 O DIG LATE<0> data output; not affected by analog input. 1 I ST PORTE<0> data input; disabled when analog input enabled. RD 1 I TTL PSP read enable input (PSP enabled). AN5 1 I ANA A/D Input Channel 5; default input configuration on POR. RE1/WR/AN6 RE1 0 O DIG LATE<1> data output; not affected by analog input. 1 I ST PORTE<1> data input; disabled when analog input enabled. WR 1 I TTL PSP write enable input (PSP enabled). AN6 1 I ANA A/D Input Channel 6; default input configuration on POR. RE2/CS/AN7 RE2 0 O DIG LATE<2> data output; not affected by analog input. 1 I ST PORTE<2> data input; disabled when analog input enabled. CS 1 I TTL PSP write enable input (PSP enabled). AN7 1 I ANA A/D Input Channel 7; default input configuration on POR. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTE(1) — — — — — RE2 RE1 RE0 50 LATE(1) — — — — — PORTE Data Latch Register 50 (Read and Write to Data Latch) TRISE(1) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 50 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 48 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE. Note 1: These registers are not available in 28-pin devices. DS39682E-page 112 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 10.7 Parallel Slave Port The timing for the control signals in Write and Read modes is shown in Figure10-4 and Figure10-5, Note: The Parallel Slave Port is only available in respectively. 40/44-pin devices. FIGURE 10-3: PORTD AND PORTE In addition to its function as a general I/O port, PORTD BLOCK DIAGRAM can also operate as an 8-bit wide Parallel Slave Port (PSP) or microprocessor port. PSP operation is (PARALLEL SLAVE PORT) controlled by the 4 upper bits of the TRISE register (Register10-1). Setting control bit, PSPMODE One bit of PORTD (TRISE<4>), enables PSP operation as long as the Data Bus Enhanced CCP module is not operating in Dual Output D Q or Quad Output PWM mode. In Slave mode, the port is RDx pin asynchronously readable and writable by the external WR LATD CK or world. WR PORTD Data Latch TTL The PSP can directly interface to an 8-bit micro- processor data bus. The external microprocessor can Q D read or write the PORTD latch as an 8-bit latch. Setting the control bit, PSPMODE, enables the PORTE I/O RD PORTD ENEN pins to become control inputs for the microprocessor port. When set, port pin RE0 is the RD input, RE1 is the WR input and RE2 is the CS (Chip Select) input. For this functionality, the corresponding data direction bits RD LATD of the TRISE register (TRISE<2:0>) must be config- ured as inputs (set). The A/D port configuration bits, Set Interrupt Flag PFCG<3:0> (ADCON1<3:0>), must also be set to a PSPIF (PIR1<7>) value in the range of ‘1010’ through ‘1111’. A write to the PSP occurs when both the CS and WR PORTE Pins lines are first detected low and ends when either are detected high. The PSPIF and IBF flag bits are both set Read TTL RD when the write ends. Chip Select A read from the PSP occurs when both the CS and RD TTL CS lines are first detected low. The data in PORTD is read out and the OBF bit is clear. If the user writes new data Write TTL WR to PORTD to set OBF, the data is immediately read out; however, the OBF bit is not set. When either the CS or RD lines are detected high, the Note: I/O pins have diode protection to VDD and VSS. PORTD pins return to the input state and the PSPIF bit is set. User applications should wait for PSPIF to be set before servicing the PSP; when this happens, the IBF and OBF bits can be polled and the appropriate action taken. © 2009 Microchip Technology Inc. DS39682E-page 113

PIC18F45J10 FAMILY FIGURE 10-4: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 10-5: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 10-13: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 50 LATD(1) PORTD Data Latch Register (Read and Write to Data Latch) 50 TRISD(1) PORTD Data Direction Control Register 50 PORTE(1) — — — — — RE2 RE1 RE0 50 LATE(1) — — — — — PORTE Data Latch Register 50 (Read and Write to Data Latch) TRISE(1) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 50 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47 PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49 PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49 IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 48 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’. DS39682E-page 114 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 11.0 TIMER0 MODULE The T0CON register (Register11-1) controls all aspects of the module’s operation, including the The Timer0 module incorporates the following features: prescale selection. It is both readable and writable. • Software selectable operation as a timer or A simplified block diagram of the Timer0 module in 8-bit counter in both 8-bit or 16-bit modes mode is shown in Figure11-1. Figure11-2 shows a • Readable and writable registers simplified block diagram of the Timer0 module in 16-bit • Dedicated 8-bit, software programmable mode. prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2009 Microchip Technology Inc. DS39682E-page 115

PIC18F45J10 FAMILY 11.1 Timer0 Operation internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the Timer0 can operate as either a timer or a counter; the timer/counter. mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on 11.2 Timer0 Reads and Writes in every clock by default unless a different prescaler value 16-Bit Mode is selected (see Section11.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited TMR0H is not the actual high byte of Timer0 in 16-bit for the following two instruction cycles. The user can mode. It is actually a buffered version of the real high work around this by writing an adjusted value to the byte of Timer0 which is not directly readable nor TMR0 register. writable (refer to Figure11-2). TMR0H is updated with the contents of the high byte of Timer0 during a read of The Counter mode is selected by setting the T0CS bit TMR0L. This provides the ability to read all 16 bits of (= 1). In this mode, Timer0 increments either on every Timer0 without having to verify that the read of the high rising or falling edge of pin RB5/T0CKI. The increment- and low byte were valid, due to a rollover between ing edge is determined by the Timer0 Source Edge successive reads of the high and low byte. Select bit, T0SE (T0CON<4>); clearing this bit selects the rising edge. Restrictions on the external clock input Similarly, a write to the high byte of Timer0 must also are discussed below. take place through the TMR0H Buffer register. The high byte is updated with the contents of TMR0H when a An external clock source can be used to drive Timer0; write occurs to TMR0L. This allows all 16 bits of Timer0 however, it must meet certain requirements to ensure to be updated at once. that the external clock can be synchronized with the FIGURE 11-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 Sync with Set 1 Internal TMR0L TMR0IF T0CKI pin Programmable 0 Clocks on Overflow Prescaler T0SE (2 TCY Delay) T0CS 3 8 T0PS<2:0> 8 PSA Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 11-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 1 1 SIynntecr nwaitlh TMR0L HTigMh RB0yte STMetR 0IF T0CKI pin ProPgrreasmcamlearble 0 Clocks 8 on Overflow T0SE (2 TCY Delay) T0CS 3 Read TMR0L T0PS<2:0> Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS39682E-page 116 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 11.3 Prescaler 11.3.1 SWITCHING PRESCALER ASSIGNMENT An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable. The prescaler assignment is fully under software Its value is set by the PSA and T0PS<2:0> bits control and can be changed “on-the-fly” during program (T0CON<3:0>) which determine the prescaler execution. assignment and prescale ratio. 11.4 Timer0 Interrupt Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values The TMR0 interrupt is generated when the TMR0 from 1:2 through 1:256 in power-of-2 increments are register overflows from FFh to 00h in 8-bit mode, or selectable. from FFFFh to 0000h in 16-bit mode. This overflow sets When assigned to the Timer0 module, all instructions the TMR0IF flag bit. The interrupt can be masked by writing to the TMR0 register (e.g., CLRF TMR0, MOVWF clearing the TMR0IE bit (INTCON<5>). Before TMR0, BSF TMR0, etc.) clear the prescaler count. re-enabling the interrupt, the TMR0IF bit must be cleared in software by the Interrupt Service Routine. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler Since Timer0 is shut down in Sleep mode, the TMR0 count but will not change the prescaler interrupt cannot awaken the processor from Sleep. assignment. TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page TMR0L Timer0 Register Low Byte 48 TMR0H Timer0 Register High Byte 48 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 48 TRISA — — TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 50 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. © 2009 Microchip Technology Inc. DS39682E-page 117

PIC18F45J10 FAMILY NOTES: DS39682E-page 118 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 12.0 TIMER1 MODULE A simplified block diagram of the Timer1 module is shown in Figure12-1. A block diagram of the module’s The Timer1 timer/counter module incorporates these operation in Read/Write mode is shown in Figure12-2. features: The module incorporates its own low-power oscillator • Software selectable operation as a 16-bit timer or to provide an additional clocking option. The Timer1 counter oscillator can also be used as a low-power clock source • Readable and writable 8-bit registers (TMR1H for the microcontroller in power-managed operation. and TMR1L) Timer1 can also be used to provide Real-Time Clock • Selectable clock source (internal or external) with (RTC) functionality to applications with only a minimal device clock or Timer1 oscillator internal options addition of external components and code overhead. • Interrupt-on-overflow Timer1 is controlled through the T1CON Control • Reset on CCP Special Event Trigger register (Register12-1). It also contains the Timer1 • Device clock status flag (T1RUN) Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>). REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of TImer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 6 T1RUN: Timer1 System Clock Status bit 1 = Device clock is derived from Timer1 oscillator 0 = Device clock is derived from another source bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 =Timer1 oscillator is enabled 0 =Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2009 Microchip Technology Inc. DS39682E-page 119

PIC18F45J10 FAMILY 12.1 Timer1 Operation When Timer1 is enabled, the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. This means Timer1 can operate in one of these modes: the values of TRISC<1:0> are ignored and the pins are • Timer read as ‘0’. • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction cycle (FOSC/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. FIGURE 12-1: TIMER1 BLOCK DIAGRAM Timer1 Oscillator Timer1 Clock Input On/Off 1 T1OSO/T1CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR1CS Timer1 On/Off T1CKPS<1:0> T1SYNC TMR1ON Set Clear TMR1 TMR1L HiTgMh RBy1te TMR1IF (CCP Special Event Trigger) on Overflow Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39682E-page 120 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY FIGURE 12-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator Timer1 Clock Input 1 T1OSO/T1CKI 1 Prescaler Synchronize FOSC/4 1, 2, 4, 8 Detect 0 Internal Clock 0 T1OSI 2 Sleep Input T1OSCEN(1) TMR1CS Timer1 T1CKPS<1:0> On/Off T1SYNC TMR1ON Clear TMR1 TMR1L HiTgMh RB1yte STMetR 1IF (CCP Special Event Trigger) on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. 12.2 Timer1 16-Bit Read/Write Mode 12.3 Timer1 Oscillator Timer1 can be configured for 16-bit reads and writes An on-chip crystal oscillator circuit is incorporated (see Figure12-2). When the RD16 control bit between pins T1OSI (input) and T1OSO (amplifier (T1CON<7>) is set, the address for TMR1H is mapped output). It is enabled by setting the Timer1 Oscillator to a buffer register for the high byte of Timer1. A read Enable bit, T1OSCEN (T1CON<3>). The oscillator is a from TMR1L will load the contents of the high byte of low-power circuit rated for 32kHz crystals. It will continue Timer1 into the Timer1 High Byte Buffer register. This to run during all power-managed modes. The circuit for a provides the user with the ability to accurately read all typical oscillator is shown in Figure12-3. Table12-1 16bits of Timer1 without having to determine whether a shows the capacitor selection for the Timer1 oscillator. read of the high byte, followed by a read of the low byte, The user must provide a software time delay to ensure has become invalid due to a rollover between reads. proper start-up of the Timer1 oscillator. A write to the high byte of Timer1 must also take place through the TMR1H Buffer register. The Timer1 high FIGURE 12-3: EXTERNAL byte is updated with the contents of TMR1H when a COMPONENTS FOR THE write occurs to TMR1L. This allows a user to write all TIMER1 OSCILLATOR 16 bits to both the high and low bytes of Timer1 at once. C1 The high byte of Timer1 is not directly readable or PIC18F45J10 27 pF writable in this mode. All reads and writes must take T1OSI place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. XTAL The prescaler is only cleared on writes to TMR1L. 32.768 kHz T1OSO C2 27 pF Note: See the Notes with Table12-1 for additional information about capacitor selection. © 2009 Microchip Technology Inc. DS39682E-page 121

PIC18F45J10 FAMILY TABLE 12-1: CAPACITOR SELECTION FOR 12.3.2 TIMER1 OSCILLATOR LAYOUT THE TIMER OSCILLATOR(2,3,4) CONSIDERATIONS Oscillator The Timer1 oscillator circuit draws very little power Freq. C1 C2 Type during operation. Due to the low-power nature of the LP 32kHz 27pF(1) 27pF(1) oscillator, it may also be sensitive to rapidly changing signals in close proximity. Note1: Microchip suggests these values as a The oscillator circuit, shown in Figure12-3, should be starting point in validating the oscillator located as close as possible to the microcontroller. circuit. There should be no circuits passing within the oscillator 2: Higher capacitance increases the stability circuit boundaries other than VSS or VDD. of the oscillator but also increases the If a high-speed circuit must be located near the oscilla- start-up time. tor (such as the CCP1 pin in Output Compare or PWM 3: Since each resonator/crystal has its own mode, or the primary oscillator using the OSC2 pin), a characteristics, the user should consult grounded guard ring around the oscillator circuit, as the resonator/crystal manufacturer for shown in Figure12-4, may be helpful when used on a appropriate values of external single-sided PCB or in addition to a ground plane. components. FIGURE 12-4: OSCILLATOR CIRCUIT 4: Capacitor values are for design guidance WITH GROUNDED only. GUARD RING 12.3.1 USING TIMER1 AS A VDD CLOCK SOURCE VSS The Timer1 oscillator is also available as a clock source in power-managed modes. By setting the clock select OSC1 bits, SCS<1:0> (OSCCON<1:0>), to ‘01’, the device switches to SEC_RUN mode; both the CPU and OSC2 peripherals are clocked from the Timer1 oscillator. If the IDLEN bit (OSCCON<7>) is cleared and a SLEEP instruction is executed, the device enters SEC_IDLE RC0 mode. Additional details are available in Section4.0 “Power-Managed Modes”. RC1 Whenever the Timer1 oscillator is providing the clock source, the Timer1 system clock status flag, T1RUN (T1CON<6>), is set. This can be used to determine the RC2 controller’s current clocking mode. It can also indicate Note: Not drawn to scale. the clock source being currently used by the Fail-Safe Clock Monitor. If the Clock Monitor is enabled and the Timer1 oscillator fails while providing the clock, polling 12.4 Timer1 Interrupt the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source. The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled or disabled by setting or clearing the Timer1 Interrupt Enable bit, TMR1IE (PIE1<0>). DS39682E-page 122 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 12.5 Resetting Timer1 Using the 12.6 Using Timer1 as a Real-Time Clock ECCP/CCP Special Event Trigger Adding an external LP oscillator to Timer1 (such as the If ECCP1/CCP1 or CCP2 is configured to generate one described in Section12.3 “Timer1 Oscillator” a Special Event Trigger in Compare mode above) gives users the option to include RTC function- (CCPxM<3:0>=1011), this signal will reset Timer1. ality to their applications. This is accomplished with an The trigger from CCP2 will also start an A/D conversion inexpensive watch crystal to provide an accurate time if the A/D module is enabled (see Section15.2.1 base and several lines of application code to calculate “Special Event Trigger” for more information). the time. When operating in Sleep mode and using a battery or supercapacitor as a power source, it can The module must be configured as either a timer or a completely eliminate the need for a separate RTC synchronous counter to take advantage of this feature. device and battery backup. When used this way, the CCPRH:CCPRL register pair effectively becomes a period register for Timer1. The application code routine, RTCisr, shown in Example12-1, demonstrates a simple method to If Timer1 is running in Asynchronous Counter mode, increment a counter at one-second intervals using an this Reset operation may not work. Interrupt Service Routine. Incrementing the TMR1 In the event that a write to Timer1 coincides with a register pair to overflow triggers the interrupt and calls Special Event Trigger, the write operation will take the routine which increments the seconds counter by precedence. one. Additional counters for minutes and hours are incremented as the previous counter overflows. Note: The Special Event Triggers from the ECCP1/CCPx module will not set the Since the register pair is 16 bits wide, counting up to TMR1IF interrupt flag bit (PIR1<0>). overflow the register directly from a 32.768kHz clock would take 2 seconds. To force the overflow at the required one-second intervals, it is necessary to preload it. The simplest method is to set the MSb of TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered; doing so may introduce cumulative error over many cycles. For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1) as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. © 2009 Microchip Technology Inc. DS39682E-page 123

PIC18F45J10 FAMILY EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW 80h ; Preload TMR1 register pair MOVWF TMR1H ; for 1 second overflow CLRF TMR1L MOVLW b’00001111’ ; Configure for external clock, MOVWF T1CON ; Asynchronous operation, external oscillator CLRF secs ; Initialize timekeeping registers CLRF mins ; MOVLW .12 MOVWF hours BSF PIE1, TMR1IE ; Enable Timer1 interrupt RETURN RTCisr BSF TMR1H, 7 ; Preload for 1 sec overflow BCF PIR1, TMR1IF ; Clear interrupt flag INCF secs, F ; Increment seconds MOVLW .59 ; 60 seconds elapsed? CPFSGT secs RETURN ; No, done CLRF secs ; Clear seconds INCF mins, F ; Increment minutes MOVLW .59 ; 60 minutes elapsed? CPFSGT mins RETURN ; No, done CLRF mins ; clear minutes INCF hours, F ; Increment hours MOVLW .23 ; 24 hours elapsed? CPFSGT hours RETURN ; No, done CLRF hours ; Reset hours RETURN ; Done TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47 PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49 PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49 IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49 TMR1L Timer1 Register Low Byte 48 TMR1H Timer1 Register High Byte 48 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 48 Legend: Shaded cells are not used by the Timer1 module. Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’. DS39682E-page 124 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 13.0 TIMER2 MODULE 13.1 Timer2 Operation The Timer2 timer module incorporates the following In normal operation, TMR2 is incremented from 00h on features: each clock (FOSC/4). A 4-bit counter/prescaler on the clock input gives direct input, divide-by-4 and divide-by-16 • 8-bit Timer and Period registers (TMR2 and PR2, prescale options; these are selected by the prescaler con- respectively) trol bits, T2CKPS<1:>0 (T2CON<1:0>). The value of • Readable and writable (both registers) TMR2 is compared to that of the Period register, PR2, on • Software programmable prescaler each clock cycle. When the two values match, the (1:1, 1:4 and 1:16) comparator generates a match signal as the timer output. • Software programmable postscaler This signal also resets the value of TMR2 to 00h on the (1:1 through 1:16) next cycle and drives the output counter/postscaler (see • Interrupt on TMR2 to PR2 match Section13.2 “Timer2 Interrupt”). • Optional use as the shift clock for the The TMR2 and PR2 registers are both directly readable MSSP module and writable. The TMR2 register is cleared on any device Reset, while the PR2 register initializes at FFh. The module is controlled through the T2CON register Both the prescaler and postscaler counters are cleared (Register13-1) which enables or disables the timer and on the following events: configures the prescaler and postscaler. Timer2 can be shut off by clearing control bit, TMR2ON (T2CON<2>), • a write to the TMR2 register to minimize power consumption. • a write to the T2CON register A simplified block diagram of the module is shown in • any device Reset (Power-on Reset, MCLR Reset, Figure13-1. Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written. REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 © 2009 Microchip Technology Inc. DS39682E-page 125

PIC18F45J10 FAMILY 13.2 Timer2 Interrupt 13.3 Timer2 Output Timer2 can also generate an optional device interrupt. The unscaled output of TMR2 is available primarily to The Timer2 output signal (TMR2 to PR2 match) pro- the CCP modules, where it is used as a time base for vides the input for the 4-bit output counter/postscaler. operations in PWM mode. This counter generates the TMR2 match interrupt flag Timer2 can be optionally used as the shift clock source which is latched in TMR2IF (PIR1<1>). The interrupt is for the MSSP module operating in SPI mode. enabled by setting the TMR2 Match Interrupt Enable Additional information is provided in Section16.0 bit, TMR2IE (PIE1<1>). “Master Synchronous Serial Port (MSSP) Module”. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0> (T2CON<6:3>). FIGURE 13-1: TIMER2 BLOCK DIAGRAM 4 1:1 to 1:16 T2OUTPS<3:0> Set TMR2IF Postscaler 2 T2CKPS<1:0> TMR2 Output (to PWM or MSSP) TMR2/PR2 Reset Match 1:1, 1:4, 1:16 FOSC/4 TMR2 Comparator PR2 Prescaler 8 8 8 Internal Data Bus TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47 PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49 PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49 IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49 TMR2 Timer2 Register 48 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 48 PR2 Timer2 Period Register 48 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’. DS39682E-page 126 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 14.0 CAPTURE/COMPARE/PWM The Capture and Compare operations described in this (CCP) MODULES chapter apply to all standard and Enhanced CCP modules. PIC18F45J10 family devices all have two CCP Note: Throughout this section and Section15.0 (Capture/Compare/PWM) modules. Each module “Enhanced Capture/Compare/PWM (ECCP) contains a 16-bit register which can operate as a 16-bit Module”, references to the register and bit Capture register, a 16-bit Compare register or a PWM names for CCP modules are referred to gener- Master/Slave Duty Cycle register. ically by the use of ‘x’ or ‘y’ in place of the In 28-pin devices, the two standard CCP modules specific module number. Thus, “CCPxCON” (CCP1 and CCP2) operate as described in this chapter. might refer to the control register for CCP1, In 40/44-pin devices, CCP1 is implemented as an CCP2 or ECCP1. “CCPxCON” is used Enhanced CCP module (ECCP1) with standard Capture throughout these sections to refer to the and Compare modes and Enhanced PWM modes. The module control register regardless of whether Enhanced CCP implementation is discussed in the CCP module is a standard or Enhanced Section15.0 “Enhanced Capture/Compare/PWM implementation. (ECCP) Module”. REGISTER 14-1: CCPxCON: CCP1/CCP2 CONTROL REGISTER IN 28-PIN DEVICES U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs (DCxB<9:2>) of the duty cycle are found in CCPRxL. bit 3-0 CCPxM<3:0>: CCPx Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0001 = Reserved 0010 = Compare mode, toggle output on match (CCPxIF bit is set) 0011 = Reserved 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set) 1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set) 1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin reflects I/O state) 1011 = Compare mode: trigger special event, reset timer, start A/D conversion on CCPx match (CCPxIF bit is set) 11xx = PWM mode © 2009 Microchip Technology Inc. DS39682E-page 127

PIC18F45J10 FAMILY 14.1 CCP Module Configuration Both modules may be active at any given time and may share the same timer resource if they are configured to Each Capture/Compare/PWM module is associated operate in the same mode (Capture/Compare or PWM) with a control register (generically, CCPxCON) and a at the same time. The interactions between the two data register (CCPRx). The data register, in turn, is modules are summarized in Figure14-1 and comprised of two 8-bit registers: CCPRxL (low byte) Figure14-2. In Timer1 in Asynchronous Counter mode, and CCPRxH (high byte). All registers are both the capture operation will not work. readable and writable. 14.1.2 CCP2 PIN ASSIGNMENT 14.1.1 CCP MODULES AND TIMER The pin assignment for CCP2 (Capture input, Compare RESOURCES and PWM output) can change, based on device config- The CCP modules utilize Timers 1 or 2, depending on uration. The CCP2MX Configuration bit determines the mode selected. Timer1 is available to modules in which pin CCP2 is multiplexed to. By default, it is Capture or Compare modes, while Timer2 is available assigned to RC1 (CCP2MX = 1). If the Configuration bit for modules in PWM mode. is cleared, CCP2 is multiplexed with RB3. Changing the pin assignment of CCP2 does not auto- TABLE 14-1: ECCP/CCP MODE – TIMER matically change any requirements for configuring the RESOURCE port pin. Users must always verify that the appropriate ECCP/CCP Mode Timer Resource TRIS register is configured correctly for CCP2 operation regardless of where it is located. Capture Timer1 Compare Timer1 PWM Timer2 TABLE 14-2: INTERACTIONS BETWEEN ECCP1/CCP1 AND CCP2 FOR TIMER RESOURCES CCP1 Mode CCP2 Mode Interaction Capture Capture Each module uses TMR1 as the time base. Capture Compare CCP2 can be configured for the Special Event Trigger to reset TMR1. Automatic A/D conversions on the trigger event can also be done. Operation of ECCP1/CCP1 will be affected. Compare Capture ECCP1/CCP1 can be configured for the Special Event Trigger to reset TMR1. Operation of CCP2 will be affected. Compare Compare Either module can be configured for the Special Event Trigger to reset TMR1. Automatic A/D conversions on the CCP2 trigger event can be done. Capture PWM(1) None Compare PWM(1) None PWM(1) Capture None PWM(1) Compare None PWM(1) PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt). Note 1: Includes standard and Enhanced PWM operation. DS39682E-page 128 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 14.2 Capture Mode 14.2.3 CCP PRESCALER In Capture mode, the CCPRxH:CCPRxL register pair There are four prescaler settings in Capture mode; they captures the 16-bit value of the TMR1 register when an are specified as part of the operating mode selected by event occurs on the corresponding CCPx pin. An event the mode select bits (CCPxM<3:0>). Whenever the is defined as one of the following: CCP module is turned off or Capture mode is disabled, the prescaler counter is cleared. This means that any • every falling edge Reset will clear the prescaler counter. • every rising edge Switching from one capture prescaler to another may • every 4th rising edge generate an interrupt. Also, the prescaler counter will • every 16th rising edge not be cleared; therefore, the first capture may be from The event is selected by the mode select bits, a non-zero prescaler. Example14-1 shows the CCPxM<3:0> (CCPxCON<3:0>). When a capture is recommended method for switching between capture made, the interrupt request flag bit, CCPxIF, is set; it prescalers. This example also clears the prescaler must be cleared in software. If another capture occurs counter and will not generate the “false” interrupt. before the value in register CCPRx is read, the old captured value is overwritten by the new captured value. EXAMPLE 14-1: CHANGING BETWEEN CAPTURE PRESCALERS 14.2.1 CCP PIN CONFIGURATION (CCP2 SHOWN) In Capture mode, the appropriate CCPx pin should be CLRF CCP2CON ; Turn CCP module off configured as an input by setting the corresponding MOVLW NEW_CAPT_PS ; Load WREG with the TRIS direction bit. ; new prescaler mode ; value and CCP ON Note: If RB3/CCP2 or RC1/CCP2 is configured MOVWF CCP2CON ; Load CCP2CON with as an output, a write to the port can cause ; this value a capture condition. 14.2.2 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false inter- rupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode. FIGURE 14-1: CAPTURE MODE OPERATION BLOCK DIAGRAM Set CCP1IF CCPR1H CCPR1L CCP1 pin Prescaler and ÷ 1, 4, 16 Edge Detect TMR1H TMR1L 4 CCP1CON<3:0> Set CCP2IF 4 Q1:Q4 4 CCP2CON<3:0> CCPR2H CCPR2L CCP2 pin Prescaler and ÷ 1, 4, 16 Edge Detect TMR1H TMR1L © 2009 Microchip Technology Inc. DS39682E-page 129

PIC18F45J10 FAMILY 14.3 Compare Mode 14.3.2 TIMER1 MODE SELECTION In Compare mode, the 16-bit CCPRx register value is Timer1 must be running in Timer mode or Synchro- constantly compared against the TMR1 register value. nized Counter mode if the CCP module is using the When a match occurs, the CCPx pin can be: compare feature. In Asynchronous Counter mode, the compare operation may not work. • driven high • driven low 14.3.3 SOFTWARE INTERRUPT MODE • toggled (high-to-low or low-to-high) When the Generate Software Interrupt mode is chosen • remain unchanged (that is, reflects the state of the (CCPxM<3:0> = 1010), the corresponding CCPx pin is I/O latch) not affected. Only a CCP interrupt is generated, if The action on the pin is based on the value of the mode enabled and the CCPxIE bit is set. select bits (CCPxM<3:0>). At the same time, the inter- 14.3.4 SPECIAL EVENT TRIGGER rupt flag bit, CCPxIF, is set. Both CCP modules are equipped with a Special Event 14.3.1 CCP PIN CONFIGURATION Trigger. This is an internal hardware signal generated The user must configure the CCPx pin as an output by in Compare mode to trigger actions by other modules. clearing the appropriate TRIS bit. The Special Event Trigger is enabled by selecting the Compare Special Event Trigger mode Note: Clearing the CCP2CON register will force (CCPxM<3:0> = 1011). the RB3 or RC1 compare output latch For either CCP module, the Special Event Trigger resets (depending on device configuration) to the the Timer register pair for whichever timer resource is default low level. This is not the PORTB or currently assigned as the module’s time base. This PORTC I/O data latch. allows the CCPRx registers to serve as a Programmable Period register for either timer. The Special Event Trigger for CCP2 can also start an A/D conversion. In order to do this, the A/D converter must already be enabled. FIGURE 14-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger Set CCP1IF (Timer1 Reset) CCPR1H CCPR1L CCP1 pin Compare Output S Q Comparator Match Logic R TRIS 4 Output Enable CCP1CON<3:0> TMR1H TMR1L Special Event Trigger (Timer1 Reset, A/D Trigger) Set CCP2IF CCP2 pin Compare Output S Q Comparator Match Logic R TRIS 4 Output Enable CCPR2H CCPR2L CCP2CON<3:0> DS39682E-page 130 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY TABLE 14-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47 RCON IPEN — CM RI TO PD POR BOR 46 PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49 PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49 IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49 PIR2 OSCFIF CMIF — — BCL1IF — — CCP2IF 49 PIE2 OSCFIE CMIE — — BCL1IE — — CCP2IE 49 IPR2 OSCFIP CMIP — — BCL1IP — — CCP2IP 49 TRISB PORTB Data Direction Control Register 50 TRISC PORTC Data Direction Control Register 50 TMR1L Timer1 Register Low Byte 48 TMR1H Timer1 Register High Byte 48 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 48 CCPR1L Capture/Compare/PWM Register 1 Low Byte 49 CCPR1H Capture/Compare/PWM Register 1 High Byte 49 CCP1CON P1M1(1) P1M0(1) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 49 CCPR2L Capture/Compare/PWM Register 2 Low Byte 49 CCPR2H Capture/Compare/PWM Register 2 High Byte 49 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 49 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare or Timer1. Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’. © 2009 Microchip Technology Inc. DS39682E-page 131

PIC18F45J10 FAMILY 14.4 PWM Mode 14.4.1 PWM PERIOD In Pulse-Width Modulation (PWM) mode, the CCPx pin The PWM period is specified by writing to the PR2 produces up to a 10-bit resolution PWM output. Since register. The PWM period can be calculated using the the CCP2 pin is multiplexed with a PORTB or PORTC following formula: data latch, the appropriate TRIS bit must be cleared to make the CCP2 pin an output. EQUATION 14-1: Note: Clearing the CCP2CON register will force PWM Period = [(PR2) + 1] • 4 • TOSC • the RB3 or RC1 output latch (depending on (TMR2 Prescale Value) device configuration) to the default low level. This is not the PORTB or PORTC I/O PWM frequency is defined as 1/[PWM period]. data latch. When TMR2 is equal to PR2, the following three events Figure14-3 shows a simplified block diagram of the occur on the next increment cycle: CCP module in PWM mode. • TMR2 is cleared For a step-by-step procedure on how to set up the CCP • The CCPx pin is set (exception: if PWM duty module for PWM operation, see Section14.4.4 cycle=0%, the CCPx pin will not be set) “Setup for PWM Operation”. • The PWM duty cycle is latched from CCPRxL into CCPRxH FIGURE 14-3: SIMPLIFIED PWM BLOCK Note: The Timer2 postscalers (see Section13.0 DIAGRAM “Timer2 Module”) are not used in the CCPxCON<5:4> determination of the PWM frequency. The Duty Cycle Registers postscaler could be used to have a servo CCPRxL update rate at a different frequency than the PWM output. 14.4.2 PWM DUTY CYCLE CCPRxH (Slave) CCPx Output The PWM duty cycle is specified by writing to the Comparator R Q CCPRxL register and to the CCPxCON<5:4> bits. Up to 10-bit resolution is available. The CCPRxL contains the eight MSbs and the CCPxCON<5:4> contains the TMR2 (Note 1) two LSbs. This 10-bit value is represented by S CCPRxL:CCPxCON<5:4>. The following equation is Corresponding used to calculate the PWM duty cycle in time: Comparator TRIS bit Clear Timer, CCP1 pin and EQUATION 14-2: latch D.C. PR2 PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) • Note1: The 8-bit TMR2 value is concatenated with the 2-bit TOSC • (TMR2 Prescale Value) internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. CCPRxL and CCPxCON<5:4> can be written to at any A PWM output (Figure14-4) has a time base (period) time, but the duty cycle value is not latched into and a time that the output stays high (duty cycle). CCPRxH until after a match between PR2 and TMR2 The frequency of the PWM is the inverse of the occurs (i.e., the period is complete). In PWM mode, period (1/period). CCPRxH is a read-only register. FIGURE 14-4: PWM OUTPUT Period Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 DS39682E-page 132 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY The CCPRxH register and a 2-bit internal latch are EQUATION 14-3: used to double-buffer the PWM duty cycle. This ⎛FOSC⎞ double-buffering is essential for glitchless PWM log⎝F----P---W-----M---⎠ operation. PWM Resolution (max) = -----------------------------bits log(2) When the CCPRxH and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCPx pin is cleared. Note: If the PWM duty cycle value is longer than the PWM period, the CCP2 pin will not be The maximum PWM resolution (bits) for a given PWM cleared. frequency is given by the equation: TABLE 14-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 14.4.3 PWM AUTO-SHUTDOWN 14.4.4 SETUP FOR PWM OPERATION (CCP1 ONLY) The following steps should be taken when configuring The PWM auto-shutdown features of the Enhanced CCP the CCP module for PWM operation: module are also available to CCP1 in 28-pin devices. The 1. Set the PWM period by writing to the PR2 operation of this feature is discussed in detail in register. Section15.4.7 “Enhanced PWM Auto-Shutdown”. 2. Set the PWM duty cycle by writing to the Auto-shutdown features are not available for CCP2. CCPRxL register and CCPxCON<5:4> bits. 3. Make the CCPx pin an output by clearing the appropriate TRIS bit. 4. Set the TMR2 prescale value, then enable Timer2 by writing to T2CON. 5. Configure the CCPx module for PWM operation. © 2009 Microchip Technology Inc. DS39682E-page 133

PIC18F45J10 FAMILY TABLE 14-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47 RCON IPEN — CM RI TO PD POR BOR 46 PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49 PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49 IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49 TRISB PORTB Data Direction Control Register 50 TRISC PORTC Data Direction Control Register 50 TMR2 Timer2 Register 48 PR2 Timer2 Period Register 48 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 48 CCPR1L Capture/Compare/PWM Register 1 Low Byte 49 CCPR1H Capture/Compare/PWM Register 1 High Byte 49 CCP1CON P1M1(1) P1M0(1) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 49 CCPR2L Capture/Compare/PWM Register 2 Low Byte 49 CCPR2H Capture/Compare/PWM Register 2 High Byte 49 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 49 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1) 49 ECCP1DEL PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1) 49 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’. DS39682E-page 134 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 15.0 ENHANCED CAPTURE/ and restart. The Enhanced features are discussed in COMPARE/PWM (ECCP) detail in Section15.4 “Enhanced PWM Mode”. Capture, Compare and single output PWM functions of MODULE the ECCP module are the same as described for the standard CCP module. Note: The ECCP module is implemented only in 40/44-pin devices. The control register for the Enhanced CCP module is shown in Register15-1. It differs from the CCP1CON In PIC18F44J10/45J10 devices, ECCP1 is register in PIC18F24J10/25J10 devices in that the two implemented as a standard CCP module with Most Significant bits are implemented to control PWM Enhanced PWM capabilities. These include the functionality. provisions for 2 or 4 output channels, user-selectable polarity, dead-band control and automatic shutdown REGISTER 15-1: CCP1CON: ECCP1 CONTROL REGISTER (40/44-PIN DEVICES) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 P1M<1:0>: Enhanced PWM Output Configuration bits If CCP1M<3:2> = 00, 01, 10: xx = P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins If CCP1M<3:2> = 11: 00 = Single output: P1A modulated; P1B, P1C, P1D assigned as port pins 01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive 10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive bit 5-4 DC1B<1:0>: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPR1L. bit 3-0 CCP1M<3:0>: CCP1 Module Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP module) 0001 = Reserved 0010 = Compare mode, toggle output on match 0011 = Capture mode 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, initialize CCP1 pin low, set output on compare match (set CCP1IF) 1001 = Compare mode, initialize CCP1 pin high, clear output on compare match (set CCP1IF) 1010 = Compare mode, generate software interrupt only, CCP1 pin reverts to I/O state 1011 = Compare mode, trigger special event (ECCP resets TMR1, sets CCP1IF bit) 1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high 1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low © 2009 Microchip Technology Inc. DS39682E-page 135

PIC18F45J10 FAMILY In addition to the expanded range of modes available 15.2 Capture and Compare Modes through the CCP1CON register and ECCP1AS register, the ECCP module has an additional register Except for the operation of the Special Event Trigger associated with Enhanced PWM operation and discussed below, the Capture and Compare modes of auto-shutdown features. It is: the ECCP module are identical in operation to that of CCP2. These are discussed in detail in Section14.2 • ECCP1DEL (PWM Dead-Band Delay) “Capture Mode” and Section14.3 “Compare Mode”. No changes are required when moving 15.1 ECCP Outputs and Configuration between 28-pin and 40/44-pin devices. The Enhanced CCP module may have up to four PWM 15.2.1 SPECIAL EVENT TRIGGER outputs, depending on the selected operating mode. These outputs, designated P1A through P1D, are The Special Event Trigger output of ECCP1 resets the multiplexed with I/O pins on PORTC and PORTD. The TMR1 register pair. This allows the CCPR1 register to outputs that are active depend on the ECCP operating effectively be a 16-bit programmable period register for mode selected. The pin assignments are summarized Timer1. in Table15-1. 15.3 Standard PWM Mode To configure the I/O pins as PWM outputs, the proper PWM mode must be selected by setting the P1M<1:0> When configured in Single Output mode, the ECCP and CCP1M<3:0> bits. The appropriate TRISC and module functions identically to the standard CCP TRISD direction bits for the port pins must also be set module in PWM mode, as described in Section14.4 as outputs. “PWM Mode”. This is also sometimes referred to as “Compatible CCP” mode, as in Table15-1. 15.1.1 ECCP MODULES AND TIMER RESOURCES Note: When setting up single output PWM operations, users are free to use either of Like the standard CCP modules, the ECCP module can the processes described in Section14.4.4 utilize Timers 1 or 2, depending on the mode selected. “Setup for PWM Operation” or Timer1 is available for modules in Capture or Compare Section15.4.9 “Setup for PWM Opera- modes, while Timer2 is available for modules in PWM tion”. The latter is more generic and will mode. Interactions between the standard and work for either single or multi-output PWM. Enhanced CCP modules are identical to those described for standard CCP modules. Additional details on timer resources are provided in Section14.1.1 “CCP Modules and Timer Resources”. TABLE 15-1: PIN ASSIGNMENTS FOR VARIOUS ECCP1 MODES CCP1CON ECCP Mode RC2 RD5 RD6 RD7 Configuration All 40/44-pin Devices: Compatible CCP 00xx 11xx CCP1 RD5/PSP5 RD6/PSP6 RD7/PSP7 Dual PWM 10xx 11xx P1A P1B RD6/PSP6 RD7/PSP7 Quad PWM x1xx 11xx P1A P1B P1C P1D Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP1 in a given mode. DS39682E-page 136 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 15.4 Enhanced PWM Mode 15.4.1 PWM PERIOD The Enhanced PWM mode provides additional PWM The PWM period is specified by writing to the PR2 output options for a broader range of control applica- register. The PWM period can be calculated using the tions. The module is a backward compatible version of following equation. the standard CCP module and offers up to four outputs, designated P1A through P1D. Users are also able to EQUATION 15-1: select the polarity of the signal (either active-high or PWM Period = [(PR2) + 1] • 4 • TOSC • active-low). The module’s output mode and polarity are (TMR2 Prescale Value) configured by setting the P1M<1:0> and CCP1M<3:0> bits of the CCP1CON register. PWM frequency is defined as 1/[PWM period]. When Figure15-1 shows a simplified block diagram of PWM TMR2 is equal to PR2, the following three events occur operation. All control registers are double-buffered and on the next increment cycle: are loaded at the beginning of a new PWM cycle (the • TMR2 is cleared period boundary when Timer2 resets) in order to • The CCP1 pin is set (if PWM duty cycle=0%, the prevent glitches on any of the outputs. The exception is CCP1 pin will not be set) the PWM Dead-Band Delay register, ECCP1DEL, • The PWM duty cycle is copied from CCPR1L into which is loaded at either the duty cycle boundary or the CCPR1H period boundary (whichever comes first). Because of the buffering, the module waits until the assigned timer Note: The Timer2 postscaler (see Section13.0 resets instead of starting immediately. This means that “Timer2 Module”) is not used in the Enhanced PWM waveforms do not exactly match the determination of the PWM frequency. The standard PWM waveforms, but are instead offset by postscaler could be used to have a servo one full instruction cycle (4 TOSC). update rate at a different frequency than As before, the user must manually configure the the PWM output. appropriate TRIS bits for output. FIGURE 15-1: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE CCP1CON<5:4> P1M1<1:0> CCP1M<3:0> Duty Cycle Registers 2 4 CCPR1L CCP1/P1A CCP1/P1A TRISx<x> CCPR1H (Slave) P1B P1B Output TRISx<x> Comparator R Q Controller P1C P1C TMR2 (Note 1) S TRISx<x> P1D P1D Comparator Clear Timer, TRISx<x> set CCP1 pin and latch D.C. PR2 ECCP1DEL Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. © 2009 Microchip Technology Inc. DS39682E-page 137

PIC18F45J10 FAMILY 15.4.2 PWM DUTY CYCLE Note: If the PWM duty cycle value is longer than The PWM duty cycle is specified by writing to the the PWM period, the CCP1 pin will not be CCPR1L register and to the CCP1CON<5:4> bits. Up cleared. to 10-bit resolution is available. The CCPR1L register contains the eight MSbs and the CCP1CON<5:4> 15.4.3 PWM OUTPUT CONFIGURATIONS contains the two LSbs. This 10-bit value is represented The P1M<1:0> bits in the CCP1CON register allow one by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is of four configurations: calculated by the following equation: • Single Output EQUATION 15-2: • Half-Bridge Output PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) • • Full-Bridge Output, Forward mode TOSC • (TMR2 Prescale Value) • Full-Bridge Output, Reverse mode The Single Output mode is the standard PWM mode CCPR1L and CCP1CON<5:4> can be written to at any discussed in Section15.4 “Enhanced PWM Mode”. time, but the duty cycle value is not copied into The Half-Bridge and Full-Bridge Output modes are CCPR1H until a match between PR2 and TMR2 occurs covered in detail in the sections that follow. (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. The general relationship of the outputs in all configurations is summarized in Figure15-2. The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM opera- tion. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the CCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the following equation: EQUATION 15-3: log(FOSC) PWM Resolution (max) = FPWM bits log(2) TABLE 15-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.58 DS39682E-page 138 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY FIGURE 15-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) 0 PR2 + 1 CCP1CON SIGNAL Duty <7:6> Cycle Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive FIGURE 15-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) 0 PR2 + 1 CCP1CON SIGNAL Duty <7:6> Cycle Period 00 (Single Output) P1A Modulated P1A Modulated Delay(1) Delay(1) 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (ECCP1DEL<6:0>) Note 1: Dead-band delay is programmed using the ECCP1DEL register (see Section15.4.6 “Programmable Dead-Band Delay”). © 2009 Microchip Technology Inc. DS39682E-page 139

PIC18F45J10 FAMILY 15.4.4 HALF-BRIDGE MODE FIGURE 15-4: HALF-BRIDGE PWM OUTPUT In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal Period Period is output on the P1A pin, while the complementary PWM Duty Cycle output signal is output on the P1B pin (Figure15-4). This mode can be used for half-bridge applications, as shown P1A(2) in Figure15-5, or for full-bridge applications where four td power switches are being modulated with two PWM td signals. P1B(2) In Half-Bridge Output mode, the programmable dead- band delay can be used to prevent shoot-through (1) (1) (1) current in half-bridge power devices. The value of bits, PDC<6:0>, sets the number of instruction cycles before td = Dead-Band Delay the output is driven active. If the value is greater than the duty cycle, the corresponding output remains Note 1: At this time, the TMR2 register is equal to the inactive during the entire cycle. See Section15.4.6 PR2 register. “Programmable Dead-Band Delay” for more details 2: Output signals are shown as active-high. of the dead-band delay operations. Since the P1A and P1B outputs are multiplexed with the PORTC<2> and PORTD<5> data latches, the TRISC<2> and TRISD<5> bits must be cleared to configure P1A and P1B as outputs. FIGURE 15-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) V+ PIC18F4XJ10 FET Driver + P1A V - Load FET Driver + P1B V - V- Half-Bridge Output Driving a Full-Bridge Circuit V+ PIC18F4XJ10 FET FET Driver Driver P1A Load FET FET Driver Driver P1B V- DS39682E-page 140 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 15.4.5 FULL-BRIDGE MODE P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2> and PORTD<7:5> data latches. The In Full-Bridge Output mode, four pins are used as TRISC<2> and TRISD<7:5> bits must be cleared to outputs; however, only two outputs are active at a time. make the P1A, P1B, P1C and P1D pins outputs. In the Forward mode, pin P1A is continuously active and pin P1D is modulated. In the Reverse mode, pin P1C is continuously active and pin P1B is modulated. These are illustrated in Figure15-6. FIGURE 15-6: FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A(2) Duty Cycle P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Duty Cycle P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2009 Microchip Technology Inc. DS39682E-page 141

PIC18F45J10 FAMILY FIGURE 15-7: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18F4XJ10 FET QA QC FET Driver Driver P1A Load P1B FET FET Driver Driver P1C QB QD V- P1D 15.4.5.1 Direction Change in Full-Bridge Mode Figure15-9 shows an example where the PWM direction changes from forward to reverse at a near In the Full-Bridge Output mode, the P1M1 bit in the 100% duty cycle. At time t1, the outputs P1A and P1D CCP1CON register allows the user to control the become inactive while output P1C becomes active. In forward/reverse direction. When the application firm- this example, since the turn-off time of the power ware changes this direction control bit, the module will devices is longer than the turn-on time, a shoot-through assume the new direction on the next PWM cycle. current may flow through power devices, QC and QD Just before the end of the current PWM period, the (see Figure15-7), for the duration of ‘t’. The same modulated outputs (P1B and P1D) are placed in their phenomenon will occur to power devices, QA and QB, inactive state, while the unmodulated outputs (P1A and for PWM direction change from reverse to forward. P1C) are switched to drive in the opposite direction. If changing PWM direction at high duty cycle is required This occurs in the time interval, 4TOSC * (Timer2 for an application, one of the following requirements Prescale Value), before the next PWM period begins. must be met: The Timer2 prescaler will be either 1, 4 or 16, depend- ing on the value of the T2CKPS<1:0> bits 1. Reduce PWM for a PWM period before (T2CON<1:0>). During the interval from the switch of changing directions. the unmodulated outputs to the beginning of the next 2. Use switch drivers that can drive the switches off period, the modulated outputs (P1B and P1D) remain faster than they can drive them on. inactive. This relationship is shown in Figure15-8. Other options to prevent shoot-through current may Note that in the Full-Bridge Output mode, the ECCP1 exist. module does not provide any dead-band delay. In general, since only one output is modulated at all times, dead-band delay is not required. However, there is a situation where a dead-band delay might be required. This situation occurs when both of the following conditions are true: 1. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. 2. The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. DS39682E-page 142 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY FIGURE 15-8: PWM DIRECTION CHANGE Period(1) Period SIGNAL P1A (Active-High) P1B (Active-High) DC P1C (Active-High) (Note 2) P1D (Active-High) DC Note 1: The direction bit in the ECCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals are inactive at this time. FIGURE 15-9: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A(1) P1B(1) DC P1C(1) P1D(1) DC t (2) ON External Switch C(1) t (3) OFF External Switch D(1) Potential t = t – t (2,3) OFF ON Shoot-Through Current(1) Note 1: All signals are shown as active-high. 2: t is the turn-on delay of power switch QC and its driver. ON 3: t is the turn-off delay of power switch QD and its driver. OFF © 2009 Microchip Technology Inc. DS39682E-page 143

PIC18F45J10 FAMILY 15.4.6 PROGRAMMABLE DEAD-BAND A shutdown event can be caused by either of the DELAY comparator modules, a low level on the Fault input pin (FLT0) or any combination of these three sources. The Note: Programmable dead-band delay is not comparators may be used to monitor a voltage input implemented in 28-pin devices with proportional to a current being monitored in the bridge standard CCP modules. circuit. If the voltage exceeds a threshold, the In half-bridge applications, where all power switches comparator switches state and triggers a shutdown. are modulated at the PWM frequency at all times, the Alternatively, a low digital signal on FLT0 can also trigger power switches normally require more time to turn off a shutdown. The auto-shutdown feature can be disabled than to turn on. If both the upper and lower power by not selecting any auto-shutdown sources. The auto- switches are switched at the same time (one turned on shutdown sources to be used are selected using the and the other turned off), both switches may be on for ECCPAS<2:0> bits (bits<6:4> of the ECCP1AS a short period of time until one switch completely turns register). off. During this brief interval, a very high current (shoot- When a shutdown occurs, the output pins are through current) may flow through both power asynchronously placed in their shutdown states, switches, shorting the bridge supply. To avoid this specified by the PSSAC<1:0> and PSSBD<1:0> bits potentially destructive shoot-through current from (ECCPAS<3:0>). Each pin pair (P1A/P1C and P1B/ flowing during switching, turning on either of the power P1D) may be set to drive high, drive low or be tri-stated switches is normally delayed to allow the other switch (not driving). The ECCPASE bit (ECCP1AS<7>) is also to completely turn off. set to hold the Enhanced PWM outputs in their In the Half-Bridge Output mode, a digitally programmable shutdown states. dead-band delay is available to avoid shoot-through The ECCPASE bit is set by hardware when a shutdown current from destroying the bridge power switches. The event occurs. If automatic restarts are not enabled, the delay occurs at the signal transition from the nonactive ECCPASE bit is cleared by firmware when the cause of state to the active state. See Figure15-4 for an the shutdown clears. If automatic restarts are enabled, illustration. Bits PDC<6:0> of the ECCP1DEL register the ECCPASE bit is automatically cleared when the (Register15-2) set the delay period in terms of microcon- cause of the auto-shutdown has cleared. troller instruction cycles (TCY or 4 TOSC). These bits are If the ECCPASE bit is set when a PWM period begins, not available in 28-pin devices as the standard CCP the PWM outputs remain in their shutdown state for that module does not support half-bridge operation. entire PWM period. When the ECCPASE bit is cleared, 15.4.7 ENHANCED PWM AUTO-SHUTDOWN the PWM outputs will return to normal operation at the beginning of the next PWM period. When the ECCP1 is programmed for any of the Enhanced PWM modes, the active output pins may be Note: Writing to the ECCPASE bit is disabled configured for auto-shutdown. Auto-shutdown immedi- while a shutdown condition is active. ately places the Enhanced PWM output pins into a defined shutdown state when a shutdown event occurs. REGISTER 15-2: ECCP1DEL: PWM DEAD-BAND DELAY REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM bit 6-0 PDC<6:0>: PWM Delay Count bits(1) Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for a PWM signal to transition to active. Note 1: Reserved on 28-pin devices; maintain these bits clear. DS39682E-page 144 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY REGISTER 15-3: ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in shutdown state 0 = ECCP outputs are operating bit 6-4 ECCPAS<2:0>: ECCP Auto-Shutdown Source Select bits 111 = FLT0, Comparator 1 or Comparator 2 110 = FLT0 or Comparator 2 101 = FLT0 or Comparator 1 100 = FLT0 011 = Either Comparator 1 or 2 010 = Comparator 2 output 001 = Comparator 1 output 000 = Auto-shutdown is disabled bit 3-2 PSSAC<1:0>: Pins A and C Shutdown State Control bits 1x = Pins A and C are tri-state (40/44-pin devices); PWM output is tri-state (28-pin devices) 01 = Drive Pins A and C to ‘1’ 00 = Drive Pins A and C to ‘0’ bit 1-0 PSSBD<1:0>: Pins B and D Shutdown State Control bits(1) 1x = Pins B and D tri-state 01 = Drive Pins B and D to ‘1’ 00 = Drive Pins B and D to ‘0’ Note 1: Reserved on 28-pin devices; maintain these bits clear. © 2009 Microchip Technology Inc. DS39682E-page 145

PIC18F45J10 FAMILY 15.4.7.1 Auto-Shutdown and Automatic 15.4.8 START-UP CONSIDERATIONS Restart When the ECCP module is used in the PWM mode, the The auto-shutdown feature can be configured to allow application hardware must use the proper external pull- automatic restarts of the module following a shutdown up and/or pull-down resistors on the PWM output pins. event. This is enabled by setting the PRSEN bit of the When the microcontroller is released from Reset, all of ECCP1DEL register (ECCP1DEL<7>). the I/O pins are in the high-impedance state. The external circuits must keep the power switch devices in In Shutdown mode with PRSEN = 1 (Figure15-10), the the OFF state until the microcontroller drives the I/O ECCPASE bit will remain set for as long as the cause pins with the proper signal levels, or activates the PWM of the shutdown continues. When the shutdown condi- output(s). tion clears, the ECCPASE bit is cleared. If PRSEN =0 (Figure15-11), once a shutdown condition occurs, the The CCP1M<1:0> bits (CCP1CON<1:0>) allow the ECCPASE bit will remain set until it is cleared by firm- user to choose whether the PWM output signals are ware. Once ECCPASE is cleared, the Enhanced PWM active-high or active-low for each pair of PWM output will resume at the beginning of the next PWM period. pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pins are Note: Writing to the ECCPASE bit is disabled configured as outputs. Changing the polarity configura- while a shutdown condition is active. tion while the PWM pins are configured as outputs is Independent of the PRSEN bit setting, if the auto- not recommended, since it may result in damage to the shutdown source is one of the comparators, the application circuits. shutdown condition is a level. The ECCPASE bit The P1A, P1B, P1C and P1D output latches may not be cannot be cleared as long as the cause of the shutdown in the proper states when the PWM module is initialized. persists. Enabling the PWM pins for output at the same time as The Auto-Shutdown mode can be forced by writing a ‘1’ the ECCP module may cause damage to the applica- to the ECCPASE bit. tion circuit. The ECCP module must be enabled in the proper output mode and complete a full PWM cycle before configuring the PWM pins as outputs. The com- pletion of a full PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. FIGURE 15-10: PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED) PWM Period ShutdownEvent ECCPASE bit PWM Activity Normal PWM Start of Shutdown Shutdown PWM PWM Period Event Occurs Event Clears Resumes FIGURE 15-11: PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED) PWM Period ShutdownEvent ECCPASE bit PWM Activity Normal PWM ECCPASE Cleared by Start of Shutdown Shutdown Firmware PWM PWM Period Event Occurs Event Clears Resumes DS39682E-page 146 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 15.4.9 SETUP FOR PWM OPERATION 15.4.10 OPERATION IN POWER-MANAGED MODES The following steps should be taken when configuring the ECCP module for PWM operation: In Sleep mode, all clock sources are disabled. Timer2 1. Configure the PWM pins, P1A and P1B (and will not increment and the state of the module will not P1C and P1D, if used), as inputs by setting the change. If the CCP1 pin is driving a value, it will con- corresponding TRIS bits. tinue to drive that value. When the device wakes up, it 2. Set the PWM period by loading the PR2 register. will continue from this state. If Two-Speed Start-ups are enabled, the initial start-up frequency from INTOSC 3. If auto-shutdown is required: and the postscaler may not be stable immediately. • Disable auto-shutdown (ECCPASE = 0) In PRI_IDLE mode, the primary clock will continue to • Configure source (FLT0, Comparator 1 or clock the ECCP module without change. In all other Comparator 2) power-managed modes, the selected power-managed • Wait for non-shutdown condition mode clock will clock Timer2. Other power-managed 4. Configure the ECCP module for the desired mode clocks will most likely be different than the PWM mode and configuration by loading the primary clock frequency. CCP1CON register with the appropriate values: • Select one of the available output 15.4.10.1 Operation with Fail-Safe configurations and direction with the Clock Monitor P1M<1:0> bits. If the Fail-Safe Clock Monitor is enabled, a clock failure • Select the polarities of the PWM output will force the device into the power-managed RC_RUN signals with the CCP1M<3:0> bits. mode and the OSCFIF bit (PIR2<7>) will be set. The 5. Set the PWM duty cycle by loading the CCPR1L ECCP will then be clocked from the internal oscillator register and CCP1CON<5:4> bits. clock source, which may have a different clock 6. For Half-Bridge Output mode, set the dead- frequency than the primary clock. band delay by loading ECCP1DEL<6:0> with See the previous section for additional details. the appropriate value. 7. If auto-shutdown operation is required, load the 15.4.11 EFFECTS OF A RESET ECCP1AS register: Both Power-on Reset and subsequent Resets will force • Select the auto-shutdown sources using the all ports to Input mode and the CCP registers to their ECCPAS<2:0> bits. Reset states. • Select the shutdown states of the PWM This forces the Enhanced CCP module to reset to a output pins using the PSSAC<1:0> and state compatible with the standard CCP module. PSSBD<1:0> bits. • Set the ECCPASE bit (ECCP1AS<7>). • Configure the comparators using the CMCON register. • Configure the comparator inputs as analog inputs. 8. If auto-restart operation is required, set the PRSEN bit (ECCP1DEL<7>). 9. Configure and start TMR2: • Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit (PIR1<1>). • Set the TMR2 prescale value by loading the T2CKPS bits (T2CON<1:0>). • Enable Timer2 by setting the TMR2ON bit (T2CON<2>). 10. Enable PWM outputs after a new PWM cycle has started: • Wait until TMRx overflows (TMRxIF bit is set). • Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCP1AS<7>). © 2009 Microchip Technology Inc. DS39682E-page 147

PIC18F45J10 FAMILY TABLE 15-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47 RCON IPEN — CM RI TO PD POR BOR 46 PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49 PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49 IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49 PIR2 OSCFIF CMIF — — BCL1IF — — CCP2IF 49 PIE2 OSCFIE CMIE — — BCL1IE — — CCP2IE 49 IPR2 OSCFIP CMIP — — BCL1IP — — CCP2IP 49 TRISB PORTB Data Direction Control Register 50 TRISC PORTC Data Direction Control Register 50 TRISD(1) PORTD Data Direction Control Register 50 TMR1L Timer1 Register Low Byte 48 TMR1H Timer1 Register High Byte 48 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 48 TMR2 Timer2 Register 48 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 48 PR2 Timer2 Period Register 48 CCPR1L Capture/Compare/PWM Register 1 Low Byte 49 CCPR1H Capture/Compare/PWM Register 1 High Byte 49 CCP1CON P1M1(1) P1M0(1) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 49 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1) 49 ECCP1DEL PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1) 49 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation. Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’. DS39682E-page 148 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 16.0 MASTER SYNCHRONOUS Note: In devices with more than one MSSP SERIAL PORT (MSSP) module, it is very important to pay close MODULE attention to SSPxCON register names. SSP1CON1 and SSP1CON2 control 16.1 Master SSP (MSSP) Module different operational aspects of the same Overview module, while SSP1CON1 and SSP2CON1 control the same features for The Master Synchronous Serial Port (MSSP) module is two different modules. a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral 16.3 SPI Mode devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module The SPI mode allows 8 bits of data to be synchronously can operate in one of two modes: transmitted and received simultaneously. All four modes of SPI are supported. To accomplish • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C™) communication, typically three pins are used: - Full Master mode • Serial Data Out (SDOx) – RC5/SDO1 or - Slave mode (with general address call) RD2/PSP2/SDO2 • Serial Data In (SDIx) – RC4/SDI1/SDA1 or The I2C interface supports the following modes in RD1/PSP1/SDI2/SDA2 hardware: • Serial Clock (SCKx) – RC3/SCK1/SCL1 or • Master mode RD0/PSP0/SCK2/SCL2 • Multi-Master mode Additionally, a fourth pin may be used when in a Slave • Slave mode mode of operation: PIC18F24J10/25J10 (28-pin) devices have one MSSP • Slave Select (SSx) – RA5/AN4/SS1/C2OUT or module designated as MSSP1. PIC18F44J10/45J10 RD3/PSP3/SS2 (40/44-pin) devices have two MSSP modules, designated as MSSP1 and MSSP2. Each module Figure16-1 shows the block diagram of the MSSP operates independently of the other. module when operating in SPI mode. Note: Throughout this section, generic refer- FIGURE 16-1: MSSP BLOCK DIAGRAM ences to an MSSP module in any of its (SPIMODE) operating modes may be interpreted as Internal being equally applicable to MSSP1 or Data Bus MSSP2. Register names and module I/O Read Write signals use the generic designator ‘x’ to indicate the use of a numeral to distinguish SSPxBUF reg a particular module, when required. Control bit names are not individuated. SDIx SSPxSR reg 16.2 Control Registers Shift SDOx bit 0 Clock Each MSSP module has three associated control registers. These include a status register (SSPxSTAT) and two control registers (SSPxCON1 and SSPxCON2). The use of these registers and their individual configura- SSx SSx Control tion bits differ significantly depending on whether the Enable MSSP module is operated in SPI or I2C mode. Edge Select Additional details are provided under the individual sections. 2 Clock Select Note: Disabling the MSSP module by clearing SSPM<3:0> the SSPEN (SSPxCON1<5>) bit may not SMP:CKE 4 (T M R 2 O u tp u t) reset the module. It is recommended to 2 2 clear the SSPxSTAT, SSPxCON1 and Edge SSPxCON2 registers and select the mode Select Prescaler TOSC SCKx 4, 16, 64 prior to setting the SSPEN bit to enable Data to TX/RX in SSPxSR the MSSP module. TRIS bit Note: Only port I/O names are used in this diagram for the sake of brevity. Refer to the text for a full list of multiplexed functions. © 2009 Microchip Technology Inc. DS39682E-page 149

PIC18F45J10 FAMILY 16.3.1 REGISTERS SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data Each MSSP module has four registers for SPI mode bytes are written to or read from. operation. These are: In receive operations, SSPxSR and SSPxBUF • MSSP Control Register 1 (SSPxCON1) together create a double-buffered receiver. When • MSSP Status Register (SSPxSTAT) SSPxSR receives a complete byte, it is transferred to • Serial Receive/Transmit Buffer Register SSPxBUF and the SSPxIF interrupt is set. (SSPxBUF) During transmission, the SSPxBUF is not • MSSP Shift Register (SSPxSR) – Not directly double-buffered. A write to SSPxBUF will write to both accessible SSPxBUF and SSPxSR. SSPxCON1 and SSPxSTAT are the control and status registers in SPI mode operation. The SSPxCON1 register is readable and writable. The lower 6 bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. REGISTER 16-1: SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE(1) D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Select bit(1) 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state bit 5 D/A: Data/Address bit Used in I2C mode only. bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write Information bit Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Note 1: Polarity of clock state is set by the CKP bit (SSPxCON1<4>). DS39682E-page 150 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY REGISTER 16-2: SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) SPI Slave mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow bit 5 SSPEN: Master Synchronous Serial Port Enable bit(2) 1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(3) 0101 = SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin 0100 = SPI Slave mode, clock = SCKx pin, SSx pin control enabled 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only. © 2009 Microchip Technology Inc. DS39682E-page 151

PIC18F45J10 FAMILY 16.3.2 OPERATION SSPxBUF register during transmission/reception of data will be ignored and the Write Collision detect bit, WCOL When initializing the SPI, several options need to be (SSPxCON1<7>), will be set. User software must clear specified. This is done by programming the appropriate the WCOL bit so that it can be determined if the following control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). write(s) to the SSPxBUF register completed These control bits allow the following to be specified: successfully. • Master mode (SCKx is the clock output) When the application software is expecting to receive • Slave mode (SCKx is the clock input) valid data, the SSPxBUF should be read before the next • Clock Polarity (Idle state of SCKx) byte of data to transfer is written to the SSPxBUF. The • Data Input Sample Phase (middle or end of data Buffer Full bit, BF (SSPxSTAT<0>), indicates when output time) SSPxBUF has been loaded with the received data • Clock Edge (output data on rising/falling edge of (transmission is complete). When the SSPxBUF is read, SCKx) the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt • Clock Rate (Master mode only) is used to determine when the transmission/reception • Slave Select mode (Slave mode only) has completed. The SSPxBUF must be read and/or Each MSSP consists of a transmit/receive shift register written. If the interrupt method is not going to be used, (SSPxSR) and a buffer register (SSPxBUF). The then software polling can be done to ensure that a write SSPxSR shifts the data in and out of the device, MSb collision does not occur. Example16-1 shows the first. The SSPxBUF holds the data that was written to the loading of the SSP1BUF (SSP1SR) for data SSPxSR until the received data is ready. Once the 8 bits transmission. of data have been received, that byte is moved to the The SSPxSR is not directly readable or writable and SSPxBUF register. Then, the Buffer Full detect bit, BF can only be accessed by addressing the SSPxBUF (SSPxSTAT<0>), and the interrupt flag bit, SSPxIF, are register. Additionally, the SSPxSTAT register indicates set. This double-buffering of the received data the various status conditions. (SSPxBUF) allows the next byte to start reception before reading the data that was just received. Any write to the EXAMPLE 16-1: LOADING THE SSP1BUF (SSP1SR) REGISTER LOOP BTFSS SSP1STAT, BF ;Has data been received (transmit complete)? BRA LOOP ;No MOVF SSP1BUF, W ;WREG reg = contents of SSP1BUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA, W ;W reg = contents of TXDATA MOVWF SSP1BUF ;New data to xmit DS39682E-page 152 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 16.3.3 ENABLING SPI I/O Any serial port function that is not desired may be overridden by programming the corresponding data To enable the serial port, MSSP Enable bit, SSPEN direction (TRIS) register to the opposite value. (SSPxCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the 16.3.4 TYPICAL CONNECTION SSPxCON registers and then set the SSPEN bit. This configures the SDIx, SDOx, SCKx and SSx pins as Figure16-2 shows a typical connection between two serial port pins. For the pins to behave as the serial port microcontrollers. The master controller (Processor 1) function, some must have their data direction bits (in initiates the data transfer by sending the SCKx signal. the TRIS register) appropriately programmed as Data is shifted out of both shift registers on their pro- follows: grammed clock edge and latched on the opposite edge of the clock. Both processors should be programmed to • SDIx is automatically controlled by the SPI module the same Clock Polarity (CKP), then both controllers • SDOx must have TRISC<5> (or TRISD<2>) bit would send and receive data at the same time. cleared Whether the data is meaningful (or dummy data) • SCKx (Master mode) must have TRISC<3> (or depends on the application software. This leads to TRISD<0>) bit cleared three scenarios for data transmission: • SCKx (Slave mode) must have TRISC<3> (or • Master sends data – Slave sends dummy data TRISD<0>) bit set • Master sends data – Slave sends data • SSx must have TRISA<5> (or TRISD<3>) bit set • Master sends dummy data – Slave sends data FIGURE 16-2: SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xxb SPI Slave SSPM<3:0> = 010xb SDOx SDIx Serial Input Buffer Serial Input Buffer (SSPxBUF) (SSPxBUF) SDIx SDOx Shift Register Shift Register (SSPxSR) (SSPxSR) MSb LSb MSb LSb Serial Clock SCKx SCKx PROCESSOR 1 PROCESSOR 2 © 2009 Microchip Technology Inc. DS39682E-page 153

PIC18F45J10 FAMILY 16.3.5 MASTER MODE The clock polarity is selected by appropriately programming the CKP bit (SSPxCON1<4>). This then, The master can initiate the data transfer at any time would give waveforms for SPI communication as because it controls the SCKx. The master determines shown in Figure16-3, Figure16-5 and Figure16-6, when the slave (Processor 2, Figure16-2) will where the MSB is transmitted first. In Master mode, the broadcast data by the software protocol. SPI clock rate (bit rate) is user-programmable to be one In Master mode, the data is transmitted/received as of the following: soon as the SSPxBUF register is written to. If the SPI • FOSC/4 (or TCY) is only going to receive, the SDOx output could be dis- abled (programmed as an input). The SSPxSR register • FOSC/16 (or 4 • TCY) will continue to shift in the signal present on the SDIx • FOSC/64 (or 16 • TCY) pin at the programmed clock rate. As each byte is • Timer2 output/2 received, it will be loaded into the SSPxBUF register as This allows a maximum data rate (at 40MHz) of if a normal received byte (interrupts and status bits 10.00Mbps. appropriately set). This could be useful in receiver applications as a “Line Activity Monitor” mode. Figure16-3 shows the waveforms for Master mode. When the CKE bit is set, the SDOx data is valid before there is a clock edge on SCKx. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown. FIGURE 16-3: SPI MODE WAVEFORM (MASTER MODE) Write to SSPxBUF SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) 4 Clock Modes SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDIx (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDIx (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPxIF Next Q4 Cycle SSPxSR to after Q2↓ SSPxBUF DS39682E-page 154 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 16.3.6 SLAVE MODE SDOx pin is driven. When the SSx pin goes high, the SDOx pin is no longer driven, even if in the middle of a In Slave mode, the data is transmitted and received as transmitted byte and becomes a floating output. the external clock pulses appear on SCKx. When the External pull-up/pull-down resistors may be desirable last bit is latched, the SSPxIF interrupt flag bit is set. depending on the application. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock Note 1: When the SPI is in Slave mode with SSx pin line can be observed by reading the SCKx pin. The Idle control enabled (SSPxCON1<3:0>=0100), state is determined by the CKP bit (SSPxCON1<4>). the SPI module will reset if the SSx pin is set to VDD. While in Slave mode, the external clock is supplied by the external clock source on the SCKx pin. This 2: If the SPI is used in Slave mode with CKE external clock must meet the minimum high and low set, then the SSx pin control must be times as specified in the electrical specifications. enabled. While in Sleep mode, the slave can transmit/receive When the SPI module resets, the bit counter is forced data. When a byte is received, the device will wake-up to ‘0’. This can be done by either forcing the SSx pin to from Sleep. a high level or clearing the SSPEN bit. To emulate two-wire communication, the SDOx pin can 16.3.7 SLAVE SELECT be connected to the SDIx pin. When the SPI needs to SYNCHRONIZATION operate as a receiver, the SDOx pin can be configured The SSx pin allows a Synchronous Slave mode. The as an input. This disables transmissions from the SPI must be in Slave mode with SSx pin control SDOx. The SDIx can always be left as an input (SDIx enabled (SSPxCON1<3:0> = 04h). When the SSx pin function) since it cannot create a bus conflict. is low, transmission and reception are enabled and the FIGURE 16-4: SLAVE SYNCHRONIZATION WAVEFORM SSx SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx bit 7 bit 6 bit 7 bit 0 SDIx bit 0 (SMP = 0) bit 7 bit 7 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle SSPxSR to after Q2↓ SSPxBUF © 2009 Microchip Technology Inc. DS39682E-page 155

PIC18F45J10 FAMILY FIGURE 16-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle SSPxSR to after Q2↓ SSPxBUF FIGURE 16-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle after Q2↓ SSPxSR to SSPxBUF DS39682E-page 156 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 16.3.8 OPERATION IN POWER-MANAGED 16.3.10 BUS MODE COMPATIBILITY MODES Table16-1 shows the compatibility between the In SPI Master mode, module clocks may be operating standard SPI modes and the states of the CKP and at a different speed than when in Full-Power mode; in CKE control bits. the case of Sleep mode, all clocks are halted. TABLE 16-1: SPI BUS MODES In Idle modes, a clock is provided to the peripherals. That clock should be from the primary clock source, the Control Bits State Standard SPI Mode secondary clock (Timer1 oscillator at 32.768 kHz) or Terminology CKP CKE the INTOSC source. See Section3.6 “Clock Sources and Oscillator Switching” for additional information. 0, 0 0 1 In most cases, the speed that the master clocks SPI 0, 1 0 0 data is not important; however, this should be 1, 0 1 1 evaluated for each system. 1, 1 1 0 If MSSP interrupts are enabled, they can wake the con- There is also an SMP bit which controls when the data troller from Sleep mode, or one of the Idle modes, when is sampled. the master completes sending data. If an exit from Sleep or Idle mode is not desired, MSSP interrupts 16.3.11 SPI CLOCK SPEED AND MODULE should be disabled. INTERACTIONS If the Sleep mode is selected, all module clocks are Because MSSP1 and MSSP2 are independent halted and the transmission/reception will remain in modules, they can operate simultaneously at different that state until the devices wakes. After the device data rates. Setting the SSPM<3:0> bits of the returns to Run mode, the module will resume SSPxCON1 register determines the rate for the transmitting and receiving data. corresponding module. In SPI Slave mode, the SPI Transmit/Receive Shift An exception is when both modules use Timer2 as a register operates asynchronously to the device. This time base in Master mode. In this instance, any allows the device to be placed in any power-managed changes to the Timer2 operation will affect both MSSP mode and data to be shifted into the SPI modules equally. If different bit rates are required for Transmit/Receive Shift register. When all 8 bits have each module, the user should select one of the other been received, the MSSP interrupt flag bit will be set three time base options for one of the modules. and if enabled, will wake the device. 16.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. © 2009 Microchip Technology Inc. DS39682E-page 157

PIC18F45J10 FAMILY TABLE 16-2: REGISTERS ASSOCIATED WITH SPI OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47 PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49 PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49 IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49 PIR3 SSP2IF BCL2IF — — — — — — 49 PIE3 SSP2IE BCL2IE — — — — — — 49 IPR3 SSP2IP BCL2IP — — — — — — 49 TRISA — — TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 50 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 50 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 50 SSP1BUF MSSP1 Receive Buffer/Transmit Register 48 SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 48 SSP1STAT SMP CKE D/A P S R/W UA BF 48 SSP2BUF MSSP2 Receive Buffer/Transmit Register 50 SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 50 SSP2STAT SMP CKE D/A P S R/W UA BF 50 Legend: Shaded cells are not used by the MSSP module in SPI mode. Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’. DS39682E-page 158 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 16.4 I2C Mode 16.4.1 REGISTERS The MSSP module in I2C mode fully implements all The MSSP module has six registers for I2C operation. master and slave functions (including general call These are: support) and provides interrupts on Start and Stop bits • MSSP Control Register 1 (SSPxCON1) in hardware to determine a free bus (multi-master • MSSP Control Register 2 (SSPxCON2) function). The MSSP module implements the standard • MSSP Status Register (SSPxSTAT) mode specifications, as well as 7-bit and 10-bit • Serial Receive/Transmit Buffer Register addressing. (SSPxBUF) Two pins are used for data transfer: • MSSP Shift Register (SSPxSR) – Not directly • Serial clock (SCLx) – RC3/SCK1/SCL1 or accessible RD6/SCK2/SCL2 • MSSP Address Register (SSPxADD) • Serial data (SDAx) – RC4/SDI1/SDA1 or SSPxCON1, SSPxCON2 and SSPxSTAT are the RD5/SDI2/SDA2 control and status registers in I2C mode operation. The The user must configure these pins as inputs by setting SSPxCON1 and SSPxCON2 registers are readable the associated TRIS bits. and writable. The lower 6 bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are FIGURE 16-7: MSSP BLOCK DIAGRAM read/write. (I2C™ MODE) Many of the bits in SSPxCON2 assume different functions, depending on whether the module is operat- Internal ing in Master or Slave mode; bits<5:2> also assume Data Bus different names in Slave mode. The different aspects of Read Write SSPxCON2 are shown in Register16-5 (for Master mode) and Register16-6 (Slave mode). SSPxBUF reg SCLx SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data bytes Shift are written to or read from. Clock SSPxADD register holds the slave device address SSPxSR reg when the MSSP is configured in I2C Slave mode. When SDAx MSb LSb the MSSP is configured in Master mode, the lower seven bits of SSPxADD act as the Baud Rate Match Detect Addr Match Generator reload value. Address Mask In receive operations, SSPxSR and SSPxBUF together create a double-buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF SSPxADD reg and the SSPxIF interrupt is set. During transmission, the SSPxBUF is not double-buffered. A write to SSPxBUF will write to both Start and Set, Reset SSPxBUF and SSPxSR. Stop bit Detect S, P bits (SSPxSTAT reg) Note: Disabling the MSSP module by clearing the SSPEN (SSPxCON1<5>) bit may not Note: Only port I/O names are used in this diagram for reset the module. It is recommended to the sake of brevity. Refer to the text for a full list of clear the SSPxSTAT, SSPxCON1 and multiplexed functions. SSPxCON2 registers and select the mode prior to setting the SSPEN bit to enable the MSSP module. © 2009 Microchip Technology Inc. DS39682E-page 159

PIC18F45J10 FAMILY REGISTER 16-3: SSPxSTAT: MSSPx STATUS REGISTER (I2C™ MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R0 R-0 SMP CKE D/A P(1) S(1) R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit(1) 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last bit 3 S: Start bit(1) 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last bit 2 R/W: Read/Write Information bit (I2C mode only) In Slave mode:(2) 1 = Read 0 = Write In Master mode:(3) 1 = Transmit is in progress 0 = Transmit is not in progress bit 1 UA: Update Address bit (10-Bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = SSPxBUF is full 0 = SSPxBUF is empty In Receive mode: 1 = SSPxBUF is full (does not include the ACK and Stop bits) 0 = SSPxBUF is empty (does not include the ACK and Stop bits) Note 1: This bit is cleared on Reset and when SSPEN is cleared. 2: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode. DS39682E-page 160 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY REGISTER 16-4: SSPxCON1: MSSPx CONTROL REGISTER 1 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN(1) CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a “don’t care” bit. bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a “don’t care” bit in Transmit mode. bit 5 SSPEN: Master Synchronous Serial Port Enable bit(1) 1 = Enables the serial port and configures the SDAx and SCLx pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: SCK Release Control bit In Slave mode: 1 = Release clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode. bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (slave Idle) 1000 = I2C Master mode, clock = FOSC/(4 * (SSPxADD + 1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. Note 1: When enabled, the SDAx and SCLx pins must be configured as inputs. © 2009 Microchip Technology Inc. DS39682E-page 161

PIC18F45J10 FAMILY REGISTER 16-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ MASTER MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit Unused in Master mode. bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(1) 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit(2) 1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (Master Receive mode only)(2) 1 = Enables Receive mode for I2C 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit(2) 1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit(2) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable bit(2) 1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Start condition Idle Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. 2: If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). DS39682E-page 162 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY REGISTER 16-6: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ SLAVE MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 SEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit 1 = Enable interrupt when a general call address (0000h) is received in the SSPxSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit Unused in Slave mode. bit 5-2 ADMSK<5:2>: Slave Address Mask Select bits 1 = Masking of corresponding bits of SSPxADD enabled 0 = Masking of corresponding bits of SSPxADD disabled bit 1 ADMSK1: Slave Address Least Significant bit(s) Mask Select bit In 7-Bit Addressing mode: 1 = Masking of SSPxADD<1> only enabled 0 = Masking of SSPxADD<1> only disabled In 10-Bit Addressing mode: 1 = Masking of SSPxADD<1:0> enabled 0 = Masking of SSPxADD<1:0> disabled bit 0 SEN: Stretch Enable bit(1) 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: If the I2C module is active, this bit may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). © 2009 Microchip Technology Inc. DS39682E-page 163

PIC18F45J10 FAMILY 16.4.2 OPERATION The SCLx clock input must have a minimum high and low for proper operation. The high and low times of the The MSSP module functions are enabled by setting the I2C specification, as well as the requirement of the MSSP Enable bit, SSPEN (SSPxCON1<5>). MSSP module, are shown in timing parameter 100 and The SSPxCON1 register allows control of the I2C parameter 101. operation. Four mode selection bits (SSPxCON1<3:0>) allow one of the following I2C 16.4.3.1 Addressing modes to be selected: Once the MSSP module has been enabled, it waits for • I2C Master mode, a Start condition to occur. Following the Start condition, clock = (FOSC/4) x (SSPxADD+1) the 8 bits are shifted into the SSPxSR register. All • I2C Slave mode (7-bit address) incoming bits are sampled with the rising edge of the • I2C Slave mode (10-bit address) clock (SCLx) line. The value of register SSPxSR<7:1> is compared to the value of the SSPxADD register. The • I2C Slave mode (7-bit address) with Start and address is compared on the falling edge of the eighth Stop bit interrupts enabled clock (SCLx) pulse. If the addresses match and the BF • I2C Slave mode (10-bit address) with Start and and SSPOV bits are clear, the following events occur: Stop bit interrupts enabled 1. The SSPxSR register value is loaded into the • I2C Firmware Controlled Master mode, SSPxBUF register. slave is Idle 2. The Buffer Full bit, BF, is set. Selection of any I2C mode, with the SSPEN bit set, 3. An ACK pulse is generated. forces the SCLx and SDAx pins to be open-drain, 4. The MSSP Interrupt Flag bit, SSPxIF, is set (and provided these pins are programmed to inputs by interrupt is generated, if enabled) on the falling setting the appropriate TRISC or TRISD bits. To ensure edge of the ninth SCLx pulse. proper operation of the module, pull-up resistors must be provided externally to the SCLx and SDAx pins. In 10-Bit Addressing mode, two address bytes need to be received by the slave. The five Most Significant bits 16.4.3 SLAVE MODE (MSbs) of the first address byte specify if this is a 10-bit In Slave mode, the SCLx and SDAx pins must be address. Bit R/W (SSPxSTAT<2>) must specify a write configured as inputs (TRISC<4:3> set). The MSSP so the slave device will receive the second address byte. module will override the input state with the output data For a 10-bit address, the first byte would equal ‘11110 when required (slave-transmitter). A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the address. The sequence of events for 10-Bit Addressing The I2C Slave mode hardware will always generate an mode is as follows, with steps 7 through 9 for the interrupt on an exact address match. In addition, slave-transmitter: address masking will also allow the hardware to gener- ate an interrupt for more than one address (up to 31 in 1. Receive first (high) byte of address (bits, 7-bit addressing and up to 63 in 10-bit addressing). SSPxIF, BF and UA (SSPxSTAT<1>), are set). Through the mode select bits, the user can also choose 2. Update the SSPxADD register with second (low) to interrupt on Start and Stop bits. byte of address (clears bit, UA, and releases the SCLx line). When an address is matched, or the data transfer after an address match is received, the hardware auto- 3. Read the SSPxBUF register (clears bit, BF) and matically will generate the Acknowledge (ACK) pulse clear flag bit, SSPxIF. and load the SSPxBUF register with the received value 4. Receive second (low) byte of address (bits, currently in the SSPxSR register. SSPxIF, BF and UA, are set). Any combination of the following conditions will cause 5. Update the SSPxADD register with the first the MSSP module not to give this ACK pulse: (high) byte of address. If match releases SCLx line, this will clear bit, UA. • The Buffer Full bit, BF (SSPxSTAT<0>), was set 6. Read the SSPxBUF register (clears bit, BF) and before the transfer was received. clear flag bit, SSPxIF. • The MSSP Overflow bit, SSPOV 7. Receive Repeated Start condition. (SSPxCON1<6>), was set before the transfer was received. 8. Receive first (high) byte of address (bits, SSPxIF and BF, are set). In this case, the SSPxSR register value is not loaded 9. Read the SSPxBUF register (clears bit, BF) and into the SSPxBUF, but the SSPxIF bit is set. The BF bit clear flag bit, SSPxIF. is cleared by reading the SSPxBUF register, while the SSPOV bit is cleared through software. DS39682E-page 164 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 16.4.3.2 Address Masking For the module to issue an address Acknowledge, it is sufficient to match only on addresses that do not have an Masking an address bit causes that bit to become a active address mask. “don’t care”. When one address bit is masked, two addresses will be Acknowledged and cause an In 10-Bit Addressing mode, ADMSK<5:2> bits mask interrupt. It is possible to mask more than one address the corresponding address bits in the SSPxADD regis- bit at a time, which makes it possible to Acknowledge ter. In addition, ADMSK1 simultaneously masks the two up to 31 addresses in 7-Bit Addressing mode and up to LSbs of the address (SSPxADD<1:0>). For any 63addresses in 10-Bit Addressing mode (see ADMSK bits that are active (ADMSK<n>=1), the cor- Example16-2). responding address bit is ignored (SSPxADD<n>=x). The I2C Slave behaves the same way, whether Also note that although in 10-Bit Addressing mode, the upper address bits reuse part of the SSPxADD register address masking is used or not. However, when address masking is used, the I2C slave can bits, the address mask bits do not interact with those bits. They only affect the lower address bits. Acknowledge multiple addresses and cause interrupts. When this occurs, it is necessary to determine which Note1: ADMSK1 masks the two Least Significant address caused the interrupt by checking SSPxBUF. bits of the address. In 7-Bit Addressing mode, Address Mask bits, 2: The two Most Significant bits of the ADMSK<5:1> (SSPxCON2<5:1>), mask the address are not affected by address corresponding address bits in the SSPxADD register. For masking. any ADMSK bits that are set (ADMSK<n>=1), the cor- responding address bit is ignored (SSPxADD<n>=x). EXAMPLE 16-2: ADDRESS MASKING EXAMPLES 7-Bit Addressing: SSPxADD<7:1>= A0h (1010000) (SSPxADD<0> is assumed to be ‘0’) ADMSK<5:1> = 00111 Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh 10-Bit Addressing: SSPxADD<7:0>= A0h (10100000) (the two MSbs of the address are ignored in this example, since they are not affected by masking) ADMSK<5:1> = 00111 Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh © 2009 Microchip Technology Inc. DS39682E-page 165

PIC18F45J10 FAMILY 16.4.3.3 Reception 16.4.3.4 Transmission When the R/W bit of the address byte is clear and an When the R/W bit of the incoming address byte is set address match occurs, the R/W bit of the SSPxSTAT and an address match occurs, the R/W bit of the register is cleared. The received address is loaded into SSPxSTAT register is set. The received address is the SSPxBUF register and the SDAx line is held low loaded into the SSPxBUF register. The ACK pulse will (ACK). be sent on the ninth bit and pin RC3 or RD6 is held low, regardless of SEN (see Section16.4.4 “Clock When the address byte overflow condition exists, then Stretching” for more details). By stretching the clock, the no Acknowledge (ACK) pulse is given. An overflow the master will be unable to assert another clock pulse condition is defined as either bit, BF (SSPxSTAT<0>), until the slave is done preparing the transmit data. The is set, or bit, SSPOV (SSPxCON1<6>), is set. transmit data must be loaded into the SSPxBUF regis- An MSSP interrupt is generated for each data transfer ter which also loads the SSPxSR register. Then pin byte. The interrupt flag bit, SSPxIF, must be cleared in RC3 or RD0 should be enabled by setting bit, CKP software. The SSPxSTAT register is used to determine (SSPxCON1<4>). The eight data bits are shifted out on the status of the byte. the falling edge of the SCLx input. This ensures that the If SEN is enabled (SSPxCON2<0> = 1), SCKx/SCLx SDAx signal is valid during the SCLx high time (RC3 or RD0) will be held low (clock stretch) following (Figure16-9). each data transfer. The clock must be released by The ACK pulse from the master-receiver is latched on setting bit, CKP (SSPxCON1<4>). See Section16.4.4 the rising edge of the ninth SCLx input pulse. If the “Clock Stretching” for more details. SDAx line is high (not ACK), then the data transfer is complete. In this case, when the ACK is latched by the slave, the slave logic is reset (resets SSPxSTAT register) and the slave monitors for another occurrence of the Start bit. If the SDAx line was low (ACK), the next transmit data must be loaded into the SSPxBUF regis- ter. Again, pin RC3 or RD0 must be enabled by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared in software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse. DS39682E-page 166 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 2 FIGURE 16-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESSING) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R 5 D 3 D6 2 7 D 1 K C A 9 0 D 8 1 D 7 D2 6 a 3 at D 5 D e eceiving D4 4 n softwarF is read R D6D5 23 Cleared iSSPxBU 7 D 1 = 0 ACK 9 W 8 R/ A1 7 A2 6 = )0 ddress A3 5 n SEN A e Receiving A5A4 34 eset to ‘’ wh0 SDAxA7A6 SCLx12S SSPxIF (PIR1<3> or PIR3<7>) BF (SSPxSTAT<0>) SSPOV (SSPxCON1<6>) CKP(CKP does not r © 2009 Microchip Technology Inc. DS39682E-page 167

PIC18F45J10 FAMILY 2 FIGURE 16-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESSING) P R S K F I AC 9 PxI S D0 8 m S o Data D1 7 Fr Transmitting D5D4D3D2 3456 eared in software UF is written in software et in software D6 2 Cl SSPxB KP is s C D7 1 R S ACK 9 PxIF I S S D0 8 m o Fr D1 7 Transmitting Data D6D7D5D4D3D2 234561 SCLx held lowwhile CPUresponds to SSPxIF Cleared in software SSPxBUF is written in software Clear by reading CKP is set in software K C A 9 0 = W 8 R/ 1 A 7 ess A2 6 Addr A3 5 g n eivi A4 4 ec R A5 3 >) 7 A6A7 12 Data in sampled > or PIR3< 0>) <4>) 3 < N DAx CLx S SPxIF (PIR1< F (SSPxSTAT KP (SSPxCO S S S B C DS39682E-page 168 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY FIGURE 16-10: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESSING) ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 e Byte 3D2 6 softwar a D 5 n ceive Dat D5D4 34 Cleared i e R D6 2 7 D 1 K AC 9 0 D 8 untilDD has Receive Data Byte D6D5D4D3D1D2 234576 Cleared in software Cleared by hardware whenSSPxADD is updated with highbyte of address d low SPxA D7 1 Clock is helupdate of Staken place ACK0 89 A Clock is held low untilupdate of SSPxADD has taken place Receive First Byte of AddressReceive Second Byte of AddressR/W = 0 ACKDAx11110A9A8A7A6A5A4A3A2A1 CLx1234567891234567S SPxIF (PIR1<3> or PIR3<7>) Cleared in softwareCleared in software F (SSPxSTAT<0>) SSPxBUF is written withDummy read of SSPxBUFcontents of SSPxSRto clear BF flag SPOV (SSPxCON1<6>) A (SSPxSTAT<1>) UA is set indicating thatCleared by hardwarethe SSPxADD needs to bewhen SSPxADD is updatedupdatedwith low byte of address UA is set indicating thatSSPxADD needs to beupdated KP(CKP does not reset to ‘’ when SEN = )00 S S S B S U C © 2009 Microchip Technology Inc. DS39682E-page 169

PIC18F45J10 FAMILY 2 FIGURE 16-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESSING) Bus masterterminatestransfer ACK D0 89P Completion ofdata transmissionclears BF flag are, holding SCLx low w Clock is held low untilupdate of SSPxADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive First Byte of AddressR/W = Transmitting Data Byte1 ACK11110A8A9D7D6D5D4D3D1D2ACK 91234578961234576Sr Cleared in softwareCleared in software Dummy read of SSPxBUFWrite of SSPxBUFBF flag is clearto clear BF flaginitiates transmitat the end of thethird address sequence Cleared by hardware whenSSPxADD is updated with highbyte of address. CKP is set in software CKP is automatically cleared in hard Clock is held low untilupdate of SSPxADD has taken place W = 0Receive Second Byte of Address A7A6A5A4A3A2A1A0ACK 912345678 Cleared in software Dummy read of SSPxBUFto clear BF flag Cleared by hardware whenSSPxADD is updated with lowbyte of address UA is set indicating thatSSPxADD needs to beupdated R/ 8 h be Receive First Byte of Address DAx11110A9A8 CLx1234567S SPxIF (PIR1<3> or PIR3<7>) F (SSPxSTAT<0>) SSPxBUF is written witcontents of SSPxSR A (SSPxSTAT<1>) UA is set indicating thatthe SSPxADD needs to updated KP (SSPxCON1<4>) S S S B U C DS39682E-page 170 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 16.4.4 CLOCK STRETCHING 16.4.4.3 Clock Stretching for 7-Bit Slave Transmit Mode Both 7-Bit and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The 7-Bit Slave Transmit mode implements clock The SEN bit (SSPxCON2<0>) allows clock stretching stretching by clearing the CKP bit after the falling edge of the ninth clock, if the BF bit is clear. This occurs to be enabled during receives. Setting SEN will cause the SCLx pin to be held low at the end of each data regardless of the state of the SEN bit. receive sequence. The user’s ISR must set the CKP bit before transmis- sion is allowed to continue. By holding the SCLx line 16.4.4.1 Clock Stretching for 7-Bit Slave low, the user has time to service the ISR and load the Receive Mode (SEN = 1) contents of the SSPxBUF before the master device In 7-Bit Slave Receive mode, on the falling edge of the can initiate another transmit sequence (see ninth clock at the end of the ACK sequence, if the BF Figure16-9). bit is set, the CKP bit in the SSPxCON1 register is Note1: If the user loads the contents of automatically cleared, forcing the SCLx output to be SSPxBUF, setting the BF bit before the held low. The CKP being cleared to ‘0’ will assert the falling edge of the ninth clock, the CKP bit SCLx line low. The CKP bit must be set in the user’s will not be cleared and clock stretching ISR before reception is allowed to continue. By holding will not occur. the SCLx line low, the user has time to service the ISR 2: The CKP bit can be set in software and read the contents of the SSPxBUF before the regardless of the state of the BF bit. master device can initiate another receive sequence. This will prevent buffer overruns from occurring (see Figure16-13). 16.4.4.4 Clock Stretching for 10-Bit Slave Transmit Mode Note1: If the user reads the contents of the SSPxBUF before the falling edge of the In 10-Bit Slave Transmit mode, clock stretching is con- ninth clock, thus clearing the BF bit, the trolled during the first two address sequences by the CKP bit will not be cleared and clock state of the UA bit, just as it is in 10-bit Slave Receive stretching will not occur. mode. The first two addresses are followed by a third address sequence which contains the high-order bits 2: The CKP bit can be set in software of the 10-bit address and the R/W bit set to ‘1’. After regardless of the state of the BF bit. The the third address sequence is performed, the UA bit is user should be careful to clear the BF bit not set, the module is now configured in Transmit in the ISR before the next receive mode and clock stretching is controlled by the BF flag sequence in order to prevent an overflow as in 7-Bit Slave Transmit mode (see Figure16-11). condition. 16.4.4.2 Clock Stretching for 10-Bit Slave Receive Mode (SEN = 1) In 10-Bit Slave Receive mode during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to ‘0’. The release of the clock line occurs upon updating SSPxADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPxADD register before the falling edge of the ninth clock occurs and if the user hasn’t cleared the BF bit by read- ing the SSPxBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. © 2009 Microchip Technology Inc. DS39682E-page 171

PIC18F45J10 FAMILY 16.4.4.5 Clock Synchronization and already asserted the SCLx line. The SCLx output will the CKP bit remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCLx. This When the CKP bit is cleared, the SCLx output is forced ensures that a write to the CKP bit will not violate the to ‘0’. However, clearing the CKP bit will not assert the minimum high time requirement for SCLx (see SCLx output low until the SCLx output is already sam- Figure16-12). pled low. Therefore, the CKP bit will not assert the SCLx line until an external I2C master device has FIGURE 16-12: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDAx DX DX – 1 SCLx Master Device CKP Asserts Clock Master Device Deasserts Clock WR SSPxCON DS39682E-page 172 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 2 FIGURE 16-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESSING) w Clock is not held lobecause ACK = 1 ACK 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D0 8 1 D 7 D2 6 ata D3 5 D g eivin D4 4 c e R D5 3 e Clock is held low untilCKP is set to ‘’1 ACK D0D7D6 8912 CKPwrittento ‘’ in1softwarBF is set after falling edge of the 9th clock,CKP is reset to ‘’ and0clock stretching occurs 1 D 7 D2 6 Clock is not held lowbecause buffer full bit is clear prior to falling edge of 9th clock Receiving Data D7D6D5D4D3 12345 Cleared in software SPxBUF is read If BF is clearedprior to the fallingedge of the 9th clock,CKP will not be resetto ‘’ and no clock0stretching will occur S K 9 0 C = A W 8 R/ A1 7 A2 6 s s e ddr A3 5 A g eivin A4 4 c e R A5 3 >) A6 2 R3<7 >) A7 1 > or PI 0>) ON1<6 DAx CLxS SPxIF (PIR1<3 F (SSPxSTAT< SPOV (SSPxC KP S S S B S C © 2009 Microchip Technology Inc. DS39682E-page 173

PIC18F45J10 FAMILY FIGURE 16-14: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESSING) Clock is not held lowbecause ACK = 1 ACK 0 9P Bus masterterminatestransfer SSPOV is setbecause SSPxBUF isstill full. ACK is not sent. D 8 1 D 7 e Clock is held low untilupdate of SSPxADD has Clock is held low untiltaken placeCKP is set to ‘’1 Receive Data ByteReceive Data Byte ACKD7D6D5D4D3D1D0D2D7D6D5D4D3D2 123457896123456 Cleared in softwareCleared in softwar Dummy read of SSPxBUFto clear BF flag Cleared by hardware whenSSPxADD is updated with highbyte of address after falling edgeof ninth clock CKP written to ‘’1in software Note:An update of the SSPxADD register before thefalling edge of the ninth clock will have no effecton UA and UA will remain set. K C 9 A Clock is held low untilupdate of SSPxADD has taken place Receive First Byte of AddressReceive Second Byte of AddressR/W = 0 DAx11110A9A8A7A6A5A4A3A2A1A0ACK CLx12345678912345678S SPxIF (PIR1<3> or PIR3<7>) Cleared in softwareCleared in software F (SSPxSTAT<0>) SSPxBUF is written withDummy read of SSPxBUFcontents of SSPxSRto clear BF flag SPOV (SSPxCON1<6>) A (SSPxSTAT<1>) UA is set indicating thatCleared by hardware whenthe SSPxADD needs to beSSPxADD is updated with lowupdatedbyte of address after falling edgeof ninth clock UA is set indicating thatSSPxADD needs to beupdated KPNote:An update of the SSPxADDregister before the fallingedge of the ninth clock willhave no effect on UA andUA will remain set. S S S B S U C DS39682E-page 174 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 16.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPxSR is SUPPORT transferred to the SSPxBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK The addressing procedure for the I2C bus is such that bit), the SSPxIF interrupt flag bit is set. the first byte after the Start condition usually determines which device will be the slave addressed by When the interrupt is serviced, the source for the the master. The exception is the general call address interrupt can be checked by reading the contents of the which can address all devices. When this address is SSPxBUF. The value can be used to determine if the used, all devices should, in theory, respond with an address was device-specific or a general call address. Acknowledge. In 10-bit mode, the SSPxADD is required to be updated The general call address is one of eight addresses for the second half of the address to match and the UA reserved for specific purposes by the I2C protocol. It bit is set (SSPxSTAT<1>). If the general call address is consists of all ‘0’s with R/W = 0. sampled when the GCEN bit is set, while the slave is configured in 10-Bit Addressing mode, then the second The general call address is recognized when the half of the address is not necessary, the UA bit will not General Call Enable bit, GCEN, is enabled be set and the slave will begin receiving data after the (SSPxCON2<7> set). Following a Start bit detect, 8 bits Acknowledge (Figure16-15). are shifted into the SSPxSR and the address is compared against the SSPxADD. It is also compared to the general call address and fixed in hardware. FIGURE 16-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESSING MODE) Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK General Call Address SDAx ACK D7 D6 D5 D4 D3 D2 D1 D0 SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPxIF BF (SSPxSTAT<0>) Cleared in software SSPxBUF is read SSPOV (SSPxCON1<6>) ‘0’ GCEN (SSPxCON2<7>) ‘1’ © 2009 Microchip Technology Inc. DS39682E-page 175

PIC18F45J10 FAMILY 16.4.6 MASTER MODE Note: The MSSP module, when configured in Master mode is enabled by setting and clearing the I2C Master mode, does not allow queueing appropriate SSPM bits in SSPxCON1 and by setting of events. For instance, the user is not the SSPEN bit. In Master mode, the SCLx and SDAx allowed to initiate a Start condition and lines are manipulated by the MSSP hardware. immediately write the SSPxBUF register to initiate transmission before the Start con- Master mode of operation is supported by interrupt dition is complete. In this case, the generation on the detection of the Start and Stop SSPxBUF will not be written to and the conditions. The Stop (P) and Start (S) bits are cleared WCOL bit will be set, indicating that a write from a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is to the SSPxBUF did not occur. set, or the bus is Idle, with both the S and P bits clear. The following events will cause the MSSP Interrupt In Firmware Controlled Master mode, user code Flag bit, SSPxIF, to be set (and MSSP interrupt, if conducts all I2C bus operations based on Start and enabled): Stop bit conditions. • Start condition Once Master mode is enabled, the user has six • Stop condition options. • Data transfer byte transmitted/received 1. Assert a Start condition on SDAx and SCLx. • Acknowledge transmit 2. Assert a Repeated Start condition on SDAx and • Repeated Start SCLx. 3. Write to the SSPxBUF register initiating transmission of data/address. 4. Configure the I2C port to receive data. 5. Generate an Acknowledge condition at the end of a received byte of data. 6. Generate a Stop condition on SDAx and SCLx. 2 FIGURE 16-16: MSSP BLOCK DIAGRAM (I C™ MASTER MODE) Internal SSPM<3:0> Data Bus SSPxADD<6:0> Read Write SSPxBUF Baud Rate Generator SDAx Shift SDAx In Clock ct e SSPxSR Detce) MSb LSb L ur e Oo abl WCk s SCLx Receive En StAarcGtk bneiont,we Srlaetotdepg ebit, Clock Cntl ck Arbitrate/(hold off cloc o Cl Start bit Detect, Stop bit Detect, SCLx In Write Collision Detect, Set/Reset S, P, WCOL (SSPxSTAT, SSPxCON1); Clock Arbitration, Set SSPxIF, BCLxIF; Bus Collision State Counter for Reset ACKSTAT, PEN (SSPxCON2) End of XMIT/RCV DS39682E-page 176 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 16.4.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock 1. The user generates a Start condition by setting pulses and the Start and Stop conditions. A transfer is the Start Enable bit, SEN (SSPxCON2<0>). ended with a Stop condition or with a Repeated Start 2. SSPxIF is set. The MSSP module will wait the condition. Since the Repeated Start condition is also required start time before any other operation the beginning of the next serial transfer, the I2C bus will takes place. not be released. 3. The user loads the SSPxBUF with the slave In Master Transmitter mode, serial data is output address to transmit. through SDAx, while SCLx outputs the serial clock. The 4. Address is shifted out the SDAx pin until all 8 bits first byte transmitted contains the slave address of the are transmitted. receiving device (7 bits) and the Read/Write (R/W) bit. 5. The MSSP module shifts in the ACK bit from the In this case, the R/W bit will be logic ‘0’. Serial data is slave device and writes its value into the transmitted 8 bits at a time. After each byte is transmit- SSPxCON2 register (SSPxCON2<6>). ted, an Acknowledge bit is received. Start and Stop 6. The MSSP module generates an interrupt at the conditions are output to indicate the beginning and the end of the ninth clock cycle by setting the end of a serial transfer. SSPxIF bit. In Master Receive mode, the first byte transmitted 7. The user loads the SSPxBUF with eight bits of contains the slave address of the transmitting device data. (7bits) and the R/W bit. In this case, the R/W bit will be 8. Data is shifted out the SDAx pin until all 8 bits logic ‘1’. Thus, the first byte transmitted is a 7-bit slave are transmitted. address followed by a ‘1’ to indicate the receive bit. 9. The MSSP module shifts in the ACK bit from the Serial data is received via SDAx, while SCLx outputs slave device and writes its value into the the serial clock. Serial data is received 8 bits at a time. SSPxCON2 register (SSPxCON2<6>). After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the 10. The MSSP module generates an interrupt at the beginning and end of transmission. end of the ninth clock cycle by setting the SSPxIF bit. The Baud Rate Generator used for the SPI mode 11. The user generates a Stop condition by setting operation is used to set the SCLx clock frequency for either 100kHz, 400kHz or 1MHz I2C operation. See the Stop Enable bit, PEN (SSPxCON2<2>). Section16.4.7 “Baud Rate” for more detail. 12. Interrupt is generated once the Stop condition is complete. © 2009 Microchip Technology Inc. DS39682E-page 177

PIC18F45J10 FAMILY 16.4.7 BAUD RATE Table16-3 demonstrates clock rates based on In I2C Master mode, the Baud Rate Generator (BRG) instruction cycles and the BRG value loaded into SSPxADD. reload value is placed in the lower 7 bits of the SSPxADD register (Figure16-17). When a write 16.4.7.1 Baud Rate and Module occurs to SSPxBUF, the Baud Rate Generator will Interdependence automatically begin counting. The BRG counts down to ‘0’ and stops until another reload has taken place. The Because MSSP1 and MSSP2 are independent, they BRG count is decremented twice per instruction cycle can operate simultaneously in I2C Master mode at (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the different baud rates. This is done by using different BRG is reloaded automatically. BRG reload values for each module. Once the given operation is complete (i.e., transmis- Because this mode derives its basic clock source from sion of the last data bit is followed by ACK), the internal the system clock, any changes to the clock will affect clock will automatically stop counting and the SCLx pin both modules in the same proportion. It may be pos- will remain in its last state. sible to change one or both baud rates back to a previous value by changing the BRG reload value. FIGURE 16-17: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPxADD<6:0> SSPM<3:0> Reload Reload SCLx Control CLKO BRG Down Counter FOSC/4 TABLE 16-3: I2C™ CLOCK RATE w/BRG FSCL FCY FCY * 2 BRG Value (2 Rollovers of BRG) 10 MHz 20 MHz 18h 400 kHz(1) 10 MHz 20 MHz 1Fh 312.5 kHz 10 MHz 20 MHz 63h 100 kHz 4 MHz 8 MHz 09h 400 kHz(1) 4 MHz 8 MHz 0Ch 308 kHz 4 MHz 8 MHz 27h 100 kHz 1 MHz 2 MHz 02h 333 kHz(1) 1 MHz 2 MHz 09h 100 kHz 1 MHz 2 MHz 00h 1 MHz(1) Note 1: The I2C™ interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100kHz) in all details, but may be used with care where higher rates are required by the application. DS39682E-page 178 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 16.4.7.2 Clock Arbitration SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and Clock arbitration occurs when the master, during any begins counting. This ensures that the SCLx high time receive, transmit or Repeated Start/Stop condition, will always be at least one BRG rollover count in the deasserts the SCLx pin (SCLx allowed to float high). event that the clock is held low by an external device When the SCLx pin is allowed to float high, the Baud (Figure16-18). Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the FIGURE 16-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDAx DX DX – 1 SCLx deasserted but slave holds SCLx allowed to transition high SCLx low (clock arbitration) SCLx BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCLx is sampled high, reload takes place and BRG starts its count BRG Reload © 2009 Microchip Technology Inc. DS39682E-page 179

PIC18F45J10 FAMILY 16.4.8 I2C MASTER MODE START Note: If, at the beginning of the Start condition, CONDITION TIMING the SDAx and SCLx pins are already sam- To initiate a Start condition, the user sets the Start pled low, or if during the Start condition, the Enable bit, SEN (SSPxCON2<0>). If the SDAx and SCLx line is sampled low before the SDAx SCLx pins are sampled high, the Baud Rate Generator line is driven low, a bus collision occurs. is reloaded with the contents of SSPxADD<6:0> and The Bus Collision Interrupt Flag, BCLxIF, starts its count. If SCLx and SDAx are both sampled is set, the Start condition is aborted and high when the Baud Rate Generator times out (TBRG), the I2C module is reset into its Idle state. the SDAx pin is driven low. The action of the SDAx 16.4.8.1 WCOL Status Flag being driven low while SCLx is high is the Start condi- tion and causes the S bit (SSPxSTAT<3>) to be set. If the user writes the SSPxBUF when a Start sequence Following this, the Baud Rate Generator is reloaded is in progress, the WCOL is set and the contents of the with the contents of SSPxADD<6:0> and resumes its buffer are unchanged (the write doesn’t occur). count. When the Baud Rate Generator times out Note: Because queueing of events is not (TBRG), the SEN bit (SSPxCON2<0>) will be automati- allowed, writing to the lower 5 bits of cally cleared by hardware. The Baud Rate Generator is SSPxCON2 is disabled until the Start suspended, leaving the SDAx line held low and the condition is complete. Start condition is complete. FIGURE 16-19: FIRST START BIT TIMING Set S bit (SSPxSTAT<3>) Write to SEN bit occurs here SDAx = 1, At completion of Start bit, SCLx = 1 hardware clears SEN bit and sets SSPxIF bit TBRG TBRG Write to SSPxBUF occurs here 1st bit 2nd bit SDAx TBRG SCLx TBRG S DS39682E-page 180 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 16.4.9 I2C MASTER MODE REPEATED Note1: If RSEN is programmed while any other START CONDITION TIMING event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit 2: A bus collision during the Repeated Start (SSPxCON2<1>) is programmed high and the I2C logic condition occurs if: module is in the Idle state. When the RSEN bit is set, • SDAx is sampled low when SCLx the SCLx pin is asserted low. When the SCLx pin is goes from low-to-high. sampled low, the Baud Rate Generator is loaded with the contents of SSPxADD<6:0> and begins counting. • SCLx goes low before SDAx is The SDAx pin is released (brought high) for one Baud asserted low. This may indicate that Rate Generator count (TBRG). When the Baud Rate another master is attempting to Generator times out, if SDAx is sampled high, the SCLx transmit a data ‘1’. pin will be deasserted (brought high). When SCLx is Immediately following the SSPxIF bit getting set, the sampled high, the Baud Rate Generator is reloaded user may write the SSPxBUF with the 7-bit address in with the contents of SSPxADD<6:0> and begins count- 7-bit mode or the default first address in 10-bit mode. ing. SDAx and SCLx must be sampled high for one After the first eight bits are transmitted and an ACK is TBRG. This action is then followed by assertion of the received, the user may then transmit an additional eight SDAx pin (SDAx = 0) for one TBRG while SCLx is high. bits of address (10-bit mode) or eight bits of data (7-bit Following this, the RSEN bit (SSPxCON2<1>) will be mode). automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDAx pin held low. As 16.4.9.1 WCOL Status Flag soon as a Start condition is detected on the SDAx and If the user writes the SSPxBUF when a Repeated Start SCLx pins, the S bit (SSPxSTAT<3>) will be set. The sequence is in progress, the WCOL is set and the SSPxIF bit will not be set until the Baud Rate Generator contents of the buffer are unchanged (the write doesn’t has timed out. occur). Note: Because queueing of events is not allowed, writing of the lower 5 bits of SSPxCON2 is disabled until the Repeated Start condition is complete. FIGURE 16-20: REPEATED START CONDITION WAVEFORM S bit set by hardware SDAx = 1, At completion of Start bit, Write to SSPxCON2 occurs here:SDAx = 1, SCLx = 1 hardware clears RSEN bit SCLx (no change) and sets SSPxIF TBRG TBRG TBRG SDAx 1st bit RSEN bit set by hardware on falling edge of ninth clock, Write to SSPxBUF occurs here end of Xmit TBRG SCLx TBRG Sr = Repeated Start © 2009 Microchip Technology Inc. DS39682E-page 181

PIC18F45J10 FAMILY 16.4.10 I2C MASTER MODE The user should verify that the WCOL is clear after TRANSMISSION each write to SSPxBUF to ensure the transfer is correct. In all cases, WCOL must be cleared in Transmission of a data byte, a 7-bit address or the software. other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will 16.4.10.3 ACKSTAT Status Flag set the Buffer Full flag bit, BF, and allow the Baud Rate In Transmit mode, the ACKSTAT bit (SSPxCON2<6>) Generator to begin counting and start the next trans- is cleared when the slave has sent an Acknowledge mission. Each bit of address/data will be shifted out (ACK=0) and is set when the slave does not Acknowl- onto the SDAx pin after the falling edge of SCLx is edge (ACK = 1). A slave sends an Acknowledge when asserted (see data hold time specification it has recognized its address (including a general call), parameter106). SCLx is held low for one Baud Rate or when the slave has properly received its data. Generator rollover count (TBRG). Data should be valid before SCLx is released high (see data setup time 16.4.11 I2C MASTER MODE RECEPTION specification parameter107). When the SCLx pin is released high, it is held that way for TBRG. The data on Master mode reception is enabled by programming the the SDAx pin must remain stable for that duration and Receive Enable bit, RCEN (SSPxCON2<3>). some hold time after the next falling edge of SCLx. Note: The MSSP module must be in an Idle state After the eighth bit is shifted out (the falling edge of the before the RCEN bit is set or the RCEN bit eighth clock), the BF flag is cleared and the master will be disregarded. releases SDAx. This allows the slave device being addressed to respond with an ACK bit during the ninth The Baud Rate Generator begins counting, and on bit time if an address match occurred, or if data was each rollover, the state of the SCLx pin changes received properly. The status of ACK is written into the (high-to-low/low-to-high) and data is shifted into the ACKDT bit on the falling edge of the ninth clock. If the SSPxSR. After the falling edge of the eighth clock, the master receives an Acknowledge, the Acknowledge receive enable flag is automatically cleared, the con- Status bit, ACKSTAT, is cleared; if not, the bit is set. tents of the SSPxSR are loaded into the SSPxBUF, the After the ninth clock, the SSPxIF bit is set and the BF flag bit is set, the SSPxIF flag bit is set and the Baud master clock (Baud Rate Generator) is suspended until Rate Generator is suspended from counting, holding the next data byte is loaded into the SSPxBUF, leaving SCLx low. The MSSP is now in Idle state awaiting the SCLx low and SDAx unchanged (Figure16-21). next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can After the write to the SSPxBUF, each bit of the address then send an Acknowledge bit at the end of reception will be shifted out on the falling edge of SCLx until all by setting the Acknowledge Sequence Enable bit, seven address bits and the R/W bit are completed. On ACKEN (SSPxCON2<4>). the falling edge of the eighth clock, the master will deassert the SDAx pin, allowing the slave to respond 16.4.11.1 BF Status Flag with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDAx pin to see if the In receive operation, the BF bit is set when an address address was recognized by a slave. The status of the or data byte is loaded into SSPxBUF from SSPxSR. It ACK bit is loaded into the ACKSTAT status bit is cleared when the SSPxBUF register is read. (SSPxCON2<6>). Following the falling edge of the 16.4.11.2 SSPOV Status Flag ninth clock transmission of the address, the SSPxIF is set, the BF flag is cleared and the Baud Rate Generator In receive operation, the SSPOV bit is set when 8 bits is turned off until another write to the SSPxBUF takes are received into the SSPxSR and the BF flag bit is place, holding SCLx low and allowing SDAx to float. already set from a previous reception. 16.4.10.1 BF Status Flag 16.4.11.3 WCOL Status Flag In Transmit mode, the BF bit (SSPxSTAT<0>) is set If the user writes the SSPxBUF when a receive is when the CPU writes to SSPxBUF and is cleared when already in progress (i.e., SSPxSR is still shifting in a all 8 bits are shifted out. data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur). 16.4.10.2 WCOL Status Flag If the user writes to the SSPxBUF when a transmit is already in progress (i.e., SSPxSR is still shifting out a data byte), the WCOL is set and the contents of the buf- fer are unchanged (the write doesn’t occur) after 2TCY after the SSPxBUF write. If SSPxBUF is rewritten within 2 TCY, the WCOL bit is set and SSPxBUF is updated. This may result in a corrupted transfer. DS39682E-page 182 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY FIGURE 16-21: I2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESSING) 1 AT in ON2 = oftware STxC P n s ACKSSP ared i K e >) AC 9 Cl 6 N2< D0 8 e slave, clear ACKSTAT bit (SSPxCO Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1 234567 Cleared in software service routinfrom MSSP interrupt SSPxBUF is written in software om D7 1 xIF Fr ow SP = 0 SCLx held lwhile CPUsponds to S CK re = 0 A W 9 are R/W A1 ess and R/ 78 d by hardw ave A2 addr 6 eare PxCON2<0> (SEN = )1dition begins SEN = 0 Transmit Address to Sl A7A6A5A4A3 SSPxBUF written with 7-bit start transmit 12345 Cleared in software SSPxBUF written After Start condition, SEN cl Sn Write SStart co S T<0>) A T S x F SP SDAx SCLx SSPxI BF (S SEN PEN R/W © 2009 Microchip Technology Inc. DS39682E-page 183

PIC18F45J10 FAMILY FIGURE 16-22: I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESSING) pt Write to SSPxCON2<4>to start Acknowledge sequenceSDAx = ACKDT (SSPxCON2<5>) = 0 Set ACKEN, start Acknowledge sequenceACK from Master,er configured as a receiverSDAx = ACKDT = SDAx = ACKDT = 10ogramming SSPxCON2<3> (RCEN = )1PEN bit = 1RCEN = , startRCEN cleared1RCEN clearedwritten herenext receiveautomaticallyautomatically Receiving Data from SlaveReceiving Data from SlaveACKD0D2D5D2D5D3D4D6D7D3D4D6D7D1D1D0ACK Bus masterACK is not sentterminatestransfer967898756512343124PSet SSPxIF at endData shifted in on falling edge of CLKof receiveSet SSPxIF interruat end of Acknow-Set SSPxIF interruptSet SSPxIF interruptledge sequenceat end of receiveat end of Acknowledgesequence Set P bit Cleared in softwareCleared in softwareCleared in software(SSPxSTAT<4>)Cleared insoftwareand SSPxIF Last bit is shifted into SSPxSR andcontents are unloaded into SSPxBUF SSPOV is set becauseSSPxBUF is still full Mastby pr ACK from Slave R/W = 1A1ACK 798 e, Write to SSPxCON2<0> (SEN = ),1begin Start condition SEN = 0Write to SSPxBUF occurs herstart XMIT Transmit Address to Slave A7A6A5A4A3A2SDAx 361245SCLxS SSPxIF Cleared in softwareSDAx = , SCLx = 01while CPU responds to SSPxIF BF (SSPxSTAT<0>) SSPOV ACKEN DS39682E-page 184 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 16.4.12 ACKNOWLEDGE SEQUENCE 16.4.13 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDAx pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge Sequence Enable bit, ACKEN bit, PEN (SSPxCON2<2>). At the end of a (SSPxCON2<4>). When this bit is set, the SCLx pin is receive/transmit, the SCLx line is held low after the fall- pulled low and the contents of the Acknowledge data bit ing edge of the ninth clock. When the PEN bit is set, the are presented on the SDAx pin. If the user wishes to master will assert the SDAx line low. When the SDAx generate an Acknowledge, then the ACKDT bit should line is sampled low, the Baud Rate Generator is be cleared. If not, the user should set the ACKDT bit reloaded and counts down to 0. When the Baud Rate before starting an Acknowledge sequence. The Baud Generator times out, the SCLx pin will be brought high Rate Generator then counts for one rollover period and one TBRG (Baud Rate Generator rollover count) (TBRG) and the SCLx pin is deasserted (pulled high). later, the SDAx pin will be deasserted. When the SDAx When the SCLx pin is sampled high (clock arbitration), pin is sampled high while SCLx is high, the P bit the Baud Rate Generator counts for TBRG. The SCLx pin (SSPxSTAT<4>) is set. A TBRG later, the PEN bit is is then pulled low. Following this, the ACKEN bit is auto- cleared and the SSPxIF bit is set (Figure16-24). matically cleared, the Baud Rate Generator is turned off 16.4.13.1 WCOL Status Flag and the MSSP module then goes into Idle mode (Figure16-23). If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the 16.4.12.1 WCOL Status Flag contents of the buffer are unchanged (the write doesn’t If the user writes the SSPxBUF when an Acknowledge occur). sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). FIGURE 16-23: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSPxCON2 ACKEN = 1, ACKDT = 0 TBRG TBRG SDAx D0 ACK SCLx 8 9 SSPxIF Cleared in SSPxIF set at Cleared in software the end of receive software SSPxIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. © 2009 Microchip Technology Inc. DS39682E-page 185

PIC18F45J10 FAMILY FIGURE 16-24: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPxCON2, SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG set PEN after SDAx sampled high. P bit (SSPxSTAT<4>) is set. Falling edge of PEN bit (SSPxCON2<2>) is cleared by 9th clock hardware and the SSPxIF bit is set TBRG SCLx SDAx ACK P TBRG TBRG TBRG SCLx brought high after TBRG SDAx asserted low before rising edge of clock to set up Stop condition Note: TBRG = one Baud Rate Generator period. 16.4.14 SLEEP OPERATION 16.4.17 MULTI-MASTER COMMUNICATION, While in Sleep mode, the I2C module can receive BUS COLLISION AND BUS ARBITRATION addresses or data and when an address match or complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra- from Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto the SDAx pin, arbitration takes place when the master 16.4.15 EFFECTS OF A RESET outputs a ‘1’ on SDAx, by letting SDAx float high, and A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCLx pin floats current transfer. high, data should be stable. If the expected data on SDAx is a ‘1’ and the data sampled on the SDAx 16.4.16 MULTI-MASTER MODE pin=0, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLxIF In Multi-Master mode, the interrupt generation on the and reset the I2C port to its Idle state (Figure16-25). detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is MSSP module is disabled. Control of the I2C bus may cleared, the SDAx and SCLx lines are deasserted and be taken when the P bit (SSPxSTAT<4>) is set, or the the SSPxBUF can be written to. When the user services bus is Idle, with both the S and P bits clear. When the the bus collision Interrupt Service Routine, and if the I2C bus is busy, enabling the MSSP interrupt will generate bus is free, the user can resume communication by the interrupt when the Stop condition occurs. asserting a Start condition. In multi-master operation, the SDAx line must be If a Start, Repeated Start, Stop or Acknowledge condition monitored for arbitration to see if the signal level is the was in progress when the bus collision occurred, the expected output level. This check is performed in condition is aborted, the SDAx and SCLx lines are deas- hardware with the result placed in the BCLxIF bit. serted and the respective control bits in the SSPxCON2 register are cleared. When the user services the bus The states where arbitration can be lost are: collision Interrupt Service Routine, and if the I2C bus is • Address Transfer free, the user can resume communication by asserting a • Data Transfer Start condition. • A Start Condition The master will continue to monitor the SDAx and SCLx • A Repeated Start Condition pins. If a Stop condition occurs, the SSPxIF bit will be set. • An Acknowledge Condition A write to the SSPxBUF will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determi- nation of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPxSTAT register, or the bus is Idle and the S and P bits are cleared. DS39682E-page 186 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY FIGURE 16-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Sample SDAx. While SCLx is high, Data changes SDAx line pulled low data doesn’t match what is driven while SCLx = 0 by another source by the master. Bus collision has occurred. SDAx released by master SDAx SCLx Set bus collision interrupt (BCLxIF) BCLxIF © 2009 Microchip Technology Inc. DS39682E-page 187

PIC18F45J10 FAMILY 16.4.17.1 Bus Collision During a Start If the SDAx pin is sampled low during this count, the Condition BRG is reset and the SDAx line is asserted early (Figure16-28). If, however, a ‘1’ is sampled on the During a Start condition, a bus collision occurs if: SDAx pin, the SDAx pin is asserted low at the end of a) SDAx or SCLx are sampled low at the beginning the BRG count. The Baud Rate Generator is then of the Start condition (Figure16-26). reloaded and counts down to 0. If the SCLx pin is b) SCLx is sampled low before SDAx is asserted sampled as ‘0’ during this time, a bus collision does not low (Figure16-27). occur. At the end of the BRG count, the SCLx pin is asserted low. During a Start condition, both the SDAx and the SCLx pins are monitored. Note: The reason that bus collision is not a factor during a Start condition is that no two bus If the SDAx pin is already low, or the SCLx pin is masters can assert a Start condition at the already low, then all of the following occur: exact same time. Therefore, one master • the Start condition is aborted; will always assert SDAx before the other. • the BCLxIF flag is set; and This condition does not cause a bus colli- • the MSSP module is reset to its Idle state sion because the two masters must be (Figure16-26). allowed to arbitrate the first address The Start condition begins with the SDAx and SCLx following the Start condition. If the address pins deasserted. When the SDAx pin is sampled high, is the same, arbitration must be allowed to the Baud Rate Generator is loaded from continue into the data portion, Repeated SSPxADD<6:0> and counts down to ‘0’. If the SCLx pin Start or Stop conditions. is sampled low while SDAx is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 16-26: BUS COLLISION DURING START CONDITION (SDAx ONLY) SDAx goes low before the SEN bit is set. Set BCLxIF, S bit and SSPxIF set because SDAx = 0, SCLx = 1. SDAx SCLx Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDAx = 1, SCLx = 1 MSSP module reset into Idle state. SEN SDAx sampled low before Start condition. Set BCLxIF. S bit and SSPxIF set because BCLxIF SDAx = 0, SCLx = 1. SSPxIF and BCLxIF are cleared in software S SSPxIF SSPxIF and BCLxIF are cleared in software DS39682E-page 188 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY FIGURE 16-27: BUS COLLISION DURING START CONDITION (SCLx = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start SCLx sequence if SDAx = 1, SCLx = 1 SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF. BCLxIF Interrupt cleared in software S ‘0’ ‘0’ SSPxIF ‘0’ ‘0’ FIGURE 16-28: BRG RESET DUE TO SDAx ARBITRATION DURING START CONDITION SDAx = 0, SCLx = 1 Set S Set SSPxIF Less than TBRG TBRG SDAx SDAx pulled low by other master. Reset BRG and assert SDAx. SCLx S SCLx pulled low after BRG time-out SEN Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 BCLxIF ‘0’ S SSPxIF SDAx = 0, SCLx = 1, Interrupts cleared set SSPxIF in software © 2009 Microchip Technology Inc. DS39682E-page 189

PIC18F45J10 FAMILY 16.4.17.2 Bus Collision During a Repeated If SDAx is low, a bus collision has occurred (i.e., another Start Condition master is attempting to transmit a data ‘0’, see Figure16-29). If SDAx is sampled high, the BRG is During a Repeated Start condition, a bus collision reloaded and begins counting. If SDAx goes from occurs if: high-to-low before the BRG times out, no bus collision a) A low level is sampled on SDAx when SCLx occurs because no two masters can assert SDAx at goes from low level to high level. exactly the same time. b) SCLx goes low before SDAx is asserted low, If SCLx goes from high-to-low before the BRG times indicating that another master is attempting to out and SDAx has not already been asserted, a bus transmit a data ‘1’. collision occurs. In this case, another master is When the user deasserts SDAx and the pin is allowed attempting to transmit a data ‘1’ during the Repeated to float high, the BRG is loaded with SSPxADD<6:0> Start condition (see Figure16-30). and counts down to 0. The SCLx pin is then deasserted If, at the end of the BRG time-out, both SCLx and SDAx and when sampled high, the SDAx pin is sampled. are still high, the SDAx pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCLx pin, the SCLx pin is driven low and the Repeated Start condition is complete. FIGURE 16-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDAx SCLx Sample SDAx when SCLx goes high. If SDAx = 0, set BCLxIF and release SDAx and SCLx. RSEN BCLxIF Cleared in software S ‘0’ SSPxIF ‘0’ FIGURE 16-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDAx SCLx SCLx goes low before SDAx, BCLxIF set BCLxIF. Release SDAx and SCLx. Interrupt cleared in software RSEN S ‘0’ SSPxIF DS39682E-page 190 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 16.4.17.3 Bus Collision During a Stop The Stop condition begins with SDAx asserted low. Condition When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with a) After the SDAx pin has been deasserted and SSPxADD<6:0> and counts down to 0. After the BRG allowed to float high, SDAx is sampled low after times out, SDAx is sampled. If SDAx is sampled low, a the BRG has timed out. bus collision has occurred. This is due to another b) After the SCLx pin is deasserted, SCLx is master attempting to drive a data ‘0’ (Figure16-31). If sampled low before SDAx goes high. the SCLx pin is sampled low before SDAx is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure16-32). FIGURE 16-31: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDAx sampled low after TBRG, set BCLxIF SDAx SDAx asserted low SCLx PEN BCLxIF P ‘0’ SSPxIF ‘0’ FIGURE 16-32: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDAx SCLx goes low before SDAx goes high, Assert SDAx set BCLxIF SCLx PEN BCLxIF P ‘0’ SSPxIF ‘0’ © 2009 Microchip Technology Inc. DS39682E-page 191

PIC18F45J10 FAMILY TABLE 16-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47 PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49 PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49 IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49 PIR2 OSCFIF CMIF — — BCL1IF — — CCP2IF 49 PIE2 OSCFIE CMIE — — BCL1IE — — CCP2IE 49 IPR2 OSCFIP CMIP — — BCL1IP — — CCP2IP 49 PIR3 SSP2IF BCL2IF — — — — — — 49 PIE3 SSP2IE BCL2IE — — — — — — 49 IPR3 SSP2IP BCL2IP — — — — — — 49 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 50 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 50 SSP1BUF MSSP1 Receive Buffer/Transmit Register 48 SSP1ADD MSSP1 Address Register (I2C™ Slave mode). 48 MSSP1 Baud Rate Reload Register (I2C Master mode). SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 48 SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 48 GCEN ACKSTAT ADMSK5(2) ADMSK4(2) ADMSK3(2) ADMSK2(2) ADMSK1(2) SEN 48 SSP1STAT SMP CKE D/A P S R/W UA BF 48 SSP2BUF MSSP2 Receive Buffer/Transmit Register 50 SSP2ADD MSSP2 Address Register (I2C Slave mode). 50 MSSP2 Baud Rate Reload Register (I2C Master mode). SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 50 SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 50 GCEN ACKSTAT ADMSK5(2) ADMSK4(2) ADMSK3(2) ADMSK2(2) ADMSK1(2) SEN 48 SSP2STAT SMP CKE D/A P S R/W UA BF 50 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode. Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’. 2: Alternate names and definitions for these bits when the MSSP module is operating in I2C Slave mode. See Section16.4.3.2 “Address Masking” for details. DS39682E-page 192 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 17.0 ENHANCED UNIVERSAL The pins of the Enhanced USART are multiplexed SYNCHRONOUS with PORTC. In order to configure RC6/TX/CK and RC7/RX/DT as an EUSART: ASYNCHRONOUS RECEIVER • bit SPEN (RCSTA<7>) must be set (= 1) TRANSMITTER (EUSART) • bit TRISC<7> must be set (= 1) The Enhanced Universal Synchronous Asynchronous • bit TRISC<6> must be set (= 1) Receiver Transmitter (EUSART) module is one of the Note: The EUSART control will automatically two serial I/O modules. (Generically, the USART is also reconfigure the pin from input to output as known as a Serial Communications Interface or SCI.) needed. The EUSART can be configured as a full-duplex, asynchronous system that can communicate with The operation of the Enhanced USART module is peripheral devices, such as CRT terminals and controlled through three registers: personal computers. It can also be configured as a half- • Transmit Status and Control (TXSTA) duplex synchronous system that can communicate • Receive Status and Control (RCSTA) with peripheral devices, such as A/D or D/A integrated • Baud Rate Control (BAUDCON) circuits, serial EEPROMs, etc. These are detailed on the following pages in The Enhanced USART module implements additional Register17-1, Register17-2 and Register17-3, features, including automatic baud rate detection and respectively. calibration, automatic wake-up on Sync Break recep- tion and 12-bit Break character transmit. These make it ideally suited for use in Local Interconnect Network (LIN/J2602) bus systems. The EUSART can be configured in the following modes: • Asynchronous (full duplex) with: - Auto-wake-up on character reception - Auto-baud calibration - 12-bit Break character transmission • Synchronous – Master (half duplex) with selectable clock polarity • Synchronous – Slave (half duplex) with selectable clock polarity © 2009 Microchip Technology Inc. DS39682E-page 193

PIC18F45J10 FAMILY REGISTER 17-1: TXSTA: EUSART TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-Bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care. bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th Bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS39682E-page 194 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY REGISTER 17-2: RCSTA: EUSART RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care. Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave: Don’t care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 9-bit (RX9 = 0): Don’t care. bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receiving next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit, CREN) 0 = No overrun error bit 0 RX9D: 9th Bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. © 2009 Microchip Technology Inc. DS39682E-page 195

PIC18F45J10 FAMILY REGISTER 17-3: BAUDCON: BAUD RATE CONTROL REGISTER 1 R/W-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurred bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: Unused in this mode. Synchronous mode: 1 = Idle state for clock (CK) is a high level 0 = Idle state for clock (CK) is a low level bit 3 BRG16: 16-Bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator – SPBRGH and SPBRG 0 = 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RX pin – interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RX pin not monitored or rising edge detected Synchronous mode: Unused in this mode. bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h); cleared in hardware upon completion. 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. DS39682E-page 196 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 17.1 Baud Rate Generator (BRG) advantageous to use the high baud rate (BRGH = 1) or the 16-bit BRG to reduce the baud rate error, or The BRG is a dedicated 8-bit or 16-bit generator that achieve a slow baud rate for a fast oscillator frequency. supports both the Asynchronous and Synchronous Writing a new value to the SPBRGH:SPBRG registers modes of the EUSART. By default, the BRG operates causes the BRG timer to be reset (or cleared). This in 8-bit mode; setting the BRG16 bit (BAUDCON<3>) ensures the BRG does not wait for a timer overflow selects 16-bit mode. before outputting the new baud rate. The SPBRGH:SPBRG register pair controls the period of a free-running timer. In Asynchronous mode, bits, 17.1.1 OPERATION IN POWER-MANAGED BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>), also MODES control the baud rate. In Synchronous mode, BRGH is The device clock is used to generate the desired baud ignored. Table17-1 shows the formula for computation rate. When one of the power-managed modes is of the baud rate for different EUSART modes which entered, the new clock source may be operating at a only apply in Master mode (internally generated clock). different frequency. This may require an adjustment to Given the desired baud rate and FOSC, the nearest the value in the SPBRG register pair. integer value for the SPBRGH:SPBRG registers can be calculated using the formulas in Table17-1. From this, 17.1.2 SAMPLING the error in baud rate can be determined. An example The data on the RX pin is sampled three times by a calculation is shown in Example17-1. Typical baud majority detect circuit to determine if a high or a low rates and error values for the various Asynchronous level is present at the RX pin. modes are shown in Table17-2. It may be TABLE 17-1: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n + 1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n + 1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n + 1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPBRGH:SPBRG register pair © 2009 Microchip Technology Inc. DS39682E-page 197

PIC18F45J10 FAMILY EXAMPLE 17-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1)) Solving for SPBRGH:SPBRG: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.16% TABLE 17-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 49 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 49 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 49 SPBRGH EUSART Baud Rate Generator Register High Byte 49 SPBRG EUSART Baud Rate Generator Register Low Byte 49 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. DS39682E-page 198 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY TABLE 17-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — — 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — — 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51 1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12 2.4 2.404 0.16 25 2.403 -0.16 12 — — — 9.6 8.929 -6.99 6 — — — — — — 19.2 20.833 8.51 2 — — — — — — 57.6 62.500 8.51 0 — — — — — — 115.2 62.500 -45.75 0 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — — — — — — — — — — 2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 — — — — — — 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — © 2009 Microchip Technology Inc. DS39682E-page 199

PIC18F45J10 FAMILY TABLE 17-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1665 1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1.201 -0.16 415 2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2.403 -0.16 207 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207 1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51 2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25 9.6 9.615 0.16 25 9.615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz RATE (K) Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate value Rate value Rate value Rate value Error Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 0.300 -0.01 6665 1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1.200 -0.04 1665 2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2.400 -0.04 832 9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9.615 -0.16 207 19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19.230 -0.16 103 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57.142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117.647 -2.12 16 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz RATE Actual SPBRG Actual SPBRG Actual SPBRG (K) % % % Rate value Rate value Rate value Error Error Error (K) (decimal) (K) (decimal) (K) (decimal) 0.3 0.300 0.01 3332 0.300 -0.04 1665 0.300 -0.04 832 1.2 1.200 0.04 832 1.201 -0.16 415 1.201 -0.16 207 2.4 2.404 0.16 415 2.403 -0.16 207 2.403 -0.16 103 9.6 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25 19.2 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12 57.6 58.824 2.12 16 55.555 3.55 8 — — — 115.2 111.111 -3.55 8 — — — — — — DS39682E-page 200 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 17.1.3 AUTO-BAUD RATE DETECT Note1: If the WUE bit is set with the ABDEN bit, The Enhanced USART module supports the automatic Auto-Baud Rate Detection will occur on detection and calibration of baud rate. This feature is the byte following the Break character. active only in Asynchronous mode and while the WUE 2: It is up to the user to determine that the bit is clear. incoming character baud rate is within the The automatic baud rate measurement sequence range of the selected BRG clock source. (Figure17-1) begins whenever a Start bit is received Some combinations of oscillator frequency and the ABDEN bit is set. The calculation is and EUSART baud rates are not possible self-averaging. due to bit error rates. Overall system tim- ing and communication baud rates must In the Auto-Baud Rate Detect (ABD) mode, the clock to be taken into consideration when using the the BRG is reversed. Rather than the BRG clocking the Auto-Baud Rate Detection feature. incoming RX signal, the RX signal is timing the BRG. In ABD mode, the internal Baud Rate Generator is used as a counter to time the bit period of the incoming serial TABLE 17-4: BRG COUNTER byte stream. CLOCK RATES Once the ABDEN bit is set, the state machine will clear BRG16 BRGH BRG Counter Clock the BRG and look for a Start bit. The Auto-Baud Rate Detect must receive a byte with the value 55h (ASCII 0 0 FOSC/512 “U”, which is also the LIN/J2602 bus Sync character) in 0 1 FOSC/128 order to calculate the proper bit rate. The measurement 1 0 FOSC/128 is taken over both a low and a high bit time in order to 1 1 FOSC/32 minimize any effects caused by asymmetry of the incom- Note: During the ABD sequence, SPBRG and ing signal. After a Start bit, the SPBRG begins counting SPBRGH are both used as a 16-bit counter, up, using the preselected clock source on the first rising independent of BRG16 setting. edge of RX. After eight bits on the RX pin or the fifth ris- ing edge, an accumulated value totalling the proper BRG period is left in the SPBRGH:SPBRG register pair. Once 17.1.3.1 ABD and EUSART Transmission the 5th edge is seen (this should correspond to the Stop Since the BRG clock is reversed during ABD acquisi- bit), the ABDEN bit is automatically cleared. tion, the EUSART transmitter cannot be used during If a rollover of the BRG occurs (an overflow from FFFFh ABD. This means that whenever the ABDEN bit is set, to 0000h), the event is trapped by the ABDOVF status TXREG cannot be written to. Users should also ensure bit (BAUDCON<7>). It is set in hardware by BRG roll- that ABDEN does not become set during a transmit overs and can be set or cleared by the user in software. sequence. Failing to do this may result in unpredictable ABD mode remains active after rollover events and the EUSART operation. ABDEN bit remains set (Figure17-2). While calibrating the baud rate period, the BRG regis- ters are clocked at 1/8th the preconfigured clock rate. Note that the BRG clock will be configured by the BRG16 and BRGH bits. Independent of the BRG16 bit setting, both the SPBRG and SPBRGH will be used as a 16-bit counter. This allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the SPBRGH register. Refer to Table17-4 for counter clock rates to the BRG. While the ABD sequence takes place, the EUSART state machine is held in Idle. The RCIF interrupt is set once the fifth rising edge on RX is detected. The value in the RCREG needs to be read to clear the RCIF interrupt. The contents of RCREG should be discarded. © 2009 Microchip Technology Inc. DS39682E-page 201

PIC18F45J10 FAMILY FIGURE 17-1: AUTOMATIC BAUD RATE CALCULATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RX pin Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Stop Bit BRG Clock Set by User Auto-Cleared ABDEN bit RCIF bit (Interrupt) Read RCREG SPBRG XXXXh 1Ch SPBRGH XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE=0. FIGURE 17-2: BRG OVERFLOW SEQUENCE BRG Clock ABDEN bit RX pin Start Bit 0 ABDOVF bit FFFFh BRG Value XXXXh 0000h 0000h DS39682E-page 202 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 17.2 EUSART Asynchronous Mode Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty The Asynchronous mode of operation is selected by and the TXIF flag bit (PIR1<4>) is set. This interrupt can clearing the SYNC bit (TXSTA<4>). In this mode, the be enabled or disabled by setting or clearing the interrupt EUSART uses standard Non-Return-to-Zero (NRZ) for- enable bit, TXIE (PIE1<4>). TXIF will be set regardless of mat (one Start bit, eight or nine data bits and one Stop the state of TXIE; it cannot be cleared in software. TXIF bit). The most common data format is 8 bits. An on-chip, is also not cleared immediately upon loading TXREG, but dedicated 8-bit/16-bit Baud Rate Generator can be used becomes valid in the second instruction cycle following to derive standard baud rate frequencies from the the load instruction. Polling TXIF immediately following a oscillator. load of TXREG will return invalid results. The EUSART transmits and receives the LSb first. The While TXIF indicates the status of the TXREG register, EUSART’s transmitter and receiver are functionally independent but use the same data format and baud another bit, TRMT (TXSTA<1>), shows the status of rate. The Baud Rate Generator produces a clock, either the TSR register. TRMT is a read-only bit which is set x16 or x64 of the bit shift rate depending on the BRGH when the TSR register is empty. No interrupt logic is and BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity tied to this bit so the user has to poll this bit in order to is not supported by the hardware but can be determine if the TSR register is empty. implemented in software and stored as the 9th data bit. Note1: The TSR register is not mapped in data When operating in Asynchronous mode, the EUSART memory so it is not available to the user. module consists of the following important elements: 2: Flag bit TXIF is set when enable bit TXEN • Baud Rate Generator is set. • Sampling Circuit To set up an Asynchronous Transmission: • Asynchronous Transmitter 1. Initialize the SPBRGH:SPBRG registers for the • Asynchronous Receiver appropriate baud rate. Set or clear the BRGH • Auto-Wake-up on Sync Break Character and BRG16 bits, as required, to achieve the • 12-Bit Break Character Transmit desired baud rate. • Auto-Baud Rate Detection 2. Enable the asynchronous serial port by clearing bit, SYNC, and setting bit, SPEN. 17.2.1 EUSART ASYNCHRONOUS 3. If interrupts are desired, set enable bit, TXIE. TRANSMITTER 4. If 9-bit transmission is desired, set transmit bit, The EUSART transmitter block diagram is shown in TX9. Can be used as address/data bit. Figure17-3. The heart of the transmitter is the Transmit 5. Enable the transmission by setting bit, TXEN, (Serial) Shift Register (TSR). The Shift register obtains which will also set bit, TXIF. its data from the Read/Write Transmit Buffer register, 6. If 9-bit transmission is selected, the ninth bit TXREG. The TXREG register is loaded with data in should be loaded in bit, TX9D. software. The TSR register is not loaded until the Stop 7. Load data to the TXREG register (starts bit has been transmitted from the previous load. As transmission). soon as the Stop bit is transmitted, the TSR is loaded 8. If using interrupts, ensure that the GIE and PEIE with new data from the TXREG register (if available). bits in the INTCON register (INTCON<7:6>) are set. FIGURE 17-3: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG Register TXIE 8 MSb LSb (8) • • • 0 Pin Buffer and Control TSR Register TX pin Interrupt TXEN Baud Rate CLK TRMT SPEN BRG16 SPBRGH SPBRG TX9 Baud Rate Generator TX9D © 2009 Microchip Technology Inc. DS39682E-page 203

PIC18F45J10 FAMILY FIGURE 17-4: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) FIGURE 17-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG Word 1 Word 2 BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXIF bit 1 TCY Word 1 Word 2 (Interrupt Reg. Flag) 1 TCY Word 1 Word 2 TRMT bit Transmit Shift Reg. Transmit Shift Reg. (Transmit Shift Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions. TABLE 17-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47 PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49 PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49 IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 49 TXREG EUSART Transmit Register 49 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 49 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 49 SPBRGH EUSART Baud Rate Generator Register High Byte 49 SPBRG EUSART Baud Rate Generator Register Low Byte 49 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’. DS39682E-page 204 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 17.2.2 EUSART ASYNCHRONOUS 17.2.3 SETTING UP 9-BIT MODE WITH RECEIVER ADDRESS DETECT The receiver block diagram is shown in Figure17-6. This mode would typically be used in RS-485 systems. The data is received on the RX pin and drives the data To set up an Asynchronous Reception with Address recovery block. The data recovery block is actually a Detect Enable: high-speed shifter operating at x16 times the baud rate, 1. Initialize the SPBRGH:SPBRG registers for the whereas the main receive serial shifter operates at the appropriate baud rate. Set or clear the BRGH bit rate or at FOSC. This mode would typically be used and BRG16 bits, as required, to achieve the in RS-232 systems. desired baud rate. To set up an Asynchronous Reception: 2. Enable the asynchronous serial port by clearing 1. Initialize the SPBRGH:SPBRG registers for the the SYNC bit and setting the SPEN bit. appropriate baud rate. Set or clear the BRGH 3. If interrupts are required, set the RCEN bit and and BRG16 bits, as required, to achieve the select the desired priority level with the RCIP bit. desired baud rate. 4. Set the RX9 bit to enable 9-bit reception. 2. Enable the asynchronous serial port by clearing 5. Set the ADDEN bit to enable address detect. bit, SYNC, and setting bit, SPEN. 6. Enable reception by setting the CREN bit. 3. If interrupts are desired, set enable bit, RCIE. 7. The RCIF bit will be set when reception is 4. If 9-bit reception is desired, set bit, RX9. complete. The interrupt will be Acknowledged if 5. Enable the reception by setting bit, CREN. the RCIE and GIE bits are set. 6. Flag bit, RCIF, will be set when reception is 8. Read the RCSTA register to determine if any complete and an interrupt will be generated if error occurred during reception, as well as read enable bit, RCIE, was set. bit 9 of data (if applicable). 7. Read the RCSTA register to get the 9th bit (if 9. Read RCREG to determine if the device is being enabled) and determine if any error occurred addressed. during reception. 10. If any error occurred, clear the CREN bit. 8. Read the 8-bit received data by reading the 11. If the device has been addressed, clear the RCREG register. ADDEN bit to allow all received data into the 9. If any error occurred, clear the error by clearing receive buffer and interrupt the CPU. enable bit, CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 17-6: EUSART RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK BRG16 SPBRGH SPBRG ÷ o6r4 MSb RSR Register LSb ÷ 16 or Stop (8) 7 • • • 1 0 Start Baud Rate Generator ÷ 4 RX9 Pin Buffer Data and Control Recovery RX RX9D RCREG Register FIFO SPEN 8 Interrupt RCIF Data Bus RCIE © 2009 Microchip Technology Inc. DS39682E-page 205

PIC18F45J10 FAMILY FIGURE 17-7: ASYNCHRONOUS RECEPTION RX (pin) Start Start Start bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg Word 1 Word 2 Read Rcv RCREG RCREG Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word causing the OERR (Overrun) bit to be set. TABLE 17-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47 PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49 PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49 IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 49 RCREG EUSART Receive Register 49 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 49 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 49 SPBRGH EUSART Baud Rate Generator Register High Byte 49 SPBRG EUSART Baud Rate Generator Register Low Byte 49 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’. 17.2.4 AUTO-WAKE-UP ON SYNC BREAK Following a wake-up event, the module generates an CHARACTER RCIF interrupt. The interrupt is generated synchro- nously to the Q clocks in normal operating modes During Sleep mode, all clocks to the EUSART are (Figure17-8) and asynchronously, if the device is in suspended. Because of this, the Baud Rate Generator Sleep mode (Figure17-9). The interrupt condition is is inactive and a proper byte reception cannot be per- cleared by reading the RCREG register. formed. The auto-wake-up feature allows the controller to wake-up due to activity on the RX/DT line while the The WUE bit is automatically cleared once a low-to- EUSART is operating in Asynchronous mode. high transition is observed on the RX line following the wake-up event. At this point, the EUSART module is in The auto-wake-up feature is enabled by setting the Idle mode and returns to normal operation. This signals WUE bit (BAUDCON<1>). Once set, the typical receive to the user that the Sync Break event is over. sequence on RX/DT is disabled and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event con- sists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a Wake-up Signal character for the LIN/J2602 support protocol.) DS39682E-page 206 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 17.2.4.1 Special Considerations Using 17.2.4.2 Special Considerations Using Auto-Wake-up the WUE Bit Since auto-wake-up functions by sensing rising edge The timing of WUE and RCIF events may cause some transitions on RX/DT, information with any state confusion when it comes to determining the validity of changes before the Stop bit may signal a false End-Of- received data. As noted, setting the WUE bit places the Character (EOC) and cause data or framing errors. To EUSART in an Idle mode. The wake-up event causes a work properly, therefore, the initial character in the receive interrupt by setting the RCIF bit. The WUE bit is transmission must be all ‘0’s. This can be 00h (8 bytes) cleared after this when a rising edge is seen on RX/DT. for standard RS-232 devices or 000h (12 bits) for LIN The interrupt condition is then cleared by reading the bus. RCREG register. Ordinarily, the data in RCREG will be dummy data and should be discarded. Oscillator start-up time must also be considered, especially in applications using oscillators with longer The fact that the WUE bit has been cleared (or is still start-up intervals (i.e., HS mode). The Sync Break (or set) and the RCIF flag is set should not be used as an Wake-up Signal) character must be of sufficient length indicator of the integrity of the data in RCREG. Users and be followed by a sufficient interval to allow enough should consider implementing a parallel method in time for the selected oscillator to start and provide firmware to verify received data integrity. proper initialization of the EUSART. To assure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. FIGURE 17-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit(1) RX/DT Line RCIF Cleared due to user read of RCREG Note1: The EUSART remains in Idle while the WUE bit is set. FIGURE 17-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto-Cleared WUE bit(2) RX/DT Line Note 1 RCIF Cleared due to user read of RCREG Sleep Command Executed Sleep Ends Note1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set. © 2009 Microchip Technology Inc. DS39682E-page 207

PIC18F45J10 FAMILY 17.2.5 BREAK CHARACTER SEQUENCE 1. Configure the EUSART for the desired mode. The EUSART module has the capability of sending the 2. Set the TXEN and SENDB bits to set up the special Break character sequences that are required by Break character. the LIN/J2602 support standard. The Break character 3. Load the TXREG with a dummy character to transmit consists of a Start bit, followed by twelve ‘0’ initiate transmission (the value is ignored). bits and a Stop bit. The frame Break character is sent 4. Write ‘55h’ to TXREG to load the Sync character whenever the SENDB and TXEN bits (TXSTA<3> and into the transmit FIFO buffer. TXSTA<5>) are set while the Transmit Shift register is 5. After the Break has been sent, the SENDB bit is loaded with data. Note that the value of data written to reset by hardware. The Sync character now TXREG will be ignored and all ‘0’s will be transmitted. transmits in the preconfigured mode. The SENDB bit is automatically reset by hardware after When the TXREG becomes empty, as indicated by the the corresponding Stop bit is sent. This allows the user TXIF, the next data byte can be written to TXREG. to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync 17.2.6 RECEIVING A BREAK CHARACTER character in the LIN/J2602 support). The Enhanced USART module can receive a Break Note that the data value written to the TXREG for the character in two ways. Break character is ignored. The write simply serves the The first method forces configuration of the baud rate purpose of initiating the proper sequence. at a frequency of 9/13 the typical speed. This allows for The TRMT bit indicates when the transmit operation is the Stop bit transition to be at the correct sampling loca- active or Idle, just as it does during normal transmis- tion (13 bits for Break versus Start bit and 8 data bits for sion. See Figure17-10 for the timing of the Break typical data). character sequence. The second method uses the auto-wake-up feature 17.2.5.1 Break and Sync Transmit Sequence described in Section17.2.4 “Auto-Wake-up on Sync Break Character”. By enabling this feature, the The following sequence will send a message frame EUSART will sample the next two transitions on RX/DT, header made up of a Break, followed by an Auto-Baud cause an RCIF interrupt and receive the next data byte Sync byte. This sequence is typical of a LIN bus followed by another interrupt. master. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABD bit once the TXIF interrupt is observed. FIGURE 17-10: SEND BREAK CHARACTER SEQUENCE Write to TXREG Dummy Write BRG Output (Shift Clock) TX (pin) Start Bit Bit 0 Bit 1 Bit 11 Stop Bit Break TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB sampled here Auto-Cleared SENDB (Transmit Shift Reg. Empty Flag) DS39682E-page 208 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 17.3 EUSART Synchronous Once the TXREG register transfers the data to the TSR Master Mode register (occurs in one TCY), the TXREG is empty and the TXIF flag bit (PIR1<4>) is set. The interrupt can be The Synchronous Master mode is entered by setting enabled or disabled by setting or clearing the interrupt the CSRC bit (TXSTA<7>). In this mode, the data is enable bit, TXIE (PIE1<4>). TXIF is set regardless of transmitted in a half-duplex manner (i.e., transmission the state of enable bit TXIE; it cannot be cleared in and reception do not occur at the same time). When software. It will reset only when new data is loaded into transmitting data, the reception is inhibited and vice the TXREG register. versa. Synchronous mode is entered by setting bit While flag bit TXIF indicates the status of the TXREG SYNC (TXSTA<4>). In addition, enable bit SPEN register, another bit, TRMT (TXSTA<1>), shows the (RCSTA<7>) is set in order to configure the TX and RX status of the TSR register. TRMT is a read-only bit which pins to CK (clock) and DT (data) lines, respectively. is set when the TSR is empty. No interrupt logic is tied to The Master mode indicates that the processor trans- this bit so the user has to poll this bit in order to deter- mits the master clock on the CK line. Clock polarity is mine if the TSR register is empty. The TSR is not selected with the SCKP bit (BAUDCON<4>). Setting mapped in data memory so it is not available to the user. SCKP sets the Idle state on CK as high, while clearing To set up a Synchronous Master Transmission: the bit sets the Idle state as low. This option is provided to support Microwire devices with this module. 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRG16 17.3.1 EUSART SYNCHRONOUS MASTER bit, as required, to achieve the desired baud rate. TRANSMISSION 2. Enable the synchronous master serial port by setting bits, SYNC, SPEN and CSRC. The EUSART transmitter block diagram is shown in Figure17-3. The heart of the transmitter is the Transmit 3. If interrupts are desired, set enable bit, TXIE. (Serial) Shift Register (TSR). The Shift register obtains 4. If 9-bit transmission is desired, set bit, TX9. its data from the Read/Write Transmit Buffer register, 5. Enable the transmission by setting bit, TXEN. TXREG. The TXREG register is loaded with data in 6. If 9-bit transmission is selected, the ninth bit software. The TSR register is not loaded until the last should be loaded in bit, TX9D. bit has been transmitted from the previous load. As 7. Start transmission by loading data to the TXREG soon as the last bit is transmitted, the TSR is loaded register. with new data from the TXREG (if available). 8. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 17-11: SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 RC6/TX/CK pin (SCKP = 0) RC6/TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ ‘1’ Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words. © 2009 Microchip Technology Inc. DS39682E-page 209

PIC18F45J10 FAMILY FIGURE 17-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 17-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47 PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49 PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49 IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 49 TXREG EUSART Transmit Register 49 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 49 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 49 SPBRGH EUSART Baud Rate Generator Register High Byte 49 SPBRG EUSART Baud Rate Generator Register Low Byte 49 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’. DS39682E-page 210 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 17.3.2 EUSART SYNCHRONOUS 3. Ensure bits, CREN and SREN, are clear. MASTER RECEPTION 4. If interrupts are desired, set enable bit, RCIE. 5. If 9-bit reception is desired, set bit, RX9. Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, 6. If a single reception is required, set bit, SREN. SREN (RCSTA<5>), or the Continuous Receive For continuous reception, set bit, CREN. Enable bit, CREN (RCSTA<4>). Data is sampled on the 7. Interrupt flag bit, RCIF, will be set when reception RX pin on the falling edge of the clock. is complete and an interrupt will be generated if the enable bit, RCIE, was set. If enable bit SREN is set, only a single word is received. If enable bit CREN is set, the reception is continuous 8. Read the RCSTA register to get the 9th bit (if until CREN is cleared. If both bits are set, then CREN enabled) and determine if any error occurred takes precedence. during reception. To set up a Synchronous Master Reception: 9. Read the 8-bit received data by reading the RCREG register. 1. Initialize the SPBRGH:SPBRG registers for the 10. If any error occurred, clear the error by clearing appropriate baud rate. Set or clear the BRG16 bit, CREN. bit, as required, to achieve the desired baud rate. 11. If using interrupts, ensure that the GIE and PEIE bits 2. Enable the synchronous master serial port by in the INTCON register (INTCON<7:6>) are set. setting bits, SYNC, SPEN and CSRC. FIGURE 17-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RC6/TX/CK pin (SCKP = 0) RC6/TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 17-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47 PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49 PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49 IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 49 RCREG EUSART Receive Register 49 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 49 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 49 SPBRGH EUSART Baud Rate Generator Register High Byte 49 SPBRG EUSART Baud Rate Generator Register Low Byte 49 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’. © 2009 Microchip Technology Inc. DS39682E-page 211

PIC18F45J10 FAMILY 17.4 EUSART Synchronous To set up a Synchronous Slave Transmission: Slave Mode 1. Enable the synchronous slave serial port by setting bits, SYNC and SPEN, and clearing bit, Synchronous Slave mode is entered by clearing bit, CSRC. CSRC (TXSTA<7>). This mode differs from the 2. Clear bits, CREN and SREN. Synchronous Master mode in that the shift clock is sup- plied externally at the CK pin (instead of being supplied 3. If interrupts are desired, set enable bit, TXIE. internally in Master mode). This allows the device to 4. If 9-bit transmission is desired, set bit, TX9. transfer or receive data while in any low-power mode. 5. Enable the transmission by setting enable bit, TXEN. 17.4.1 EUSART SYNCHRONOUS 6. If 9-bit transmission is selected, the ninth bit SLAVE TRANSMISSION should be loaded in bit, TX9D. The operation of the Synchronous Master and Slave 7. Start transmission by loading data to the TXREG modes is identical, except in the case of the Sleep register. mode. 8. If using interrupts, ensure that the GIE and PEIE If two words are written to the TXREG and then the bits in the INTCON register (INTCON<7:6>) are SLEEP instruction is executed, the following will occur: set. a) The first word will immediately transfer to the TSR register and transmit. b) The second word will remain in the TXREG register. c) Flag bit, TXIF, will not be set. d) When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit, TXIF, will now be set. e) If enable bit, TXIE, is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. TABLE 17-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47 PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49 PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49 IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 49 TXREG EUSART Transmit Register 49 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 49 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 49 SPBRGH EUSART Baud Rate Generator Register High Byte 49 SPBRG EUSART Baud Rate Generator Register Low Byte 49 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’. DS39682E-page 212 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 17.4.2 EUSART SYNCHRONOUS SLAVE To set up a Synchronous Slave Reception: RECEPTION 1. Enable the synchronous master serial port by The operation of the Synchronous Master and Slave setting bits, SYNC and SPEN, and clearing bit, modes is identical, except in the case of Sleep, or any CSRC. Idle mode and bit, SREN, which is a “don’t care” in 2. If interrupts are desired, set enable bit, RCIE. Slave mode. 3. If 9-bit reception is desired, set bit, RX9. If receive is enabled by setting the CREN bit prior to 4. To enable reception, set enable bit, CREN. entering Sleep or any Idle mode, then a word may be 5. Flag bit, RCIF, will be set when reception is received while in this low-power mode. Once the word complete. An interrupt will be generated if is received, the RSR register will transfer the data to the enable bit, RCIE, was set. RCREG register; if the RCIE enable bit is set, the inter- 6. Read the RCSTA register to get the 9th bit (if rupt generated will wake the chip from the low-power enabled) and determine if any error occurred mode. If the global interrupt is enabled, the program will during reception. branch to the interrupt vector. 7. Read the 8-bit received data by reading the RCREG register. 8. If any error occurred, clear the error by clearing bit, CREN. 9. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 17-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47 PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49 PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49 IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 49 RCREG EUSART Receive Register 49 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 49 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 49 SPBRGH EUSART Baud Rate Generator Register High Byte 49 SPBRG EUSART Baud Rate Generator Register Low Byte 49 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’. © 2009 Microchip Technology Inc. DS39682E-page 213

PIC18F45J10 FAMILY NOTES: DS39682E-page 214 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 18.0 10-BIT ANALOG-TO-DIGITAL The ADCON0 register, shown in Register18-1, CONVERTER (A/D) MODULE controls the operation of the A/D module. The ADCON1 register, shown in Register18-2, configures The Analog-to-Digital (A/D) converter module has the functions of the port pins. The ADCON2 register, 10inputs for the 28-pin devices and 13 for the 40/44-pin shown in Register18-3, configures the A/D clock devices. This module allows conversion of an analog source, programmed acquisition time and justification. input signal to a corresponding 10-bit digital number. The module has five registers: • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) • A/D Control Register 0 (ADCON0) • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) REGISTER 18-1: ADCON0: A/D CONTROL REGISTER 0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCAL — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADCAL: A/D Calibration bit 1 = Calibration is performed on next A/D conversion 0 = Normal A/D converter operation (no calibration is performed) bit 6 Unimplemented: Read as ‘0’ bit 5-2 CHS<3:0>: Analog Channel Select bits 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5)(1,2) 0110 = Channel 6 (AN6)(1,2) 0111 = Channel 7 (AN7)(1,2) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12) 1101 = Unimplemented(2) 1110 = Unimplemented(2) 1111 = Unimplemented(2) bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress 0 = A/D Idle bit 0 ADON: A/D On bit 1 = A/D converter module is enabled 0 = A/D converter module is disabled Note 1: These channels are not implemented on 28-pin devices. 2: Performing a conversion on unimplemented channels will return a floating input measurement. © 2009 Microchip Technology Inc. DS39682E-page 215

PIC18F45J10 FAMILY REGISTER 18-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 VCFG1: Voltage Reference Configuration bit (VREF- source) 1 = VREF- (AN2) 0 = VSS bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source) 1 = VREF+ (AN3) 0 = VDD bit 3-0 PCFG<3:0>: A/D Port Configuration Control bits: PCFG<3:0> N12 N11 N10 N9 N8 (1)N7 (1)N6 (1)N5 N4 N3 N2 N1 N0 A A A A A A A A A A A A A 0000 A A A A A A A A A A A A A 0001 A A A A A A A A A A A A A 0010 A A A A A A A A A A A A A 0011 D A A A A A A A A A A A A 0100 D D A A A A A A A A A A A 0101 D D D A A A A A A A A A A 0110 D D D D A A A A A A A A A 0111 D D D D D A A A A A A A A 1000 D D D D D D A A A A A A A 1001 D D D D D D D A A A A A A 1010 D D D D D D D D A A A A A 1011 D D D D D D D D D A A A A 1100 D D D D D D D D D D A A A 1101 D D D D D D D D D D D A A 1110 D D D D D D D D D D D D A 1111 D D D D D D D D D D D D D A = Analog input D = Digital I/O Note 1: AN5 through AN7 are available only on 40/44-pin devices. DS39682E-page 216 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY REGISTER 18-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(1) bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(1) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. © 2009 Microchip Technology Inc. DS39682E-page 217

PIC18F45J10 FAMILY The analog reference voltage is software selectable to A device Reset forces all registers to their Reset state. either the device’s positive and negative supply voltage This forces the A/D module to be turned off and any (VDD and VSS), or the voltage level on the RA3/AN3/ conversion in progress is aborted. VREF+ and RA2/AN2/VREF-/CVREF pins. Each port pin associated with the A/D converter can be The A/D converter has a unique feature of being able configured as an analog input, or as a digital I/O. The to operate while the device is in Sleep mode. To oper- ADRESH and ADRESL registers contain the result of ate in Sleep, the A/D conversion clock must be derived the A/D conversion. When the A/D conversion is com- from the A/D’s internal RC oscillator. plete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit (ADCON0 register) is The output of the sample and hold is the input into the cleared and A/D Interrupt Flag bit, ADIF, is set. The block converter, which generates the result via successive diagram of the A/D module is shown in Figure18-1. approximation. FIGURE 18-1: A/D BLOCK DIAGRAM CHS<3:0> 1100 AN12 1011 AN11 1010 AN10 1001 AN9 1000 AN8 0111 AN7(1) 0110 AN6(1) 0101 AN5(1) 0100 AN4 VAIN 10-Bit (Input Voltage) 0011 AN3 A/D Converter 0010 AN2 0001 VCFG<1:0> AN1 VDD(2) 0000 AN0 X0 VREF+ X1 Reference Voltage 1X VREF- 0X VSS(2) Note 1: Channels AN5 through AN7 are not available in 28-pin devices. 2: I/O pins have diode protection to VDD and VSS. DS39682E-page 218 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY After the A/D module has been configured as desired, 2. Configure A/D interrupt (if desired): the selected channel must be acquired before the • Clear ADIF bit conversion is started. The analog input channels must • Set ADIE bit have their corresponding TRIS bits selected as an • Set GIE bit input. To determine acquisition time, see Section18.1 “A/D Acquisition Requirements”. After this acquisi- 3. Wait the required acquisition time (if required). tion time has elapsed, the A/D conversion can be 4. Start conversion: started. An acquisition time can be programmed to • Set GO/DONE bit (ADCON0<1>) occur between setting the GO/DONE bit and the actual 5. Wait for A/D conversion to complete, by either: start of the conversion. • Polling for the GO/DONE bit to be cleared The following steps should be followed to do an A/D OR conversion: • Waiting for the A/D interrupt 1. Configure the A/D module: 6. Read A/D Result registers (ADRESH:ADRESL); • Configure analog pins, voltage reference and clear bit, ADIF, if required. digital I/O (ADCON1) 7. For next conversion, go to step 1 or step 2, as • Select A/D input channel (ADCON0) required. The A/D conversion time per bit is • Select A/D acquisition time (ADCON2) defined as TAD. A minimum wait of 2 TAD is • Select A/D conversion clock (ADCON2) required before next acquisition starts. • Turn on A/D module (ADCON0) FIGURE 18-2: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V RS ANx RIC ≤ 1k SS RSS VAIN C5 PpIFN VT = 0.6V I±L1E0A0K AnGAE CHOLD = 25 pF VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to VDD various junctions RIC = Interconnect Resistance SS = Sampling Switch CHOLD = Sample/Hold Capacitance (from DAC) RSS = Sampling Switch Resistance 1 2 3 4 Sampling Switch (kΩ) © 2009 Microchip Technology Inc. DS39682E-page 219

PIC18F45J10 FAMILY 18.1 A/D Acquisition Requirements To calculate the minimum acquisition time, Equation18-1 may be used. This equation assumes For the A/D converter to meet its specified accuracy, that 1/2 LSb error is used (1024 steps for the A/D). The the charge holding capacitor (CHOLD) must be allowed 1/2 LSb error is the maximum error allowed for the A/D to fully charge to the input channel voltage level. The to meet its specified resolution. analog input model is shown in Figure18-2. The Equation18-3 shows the calculation of the minimum source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required acquisition time, TACQ. This calculation is based on the following application system required to charge the capacitor CHOLD. The sampling assumptions: switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage CHOLD = 25 pF at the analog input (due to pin leakage current). The Rs = 2.5 kΩ maximum recommended impedance for analog Conversion Error ≤ 1/2 LSb sources is 2.5kΩ. After the analog input channel is VDD = 3V→Rss = 2 kΩ selected (changed), the channel must be sampled for Temperature = 85°C (system max.) at least the minimum acquisition time before starting a conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. EQUATION 18-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 18-2: A/D MINIMUM CHARGING TIME VHOLD = (VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))) or TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) EQUATION 18-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF TAMP = 0.2 μs TCOFF = (Temp – 25°C)(0.02 μs/°C) (85°C – 25°C)(0.02 μs/°C) 1.2 μs Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms. TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) μs -(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883) μs 1.05 μs TACQ = 0.2 μs + 1 μs + 1.2 μs 2.4 μs DS39682E-page 220 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 18.2 Selecting and Configuring TABLE 18-1: TAD vs. DEVICE OPERATING Automatic Acquisition Time FREQUENCIES The ADCON2 register allows the user to select an AD Clock Source (TAD) Maximum acquisition time that occurs each time the GO/DONE Device bit is set. Operation ADCS<2:0> Frequency When the GO/DONE bit is set, sampling is stopped and 2 TOSC 000 2.86 MHz a conversion begins. The user is responsible for ensur- 4 TOSC 100 5.71 MHz ing the required acquisition time has passed between 8 TOSC 001 11.43 MHz selecting the desired input channel and setting the GO/DONE bit. This occurs when the ACQT<2:0> bits 16 TOSC 101 22.86 MHz (ADCON2<5:3>) remain in their Reset state (‘000’) and 32 TOSC 010 40.0 MHz is compatible with devices that do not offer 64 TOSC 110 40.0 MHz programmable acquisition times. RC(2) x11 1.00 MHz(1) If desired, the ACQT bits can be set to select a pro- Note 1: The RC source has a typical TAD time of grammable acquisition time for the A/D module. When 4μs. the GO/DONE bit is set, the A/D module continues to 2: For device frequencies above 1 MHz, the sample the input for the selected acquisition time, then device must be in Sleep mode for the entire automatically begins a conversion. Since the acquisi- conversion or the A/D accuracy may be out tion time is programmed, there may be no need to wait of specification. for an acquisition time between selecting a channel and setting the GO/DONE bit. 18.4 Configuring Analog Port Pins In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the The ADCON1, TRISA, TRISF and TRISH registers A/D begins sampling the currently selected channel control the operation of the A/D port pins. The port pins again. If an acquisition time is programmed, there is needed as analog inputs must have their correspond- nothing to indicate if the acquisition time has ended or ing TRIS bits set (input). If the TRIS bit is cleared if the conversion has begun. (output), the digital output level (VOH or VOL) will be converted. 18.3 Selecting the A/D Conversion The A/D operation is independent of the state of the Clock CHS<3:0> bits and the TRIS bits. The A/D conversion time per bit is defined as TAD. The Note 1: When reading the PORT register, all pins A/D conversion requires 11 TAD per 10-bit conversion. configured as analog input channels will The source of the A/D conversion clock is software read as cleared (a low level). Pins config- selectable. ured as digital inputs will convert an analog input. Analog levels on a digitally There are seven possible options for TAD: configured input will be accurately • 2 TOSC converted. • 4 TOSC 2: Analog levels on any pin defined as a • 8 TOSC digital input may cause the digital input • 16 TOSC buffer to consume current out of the • 32 TOSC device’s specification limits. • 64 TOSC • Internal RC Oscillator For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible but greater than the minimum TAD (see parameter 130 in Table24-25 for more information). Table18-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. © 2009 Microchip Technology Inc. DS39682E-page 221

PIC18F45J10 FAMILY 18.5 A/D Conversions 18.6 Use of the ECCP2 Trigger Figure18-3 shows the operation of the A/D converter An A/D conversion can be started by the “Special Event after the GO/DONE bit has been set and the Trigger” of the ECCP2 module. This requires that the ACQT<2:0> bits are cleared. A conversion is started CCP2M<3:0> bits (CCP2CON<3:0>) be programmed after the following instruction to allow entry into Sleep as ‘1011’ and that the A/D module is enabled (ADON mode before the conversion begins. bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion Figure18-4 shows the operation of the A/D converter and the Timer1 (or Timer3) counter will be reset to zero. after the GO/DONE bit has been set, the ACQT<2:0> Timer1 (or Timer3) is reset to automatically repeat the bits are set to ‘010’ and selecting a 4TAD acquisition A/D acquisition period with minimal software overhead time before the conversion starts. (moving ADRESH/ADRESL to the desired location). Clearing the GO/DONE bit during a conversion will abort The appropriate analog input channel must be selected the current conversion. The A/D Result register pair will and the minimum acquisition period is either timed by NOT be updated with the partially completed A/D the user, or an appropriate TACQ time is selected before conversion sample. This means the ADRESH:ADRESL the Special Event Trigger sets the GO/DONE bit (starts registers will continue to contain the value of the last a conversion). completed conversion (or the last value written to the If the A/D module is not enabled (ADON is cleared), the ADRESH:ADRESL registers). Special Event Trigger will be ignored by the A/D module After the A/D conversion is completed or aborted, a but will still reset the Timer1 (or Timer3) counter. 2TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. FIGURE 18-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY - TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit Next Q4: ADRESH/ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. FIGURE 18-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) TACQT Cycles TAD Cycles 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Automatic Acquisition Conversion starts Time (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues acquiring input) Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is reconnected to analog input. DS39682E-page 222 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 18.7 A/D Converter Calibration If the A/D is expected to operate while the device is in a power-managed mode, the ACQT<2:0> and The A/D converter in the PIC18F45J10 family of ADCS<2:0> bits in ADCON2 should be updated in devices includes a self-calibration feature which com- accordance with the power-managed mode clock that pensates for any offset generated within the module. will be used. After the power-managed mode is entered The calibration process is automated and is initiated by (either of the power-managed Run modes), an A/D setting the ADCAL bit (ADCON0<7>). The next time acquisition or conversion may be started. Once an the GO/DONE bit is set, the module will perform a acquisition or conversion is started, the device should “dummy” conversion (that is, with reading none of the continue to be clocked by the same power-managed input channels) and store the resulting value internally mode clock source until the conversion has been com- to compensate for offset. Thus, subsequent offsets will pleted. If desired, the device may be placed into the be compensated. corresponding power-managed Idle mode during the The calibration process assumes that the device is in a conversion. relatively steady-state operating condition. If A/D If the power-managed mode clock frequency is less calibration is used, it should be performed after each than 1MHz, the A/D RC clock source should be device Reset or if there are other major changes in selected. operating conditions. Operation in the Sleep mode requires the A/D RC clock 18.8 Operation in Power-Managed to be selected. If bits, ACQT<2:0>, are set to ‘000’ and a conversion is started, the conversion will be delayed Modes one instruction cycle to allow execution of the SLEEP The selection of the automatic acquisition time and A/D instruction and entry to Sleep mode. The IDLEN and conversion clock is determined in part by the clock SCS bits in the OSCCON register must have already source and frequency while in a power-managed mode. been cleared prior to starting the conversion. TABLE 18-2: REGISTERS ASSOCIATED WITH A/D OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47 PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49 PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49 IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49 PIR2 OSCFIF CMIF — — BCL1IF — — CCP2IF 49 PIE2 OSCFIE CMIE — — BCL1IE — — CCP2IE 49 IPR2 OSCFIP CMIP — — BCL1IP — — CCP2IP 49 ADRESH A/D Result Register High Byte 48 ADRESL A/D Result Register Low Byte 48 ADCON0 ADCAL — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 48 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 48 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 48 PORTA — — RA5 — RA3 RA2 RA1 RA0 50 TRISA — — TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 50 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 50 TRISB PORTB Data Direction Control Register 50 LATB PORTB Data Latch Register (Read and Write to Data Latch) 50 PORTE(1) — — — — — RE2 RE1 RE0 50 TRISE(1) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 50 LATE(1) — — — — — PORTE Data Latch Register 50 (Read and Write to Data Latch) Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’. © 2009 Microchip Technology Inc. DS39682E-page 223

PIC18F45J10 FAMILY NOTES: DS39682E-page 224 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 19.0 COMPARATOR MODULE The CMCON register (Register19.1) selects the comparator input and output configuration. Block The analog comparator module contains two diagrams of the various comparator configurations are comparators that can be configured in a variety of shown in Figure19-1. ways. The inputs can be selected from the analog inputs multiplexed with pins RA0 through RA5, as well as the on-chip voltage reference (see Section20.0 “Comparator Voltage Reference Module”). The digi- tal outputs (normal or inverted) are available at the pin level and can also be read through the control register. REGISTER 19-1: CMCON: COMPARATOR CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN- 0 = C2 VIN+ < C2 VIN- When C2INV = 1: 1 = C2 VIN+ < C2 VIN- 0 = C2 VIN+ > C2 VIN- bit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN- 0 = C1 VIN+ < C1 VIN- When C1INV = 1: 1 = C1 VIN+ < C1 VIN- 0 = C1 VIN+ > C1 VIN- bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted bit 4 C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted bit 3 CIS: Comparator Input Switch bit When CM<2:0> = 110: 1 = C1 VIN- connects to RA3/AN3/VREF+ C2 VIN- connects to RA2/AN2/VREF-/CVREF 0 = C1 VIN- connects to RA0/AN0 C2 VIN- connects to RA1/AN1 bit 2-0 CM<2:0>: Comparator Mode bits Figure19-1 shows the Comparator modes and the CM<2:0> bit settings. © 2009 Microchip Technology Inc. DS39682E-page 225

PIC18F45J10 FAMILY 19.1 Comparator Configuration changed, the comparator output level may not be valid for the specified mode change delay shown in There are eight modes of operation for the compara- Section24.0 “Electrical Characteristics”. tors, shown in Figure19-1. Bits, CM<2:0> of the CMCON register, are used to select these modes. The Note: Comparator interrupts should be disabled TRISA register controls the data direction of the com- during a Comparator mode change; parator pins for each mode. If the Comparator mode is otherwise, a false interrupt may occur. FIGURE 19-1: COMPARATOR I/O OPERATING MODES Comparators Reset Comparators Off (POR Default Value) CM<2:0> = 000 CM<2:0> = 111 RA0/AN0 A VIN- RA0/AN0 D VIN- RA3/AN3/ A VIN+ C1 Off (Read as ‘0’) RA3/AN3/ D VIN+ C1 Off (Read as ‘0’) VREF+ VREF+ RA1/AN1 A VIN- RA1/AN1 D VIN- RA2/AN2/ A VIN+ C2 Off (Read as ‘0’) RA2/AN2/ D VIN+ C2 Off (Read as ‘0’) VREF-/CVREF VREF-/CVREF Two Independent Comparators Two Independent Comparators with Outputs CM<2:0> = 010 CM<2:0> = 011 RA0/AN0 A VIN- RA0/AN0 A VIN- RA3/AN3/ A VIN+ C1 C1OUT RA3/AN3/ A VIN+ C1 C1OUT VREF+ VREF+ RB5/KBI1/ T0CKI/C1OUT* RA1/AN1 A VIN- RA2/AN2/ A VIN+ C2 C2OUT RA1/AN1 A VIN- VREF-/CVREF RA2/AN2/ A VIN+ C2 C2OUT VREF-/CVREF RA5/AN4/SS1/C2OUT* Two Common Reference Comparators Two Common Reference Comparators with Outputs CM<2:0> = 100 CM<2:0> = 101 RA0/AN0 A VIN- RA0/AN0 A VIN- RA3/AN3/ A VIN+ C1 C1OUT RA3/AN3/ A VIN+ C1 C1OUT VREF+ VREF+ RB5/KBI1/ T0CKI/C1OUT* RA1/AN1 A VIN- RVRAE2F/A-/CNV2/REDF VIN+ C2 C2OUT RRAA21//AANN21/ AD VVIINN-+ C2 C2OUT VREF-/CVREF RA5/AN4/SS1/C2OUT* One Independent Comparator with Output Four Inputs Multiplexed to Two Comparators CM<2:0> = 001 CM<2:0> = 110 RA0/AN0 A VIN- RA0/AN0 A CIS = 0 VIN- RVRAE3F/A+N3/ A VIN+ C1 C1OUT RVRAE3F/A+N3/ A CIS = 1 VIN+ C1 C1OUT RB5/KBI1/T0CKI/C1OUT* A RA1/AN1 CIS = 0 VIN- RA1/AN1 D VIN- RVRAE2F/A-/CNV2/REF/A CIS = 1 VIN+ C2 C2OUT RA2/AN2/ D VIN+ C2 Off (Read as ‘0’) VREF-/CVREF/ CVREF From VREF Module A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch * Setting the TRISA<5> bit will disable the comparator outputs by configuring the pins as inputs. DS39682E-page 226 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 19.2 Comparator Operation 19.3.2 INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure19-2, along with The comparator module also allows the selection of an the relationship between the analog input levels and internally generated voltage reference from the the digital output. When the analog input at VIN+ is less comparator voltage reference module. This module is than the analog input, VIN-, the output of the described in more detail in Section20.0 “Comparator comparator is a digital low level. When the analog input Voltage Reference Module”. at VIN+ is greater than the analog input, VIN-, the output The internal reference is only available in the mode of the comparator is a digital high level. The shaded where four inputs are multiplexed to two comparators areas of the output of the comparator in Figure19-2 (CM<2:0>=110). In this mode, the internal voltage represent the uncertainty due to input offsets and reference is applied to the VIN+ pin of both comparators. response time. 19.4 Comparator Response Time 19.3 Comparator Reference Response time is the minimum time, after selecting a Depending on the comparator operating mode, either new reference voltage or input source, before the an external or internal voltage reference may be used. comparator output has a valid level. If the internal ref- The analog signal present at VIN- is compared to the erence is changed, the maximum delay of the internal signal at VIN+ and the digital output of the comparator voltage reference must be considered when using the is adjusted accordingly (Figure19-2). comparator outputs. Otherwise, the maximum delay of the comparators should be used (see Section24.0 FIGURE 19-2: SINGLE COMPARATOR “Electrical Characteristics”). 19.5 Comparator Outputs VIN+ + The comparator outputs are read through the CMCON Output register. These bits are read-only. The comparator VIN- – outputs may also be directly output to the RB5 and RA5 I/O pins. When enabled, multiplexors in the output path of the RB5 and RA5 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is related to the input offset voltage and VIN- the response time given in the specifications. Figure19-3 shows the comparator output block VIN+ diagram. The TRISA bits will still function as an output enable/ disable for the RB5 and RA5 pins while in this mode. Output The polarity of the comparator outputs can be changed using the C2INV and C1INV bits (CMCON<5:4>). Note1: When reading the PORT register, all pins 19.3.1 EXTERNAL REFERENCE SIGNAL configured as analog inputs will read as a When external voltage references are used, the ‘0’. Pins configured as digital inputs will comparator module can be configured to have the com- convert an analog input according to the parators operate from the same or different reference Schmitt Trigger input specification. sources. However, threshold detector applications may 2: Analog levels on any pin defined as a require the same reference. The reference signal must digital input may cause the input buffer to be between VSS and VDD and can be applied to either consume more current than is specified. pin of the comparator(s). © 2009 Microchip Technology Inc. DS39682E-page 227

PIC18F45J10 FAMILY FIGURE 19-3: COMPARATOR OUTPUT BLOCK DIAGRAM X E L + Port Pins P TI To RB5 or UL - RA5 pin M D Q Bus CxINV Data Read CMCON EN D Q Set CMIF bit EN CL From Other Reset Comparator 19.6 Comparator Interrupts 19.7 Comparator Operation During Sleep The comparator interrupt flag is set whenever there is a change in the output value of either comparator. When a comparator is active and the device is placed Software will need to maintain information about the in Sleep mode, the comparator remains active and the status of the output bits, as read from CMCON<7:6>, to interrupt is functional, if enabled. This interrupt will determine the actual change that occurred. The CMIF wake-up the device from Sleep mode, when enabled. bit (PIR2<6>) is the Comparator Interrupt Flag. The Each operational comparator will consume additional CMIF bit must be reset by clearing it. Since it is also current, as shown in the comparator specifications. To possible to write a ‘1’ to this register, a simulated minimize power consumption while in Sleep mode, turn interrupt may be initiated. off the comparators (CM<2:0>=111) before entering Both the CMIE bit (PIE2<6>) and the PEIE bit Sleep. If the device wakes up from Sleep, the contents (INTCON<6>) must be set to enable the interrupt. In of the CMCON register are not affected. addition, the GIE bit (INTCON<7>) must also be set. If 19.8 Effects of a Reset any of these bits are clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt A device Reset forces the CMCON register to its Reset condition occurs. state, causing the comparator modules to be turned off Note: If a change in the CMCON register (CM<2:0>=111). However, the input pins (RA0 (C1OUT or C2OUT) should occur when a through RA3) are configured as analog inputs by read operation is being executed (start of default on device Reset. The I/O configuration for these the Q2 cycle), then the CMIF (PIR2 pins is determined by the setting of the PCFG<3:0> bits register) interrupt flag may not get set. (ADCON1<3:0>). Therefore, device current is minimized when analog inputs are present at Reset The user, in the Interrupt Service Routine, can clear the time. interrupt in the following manner: a) Any read or write of CMCON will end the mismatch condition. b) Clear flag bit CMIF. A mismatch condition will continue to set flag bit, CMIF. Reading CMCON will end the mismatch condition and allow flag bit, CMIF, to be cleared. DS39682E-page 228 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 19.9 Analog Input Connection range by more than 0.6V in either direction, one of the Considerations diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10kΩ is A simplified circuit for an analog input is shown in recommended for the analog sources. Any external Figure19-4. Since the analog pins are connected to a component connected to an analog input pin, such as digital output, they have reverse biased diodes to VDD a capacitor or a Zener diode, should have very little and VSS. The analog input, therefore, must be between leakage current. VSS and VDD. If the input voltage deviates from this FIGURE 19-4: COMPARATOR ANALOG INPUT MODEL VDD RS < 10k VT = 0.6V RIC Comparator AIN Input VA C5 PpIFN VT = 0.6V I±L1E0A0K AnGAE VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage TABLE 19-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 49 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 49 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 50 PIR2 OSCFIF CMIF — — BCL1IF — — CCP2IF 49 PIE2 OSCFIE CMIE — — BCL1IE — — CCP2IE 49 IPR2 OSCFIP CMIP — — BCL1IP — — CCP2IP 49 PORTA — — RA5 — RA3 RA2 RA1 RA0 50 LATA — — PORTA Data Latch Register (Read and Write to Data Latch) 50 TRISA — — TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 50 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. © 2009 Microchip Technology Inc. DS39682E-page 229

PIC18F45J10 FAMILY NOTES: DS39682E-page 230 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 20.0 COMPARATOR VOLTAGE used is selected by the CVRR bit (CVRCON<5>). The REFERENCE MODULE primary difference between the ranges is the size of the steps selected by the CVREF Selection bits The comparator voltage reference is a 16-tap resistor (CVR<3:0>), with one range offering finer resolution. ladder network that provides a selectable reference The equations used to calculate the output of the voltage. Although its primary purpose is to provide a comparator voltage reference are as follows: reference for the analog comparators, it may also be If CVRR = 1: used independently of them. CVREF = ((CVR<3:0>)/24) x CVRSRC A block diagram of the module is shown in Figure20-1. If CVRR = 0: The resistor ladder is segmented to provide two ranges CVREF = (CVRSRC x 1/4) + (((CVR<3:0>)/32) x of CVREF values and has a power-down function to CVRSRC) conserve power when the reference is not being used. The comparator reference supply voltage can come The module’s supply reference can be provided from either device VDD/VSS or an external voltage reference. from either VDD and VSS, or the external VREF+ and VREF- that are multiplexed with RA2 and RA3. The voltage source is selected by the CVRSS bit 20.1 Configuring the Comparator (CVRCON<4>). Voltage Reference The settling time of the comparator voltage reference The voltage reference module is controlled through the must be considered when changing the CVREF CVRCON register (Register20-1). The comparator output (see Table24-3 in Section24.0 “Electrical voltage reference provides two ranges of output Characteristics”). voltage, each with 16 distinct levels. The range to be REGISTER 20-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit(1) 1 = CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF pin 0 = CVREF voltage is disconnected from the RA2/AN2/VREF-/CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range) 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range) bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-) 0 = Comparator reference source, CVRSRC = VDD – VSS bit 3-0 CVR<3:0>: Comparator VREF Value Selection bits (0 ≤ (CVR<3:0>) ≤ 15) When CVRR = 1: CVREF = ((CVR<3:0>)/24) • (CVRSRC) When CVRR = 0: CVREF = (CVRSRC/4) + ((CVR<3:0>)/32) • (CVRSRC) Note 1: CVROE overrides the TRISA<2> bit setting. © 2009 Microchip Technology Inc. DS39682E-page 231

PIC18F45J10 FAMILY FIGURE 20-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 VREF+ VDD CVRSS = 0 8R CVR<3:0> R CVREN R R R X U M 16 Steps 1 CVREF o- 6-t 1 R R R CVRR 8R CVRSS = 1 VREF- CVRSS = 0 20.2 Voltage Reference Accuracy/Error 20.4 Effects of a Reset The full range of voltage reference cannot be realized A device Reset disables the voltage reference by due to the construction of the module. The transistors clearing bit, CVREN (CVRCON<7>). This Reset also on the top and bottom of the resistor ladder network disconnects the reference from the RA2 pin by clearing (Figure20-1) keep CVREF from approaching the refer- bit, CVROE (CVRCON<6>) and selects the high-voltage ence source rails. The voltage reference is derived range by clearing bit, CVRR (CVRCON<5>). The CVR from the reference source; therefore, the CVREF output value select bits are also cleared. changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be 20.5 Connection Considerations found in Section24.0 “Electrical Characteristics”. The voltage reference module operates independently 20.3 Operation During Sleep of the comparator module. The output of the reference generator may be connected to the RA2 pin if the When the device wakes up from Sleep through an CVROE bit is set. Enabling the voltage reference out- interrupt or a Watchdog Timer time-out, the contents of put onto RA2 when it is configured as a digital input will the CVRCON register are not affected. To minimize increase current consumption. Connecting RA2 as a current consumption in Sleep mode, the voltage digital output with CVRSS enabled will also increase reference should be disabled. current consumption. The RA2 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to VREF. Figure20-2 shows an example buffering technique. DS39682E-page 232 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY FIGURE 20-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18F45J10 CVREF R(1) Module + Voltage RA2 – CVREF Output Reference Output Impedance Note 1: R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>. TABLE 20-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 49 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 49 TRISA — — TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 50 Legend: Shaded cells are not used with the comparator voltage reference. © 2009 Microchip Technology Inc. DS39682E-page 233

PIC18F45J10 FAMILY NOTES: DS39682E-page 234 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 21.0 SPECIAL FEATURES OF THE 21.1.1 CONSIDERATIONS FOR CPU CONFIGURING THE PIC18F45J10 FAMILY DEVICES PIC18F45J10 family devices include several features Unlike most PIC18 microcontrollers, devices of the intended to maximize reliability and minimize cost PIC18F45J10 family do not use persistent memory through elimination of external components. These are: registers to store configuration information. The config- • Oscillator Selection uration bytes are implemented as volatile memory • Resets: which means that configuration data must be - Power-on Reset (POR) programmed each time the device is powered up. - Power-up Timer (PWRT) Configuration data is stored in the four words at the top - Oscillator Start-up Timer (OST) of the on-chip program memory space, known as the - Brown-out Reset (BOR) Flash Configuration Words. It is stored in program memory in the same order shown in Table21-1, with • Interrupts CONFIG1L at the lowest address and CONFIG3H at • Watchdog Timer (WDT) the highest. The data is automatically loaded in the • Fail-Safe Clock Monitor proper Configuration registers during device power-up. • Two-Speed Start-up When creating applications for these devices, users • Code Protection should always specifically allocate the location of the • In-Circuit Serial Programming™ (ICSP™) Flash Configuration Word for configuration data; this is The oscillator can be configured for the application to make certain that program code is not stored in this depending on frequency, power, accuracy and cost. All address when the code is compiled. of the options are discussed in detail in Section3.0 The volatile memory cells used for the Configuration “Oscillator Configurations”. bits always reset to ‘1’ on Power-on Resets. For all A complete discussion of device Resets and interrupts other type of Reset events, the previously programmed is available in previous sections of this data sheet. values are maintained and used without reloading from program memory. In addition to their Power-up and Oscillator Start-up Timers provided for Resets, the PIC18F45J10 family of The four Most Significant bits of CONFIG1H, devices have a configurable Watchdog Timer which is CONFIG2H and CONFIG3H in program memory controlled in software. should also be ‘1111’. This makes these Configuration The inclusion of an internal RC oscillator also provides Words appear to be NOP instructions in the remote event that their locations are ever executed by the additional benefits of a Fail-Safe Clock Monitor accident. Since Configuration bits are not implemented (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and in the corresponding locations, writing ‘1’s to these automatic switchover in the event of its failure. locations has no effect on device operation. Two-Speed Start-up enables code to be executed To prevent inadvertent configuration changes during almost immediately on start-up, while the primary clock code execution, all programmable Configuration bits source completes its start-up delays. are write-once. After a bit is initially programmed during All of these features are enabled and configured by a power cycle, it cannot be written to again. Changing setting the appropriate Configuration register bits. a device configuration requires a device Reset. 21.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’) or left unprogrammed (read as ‘1’) to select various device configurations. These bits are mapped starting at program memory location 300000h. A complete list is shown in Table21-1. A detailed explanation of the various bit functions is provided in Register21-1 through Register21-8. © 2009 Microchip Technology Inc. DS39682E-page 235

PIC18F45J10 FAMILY TABLE 21-1: CONFIGURATION BITS AND DEVICE IDs Default/ File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed Value(1) 300000h CONFIG1L DEBUG XINST STVREN — — — — WDTEN 111- ---1 300001h CONFIG1H —(2) —(2) —(2) —(2) —(3) CP0 — — 1111 01-- 300002h CONFIG2L IESO FCMEN — — — FOSC2 FOSC1 FOSC0 11-- -111 300003h CONFIG2H —(2) —(2) —(2) —(2) WDTPS3 WDTPS2 WDTPS1 WDTPS0 1111 1111 300004h CONFIG3L — — — — — — — — ---- ---- 300005h CONFIG3H —(2) —(2) —(2) —(2) — — — CCP2MX 1111 ---1 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(4) 3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0001 110x(4) Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’. Note 1: Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset states, the configuration bytes maintain their previously programmed states. 2: The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if it is accidentally executed. 3: This bit should always be maintained as ‘0’. 4: See Register21-7 and Register21-8 for DEVID values. These registers are read-only and cannot be programmed by the user. DS39682E-page 236 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY REGISTER 21-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h) R/WO-1 R/WO-1 R/WO-1 U-0 U-0 U-0 U-0 R/WO-1 DEBUG XINST STVREN — — — — WDTEN bit 7 bit 0 Legend: R = Readable bit WO = Write Once bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug bit 6 XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode) bit 5 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Reset on stack overflow/underflow enabled 0 = Reset on stack overflow/underflow disabled bit 4-1 Unimplemented: Read as ‘0’ bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on SWDTEN bit) REGISTER 21-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) U-0 U-0 U-0 U-0 U-0 R/WO-1 U-0 U-0 —(1) —(1) —(1) —(1) —(2) CP0 — — bit 7 bit 0 Legend: R = Readable bit WO = Write Once bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘1’(1) bit 3 Unimplemented: Read as ‘0’(2) bit 2 CP0: Code Protection bit 1 = Program memory is not code-protected 0 = Program memory is code-protected bit 1-0 Unimplemented: Read as ‘0’ Note 1: The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if it is accidentally executed. 2: This bit should always be maintained as ‘0’. © 2009 Microchip Technology Inc. DS39682E-page 237

PIC18F45J10 FAMILY REGISTER 21-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) R/WO-1 R/WO-1 U-0 U-0 U-0 R/WO-1 R/WO-1 R/WO-1 IESO FCMEN — — — FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit WO = Write Once bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit 1 = Two-Speed Start-up enabled 0 = Two-Speed Start-up disabled bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled bit 5-3 Unimplemented: Read as ‘0’ bit 2 FOSC2: Default/Reset System Clock Select bit 1 = Clock selected by FOSC<1:0> as system clock is enabled when OSCCON<1:0> = 00 0 = INTRC enabled as system clock when OSCCON<1:0> = 00 bit 1-0 FOSC<1:0>: Oscillator Selection bits 11 = EC oscillator, PLL enabled and under software control, CLKO function on OSC2 10 = EC oscillator, CLKO function on OSC2 01 = HS oscillator, PLL enabled and under software control 00 = HS oscillator DS39682E-page 238 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY REGISTER 21-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 U-0 R/WO-1 R/WO-1 R/WO-1 R/WO-1 —(1) —(1) —(1) —(1) WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: R = Readable bit WO = Write Once bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘1’(1) bit 3-0 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 Note 1: The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if it is accidentally executed. © 2009 Microchip Technology Inc. DS39682E-page 239

PIC18F45J10 FAMILY REGISTER 21-5: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit WO = Write Once bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Unimplemented: Read as ‘0’ REGISTER 21-6: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/WO-1 —(1) —(1) —(1) —(1) — — — CCP2MX bit 7 bit 0 Legend: R = Readable bit WO = Write Once bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 Unimplemented: Read as ‘1’(1) bit 0 CCP2MX: CCP2 MUX bit 1 = CCP2 is multiplexed with RC1 0 = CCP2 is multiplexed with RB3 Note 1: The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if it is accidentally executed. DS39682E-page 240 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY REGISTER 21-7: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F45J10 FAMILY DEVICES R R R R R R R R DEV2(1) DEV1(1) DEV0(1) REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Read-only bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-5 DEV<2:0>: Device ID bits 011 = PIC18LF4XJ10 010 = PIC18LF2XJ10 001 = PIC18F4XJ10 000 = PIC18F2XJ10 bit 4-0 REV<4:0>: Revision ID bits These bits are used to indicate the device revision. Note 1: Where values for DEV<2:0> are shared by more than one device number, the specific device is always identified by using the entire DEV<10:0> bit sequence. REGISTER 21-8: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F45J10 FAMILY DEVICES R R R R R R R R DEV10(1) DEV9(1) DEV8(1) DEV7(1) DEV6(1) DEV5(1) DEV4(1) DEV3(1) bit 7 bit 0 Legend: R = Read-only bit bit 7-0 DEV<10:3>: Device ID bits(1) These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number. 0001 1100 = PIC18FX5J10 devices 0001 1101 = PIC18FX4J10 devices Note 1: The values for DEV<10:3> may be shared with other device families. The specific device is always identified by using the entire DEV<10:0> bit sequence. © 2009 Microchip Technology Inc. DS39682E-page 241

PIC18F45J10 FAMILY 21.2 Watchdog Timer (WDT) Note1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts For PIC18F45J10 family devices, the WDT is driven by when executed. the INTRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT period 2: When a CLRWDT instruction is executed, is 4ms and has the same stability as the INTRC the postscaler count will be cleared. oscillator. The 4ms period of the WDT is multiplied by a 16-bit 21.2.1 CONTROL REGISTER postscaler. Any output of the WDT postscaler is selected The WDTCON register (Register21-9) is a readable by a multiplexor, controlled by the WDTPS bits in Config- and writable register. The SWDTEN bit enables or uration Register 2H. Available periods range from about disables WDT operation. 4ms to 135seconds (2.25minutes) depending on volt- age, temperature and Watchdog postscaler. The WDT and postscaler are cleared whenever a SLEEP or CLRWDT instruction is executed, or a clock failure (primary or Timer1 oscillator) has occurred. FIGURE 21-1: WDT BLOCK DIAGRAM Enable WDT SWDTEN INTRC Control WDT Counter INTRC Oscillator ÷128 Wake-up from Power-Managed Modes CLRWDT Programmable Postscaler Reset WDT All Device Resets 1:1 to 1:32,768 Reset WDT 4 WDTPS<3:0> Sleep REGISTER 21-9: WDTCON: WATCHDOG TIMER CONTROL REGISTER u-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled. TABLE 21-2: SUMMARY OF WATCHDOG TIMER REGISTERS Reset Values Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page RCON IPEN — CM RI TO PD POR BOR 48 WDTCON — — — — — — — SWDTEN 48 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer. DS39682E-page 242 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 21.3 On-Chip Voltage Regulator 21.3.1 ON-CHIP REGULATOR AND BOR When the on-chip regulator is enabled, PIC18F45J10 Note: The on-chip voltage regulator is only family devices also have a simple brown-out capability. available in parts designated with an “F”, If the voltage supplied to the regulator is inadequate to such as PIC18F45J10. maintain a regulated level, the regulator Reset circuitry In parts designated “LF”, the microcontroller core is will generate a BOR Reset. This event is captured by powered from an external source that is separate from the BOR flag bit (RCON<0>). VDD. This voltage is supplied on the VDDCORE pin. The operation of the BOR is described in more detail in In “F” devices, a low-ESR capacitor must be connected Section5.4 “Brown-out Reset (BOR) to the VDDCORE/VCAP pin for proper device operation. (PIC18F2XJ10/4XJ10 Devices Only)” and In parts designated with an “LF” part number (i.e., Section5.4.1 “Detecting BOR”. The brown-out voltage PIC18LF45J10), power to the core must be supplied on levels are specific in Section 23.1 “DC Characteristics: VDDCORE/VCAP. It is always good design practice to Supply Voltage”. have sufficient capacitance on all supply pins. Examples are shown in Figure21-2. 21.3.2 POWER-UP REQUIREMENTS Note: In parts designated with an “LF”, such as The on-chip regulator is designed to meet the power-up PIC18LF45J10, VDDCORE must never requirements for the device. While powering up, exceed VDD. VDDCORE must never exceed VDD by 0.3 volts. The specifications for core voltage and capacitance are listed inTable24-4 of Section24.0 “Electrical Characteristics”. FIGURE 21-2: CONNECTIONS FOR THE ON-CHIP REGULATOR PIC18FXXJ10 Devices (Regulator Enabled): 3.3V PIC18FXXJ10 VDD VDDCORE/VCAP CEFC VSS PIC18LFXXJ10 Devices (Regulator Disabled): 2.5V PIC18LFXXJ10 VDD VDDCORE/VCAP VSS OR 2.5V 3.3V PIC18LFXXJ10 VDD VDDCORE/VCAP VSS © 2009 Microchip Technology Inc. DS39682E-page 243

PIC18F45J10 FAMILY 21.4 Two-Speed Start-up In all other power-managed modes, Two-Speed Start-up is not used. The device will be clocked by the The Two-Speed Start-up feature helps to minimize the currently selected clock source until the primary clock latency period, from oscillator start-up to code execu- source becomes available. The setting of the IESO bit tion, by allowing the microcontroller to use the INTRC is ignored. oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO 21.4.1 SPECIAL CONSIDERATIONS FOR Configuration bit. USING TWO-SPEED START-UP Two-Speed Start-up should be enabled only if the While using the INTRC oscillator in Two-Speed primary oscillator mode is HS (Crystal-Based) modes. Start-up, the device still obeys the normal command Since the EC mode does not require an OST start-up sequences for entering power-managed modes, delay, Two-Speed Start-up should be disabled. including serial SLEEP instructions (refer to When enabled, Resets and wake-ups from Sleep mode Section4.1.4 “Multiple Sleep Commands”). In cause the device to configure itself to run from the practice, this means that user code can change the internal oscillator block as the clock source, following SCS<1:0> bit settings or issue SLEEP instructions the time-out of the Power-up Timer after a POR Reset before the OST times out. This would allow an applica- is enabled. This allows almost immediate code execu- tion to briefly wake-up, perform routine “housekeeping” tion while the primary oscillator starts and the OST is tasks and return to Sleep before the device starts to running. Once the OST times out, the device operate from the primary oscillator. automatically switches to PRI_RUN mode. User code can also check if the primary clock source is currently providing the device clocking by checking the status of the OSTS bit (OSCCON<3>). If the bit is set, the primary oscillator is providing the clock. Otherwise, the internal oscillator block is providing the clock during wake-up from Reset or Sleep mode. FIGURE 21-3: TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 INTOSC OSC1 TOST(1) CPU Clock Peripheral Clock Program PC PC + 2 PC + 4 PC + 6 Counter Wake From Interrupt Event OSTS bit Set Note1: TOST = 1024 TOSC. These intervals are not shown to scale. DS39682E-page 244 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 21.5 Fail-Safe Clock Monitor To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide The Fail-Safe Clock Monitor (FSCM) allows the a higher clock speed by setting bits IRCF<2:0> microcontroller to continue operation in the event of an immediately after Reset. For wake-ups from Sleep, the external oscillator failure by automatically switching the INTOSC or postscaler clock sources can be selected device clock to the internal oscillator block. The FSCM by setting IRCF<2:0> prior to entering Sleep mode. function is enabled by setting the FCMEN The FSCM will detect failures of the primary or second- Configuration bit. ary clock sources only. If the internal oscillator block When FSCM is enabled, the INTRC oscillator runs at fails, no failure would be detected, nor would any action all times to monitor clocks to peripherals and provide a be possible. backup clock in the event of a clock failure. Clock monitoring (shown in Figure21-4) is accomplished by 21.5.1 FSCM AND THE WATCHDOG TIMER creating a sample clock signal which is the INTRC out- Both the FSCM and the WDT are clocked by the put divided by 64. This allows ample time between INTRC oscillator. Since the WDT operates with a FSCM sample clocks for a peripheral clock edge to separate divider and counter, disabling the WDT has occur. The peripheral device clock and the sample no effect on the operation of the INTRC oscillator when clock are presented as inputs to the Clock Monitor latch the FSCM is enabled. (CM). The CM is set on the falling edge of the device clock source but cleared on the rising edge of the As already noted, the clock source is switched to the sample clock. INTRC clock when a clock failure is detected; this may mean a substantial change in the speed of code execu- FIGURE 21-4: FSCM BLOCK DIAGRAM tion. If the WDT is enabled with a small prescale value, a decrease in clock speed allows a WDT time-out to Clock Monitor occur and a subsequent device Reset. For this reason, Latch (CM) (edge-triggered) Fail-Safe Clock Monitor events also reset the WDT and Peripheral postscaler, allowing it to start timing from when execu- S Q Clock tion speed was changed and decreasing the likelihood of an erroneous time-out. INTRC 21.5.2 EXITING FAIL-SAFE OPERATION ÷ 64 C Q Source The fail-safe condition is terminated by either a device (32 μs) 488 Hz Reset or by entering a power-managed mode. On (2.048 ms) Reset, the controller starts the primary clock source specified in Configuration Register 2H (with the OST Clock oscillator, start-up delays if running in HS mode). The Failure INTRC oscillator provides the device clock until the Detected primary clock source becomes ready (similar to a Two-Speed Start-up). The clock source is then Clock failure is tested for on the falling edge of the switched to the primary clock (indicated by the OSTS sample clock. If a sample clock falling edge occurs bit in the OSCCON register becoming set). The while CM is still set, a clock failure has been detected Fail-Safe Clock Monitor then resumes monitoring the (Figure21-5). This causes the following: peripheral clock. • the FSCM generates an oscillator fail interrupt by The primary clock source may never become ready setting bit, OSCFIF (PIR2<7>); during start-up. In this case, operation is clocked by the • the device clock source is switched to the internal INTRC oscillator. The OSCCON register will remain in oscillator block (OSCCON is not updated to show its Reset state until a power-managed mode is entered. the current clock source – this is the fail-safe condition); and • the WDT is reset. During switchover, the postscaler frequency from the internal oscillator block may not be sufficiently stable for timing sensitive applications. In these cases, it may be desirable to select another clock configuration and enter an alternate power-managed mode. This can be done to attempt a partial recovery or execute a controlled shutdown. See Section4.1.4 “Multiple Sleep Commands” and Section21.4.1 “Special Considerations for Using Two-Speed Start-up” for more details. © 2009 Microchip Technology Inc. DS39682E-page 245

PIC18F45J10 FAMILY FIGURE 21-5: FSCM TIMING DIAGRAM Sample Clock Device Oscillator Clock Failure Output CM Output (Q) Failure Detected OSCFIF CM Test CM Test CM Test Note: The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 21.5.3 FSCM INTERRUPTS IN 21.5.4 POR OR WAKE-UP FROM SLEEP POWER-MANAGED MODES The FSCM is designed to detect oscillator failure at any By entering a power-managed mode, the clock point after the device has exited Power-on Reset multiplexor selects the clock source selected by the (POR) or low-power Sleep mode. When the primary OSCCON register. Fail-Safe Monitoring of the device clock is either EC or INTRC modes, monitoring power-managed clock source resumes in the can begin immediately following these events. power-managed mode. For HS mode, the situation is somewhat different. If an oscillator failure occurs during power-managed Since the oscillator may require a start-up time consid- operation, the subsequent events depend on whether erably longer than the FSCM sample clock time, a false or not the oscillator failure interrupt is enabled. If clock failure may be detected. To prevent this, the enabled (OSCFIF=1), code execution will be clocked internal oscillator block is automatically configured as by the INTOSC multiplexor. An automatic transition the device clock and functions until the primary clock is back to the failed clock source will not occur. stable (the OST timer has timed out). This is identical to Two-Speed Start-up mode. Once the primary clock is If the interrupt is disabled, subsequent interrupts while stable, the INTRC returns to its role as the FSCM in Idle mode will cause the CPU to begin executing source. instructions while being clocked by the INTOSC source. Note: The same logic that prevents false oscilla- tor failure interrupts on POR, or wake from Sleep, will also prevent the detection of the oscillator’s failure to start at all following these events. This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start. Even so, no oscillator failure interrupt will be flagged. As noted in Section21.4.1 “Special Considerations for Using Two-Speed Start-up”, it is also possible to select another clock configuration and enter an alternate power-managed mode while waiting for the primary clock to become stable. When the new power-managed mode is selected, the primary clock is disabled. DS39682E-page 246 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 21.6 Program Verification and 21.7 In-Circuit Serial Programming Code Protection PIC18F45J10 family microcontrollers can be serially For all devices in the PIC18F45J10 family of devices, programmed while in the end application circuit. This is the on-chip program memory space is treated as a simply done with two lines for clock and data and three single block. Code protection for this block is controlled other lines for power, ground and the programming by one Configuration bit, CP0. This bit inhibits external voltage. This allows customers to manufacture boards reads and writes to the program memory space. It has with unprogrammed devices and then program the no direct effect in normal execution mode. microcontroller just before shipping the product. This also allows the most recent firmware or a custom 21.6.1 CONFIGURATION REGISTER firmware to be programmed. PROTECTION 21.8 In-Circuit Debugger The Configuration registers are protected against untoward changes or reads in two ways. The primary When the DEBUG Configuration bit is programmed to protection is the write-once feature of the Configuration a ‘0’, the In-Circuit Debugger functionality is enabled. bits which prevents reconfiguration once the bit has This function allows simple debugging functions when been programmed during a power cycle. To safeguard used with MPLAB® IDE. When the microcontroller has against unpredictable events, Configuration bit this feature enabled, some resources are not available changes resulting from individual cell-level disruptions for general use. Table21-3 shows which resources are (such as ESD events) will cause a parity error and required by the background debugger. trigger a device Reset. The data for the Configuration registers is derived from TABLE 21-3: DEBUGGER RESOURCES the Flash Configuration Words in program memory. I/O pins: RB6, RB7 When the CP0 bit is set, the source data for device Stack: 2 levels configuration is also protected as a consequence. Program Memory: 512 bytes Data Memory: 32 bytes © 2009 Microchip Technology Inc. DS39682E-page 247

PIC18F45J10 FAMILY NOTES: DS39682E-page 248 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 22.0 INSTRUCTION SET SUMMARY The literal instructions may use some of the following operands: PIC18F45J10 family devices incorporate the standard • A literal value to be loaded into a file register set of 75 PIC18 core instructions, as well as an extended (specified by ‘k’) set of 8 new instructions, for the optimization of code that is recursive or that utilizes a software stack. The • The desired FSR register to load the literal value extended set is discussed later in this section. into (specified by ‘f’) • No operand required 22.1 Standard Instruction Set (specified by ‘—’) The control instructions may use some of the following The standard PIC18 instruction set adds many operands: enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from these • A program memory address (specified by ‘n’) PIC MCU instruction sets. Most instructions are a sin- • The mode of the CALL or RETURN instructions gle program memory word (16 bits), but there are four (specified by ‘s’) instructions that require two program memory • The mode of the table read and table write locations. instructions (specified by ‘m’) Each single-word instruction is a 16-bit word divided • No operand required into an opcode, which specifies the instruction type and (specified by ‘—’) one or more operands, which further specify the All instructions are a single word, except for four operation of the instruction. double-word instructions. These instructions were The instruction set is highly orthogonal and is grouped made double-word to contain the required information into four basic categories: in 32 bits. In the second word, the 4 MSbs are ‘1’s. If this second word is executed as an instruction (by • Byte-oriented operations itself), it will execute as a NOP. • Bit-oriented operations All single-word instructions are executed in a single • Literal operations instruction cycle, unless a conditional test is true or the • Control operations program counter is changed as a result of the instruc- The PIC18 instruction set summary in Table22-2 lists tion. In these cases, the execution takes two instruction byte-oriented, bit-oriented, literal and control cycles, with the additional instruction cycle(s) executed operations. Table22-1 shows the opcode field as a NOP. descriptions. The double-word instructions execute in two instruction Most byte-oriented instructions have three operands: cycles. 1. The file register (specified by ‘f’) One instruction cycle consists of four oscillator periods. 2. The destination of the result (specified by ‘d’) Thus, for an oscillator frequency of 4MHz, the normal 3. The accessed memory (specified by ‘a’) instruction execution time is 1μs. If a conditional test is true, or the program counter is changed as a result of The file register designator ‘f’ specifies which file an instruction, the instruction execution time is 2 μs. register is to be used by the instruction. The destination Two-word branch instructions (if true) would take 3 μs. designator ‘d’ specifies where the result of the opera- Figure22-1 shows the general formats that the instruc- tion is to be placed. If ‘d’ is zero, the result is placed in tions can have. All examples use the convention ‘nnh’ the WREG register. If ‘d’ is one, the result is placed in to represent a hexadecimal number. the file register specified in the instruction. The Instruction Set Summary, shown in Table22-2, All bit-oriented instructions have three operands: lists the standard instructions recognized by the 1. The file register (specified by ‘f’) Microchip Assembler (MPASMTM). 2. The bit in the file register (specified by ‘b’) Section22.1.1 “Standard Instruction Set” provides 3. The accessed memory (specified by ‘a’) a description of each instruction. The bit field designator ‘b’ selects the number of the bit affected by the operation, while the file register designator ‘f’ represents the number of the file in which the bit is located. © 2009 Microchip Technology Inc. DS39682E-page 249

PIC18F45J10 FAMILY TABLE 22-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. d Destination select bit d = 0: store result in WREG d = 1: store result in file register f dest Destination: either the WREG register or the specified register file location. f 8-bit register file address (00h to FFh) or 2-bit FSR designator (0h to 3h). f 12-bit register file address (000h to FFFh). This is the source address. s f 12-bit register file address (000h to FFFh). This is the destination address. d GIE Global Interrupt Enable bit. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) +* Pre-Increment register (such as TBLPTR with table reads and writes) n The relative address (2’s complement number) for relative branch instructions or the direct address for Call/Branch and Return instructions. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. PD Power-down bit. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) TBLPTR 21-bit Table Pointer (points to a program memory location). TABLAT 8-bit Table Latch. TO Time-out bit. TOS Top-of-Stack. u Unused or unchanged. WDT Watchdog Timer. WREG Working register (accumulator). x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. z 7-bit offset value for indirect addressing of register files (source). s z 7-bit offset value for indirect addressing of register files (destination). d { } Optional argument. [text] Indicates an indexed address. (text) The contents of text. [expr]<n> Specifies bit n of the register indicated by the pointer expr. → Assigned to. < > Register bit field. ∈ In the set of. italics User-defined term (font is Courier New). DS39682E-page 250 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY FIGURE 22-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations Example Instruction 15 10 9 8 7 0 OPCODE d a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2 15 12 11 0 1111 f (Destination FILE #) f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 0 OPCODE k (literal) MOVLW 7Fh k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 0 OPCODE n<7:0> (literal) GOTO Label 15 12 11 0 1111 n<19:8> (literal) n = 20-bit immediate value 15 8 7 0 OPCODE S n<7:0> (literal) CALL MYFUNC 15 12 11 0 1111 n<19:8> (literal) S = Fast bit 15 11 10 0 OPCODE n<10:0> (literal) BRA MYFUNC 15 8 7 0 OPCODE n<7:0> (literal) BC MYFUNC © 2009 Microchip Technology Inc. DS39682E-page 251

PIC18F45J10 FAMILY TABLE 22-2: PIC18FXXXX INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED OPERATIONS ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2 CLRF f, a Clear f 1 0110 101a ffff ffff Z 2 COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2 CPFSEQ f, a Compare f with WREG, Skip = 1 (2 or 3) 0110 001a ffff ffff None 4 CPFSGT f, a Compare f with WREG, Skip > 1 (2 or 3) 0110 010a ffff ffff None 4 CPFSLT f, a Compare f with WREG, Skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2 DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4 DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2 INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4 INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4 INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2 IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2 MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1 MOVFF fs, fd Move fs (source) to 1st Word 2 1100 ffff ffff ffff None fd (destination) 2nd Word 1111 ffff ffff ffff MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2 NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2 RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N SETF f, a Set f 1 0110 100a ffff ffff None 1, 2 SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N Borrow SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2 SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N Borrow SWAPF f, d, a Swap Nibbles in f 1 0011 10da ffff ffff None 4 TSTFSZ f, a Test f, Skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2 XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS39682E-page 252 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY TABLE 22-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BIT-ORIENTED OPERATIONS BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2 BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2 BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4 BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4 BTG f, d, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2 CONTROL OPERATIONS BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None CALL n, s Call subroutine 1st Word 2 1110 110s kkkk kkkk None 2nd Word 1111 kkkk kkkk kkkk CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C GOTO n Go to address 1st Word 2 1110 1111 kkkk kkkk None 2nd Word 1111 kkkk kkkk kkkk NOP — No Operation 1 0000 0000 0000 0000 None NOP — No Operation 1 1111 xxxx xxxx xxxx None 4 POP — Pop Top of Return Stack (TOS) 1 0000 0000 0000 0110 None PUSH — Push Top of Return Stack (TOS) 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 1nnn nnnn nnnn None RESET Software Device Reset 1 0000 0000 1111 1111 All RETFIE s Return from Interrupt Enable 2 0000 0000 0001 000s GIE/GIEH, PEIE/GIEL RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. © 2009 Microchip Technology Inc. DS39682E-page 253

PIC18F45J10 FAMILY TABLE 22-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb LITERAL OPERATIONS ADDLW k Add Literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND Literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR Literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move Literal (12-bit) 2nd Word 2 1110 1110 00ff kkkk None to FSR(f) 1st Word 1111 0000 kkkk kkkk MOVLB k Move Literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move Literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply Literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from Literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR Literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with Post-Increment 0000 0000 0000 1001 None TBLRD*- Table Read with Post-Decrement 0000 0000 0000 1010 None TBLRD+* Table Read with Pre-Increment 0000 0000 0000 1011 None TBLWT* Table Write 2 0000 0000 0000 1100 None TBLWT*+ Table Write with Post-Increment 0000 0000 0000 1101 None TBLWT*- Table Write with Post-Decrement 0000 0000 0000 1110 None TBLWT+* Table Write with Pre-Increment 0000 0000 0000 1111 None Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned. 3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS39682E-page 254 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 22.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW k Syntax: ADDWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (W) + k → W a ∈ [0,1] Status Affected: N, OV, C, DC, Z Operation: (W) + (f) → dest Encoding: 0000 1111 kkkk kkkk Status Affected: N, OV, C, DC, Z Description: The contents of W are added to the Encoding: 0010 01da ffff ffff 8-bit literal ‘k’ and the result is placed in W. Description: Add W to register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the Words: 1 result is stored back in register ‘f’ Cycles: 1 (default). Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank (default). Decode Read Process Write to W If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Example: ADDLW 15h Section22.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. W = 10h After Instruction Words: 1 W = 25h Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWF REG, 0, 0 Before Instruction W = 17h REG = 0C2h After Instruction W = 0D9h REG = 0C2h Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). © 2009 Microchip Technology Inc. DS39682E-page 255

PIC18F45J10 FAMILY ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC f {,d {,a}} Syntax: ANDLW k Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255 d ∈ [0,1] Operation: (W) .AND. k → W a ∈ [0,1] Status Affected: N, Z Operation: (W) + (f) + (C) → dest Encoding: 0000 1011 kkkk kkkk Status Affected: N,OV, C, DC, Z Description: The contents of W are ANDed with the Encoding: 0010 00da ffff ffff 8-bit literal ‘k’. The result is placed in W. Description: Add W, the Carry flag and data memory Words: 1 location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is Cycles: 1 placed in data memory location ‘f’. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Decode Read literal Process Write to W If ‘a’ is ‘0’ and the extended instruction ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: ANDLW 05Fh mode whenever f ≤ 95 (5Fh). See Section22.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed W = A3h Literal Offset Mode” for details. After Instruction Words: 1 W = 03h Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: ADDWFC REG, 0, 1 Before Instruction Carry bit = 1 REG = 02h W = 4Dh After Instruction Carry bit = 0 REG = 02h W = 50h DS39682E-page 256 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY ANDWF AND W with f BC Branch if Carry Syntax: ANDWF f {,d {,a}} Syntax: BC n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 d ∈ [0,1] Operation: if Carry bit is ‘1’, a ∈ [0,1] (PC) + 2 + 2n → PC Operation: (W) .AND. (f) → dest Status Affected: None Status Affected: N, Z Encoding: 1110 0010 nnnn nnnn Encoding: 0001 01da ffff ffff Description: If the Carry bit is ‘1’, then the program Description: The contents of W are ANDed with will branch. register ‘f’. If ‘d’ is ‘0’, the result is stored The 2’s complement number, ‘2n’, is in W. If ‘d’ is ‘1’, the result is stored back added to the PC. Since the PC will have in register ‘f’ (default). incremented to fetch the next If ‘a’ is ‘0’, the Access Bank is selected. instruction, the new address will be If ‘a’ is ‘1’, the BSR is used to select the PC+2+2n. This instruction is then a GPR bank (default). two-cycle instruction. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f ≤ 95 (5Fh). See Q Cycle Activity: Section22.2.3 “Byte-Oriented and If Jump: Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4 Literal Offset Mode” for details. Decode Read literal Process Write to PC Words: 1 ‘n’ Data Cycles: 1 No No No No operation operation operation operation Q Cycle Activity: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read literal Process No register ‘f’ Data destination ‘n’ Data operation Example: ANDWF REG, 0, 0 Example: HERE BC 5 Before Instruction Before Instruction W = 17h PC = address (HERE) REG = C2h After Instruction After Instruction If Carry = 1; W = 02h PC = address (HERE + 12) REG = C2h If Carry = 0; PC = address (HERE + 2) © 2009 Microchip Technology Inc. DS39682E-page 257

PIC18F45J10 FAMILY BCF Bit Clear f BN Branch if Negative Syntax: BCF f, b {,a} Syntax: BN n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 0 ≤ b ≤ 7 Operation: if Negative bit is ‘1’, a ∈ [0,1] (PC) + 2 + 2n → PC Operation: 0 → f<b> Status Affected: None Status Affected: None Encoding: 1110 0110 nnnn nnnn Encoding: 1001 bbba ffff ffff Description: If the Negative bit is ‘1’, then the Description: Bit ‘b’ in register ‘f’ is cleared. program will branch. If ‘a’ is ‘0’, the Access Bank is selected. The 2’s complement number, ‘2n’, is If ‘a’ is ‘1’, the BSR is used to select the added to the PC. Since the PC will have GPR bank (default). incremented to fetch the next If ‘a’ is ‘0’ and the extended instruction instruction, the new address will be set is enabled, this instruction operates PC+2+2n. This instruction is then a in Indexed Literal Offset Addressing two-cycle instruction. mode whenever f ≤ 95 (5Fh). See Words: 1 Section22.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Cycles: 1(2) Literal Offset Mode” for details. Q Cycle Activity: Words: 1 If Jump: Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to PC Q Cycle Activity: ‘n’ Data Q1 Q2 Q3 Q4 No No No No Decode Read Process Write operation operation operation operation register ‘f’ Data register ‘f’ If No Jump: Q1 Q2 Q3 Q4 Example: BCF FLAG_REG, 7, 0 Decode Read literal Process No Before Instruction ‘n’ Data operation FLAG_REG = C7h After Instruction Example: HERE BN Jump FLAG_REG = 47h Before Instruction PC = address (HERE) After Instruction If Negative = 1; PC = address (Jump) If Negative = 0; PC = address (HERE + 2) DS39682E-page 258 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC n Syntax: BNN n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘0’, Operation: if Negative bit is ‘0’, (PC) + 2 + 2n → PC (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn Description: If the Carry bit is ‘0’, then the program Description: If the Negative bit is ‘0’, then the will branch. program will branch. The 2’s complement number, ‘2n’, is The 2’s complement number, ‘2n’, is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC+2+2n. This instruction is then a PC+2+2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC ‘n’ Data ‘n’ Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNC Jump Example: HERE BNN Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Carry = 0; If Negative = 0; PC = address (Jump) PC = address (Jump) If Carry = 1; If Negative = 1; PC = address (HERE + 2) PC = address (HERE + 2) © 2009 Microchip Technology Inc. DS39682E-page 259

PIC18F45J10 FAMILY BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV n Syntax: BNZ n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘0’, Operation: if Zero bit is ‘0’, (PC) + 2 + 2n → PC (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn Description: If the Overflow bit is ‘0’, then the Description: If the Zero bit is ‘0’, then the program program will branch. will branch. The 2’s complement number, ‘2n’, is The 2’s complement number, ‘2n’, is added to the PC. Since the PC will have added to the PC. Since the PC will have incremented to fetch the next incremented to fetch the next instruction, the new address will be instruction, the new address will be PC+2+2n. This instruction is then a PC+2+2n. This instruction is then a two-cycle instruction. two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: Q Cycle Activity: If Jump: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC ‘n’ Data ‘n’ Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump: If No Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No ‘n’ Data operation ‘n’ Data operation Example: HERE BNOV Jump Example: HERE BNZ Jump Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If Overflow = 0; If Zero = 0; PC = address (Jump) PC = address (Jump) If Overflow = 1; If Zero = 1; PC = address (HERE + 2) PC = address (HERE + 2) DS39682E-page 260 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY BRA Unconditional Branch BSF Bit Set f Syntax: BRA n Syntax: BSF f, b {,a} Operands: -1024 ≤ n ≤ 1023 Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 Operation: (PC) + 2 + 2n → PC a ∈ [0,1] Status Affected: None Operation: 1 → f<b> Encoding: 1101 0nnn nnnn nnnn Status Affected: None Description: Add the 2’s complement number, ‘2n’, to Encoding: 1000 bbba ffff ffff the PC. Since the PC will have incremented to fetch the next instruction, Description: Bit ‘b’ in register ‘f’ is set. the new address will be PC+2+2n. This If ‘a’ is ‘0’, the Access Bank is selected. instruction is a two-cycle instruction. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 2 set is enabled, this instruction operates Q Cycle Activity: in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Q1 Q2 Q3 Q4 Section22.2.3 “Byte-Oriented and Decode Read literal Process Write to PC Bit-Oriented Instructions in Indexed ‘n’ Data Literal Offset Mode” for details. No No No No Words: 1 operation operation operation operation Cycles: 1 Q Cycle Activity: Example: HERE BRA Jump Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write PC = address (HERE) register ‘f’ Data register ‘f’ After Instruction PC = address (Jump) Example: BSF FLAG_REG, 7, 1 Before Instruction FLAG_REG = 0Ah After Instruction FLAG_REG = 8Ah © 2009 Microchip Technology Inc. DS39682E-page 261

PIC18F45J10 FAMILY BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 0 ≤ b < 7 a ∈ [0,1] a ∈ [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped. If bit ‘b’ is ‘0’, then instruction is skipped. If bit ‘b’ is ‘1’, then the next instruction fetched during the the next instruction fetched during the current instruction execution is discarded current instruction execution is discarded and a NOP is executed instead, making and a NOP is executed instead, making this a two-cycle instruction. this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). GPR bank (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in set is enabled, this instruction operates Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). mode whenever f ≤ 95 (5Fh). See Section22.2.3 “Byte-Oriented and See Section22.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process No Decode Read Process No register ‘f’ Data operation register ‘f’ Data operation If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE BTFSC FLAG, 1, 0 Example: HERE BTFSS FLAG, 1, 0 FALSE : FALSE : TRUE : TRUE : Before Instruction Before Instruction PC = address (HERE) PC = address (HERE) After Instruction After Instruction If FLAG<1> = 0; If FLAG<1> = 0; PC = address (TRUE) PC = address (FALSE) If FLAG<1> = 1; If FLAG<1> = 1; PC = address (FALSE) PC = address (TRUE) DS39682E-page 262 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV n Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127 0 ≤ b < 7 Operation: if Overflow bit is ‘1’, a ∈ [0,1] (PC) + 2 + 2n → PC Operation: (f<b>) → f<b> Status Affected: None Status Affected: None Encoding: 1110 0100 nnnn nnnn Encoding: 0111 bbba ffff ffff Description: If the Overflow bit is ‘1’, then the Description: Bit ‘b’ in data memory location ‘f’ is program will branch. inverted. The 2’s complement number, ‘2n’, is If ‘a’ is ‘0’, the Access Bank is selected. added to the PC. Since the PC will have If ‘a’ is ‘1’, the BSR is used to select the incremented to fetch the next GPR bank (default). instruction, the new address will be If ‘a’ is ‘0’ and the extended instruction PC+2+2n. This instruction is then a set is enabled, this instruction operates two-cycle instruction. in Indexed Literal Offset Addressing Words: 1 mode whenever f ≤ 95 (5Fh). See Section22.2.3 “Byte-Oriented and Cycles: 1(2) Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. If Jump: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read literal Process Write to PC ‘n’ Data Q Cycle Activity: No No No No Q1 Q2 Q3 Q4 operation operation operation operation Decode Read Process Write If No Jump: register ‘f’ Data register ‘f’ Q1 Q2 Q3 Q4 Decode Read literal Process No Example: BTG PORTC, 4, 0 ‘n’ Data operation Before Instruction: PORTC = 0111 0101 [75h] Example: HERE BOV Jump After Instruction: PORTC = 0110 0101 [65h] Before Instruction PC = address (HERE) After Instruction If Overflow = 1; PC = address (Jump) If Overflow = 0; PC = address (HERE + 2) © 2009 Microchip Technology Inc. DS39682E-page 263

PIC18F45J10 FAMILY BZ Branch if Zero CALL Subroutine Call Syntax: BZ n Syntax: CALL k {,s} Operands: -128 ≤ n ≤ 127 Operands: 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: if Zero bit is ‘1’, (PC) + 2 + 2n → PC Operation: (PC) + 4 → TOS, k → PC<20:1>; Status Affected: None if s = 1, Encoding: 1110 0000 nnnn nnnn (W) → WS, Description: If the Zero bit is ‘1’, then the program (STATUS) → STATUSS, will branch. (BSR) → BSRS The 2’s complement number, ‘2n’, is Status Affected: None added to the PC. Since the PC will Encoding: have incremented to fetch the next 1st word (k<7:0>) 1110 110s k kkk kkkk instruction, the new address will be 7 0 2nd word(k<19:8>) 1111 k kkk kkkk kkkk PC+2+2n. This instruction is then a 19 8 two-cycle instruction. Description: Subroutine call of entire 2-Mbyte memory range. First, return address Words: 1 (PC + 4) is pushed onto the return Cycles: 1(2) stack. If ‘s’ = 1, the W, STATUS and Q Cycle Activity: BSR registers are also pushed into their If Jump: respective shadow registers, WS, STATUSS and BSRS. If ‘s’ = 0, no Q1 Q2 Q3 Q4 update occurs (default). Then, the Decode Read literal Process Write to PC 20-bit value ‘k’ is loaded into PC<20:1>. ‘n’ Data CALL is a two-cycle instruction. No No No No Words: 2 operation operation operation operation If No Jump: Cycles: 2 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read literal Process No Q1 Q2 Q3 Q4 ‘n’ Data operation Decode Read literal PUSH PC to Read literal ‘k’<7:0>, stack ‘k’<19:8>, Example: HERE BZ Jump Write to PC No No No No Before Instruction operation operation operation operation PC = address (HERE) After Instruction If Zero = 1; Example: HERE CALL THERE, 1 PC = address (Jump) If Zero = 0; Before Instruction PC = address (HERE + 2) PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 4) WS = W BSRS = BSR STATUSS= STATUS DS39682E-page 264 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY CLRF Clear f CLRWDT Clear Watchdog Timer Syntax: CLRF f {,a} Syntax: CLRWDT Operands: 0 ≤ f ≤ 255 Operands: None a ∈ [0,1] Operation: 000h → WDT, Operation: 000h → f, 000h → WDT postscaler, 1 → Z 1 → TO, 1 → PD Status Affected: Z Status Affected: TO, PD Encoding: 0110 101a ffff ffff Encoding: 0000 0000 0000 0100 Description: Clears the contents of the specified register. Description: CLRWDT instruction resets the If ‘a’ is ‘0’, the Access Bank is selected. Watchdog Timer. It also resets the If ‘a’ is ‘1’, the BSR is used to select the postscaler of the WDT. Status bits, TO GPR bank (default). and PD, are set. If ‘a’ is ‘0’ and the extended instruction Words: 1 set is enabled, this instruction operates in Indexed Literal Offset Addressing Cycles: 1 mode whenever f ≤ 95 (5Fh). See Q Cycle Activity: Section22.2.3 “Byte-Oriented and Q1 Q2 Q3 Q4 Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Decode No Process No operation Data operation Words: 1 Cycles: 1 Example: CLRWDT Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 WDT Counter = ? Decode Read Process Write After Instruction register ‘f’ Data register ‘f’ WDT Counter = 00h WDT Postscaler = 0 TO = 1 Example: CLRF FLAG_REG, 1 PD = 1 Before Instruction FLAG_REG = 5Ah After Instruction FLAG_REG = 00h © 2009 Microchip Technology Inc. DS39682E-page 265

PIC18F45J10 FAMILY COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF f {,d {,a}} Syntax: CPFSEQ f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W), skip if (f) = (W) Operation: (f) → dest (unsigned comparison) Status Affected: N, Z Status Affected: None Encoding: 0001 11da ffff ffff Encoding: 0110 001a ffff ffff Description: The contents of register ‘f’ are Description: Compares the contents of data memory complemented. If ‘d’ is ‘0’, the result is location ‘f’ to the contents of W by stored in W. If ‘d’ is ‘1’, the result is performing an unsigned subtraction. stored back in register ‘f’ (default). If ‘f’ = W, then the fetched instruction is If ‘a’ is ‘0’, the Access Bank is selected. discarded and a NOP is executed If ‘a’ is ‘1’, the BSR is used to select the instead, making this a two-cycle GPR bank (default). instruction. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank is selected. set is enabled, this instruction operates If ‘a’ is ‘1’, the BSR is used to select the in Indexed Literal Offset Addressing GPR bank (default). mode whenever f ≤ 95 (5Fh). See If ‘a’ is ‘0’ and the extended instruction Section22.2.3 “Byte-Oriented and set is enabled, this instruction operates Bit-Oriented Instructions in Indexed in Indexed Literal Offset Addressing Literal Offset Mode” for details. mode whenever f ≤ 95 (5Fh). See Words: 1 Section22.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Cycles: 1 Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1(2) Decode Read Process Write to Note: 3 cycles if skip and followed register ‘f’ Data destination by a 2-word instruction. Q Cycle Activity: Example: COMF REG, 0, 0 Q1 Q2 Q3 Q4 Before Instruction Decode Read Process No REG = 13h register ‘f’ Data operation After Instruction If skip: REG = 13h Q1 Q2 Q3 Q4 W = ECh No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE CPFSEQ REG, 0 NEQUAL : EQUAL : Before Instruction PC Address = HERE W = ? REG = ? After Instruction If REG = W; PC = Address (EQUAL) If REG ≠ W; PC = Address (NEQUAL) DS39682E-page 266 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W), Operation: (f) – (W), skip if (f) > (W) skip if (f) < (W) (unsigned comparison) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 010a ffff ffff Encoding: 0110 000a ffff ffff Description: Compares the contents of data memory Description: Compares the contents of data memory location ‘f’ to the contents of the W by location ‘f’ to the contents of W by performing an unsigned subtraction. performing an unsigned subtraction. If the contents of ‘f’ are greater than the , If the contents of ‘f’ are less than the contents of WREG then the fetched contents of W, then the fetched instruction is discarded and a NOP is instruction is discarded and a NOP is executed instead, making this a executed instead, making this a two-cycle instruction. two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Words: 1 in Indexed Literal Offset Addressing Cycles: 1(2) mode whenever f ≤ 95 (5Fh). See Note: 3 cycles if skip and followed Section22.2.3 “Byte-Oriented and by a 2-word instruction. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1(2) Decode Read Process No Note: 3 cycles if skip and followed register ‘f’ Data operation by a 2-word instruction. If skip: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No Decode Read Process No operation operation operation operation register ‘f’ Data operation If skip and followed by 2-word instruction: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 No No No No Example: HERE CPFSLT REG, 1 operation operation operation operation NLESS : No No No No LESS : operation operation operation operation Before Instruction PC = Address (HERE) Example: HERE CPFSGT REG, 0 W = ? NGREATER : After Instruction GREATER : If REG < W; Before Instruction PC = Address (LESS) If REG ≥ W; PC = Address (HERE) PC = Address (NLESS) W = ? After Instruction If REG > W; PC = Address (GREATER) If REG ≤ W; PC = Address (NGREATER) © 2009 Microchip Technology Inc. DS39682E-page 267

PIC18F45J10 FAMILY DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: If [W<3:0> > 9] or [DC = 1] then, a ∈ [0,1] (W<3:0>) + 6 → W<3:0>; else, Operation: (f) – 1 → dest (W<3:0>) → W<3:0> Status Affected: C, DC, N, OV, Z If [W<7:4> + DC > 9] or [C = 1] then, Encoding: 0000 01da ffff ffff (W<7:4>) + 6 + DC → W<7:4>; Description: Decrement register ‘f’. If ‘d’ is ‘0’, the else, result is stored in W. If ‘d’ is ‘1’, the (W<7:4>) + DC → W<7:4> result is stored back in register ‘f’ Status Affected: C (default). If ‘a’ is ‘0’, the Access Bank is selected. Encoding: 0000 0000 0000 0111 If ‘a’ is ‘1’, the BSR is used to select the Description: DAW adjusts the eight-bit value in W, GPR bank (default). resulting from the earlier addition of two If ‘a’ is ‘0’ and the extended instruction variables (each in packed BCD format) set is enabled, this instruction operates and produces a correct packed BCD in Indexed Literal Offset Addressing result. mode whenever f ≤ 95 (5Fh). See Section22.2.3 “Byte-Oriented and Words: 1 Bit-Oriented Instructions in Indexed Cycles: 1 Literal Offset Mode” for details. Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read Process Write Q Cycle Activity: register W Data W Q1 Q2 Q3 Q4 Example 1: Decode Read Process Write to DAW register ‘f’ Data destination Before Instruction W = A5h Example: DECF CNT, 1, 0 C = 0 DC = 0 Before Instruction After Instruction CNT = 01h Z = 0 W = 05h C = 1 After Instruction DC = 0 CNT = 00h Example 2: Z = 1 Before Instruction W = CEh C = 0 DC = 0 After Instruction W = 34h C = 1 DC = 0 DS39682E-page 268 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if Not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, Operation: (f) – 1 → dest, skip if result = 0 skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). placed back in register ‘f’ (default). If the result is ‘0’, the next instruction, If the result is not ‘0’, the next which is already fetched, is discarded instruction, which is already fetched, is and a NOP is executed instead, making discarded and a NOP is executed it a two-cycle instruction. instead, making it a two-cycle If ‘a’ is ‘0’, the Access Bank is selected. instruction. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected. GPR bank (default). If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’ and the extended instruction GPR bank (default). set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction in Indexed Literal Offset Addressing set is enabled, this instruction operates mode whenever f ≤ 95 (5Fh). See in Indexed Literal Offset Addressing Section22.2.3 “Byte-Oriented and mode whenever f ≤ 95 (5Fh). See Bit-Oriented Instructions in Indexed Section22.2.3 “Byte-Oriented and Literal Offset Mode” for details. Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed Cycles: 1(2) by a 2-word instruction. Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to If skip: register ‘f’ Data destination Q1 Q2 Q3 Q4 If skip: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No If skip and followed by 2-word instruction: operation operation operation operation Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction: No No No No Q1 Q2 Q3 Q4 operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation No No No No operation operation operation operation Example: HERE DECFSZ CNT, 1, 1 GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0 CONTINUE ZERO : NZERO : Before Instruction PC = Address (HERE) Before Instruction After Instruction TEMP = ? CNT = CNT – 1 After Instruction If CNT = 0; TEMP = TEMP – 1, PC = Address (CONTINUE) If TEMP = 0; If CNT ≠ 0; PC = Address (ZERO) PC = Address (HERE + 2) If TEMP ≠ 0; PC = Address (NZERO) © 2009 Microchip Technology Inc. DS39682E-page 269

PIC18F45J10 FAMILY GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF f {,d {,a}} Operands: 0 ≤ k ≤ 1048575 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: k → PC<20:1> a ∈ [0,1] Status Affected: None Operation: (f) + 1 → dest Encoding: Status Affected: C, DC, N, OV, Z 1st word (k<7:0>) 1110 1111 k kkk kkkk 7 0 2nd word(k<19:8>) 1111 k kkk kkkk kkkk Encoding: 0010 10da ffff ffff 19 8 Description: GOTO allows an unconditional branch Description: The contents of register ‘f’ are anywhere within entire incremented. If ‘d’ is ‘0’, the result is 2-Mbyte memory range. The 20-bit placed in W. If ‘d’ is ‘1’, the result is value ‘k’ is loaded into PC<20:1>. GOTO placed back in register ‘f’ (default). is always a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Words: 2 GPR bank (default). Cycles: 2 If ‘a’ is ‘0’ and the extended instruction Q Cycle Activity: set is enabled, this instruction operates in Indexed Literal Offset Addressing Q1 Q2 Q3 Q4 mode whenever f ≤ 95 (5Fh). See Decode Read literal No Read literal Section22.2.3 “Byte-Oriented and ‘k’<7:0>, operation ‘k’<19:8>, Bit-Oriented Instructions in Indexed Write to PC Literal Offset Mode” for details. No No No No Words: 1 operation operation operation operation Cycles: 1 Example: GOTO THERE Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 PC = Address (THERE) Decode Read Process Write to register ‘f’ Data destination Example: INCF CNT, 1, 0 Before Instruction CNT = FFh Z = 0 C = ? DC = ? After Instruction CNT = 00h Z = 1 C = 1 DC = 1 DS39682E-page 270 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY INCFSZ Increment f, Skip if 0 INFSNZ Increment f, Skip if Not 0 Syntax: INCFSZ f {,d {,a}} Syntax: INFSNZ f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest, Operation: (f) + 1 → dest, skip if result ≠ 0 skip if result = 0 Status Affected: None Status Affected: None Encoding: 0100 10da ffff ffff Encoding: 0011 11da ffff ffff Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). placed back in register ‘f’ (default). If the result is not ‘0’, the next If the result is ‘0’, the next instruction, instruction, which is already fetched, is which is already fetched, is discarded discarded and a NOP is executed and a NOP is executed instead, making instead, making it a two-cycle it a two-cycle instruction. instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). GPR bank (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See mode whenever f ≤ 95 (5Fh). See Section22.2.3 “Byte-Oriented and Section22.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed by a 2-word instruction. by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register ‘f’ Data destination register ‘f’ Data destination If skip: If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example: HERE INCFSZ CNT, 1, 0 Example: HERE INFSNZ REG, 1, 0 NZERO : ZERO ZERO : NZERO Before Instruction Before Instruction PC = Address (HERE) PC = Address (HERE) After Instruction After Instruction CNT = CNT + 1 REG = REG + 1 If CNT = 0; If REG ≠ 0; PC = Address (ZERO) PC = Address (NZERO) If CNT ≠ 0; If REG = 0; PC = Address (NZERO) PC = Address (ZERO) © 2009 Microchip Technology Inc. DS39682E-page 271

PIC18F45J10 FAMILY IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (W) .OR. k → W a ∈ [0,1] Status Affected: N, Z Operation: (W) .OR. (f) → dest Encoding: 0000 1001 kkkk kkkk Status Affected: N, Z Description: The contents of W are ORed with the Encoding: 0001 00da ffff ffff eight-bit literal ‘k’. The result is placed in W. Description: Inclusive OR W with register ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, Words: 1 the result is placed back in register ‘f’ Cycles: 1 (default). Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank (default). Decode Read Process Write to W If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: IORLW 35h mode whenever f ≤ 95 (5Fh). See Section22.2.3 “Byte-Oriented and Before Instruction Bit-Oriented Instructions in Indexed W = 9Ah Literal Offset Mode” for details. After Instruction Words: 1 W = BFh Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: IORWF RESULT, 0, 1 Before Instruction RESULT = 13h W = 91h After Instruction RESULT = 13h W = 93h DS39682E-page 272 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF f {,d {,a}} Operands: 0 ≤ f ≤ 2 Operands: 0 ≤ f ≤ 255 0 ≤ k ≤ 4095 d ∈ [0,1] a ∈ [0,1] Operation: k → FSRf Operation: f → dest Status Affected: None Status Affected: N, Z Encoding: 1110 1110 00ff k kkk 11 1111 0000 k kkk kkkk Encoding: 0101 00da ffff ffff 7 Description: The 12-bit literal ‘k’ is loaded into the Description: The contents of register ‘f’ are moved to File Select Register pointed to by ‘f’. a destination dependent upon the status of ‘d’. If ‘d’ is ‘0’, the result is Words: 2 placed in W. If ‘d’ is ‘1’, the result is Cycles: 2 placed back in register ‘f’ (default). Q Cycle Activity: Location ‘f’ can be anywhere in the 256-byte bank. Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is selected. Decode Read literal Process Write If ‘a’ is ‘1’, the BSR is used to select the ‘k’ MSB Data literal ‘k’ GPR bank (default). MSB to If ‘a’ is ‘0’ and the extended instruction FSRfH set is enabled, this instruction operates Decode Read literal Process Write literal in Indexed Literal Offset Addressing ‘k’ LSB Data ‘k’ to FSRfL mode whenever f ≤ 95 (5Fh). See Section22.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Example: LFSR 2, 3ABh Literal Offset Mode” for details. After Instruction Words: 1 FSR2H = 03h FSR2L = ABh Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write W register ‘f’ Data Example: MOVF REG, 0, 0 Before Instruction REG = 22h W = FFh After Instruction REG = 22h W = 22h © 2009 Microchip Technology Inc. DS39682E-page 273

PIC18F45J10 FAMILY MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF f ,f Syntax: MOVLW k s d Operands: 0 ≤ f ≤ 4095 Operands: 0 ≤ k ≤ 255 s 0 ≤ f ≤ 4095 d Operation: k → BSR Operation: (f ) → f s d Status Affected: None Status Affected: None Encoding: 0000 0001 kkkk kkkk Encoding: Description: The eight-bit literal ‘k’ is loaded into the 1st word (source) 1100 ffff ffff ffffs Bank Select Register (BSR). The value 2nd word (destin.) 1111 ffff ffff ffffd of BSR<7:4> always remains ‘0’, Description: The contents of source register ‘f ’ are regardless of the value of k :k . s 7 4 moved to destination register ‘f ’. d Words: 1 Location of source ‘f ’ can be anywhere s in the 4096-byte data space (000h to Cycles: 1 FFFh) and location of destination ‘fd’ Q Cycle Activity: can also be anywhere from 000h to Q1 Q2 Q3 Q4 FFFh. Either source or destination can be W Decode Read Process Write literal (a useful special situation). literal ‘k’ Data ‘k’ to BSR MOVFF is particularly useful for transferring a data memory location to a Example: MOVLB 5 peripheral register (such as the transmit Before Instruction buffer or an I/O port). BSR Register = 02h The MOVFF instruction cannot use the After Instruction PCL, TOSU, TOSH or TOSL as the BSR Register = 05h destination register. Words: 2 Cycles: 2 (3) Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation (src) Decode No No Write operation operation register ‘f’ No dummy (dest) read Example: MOVFF REG1, REG2 Before Instruction REG1 = 33h REG2 = 11h After Instruction REG1 = 33h REG2 = 33h DS39682E-page 274 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF f {,a} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: k → W Operation: (W) → f Status Affected: None Status Affected: None Encoding: 0000 1110 kkkk kkkk Encoding: 0110 111a ffff ffff Description: The eight-bit literal ‘k’ is loaded into W. Description: Move data from W to register ‘f’. Words: 1 Location ‘f’ can be anywhere in the Cycles: 1 256-byte bank. Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the Q1 Q2 Q3 Q4 GPR bank (default). Decode Read Process Write to W If ‘a’ is ‘0’ and the extended instruction literal ‘k’ Data set is enabled, this instruction operates in Indexed Literal Offset Addressing Example: MOVLW 5Ah mode whenever f ≤ 95 (5Fh). See Section22.2.3 “Byte-Oriented and After Instruction Bit-Oriented Instructions in Indexed W = 5Ah Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: MOVWF REG, 0 Before Instruction W = 4Fh REG = FFh After Instruction W = 4Fh REG = 4Fh © 2009 Microchip Technology Inc. DS39682E-page 275

PIC18F45J10 FAMILY MULLW Multiply Literal with W MULWF Multiply W with f Syntax: MULLW k Syntax: MULWF f {,a} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) x k → PRODH:PRODL Operation: (W) x (f) → PRODH:PRODL Status Affected: None Status Affected: None Encoding: 0000 1101 kkkk kkkk Encoding: 0000 001a ffff ffff Description: An unsigned multiplication is carried out between the contents of W and the Description: An unsigned multiplication is carried 8-bit literal ‘k’. The 16-bit result is out between the contents of W and the placed in the PRODH:PRODL register register file location ‘f’. The 16-bit pair. PRODH contains the high byte. result is stored in the PRODH:PRODL W is unchanged. register pair. PRODH contains the None of the Status flags are affected. high byte. Both W and ‘f’ are Note that neither overflow nor carry is unchanged. possible in this operation. A zero result None of the Status flags are affected. is possible but not detected. Note that neither overflow nor carry is possible in this operation. A zero Words: 1 result is possible but not detected. Cycles: 1 If ‘a’ is ‘0’, the Access Bank is Q Cycle Activity: selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode Read Process Write set is enabled, this instruction literal ‘k’ Data registers operates in Indexed Literal Offset PRODH: Addressing mode whenever PRODL f ≤ 95 (5Fh). See Section22.2.3 “Byte-Oriented and Bit-Oriented Example: MULLW 0C4h Instructions in Indexed Literal Offset Mode” for details. Before Instruction Words: 1 W = E2h PRODH = ? Cycles: 1 PRODL = ? Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 W = E2h PRODH = ADh Decode Read Process Write PRODL = 08h register ‘f’ Data registers PRODH: PRODL Example: MULWF REG, 1 Before Instruction W = C4h REG = B5h PRODH = ? PRODL = ? After Instruction W = C4h REG = B5h PRODH = 8Ah PRODL = 94h DS39682E-page 276 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY NEGF Negate f NOP No Operation Syntax: NEGF f {,a} Syntax: NOP Operands: 0 ≤ f ≤ 255 Operands: None a ∈ [0,1] Operation: No operation Operation: (f) + 1 → f Status Affected: None Status Affected: N, OV, C, DC, Z Encoding: 0000 0000 0000 0000 Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx Description: Location ‘f’ is negated using two’s Description: No operation. complement. The result is placed in the Words: 1 data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. Cycles: 1 If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction Decode No No No set is enabled, this instruction operates operation operation operation in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section22.2.3 “Byte-Oriented and Example: Bit-Oriented Instructions in Indexed None. Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register ‘f’ Data register ‘f’ Example: NEGF REG, 1 Before Instruction REG = 0011 1010 [3Ah] After Instruction REG = 1100 0110 [C6h] © 2009 Microchip Technology Inc. DS39682E-page 277

PIC18F45J10 FAMILY POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) → bit bucket Operation: (PC + 2) → TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return Description: The PC + 2 is pushed onto the top of stack and is discarded. The TOS value the return stack. The previous TOS then becomes the previous value that value is pushed down on the stack. was pushed onto the return stack. This instruction allows implementing a This instruction is provided to enable software stack by modifying TOS and the user to properly manage the return then pushing it onto the return stack. stack to incorporate a software stack. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode PUSH No No Decode No POP TOS No PC+2 onto operation operation operation value operation return stack Example: POP Example: PUSH GOTO NEW Before Instruction Before Instruction TOS = 345Ah TOS = 0031A2h PC = 0124h Stack (1 level down) = 014332h After Instruction After Instruction PC = 0126h TOS = 014332h TOS = 0126h PC = NEW Stack (1 level down) = 345Ah DS39682E-page 278 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY RCALL Relative Call RESET Reset Syntax: RCALL n Syntax: RESET Operands: -1024 ≤ n ≤ 1023 Operands: None Operation: (PC) + 2 → TOS, Operation: Reset all registers and flags that are (PC) + 2 + 2n → PC affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111 Description: Subroutine call with a jump up to 1K Description: This instruction provides a way to from the current location. First, return execute a MCLR Reset in software. address (PC+2) is pushed onto the Words: 1 stack. Then, add the 2’s complement number, ‘2n’, to the PC. Since the PC Cycles: 1 will have incremented to fetch the next Q Cycle Activity: instruction, the new address will be Q1 Q2 Q3 Q4 PC+2+2n. This instruction is a two-cycle instruction. Decode Start No No Reset operation operation Words: 1 Cycles: 2 Example: RESET Q Cycle Activity: After Instruction Q1 Q2 Q3 Q4 Registers= Reset Value Decode Read literal Process Write to PC Flags* = Reset Value ‘n’ Data PUSH PC to stack No No No No operation operation operation operation Example: HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS= Address (HERE + 2) © 2009 Microchip Technology Inc. DS39682E-page 279

PIC18F45J10 FAMILY RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (TOS) → PC, Operation: k → W, 1 → GIE/GIEH or PEIE/GIEL; (TOS) → PC, if s = 1, PCLATU, PCLATH are unchanged (WS) → W, Status Affected: None (STATUSS) → STATUS, (BSRS) → BSR, Encoding: 0000 1100 kkkk kkkk PCLATU, PCLATH are unchanged Description: W is loaded with the eight-bit literal ‘k’. Status Affected: GIE/GIEH, PEIE/GIEL. The program counter is loaded from the top of the stack (the return address). Encoding: 0000 0000 0001 000s The high address latch (PCLATH) Description: Return from interrupt. Stack is popped remains unchanged. and Top-of-Stack (TOS) is loaded into Words: 1 the PC. Interrupts are enabled by setting either the high or low-priority Cycles: 2 global interrupt enable bit. If ‘s’ = 1, the Q Cycle Activity: contents of the shadow registers, WS, Q1 Q2 Q3 Q4 STATUSS and BSRS, are loaded into their corresponding registers, W, Decode Read Process POP PC STATUS and BSR. If ‘s’ = 0, no update literal ‘k’ Data from stack, of these registers occurs (default). Write to W No No No No Words: 1 operation operation operation operation Cycles: 2 Q Cycle Activity: Example: Q1 Q2 Q3 Q4 Decode No No POP PC CALL TABLE ; W contains table operation operation from stack ; offset value ; W now has Set GIEH or ; table value GIEL : No No No No TABLE operation operation operation operation ADDWF PCL ; W = offset RETLW k0 ; Begin table Example: RETFIE 1 RETLW k1 ; : After Interrupt : PC = TOS RETLW kn ; End of table W = WS BSR = BSRS STATUS = STATUSS Before Instruction GIE/GIEH, PEIE/GIEL = 1 W = 07h After Instruction W = value of kn DS39682E-page 280 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF f {,d {,a}} Operands: s ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (TOS) → PC; a ∈ [0,1] if s = 1, (WS) → W, Operation: (f<n>) → dest<n + 1>, (STATUSS) → STATUS, (f<7>) → C, (BSRS) → BSR, (C) → dest<0> PCLATU, PCLATH are unchanged Status Affected: C, N, Z Status Affected: None Encoding: 0011 01da ffff ffff Encoding: 0000 0000 0001 001s Description: The contents of register ‘f’ are rotated Description: Return from subroutine. The stack is one bit to the left through the Carry popped and the top of the stack (TOS) flag. If ‘d’ is ‘0’, the result is placed in is loaded into the program counter. If W. If ‘d’ is ‘1’, the result is stored back ‘s’= 1, the contents of the shadow in register ‘f’ (default). registers, WS, STATUSS and BSRS, If ‘a’ is ‘0’, the Access Bank is are loaded into their corresponding selected. If ‘a’ is ‘1’, the BSR is used to registers, W, STATUS and BSR. If select the GPR bank (default). ‘s’ = 0, no update of these registers If ‘a’ is ‘0’ and the extended instruction occurs (default). set is enabled, this instruction operates in Indexed Literal Offset Words: 1 Addressing mode whenever Cycles: 2 f ≤ 95 (5Fh). See Section22.2.3 Q Cycle Activity: “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Q1 Q2 Q3 Q4 Mode” for details. Decode No Process POP PC operation Data from stack C register f No No No No operation operation operation operation Words: 1 Cycles: 1 Q Cycle Activity: Example: RETURN Q1 Q2 Q3 Q4 After Instruction: Decode Read Process Write to PC = TOS register ‘f’ Data destination Example: RLCF REG, 0, 0 Before Instruction REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 1100 1100 C = 1 © 2009 Microchip Technology Inc. DS39682E-page 281

PIC18F45J10 FAMILY RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF f {,d {,a}} Syntax: RRCF f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f<n>) → dest<n + 1>, Operation: (f<n>) → dest<n – 1>, (f<7>) → dest<0> (f<0>) → C, (C) → dest<7> Status Affected: N, Z Status Affected: C, N, Z Encoding: 0100 01da ffff ffff Encoding: 0011 00da ffff ffff Description: The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result Description: The contents of register ‘f’ are rotated is placed in W. If ‘d’ is ‘1’, the result is one bit to the right through the Carry stored back in register ‘f’ (default). flag. If ‘d’ is ‘0’, the result is placed in W. If ‘a’ is ‘0’, the Access Bank is selected. If ‘d’ is ‘1’, the result is placed back in If ‘a’ is ‘1’, the BSR is used to select the register ‘f’ (default). GPR bank (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘1’, the BSR is used to select the set is enabled, this instruction operates GPR bank (default). in Indexed Literal Offset Addressing If ‘a’ is ‘0’ and the extended instruction mode whenever f ≤ 95 (5Fh). See set is enabled, this instruction operates Section22.2.3 “Byte-Oriented and in Indexed Literal Offset Addressing Bit-Oriented Instructions in Indexed mode whenever f ≤ 95 (5Fh). See Literal Offset Mode” for details. Section22.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed register f Literal Offset Mode” for details. Words: 1 C register f Cycles: 1 Words: 1 Q Cycle Activity: Cycles: 1 Q1 Q2 Q3 Q4 Q Cycle Activity: Decode Read Process Write to register ‘f’ Data destination Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: RLNCF REG, 1, 0 Before Instruction REG = 1010 1011 Example: RRCF REG, 0, 0 After Instruction Before Instruction REG = 0101 0111 REG = 1110 0110 C = 0 After Instruction REG = 1110 0110 W = 0111 0011 C = 0 DS39682E-page 282 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY RRNCF Rotate Right f (No Carry) SETF Set f Syntax: RRNCF f {,d {,a}} Syntax: SETF f {,a} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: FFh → f Operation: (f<n>) → dest<n – 1>, Status Affected: None (f<0>) → dest<7> Encoding: 0110 100a ffff ffff Status Affected: N, Z Description: The contents of the specified register Encoding: 0100 00da ffff ffff are set to FFh. Description: The contents of register ‘f’ are rotated If ‘a’ is ‘0’, the Access Bank is selected. one bit to the right. If ‘d’ is ‘0’, the result If ‘a’ is ‘1’, the BSR is used to select the is placed in W. If ‘d’ is ‘1’, the result is GPR bank (default). placed back in register ‘f’ (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank will be set is enabled, this instruction operates selected, overriding the BSR value. If ‘a’ in Indexed Literal Offset Addressing is ‘1’, then the bank will be selected as mode whenever f ≤ 95 (5Fh). See per the BSR value (default). Section22.2.3 “Byte-Oriented and If ‘a’ is ‘0’ and the extended instruction Bit-Oriented Instructions in Indexed set is enabled, this instruction operates Literal Offset Mode” for details. in Indexed Literal Offset Addressing Words: 1 mode whenever f ≤ 95 (5Fh). See Section22.2.3 “Byte-Oriented and Cycles: 1 Bit-Oriented Instructions in Indexed Q Cycle Activity: Literal Offset Mode” for details. Q1 Q2 Q3 Q4 register f Decode Read Process Write register ‘f’ Data register ‘f’ Words: 1 Cycles: 1 Example: SETF REG, 1 Q Cycle Activity: Before Instruction Q1 Q2 Q3 Q4 REG = 5Ah After Instruction Decode Read Process Write to REG = FFh register ‘f’ Data destination Example 1: RRNCF REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = 1110 1011 Example 2: RRNCF REG, 0, 0 Before Instruction W = ? REG = 1101 0111 After Instruction W = 1110 1011 REG = 1101 0111 © 2009 Microchip Technology Inc. DS39682E-page 283

PIC18F45J10 FAMILY SLEEP Enter Sleep mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB f {,d {,a}} Operands: None Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: 00h → WDT, a ∈ [0,1] 0 → WDT postscaler, 1 → TO, Operation: (W) – (f) – (C) → dest 0 → PD Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0101 01da ffff ffff Encoding: 0000 0000 0000 0011 Description: Subtract register ‘f’ and Carry flag Description: The Power-Down status bit (PD) is (borrow) from W (2’s complement cleared. The Time-out status bit (TO) method). If ‘d’ is ‘0’, the result is stored is set. Watchdog Timer and its in W. If ‘d’ is ‘1’, the result is stored in postscaler are cleared. register ‘f’ (default). The processor is put into Sleep mode If ‘a’ is ‘0’, the Access Bank is with the oscillator stopped. selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). Words: 1 If ‘a’ is ‘0’ and the extended instruction Cycles: 1 set is enabled, this instruction Q Cycle Activity: operates in Indexed Literal Offset Addressing mode whenever Q1 Q2 Q3 Q4 f ≤ 95 (5Fh). See Section22.2.3 Decode No Process Go to “Byte-Oriented and Bit-Oriented operation Data Sleep Instructions in Indexed Literal Offset Mode” for details. Example: SLEEP Words: 1 Before Instruction Cycles: 1 TO = ? Q Cycle Activity: PD = ? After Instruction Q1 Q2 Q3 Q4 TO = 1 † Decode Read Process Write to PD = 0 register ‘f’ Data destination Example 1: SUBFWB REG, 1, 0 † If WDT causes wake-up, this bit is cleared. Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 DS39682E-page 284 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF f {,d {,a}} Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: k – (W) → W a ∈ [0,1] Status Affected: N, OV, C, DC, Z Operation: (f) – (W) → dest Encoding: 0000 1000 kkkk kkkk Status Affected: N, OV, C, DC, Z Description W is subtracted from the eight-bit Encoding: 0101 11da ffff ffff literal ‘k’. The result is placed in W. Description: Subtract W from register ‘f’ (2’s Words: 1 complement method). If ‘d’ is ‘0’, the Cycles: 1 result is stored in W. If ‘d’ is ‘1’, the Q Cycle Activity: result is stored back in register ‘f’ (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’, the Access Bank is Decode Read Process Write to W selected. If ‘a’ is ‘1’, the BSR is used literal ‘k’ Data to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction Example 1: SUBLW 02h set is enabled, this instruction Before Instruction operates in Indexed Literal Offset W = 01h Addressing mode whenever C = ? f ≤ 95 (5Fh). See Section22.2.3 After Instruction W = 01h “Byte-Oriented and Bit-Oriented C = 1 ; result is positive Instructions in Indexed Literal Offset Z = 0 Mode” for details. N = 0 Words: 1 Example 2: SUBLW 02h Cycles: 1 Before Instruction W = 02h Q Cycle Activity: C = ? Q1 Q2 Q3 Q4 After Instruction W = 00h Decode Read Process Write to C = 1 ; result is zero register ‘f’ Data destination Z = 1 N = 0 Example 1: SUBWF REG, 1, 0 Example 3: SUBLW 02h Before Instruction REG = 3 Before Instruction W = 2 W = 03h C = ? C = ? After Instruction After Instruction REG = 1 W = FFh ; (2’s complement) W = 2 C = 0 ; result is negative C = 1 ; result is positive Z = 0 Z = 0 N = 1 N = 0 Example 2: SUBWF REG, 0, 0 Before Instruction REG = 2 W = 2 C = ? After Instruction REG = 2 W = 0 C = 1 ; result is zero Z = 1 N = 0 Example 3: SUBWF REG, 1, 0 Before Instruction REG = 1 W = 2 C = ? After Instruction REG = FFh ;(2’s complement) W = 2 C = 0 ; result is negative Z = 0 N = 1 © 2009 Microchip Technology Inc. DS39682E-page 285

PIC18F45J10 FAMILY SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB f {,d {,a}} Syntax: SWAPF f {,d {,a}} Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 d ∈ [0,1] d ∈ [0,1] a ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) – (C) → dest Operation: (f<3:0>) → dest<7:4>, Status Affected: N, OV, C, DC, Z (f<7:4>) → dest<3:0> Encoding: 0101 10da ffff ffff Status Affected: None Description: Subtract W and the Carry flag (borrow) Encoding: 0011 10da ffff ffff from register ‘f’ (2’s complement Description: The upper and lower nibbles of register method). If ‘d’ is ‘0’, the result is stored ‘f’ are exchanged. If ‘d’ is ‘0’, the result in W. If ‘d’ is ‘1’, the result is stored back is placed in W. If ‘d’ is ‘1’, the result is in register ‘f’ (default). placed in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). GPR bank (default). If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates set is enabled, this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See mode whenever f ≤ 95 (5Fh). See Section22.2.3 “Byte-Oriented and Section22.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Literal Offset Mode” for details. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to Q1 Q2 Q3 Q4 register ‘f’ Data destination Decode Read Process Write to Example 1: SUBWFB REG, 1, 0 register ‘f’ Data destination Before Instruction REG = 19h (0001 1001) Example: SWAPF REG, 1, 0 W = 0Dh (0000 1101) C = 1 Before Instruction After Instruction REG = 53h REG = 0Ch (0000 1011) After Instruction W = 0Dh (0000 1101) REG = 35h C = 1 Z = 0 N = 0 ; result is positive Example 2: SUBWFB REG, 0, 0 Before Instruction REG = 1Bh (0001 1011) W = 1Ah (0001 1010) C = 0 After Instruction REG = 1Bh (0001 1011) W = 00h C = 1 Z = 1 ; result is zero N = 0 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 03h (0000 0011) W = 0Eh (0000 1101) C = 1 After Instruction REG = F5h (1111 0100) ; [2’s comp] W = 0Eh (0000 1101) C = 0 Z = 0 N = 1 ; result is negative DS39682E-page 286 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD *+ ; Operands: None Before Instruction TABLAT = 55h Operation: if TBLRD *, TBLPTR = 00A356h (Prog Mem (TBLPTR)) → TABLAT, MEMORY (00A356h) = 34h TBLPTR – No Change; After Instruction if TBLRD *+, TABLAT = 34h (Prog Mem (TBLPTR)) → TABLAT, TBLPTR = 00A357h (TBLPTR) + 1 → TBLPTR; Example 2: TBLRD +* ; if TBLRD *-, (Prog Mem (TBLPTR)) → TABLAT, Before Instruction (TBLPTR) – 1 → TBLPTR; TABLAT = AAh TBLPTR = 01A357h if TBLRD +*, MEMORY (01A357h) = 12h (TBLPTR) + 1 → TBLPTR, MEMORY (01A358h) = 34h (Prog Mem (TBLPTR)) → TABLAT After Instruction Status Affected: None TABLAT = 34h TBLPTR = 01A358h Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No operation No No operation operation (Read Program operation (Write TABLAT) Memory) © 2009 Microchip Technology Inc. DS39682E-page 287

PIC18F45J10 FAMILY TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Before Instruction Operation: if TBLWT *, TABLAT = 55h (TABLAT) → Holding Register, TBLPTR = 00A356h HOLDING REGISTER TBLPTR – No Change; (00A356h) = FFh if TBLWT *+, After Instructions (table write completion) (TABLAT) → Holding Register, TABLAT = 55h (TBLPTR) + 1 → TBLPTR; TBLPTR = 00A357h if TBLWT *-, HOLDING REGISTER (TABLAT) → Holding Register, (00A356h) = 55h (TBLPTR) – 1 → TBLPTR; Example 2: TBLWT +*; if TBLWT +*, Before Instruction (TBLPTR) + 1 → TBLPTR, TABLAT = 34h (TABLAT) → Holding Register TBLPTR = 01389Ah Status Affected: None HOLDING REGISTER (01389Ah) = FFh Encoding: 0000 0000 0000 11nn HOLDING REGISTER nn=0 * (01389Bh) = FFh =1 *+ After Instruction (table write completion) =2 *- TABLAT = 34h =3 +* TBLPTR = 01389Bh HOLDING REGISTER Description: This instruction uses the 3 LSBs of (01389Ah) = FFh TBLPTR to determine which of the HOLDING REGISTER 8 holding registers the TABLAT is written (01389Bh) = 34h to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section7.0 “Flash Program Memory” for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-MByte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No No No operationoperation operation No No No No operationoperationoperation operation (Read (Write to TABLAT) Holding Register ) DS39682E-page 288 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255 a ∈ [0,1] Operation: (W) .XOR. k → W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: 0000 1010 kkkk kkkk Encoding: 0110 011a ffff ffff Description: The contents of W are XORed with Description: If ‘f’ = 0, the next instruction fetched the 8-bit literal ‘k’. The result is placed during the current instruction execution in W. is discarded and a NOP is executed, Words: 1 making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. Cycles: 1 If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity: GPR bank (default). Q1 Q2 Q3 Q4 If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates Decode Read Process Write to W in Indexed Literal Offset Addressing literal ‘k’ Data mode whenever f ≤ 95 (5Fh). See Section22.2.3 “Byte-Oriented and Example: XORLW 0AFh Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Before Instruction W = B5h Words: 1 After Instruction Cycles: 1(2) W = 1Ah Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process No register ‘f’ Data operation If skip: Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example: HERE TSTFSZ CNT, 1 NZERO : ZERO : Before Instruction PC = Address (HERE) After Instruction If CNT = 00h, PC = Address (ZERO) If CNT ≠ 00h, PC = Address (NZERO) © 2009 Microchip Technology Inc. DS39682E-page 289

PIC18F45J10 FAMILY XORWF Exclusive OR W with f Syntax: XORWF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: N, Z Encoding: 0001 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section22.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register ‘f’ Data destination Example: XORWF REG, 1, 0 Before Instruction REG = AFh W = B5h After Instruction REG = 1Ah W = B5h DS39682E-page 290 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 22.2 Extended Instruction Set A summary of the instructions in the extended instruc- tion set is provided in Table22-3. Detailed descriptions In addition to the standard 75 instructions of the PIC18 are provided in Section22.2.2 “Extended Instruction instruction set, PIC18F45J10 family devices also Set”. The opcode field descriptions in Table22-1 provide an optional extension to the core CPU function- (page250) apply to both the standard and extended ality. The added features include eight additional PIC18 instruction sets. instructions that augment indirect and indexed addressing operations and the implementation of Note: The instruction set extension and the Indexed Literal Offset Addressing mode for many of the Indexed Literal Offset Addressing mode standard PIC18 instructions. were designed for optimizing applications written in C; the user may likely never use The additional features of the extended instruction set these instructions directly in assembler. are disabled by default. To enable them, users must set The syntax for these commands is pro- the XINST Configuration bit. vided as a reference for users who may be The instructions in the extended set can all be reviewing code that has been generated classified as literal operations, which either manipulate by a compiler. the File Select Registers, or use them for indexed addressing. Two of the instructions, ADDFSR and 22.2.1 EXTENDED INSTRUCTION SYNTAX SUBFSR, each have an additional special instantiation Most of the extended instructions use indexed argu- for using FSR2. These versions (ADDULNK and ments, using one of the File Select Registers and some SUBULNK) allow for automatic return after execution. offset to specify a source or destination register. When The extended instructions are specifically implemented an argument for an instruction serves as part of to optimize re-entrant program code (that is, code that indexed addressing, it is enclosed in square brackets is recursive or that uses a software stack) written in (“[ ]”). This is done to indicate that the argument is used high-level languages, particularly C. Among other as an index or offset. MPASM™ Assembler will flag an things, they allow users working in high-level error if it determines that an index or offset value is not languages to perform certain operations on data bracketed. structures more efficiently. These include: When the extended instruction set is enabled, brackets • dynamic allocation and deallocation of software are also used to indicate index arguments in byte- stack space when entering and leaving oriented and bit-oriented instructions. This is in addition subroutines to other changes in their syntax. For more details, see • Function Pointer invocation Section22.2.3.1 “Extended Instruction Syntax with Standard PIC18 Commands”. • Software Stack Pointer manipulation • manipulation of variables located in a software Note: In the past, square brackets have been stack used to denote optional arguments in the PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces (“{ }”). TABLE 22-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Status Description Cycles Operands Affected MSb LSb ADDFSR f, k Add Literal to FSR 1 1110 1000 ffkk kkkk None ADDULNK k Add Literal to FSR2 and Return 2 1110 1000 11kk kkkk None CALLW Call Subroutine using WREG 2 0000 0000 0001 0100 None MOVSF zs, fd Move zs (source) to 1st Word 2 1110 1011 0zzz zzzz None fd (destination) 2nd Word 1111 ffff ffff ffff MOVSS zs, zd Move zs (source) to 1st Word 2 1110 1011 1zzz zzzz None zd (destination) 2nd Word 1111 xxxx xzzz zzzz PUSHL k Store Literal at FSR2, 1 1110 1010 kkkk kkkk None Decrement FSR2 SUBFSR f, k Subtract Literal from FSR 1 1110 1001 ffkk kkkk None SUBULNK k Subtract Literal from FSR2 and 2 1110 1001 11kk kkkk None Return © 2009 Microchip Technology Inc. DS39682E-page 291

PIC18F45J10 FAMILY 22.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operation: FSR2 + k → FSR2, Operation: FSR(f) + k → FSR(f) (TOS) → PC Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk Description: The 6-bit literal ‘k’ is added to the Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’. contents of FSR2. A RETURN is then Words: 1 executed by loading the PC with the Cycles: 1 TOS. The instruction takes two cycles to Q Cycle Activity: execute; a NOP is performed during Q1 Q2 Q3 Q4 the second cycle. Decode Read Process Write to This may be thought of as a special literal ‘k’ Data FSR case of the ADDFSR instruction, where f = 3 (binary ‘11’); it operates only on FSR2. Example: ADDFSR 2, 23h Words: 1 Before Instruction Cycles: 2 FSR2 = 03FFh After Instruction Q Cycle Activity: FSR2 = 0422h Q1 Q2 Q3 Q4 Decode Read Process Write to literal ‘k’ Data FSR No No No No Operation Operation Operation Operation Example: ADDULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 0422h PC = (TOS) Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s). DS39682E-page 292 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY CALLW Subroutine Call Using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [z ], f s d Operands: None Operands: 0 ≤ z ≤ 127 s 0 ≤ f ≤ 4095 Operation: (PC + 2) → TOS, d (W) → PCL, Operation: ((FSR2) + z ) → f s d (PCLATH) → PCH, Status Affected: None (PCLATU) → PCU Encoding: Status Affected: None 1st word (source) 1110 1011 0zzz zzzz s Encoding: 0000 0000 0001 0100 2nd word (destin.) 1111 ffff ffff ffffd Description First, the return address (PC + 2) is Description: The contents of the source register are pushed onto the return stack. Next, the moved to destination register ‘f ’. The d contents of W are written to PCL; the actual address of the source register is existing value is discarded. Then, the determined by adding the 7-bit literal contents of PCLATH and PCLATU are offset ‘z ’ in the first word to the value of s latched into PCH and PCU, FSR2. The address of the destination respectively. The second cycle is register is specified by the 12-bit literal executed as a NOP instruction while the ‘fd’ in the second word. Both addresses new next instruction is fetched. can be anywhere in the 4096-byte data Unlike CALL, there is no option to space (000h to FFFh). update W, STATUS or BSR. The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the Words: 1 destination register. Cycles: 2 If the resultant source address points to Q Cycle Activity: an indirect addressing register, the value returned will be 00h. Q1 Q2 Q3 Q4 Decode Read PUSH PC to No Words: 2 WREG stack operation Cycles: 2 No No No No Q Cycle Activity: operation operation operation operation Q1 Q2 Q3 Q4 Decode Determine Determine Read Example: HERE CALLW source addr source addr source reg Decode No No Write Before Instruction operation operation register ‘f’ PC = address (HERE) PCLATH = 10h No dummy (dest) PCLATU = 00h read W = 06h After Instruction PC = 001006h Example: MOVSF [05h], REG2 TOS = address (HERE + 2) PCLATH = 10h Before Instruction PCLATU = 00h FSR2 = 80h W = 06h Contents of 85h = 33h REG2 = 11h After Instruction FSR2 = 80h Contents of 85h = 33h REG2 = 33h © 2009 Microchip Technology Inc. DS39682E-page 293

PIC18F45J10 FAMILY MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0 ≤ zs ≤ 127 Operands: 0 ≤ k ≤ 255 0 ≤ z ≤ 127 d Operation: k → (FSR2), Operation: ((FSR2) + zs) → ((FSR2) + zd) FSR2 – 1 → FSR2 Status Affected: None Status Affected: None Encoding: Encoding: 1111 1010 kkkk kkkk 1st word (source) 1110 1011 1zzz zzzz s 2nd word (dest.) 1111 xxxx xzzz zzzz Description: The 8-bit literal ‘k’ is written to the data d memory address specified by FSR2. FSR2 Description The contents of the source register are is decremented by 1 after the operation. moved to the destination register. The This instruction allows users to push values addresses of the source and destination onto a software stack. registers are determined by adding the 7-bit literal offsets ‘z ’ or ‘z ’, Words: 1 s d respectively, to the value of FSR2. Both Cycles: 1 registers can be located anywhere in the 4096-byte data memory space Q Cycle Activity: (000h to FFFh). Q1 Q2 Q3 Q4 The MOVSS instruction cannot use the Decode Read ‘k’ Process Write to PCL, TOSU, TOSH or TOSL as the data destination destination register. If the resultant source address points to an indirect addressing register, the Example: PUSHL 08h value returned will be 00h. If the resultant destination address points to Before Instruction an indirect addressing register, the FSR2H:FSR2L = 01ECh Memory (01ECh) = 00h instruction will execute as a NOP. Words: 2 After Instruction FSR2H:FSR2L = 01EBh Cycles: 2 Memory (01ECh) = 08h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Determine Determine Read source addr source addr source reg Decode Determine Determine Write dest addr dest addr to dest reg Example: MOVSS [05h], [06h] Before Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 11h After Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 33h DS39682E-page 294 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operation: FSR2 – k → FSR2 Operation: FSR(f) – k → FSRf (TOS) → PC Status Affected: None Status Affected: None Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk Description: The 6-bit literal ‘k’ is subtracted from Description: The 6-bit literal ‘k’ is subtracted from the the contents of the FSR specified by contents of the FSR2. A RETURN is then ‘f’. executed by loading the PC with the TOS. Words: 1 The instruction takes two cycles to execute; a NOP is performed during the Cycles: 1 second cycle. Q Cycle Activity: This may be thought of as a special case of Q1 Q2 Q3 Q4 the SUBFSR instruction, where f = 3 (binary Decode Read Process Write to ‘11’); it operates only on FSR2. register ‘f’ Data destination Words: 1 Cycles: 2 Q Cycle Activity: Example: SUBFSR 2, 23h Q1 Q2 Q3 Q4 Before Instruction FSR2 = 03FFh Decode Read Process Write to register ‘f’ Data destination After Instruction FSR2 = 03DCh No No No No Operation Operation Operation Operation Example: SUBULNK 23h Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 03DCh PC = (TOS) © 2009 Microchip Technology Inc. DS39682E-page 295

PIC18F45J10 FAMILY 22.2.3 BYTE-ORIENTED AND 22.2.3.1 Extended Instruction Syntax with BIT-ORIENTED INSTRUCTIONS IN Standard PIC18 Commands INDEXED LITERAL OFFSET MODE When the extended instruction set is enabled, the file Note: Enabling the PIC18 instruction set register argument, ‘f’, in the standard byte-oriented and extension may cause legacy applications bit-oriented commands is replaced with the literal offset to behave erratically or fail entirely. value, ‘k’. As already noted, this occurs only when ‘f’ is less than or equal to 5Fh. When an offset value is used, In addition to eight new commands in the extended set, it must be indicated by square brackets (“[ ]”). As with enabling the extended instruction set also enables the extended instructions, the use of brackets indicates Indexed Literal Offset Addressing mode (Section6.5.1 to the compiler that the value is to be interpreted as an “Indexed Addressing with Literal Offset”). This has index or an offset. Omitting the brackets, or using a a significant impact on the way that many commands of value greater than 5Fh within brackets, will generate an the standard PIC18 instruction set are interpreted. error in the MPASM Assembler. When the extended set is disabled, addresses embed- If the index argument is properly bracketed for Indexed ded in opcodes are treated as literal memory locations: Literal Offset Addressing, the Access RAM argument is either as a location in the Access Bank (‘a’ = 0), or in a never specified; it will automatically be assumed to be GPR bank designated by the BSR (‘a’ = 1). When the ‘0’. This is in contrast to standard operation (extended extended instruction set is enabled and ‘a’ = 0, how- instruction set disabled) when ‘a’ is set on the basis of ever, a file register argument of 5Fh or less is the target address. Declaring the Access RAM bit in interpreted as an offset from the pointer value in FSR2 this mode will also generate an error in the MPASM and not as a literal address. For practical purposes, this Assembler. means that all instructions that use the Access RAM bit as an argument – that is, all byte-oriented and bit- The destination argument, ‘d’, functions as before. oriented instructions, or almost half of the core PIC18 Refer to the MPLAB® IDE, MPASM™ or MPLAB C18 instructions – may behave differently when the documentation for information on enabling Extended extended instruction set is enabled. Instruction set support When the content of FSR2 is 00h, the boundaries of the 22.2.4 CONSIDERATIONS WHEN Access RAM are essentially remapped to their original ENABLING THE EXTENDED values. This may be useful in creating backward INSTRUCTION SET compatible code. If this technique is used, it may be necessary to save the value of FSR2 and restore it It is important to note that the extensions to the instruc- when moving back and forth between C and assembly tion set may not be beneficial to all users. In particular, routines in order to preserve the Stack Pointer. Users users who are not writing code that uses a software must also keep in mind the syntax requirements of the stack may not benefit from using the extensions to the extended instruction set (see Section22.2.3.1 instruction set. “Extended Instruction Syntax with Standard PIC18 Additionally, the Indexed Literal Offset Addressing Commands”). mode may create issues with legacy applications Although the Indexed Literal Offset Addressing mode written to the PIC18 assembler. This is because can be very useful for dynamic stack and pointer instructions in the legacy code may attempt to address manipulation, it can also be very annoying if a simple registers in the Access Bank below 5Fh. Since these arithmetic operation is carried out on the wrong addresses are interpreted as literal offsets to FSR2 register. Users who are accustomed to the PIC18 pro- when the instruction set extension is enabled, the gramming must keep in mind that, when the extended application may read or write to the wrong data instruction set is enabled, register addresses of 5Fh or addresses. less are used for Indexed Literal Offset Addressing. When porting an application to the PIC18F45J10 Representative examples of typical byte-oriented and family, it is very important to consider the type of code. bit-oriented instructions in the Indexed Literal Offset A large, re-entrant application that is written in ‘C’ and Addressing mode are provided on the following page to would benefit from efficient compilation will do well show how execution is affected. The operand condi- when using the instruction set extensions. Legacy tions shown in the examples are applicable to all applications that heavily use the Access Bank will most instructions of these types. likely not benefit from using the extended instruction set. DS39682E-page 296 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY ADD W to Indexed Bit Set Indexed ADDWF BSF (Indexed Literal Offset mode) (Indexed Literal Offset mode) Syntax: ADDWF [k] {,d} Syntax: BSF [k], b Operands: 0 ≤ k ≤ 95 Operands: 0 ≤ f ≤ 95 d ∈ [0,1] 0 ≤ b ≤ 7 Operation: (W) + ((FSR2) + k) → dest Operation: 1 → ((FSR2) + k)<b> Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: 0010 01d0 kkkk kkkk Encoding: 1000 bbb0 kkkk kkkk Description: The contents of W are added to the Description: Bit ‘b’ of the register indicated by FSR2, contents of the register indicated by offset by the value ‘k’, is set. FSR2, offset by the value ‘k’. Words: 1 If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in Cycles: 1 register ‘f’ (default). Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read Process Write to register ‘f’ Data destination Q Cycle Activity: Q1 Q2 Q3 Q4 Example: BSF [FLAG_OFST], 7 Decode Read ‘k’ Process Write to Before Instruction Data destination FLAG_OFST = 0Ah FSR2 = 0A00h Example: ADDWF [OFST], 0 Contents of 0A0Ah = 55h Before Instruction After Instruction W = 17h Contents OFST = 2Ch of 0A0Ah = D5h FSR2 = 0A00h Contents of 0A2Ch = 20h After Instruction W = 37h Set Indexed Contents SETF of 0A2Ch = 20h (Indexed Literal Offset mode) Syntax: SETF [k] Operands: 0 ≤ k ≤ 95 Operation: FFh → ((FSR2) + k) Status Affected: None Encoding: 0110 1000 kkkk kkkk Description: The contents of the register indicated by FSR2, offset by ‘k’, are set to FFh. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read ‘k’ Process Write Data register Example: SETF [OFST] Before Instruction OFST = 2Ch FSR2 = 0A00h Contents of 0A2Ch = 00h After Instruction Contents of 0A2Ch = FFh © 2009 Microchip Technology Inc. DS39682E-page 297

PIC18F45J10 FAMILY 22.2.5 SPECIAL CONSIDERATIONS WITH To develop software for the extended instruction set, MICROCHIP MPLAB® IDE TOOLS the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). The latest versions of Microchip’s software tools have Depending on the environment being used, this may be been designed to fully support the extended instruction done in several ways: set of the PIC18F45J10 family of devices. This includes • A menu option, or dialog box within the the MPLAB C18 C compiler, MPASM assembly lan- environment, that allows the user to configure the guage and MPLAB Integrated Development language tool and its settings for the project Environment (IDE). • A command line option When selecting a target device for software • A directive in the source code development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for These options vary between different compilers, the XINST Configuration bit is ‘0’, disabling the assemblers and development environments. Users are extended instruction set and Indexed Literal Offset encouraged to review the documentation accompany- Addressing mode. For proper execution of applications ing their development systems for the appropriate developed to take advantage of the extended information. instruction set, XINST must be set during programming. DS39682E-page 298 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 23.0 DEVELOPMENT SUPPORT 23.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers are supported with a full range of hardware and software development tools: The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- • Integrated Development Environment controller market. The MPLAB IDE is a Windows® - MPLAB® IDE Software operating system-based application that contains: • Assemblers/Compilers/Linkers • A single graphical interface to all debugging tools - MPASMTM Assembler - Simulator - MPLAB C18 and MPLAB C30 C Compilers - Programmer (sold separately) - MPLINKTM Object Linker/ MPLIBTM Object Librarian - Emulator (sold separately) - MPLAB ASM30 Assembler/Linker/Library - In-Circuit Debugger (sold separately) • Simulators • A full-featured editor with color-coded context - MPLAB SIM Software Simulator • A multiple project manager • Emulators • Customizable data windows with direct edit of contents - MPLAB ICE 2000 In-Circuit Emulator • High-level source code debugging - MPLAB REAL ICE™ In-Circuit Emulator • Visual device initializer for easy register • In-Circuit Debugger initialization - MPLAB ICD 2 • Mouse over variable inspection • Device Programmers • Drag and drop variables from source to watch - PICSTART® Plus Development Programmer windows - MPLAB PM3 Device Programmer • Extensive on-line help - PICkit™ 2 Development Programmer • Integration of select third party tools, such as • Low-Cost Demonstration and Development HI-TECH Software C Compilers and IAR Boards and Evaluation Kits C Compilers The MPLAB IDE allows you to: • Edit your source files (either assembly or C) • One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2009 Microchip Technology Inc. DS39682E-page 299

PIC18F45J10 FAMILY 23.2 MPASM Assembler 23.5 MPLAB ASM30 Assembler, Linker and Librarian The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. MPLAB ASM30 Assembler produces relocatable The MPASM Assembler generates relocatable object machine code from symbolic assembly language for files for the MPLINK Object Linker, Intel® standard HEX dsPIC30F devices. MPLAB C30 C Compiler uses the files, MAP files to detail memory usage and symbol assembler to produce its object file. The assembler reference, absolute LST files that contain source lines generates relocatable object files that can then be and generated machine code and COFF files for archived or linked with other relocatable object files and debugging. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler features include: • Support for the entire dsPIC30F instruction set • Integration into MPLAB IDE projects • Support for fixed-point and floating-point data • User-defined macros to streamline • Command line interface assembly code • Rich directive set • Conditional assembly for multi-purpose source files • Flexible macro language • Directives that allow complete control over the • MPLAB IDE compatibility assembly process 23.6 MPLAB SIM Software Simulator 23.3 MPLAB C18 and MPLAB C30 The MPLAB SIM Software Simulator allows code C Compilers development in a PC-hosted environment by simulat- ing the PIC MCUs and dsPIC® DSCs on an instruction The MPLAB C18 and MPLAB C30 Code Development level. On any given instruction, the data areas can be Systems are complete ANSI C compilers for examined or modified and stimuli can be applied from Microchip’s PIC18 and PIC24 families of microcon- a comprehensive stimulus controller. Registers can be trollers and the dsPIC30 and dsPIC33 family of digital logged to files for further run-time analysis. The trace signal controllers. These compilers provide powerful buffer and logic analyzer display extend the power of integration capabilities, superior code optimization and the simulator to record and track program execution, ease of use not found with other compilers. actions on I/O, most peripherals and internal registers. For easy source level debugging, the compilers provide The MPLAB SIM Software Simulator fully supports symbol information that is optimized to the MPLAB IDE symbolic debugging using the MPLAB C18 and debugger. MPLAB C30 CCompilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator 23.4 MPLINK Object Linker/ offers the flexibility to develop and debug code outside MPLIB Object Librarian of the hardware laboratory environment, making it an excellent, economical software development tool. The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS39682E-page 300 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 23.7 MPLAB ICE 2000 23.9 MPLAB ICD 2 In-Circuit Debugger High-Performance Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a In-Circuit Emulator powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed The MPLAB ICE 2000 In-Circuit Emulator is intended USB interface. This tool is based on the Flash PIC to provide the product development engineer with a MCUs and can be used to develop for these and other complete microcontroller design tool set for PIC PIC MCUs and dsPIC DSCs. The MPLAB ICD2 utilizes microcontrollers. Software control of the MPLAB ICE the in-circuit debugging capability built into theFlash 2000 In-Circuit Emulator is advanced by the MPLAB devices. This feature, along with Microchip’s In-Circuit Integrated Development Environment, which allows Serial ProgrammingTM (ICSPTM) protocol, offers cost- editing, building, downloading and source debugging effective, in-circuit Flash debugging from the graphical from a single environment. user interface of the MPLAB Integrated Development The MPLAB ICE 2000 is a full-featured emulator Environment. This enables a designer to develop and system with enhanced trace, trigger and data monitor- debug source code by setting breakpoints, single step- ing features. Interchangeable processor modules allow ping and watching variables, and CPU status and the system to be easily reconfigured for emulation of peripheral registers. Running at full speed enables different processors. The architecture of the MPLAB testing hardware and applications in real time. MPLAB ICE 2000 In-Circuit Emulator allows expansion to ICD2 also serves as a development programmer for support new PIC microcontrollers. selected PIC devices. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with 23.10 MPLAB PM3 Device Programmer advanced features that are typically found on more The MPLAB PM3 Device Programmer is a universal, expensive development tools. The PC platform and Microsoft® Windows® 32-bit operating system were CE compliant device programmer with programmable chosen to best make these features available in a voltage verification at VDDMIN and VDDMAX for simple, unified application. maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various 23.8 MPLAB REAL ICE In-Circuit package types. The ICSP™ cable assembly is included Emulator System as a standard item. In Stand-Alone mode, the MPLAB MPLAB REAL ICE In-Circuit Emulator System is PM3 Device Programmer can read, verify and program Microchip’s next generation high-speed emulator for PIC devices without a PC connection. It can also set Microchip Flash DSC and MCU devices. It debugs and code protection in this mode. The MPLAB PM3 programs PIC® Flash MCUs and dsPIC® Flash DSCs connects to the host PC via an RS-232 or USB cable. with the easy-to-use, powerful graphical user interface of The MPLAB PM3 has high-speed communications and the MPLAB Integrated Development Environment (IDE), optimized algorithms for quick programming of large included with each kit. memory devices and incorporates an SD/MMC card for file storage and secure data applications. The MPLAB REAL ICE probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high-speed, noise tolerant, Low- Voltage Differential Signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software break- points and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2009 Microchip Technology Inc. DS39682E-page 301

PIC18F45J10 FAMILY 23.11 PICSTART Plus Development 23.13 Demonstration, Development and Programmer Evaluation Boards The PICSTART Plus Development Programmer is an A wide variety of demonstration, development and easy-to-use, low-cost, prototype programmer. It evaluation boards for various PIC MCUs and dsPIC connects to the PC via a COM (RS-232) port. MPLAB DSCs allows quick application development on fully func- Integrated Development Environment software makes tional systems. Most boards include prototyping areas for using the programmer simple and efficient. The adding custom circuitry and provide application firmware PICSTART Plus Development Programmer supports and source code for examination and modification. most PIC devices in DIP packages up to 40 pins. The boards support a variety of features, including LEDs, Larger pin count devices, such as the PIC16C92X and temperature sensors, switches, speakers, RS-232 PIC17C76X, may be supported with an adapter socket. interfaces, LCD displays, potentiometers and additional The PICSTART Plus Development Programmer is CE EEPROM memory. compliant. The demonstration and development boards can be used in teaching environments, for prototyping custom 23.12 PICkit 2 Development Programmer circuits and for learning about various microcontroller The PICkit™ 2 Development Programmer is a low-cost applications. programmer and selected Flash device debugger with In addition to the PICDEM™ and dsPICDEM™ demon- an easy-to-use interface for programming many of stration/development board series of circuits, Microchip Microchip’s baseline, mid-range and PIC18F families of has a line of evaluation kits and demonstration software Flash memory microcontrollers. The PICkit 2 Starter Kit for analog filter design, KEELOQ® security ICs, CAN, includes a prototyping development board, twelve IrDA®, PowerSmart battery management, SEEVAL® sequential lessons, software and HI-TECH’s PICC™ evaluation system, Sigma-Delta ADC, flow rate Lite C compiler, and is designed to help get up to speed sensing, plus many more. quickly using PIC® microcontrollers. The kit provides Check the Microchip web page (www.microchip.com) everything needed to program, evaluate and develop for the complete list of demonstration, development applications using Microchip’s powerful, mid-range and evaluation kits. Flash memory family of microcontrollers. DS39682E-page 302 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 24.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +100°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any digital-only input MCLR I/O pin with respect to VSS ...........................................................-0.3V to 6.0V Voltage on any combined digital and analog pin with respect to VSS ............................................-0.3V to (VDD + 0.3V) Voltage on VDDCORE with respect to VSS...................................................................................................-0.3V to 2.75V Voltage on VDD with respect to VSS ........................................................................................................... -0.3V to 4.0V Total power dissipation (Note 1)...............................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300mA Maximum current into VDD pin..............................................................................................................................250mA Maximum output current sunk by any PORTB and PORTC I/O pin........................................................................25mA Maximum output current sunk by any PORTA, PORTD, and PORTE I/O pin...........................................................4mA Maximum output current sourced by any PORTB and PORTC I/O pin..................................................................25mA Maximum output current sourced by any PORTA, PORTD, and PORTE I/O pin.....................................................4mA Maximum current sunk by all ports combined.......................................................................................................200mA Maximum current sourced by all ports combined..................................................................................................200mA Note1: Power dissipation is calculated as follows: Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL) † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2009 Microchip Technology Inc. DS39682E-page 303

PIC18F45J10 FAMILY FIGURE 24-1: PIC18LF45J10 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 3.00V 2.75V 2.7V 1) ()E 2.50V PIC18LF24J10/25J10/44J10/45J10 R O 2.35V C 2.25V D D V ( e 2.00V g a olt V 4 MHz 40 MHz Frequency For VDDCORE values, 2V to 2.35V, FMAX = (102.85 MHz/V) * (VDDCORE – 2V) + 4 MHz Note 1: For devices without the voltage regulator, VDD and VDDCORE must be maintained so that VDDCORE ≤ VDD ≤ 3.6V. FIGURE 24-2: PIC18F45J10 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 4.0V 3.6V 3.5V ) PIC18F2XJ10/4XJ10 D D 3.0V 2.7V V ( e 2.5V g a t l o V 4 MHz 40 MHz Frequency DS39682E-page 304 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 2D005 4.1 DC Characteristics: Supply Voltage PIC18F24J10/25J10/44J10/45J10 (Industrial) PIC18LF24J10/25J10/44J10/45J10 (Industrial) PIC18F45J10 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Characteristic Min Typ Max Units Conditions No. D001 VDD Supply Voltage VDDCORE — 3.6 V PIC18LF4XJ10, PIC18LF2XJ10 D001 VDD Supply Voltage 2.7(1) — 3.6 V PIC18F4X/2XJ10 D001B VDDCORE External Supply for 2.0 — 2.7 V Valid only in parts designated “LF”. Microcontroller Core See Section21.3 “On-Chip Voltage Regulator” for details. D002 VDR RAM Data Retention 1.5 — — V Voltage(1) D003 VPOR VDD Start Voltage — — 0.15 V SeeSection5.3 “Power-on to ensure internal Reset (POR)” for details Power-on Reset signal D004 SVDD VDD Rise Rate 0.05 — — V/ms See Section5.3 “Power-on to ensure internal Reset (POR)” for details Power-on Reset signal D005 VBOR Brown-out Reset (BOR) 2.35 2.5 2.7 V Voltage Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. © 2009 Microchip Technology Inc. DS39682E-page 305

PIC18F45J10 FAMILY 24.2 DC Characteristics: Power-Down and Supply Current PIC18F24J10/25J10/44J10/45J10 (Industrial) PIC18LF24J10/25J10/44J10/45J10 (Industrial) PIC18F45J10 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Typ Max Units Conditions No. Power-Down Current (IPD)(1) All devices 19 104 μA -40°C VDD = 2.5V 25 104 μA +25°C (Sleep mode) 40 184 μA +85°C All devices 20 203 μA -40°C VDD = 3.3V 25 203 μA +25°C (Sleep mode) 45 289 μA +85°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. DS39682E-page 306 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 24.2 DC Characteristics: Power-Down and Supply Current PIC18F24J10/25J10/44J10/45J10 (Industrial) PIC18LF24J10/25J10/44J10/45J10 (Industrial) (Continued) PIC18F45J10 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) All devices 3.8 7.7 mA -40°C 3.7 7.5 mA +25°C VDD = 2.5V 3.7 7.5 mA +85°C FOSC = 31kHz (RC_RUN mode, All devices 3.9 7.9 mA -40°C Internal oscillator source) 3.7 7.5 mA +25°C VDD = 3.3V 3.7 7.5 mA +85°C All devices 64 167 μA -40°C 77 193 μA +25°C VDD = 2.5V 95 269 μA +85°C FOSC = 31kHz (RC_IDLE mode, All devices 65 266 μA -40°C Internal oscillator source) 79 294 μA +25°C VDD = 3.3V 98 360 μA +85°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. © 2009 Microchip Technology Inc. DS39682E-page 307

PIC18F45J10 FAMILY 24.2 DC Characteristics: Power-Down and Supply Current PIC18F24J10/25J10/44J10/45J10 (Industrial) PIC18LF24J10/25J10/44J10/45J10 (Industrial) (Continued) PIC18F45J10 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) All devices 4.2 8.5 mA -40°C 3.9 8.0 mA +25°C VDD = 2.5V 3.6 7.3 mA +85°C FOSC = 1MHz (PRI_RUN mode, All devices 4.3 8.6 mA -40°C EC oscillator) 4.0 8.1 mA +25°C VDD = 3.3V 3.7 7.6 mA +85°C All devices 4.6 9.3 mA -40°C 4.3 8.7 mA +25°C VDD = 2.5V 4.0 8.1 mA +85°C FOSC = 4MHz (PRI_RUN mode, All devices 4.7 9.4 mA -40°C EC oscillator) 4.4 8.8 mA +25°C VDD = 3.3V 4.1 8.2 mA +85°C All devices 11.0 22.0 mA -40°C 10.5 21.0 mA +25°C VDD = 2.5V 10.0 20.0 mA +85°C FOSC = 40MHz (PRI_RUN mode, All devices 12.0 24.0 mA -40°C EC oscillator) 11.5 23.0 mA +25°C VDD = 3.3V 11.0 22.0 mA +85°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. DS39682E-page 308 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 24.2 DC Characteristics: Power-Down and Supply Current PIC18F24J10/25J10/44J10/45J10 (Industrial) PIC18LF24J10/25J10/44J10/45J10 (Industrial) (Continued) PIC18F45J10 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) All devices 6.2 14 mA -40°C FOSC = 4MHZ, 5.7 13 mA +25°C VDD = 2.5V 16 MHZ internal 5.7 13 mA +85°C (PRI_RUN HS+PLL) All devices 6.6 15 mA -40°C FOSC = 4MHZ, 6.1 14 mA +25°C VDD = 3.3V 16 MHZ internal 6.1 14 mA +85°C (PRI_RUN HS+PLL) All devices 11.0 22 mA -40°C FOSC = 10MHZ, 10.5 21 mA +25°C VDD = 2.5V 40 MHZ internal 10.0 20 mA +85°C (PRI_RUN HS+PLL) All devices 12.0 24 mA -40°C FOSC = 10MHZ, 11.5 23 mA +25°C VDD = 3.3V 40 MHZ internal 11.0 22 mA +85°C (PRI_RUN HS+PLL) Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. © 2009 Microchip Technology Inc. DS39682E-page 309

PIC18F45J10 FAMILY 24.2 DC Characteristics: Power-Down and Supply Current PIC18F24J10/25J10/44J10/45J10 (Industrial) PIC18LF24J10/25J10/44J10/45J10 (Industrial) (Continued) PIC18F45J10 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) All devices 150 337 μA -40°C 160 355 μA +25°C VDD = 2.5V 220 512 μA +85°C FOSC = 1MHz (PRI_IDLE mode, All devices 190 518 μA -40°C EC oscillator) 200 528 μA +25°C VDD = 3.3V 250 647 μA +85°C All devices 350 737 μA -40°C 375 787 μA +25°C VDD = 2.5V 420 917 μA +85°C FOSC = 4MHz (PRI_IDLE mode, All devices 410 954 μA -40°C EC oscillator) 0.450 1.03 mA +25°C VDD = 3.3V 0.475 1.13 mA +85°C All devices 5.0 10.1 mA -40°C 5.2 10.6 mA +25°C VDD = 2.5V 5.5 11.1 mA +85°C FOSC = 40MHz (PRI_IDLE mode, All devices 5.5 11.1 mA -40°C EC oscillator) 6.0 12.1 mA +25°C VDD = 3.3V 6.5 13.1 mA +85°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. DS39682E-page 310 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 24.2 DC Characteristics: Power-Down and Supply Current PIC18F24J10/25J10/44J10/45J10 (Industrial) PIC18LF24J10/25J10/44J10/45J10 (Industrial) (Continued) PIC18F45J10 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Typ Max Units Conditions No. Supply Current (IDD)(2) All devices 4.1 8.3 mA -40°C 3.8 7.7 mA +25°C VDD = 2.5V 3.8 7.7 mA +85°C FOSC = 32kHz (SEC_RUN mode, All devices 4.1 8.3 mA -40°C Timer1 as clock) 3.8 7.7 mA +25°C VDD = 3.3V 3.8 7.7 mA +85°C All devices 66 169 μA -40°C 79 195 μA +25°C VDD = 2.5V 97 271 μA +85°C FOSC = 32kHz (SEC_IDLE mode, All devices 67 268 μA -40°C Timer1 as clock) 81 296 μA +25°C VDD = 3.3V 100 362 μA +85°C Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. © 2009 Microchip Technology Inc. DS39682E-page 311

PIC18F45J10 FAMILY 24.2 DC Characteristics: Power-Down and Supply Current PIC18F24J10/25J10/44J10/45J10 (Industrial) PIC18LF24J10/25J10/44J10/45J10 (Industrial) (Continued) PIC18F45J10 Family Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Device Typ Max Units Conditions No. Module Differential Currents (ΔIWDT, ΔIOSCB, ΔIAD) D022 Watchdog Timer 3.2 6.5 μA -40°C (ΔIWDT) 3.2 6.5 μA +25°C VDD = 2.5V 5.1 10.3 μA +85°C 3.5 7.1 μA -40°C 3.5 7.1 μA +25°C VDD = 3.3V 5.5 11.2 μA +85°C D025 Timer1 Oscillator 8.4 17 μA -40°C (ΔIOSCB) 11.5 24 μA +25°C VDD = 2.5V 32kHz on Timer1(3) 13.2 30 μA +85°C 9.6 20 μA -40°C 12.4 25 μA +25°C VDD = 3.3V 32kHz on Timer1(3) 14.1 29 μA +85°C D026 A/D Converter 1.0 5 μA -40°C to +85°C VDD = 2.5V A/D on, not converting (ΔIAD) 1.2 5 μA -40°C to +85°C VDD = 3.3V Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). 2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. DS39682E-page 312 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 24.3 DC Characteristics: PIC18F45J10 Family (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Characteristic Min Max Units Conditions No. VIL Input Low Voltage All I/O Ports: D030 with TTL Buffer VSS 0.15 VDD V VDD < 3.3V D030A — 0.8 V 3.3V ≤ VDD ≤ 3.6V D031 with Schmitt Trigger Buffer VSS 0.2 VDD V D032 MCLR VSS 0.2 VDD V D033 OSC1 VSS 0.3 VDD V HS, HSPLL modes D033A OSC1 VSS 0.2 VDD V EC, ECPLL modes(1) D034 T1CKI VSS 0.3 V VIH Input High Voltage I/O Ports with non 5.5V Tolerance:(4) D040 with TTL Buffer 0.25 VDD + 0.8V VDD V VDD < 3.3V D040A 2.0 VDD V 3.3V ≤ VDD ≤ 3.6V D041 with Schmitt Trigger Buffer 0.8 VDD VDD V I/O Ports with 5.5V Tolerance:(4) Dxxx with TTL Buffer 0.25 VDD + 0.8V 5.5 V VDD < 3.3V DxxxA 2.0 5.5 V 3.3V ≤ VDD ≤ 3.6V Dxxx with Schmitt Trigger Buffer 0.8 VDD 5.5 V D042 MCLR 0.8 VDD VDD V D043 OSC1 0.7 VDD VDD V HS, HSPLL modes D043A OSC1 0.8 VDD VDD V EC, ECPLL modes D044 T1CKI 1.6 VDD V IIL Input Leakage Current(2,3) D060 I/O Ports with non 5.5V — ±0.2 μA VSS ≤ VPIN ≤ VDD, Tolerance(4) Pin at high-impedance D060A I/O Ports with 5.5V — ±0.2 μA VSS ≤ VPIN ≤ 5.5V, Tolerance(4) Pin at high-impedance D061 MCLR — ±0.2 μA Vss ≤ VPIN ≤ VDD D063 OSC1 — ±0.2 μA Vss ≤ VPIN ≤ VDD IPU Weak Pull-up Current D070 IPURB PORTB Weak Pull-up Current 30 240 μA VDD = 3.3V, VPIN = VSS Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Refer to Table10-2 for the pins that have corresponding tolerance limits. © 2009 Microchip Technology Inc. DS39682E-page 313

PIC18F45J10 FAMILY 24.3 DC Characteristics: PIC18F45J10 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol Characteristic Min Max Units Conditions No. VOL Output Low Voltage D080 I/O Ports (PORTB, PORTC) — 0.4 V IOL = 8.5 mA, VDD 3.3V -40°C to +85°C I/O Ports (PORTA, PORTD, — 0.4 V IOL = 3.4 mA, VDD 3.3V PORTE) -40°C to +85°C D083 OSC2/CLKO — 0.4 V IOL = 1.6 mA, VDD 3.3V (EC mode) -40°C to +85°C VOH Output High Voltage(3) D090 I/O Ports (PORTB, PORTC) 2.4 — V IOH = -6 mA, VDD 3.3V -40°C to +85°C I/O Ports (PORTA, PORTD, 2.4 — V IOH = -2 mA, VDD 3.3V PORTE) -40°C to +85°C D092 OSC2/CLKO 2.4 — V IOH = 1.0 mA, VDD 3.3V (EC mode) -40°C to +85°C Capacitive Loading Specs on Output Pins D100(4) COSC2 OSC2 Pin — 15 pF In HS mode when external clock is used to drive OSC1 D101 CIO All I/O Pins — 50 pF To meet the AC Timing Specifications D102 CB SCLx, SDAx — 400 pF I2C™ Specification Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: Refer to Table10-2 for the pins that have corresponding tolerance limits. DS39682E-page 314 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY TABLE 24-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Sym Characteristic Min Typ† Max Units Conditions No. Program Flash Memory D130 EP Cell Endurance 100 1K — E/W -40°C to +85°C D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage D132B VPEW Voltage for Self-Timed Erase or Write: VDD 2.7 — 3.6 V PIC18FXXJ10 VDDCORE 2.25 — 2.7 V PIC18LFXXJ10 D133A TIW Self-Timed Write Cycle Time — 2.8 — ms D133B TIE Self-Timed Page Erased Cycle — 33.0 — ms Time D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications are violated D135 IDDP Supply Current during — 10 — mA Programming † Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2009 Microchip Technology Inc. DS39682E-page 315

PIC18F45J10 FAMILY TABLE 24-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. D300 VIOFF Input Offset Voltage — ±5.0 ±25 mV D301 VICM Input Common Mode Voltage* 0 — VDD – 1.5 V D302 CMRR Common Mode Rejection Ratio* 55 — — dB D303 TRESP Response Time(1)* — 150 400 ns D304 TMC2OV Comparator Mode Change to — — 10 μs Output Valid* D305 VIRV Internal Reference Voltage — 1.2 — V * These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. TABLE 24-3: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. D310 VRES Resolution VDD/24 — VDD/32 LSb D311 VRAA Absolute Accuracy — — 1/2 LSb D312 VRUR Unit Resistor Value (R) — 2k — Ω 310 TSET Settling Time(1) — — 10 μs Note 1: Settling time measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’. TABLE 24-4: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param Sym Characteristics Min Typ Max Units Comments No. VRGOUT Regulator Output Voltage — 2.5 — V CEFC External Filter Capacitor 4.7 10 — μF Series resistance < 3 Ohm Value recommended; < 5 Ohm required. * These parameters are characterized but not tested. Parameter numbers not yet assigned for these specifications. DS39682E-page 316 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 24.4 AC (Timing) Characteristics 24.4.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKO rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO Stop condition STA Start condition © 2009 Microchip Technology Inc. DS39682E-page 317

PIC18F45J10 FAMILY 24.4.2 TIMING CONDITIONS The temperature and voltages specified in Table24-5 apply to all timing specifications unless otherwise noted. Figure24-3 specifies the load conditions for the timing specifications. TABLE 24-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial AC CHARACTERISTICS Operating voltage VDD range as described in DC spec Section24.1 and Section24.3. FIGURE 24-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 Load Condition 2 VDD/2 RL Pin CL VSS CL Pin RL = 464Ω VSS CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports CL = 15 pF for OSC2/CLK0 DS39682E-page 318 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 24.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 24-4: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO TABLE 24-6: EXTERNAL CLOCK TIMING REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 1A FOSC External CLKI Frequency(1) DC 40 MHz EC Oscillator mode Oscillator Frequency(1) 4 25 MHz HS Oscillator mode 1 TOSC External CLKI Period(1) 25 — ns EC Oscillator mode Oscillator Period(1) 25 250 ns HS Oscillator mode 2 TCY Instruction Cycle Time(1) 100 — ns TCY = 4/FOSC, Industrial 3 TOSL, External Clock in (OSC1) 10 — ns EC Oscillator mode TOSH High or Low Time 4 TOSR, External Clock in (OSC1) — 7.5 ns EC Oscillator mode TOSF Rise or Fall Time Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. © 2009 Microchip Technology Inc. DS39682E-page 319

PIC18F45J10 FAMILY TABLE 24-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5V TO 3.6V) Param Sym Characteristic Min Typ† Max Units Conditions No. F10 FOSC Oscillator Frequency Range 4 — 10 MHz F11 FSYS On-Chip VCO System Frequency 20 — 40 MHz F12 ΤRC PLL Start-up Time (lock time) — — 2 ms F13 ΔCLK CLKO Stability (Jitter) -2 — +2 % † Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 24-8: AC CHARACTERISTICS: INTERNAL RC ACCURACY PIC18F24J10/25J10/44J10/45J10 (INDUSTRIAL) Param Characteristic Min Typ Max Units Conditions No. INTRC Accuracy @ Freq = 31 kHz(1) 21.7 — 40.3 kHz Note 1: Change of INTRC frequency as VDD core changes. DS39682E-page 320 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY FIGURE 24-5: CLKO AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKO 13 12 14 19 18 16 I/O pin (Input) 17 15 I/O pin Old Value New Value (Output) 20, 21 Note: Refer to Figure24-3 for load conditions. TABLE 24-9: CLKO AND I/O TIMING REQUIREMENTS Param Symbol Characteristic Min Typ Max Units Conditions No. 10 TOSH2CKL OSC1 ↑ to CLKO ↓ — 75 200 ns 11 TOSH2CKH OSC1 ↑ to CLKO ↑ — 75 200 ns 12 TCKR CLKO Rise Time — 15 30 ns 13 TCKF CLKO Fall Time — 15 30 ns 14 TCKL2IOV CLKO ↓ to Port Out Valid — — 0.5 TCY + 20 ns 15 TIOV2CKH Port In Valid before CLKO ↑ 0.25 TCY + 25 — — ns 16 TCKH2IOI Port In Hold after CLKO ↑ 0 — — ns 17 TOSH2IOV OSC1 ↑ (Q1 cycle) to Port Out Valid — 50 150 ns 18 TOSH2IOI OSC1 ↑ (Q2 cycle) to Port Input Invalid 100 — — ns 18A (I/O in hold time) 200 — — ns 19 TIOV2OSH Port Input Valid to OSC1 ↑ 0 — — ns (I/O in setup time) 20 TIOR Port Output Rise Time — — 6 ns 21 TIOF Port Output Fall Time — — 5 ns 22† TINP INTx pin High or Low Time TCY — — ns 23† TRBP RB<7:4> Change INTx High or Low Time TCY — — ns † These parameters are asynchronous events not related to any internal clock edges. © 2009 Microchip Technology Inc. DS39682E-page 321

PIC18F45J10 FAMILY FIGURE 24-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure24-3 for load conditions. FIGURE 24-7: BROWN-OUT RESET TIMING BVDD VDD VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference Voltage Stable TABLE 24-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol Characteristic Min Typ Max Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — μs 31 TWDT Watchdog Timer Time-out Period 2.8 4.1 5.4 ms (no postscaler) 32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period 33 TPWRT Power-up Timer Period 46.2 66 85.8 ms 34 TIOZ I/O High-Impedance from MCLR — 2 — μs Low or Watchdog Timer Reset 38 TCSD CPU Start-up Time — 200 — μs DS39682E-page 322 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY FIGURE 24-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1OSO/T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure24-3 for load conditions. TABLE 24-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 40 TT0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 41 TT0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns 42 TT0P T0CKI Period No prescaler TCY + 10 — ns With prescaler Greater of: — ns N = prescale 20ns or value (TCY + 40)/N (1, 2, 4,..., 256) 45 TT1H T1CKI High Synchronous, no prescaler 0.5 TCY + 20 — ns Time Synchronous, with prescaler 10 — ns Asynchronous 30 — ns 46 TT1L T1CKI Low Synchronous, no prescaler 0.5 TCY + 5 — ns Time Synchronous, with prescaler 10 — ns Asynchronous 30 — ns 47 TT1P T1CKI Input Synchronous Greater of: — ns N = prescale Period 20ns or value (TCY + 40)/N (1, 2, 4, 8) Asynchronous 60 — ns FT1 T1CKI Oscillator Input Frequency Range DC 50 kHz 48 TCKE2TMRI Delay from External T1CKI Clock Edge to 2 TOSC 7 TOSC — Timer Increment © 2009 Microchip Technology Inc. DS39682E-page 323

PIC18F45J10 FAMILY FIGURE 24-9: CAPTURE/COMPARE/PWM TIMINGS (INCLUDING ECCP MODULE) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 54 Note: Refer to Figure24-3 for load conditions. TABLE 24-12: CAPTURE/COMPARE/PWM REQUIREMENTS (INCLUDING ECCP MODULE) Param Symbol Characteristic Min Max Units Conditions No. 50 TCCL CCPx Input Low No prescaler 0.5 TCY + 20 — ns Time With prescaler 10 — ns 51 TCCH CCPx Input No prescaler 0.5 TCY + 20 — ns High Time With prescaler 10 — ns 52 TCCP CCPx Input Period 3 TCY + 40 — ns N = prescale N value (1, 4 or 16) 53 TCCR CCPx Output Fall Time — 25 ns 54 TCCF CCPx Output Fall Time — 25 ns TABLE 24-13: PARALLEL SLAVE PORT REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 62 TdtV2wrH Data In Valid before WR ↑ or CS ↑ (setup time) 20 — ns 63 TwrH2dtI WR ↑ or CS ↑ to Data–In Invalid (hold time) 20 — ns 64 TrdL2dtV RD ↓ and CS ↓ to Data–Out Valid — 80 ns 65 TrdH2dtI RD ↑ or CS ↓ to Data–Out Invalid 10 30 ns 66 TibfINH Inhibit of the IBF Flag bit being Cleared from — 3 TCY WR ↑ or CS ↑ DS39682E-page 324 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY FIGURE 24-10: EXAMPLE SPI™ MASTER MODE TIMING (CKE=0) SSx 70 SCKx (CKP = 0) 71 72 78 79 SCKx (CKP = 1) 79 78 80 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure24-3 for load conditions. TABLE 24-14: EXAMPLE SPI™ MODE REQUIREMENTS (CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input TCY — ns TSSL2SCL 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 20 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns (Note 1) of Byte 2 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 40 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 78 TSCR SCKx Output Rise Time (Master mode) — 25 ns 79 TSCF SCKx Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns TSCL2DOV Note 1: Only if Parameter #71A and #72A are used. © 2009 Microchip Technology Inc. DS39682E-page 325

PIC18F45J10 FAMILY FIGURE 24-11: EXAMPLE SPI™ MASTER MODE TIMING (CKE=1) SSx 81 SCKx (CKP = 0) 71 72 79 73 SCKx (CKP = 1) 80 78 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 Note: Refer to Figure24-3 for load conditions. TABLE 24-15: EXAMPLE SPI™ MODE REQUIREMENTS (CKE=1) Param. Symbol Characteristic Min Max Units Conditions No. 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 20 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns (Note 1) of Byte 2 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 40 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 78 TSCR SCKx Output Rise Time (Master mode) — 25 ns 79 TSCF SCKx Output Fall Time (Master mode) — 25 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns TSCL2DOV 81 TDOV2SCH, SDOx Data Output Setup to SCKx Edge TCY — ns TDOV2SCL Note 1: Only if Parameter #71A and #72A are used. DS39682E-page 326 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY FIGURE 24-12: EXAMPLE SPI™ SLAVE MODE TIMING (CKE=0) SSx 70 SCKx (CKP = 0) 83 71 72 78 79 SCKx (CKP = 1) 79 78 80 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 77 SSDDIIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure24-3 for load conditions. TABLE 24-16: EXAMPLE SPI™ MODE REQUIREMENTS (CKE=0) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input TCY — ns TSSL2SCL 71 TSCH SCKx Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TSCL SCKx Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge 20 — ns TDIV2SCL 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 40 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 77 TSSH2DOZ SSx ↑ to SDOx Output High-Impedance 10 50 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns TSCL2DOV 83 TSCH2SSH, SSx ↑ after SCKx Edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. © 2009 Microchip Technology Inc. DS39682E-page 327

PIC18F45J10 FAMILY FIGURE 24-13: EXAMPLE SPI™ SLAVE MODE TIMING (CKE=1) 82 SSx 70 SCKx 83 (CKP = 0) 71 72 SCKx (CKP = 1) 80 SDOx MSb bit 6 - - - - - - 1 LSb 75, 76 77 SSDDIIx MSb In bit 6 - - - - 1 LSb In 74 Note: Refer to Figure24-3 for load conditions. TABLE 24-17: EXAMPLE SPI™ SLAVE MODE REQUIREMENTS (CKE=1) Param Symbol Characteristic Min Max Units Conditions No. 70 TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input TCY — ns TSSL2SCL 71 TSCH SCKx Input High Time Continuous 1.25 TCY + 30 — ns 71A (Slave mode) Single Byte 40 — ns (Note 1) 72 TSCL SCKx Input Low Time Continuous 1.25 TCY + 30 — ns 72A (Slave mode) Single Byte 40 — ns (Note 1) 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2) 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge 20 — ns TSCL2DIL 75 TDOR SDOx Data Output Rise Time — 25 ns 76 TDOF SDOx Data Output Fall Time — 25 ns 77 TSSH2DOZ SSx ↑ to SDOx Output High-Impedance 10 50 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge — 50 ns TSCL2DOV 82 TSSL2DOV SDOx Data Output Valid after SSx ↓ Edge — 50 ns 83 TSCH2SSH, SSx ↑ after SCKx Edge 1.5 TCY + 40 — ns TSCL2SSH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used. DS39682E-page 328 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY FIGURE 24-14: I2C™ BUS START/STOP BITS TIMING SCLx 91 93 90 92 SDAx Start Stop Condition Condition Note: Refer to Figure24-3 for load conditions. TABLE 24-18: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated Setup Time 400 kHz mode 600 — Start condition 91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first Hold Time 400 kHz mode 600 — clock pulse is generated 92 TSU:STO Stop Condition 100 kHz mode 4700 — ns Setup Time 400 kHz mode 600 — 93 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — FIGURE 24-15: I2C™ BUS DATA TIMING 103 100 102 101 SCLx 90 106 107 91 92 SDAx In 110 109 109 SDAx Out Note: Refer to Figure24-3 for load conditions. © 2009 Microchip Technology Inc. DS39682E-page 329

PIC18F45J10 FAMILY TABLE 24-19: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 4.0 — μs 400 kHz mode 0.6 — μs MSSP Module 1.5 TCY — 101 TLOW Clock Low Time 100 kHz mode 4.7 — μs 400 kHz mode 1.3 — μs MSSP Module 1.5 TCY — 102 TR SDAx and SCLx Rise Time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 103 TF SDAx and SCLx Fall Time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF 90 TSU:STA Start Condition Setup Time 100 kHz mode 4.7 — μs Only relevant for Repeated 400 kHz mode 0.6 — μs Start condition 91 THD:STA Start Condition Hold Time 100 kHz mode 4.0 — μs After this period, the first clock 400 kHz mode 0.6 — μs pulse is generated 106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 μs 107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns (Note 2) 400 kHz mode 100 — ns 92 TSU:STO Stop Condition Setup Time 100 kHz mode 4.7 — μs 400 kHz mode 0.6 — μs 109 TAA Output Valid from Clock 100 kHz mode — 3500 ns (Note 1) 400 kHz mode — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free 400 kHz mode 1.3 — μs before a new transmission can start D102 CB Bus Capacitive Loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions. 2: A Fast mode I2C™ bus device can be used in a Standard mode I2C bus system, but the requirement, TSU:DAT≥250ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, TR max. + TSU:DAT=1000+250=1250ns (according to the Standard mode I2C bus specification), before the SCLx line is released. DS39682E-page 330 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY FIGURE 24-16: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCLx 91 93 90 92 SDAx Start Stop Condition Condition Note: Refer to Figure24-3 for load conditions. TABLE 24-20: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — first clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins. FIGURE 24-17: MASTER SSP I2C™ BUS DATA TIMING 103 100 102 101 SCLx 90 106 91 107 92 SDAx In 109 109 110 SDAx Out Note: Refer to Figure24-3 for load conditions. © 2009 Microchip Technology Inc. DS39682E-page 331

PIC18F45J10 FAMILY TABLE 24-21: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 102 TR SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns 103 TF SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns 90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms Repeated Start condition 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — ms clock pulse is generated 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 106 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 ms 1 MHz mode(1) — — ns 107 TSU:DAT Data Input 100 kHz mode 250 — ns (Note 2) Setup Time 400 kHz mode 100 — ns 1 MHz mode(1) — — ns 92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 109 TAA Output Valid 100 kHz mode — 3500 ns from Clock 400 kHz mode — 1000 ns 1 MHz mode(1) — — ns 110 TBUF Bus Free Time 100 kHz mode 4.7 — ms Time the bus must be free 400 kHz mode 1.3 — ms before a new transmission can start 1 MHz mode(1) — — ms D102 CB Bus Capacitive Loading — 400 pF Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107≥250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, parameter #102 + parameter #107=1000+250=1250ns (for 100 kHz mode), before the SCLx line is released. DS39682E-page 332 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY FIGURE 24-18: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TX/CK pin 121 121 RX/DT pin 120 122 Note: Refer to Figure24-3 for load conditions. TABLE 24-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 120 TCKH2DTV SYNC XMIT (MASTER and SLAVE) Clock High to Data Out Valid — 40 ns 121 TCKRF Clock Out Rise Time and Fall Time (Master mode) — 20 ns 122 TDTRF Data Out Rise Time and Fall Time — 20 ns FIGURE 24-19: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING TX/CK pin 125 RX/DT pin 126 Note: Refer to Figure24-3 for load conditions. TABLE 24-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Param. Symbol Characteristic Min Max Units Conditions No. 125 TDTV2CKL SYNC RCV (MASTER and SLAVE) Data Hold before CK ↓ (DT hold time) 10 — ns 126 TCKL2DTL Data Hold after CK ↓ (DT hold time) 15 — ns © 2009 Microchip Technology Inc. DS39682E-page 333

PIC18F45J10 FAMILY TABLE 24-24: A/D CONVERTER CHARACTERISTICS:PIC18F24J10/25J10/44J10/45J10 (INDUSTRIAL) Param Symbol Characteristic Min Typ Max Units Conditions No. A01 NR Resolution — — 10 bit ΔVREF ≥ 3.0V A03 EIL Integral Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A04 EDL Differential Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A06 EOFF Offset Error — — <±3 LSb ΔVREF ≥ 3.0V A07 EGN Gain Error — — <±3 LSb ΔVREF ≥ 3.0V A10 — Monotonicity Guaranteed(1) — VSS ≤ VAIN ≤ VREF A20 ΔVREF Reference Voltage Range 1.8 — — V VDD < 3.0V (VREFH – VREFL) 3 — — V VDD ≥ 3.0V A21 VREFH Reference Voltage High VSS — VREFH V A22 VREFL Reference Voltage Low VSS – 0.3V — VDD – 3.0V V A25 VAIN Analog Input Voltage VREFL — VREFH V A30 ZAIN Recommended Impedance of — — 2.2 kΩ Analog Voltage Source A50 IREF VREF Input Current(2) — — 5 μA During VAIN acquisition. — — 150 μA During A/D conversion cycle. Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF- pin or VSS, whichever is selected as the VREFL source. 3: Maximum allowed impedance is 8.8 kΩ. This requires higher acquisition time than described in the A/D chapter. FIGURE 24-20: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK 132 . . . . . . A/D DATA 9 8 7 2 1 0 ADRES OLD_DATA NEW_DATA ADIF TCY GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. DS39682E-page 334 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY TABLE 24-25: A/D CONVERSION REQUIREMENTS Param Symbol Characteristic Min Max Units Conditions No. 130 TAD A/D Clock Period 0.7 25.0(1) μs TOSC based, VREF ≥ 2.0V 131 TCNV Conversion Time 11 12 TAD (not including acquisition time) (Note 2) 132 TACQ Acquisition Time (Note 3) 1.4 — μs -40°C to +85°C 135 TSWC Switching Time from Convert → Sample — (Note 4) Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. 2: ADRES registers may be read on the following TCY cycle. 3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω. 4: On the following cycle of the device clock. © 2009 Microchip Technology Inc. DS39682E-page 335

PIC18F45J10 FAMILY NOTES: DS39682E-page 336 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 25.0 PACKAGING INFORMATION 25.1 Package Marking Information 28-Lead SPDIP Example XXXXXXXXXXXXXXXXX PIC18F24J10 XXXXXXXXXXXXXXXXX -I/SPe3 YYWWNNN 0910017 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX PIC18F24J10-I/SOe3 XXXXXXXXXXXXXXXXXXXX 0910017 XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP Example XXXXXXXXXXXX PIC18F24J10 XXXXXXXXXXXX -I/SSe3 YYWWNNN 0910017 28-Lead QFN Example XXXXXXXX 18F24J10 XXXXXXXX -I/MLe3 YYWWNNN 0910017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. DS39682E-page 337

PIC18F45J10 FAMILY Package Marking Information (Continued) 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX PIC18F44J10-I/Pe3 XXXXXXXXXXXXXXXXXX 0910017 XXXXXXXXXXXXXXXXXX YYWWNNN 44-Lead QFN Example XXXXXXXXXX 18F44J10 XXXXXXXXXX -I/MLe3 XXXXXXXXXX 0910017 YYWWNNN 44-Lead TQFP Example XXXXXXXXXX 18F45J10 XXXXXXXXXX I/PTe3 XXXXXXXXXX 0910017 YYWWNNN DS39682E-page 338 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 25.2 Package Details The following sections give the technical details of the packages. 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(cid:25)(cid:3) (cid:20)(cid:30)(cid:3)(cid:4) (cid:20)(cid:30)-(cid:29) (cid:20)(cid:30)(cid:29)(cid:4) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)--(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)<(cid:29) (cid:20)(cid:3)(cid:24)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:20)-(cid:23)(cid:29) (cid:30)(cid:20)-?(cid:29) (cid:30)(cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:4) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)(cid:29)(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)(cid:4)1 © 2009 Microchip Technology Inc. DS39682E-page 339

PIC18F45J10 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:10)(cid:28)(cid:7)(cid:16)(cid:16)(cid:9)#(cid:21)(cid:18)(cid:16)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)#(cid:24)(cid:9)(cid:25)(cid:9)$(cid:12)(cid:8)(cid:6)%(cid:9)&’((cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)#(cid:22)) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 3 e b h α h φ c A A2 L A1 L1 β 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:30)(cid:20)(cid:3)(cid:5)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:3)(cid:20)?(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:3)(cid:20)(cid:4)(cid:29) = = (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2)(cid:2)+ (cid:25)(cid:30) (cid:4)(cid:20)(cid:30)(cid:4) = (cid:4)(cid:20)-(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:30)(cid:4)(cid:20)-(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:5)(cid:20)(cid:29)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:5)(cid:20)(cid:24)(cid:4)(cid:2)1(cid:22), ,(cid:11)(cid:28)’%(cid:14)(cid:9)(cid:2)@(cid:10)(cid:12)&(cid:7)(cid:10)(cid:15)(cid:28)(cid:16)A (cid:11) (cid:4)(cid:20)(cid:3)(cid:29) = (cid:4)(cid:20)(cid:5)(cid:29) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:4) = (cid:30)(cid:20)(cid:3)(cid:5) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:23)(cid:4)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:3) (cid:4)B = <B 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:30)< = (cid:4)(cid:20)-- 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)-(cid:30) = (cid:4)(cid:20)(cid:29)(cid:30) (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:4) (cid:29)B = (cid:30)(cid:29)B (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)1(cid:10)&&(cid:10)’ (cid:5) (cid:29)B = (cid:30)(cid:29)B !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:30)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:29)(cid:3)1 DS39682E-page 340 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:10)*+(cid:12)(cid:13)(cid:11)(cid:9)(cid:10)(cid:28)(cid:7)(cid:16)(cid:16)(cid:9)#(cid:21)(cid:18)(cid:16)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)(cid:10)(cid:24)(cid:9)(cid:25)(cid:9)(’(cid:26)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)(cid:10)#(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 1 2 b NOTE1 e c A A2 φ A1 L1 L 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:3)(cid:20)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:30)(cid:20)?(cid:29) (cid:30)(cid:20)(cid:5)(cid:29) (cid:30)(cid:20)<(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = = : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:5)(cid:20)(cid:23)(cid:4) (cid:5)(cid:20)<(cid:4) <(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:29)(cid:20)(cid:4)(cid:4) (cid:29)(cid:20)-(cid:4) (cid:29)(cid:20)?(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:24)(cid:20)(cid:24)(cid:4) (cid:30)(cid:4)(cid:20)(cid:3)(cid:4) (cid:30)(cid:4)(cid:20)(cid:29)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:29) (cid:4)(cid:20)(cid:5)(cid:29) (cid:4)(cid:20)(cid:24)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:3)(cid:29)(cid:2)(cid:26).3 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:29) 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)B (cid:23)B <B 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:3) = (cid:4)(cid:20)-< !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)(cid:4)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)-1 © 2009 Microchip Technology Inc. DS39682E-page 341

PIC18F45J10 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9),(cid:21)(cid:7)(cid:8)(cid:9)-(cid:16)(cid:7)(cid:18)%(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7).(cid:6)(cid:9)(cid:23)/(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)010(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31),-! 2(cid:12)(cid:18)*(cid:9)(cid:27)’(((cid:9)(cid:28)(cid:28)(cid:9))(cid:30)(cid:13)(cid:18)(cid:7)(cid:19)(cid:18)(cid:9)(cid:5)(cid:6)(cid:13).(cid:18)* !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D2 EXPOSED PAD e E b E2 2 2 1 1 K N N NOTE1 L TOPVIEW BOTTOMVIEW A A3 A1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:24)(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)- (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26).3 : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)>(cid:7)#&(cid:11) .(cid:3) -(cid:20)?(cid:29) -(cid:20)(cid:5)(cid:4) (cid:23)(cid:20)(cid:3)(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) -(cid:20)?(cid:29) -(cid:20)(cid:5)(cid:4) (cid:23)(cid:20)(cid:3)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)- (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:4) (cid:4)(cid:20)(cid:29)(cid:29) (cid:4)(cid:20)(cid:5)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27).$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)# C (cid:4)(cid:20)(cid:3)(cid:4) = = !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)!(cid:2)!(cid:28)*(cid:2)!(cid:7)(cid:15)(cid:17)"(cid:16)(cid:28)&(cid:14)#(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:30)(cid:4)(cid:29)1 DS39682E-page 342 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9),(cid:21)(cid:7)(cid:8)(cid:9)-(cid:16)(cid:7)(cid:18)%(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7).(cid:6)(cid:9)(cid:23)/(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)010(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31),-! 2(cid:12)(cid:18)*(cid:9)(cid:27)’(((cid:9)(cid:28)(cid:28)(cid:9))(cid:30)(cid:13)(cid:18)(cid:7)(cid:19)(cid:18)(cid:9)(cid:5)(cid:6)(cid:13).(cid:18)* !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) © 2009 Microchip Technology Inc. DS39682E-page 343

PIC18F45J10 FAMILY 3(cid:27)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:20)(cid:21)(cid:7)(cid:16)(cid:9)(cid:22)(cid:13)(cid:4)(cid:5)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:15)(cid:24)(cid:9)(cid:25)(cid:9)0(cid:27)(cid:27)(cid:9)(cid:28)(cid:12)(cid:16)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:15)(cid:20)(cid:22)(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c b1 A1 b e eB 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:23)(cid:4) (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:29)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:3)(cid:29) = (cid:20)(cid:30)(cid:24)(cid:29) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:29)(cid:24)(cid:4) = (cid:20)?(cid:3)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:23)<(cid:29) = (cid:20)(cid:29)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:20)(cid:24)<(cid:4) = (cid:3)(cid:20)(cid:4)(cid:24)(cid:29) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:29) = (cid:20)(cid:3)(cid:4)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< = (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)-(cid:4) = (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) = (cid:20)(cid:4)(cid:3)- : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:5)(cid:4)(cid:4) !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:30)?1 DS39682E-page 344 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 33(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9),(cid:21)(cid:7)(cid:8)(cid:9)-(cid:16)(cid:7)(cid:18)%(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7).(cid:6)(cid:9)(cid:23)/(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)(cid:3)1(cid:3)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31),-! !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D2 EXPOSED PAD e E E2 b 2 2 1 1 N NOTE1 N L K TOPVIEW BOTTOMVIEW A A3 A1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:23)(cid:23) (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:24)(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)- (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26).3 : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . <(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)>(cid:7)#&(cid:11) .(cid:3) ?(cid:20)-(cid:4) ?(cid:20)(cid:23)(cid:29) ?(cid:20)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) <(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) ?(cid:20)-(cid:4) ?(cid:20)(cid:23)(cid:29) ?(cid:20)<(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:29) (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-< ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)(cid:23)(cid:4) (cid:4)(cid:20)(cid:29)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27).$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)# C (cid:4)(cid:20)(cid:3)(cid:4) = = !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)!(cid:2)!(cid:28)*(cid:2)!(cid:7)(cid:15)(cid:17)"(cid:16)(cid:28)&(cid:14)#(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:30)(cid:4)-1 © 2009 Microchip Technology Inc. DS39682E-page 345

PIC18F45J10 FAMILY 33(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9),(cid:21)(cid:7)(cid:8)(cid:9)-(cid:16)(cid:7)(cid:18)%(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7).(cid:6)(cid:9)(cid:23)/(cid:5)(cid:24)(cid:9)(cid:25)(cid:9)(cid:3)1(cid:3)(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31),-! !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS39682E-page 346 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY 33(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)4*(cid:12)(cid:13)(cid:9),(cid:21)(cid:7)(cid:8)(cid:9)-(cid:16)(cid:7)(cid:18)5(cid:7)(cid:19)(cid:11)(cid:9)(cid:23)(cid:15)4(cid:24)(cid:9)(cid:25)(cid:9)6(cid:27)16(cid:27)16(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)%(cid:9)(cid:2)’(cid:27)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:31)4,-(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D1 E e E1 N b NOTE1 1 2 3 NOTE2 α A c φ β A1 A2 L L1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)9(cid:14)(cid:28)#! 7 (cid:23)(cid:23) 9(cid:14)(cid:28)#(cid:2)(cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)<(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:4)(cid:20)(cid:24)(cid:29) (cid:30)(cid:20)(cid:4)(cid:4) (cid:30)(cid:20)(cid:4)(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2)(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = (cid:4)(cid:20)(cid:30)(cid:29) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:29) (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)(cid:5)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:4)(cid:4)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)B -(cid:20)(cid:29)B (cid:5)B : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:30)(cid:3)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:3)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:30)(cid:4)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:30) (cid:30)(cid:4)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:4) 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-(cid:5) (cid:4)(cid:20)(cid:23)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:5) (cid:30)(cid:30)B (cid:30)(cid:3)B (cid:30)-B (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)1(cid:10)&&(cid:10)’ (cid:6) (cid:30)(cid:30)B (cid:30)(cid:3)B (cid:30)-B !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) ,(cid:11)(cid:28)’%(cid:14)(cid:9)!(cid:2)(cid:28)&(cid:2)(cid:8)(cid:10)(cid:9)(cid:15)(cid:14)(cid:9)!(cid:2)(cid:28)(cid:9)(cid:14)(cid:2)(cid:10)(cid:12)&(cid:7)(cid:10)(cid:15)(cid:28)(cid:16)D(cid:2)!(cid:7)E(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:30)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)?1 © 2009 Microchip Technology Inc. DS39682E-page 347

PIC18F45J10 FAMILY 33(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)4*(cid:12)(cid:13)(cid:9),(cid:21)(cid:7)(cid:8)(cid:9)-(cid:16)(cid:7)(cid:18)5(cid:7)(cid:19)(cid:11)(cid:9)(cid:23)(cid:15)4(cid:24)(cid:9)(cid:25)(cid:9)6(cid:27)16(cid:27)16(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)%(cid:9)(cid:2)’(cid:27)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:31)4,-(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS39682E-page 348 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY APPENDIX A: REVISION HISTORY Revision A (March 2005) Original data sheet for PIC18F45J10 family devices. Revision B (November 2006) Packaging diagrams have been updated. Revision C (January 2007) Packaging diagrams have been updated. Revision D (November 2008) Electrical characteristics and packaging diagrams have been updated. Minor edits to text throughout document. Revision E (May 2009) Pin diagrams have been edited to indicate 5.5V tolerant input pins. Packaging diagrams have been updated. Section2.0 “Guidelines for Getting Started with PIC18FJ Microcontrollers” has been added. Minor text edits throughout the document. © 2009 Microchip Technology Inc. DS39682E-page 349

PIC18F45J10 FAMILY APPENDIX B: MIGRATION migrating an application across device families to BETWEEN HIGH-END achieve a new design goal. These are summarized in TableB-1. The areas of difference which could be a DEVICE FAMILIES major impact on migration are discussed in greater detail later in this section. Devices in the PIC18F45J10 family and PIC18F4520 families are very similar in their functions and feature sets. However, there are some potentially important differences which should be considered when TABLE B-1: NOTABLE DIFFERENCES BETWEEN PIC18F45J10 AND PIC18F4520 FAMILIES Characteristic PIC18F45J10 Family PIC18F4520 Family Operating Frequency 40 MHz @ 2.15V 40 MHz @ 4.2V Supply Voltage 2.0V-3.6V 2.0V-5.5V Operating Current Low Lower Program Memory Endurance 1,000 write/erase cycles (typical) 100,000 write/erase cycles (typical) I/O Sink/Source at 25mA PORTB and PORTC only All ports Input Voltage Tolerance on I/O pins 5.5V on digital only pins VDD on all I/O pins I/O 32 36 Pull-ups PORTB PORTB Oscillator Options Limited options More options (EC, HS, XT, LP, RC, (EC, HS, fixed 32kHz INTRC) PLL, flexible INTRC) Program Memory Retention 10 years (minimum) 40 years (minimum) Programming Time (Normalized) 156μs/byte (10ms/64-byte block) 15.6μs/byte (1ms/64-byte block) Programming Entry Low Voltage, Key Sequence VPP and LVP Code Protection Single block, all or nothing Multiple code protection blocks Configuration Words Stored in last 4 words of Stored in Configuration Space, Program Memory space starting at 300000h Start-up Time from Sleep 200μs (typical) 10μs (typical) Power-up Timer Always on Configurable Data EEPROM Not available Available Brown-out Reset Simple BOR(1) Programmable BOR LVD Not available Available A/D Calibration Required Not required In-Circuit Emulation Not available Available TMR3 Not available Available Second MSSP Available(2) Not available Note 1: Brown-out Reset is not available on PIC18LFXXJ10 devices. 2: Available on 40/44-pin devices only. DS39682E-page 350 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY B.1 Power Requirement Differences B.3 Oscillator Differences The most significant difference between the PIC18F4520 family devices have a greater range of PIC18F45J10 family and PIC18F4520 device families oscillator options than PIC18F45J10 family devices. is the power requirements. PIC18F45J10 family The latter family is limited primarily to operating modes devices are designed on a smaller process; this results that support HS and EC oscillators. in lower maximum voltage and higher leakage current. In addition, the PIC18F45J10 family has an internal RC The operating voltage range for PIC18F45J10 family oscillator with only a fixed 32kHz output. The higher devices is 2.0V to 3.6V. One of the VDD pins is separated frequency RC modes of the PIC18F4520 family are not for the core logic supply (VDDCORE). This pin has specific available. voltage and capacitor requirements as described in Section24.0 “Electrical Characteristics”. B.4 Peripherals The current specifications for PIC18F45J10 family The PIC18F45J10 family is able to operate at 40MHz devices are yet to be determined. down to 2.15 volts unlike the PIC18F4520 family where 40MHz operation is limited to 4.2 +V applications. B.2 Pin Differences Peripherals must also be considered when making a There are several differences in the pinouts between conversion between the PIC18F45J10 family and the the PIC18F45J10 family and the PIC18F4520 families: PIC18F4520 families: • Input voltage tolerance • Data EEPROM: PIC18F45J10 family devices do • Output current capabilities not have this module. • Available I/O • BOR: PIC18F45J10 family devices do not have a programmable BOR. Simple brown-out capability Pins on the PIC18F45J10 family that have digital only is provided through the use of the internal voltage input capability will tolerate voltages up to 5.5V and are regulator (not available in PIC18LFXXJ10 thus tolerant to voltages above VDD. Table10-1 in devices). Section10.0 “I/O Ports” contains the complete list. • LVD: PIC18F45J10 family devices do not have In addition to input differences, there are output differ- this module. ences as well. Not all I/O pins can source or sink equal • Timer3 (TMR3) has been removed from the levels of current. Only PORTB and PORTC support the PIC18F45J10 family. 25mA source/sink capability that is supported by all • The T0CKI/C1OUT pins have been moved from output pins on the PIC18F4520. Table10-2 in RA4 to RB5. Section10.0 “I/O Ports” contains the complete list of output capabilities. • The 40/44-pin devices in the PIC18F45J10 family have a second MSSP module available on pins There are additional differences in how some pin func- RD<3:0>. tions are implemented on PIC18F45J10 family devices. First, the OSC1/OSC2 oscillator pins are strictly dedicated to the external oscillator function; there is no option to re-allocate these pins to I/O (RA6 or RA7) as on PIC18F4520 devices. Second, the MCLR pin is dedicated only to MCLR and cannot be configured as an input (RE3). Finally, RA4 does not exist on PIC18F45J10 family devices. All of these pin differences (including power pin differences) should be accounted for when making a conversion between PIC18F4520 and PIC18F45J10 family devices. © 2009 Microchip Technology Inc. DS39682E-page 351

PIC18F45J10 FAMILY NOTES: DS39682E-page 352 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY INDEX Block Diagrams A/D ...........................................................................218 A Analog Input Model ..................................................219 Baud Rate Generator ..............................................178 A/D ...................................................................................215 Capture Mode Operation .........................................129 A/D Converter Interrupt, Configuring .......................219 Comparator Analog Input Model ..............................229 Acquisition Requirements ........................................220 Comparator I/O Operating Modes ...........................226 ADCAL Bit ................................................................223 Comparator Output ..................................................228 ADCON0 Register ....................................................215 Comparator Voltage Reference ...............................232 ADCON1 Register ....................................................215 Comparator Voltage Reference Output ADCON2 Register ....................................................215 Buffer Example ................................................233 ADRESH Register ............................................215, 218 Compare Mode Operation .......................................130 ADRESL Register ....................................................215 Device Clock ..............................................................30 Analog Port Pins, Configuring ..................................221 Enhanced PWM .......................................................137 Associated Registers ...............................................223 EUSART Receive ....................................................205 Automatic Acquisition Time ......................................221 EUSART Transmit ...................................................203 Calculating the Minimum Required External Power-on Reset Circuit Acquisition Time ..............................................220 Calibration ................................................................223 (Slow VDD Power-up) ........................................43 Fail-Safe Clock Monitor ...........................................245 Configuring the Module ............................................219 Generic I/O Port Operation ........................................97 Conversion Clock (TAD) ...........................................221 Interrupt Logic ............................................................84 Conversion Status (GO/DONE Bit) ..........................218 MSSP (I2C Master Mode) ........................................176 Conversions .............................................................222 MSSP (I2C Mode) ....................................................159 Converter Characteristics ........................................334 MSSP (SPI Mode) ...................................................149 Operation in Power-Managed Modes ......................223 On-Chip Reset Circuit ................................................41 Special Event Trigger (ECCP) .........................136, 222 PIC18F24J10/25J10 ..................................................10 Use of the ECCP2 Trigger .......................................222 PIC18F44J10/45J10 ..................................................11 Absolute Maximum Ratings .............................................303 PLL ............................................................................29 AC (Timing) Characteristics .............................................317 PORTD and PORTE (Parallel Slave Port) ...............113 Load Conditions for Device PWM Operation (Simplified) ....................................132 Timing Specifications ......................................318 Reads from Flash Program Memory .........................75 Parameter Symbology .............................................317 Single Comparator ...................................................227 Temperature and Voltage Specifications .................318 Table Read Operation ...............................................71 Timing Conditions ....................................................318 Table Write Operation ...............................................72 Access Bank Table Writes to Flash Program Memory ....................77 Mapping with Indexed Literal Offset Mode .................70 Timer0 in 16-Bit Mode .............................................116 ACKSTAT ........................................................................182 Timer0 in 8-Bit Mode ...............................................116 ACKSTAT Status Flag .....................................................182 Timer1 .....................................................................120 ADCAL Bit ........................................................................223 Timer1 (16-Bit Read/Write Mode) ............................121 ADCON0 Register ............................................................215 Timer2 .....................................................................126 GO/DONE Bit ...........................................................218 Watchdog Timer ......................................................242 ADCON1 Register ............................................................215 BN ....................................................................................258 ADCON2 Register ............................................................215 BNC .................................................................................259 ADDFSR ..........................................................................292 BNN .................................................................................259 ADDLW ............................................................................255 BNOV ..............................................................................260 ADDULNK ........................................................................292 BNZ .................................................................................260 ADDWF ............................................................................255 BOR. See Brown-out Reset. ADDWFC .........................................................................256 BOV .................................................................................263 ADRESH Register ............................................................215 BRA .................................................................................261 ADRESL Register ....................................................215, 218 Break Character (12-Bit) Transmit and Receive ..............208 Analog-to-Digital Converter. See A/D. BRG. See Baud Rate Generator. ANDLW ............................................................................256 Brown-out Reset (BOR) .....................................................43 ANDWF ............................................................................257 and On-Chip Voltage Regulator ..............................243 Assembler Disabling in Sleep Mode ............................................43 MPASM Assembler ..................................................300 BSF ..................................................................................261 Auto-Wake-up on Sync Break Character .........................206 BTFSC .............................................................................262 B BTFSS .............................................................................262 Bank Select Register (BSR) ...............................................58 BTG .................................................................................263 Baud Rate Generator .......................................................178 BZ ....................................................................................264 BC ....................................................................................257 C BCF ..................................................................................258 C Compilers BF ....................................................................................182 MPLAB C18 .............................................................300 BF Status Flag .................................................................182 MPLAB C30 .............................................................300 © 2009 Microchip Technology Inc. DS39682E-page 353

PIC18F45J10 FAMILY Calibration (A/D Converter) ..............................................223 Comparator Voltage Reference .......................................231 CALL ................................................................................264 Accuracy and Error ..................................................232 CALLW .............................................................................293 Associated Registers ...............................................233 Capture (CCP Module) .....................................................129 Configuring ..............................................................231 Associated Registers ...............................................131 Connection Considerations ......................................232 CCP Pin Configuration .............................................129 Effects of a Reset ....................................................232 CCPRxH:CCPRxL Registers ...................................129 Operation During Sleep ...........................................232 Prescaler ..................................................................129 Compare (CCP Module) ..................................................130 Software Interrupt ....................................................129 Associated Registers ...............................................131 Capture (ECCP Module) ..................................................136 CCPRx Register ......................................................130 Capture/Compare/PWM (CCP) ........................................127 Pin Configuration .....................................................130 Capture Mode. See Capture. Software Interrupt ....................................................130 CCP Modules and Timer Resources .......................128 Special Event Trigger ..............................................130 CCPRxH Register ....................................................128 Timer1 Mode Selection ............................................130 CCPRxL Register .....................................................128 Compare (ECCP Module) ................................................136 Compare Mode. See Compare. Special Event Trigger ......................................136, 222 Interactions Between ECCP1/CCP1 and Computed GOTO ...............................................................55 CCP2 for Timer Resources ..............................128 Configuration Bits ............................................................235 Module Configuration ...............................................128 Configuration Register Protection ....................................247 Clock Sources ....................................................................30 Context Saving During Interrupts .......................................95 Default System Clock on Reset .................................31 CPFSEQ ..........................................................................266 Selection Using OSCCON Register ...........................31 CPFSGT ..........................................................................267 CLRF ................................................................................265 CPFSLT ...........................................................................267 CLRWDT ..........................................................................265 Crystal Oscillator/Ceramic Resonator ................................27 Code Examples Customer Change Notification Service ............................363 16 x 16 Signed Multiply Routine ................................82 Customer Notification Service .........................................363 16 x 16 Unsigned Multiply Routine ............................82 Customer Support ............................................................363 8 x 8 Signed Multiply Routine ....................................81 D 8 x 8 Unsigned Multiply Routine ................................81 Changing Between Capture Prescalers ...................129 Data Addressing Modes ....................................................66 Computed GOTO Using an Offset Value ...................55 Comparing Addressing Modes with the Erasing a Flash Program Memory Row .....................76 Extended Instruction Set Enabled .....................69 Fast Register Stack ....................................................55 Direct .........................................................................66 How to Clear RAM (Bank 1) Using Indexed Literal Offset ................................................68 Indirect Addressing ............................................66 Instructions Affected ..........................................68 Implementing a Real-Time Clock Using Indirect .......................................................................66 a Timer1 Interrupt Service ...............................124 Inherent and Literal ....................................................66 Initializing PORTA ......................................................98 Data Memory .....................................................................58 Initializing PORTB ....................................................101 Access Bank ..............................................................60 Initializing PORTC ....................................................104 and the Extended Instruction Set ..............................68 Initializing PORTD ....................................................107 Bank Select Register (BSR) ......................................58 Initializing PORTE ....................................................110 General Purpose Registers .......................................60 Loading the SSP1BUF (SSP1SR) Register .............152 Map for PIC18F45J10 Family ....................................59 Reading a Flash Program Memory Word ..................75 Special Function Registers ........................................61 Saving STATUS, WREG and DAW ................................................................................268 BSR Registers in RAM .......................................95 DC Characteristics ...........................................................313 Writing to Flash Program Memory .............................78 Power-Down and Supply Current ............................306 Code Protection ...............................................................235 Supply Voltage ........................................................305 COMF ...............................................................................266 DCFSNZ ..........................................................................269 Comparator ......................................................................225 DECF ...............................................................................268 Analog Input Connection Considerations .................229 DECFSZ ..........................................................................269 Associated Registers ...............................................229 Default System Clock ........................................................31 Configuration ............................................................226 Development Support ......................................................299 Effects of a Reset .....................................................228 Device Overview ..................................................................7 Interrupts ..................................................................228 Core Features ..............................................................7 Operation .................................................................227 Details on Individual Family Members .........................8 Operation During Sleep ...........................................228 Features (table) ...........................................................9 Outputs ....................................................................227 Other Special Features ................................................8 Reference ................................................................227 Direct Addressing ..............................................................67 External Signal .................................................227 Internal Signal ..................................................227 Response Time ........................................................227 Comparator Specifications ...............................................316 DS39682E-page 354 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY E F Effect on Standard PIC Instructions .................................296 Fail-Safe Clock Monitor ...........................................235, 245 Effects of Power-Managed Modes on Interrupts in Power-Managed Modes ......................246 Various Clock Sources ...............................................32 POR or Wake-up from Sleep ...................................246 Electrical Characteristics ..................................................303 WDT During Oscillator Failure .................................245 Enhanced Capture/Compare/PWM (ECCP) ....................135 Fast Register Stack ...........................................................55 Associated Registers ...............................................148 Firmware Instructions ......................................................249 Capture and Compare Modes ..................................136 Flash Configuration Words ..............................................235 Capture Mode. See Capture (ECCP Module). Flash Program Memory .....................................................71 Outputs and Configuration .......................................136 Associated Registers .................................................79 Pin Configurations for ECCP1 Modes ......................136 Control Registers .......................................................72 PWM Mode. See PWM (ECCP Module). EECON1 and EECON2 .....................................72 Standard PWM Mode ...............................................136 TABLAT (Table Latch) .......................................74 Timer Resources ......................................................136 TBLPTR (Table Pointer) ....................................74 Enhanced PWM Mode. See PWM (ECCP Module). ........137 Erase Sequence ........................................................76 Enhanced Universal Synchronous Asynchronous Erasing ......................................................................76 Receiver Transmitter (EUSART). See EUSART. Operation During Code-Protect .................................79 Equations Reading .....................................................................75 A/D Acquisition Time ................................................220 Table Pointer A/D Minimum Charging Time ...................................220 Boundaries Based on Operation .......................74 Errata ...................................................................................6 Table Pointer Boundaries ..........................................74 EUSART Table Reads and Table Writes ..................................71 Asynchronous Mode ................................................203 Write Sequence .........................................................77 12-Bit Break Transmit and Receive .................208 Writing To ..................................................................77 Associated Registers, Receive ........................206 Protection Against Spurious Writes ...................79 Associated Registers, Transmit .......................204 Unexpected Termination ...................................79 Auto-Wake-up on Sync Break .........................206 Write Verify ........................................................79 Receiver ...........................................................205 FSCM. See Fail-Safe Clock Monitor. Setting Up 9-Bit Mode with G Address Detect ........................................205 Transmitter .......................................................203 GOTO ..............................................................................270 Baud Rate Generator H Operation in Power-Managed Mode ................197 Baud Rate Generator (BRG) ....................................197 Hardware Multiplier ............................................................81 Associated Registers .......................................198 Introduction ................................................................81 Auto-Baud Rate Detect ....................................201 Operation ...................................................................81 Baud Rate Error, Calculating ...........................198 Performance Comparison ..........................................81 Baud Rates, Asynchronous Modes .................199 I High Baud Rate Select (BRGH Bit) .................197 I/O Ports ............................................................................97 Sampling ..........................................................197 I2C Mode (MSSP) Synchronous Master Mode ......................................209 Acknowledge Sequence Timing ..............................185 Associated Registers, Receive ........................211 Associated Registers ...............................................192 Associated Registers, Transmit .......................210 Baud Rate Generator ..............................................178 Reception .........................................................211 Bus Collision Transmission ...................................................209 During a Repeated Start Condition ..................190 Synchronous Slave Mode ........................................212 During a Stop Condition ..................................191 Associated Registers, Receive ........................213 Clock Arbitration ......................................................179 Associated Registers, Transmit .......................212 Clock Stretching ......................................................171 Reception .........................................................213 10-Bit Slave Receive Mode (SEN = 1) ............171 Transmission ...................................................212 10-Bit Slave Transmit Mode ............................171 Extended Instruction Set 7-Bit Slave Receive Mode (SEN = 1) ..............171 ADDFSR ..................................................................292 7-Bit Slave Transmit Mode ..............................171 ADDULNK ................................................................292 Clock Synchronization and the CKP Bit ..................172 and Using MPLAB IDE Tools ...................................298 Effects of a Reset ....................................................186 CALLW .....................................................................293 General Call Address Support .................................175 Considerations for Use ............................................296 I2C Clock Rate w/BRG ............................................178 MOVSF ....................................................................293 Master Mode ............................................................176 MOVSS ....................................................................294 Baud Rate Generator ......................................178 PUSHL .....................................................................294 Operation .........................................................177 SUBFSR ..................................................................295 Reception ........................................................182 SUBULNK ................................................................295 Repeated Start Condition Timing ....................181 Syntax ......................................................................291 Start Condition Timing .....................................180 External Clock Input (EC Modes) .......................................28 Transmission ...................................................182 © 2009 Microchip Technology Inc. DS39682E-page 355

PIC18F45J10 FAMILY Multi-Master Communication, Bus Collision IORLW .....................................................................272 and Arbitration ..................................................186 IORWF .....................................................................272 Multi-Master Mode ...................................................186 LFSR .......................................................................273 Operation .................................................................164 MOVF ......................................................................273 Read/Write Bit Information (R/W Bit) ...............164, 166 MOVFF ....................................................................274 Registers ..................................................................159 MOVLB ....................................................................274 Serial Clock (SCKx/SCLx) .......................................166 MOVLW ...................................................................275 Slave Mode ..............................................................164 MOVWF ...................................................................275 Addressing .......................................................164 MULLW ....................................................................276 Reception .........................................................166 MULWF ....................................................................276 Transmission ....................................................166 NEGF .......................................................................277 Sleep Operation .......................................................186 NOP .........................................................................277 Stop Condition Timing ..............................................185 Opcode Field Descriptions .......................................250 INCF .................................................................................270 POP .........................................................................278 INCFSZ ............................................................................271 PUSH .......................................................................278 In-Circuit Debugger ..........................................................247 RCALL .....................................................................279 In-Circuit Serial Programming (ICSP) ......................235, 247 RESET .....................................................................279 Indexed Literal Offset Addressing RETFIE ....................................................................280 and Standard PIC18 Instructions .............................296 RETLW ....................................................................280 Indexed Literal Offset Mode .............................................296 RETURN ..................................................................281 Indirect Addressing ............................................................67 RLCF .......................................................................281 INFSNZ ............................................................................271 RLNCF .....................................................................282 Initialization Conditions for All Registers ......................47–50 RRCF .......................................................................282 Instruction Cycle .................................................................56 RRNCF ....................................................................283 Clocking Scheme .......................................................56 SETF .......................................................................283 Instruction Flow/Pipelining .................................................56 SETF (Indexed Literal Offset Mode) ........................297 Instruction Set ..................................................................249 SLEEP .....................................................................284 ADDLW ....................................................................255 Standard Instructions ...............................................249 ADDWF ....................................................................255 SUBFWB .................................................................284 ADDWF (Indexed Literal Offset Mode) ....................297 SUBLW ....................................................................285 ADDWFC .................................................................256 SUBWF ....................................................................285 ANDLW ....................................................................256 SUBWFB .................................................................286 ANDWF ....................................................................257 SWAPF ....................................................................286 BC ............................................................................257 TBLRD .....................................................................287 BCF ..........................................................................258 TBLWT ....................................................................288 BN ............................................................................258 TSTFSZ ...................................................................289 BNC .........................................................................259 XORLW ...................................................................289 BNN .........................................................................259 XORWF ...................................................................290 BNOV .......................................................................260 INTCON Registers .............................................................85 BNZ ..........................................................................260 Inter-Integrated Circuit. See I2C Mode. BOV .........................................................................263 Internal Oscillator Block .....................................................30 BRA ..........................................................................261 Internal RC Oscillator BSF ..........................................................................261 Use with WDT ..........................................................242 BSF (Indexed Literal Offset Mode) ..........................297 Internet Address ..............................................................363 BTFSC .....................................................................262 Interrupt Sources .............................................................235 BTFSS .....................................................................262 A/D Conversion Complete .......................................219 BTG ..........................................................................263 Capture Complete (CCP) .........................................129 BZ ............................................................................264 Compare Complete (CCP) .......................................130 CALL ........................................................................264 Interrupt-on-Change (RB7:RB4) ..............................101 CLRF ........................................................................265 INTx Pin .....................................................................95 CLRWDT ..................................................................265 PORTB, Interrupt-on-Change ....................................95 COMF ......................................................................266 TMR0 .........................................................................95 CPFSEQ ..................................................................266 TMR0 Overflow ........................................................117 CPFSGT ..................................................................267 TMR1 Overflow ........................................................119 CPFSLT ...................................................................267 TMR2-to-PR2 Match (PWM) ............................132, 137 DAW .........................................................................268 Interrupts ............................................................................83 DCFSNZ ..................................................................269 Interrupts, Flag Bits DECF .......................................................................268 Interrupt-on-Change (RB7:RB4) DECFSZ ...................................................................269 Flag (RBIF Bit) .................................................101 Extended Instruction Set ..........................................291 INTOSC, INTRC. See Internal Oscillator Block. General Format ........................................................251 IORLW .............................................................................272 GOTO ......................................................................270 IORWF .............................................................................272 INCF .........................................................................270 IPR Registers .....................................................................92 INCFSZ ....................................................................271 INFSNZ ....................................................................271 DS39682E-page 356 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY L P LFSR ................................................................................273 Packaging Information .....................................................337 Details ......................................................................339 M Marking ....................................................................337 Master Clear (MCLR) .........................................................43 Parallel Slave Port (PSP) .........................................107, 113 Master Synchronous Serial Port (MSSP). See MSSP. Associated Registers ...............................................114 Memory Organization .........................................................51 CS (Chip Select) ......................................................113 Data Memory .............................................................58 PORTD ....................................................................113 Program Memory .......................................................51 RD (Read Input) ......................................................113 Memory Programming Requirements ..............................315 Select (PSPMODE Bit) ....................................107, 113 Microchip Internet Web Site .............................................363 WR (Write Input) ......................................................113 MOVF ...............................................................................273 PICSTART Plus Development Programmer ....................302 MOVFF ............................................................................274 PIE Registers .....................................................................90 MOVLB ............................................................................274 Pin Functions MOVLW ...........................................................................275 MCLR ..................................................................12, 16 MOVSF ............................................................................293 OSC1/CLKI ..........................................................12, 16 MOVSS ............................................................................294 OSC2/CLKO ........................................................12, 16 MOVWF ...........................................................................275 RA0/AN0 ..............................................................13, 17 MPLAB ASM30 Assembler, Linker, Librarian ..................300 RA1/AN1 ..............................................................13, 17 MPLAB ICD 2 In-Circuit Debugger ..................................301 RA2/AN2/VREF-/CVREF .......................................13, 17 MPLAB ICE 2000 High-Performance RA3/AN3/VREF+ ..................................................13, 17 Universal In-Circuit Emulator ...................................301 RA5/AN4/SS1/C2OUT .........................................13, 17 MPLAB Integrated Development RB0/INT0/FLT0/AN12 .........................................14, 18 Environment Software ..............................................299 RB1/INT1/AN10 ...................................................14, 18 MPLAB PM3 Device Programmer ...................................301 RB2/INT2/AN8 .....................................................14, 18 MPLAB REAL ICE In-Circuit Emulator System ................301 RB3/AN9/CCP2 ...................................................14, 18 MPLINK Object Linker/MPLIB Object Librarian ...............300 RB4/KBI0/AN11 ...................................................14, 18 MSSP RB5/KBI1/C1OUT ......................................................18 ACK Pulse ........................................................164, 166 RB5/KBI1/T0CKI/C1OUT ..........................................14 Control Registers (general) ......................................149 RB6/KBI2/PGC ....................................................14, 18 I2C Mode. See I2C Mode. RB7/KBI3/PGD ....................................................14, 18 Module Overview .....................................................149 RC0/T1OSO/T1CKI .............................................15, 19 SPI Master/Slave Connection ..................................153 RC1/T1OSI/CCP2 ...............................................15, 19 SSPxBUF Register ..................................................154 RC2/CCP1 .................................................................15 SSPxSR Register .....................................................154 RC2/CCP1/P1A .........................................................19 MULLW ............................................................................276 RC3/SCK1/SCL1 .................................................15, 19 MULWF ............................................................................276 RC4/SDI1/SDA1 ..................................................15, 19 RC5/SDO1 ...........................................................15, 19 N RC6/TX/CK ..........................................................15, 19 NEGF ...............................................................................277 RC7/RX/DT ..........................................................15, 19 NOP .................................................................................277 RD0/PSP0/SCK2/SCL2 .............................................20 Notable Differences Between PIC18F4520 RD1/PSP1/SDI2/SDA2 ..............................................20 and PIC18F45J10 Families ......................................350 RD2/PSP2/SDO2 ......................................................20 Oscillator Options .....................................................351 RD3/PSP3/SS2 .........................................................20 Peripherals ...............................................................351 RD4/PSP4 .................................................................20 Pinouts .....................................................................351 RD5/PSP5/P1B .........................................................20 Power Requirements ...............................................351 RD6/PSP6/P1C .........................................................20 O RD7/PSP7/P1D .........................................................20 RE0/RD/AN5 .............................................................21 Oscillator Configuration ......................................................27 RE1/WR/AN6 .............................................................21 EC ..............................................................................27 RE2/CS/AN7 ..............................................................21 ECPLL ........................................................................27 VDD ......................................................................15, 21 HS ..............................................................................27 VDDCORE/VCAP ....................................................15, 21 HS Modes ..................................................................27 VSS ......................................................................15, 21 HSPLL ........................................................................27 Pinout I/O Descriptions Internal Oscillator Block .............................................30 PIC18F24J10/25J10 ..................................................12 INTRC ........................................................................27 PIC18F44J10/45J10 ..................................................16 Oscillator Selection ..........................................................235 PIR Registers .....................................................................88 Oscillator Start-up Timer (OST) .........................................33 PLL Frequency Multiplier ...................................................29 Oscillator Switching ............................................................30 ECPLL Oscillator Mode .............................................29 Oscillator Transitions .........................................................31 HSPLL Oscillator Mode .............................................29 Oscillator, Timer1 .............................................................119 POP .................................................................................278 POR. See Power-on Reset. © 2009 Microchip Technology Inc. DS39682E-page 357

PIC18F45J10 FAMILY PORTA Program Memory Associated Registers ...............................................100 and Extended Instruction Set ....................................70 LATA Register ............................................................98 Flash Configuration Words ........................................52 PORTA Register ........................................................98 Instructions ................................................................57 TRISA Register ..........................................................98 Two-Word ..........................................................57 PORTB Interrupt Vector ....................................................51, 52 Associated Registers ...............................................103 Look-up Tables ..........................................................55 LATB Register ..........................................................101 Map and Stack (diagram) ..........................................51 PORTB Register ......................................................101 Memory Maps RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........101 Hard Vectors and Configuration Words .............52 TRISB Register ........................................................101 Reset Vector ........................................................51, 52 PORTC Program Verification and Code Protection ......................247 Associated Registers ...............................................106 Programming, Device Instructions ...................................249 LATC Register .........................................................104 PSP. See Parallel Slave Port. PORTC Register ......................................................104 Pulse-Width Modulation. See PWM (CCP Module) RC3/SCK1/SCL1 Pin ...............................................166 and PWM (ECCP Module). TRISC Register ........................................................104 PUSH ...............................................................................278 PORTD PUSH and POP Instructions ..............................................54 Associated Registers ...............................................109 PUSHL .............................................................................294 LATD Register .........................................................107 PWM (CCP Module) Parallel Slave Port (PSP) Function ..........................107 Associated Registers ...............................................134 PORTD Register ......................................................107 Auto-Shutdown (CCP1 Only) ...................................133 TRISD Register ........................................................107 CCPR1H:CCPR1L Registers ...................................137 PORTE Duty Cycle .......................................................132, 138 Associated Registers ...............................................112 Example Frequencies/Resolutions ..................133, 138 LATE Register ..........................................................110 Period ..............................................................132, 137 PORTE Register ......................................................110 Setup for Operation .................................................133 PSP Mode Select (PSPMODE Bit) ..........................107 TMR2-to-PR2 Match ........................................132, 137 TRISE Register ........................................................110 PWM (ECCP Module) ......................................................137 Power-Managed Modes .....................................................35 Direction Change in Full-Bridge Output Mode .........142 and EUSART Operation ...........................................197 Effects of a Reset ....................................................147 and Multiple Sleep Commands ..................................36 Enhanced PWM Auto-Shutdown .............................144 and PWM Operation ................................................147 Full-Bridge Application Example ..............................142 and SPI Operation ...................................................157 Full-Bridge Mode .....................................................141 Clock Transitions and Status Indicators .....................36 Half-Bridge Mode .....................................................140 Entering ......................................................................35 Half-Bridge Output Mode Applications Example ......140 Exiting Idle and Sleep Modes ....................................40 Operation in Power-Managed Modes ......................147 by Reset .............................................................40 Operation with Fail-Safe Clock Monitor ...................147 by WDT Time-out ...............................................40 Output Configurations ..............................................138 Without an Oscillator Start-up Delay ..................40 Output Relationships (Active-High) ..........................139 Idle Modes .................................................................38 Output Relationships (Active-Low) ..........................139 PRI_IDLE ...........................................................39 Programmable Dead-Band Delay ............................144 RC_IDLE ............................................................40 Setup for PWM Operation ........................................147 SEC_IDLE ..........................................................39 Start-up Considerations ...........................................146 Run Modes .................................................................36 Q PRI_RUN ...........................................................36 RC_RUN ............................................................37 Q Clock ....................................................................133, 138 SEC_RUN ..........................................................36 R Selecting ....................................................................35 Sleep Mode ................................................................38 RAM. See Data Memory. Summary (table) ........................................................35 RBIF Bit ...........................................................................101 Power-on Reset (POR) ......................................................43 RC_IDLE Mode ..................................................................40 Power-up Timer (PWRT) ...........................................44 RC_RUN Mode ..................................................................37 Time-out Sequence ....................................................44 RCALL .............................................................................279 Power-up Delays ................................................................33 RCON Register Power-up Timer (PWRT) ..............................................33, 44 Bit Status During Initialization ....................................46 Prescaler Reader Response ............................................................364 Timer2 ......................................................................138 Register File .......................................................................60 Prescaler, Timer0 .............................................................117 Register File Summary ................................................62–64 Prescaler, Timer2 .............................................................133 Registers PRI_IDLE Mode .................................................................39 ADCON0 (A/D Control 0) .........................................215 PRI_RUN Mode .................................................................36 ADCON1 (A/D Control 1) .........................................216 Program Counter ................................................................53 ADCON2 (A/D Control 2) .........................................217 PCL, PCH and PCU Registers ...................................53 BAUDCON (Baud Rate Control) ..............................196 PCLATH and PCLATU Registers ..............................53 CCP1CON (ECCP1 Control) ...................................135 CCPxCON (CCPx Control) ......................................127 DS39682E-page 358 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY CMCON (Comparator Control) ................................225 Return Stack Pointer (STKPTR) ........................................54 CONFIG1H (Configuration 1 High) ..........................237 Revision History ...............................................................349 CONFIG1L (Configuration 1 Low) ............................237 RLCF ...............................................................................281 CONFIG2H (Configuration 2 High) ..........................239 RLNCF .............................................................................282 CONFIG2L (Configuration 2 Low) ............................238 RRCF ...............................................................................282 CONFIG3H (Configuration 3 High) ..........................240 RRNCF ............................................................................283 CONFIG3L (Configuration 3 Low) ............................240 S CVRCON (Comparator Voltage Reference Control) ..........................................231 SCKx ...............................................................................149 DEVID1 (Device ID Register 1) ................................241 SDIx .................................................................................149 DEVID2 (Device ID Register 2) ................................241 SDOx ...............................................................................149 ECCP1DEL (PWM Dead-Band Delay) ....................144 SEC_IDLE Mode ...............................................................39 EECON1 (EEPROM Control 1) ..................................73 SEC_RUN Mode ................................................................36 EUSART Receive Status and Control ......................195 Serial Clock, SCKx ..........................................................149 INTCON (Interrupt Control) ........................................85 Serial Data In (SDIx) ........................................................149 INTCON2 (Interrupt Control 2) ...................................86 Serial Data Out (SDOx) ...................................................149 INTCON3 (Interrupt Control 3) ...................................87 Serial Peripheral Interface. See SPI Mode. IPR1 (Peripheral Interrupt Priority 1) ..........................92 SETF ...............................................................................283 IPR2 (Peripheral Interrupt Priority 2) ..........................93 Slave Select (SSx) ...........................................................149 IPR3 (Peripheral Interrupt Priority 3) ..........................93 SLEEP .............................................................................284 OSCCON (Oscillator Control) ....................................32 Sleep OSCTUNE (PLL Control) ...........................................29 OSC1 and OSC2 Pin States ......................................33 PIE1 (Peripheral Interrupt Enable 1) ..........................90 Software Simulator (MPLAB SIM) ...................................300 PIE2 (Peripheral Interrupt Enable 2) ..........................91 Special Event Trigger. See Compare (ECCP Module). PIE3 (Peripheral Interrupt Enable 3) ..........................91 Special Event Trigger. See Compare (ECCP/CCP Modules). PIR1 (Peripheral Interrupt Request (Flag) 1) .............88 Special Features of the CPU ...........................................235 PIR2 (Peripheral Interrupt Request (Flag) 2) .............89 Special Function Registers ................................................61 PIR3 (Peripheral Interrupt Request (Flag) 3) .............89 Map ............................................................................61 RCON (Reset Control) .........................................42, 94 SPI Mode (MSSP) SSPxCON1 (MSSPx Control 1, I2C Mode) ..............161 Associated Registers ...............................................158 SSPxCON1 (MSSPx Control 1, SPI Mode) .............151 Bus Mode Compatibility ...........................................157 SSPxCON2 (MSSPx Control 2, Clock Speed and Module Interactions .....................157 I2C Master Mode) ............................................162 Effects of a Reset ....................................................157 SSPxCON2 (MSSPx Control 2, Enabling SPI I/O ......................................................153 I2C Slave Mode) ..............................................163 Master Mode ............................................................154 SSPxSTAT (MSSPx Status, I2C Mode) ...................160 Master/Slave Connection ........................................153 SSPxSTAT (MSSPx Status, SPI Mode) ..................150 Operation .................................................................152 STATUS .....................................................................65 Operation in Power-Managed Modes ......................157 STKPTR (Stack Pointer) ............................................54 Serial Clock .............................................................149 T0CON (Timer0 Control) ..........................................115 Serial Data In ...........................................................149 T1CON (Timer1 Control) ..........................................119 Serial Data Out ........................................................149 T2CON (Timer2 Control) ..........................................125 Slave Mode ..............................................................155 TRISE (PORTE/PSP Control) ..................................111 Slave Select .............................................................149 TXSTA (EUSART Transmit Status Slave Select Synchronization ..................................155 and Control) .....................................................194 SPI Clock .................................................................154 WDTCON (Watchdog Timer Control) ......................242 Typical Connection ..................................................153 RESET .............................................................................279 SSPOV ............................................................................182 Reset SSPOV Status Flag .........................................................182 Brown-out Reset (BOR) .............................................41 SSPxSTAT Register Configuration Mismatch (CM) ....................................41 R/W Bit ............................................................164, 166 MCLR Reset, During Power-Managed Modes ...........41 SSx ..................................................................................149 MCLR Reset, Normal Operation ................................41 Stack Full/Underflow Resets ..............................................55 Power-on Reset (POR) ..............................................41 STATUS Register ..............................................................65 RESET Instruction .....................................................41 SUBFSR ..........................................................................295 Stack Full Reset .........................................................41 SUBFWB .........................................................................284 Stack Underflow Reset ..............................................41 SUBLW ............................................................................285 Watchdog Timer (WDT) Reset ...................................41 SUBULNK ........................................................................295 Resets ..............................................................................235 SUBWF ............................................................................285 Brown-out Reset (BOR) ...........................................235 SUBWFB .........................................................................286 Oscillator Start-up Timer (OST) ...............................235 SWAPF ............................................................................286 Power-on Reset (POR) ............................................235 T Power-up Timer (PWRT) .........................................235 RETFIE ............................................................................280 Table Pointer Operations (table) ........................................74 RETLW ............................................................................280 Table Reads/Table Writes .................................................55 RETURN ..........................................................................281 TBLRD .............................................................................287 Return Address Stack ........................................................53 TBLWT ............................................................................288 © 2009 Microchip Technology Inc. DS39682E-page 359

PIC18F45J10 FAMILY Timer0 ..............................................................................115 CLKO and I/O ..........................................................321 Associated Registers ...............................................117 Clock Synchronization .............................................172 Clock Source Select (T0CS Bit) ...............................116 Clock/Instruction Cycle ..............................................56 Operation .................................................................116 EUSART Synchronous Receive (Master/Slave) ......333 Overflow Interrupt ....................................................117 EUSART Synchronous Transmission Prescaler ..................................................................117 (Master/Slave) .................................................333 Prescaler Assignment (PSA Bit) ..............................117 Example SPI Master Mode (CKE = 0) .....................325 Prescaler Select (T0PS2:T0PS0 Bits) .....................117 Example SPI Master Mode (CKE = 1) .....................326 Prescaler. See Prescaler, Timer0. Example SPI Slave Mode (CKE = 0) .......................327 Reads and Writes in 16-Bit Mode ............................116 Example SPI Slave Mode (CKE = 1) .......................328 Source Edge Select (T0SE Bit) ................................116 External Clock (All Modes Except PLL) ...................319 Switching Prescaler Assignment ..............................117 Fail-Safe Clock Monitor ...........................................246 Timer1 ..............................................................................119 First Start Bit Timing ................................................180 16-Bit Read/Write Mode ...........................................121 Full-Bridge PWM Output ..........................................141 Associated Registers ...............................................124 Half-Bridge PWM Output .........................................140 Interrupt ....................................................................122 I2C Bus Data ............................................................329 Operation .................................................................120 I2C Bus Start/Stop Bits ............................................329 Oscillator ..........................................................119, 121 I2C Master Mode (7 or 10-Bit Transmission) ...........183 Layout Considerations .....................................122 I2C Master Mode (7-Bit Reception) ..........................184 Oscillator, as Secondary Clock ..................................30 I2C Slave Mode (10-Bit Reception, SEN = 0) ..........169 Overflow Interrupt ....................................................119 I2C Slave Mode (10-Bit Reception, SEN = 1) ..........174 Resetting, Using the ECCP/CCP I2C Slave Mode (10-Bit Transmission) ....................170 Special Event Trigger .......................................123 I2C Slave Mode (7-Bit Reception, SEN = 0) ............167 Special Event Trigger (ECCP) .................................136 I2C Slave Mode (7-Bit Reception, SEN = 1) ............173 TMR1H Register ......................................................119 I2C Slave Mode (7-Bit Transmission) ......................168 TMR1L Register .......................................................119 I2C Slave Mode General Call Address Use as a Clock Source ............................................122 Sequence (7 or 10-Bit Address Mode) ............175 Use as a Real-Time Clock .......................................123 I2C Stop Condition Receive or Transmit Mode ........186 Timer2 ..............................................................................125 Master SSP I2C Bus Data ........................................331 Associated Registers ...............................................126 Master SSP I2C Bus Start/Stop Bits ........................331 Interrupt ....................................................................126 Parallel Slave Port (PSP) Read ...............................114 Operation .................................................................125 Parallel Slave Port (PSP) Write ...............................114 Output ......................................................................126 PWM Auto-Shutdown (PRSEN = 0, PR2 Register ....................................................132, 137 Auto-Restart Disabled) ....................................146 TMR2-to-PR2 Match Interrupt ..........................132, 137 PWM Auto-Shutdown (PRSEN = 1, Timing Diagrams Auto-Restart Enabled) .....................................146 A/D Conversion ........................................................334 PWM Direction Change ...........................................143 Acknowledge Sequence ..........................................185 PWM Direction Change at Near Asynchronous Reception .........................................206 100% Duty Cycle .............................................143 Asynchronous Transmission ....................................204 PWM Output ............................................................132 Asynchronous Transmission (Back to Back) ...........204 Repeated Start Condition ........................................181 Automatic Baud Rate Calculation ............................202 Reset, Watchdog Timer (WDT), Oscillator Start-up Auto-Wake-up Bit (WUE) During Timer (OST) and Power-up Timer (PWRT) .....322 Normal Operation .............................................207 Send Break Character Sequence ............................208 Auto-Wake-up Bit (WUE) During Sleep ...................207 Slave Synchronization .............................................155 Baud Rate Generator with Clock Arbitration ............179 Slow Rise Time (MCLR Tied to VDD, BRG Overflow Sequence .........................................202 VDD Rise > TPWRT) ............................................45 BRG Reset Due to SDAx Arbitration During SPI Mode (Master Mode) .........................................154 Start Condition .................................................189 SPI Mode (Slave Mode, CKE = 0) ...........................156 Brown-out Reset (BOR) ...........................................322 SPI Mode (Slave Mode, CKE = 1) ...........................156 Bus Collision During a Repeated Synchronous Reception Start Condition (Case 1) ..................................190 (Master Mode, SREN) .....................................211 Bus Collision During a Repeated Synchronous Transmission .....................................209 Start Condition (Case 2) ..................................190 Synchronous Transmission (Through TXEN) ..........210 Bus Collision During a Time-out Sequence on Power-up Start Condition (SCLx = 0) ...............................189 (MCLR Not Tied to VDD), Case 1 ......................45 Bus Collision During a Time-out Sequence on Power-up Stop Condition (Case 1) ...................................191 (MCLR Not Tied to VDD), Case 2 ......................45 Bus Collision During a Time-out Sequence on Power-up Stop Condition (Case 2) ...................................191 (MCLR Tied to VDD, VDD Rise /Tpwrt) ...............44 Bus Collision During Timer0 and Timer1 External Clock ..........................323 Start Condition (SDAx Only) ............................188 Transition for Entry to Idle Mode ................................39 Bus Collision for Transmit and Acknowledge ...........187 Transition for Entry to SEC_RUN Mode ....................36 Capture/Compare/PWM Transition for Entry to Sleep Mode ............................38 (Including ECCP Module) ................................324 Transition for Two-Speed Start-up (INTRC) ............244 DS39682E-page 360 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY Transition for Wake From Idle to Run Mode ..............39 V Transition for Wake From Sleep ................................38 Voltage Reference Specifications ....................................316 Transition From RC_RUN Mode to Voltage Regulator (On-Chip) ...........................................243 PRI_RUN Mode .................................................37 Transition to RC_RUN Mode .....................................37 W Timing Diagrams and Specifications Watchdog Timer (WDT) ...........................................235, 242 A/D Conversion Requirements ................................335 Associated Registers ...............................................242 AC Characteristics Control Register .......................................................242 Internal RC Accuracy .......................................320 During Oscillator Failure ..........................................245 Capture/Compare/PWM Requirements Programming Considerations ..................................242 (Including ECCP Module) ................................324 WCOL ......................................................180, 181, 182, 185 CLKO and I/O Requirements ...................................321 WCOL Status Flag ...................................180, 181, 182, 185 EUSART Synchronous Receive WWW Address ................................................................363 Requirements ..................................................333 WWW, On-Line Support ......................................................6 EUSART Synchronous Transmission Requirements ..................................................333 X Example SPI Mode Requirements XORLW ...........................................................................289 (CKE = 0) .................................................325, 327 XORWF ...........................................................................290 Example SPI Mode Requirements (CKE = 1) .........................................................326 Example SPI Slave Mode Requirements (CKE = 1) 328 External Clock Requirements ..................................319 I2C Bus Data Requirements (Slave Mode) ..............330 I2C Bus Start/Stop Bits Requirements (Slave Mode) ...................................................329 Master SSP I2C Bus Data Requirements ................332 Master SSP I2C Bus Start/Stop Bits Requirements ..................................................331 Parallel Slave Port Requirements ............................324 PLL Clock .................................................................320 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ........................................322 Timer0 and Timer1 External Clock Requirements ..................................................323 Top-of-Stack Access ..........................................................53 TRISE Register PSPMODE Bit ..........................................................107 TSTFSZ ...........................................................................289 Two-Speed Start-up .................................................235, 244 Two-Word Instructions Example Cases ..........................................................57 TXSTA Register BRGH Bit .................................................................197 © 2009 Microchip Technology Inc. DS39682E-page 361

PIC18F45J10 FAMILY NOTES: DS39682E-page 362 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2009 Microchip Technology Inc. DS39682E-page 363

PIC18F45J10 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC18F45J10 Family Literature Number: DS39682E Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39682E-page 364 © 2009 Microchip Technology Inc.

PIC18F45J10 FAMILY PIC18F45J10 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC18LF45J10-I/P 301 = Industrial temp., Range PDIP package, QTP pattern #301. b) PIC18LF24J10-I/SO = Industrial temp., SOIC package. c) PIC18LF44J10-I/P = Industrial temp., PDIP Device PIC18F24J10/25J10, PIC18F44J10/45J10, PIC18F24J10/25J10T(1), PIC18F44J10/45J10T(1); package. VDD range 2.7V to 3.6V PIC18LF24J10/25J10, PIC18LF44J10/45J10, PIC18LF24J10/25J10T(1), PIC18LF44J10/45J10T(1); VDDCORE range 2.0V to 2.7V Temperature Range I = -40°C to +85°C (Industrial) Package PT = TQFP (Thin Quad Flatpack) SO = SOIC SP = Skinny Plastic DIP Note1: T = in tape and reel TQFP P = PDIP packages only. ML = QFN SS = SSOP Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) © 2009 Microchip Technology Inc. DS39682E-page 365

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC18F24J10-I/ML PIC18F24J10-I/SO PIC18F24J10-I/SP PIC18F24J10-I/SS PIC18F24J10T-I/ML PIC18F24J10T- I/SO PIC18F24J10T-I/SS PIC18F25J10-I/ML PIC18F25J10-I/SO PIC18F25J10-I/SP PIC18F25J10-I/SS PIC18F25J10T-I/ML PIC18F25J10T-I/SO PIC18F25J10T-I/SS PIC18F44J10-I/ML PIC18F44J10-I/P PIC18F44J10- I/PT PIC18F44J10T-I/ML PIC18F44J10T-I/PT PIC18F45J10-E/ML PIC18F45J10-E/P PIC18F45J10-E/PT PIC18F45J10-I/ML PIC18F45J10-I/P PIC18F45J10-I/PT PIC18F45J10T-E/PT PIC18F45J10T-I/ML PIC18F45J10T- I/PT PIC18LF24J10-I/ML PIC18LF24J10-I/SO PIC18LF24J10-I/SP PIC18LF24J10-I/SS PIC18LF24J10T-I/ML PIC18LF24J10T-I/SO PIC18LF24J10T-I/SS PIC18LF25J10-I/ML PIC18LF25J10-I/SO PIC18LF25J10-I/SP PIC18LF25J10-I/SS PIC18LF25J10T-I/ML PIC18LF25J10T-I/SO PIC18LF25J10T-I/SS PIC18LF44J10-I/ML PIC18LF44J10-I/P PIC18LF44J10-I/PT PIC18LF44J10T-I/ML PIC18LF44J10T-I/PT PIC18LF45J10-I/ML PIC18LF45J10-I/P PIC18LF45J10-I/PT PIC18LF45J10T-I/ML PIC18LF45J10T-I/PT