INTEGRATED CIRCUITS 87LPC762 Low power, low price, low pin count (20 pin) microcontroller with 2 kbyte OTP Preliminary data 2001 Oct 26 Supersedes data of 2001 Apr 04 IC28 Data Handbook (cid:0)(cid:5)(cid:6)(cid:7)(cid:6)(cid:11)(cid:13) (cid:1)(cid:4)(cid:8)(cid:6)(cid:2)(cid:10)(cid:9)(cid:3)(cid:15)(cid:2)(cid:14)(cid:10)(cid:12)(cid:13)

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PIN CONFIGURATION, 20-PIN DIP, SO, AND TSSOP PACKAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 LOGIC SYMBOL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SPECIAL FUNCTION REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Analog Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Analog Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Comparator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Internal Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Comparator Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Comparators and Power Reduction Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Comparator Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 I2C Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2C Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Reading I2CON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Checking ATN and DRDY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Writing I2CON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Regarding Transmit Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Regarding Software Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 External Interrupt Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 I/O Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Quasi-Bidirectional Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Open Drain Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Push-Pull Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Keyboard Interrupt (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Low Frequency Oscillator Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Medium Frequency Oscillator Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 High Frequency Oscillator Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 On-Chip RC Oscillator Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 External Clock Input Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 CPU Clock Modification: CLKR and DIVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power Monitoring Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Brownout Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power On Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power Reduction Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Low Voltage EPROM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Timer/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Timer Overflow Toggle Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2001 Oct 26 i

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Serial Port Control Register (SCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Using Timer 1 to Generate Baud Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 More About UART Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 More About UART Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 More About UART Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Multiprocessor Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Automatic Address Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Watchdog Feed Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Additional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Dual Data Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 EPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 32-Byte Customer Code Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 System Configuration Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Security Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 COMPARATOR ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2001 Oct 26 ii

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP • Eight keypad interrupt inputs, plus two additional external interrupt inputs. • Four interrupt priority levels. • Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog timeout time is selectable from 8 values. • Active low reset. On-chip power-on reset allows operation with no external reset components. • Low voltage reset. One of two preset low voltage levels may be GENERAL DESCRIPTION selected to allow a graceful system shutdown when power fails. The 87LPC762 is a 20-pin single-chip microcontroller designed for May optionally be configured as an interrupt. low pin count applications demanding high-integration, low cost • solutions over a wide range of performance requirements. A Oscillator Fail Detect. The watchdog timer has a separate fully member of the Philips low pin count family, the 87LPC762 offers on-chip oscillator, allowing it to perform an oscillator fail detect programmable oscillator configurations for high and low speed function. crystals or RC operation, wide operating voltage range, • Configurable on-chip oscillator with frequency range and RC programmable port output configurations, selectable Schmitt trigger oscillator options (selected by user programmed EPROM bits). inputs, LED drive outputs, and a built-in watchdog timer. The The RC oscillator option allows operation with no external 87LPC762 is based on an accelerated 80C51 processor oscillator components. architecture that executes instructions at twice the rate of standard • 80C51 devices. Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only. • Selectable Schmitt trigger port inputs. FEATURES • • LED drive capability (20 mA) on all port pins. An accelerated 80C51 CPU provides instruction cycle times of • 300–600ns for all instructions except multiply and divide when Controlled slew rate port outputs to reduce EMI. Outputs have executing at 20 MHz. Execution at up to 20 MHz when approximately 10 ns minimum ramp times. VDD = 4.5 V to 6.0 V, 10 MHz when VDD = 2.7 V to 6.0 V. • • 15 I/O pins minimum. Up to 18 I/O pins using on-chip oscillator 2.7 V to 6.0 V operating range for digital functions. and reset options. • • 2 kbytes EPROM code memory. Only power and ground connections are required to operate the •128 byte RAM data memory. 87LPC762 when fully on-chip oscillator and reset options are • selected. 32-byte customer code EPROM allows serialization of devices, • Serial EPROM programming allows simple in-circuit production storage of setup parameters, etc. • coding. Two EPROM security bits prevent reading of sensitive Two 16-bit counter/timers. Each timer may be configured to toggle application programs. a port output upon timer overflow. • Idle and Power Down reduced power modes. Improved wakeup • Two analog comparators. from Power Down mode (a low interrupt input starts execution). • Typical Power Down current is 1 m A. Full duplex UART. • • 20-pin DIP, SO, and TSSOP packages. I2C communication port. ORDERING INFORMATION Part Number Temperature Range °C and Package Frequency Drawing Number P87LPC762BN 0 to +70, Plastic Dual In-Line Package 20 MHz (5 V), 10 MHz (3 V) SOT146–1 P87LPC762BD 0 to +70, Plastic Small Outline Package 20 MHz (5 V), 10 MHz (3 V) SOT163–1 P87LPC762FN –45 to +85, Plastic Dual In-Line Package 20 MHz (5 V), 10 MHz (3 V) SOT146–1 P87LPC762FD –45 to +85, Plastic Small Outline Package 20 MHz (5 V), 10 MHz (3 V) SOT163–1 P87LPC762BDH 0 to +70, Plastic Thin Small Outline Package 20 MHz (5 V), 10 MHz (3 V) SOT360–1 2001 Oct 26 1

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP PIN CONFIGURATION, 20-PIN DIP, SO, AND TSSOP PACKAGES CMP2/P0.0 1 20 P0.1/CIN2B P1.7 2 19 P0.2/CIN2A P1.6 3 18 P0.3/CIN1B RST/P1.5 4 17 P0.4/CIN1A VSS 5 16 P0.5/CMPREF X1/P2.1 6 15 VDD X2/CLKOUT/P2.0 7 14 P0.6/CMP1 INT1/P1.4 8 13 P0.7/T1 SDA/INT0/P1.3 9 12 P1.0/TxD SCL/T0/P1.2 10 11 P1.1/RxD SU01149 LOGIC SYMBOL VDD VSS CMP2 TxD CIN2B RxD CIN2A T0 SCL CIN1B T 0 T 1 INT0 SDA CIN1A OR OR INT1 P P CMPREF RST CMP1 T1 CLKOUT/X2 2 T R O X1 P SU01150 2001 Oct 26 2

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP BLOCK DIAGRAM ACCELERATED 80C51 CPU INTERNAL BUS UART 2 K BYTE CODE EPROM I2C 128 BYTE DATA RAM TIMER 0, 1 PORT 2 CONFIGURABLE I/OS PORT 1 WATCHDOG TIMER CONFIGURABLE I/OS AND OSCILLATOR PORT 0 CONFIGURABLE I/OS ANALOG COMPARATORS KEYPAD INTERRUPT POWER MONITOR (POWER-ON RESET, BROWNOUT RESET) ON-CHIP CRYSTAL OR CONFIGURABLE RC RESONATOR OSCILLATOR OSCILLATOR SU01577 2001 Oct 26 3

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP FFFFh FFFFh UNUSED SPACE UNUSED CODE FD01h MEMORY SPACE CONFIGURATION BYTES UCFG1, UCFG2 (ACCESSIBLE VIA MOVX) FCFFh FD00h 32-BYTE CUSTOMER CODE SPACE (ACCESSIBLE VIA MOVC) FCE0h FFh SPECIAL FUNCTION UNUSED CODE REGISTERS MEMORY SPACE (ONLY DIRECTLY ADDRESSABLE) UNUSED SPACE 0800h 80h 07FFh 128 BYTES ON-CHIP DATA 7Fh MEMORY (DIRECTLY AND 2 K BYTES ON-CHIP INDIRECTLY CODE MEMORY ADDRESSABLE) 16-BIT ADDRESSABLE BYTES INTERRUPT VECTORS 0000h 00h 0000h ON-CHIP CODE ON-CHIP DATA EXTERNAL DATA MEMORY SPACE MEMORY SPACE MEMORY SPACE* * The 87LPC762 does not support access to external data memory. However, the User Configuration Bytes are accessed via the MOVX instruction as if they were in external data memory. su01221 Figure 1. 87LPC762 Program and Data Memory Map 2001 Oct 26 4

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP PIN DESCRIPTIONS MNEMONIC PIN NO. TYPE NAME AND FUNCTION P0.0–P0.7 1, 13, 14, I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. Port 0 latches are configured in 16–20 the quasi-bidirectional mode and have either ones or zeros written to them during reset, as determined by the PRHI bit in the UCFG1 configuration byte. The operation of port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. The Keyboard Interrupt feature operates with port 0 pins. Port 0 also provides various special functions as described below. 1 O P0.0 CMP2 Comparator 2 output. 20 I P0.1 CIN2B Comparator 2 positive input B. 19 I P0.2 CIN2A Comparator 2 positive input A. 18 I P0.3 CIN1B Comparator 1 positive input B. 17 I P0.4 CIN1A Comparator 1 positive input A. 16 I P0.5 CMPREF Comparator reference (negative) input. 14 O P0.6 CMP1 Comparator 1 output. 13 I/O P0.7 T1 Timer/counter 1 external count input or overflow output. P1.0–P1.7 2–4, 8–12 I/O Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for three pins as noted below. Port 1 latches are configured in the quasi-bidirectional mode and have either ones or zeros written to them during reset, as determined by the PRHI bit in the UCFG1 configuration byte. The operation of the configurable port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. Port 1 also provides various special functions as described below. 12 O P1.0 TxD Transmitter output for the serial port. 11 I P1.1 RxD Receiver input for the serial port. 10 I/O P1.2 T0 Timer/counter 0 external count input or overflow output. I/O SCL I2C serial clock input/output. When configured as an output, P1.2 is open drain, in order to conform to I2C specifications. 9 I P1.3 INT0 External interrupt 0 input. I/O SDA I2C serial data input/output. When configured as an output, P1.3 is open drain, in order to conform to I2C specifications. 8 I P1.4 INT1 External interrupt 1 input. 4 I P1.5 RST External Reset input (if selected via EPROM configuration). A low on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. When used as a port pin, P1.5 is a Schmitt trigger input only. P2.0–P2.1 6, 7 I/O Port 2: Port 2 is a 2-bit I/O port with a user-configurable output type. Port 2 latches are configured in the quasi-bidirectional mode and have either ones or zeros written to them during reset, as determined by the PRHI bit in the UCFG1 configuration byte. The operation of port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. Port 2 also provides various special functions as described below. 7 O P2.0 X2 Output from the oscillator amplifier (when a crystal oscillator option is selected via the EPROM configuration). CLKOUT CPU clock divided by 6 clock output when enabled via SFR bit and in conjunction with internal RC oscillator or external clock input. 6 I P2.1 X1 Input to the oscillator circuit and internal clock generator circuits (when selected via the EPROM configuration). VSS 5 I Ground: 0V reference. VDD 15 I Power Supply: This is the power supply voltage for normal operation as well as Idle and Power Down modes. 2001 Oct 26 5

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP SPECIAL FUNCTION REGISTERS SFR Bit Functions and Addresses Reset Name Description Address MSB LSB Value E7 E6 E5 E4 E3 E2 E1 E0 ACC* Accumulator E0h 00h Auxiliary Function AUXR1# A2h KBF BOD BOI LPEP SRST 0 – DPS 02h1 Register F7 F6 F5 F4 F3 F2 F1 F0 B* B register F0h 00h Comparator 1 control CMP1# ACh – – CE1 CP1 CN1 OE1 CO1 CMF1 00h1 register Comparator 2 control CMP2# ADh – – CE2 CP2 CN2 OE2 CO2 CMF2 00h1 register CPU clock divide-by-M DIVM# 95h 00h control DPTR: Data pointer (2 bytes) DPH Data pointer high byte 83h 00h DPL Data pointer low byte 82h 00h CF CE CD CC CB CA C9 C8 I2CFG#* I2C configuration register C8h/RD SLAVEN MASTRQ 0 TIRUN – – CT1 CT0 00h1 C8h/WR SLAVEN MASTRQ CLRTI TIRUN – – CT1 CT0 DF DE DD DC DB DA D9 D8 I2CON#* I2C control register D8h/RD RDAT ATN DRDY ARL STR STP MASTER – 80h1 D8h/WR CXA IDLE CDR CARL CSTR CSTP XSTR XSTP I2DAT# I2C data register D9h/RD RDAT 0 0 0 0 0 0 0 80h D9h/WR XDAT x x x x x x x AF AE AD AC AB AA A9 A8 IEN0* Interrupt enable 0 A8h EA EWD EBO ES ET1 EX1 ET0 EX0 00h EF EE ED EC EB EA E9 E8 IEN1#* Interrupt enable 1 E8h ETI – EC1 – – EC2 EKB EI2 00h1 BF BE BD BC BB BA B9 B8 IP0* Interrupt priority 0 B8h – PWD PBO PS PT1 PX1 PT0 PX0 00h1 Interrupt priority 0 high IP0H# B7h – PWDH PBOH PSH PT1H PX1H PT0H PX0H 00h1 byte FF FE FD FC FB FA F9 F8 IP1* Interrupt priority 1 F8h PTI – PC1 – – PC2 PKB PI2 00h1 2001 Oct 26 6

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP SFR Bit Functions and Addresses Reset Name Description Address MSB LSB Value Interrupt priority 1 high IP1H# F7h PTIH – PC1H – – PC2H PKBH PI2H 00h1 byte KBI# Keyboard Interrupt 86h 00h 87 86 85 84 83 82 81 80 P0* Port 0 80h T1 CMP1 CMPREF CIN1A CIN1B CIN2A CIN2B CMP2 Note 2 97 96 95 94 93 92 91 90 P1* Port 1 90h (P1.7) (P1.6) RST INT1 INT0 T0 RxD TxD Note 2 A7 A6 A5 A4 A3 A2 A1 A0 P2* Port 2 A0h – – – – – – X1 X2 Note 2 P0M1# Port 0 output mode 1 84h (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) 00h P0M2# Port 0 output mode 2 85h (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00H P1M1# Port 1 output mode 1 91h (P1M1.7) (P1M1.6) – (P1M1.4) – – (P1M1.1) (P1M1.0) 00h1 P1M2# Port 1 output mode 2 92h (P1M2.7) (P1M2.6) – (P1M2.4) – – (P1M2.1) (P1M2.0) 00h1 P2M1# Port 2 output mode 1 A4h P2S P1S P0S ENCLK T1OE T0OE (P2M1.1) (P2M1.0) 00h P2M2# Port 2 output mode 2 A5h – – – – – – (P2M2.1) (P2M2.0) 00h1 PCON Power control register 87h SMOD1 SMOD0 BOF POF GF1 GF0 PD IDL Note 3 D7 D6 D5 D4 D3 D2 D1 D0 PSW* Program status word D0h CY AC F0 RS1 RS0 OV F1 P 00h PT0AD# Port 0 digital input disable F6h 00h 9F 9E 9D 9C 9B 9A 99 98 SCON* Serial port control 98h SM0 SM1 SM2 REN TB8 RB8 TI RI 00h Serial port data buffer SBUF 99h xxh register Serial port address SADDR# A9h 00h register SADEN# Serial port address enable B9h 00h SP Stack pointer 81h 07h 8F 8E 8D 8C 8B 8A 89 88 TCON* Timer 0 and 1 control 88h TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00h TH0 Timer 0 high byte 8Ch 00h TH1 Timer 1 high byte 8Dh 00h TL0 Timer 0 low byte 8Ah 00h 2001 Oct 26 7

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP SFR Bit Functions and Addresses Reset Name Description Address MSB LSB Value TL1 Timer 1 low byte 8Bh 00h TMOD Timer 0 and 1 mode 89h GATE C/T M1 M0 GATE C/T M1 M0 00h WDCON# Watchdog control register A7h – – WDOVF WDRUN WDCLK WDS2 WDS1 WDS0 Note 4 WDRST# Watchdog reset register A6h xxh NOTES: * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. 1. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other purposes in future derivatives. The reset value shown in the table for these bits is 0. 2. I/O port values at reset are determined by the PRHI bit in the UCFG1 configuration byte. 3. The PCON reset value is x x BOF POF–0 0 0 0b. The BOF and POF flags are not affected by reset. The POF flag is set by hardware upon power up. The BOF flag is set by the occurrence of a brownout reset/interrupt and upon power up. 4. The WDCON reset value is xx11 0000b for a Watchdog reset, xx01 0000b for all other reset causes if the watchdog is enabled, and xx00 0000b for all other reset causes if the watchdog is disabled. 2001 Oct 26 8

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP FUNCTIONAL DESCRIPTION Port 0. Setting the corresponding bit in PT0AD disables that pin’s Details of 87LPC762 functions will be described in the following digital input. Port bits that have their digital inputs disabled will be sections. read as 0 by any instruction that accesses the port. Enhanced CPU Analog Comparators The 87LPC762 uses an enhanced 80C51 CPU which runs at twice the Two analog comparators are provided on the 87LPC762. Input and speed of standard 80C51 devices. This means that the performance of output options allow use of the comparators in a number of different the 87LPC762 running at 5 MHz is exactly the same as that of a configurations. Comparator operation is such that the output is a standard 80C51 running at 10 MHz. A machine cycle consists of 6 logical one (which may be read in a register and/or routed to a pin) oscillator cycles, and most instructions execute in 6 or 12 clocks. A when the positive input (one of two selectable pins) is greater than user configurable option allows restoring standard 80C51 execution the negative input (selectable from a pin or an internal reference timing. In that case, a machine cycle becomes 12 oscillator cycles. voltage). Otherwise the output is a zero. Each comparator may be configured to cause an interrupt when the output value changes. In the following sections, the term “CPU clock” is used to refer to the clock that controls internal instruction execution. This may Comparator Configuration sometimes be different from the externally applied clock, as in the Each comparator has a control register, CMP1 for comparator 1 and case where the part is configured for standard 80C51 timing by CMP2 for comparator 2. The control registers are identical and are means of the CLKR configuration bit or in the case where the clock shown in Figure 2. is divided down via the setting of the DIVM register. These features The overall connections to both comparators are shown in Figure 3. are described in the Oscillator section. There are eight possible configurations for each comparator, as Analog Functions determined by the control bits in the corresponding CMPn register: CPn, CNn, and OEn. These configurations are shown in Figure 4. The 87LPC762 incorporates two Analog Comparators. In order to give the best analog function performance and to minimize power The comparators function down to a VDD of 3.0V. consumption, pins that are actually being used for analog functions When each comparator is first enabled, the comparator output and must have the digital outputs and the digital inputs disabled. interrupt flag are not guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt should not be enabled Digital outputs are disabled by putting the port output into the Input during that time, and the comparator interrupt flag must be cleared Only (high impedance) mode as described in the I/O Ports section. before the interrupt is enabled in order to prevent an immediate Digital inputs on port 0 may be disabled through the use of the interrupt service. PT0AD register. Each bit in this register corresponds to one pin of CMPn Address: ACh for CMP1, ADh for CMP2 Reset Value: 00h Not Bit Addressable 7 6 5 4 3 2 1 0 — — CEn CPn CNn OEn COn CMFn BIT SYMBOL FUNCTION CMPn.7, 6 — Reserved for future use. Should not be set to 1 by user programs. CMPn.5 CEn Comparator enable. When set by software, the corresponding comparator function is enabled. Comparator output is stable 10 microseconds after CEn is first set. CMPn.4 CPn Comparator positive input select. When 0, CINnA is selected as the positive comparator input. When 1, CINnB is selected as the positive comparator input. CMPn.3 CNn Comparator negative input select. When 0, the comparator reference pin CMPREF is selected as the negative comparator input. When 1, the internal comparator reference Vref is selected as the negative comparator input. CMPn.2 OEn Output enable. When 1, the comparator output is connected to the CMPn pin if the comparator is enabled (CEn = 1). This output is asynchronous to the CPU clock. CMPn.1 COn Comparator output, synchronized to the CPU clock to allow reading by software. Cleared when the comparator is disabled (CEn = 0). CMPn.0 CMFn Comparator interrupt flag. This bit is set by hardware whenever the comparator output COn changes state. This bit will cause a hardware interrupt if enabled and of sufficient priority. Cleared by software and when the comparator is disabled (CEn = 0). SU01152 Figure 2. Comparator Control Registers (CMP1 and CMP2) 2001 Oct 26 9

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP COMPARATOR 1 CP1 (P0.4) CIN1A + (P0.3) CIN1B CO1 CMP1 (P0.6) (P0.5) CMPREF – OE1 Vref CN1 CHANGE DETECT CMF1 INTERRUPT COMPARATOR 2 CP2 (P0.2) CIN2A + (P0.1) CIN2B CO2 CMP2 (P0.0) – OE2 CN2 CHANGE DETECT CMF2 INTERRUPT SU01153 Figure 3. Comparator Input and Output Connections CPn, CNn, OEn = 0 0 0 CPn, CNn, OEn = 0 0 1 CINnA + CINnA + COn COn CMPn CMPREF – CMPREF – CPn, CNn, OEn = 0 1 0 CPn, CNn, OEn = 0 1 1 + + CINnA CINnA COn COn CMPn Vref (1.23V) – Vref (1.23V) – CPn, CNn, OEn = 1 0 0 CPn, CNn, OEn = 1 0 1 + + CINnB CINnB COn COn CMPn – – CMPREF CMPREF CPn, CNn, OEn = 1 1 0 CPn, CNn, OEn = 1 1 1 + + CINnB CINnB COn COn CMPn Vref (1.23V) – Vref (1.23V) – SU01154 Figure 4. Comparator Configurations 2001 Oct 26 10

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP Internal Reference Voltage wake up the processor. If the comparator output to a pin is enabled, An internal reference voltage generator may supply a default the pin should be configured in the push-pull mode in order to obtain reference when a single comparator input pin is used. The value of fast switching times while in power down mode. The reason is that the internal reference voltage, referred to as Vref, is 1.28 V ±10%. with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin Comparator Interrupt does not take place. Each comparator has an interrupt flag CMFn contained in its configuration register. This flag is set whenever the comparator Comparators consume power in Power Down and Idle modes, as output changes state. The flag may be polled by software or may be well as in the normal operating mode. This fact should be taken into used to generate an interrupt. The interrupt will be generated when account when system power consumption is an issue. the corresponding enable bit ECn in the IEN1 register is set and the Comparator Configuration Example interrupt system is enabled via the EA bit in the IEN0 register. The code shown in Figure 5 is an example of initializing one Comparators and Power Reduction Modes comparator. Comparator 1 is configured to use the CIN1A and Either or both comparators may remain enabled when Power Down CMPREF inputs, outputs the comparator result to the CMP1 pin, or Idle mode is activated. The comparators will continue to function and generates an interrupt when the comparator output changes. in the power reduction mode. If a comparator interrupt is enabled, a The interrupt routine used for the comparator must clear the change of the comparator output state will generate an interrupt and interrupt flag (CMF1 in this case) before returning. CmpInit: mov PT0AD,#30h ; Disable digital inputs on pins that are used ; for analog functions: CIN1A, CMPREF. anl P0M2,#0cfh ; Disable digital outputs on pins that are used orl P0M1,#30h ; for analog functions: CIN1A, CMPREF. mov CMP1,#24h ; Turn on comparator 1 and set up for: ; – Positive input on CIN1A. ; – Negative input from CMPREF pin. ; – Output to CMP1 pin enabled. call delay10us ; The comparator has to start up for at ; least 10 microseconds before use. anl CMP1,#0feh ; Clear comparator 1 interrupt flag. setb EC1 ; Enable the comparator 1 interrupt. The ; priority is left at the current value. setb EA ; Enable the interrupt system (if needed). ret ; Return to caller. SU01189 Figure 5. 2001 Oct 26 11

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP I2C Serial Interface The I2C bus uses two wires (SDA and SCL) to transfer information problems. SCL “stuck low” indicates a faulty master or slave. SCL between devices connected to the bus. The main features of the “stuck high” may mean a faulty device, or that noise induced onto bus are: the I2C bus caused all masters to withdraw from I2C arbitration. • Bidirectional data transfer between masters and slaves. The first five of these times are 4.7ms (see I2C specification) and • Serial addressing of slaves (no added wiring). are covered by the low order three bits of timer I. Timer I is clocked • by the 87LPC762 CPU clock. Timer I can be pre-loaded with one of Acknowledgment after each transferred byte. four values to optimize timing for different oscillator frequencies. At • lower frequencies, software response time is increased and will Multimaster bus. degrade maximum performance of the I2C bus. See special function • Arbitration between simultaneously transmitting masters without register I2CFG description for prescale values (CT0, CT1). corruption of serial data on bus. The MAXIMUM SCL CHANGE time is important, but its exact span The I2C subsystem includes hardware to simplify the software required is not critical. The complete 10 bits of timer I are used to count out to drive the I2C bus. The hardware is a single bit interface which in the maximum time. When I2C operation is enabled, this counter is addition to including the necessary arbitration and framing error cleared by transitions on the SCL pin. The timer does not run checks, includes clock stretching and a bus timeout timer. The between I2C frames (i.e., whenever reset or stop occurred more interface is synchronized to software either through polled loops recently than the last start). When this counter is running, it will carry or interrupts. out after 1020 to 1023 machine cycles have elapsed since a change on SCL. A carry out causes a hardware reset of the I2C interface Refer to the application note AN422, entitled “Using the 8XC751 and generates an interrupt if the Timer I interrupt is enabled. In Microcontroller as an I2C Bus Master” for additional discussion of cases where the bus hang-up is due to a lack of software response the 8xC76x I2C interface and sample driver routines. by this device, the reset releases SCL and allows I2C operation The 87LPC762 I2C implementation duplicates that of the 87C751 among other devices to continue. and 87C752 except for the following details: Timer I is enabled to run, and will reset the I2C interface upon • The interrupt vector addresses for both the I2C interrupt and the overflow, if the TIRUN bit in the I2CFG register is set. The Timer I Timer I interrupt. interrupt may be enabled via the ETI bit in IEN1, and its priority set • by the PTIH and PTI bits in the IP1H and IP1 registers respectively. The I2C SFR addresses (I2CON, I2CFG, I2DAT). • I2C Interrupts The location of the I2C interrupt enable bit and the name of the If I2C interrupts are enabled (EA and EI2 are both set to 1), an I2C SFR it is located within (EI2 is Bit 0 in IEN1). interrupt will occur whenever the ATN flag is set by a start, stop, • The location of the Timer I interrupt enable bit and the name of the arbitration loss, or data ready condition (refer to the description of ATN following). In practice, it is not efficient to operate the I2C interface in SFR it is located within (ETI is Bit 7 in IEN1). • this fashion because the I2C interrupt service routine would somehow The I2C and Timer I interrupts have a settable priority. have to distinguish between hundreds of possible conditions. Also, since I2C can operate at a fairly high rate, the software may execute Timer I is used to both control the timing of the I2C bus and also to faster if the code simply waits for the I2C interface. detect a “bus locked” condition, by causing an interrupt when nothing happens on the I2C bus for an inordinately long period of Typically, the I2C interrupt should only be used to indicate a start time while a transmission is in progress. If this interrupt occurs, the condition at an idle slave device, or a stop condition at an idle master program has the opportunity to attempt to correct the fault and device (if it is waiting to use the I2C bus). This is accomplished by resume I2C operation. enabling the I2C interrupt only during the aforementioned conditions. Six time spans are important in I2C operation and are insured by timer I: Reading I2CON • The MINIMUM HIGH time for SCL when this device is the master. RDAT The data from SDA is captured into “Receive DATa” • whenever a rising edge occurs on SCL. RDAT is also The MINIMUM LOW time for SCL when this device is a master. available (with seven low-order zeros) in the I2DAT This is not very important for a single-bit hardware interface like register. The difference between reading it here and this one, because the SCL low time is stretched until the software there is that reading I2DAT clears DRDY, allowing the responds to the I2C flags. The software response time normally I2C to proceed on to another bit. Typically, the first meets or exceeds the MIN LO time. In cases where the software seven bits of a received byte are read from responds within MIN HI + MIN LO) time, timer I will ensure that I2DAT, while the 8th is read here. Then I2DAT can be the minimum time is met. written to send the Acknowledge bit and clear DRDY. • The MINIMUM SCL HIGH TO SDA HIGH time in a stop condition. ATN “ATteNtion” is 1 when one or more of DRDY, ARL, STR, or • STP is 1. Thus, ATN comprises a single bit that can be The MINIMUM SDA HIGH TO SDA LOW time between I2C stop tested to release the I2C service routine from a “wait loop.” and start conditions (4.7ms, see I2C specification). • DRDY “Data ReaDY” (and thus ATN) is set when a rising edge The MINIMUM SDA LOW TO SCL LOW time in a start condition. occurs on SCL, except at idle slave. DRDY is cleared • The MAXIMUM SCL CHANGE time while an I2C frame is in by writing CDR = 1, or by writing or reading the I2DAT register. The following low period on SCL is stretched progress. A frame is in progress between a start condition and the until the program responds by clearing DRDY. following stop condition. This time span serves to detect a lack of software response on this device as well as external I2C 2001 Oct 26 12

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP I2CON Address: D8h Reset Value: 81h Bit Addressable1 7 6 5 4 3 2 1 0 READ RDAT ATN DRDY ARL STR STP MASTER — WRITE CXA IDLE CDR CARL CSTR CSTP XSTR XSTP BIT SYMBOL FUNCTION I2CON.7 RDAT Read: the most recently received data bit. “ CXA Write: clears the transmit active flag. I2CON.6 ATN Read: ATN = 1 if any of the flags DRDY, ARL, STR, or STP = 1. “ IDLE Write: in the I2C slave mode, writing a 1 to this bit causes the I2C hardware to ignore the bus until it is needed again. I2CON.5 DRDY Read: Data Ready flag, set when there is a rising edge on SCL. “ CDR Write: writing a 1 to this bit clears the DRDY flag. I2CON.4 ARL Read: Arbitration Loss flag, set when arbitration is lost while in the transmit mode. “ CARL Write: writing a 1 to this bit clears the CARL flag. I2CON.3 STR Read: Start flag, set when a start condition is detected at a master or non-idle slave. “ CSTR Write: writing a 1 to this bit clears the STR flag. I2CON.2 STP Read: Stop flag, set when a stop condition is detected at a master or non-idle slave. “ CSTP Write: writing a 1 to this bit clears the STP flag. I2CON.1 MASTER Read: indicates whether this device is currently as bus master. “ XSTR Write: writing a 1 to this bit causes a repeated start condition to be generated. I2CON.0 — Read: undefined. “ XSTP Write: writing a 1 to this bit causes a stop condition to be generated. SU01155 Figure 6. I2C Control Register (I2CON) I2DAT Address: D9h Reset Value: xxh Not Bit Addressable 7 6 5 4 3 2 1 0 READ RDAT — — — — — — — WRITE XDAT — — — — — — — BIT SYMBOL FUNCTION I2DAT.7 RDAT Read: the most recently received data bit, captured from SDA at every rising edge of SCL. Reading I2DAT also clears DRDY and the Transmit Active state. “ XDAT Write: sets the data for the next transmitted bit. Writing I2DAT also clears DRDY and sets the Transmit Active state. I2DAT.6–0 – Unused. SU01156 Figure 7. I2C Data Register (I2DAT) Checking ATN and DRDY STR, or STP is set, clearing DRDY will not release SCL to high, so When a program detects ATN = 1, it should next check DRDY. If that the I2C will not go on to the next bit. If a program detects DRDY = 1, then if it receives the last bit, it should capture the data ATN = 1, and DRDY = 0, it should go on to examine ARL, STR, from RDAT (in I2DAT or I2CON). Next, if the next bit is to be sent, it and STP. should be written to I2DAT. One way or another, it should clear DRDY and then return to monitoring ATN. Note that if any of ARL, 2001 Oct 26 13

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP ARL “Arbitration Loss” is 1 when transmit Active was set, but Regarding Transmit Active this device lost arbitration to another transmitter. Transmit Active is set by writing the I2DAT register, or by writing Transmit Active is cleared when ARL is 1. There are I2CON with XSTR = 1 or XSTP = 1. The I2C interface will only drive four separate cases in which ARL is set. the SDA line low when Transmit Active is set, and the ARL bit will only be set to 1 when Transmit Active is set. Transmit Active is 1. If the program sent a 1 or repeated start, but another cleared by reading the I2DAT register, or by writing I2CON with CXA device sent a 0, or a stop, so that SDA is 0 at the rising = 1. Transmit Active is automatically cleared when ARL is 1. edge of SCL. (If the other device sent a stop, the setting of ARL will be followed shortly by STP being set.) IDLE Writing 1 to “IDLE” causes a slave’s I2C hardware to ignore the I2C until the next start condition (but if 2. If the program sent a 1, but another device sent a MASTRQ is 1, then a stop condition will cause this repeated start, and it drove SDA low before SCL device to become a master). could be driven low. (This type of ARL is always accompanied by STR = 1.) CDR Writing a 1 to “Clear Data Ready” clears DRDY. (Reading or writing the I2DAT register also does this.) 3. In master mode, if the program sent a repeated start, but another device sent a 1, and it drove SCL low CARL Writing a 1 to “Clear Arbitration Loss” clears the ARL bit. before this device could drive SDA low. CSTR Writing a 1 to “Clear STaRt” clears the STR bit. 4. In master mode, if the program sent stop, but it could CSTP Writing a 1 to “Clear SToP” clears the STP bit. Note that not be sent because another device sent a 0. if one or more of DRDY, ARL, STR, or STP is 1, the low STR “STaRt” is set to a 1 when an I2C start condition is time of SCL is stretched until the service routine detected at a non-idle slave or at a master. (STR is not responds by clearing them. set when an idle slave becomes active due to a start XSTR Writing 1s to “Xmit repeated STaRt” and CDR tells the bit; the slave has nothing useful to do until the rising I2C hardware to send a repeated start condition. This edge of SCL sets DRDY.) should only be at a master. Note that XSTR need not STP “SToP” is set to 1 when an I2C stop condition is and should not be used to send an “initial” detected at a non-idle slave or at a master. (STP is not (non-repeated) start; it is sent automatically by the I2C set for a stop condition at an idle slave.) hardware. Writing XSTR = 1 includes the effect of writing I2DAT with XDAT = 1; it sets Transmit Active MASTER “MASTER” is 1 if this device is currently a master on and releases SDA to high during the SCL low time. the I2C. MASTER is set when MASTRQ is 1 and the After SCL goes high, the I2C hardware waits for the bus is not busy (i.e., if a start bit hasn’t been suitable minimum time and then drives SDA low to received since reset or a “Timer I” time-out, or if a stop make the start condition. has been received since the last start). MASTER is cleared when ARL is set, or after the software writes XSTP Writing 1s to “Xmit SToP” and CDR tells the I2C MASTRQ = 0 and then XSTP = 1. hardware to send a stop condition. This should only be done at a master. If there are no more messages to Writing I2CON initiate, the service routine should clear the MASTRQ Typically, for each bit in an I2C message, a service routine waits for bit in I2CFG to 0 before writing XSTP with 1. Writing ATN = 1. Based on DRDY, ARL, STR, and STP, and on the current XSTP = 1 includes the effect of writing I2DAT with bit position in the message, it may then write I2CON with one or XDAT = 0; it sets Transmit Active and drives SDA low more of the following bits, or it may read or write the I2DAT register. during the SCL low time. After SCL goes high, the I2C CXA Writing a 1 to “Clear Xmit Active” clears the Transmit hardware waits for the suitable minimum time and then Active state. (Reading the I2DAT register also does this.) releases SDA to high to make the stop condition. 2001 Oct 26 14

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP I2CFG Address: C8h Reset Value: 00h Bit Addressable 7 6 5 4 3 2 1 0 SLAVEN MASTRQ CLRTI TIRUN — — CT1 CT0 BIT SYMBOL FUNCTION I2CFG.7 SLAVEN Slave Enable. Writing a 1 this bit enables the slave functions of the I2C subsystem. If SLAVEN and MASTRQ are 0, the I2C hardware is disabled. This bit is cleared to 0 by reset and by an I2C time-out. I2CFG.6 MASTRQ Master Request. Writing a 1 to this bit requests mastership of the I2C bus. If a transmission is in progress when this bit is changed from 0 to 1, action is delayed until a stop condition is detected. A start condition is sent and DRDY is set (thus making ATN = 1 and generating an I2C interrupt). When a master wishes to release mastership status of the I2C, it writes a 1 to XSTP in I2CON. MASTRQ is cleared by an I2C time-out. I2CFG.5 CLRTI Writing a 1 to this bit clears the Timer I overflow flag. This bit position always reads as a 0. I2CFG.4 TIRUN Writing a 1 to this bit lets Timer I run; a zero stops and clears it. Together with SLAVEN, MASTRQ, and MASTER, this bit determines operational modes as shown in Table 1. I2CFG.2, 3 — Reserved for future use. Should not be set to 1 by user programs. I2CFG.1, 0 CT1, CT0 These two bits are programmed as a function of the CPU clock rate, to optimize the MIN HI and LO time of SCL when this device is a master on the I2C. The time value determined by these bits controls both of these parameters, and also the timing for stop and start conditions. SU01157 Figure 8. I2C Configuration Register (I2CFG) Regarding Software Response Time first line of the table where CPU clock max is greater than or equal Because the 87LPC762 can run at 20 MHz, and because the I2C to the actual frequency. interface is optimized for high-speed operation, it is quite likely that Table 2 also shows the machine cycle count for various settings of an I2C service routine will sometimes respond to DRDY (which is set CT1/CT0. This allows calculation of the actual minimum high and at a rising edge of SCL) and write I2DAT before SCL has gone low low times for SCL as follows: again. If XDAT were applied directly to SDA, this situation would produce an I2C protocol violation. The programmer need not worry about this possibility because XDAT is applied to SDA only when SCL min high/low time (in microseconds) (cid:0) 6 * Min Time Count CPU clock (in MHz) SCL is low. Conversely, a program that includes an I2C service routine may take a long time to respond to DRDY. Typically, an I2C routine operates For instance, at an 8 MHz frequency, with CT1/CT0 set to 1 0, the on a flag-polling basis during a message, with interrupts from other minimum SCL high and low times will be 5.25 m s. peripheral functions enabled. If an interrupt occurs, it will delay the Table 2 also shows the Timer I timeout period (given in machine response of the I2C service routine. The programmer need not worry cycles) for each CT1/CT0 combination. The timeout period varies about this very much either, because the I2C hardware stretches the because of the way in which minimum SCL high and low times are SCL low time until the service routine responds. The only constraint measured. When the I2C interface is operating, Timer I is pre-loaded on the response is that it must not exceed the Timer I time-out. at every SCL transition with a value dependent upon CT1/CT0. The Values to be used in the CT1 and CT0 bits are shown in Table 2. To pre-load value is chosen such that a minimum SCL high or low time allow the I2C bus to run at the maximum rate for a particular has elapsed when Timer I reaches a count of 008 (the actual value oscillator frequency, compare the actual oscillator rate to the f OSC pre-loaded into Timer I is 8 minus the machine cycle count). max column in the table. The value for CT1 and CT0 is found in the 2001 Oct 26 15

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP Table 1. Interaction of TIRUN with SLAVEN, MASTRQ, and MASTER SLAVEN, MASTRQ, TIRUN OPERATING MODE MASTER The I2C interface is disabled. Timer I is cleared and does not run. This is the state assumed after a reset. If an I2C All 0 0 application wants to ignore the I2C at certain times, it should write SLAVEN, MASTRQ, and TIRUN all to zero. All 0 1 The I2C interface is disabled. The I2C interface is enabled. The 3 low-order bits of Timer I run for min-time generation, but the hi-order bits do Any or all 1 0 not, so that there is no checking for I2C being “hung.” This configuration can be used for very slow I2C operation. The I2C interface is enabled. Timer I runs during frames on the I2C, and is cleared by transitions on SCL, and by Any or all 1 1 Start and Stop conditions. This is the normal state for I2C operation. Table 2. CT1, CT0 Values Min Time Count CPU Clock Max Timeout Period CT1, CT0 (Machine Cycles) (for 100 kHz I2C) (Machine Cycles) 1 0 7 8.4 MHz 1023 0 1 6 7.2 MHz 1022 0 0 5 6.0 MHz 1021 1 1 4 4.8 MHz 1020 Interrupts of the same or lower priority. The highest priority interrupt service The 87LPC762 uses a four priority level interrupt structure. This cannot be interrupted by any other interrupt source. So, if two allows great flexibility in controlling the handling of the 87LPC762’s many requests of different priority levels are received simultaneously, the interrupt sources. The 87LPC762 supports up to 12 interrupt sources. request of higher priority level is serviced. Each interrupt source can be individually enabled or disabled by If requests of the same priority level are received simultaneously, an setting or clearing a bit in registers IEN0 or IEN1. The IEN0 internal polling sequence determines which request is serviced. This register also contains a global disable bit, EA, which disables all is called the arbitration ranking. Note that the arbitration ranking is interrupts at once. only used to resolve simultaneous requests of the same priority level. Each interrupt source can be individually programmed to one of four Table 3 summarizes the interrupt sources, flag bits, vector priority levels by setting or clearing bits in the IP0, IP0H, IP1, and addresses, enable bits, priority bits, arbitration ranking, and whether IP1H registers. An interrupt service routine in progress can be each interrupt may wake up the CPU from Power Down mode. interrupted by a higher priority interrupt, but not by another interrupt Table 3. Summary of Interrupts Interrupt Vector Interrupt Interrupt Arbitration Power Down Description Flag Bit(s) Address Enable Bit(s) Priority Ranking Wakeup External Interrupt 0 IE0 0003h EX0 (IEN0.0) IP0H.0, IP0.0 1 (highest) Yes Timer 0 Interrupt TF0 000Bh ET0 (IEN0.1) IP0H.1, IP0.1 4 No External Interrupt 1 IE1 0013h EX1 (IEN0.2) IP0H.2, IP0.2 6 Yes Timer 1 Interrupt TF1 001Bh ET1 (IEN0.3) IP0H.3, IP0.3 9 No Serial Port Tx and Rx TI & RI 0023h ES (IEN0.4) IP0H.4, IP0.4 11 No Brownout Detect BOD 002Bh EBO (IEN0.5) IP0H.5, IP0.5 2 Yes I2C Interrupt ATN 0033h EI2 (IEN1.0) IP1H.0, IP1.0 5 No KBI Interrupt KBF 003Bh EKB (IEN1.1) IP1H.1, IP1.1 7 Yes Comparator 2 interrupt CMF2 0043h EC2 (IEN1.2) IP1H.2, IP1.2 10 Yes Watchdog Timer WDOVF 0053h EWD (IEN0.6) IP0H.6, IP0.6 3 Yes Comparator 1 interrupt CMF1 0063h EC1 (IEN1.5) IP1H.5, IP1.5 8 Yes Timer I interrupt – 0073h ETI (IEN1.7) IP1H.7, IP1.7 12 (lowest) No 2001 Oct 26 16

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP External Interrupt Inputs transition-activated, the external source has to hold the request pin The 87LPC762 has two individual interrupt inputs as well as the high for at least one machine cycle, and then hold it low for at least Keyboard Interrupt function. The latter is described separately one machine cycle. This is to ensure that the transition is seen and elsewhere in this section. The two interrupt inputs are identical to that interrupt request flag IEn is set. IEn is automatically cleared by those present on the standard 80C51 microcontroller. the CPU when the service routine is called. The external sources can be programmed to be level-activated or If the external interrupt is level-activated, the external source must transition-activated by setting or clearing bit IT1 or IT0 in Register hold the request active until the requested interrupt is actually TCON. If ITn = 0, external interrupt n is triggered by a detected low generated. If the external interrupt is still asserted when the interrupt at the INTn pin. If ITn = 1, external interrupt n is edge triggered. In service routine is completed another interrupt will be generated. It is this mode if successive samples of the INTn pin show a high in one not necessary to clear the interrupt flag IEn when the interrupt is cycle and a low in the next cycle, interrupt request flag IEn in TCON level sensitive, it simply tracks the input pin level. is set, causing an interrupt request. If an external interrupt is enabled when the 87LPC762 is put into Since the external interrupt pins are sampled once each machine Power Down or Idle mode, the interrupt will cause the processor to cycle, an input high or low should hold for at least 6 CPU Clocks to wake up and resume operation. Refer to the section on Power ensure proper sampling. If the external interrupt is Reduction Modes for details. IE0 EX0 IE1 EX1 WAKEUP (IF IN POWER DOWN) BOD EBO EA KBF (FROM IEN0 INTERRUPT EKB REGISTER) TO CPU TF0 CM2 ET0 EC2 TF1 WDT ET1 EWD RI + TI CM1 ES EC1 ATN EI2 SU01158 Figure 9. Interrupt Sources, Interrupt Enables, and Power Down Wakeup Sources 2001 Oct 26 17

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP I/O Ports input and output without the need to reconfigure the port. This is The 87LPC762 has 3 I/O ports, port 0, port 1, and port 2. The exact possible because when the port outputs a logic high, it is weakly number of I/O pins available depend upon the oscillator and reset driven, allowing an external device to pull the pin low. When the pin options chosen. At least 15 pins of the 87LPC762 may be used as is pulled low, it is driven strongly and able to sink a fairly large I/Os when a two-pin external oscillator and an external reset circuit current. These features are somewhat similar to an open drain are used. Up to 18 pins may be available if fully on-chip oscillator output except that there are three pull-up transistors in the and reset configurations are chosen. quasi-bidirectional output that serve different purposes. All but three I/O port pins on the 87LPC762 may be software One of these pull-ups, called the “very weak” pull-up, is turned on configured to one of four types on a bit-by-bit basis, as shown in whenever the port latch for the pin contains a logic 1. The very weak Table 4. These are: quasi-bidirectional (standard 80C51 port pull-up sources a very small current that will pull the pin high if it is outputs), push-pull, open drain, and input only. Two configuration left floating. registers for each port choose the output type for each port pin. A second pull-up, called the “weak” pull-up, is turned on when the Table 4. Port Output Configuration Settings port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source current for a PxM1.y PxM2.y Port Output Mode quasi-bidirectional pin that is outputting a 1. If a pin that has a logic 1 0 0 Quasi-bidirectional on it is pulled low by an external device, the weak pull-up turns off, and only the very weak pull-up remains on. In order to pull the pin 0 1 Push-Pull low under these conditions, the external device has to sink enough 1 0 Input Only (High Impedance) current to overpower the weak pull-up and take the voltage on the port pin below its input threshold. 1 1 Open Drain The third pull-up is referred to as the “strong” pull-up. This pull-up is used to speed up low-to-high transitions on a quasi-bidirectional port Quasi-Bidirectional Output Configuration pin when the port latch changes from a logic 0 to a logic 1. When this The default port output configuration for standard 87LPC762 I/O occurs, the strong pull-up turns on for a brief time, two CPU clocks, in ports is the quasi-bidirectional output that is common on the 80C51 order to pull the port pin high quickly. Then it turns off again. and most of its derivatives. This output type can be used as both an The quasi-bidirectional port configuration is shown in Figure 10. VDD 2 CPU CLOCK DELAY P STRONG P VERY P WEAK WEAK PORT PIN PORT LATCH N DATA INPUT DATA SU01159 Figure 10. Quasi-Bidirectional Output 2001 Oct 26 18

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP Open Drain Output Configuration The value of port pins at reset is determined by the PRHI bit in the The open drain output configuration turns off all pull-ups and only UCFG1 register. Ports may be configured to reset high or low as drives the pull-down transistor of the port driver when the port latch needed for the application. When port pins are driven high at reset, contains a logic 0. To be used as a logic output, a port configured in they are in quasi-bidirectional mode and therefore do not source this manner must have an external pull-up, typically a resistor tied to large amounts of current. VDD. The pull-down for this mode is the same as for the Every output on the 87LPC762 may potentially be used as a 20 mA quasi-bidirectional mode. sink LED drive output. However, there is a maximum total output The open drain port configuration is shown in Figure 11. current for all ports which must not be exceeded. Push-Pull Output Configuration All ports pins of the 87LPC762 have slew rate controlled outputs. This is to limit noise generated by quickly switching output signals. The The push-pull output configuration has the same pull-down structure slew rate is factory set to approximately 10 ns rise and fall times. as both the open drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a The bits in the P2M1 register that are not used to control logic 1. The push-pull mode may be used when more source current configuration of P2.1 and P2.0 are used for other purposes. These is needed from a port output. bits can enable Schmitt trigger inputs on each I/O port, enable toggle outputs from Timer 0 and Timer 1, and enable a clock output The push-pull port configuration is shown in Figure 12. if either the internal RC oscillator or external clock input is being The three port pins that cannot be configured are P1.2, P1.3, and used. The last two functions are described in the Timer/Counters P1.5. The port pins P1.2 and P1.3 are permanently configured as and Oscillator sections respectively. The enable bits for all of these open drain outputs. They may be used as inputs by writing ones to functions are shown in Figure 13. their respective port latches. P1.5 may be used as a Schmitt trigger Each I/O port of the 87LPC762 may be selected to use TTL level input if the 87LPC762 has been configured for an internal reset and inputs or Schmitt inputs with hysteresis. A single configuration bit is not using the external reset input function RST. determines this selection for the entire port. Port pins P1.2, P1.3, Additionally, port pins P2.0 and P2.1 are disabled for both input and and P1.5 always have a Schmitt trigger input. output if one of the crystal oscillator options is chosen. Those options are described in the Oscillator section. PORT PIN PORT LATCH N DATA INPUT DATA SU01160 Figure 11. Open Drain Output VDD P PORT PIN PORT LATCH N DATA INPUT DATA SU01161 Figure 12. Push-Pull Output 2001 Oct 26 19

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP P2M1 Address: A4h Reset Value: 00h Not Bit Addressable 7 6 5 4 3 2 1 0 P2S P1S P0S ENCLK T1OE T0DE (P2M1.1) (P2M1.0) BIT SYMBOL FUNCTION P2M1.7 P2S When P2S = 1, this bit enables Schmitt trigger inputs on Port 2. P2M1.6 P1S When P1S = 1, this bit enables Schmitt trigger inputs on Port 1. P2M1.5 P0S When P0S = 1, this bit enables Schmitt trigger inputs on Port 0. P2M1.4 ENCLK When ENCLK is set and the 87LPC762 is configured to use the on-chip RC oscillator, a clock output is enabled on the X2 pin (P2.0). Refer to the Oscillator section for details. P2M1.3 T1OE When set, the P0.7 pin is toggled whenever Timer 1 overflows. The output frequency is therefore one half of the Timer 1 overflow rate. Refer to the Timer/Counters section for details. P2M1.2 T0OE When set, the P1.2 pin is toggled whenever Timer 0 overflows. The output frequency is therefore one half of the Timer 0 overflow rate. Refer to the Timer/Counterssection for details. P2M1.1, P2M1.0 — These bits, along with the matching bits in the P2M2 register, control the output configuration of P2.1 and P2.0 respectively, as shown in Table 4. SU01222 Figure 13. Port 2 Mode Register 1 (P2M1) Keyboard Interrupt (KBI) the KBI register, as shown in Figure 15. The Keyboard Interrupt Flag The Keyboard Interrupt function is intended primarily to allow a (KBF) in the AUXR1 register is set when any enabled pin is pulled single interrupt to be generated when any key is pressed on a low while the KBI interrupt function is active. An interrupt will keyboard or keypad connected to specific pins of the 87LPC762, as generated if it has been enabled. Note that the KBF bit must be shown in Figure 14. This interrupt may be used to wake up the CPU cleared by software. from Idle or Power Down modes. This feature is particularly useful in Due to human time scales and the mechanical delay associated with handheld, battery powered systems that need to carefully manage keyswitch closures, the KBI feature will typically allow the interrupt power consumption yet also need to be convenient to use. service routine to poll port 0 in order to determine which key was The 87LPC762 allows any or all pins of port 0 to be enabled to pressed, even if the processor has to wake up from Power Down cause this interrupt. Port pins are enabled by the setting of bits in mode. Refer to the section on Power Reduction Modes for details. 2001 Oct 26 20

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP P0.7 KBI.7 P0.6 KBI.6 P0.5 KBI.5 P0.4 KBI.4 KBF (KBI INTERRUPT) P0.3 KBI.3 EKB P0.2 (FROM IEN1 REGISTER) KBI.2 P0.1 KBI.1 P0.0 KBI.0 SU01163 Figure 14. Keyboard Interrupt KBI Address: 86h Reset Value: 00h Not Bit Addressable 7 6 5 4 3 2 1 0 KBI.7 KBI.6 KBI.5 KBI.4 KBI.3 KBI.2 KBI.1 KBI.0 BIT SYMBOL FUNCTION KBI.7 KBI.7 When set, enables P0.7 as a cause of a Keyboard Interrupt. KBI.6 KBI.6 When set, enables P0.6 as a cause of a Keyboard Interrupt. KBI.5 KBI.5 When set, enables P0.5 as a cause of a Keyboard Interrupt. KBI.4 KBI.4 When set, enables P0.4 as a cause of a Keyboard Interrupt. KBI.3 KBI.3 When set, enables P0.3 as a cause of a Keyboard Interrupt. KBI.2 KBI.2 When set, enables P0.2 as a cause of a Keyboard Interrupt. KBI.1 KBI.1 When set, enables P0.1 as a cause of a Keyboard Interrupt. KBI.0 KBI.0 When set, enables P0.0 as a cause of a Keyboard Interrupt. Note: the Keyboard Interrupt must be enabled in order for the settings of the KBI register to be effective. The interrupt flag (KBF) is located at bit 7 of AUXR1. SU01164 Figure 15. Keyboard Interrupt Register (KBI) 2001 Oct 26 21

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP Oscillator The 87LPC762 provides several user selectable oscillator options, programmed. Basic oscillator types that are supported include: low, allowing optimization for a range of needs from high precision to medium, and high speed crystals, covering a range from 20 kHz to lowest possible cost. These are configured when the EPROM is 20 MHz; ceramic resonators; and on-chip RC oscillator. Low Frequency Oscillator Option This option supports an external crystal in the range of 20 kHz to 100 kHz. Table 5 shows capacitor values that may be used with a quartz crystal in this mode. Table 5. Recommended oscillator capacitors for use with the low frequency oscillator option Oscillator VDD = 2.7 to 4.5 V VDD = 4.5 to 6.0 V Frequency Lower Limit Optimal Value Upper Limit Lower Limit Optimal Value Upper Limit 20 kHz 15 pF 15 pF 33 pF 33 pF 33 pF 47 pF 32 kHz 15 pF 15 pF 33 pF 33 pF 33 pF 47 pF 100 kHz 15 pF 15 pF 33 pF 15 pF 15 pF 33 pF Medium Frequency Oscillator Option This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration. Table 6 shows capacitor values that may be used with a quartz crystal in this mode. Table 6. Recommended oscillator capacitors for use with the medium frequency oscillator option VDD = 2.7 to 4.5 V OOsscciillllaattoorr FFrreeqqueennccyy Lower Limit Optimal Value Upper Limit 100 kHz 33 pF 33 pF 47 pF 1 MHz 15 pF 15 pF 33 pF 4 MHz 15 pF 15 pF 33 pF High Frequency Oscillator Option This option supports an external crystal in the range of 4 to 20 MHz. Ceramic resonators are also supported in this configuration. Table 7 shows capacitor values that may be used with a quartz crystal in this mode. Table 7. Recommended oscillator capacitors for use with the high frequency oscillator option Oscillator VDD = 2.7 to 4.5 V VDD = 4.5 to 6.0 V Frequency Lower Limit Optimal Value Upper Limit Lower Limit Optimal Value Upper Limit 4 MHz 15 pF 33 pF 47 pF 15 pF 33 pF 68 pF 8 MHz 15 pF 15 pF 33 pF 15 pF 33 pF 47 pF 16 MHz – – – 15 pF 15 pF 33 pF 20 MHz – – – 15 pF 15 pF 33 pF On-Chip RC Oscillator Option pin may be used as a standard port pin. A clock output on the X2/P2.0 The on-chip RC oscillator option has a typical frequency of 6 MHz pin may be enabled when the external clock input is used. and can be divided down for slower operation through the use of the Clock Output DIVM register. Note that some devices have 10% tolerance and The 87LPC762 supports a clock output function when either the others 25% tolerance at this time. For on-chip oscillator tolerance on-chip RC oscillator or external clock input options are selected. see Electrical Characteristics table. A clock output on the X2/P2.0 This allows external devices to synchronize to the 87LPC762. When pin may be enabled when the on-chip RC oscillator is used. enabled, via the ENCLK bit in the P2M1 register, the clock output External Clock Input Option appears on the X2/CLKOUT pin whenever the on-chip oscillator is In this configuration, the processor clock is input from an external running, including in Idle mode. The frequency of the clock output is source driving the X1/P2.1 pin. The rate may be from 0 Hz up to 1/6 of the CPU clock rate. If the clock output is not needed in Idle 20 MHz when VDD is above 4.5 V and up to 10 MHz when VDD is mode, it may be turned off prior to entering Idle, saving additional below 4.5 V. When the external clock input mode is used, the X2/P2.0 power. The clock output may also be enabled when the external clock input option is selected. 2001 Oct 26 22

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP THE OSCILLATOR MUST BE CONFIGURED IN ONE OF QUARTZ CRYSTAL OR THE FOLLOWING MODES: CERAMIC RESONATOR – LOW FREQUENCY CRYSTAL 87LPC762 – MEDIUM FREQUENCY CRYSTAL – HIGH FREQUENCY CRYSTAL X1 CAPACITOR VALUES MAY BE OPTIMIZED FOR DIFFERENT OSCILLATOR FREQUENCIES (SEE TEXT) * X2 A SERIES RESISTOR MAY BE REQUIRED IN ORDER TO LIMIT CRYSTAL DRIVE LEVELS. THIS IS PARTICULARLY IMPORTANT FOR LOW FREQUENCY CRYSTALS (SEE TEXT). SU01224 Figure 16. Using the Crystal Oscillator 87LPC762 CMOS COMPATIBLE EXTERNAL OSCILLATOR SIGNAL X1 THE OSCILLATOR MUST BE CONFIGURED IN X2 THE EXTERNAL CLOCK INPUT MODE. A CLOCK OUTPUT MAY BE OBTAINED ON THE X2 PIN BY SETTING THE ENCLK BIT IN THE P2M1 REGISTER. SU01225 Figure 17. Using an External Clock Input 2001 Oct 26 23

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP FOSC2 (UCFG1.2) FOSC1 (UCFG1.1) FOSC0 (UCFG1.0) CLOCK SELECT EXTERNAL CLOCK INPUT XTAL SELECT OSCILLATOR STARTUP TIMER INTERNAL RC OSCILLATOR CLOCK 10-BIT RIPPLE COUNTER OUT COUNT 256 CRYSTAL: LOW FREQUENCY CLOCK SOURCES RESET COUNT COUNT 1024 CRYSTAL: MEDIUM FREQUENCY CRYSTAL: HIGH FREQUENCY DIVIDE-BY-M (DIVM REGISTER) AND CLKR SELECT CPU CLOCK POWER MONITOR RESET ÷1/÷2 POWER DOWN CLKR (UCFG1.3) SU01167 Figure 18. Block Diagram of Oscillator Control CPU Clock Modification: CLKR and DIVM Power Monitoring Functions For backward compatibility, the CLKR configuration bit allows The 87LPC762 incorporates power monitoring functions designed to setting the 87LPC762 instruction and peripheral timing to match prevent incorrect operation during initial power up and power loss or standard 80C51 timing by dividing the CPU clock by two. Default reduction during operation. This is accomplished with two hardware timing for the 87LPC762 is 6 CPU clocks per machine cycle while functions: Power-On Detect and Brownout Detect. standard 80C51 timing is 12 clocks per machine cycle. This division also applies to peripheral timing, allowing 80C51 code that Brownout Detection is oscillator frequency and/or timer rate dependent. The CLKR bit The Brownout Detect function allows preventing the processor from is located in the EPROM configuration register UCFG1, described failing in an unpredictable manner if the power supply voltage drops under EPROM Characteristics below a certain level. The default operation is for a brownout detection to cause a processor reset, however it may alternatively In addition to this, the CPU clock may be divided down from the be configured to generate an interrupt by setting the BOI bit in the oscillator rate by a programmable divider, under program control. AUXR1 register (AUXR1.5). This function is controlled by the DIVM register. If the DIVM register is set to zero (the default value), the CPU will be clocked by either The 87LPC762 allows selection of two Brownout levels: 2.5 V or the unmodified oscillator rate, or that rate divided by two, as 3.8 V. When VDD drops below the selected voltage, the brownout determined by the previously described CLKR function. detector triggers and remains active until VDD is returns to a level above the Brownout Detect voltage. When Brownout Detect causes When the DIVM register is set to some value N (between 1 and 255), a processor reset, that reset remains active as long as VDD remains the CPU clock is divided by 2 * (N + 1). Clock division values from 4 below the Brownout Detect voltage. When Brownout Detect through 512 are thus possible. This feature makes it possible to generates an interrupt, that interrupt occurs once as VDD crosses temporarily run the CPU at a lower rate, reducing power consumption, from above to below the Brownout Detect voltage. For the interrupt in a manner similar to Idle mode. By dividing the clock, the CPU can to be processed, the interrupt system and the BOI interrupt must retain the ability to respond to events other than those that can cause both be enabled (via the EA and EBO bits in IEN0). interrupts (i.e. events that allow exiting the Idle mode) by executing its normal program at a lower rate. This can allow bypassing the When Brownout Detect is activated, the BOF flag in the PCON oscillator startup time in cases where Power Down mode would register is set so that the cause of processor reset may be determined otherwise be used. The value of DIVM may be changed by the by software. This flag will remain set until cleared by software. program at any time without interrupting code execution. 2001 Oct 26 24

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP For correct activation of Brownout Detect, the VDD fall time must be The processor can be made to exit Power Down mode via Reset or no faster than 50 mV/m s. When VDD is restored, is should not rise one of the interrupt sources shown in Table 8. This will occur if the faster than 2 mV/m s in order to insure a proper reset. interrupt is enabled and its priority is higher than any interrupt currently in progress. The brownout voltage (2.5 V or 3.8 V) is selected via the BOV bit in the EPROM configuration register UCFG1. When unprogrammed In Power Down mode, the power supply voltage may be reduced to (BOV = 1), the brownout detect voltage is 2.5 V. When programmed the RAM keep-alive voltage VRAM. This retains the RAM contents (BOV = 0), the brownout detect voltage is 3.8 V. at the point where Power Down mode was entered. SFR contents If the Brownout Detect function is not required in an application, it are not guaranteed after VDD has been lowered to VRAM, therefore it is recommended to wake up the processor via Reset in this case. may be disabled, thus saving power. Brownout Detect is disabled by setting the control bit BOD in the AUXR1 register (AUXR1.6). VDD must be raised to within the operating range before the Power Down mode is exited. Since the watchdog timer has a separate Power On Detection oscillator, it may reset the processor upon overflow if it is running The Power On Detect has a function similar to the Brownout Detect, during Power Down. but is designed to work as power comes up initially, before the Note that if the Brownout Detect reset is enabled, the processor will power supply voltage reaches a level where Brownout Detect can be put into reset as soon as VDD drops below the brownout voltage. work. When this feature is activated, the POF flag in the PCON If Brownout Detect is configured as an interrupt and is enabled, it will register is set to indicate an initial power up condition. The POF flag wake up the processor from Power Down mode when VDD drops will remain set until cleared by software. below the brownout voltage. Power Reduction Modes When the processor wakes up from Power Down mode, it will start The 87LPC762 supports Idle and Power Down modes of power the oscillator immediately and begin execution when the oscillator is reduction. stable. Oscillator stability is determined by counting 1024 CPU clocks after start-up when one of the crystal oscillator configurations Idle Mode is used, or 256 clocks after start-up for the internal RC or external The Idle mode leaves peripherals running in order to allow them to clock input configurations. activate the processor when an interrupt is generated. Any enabled interrupt source or Reset may terminate Idle mode. Idle mode is Some chip functions continue to operate and draw power during entered by setting the IDL bit in the PCON register (see Figure 19). Power Down mode, increasing the total power used during Power Down. These include the Brownout Detect, Watchdog Timer, and Power Down Mode Comparators. The Power Down mode stops the oscillator in order to absolutely minimize power consumption. Power Down mode is entered by setting the PD bit in the PCON register (see Figure 19). PCON Address: 87h Reset Value: (cid:0) 30h for a Power On reset (cid:0) 20h for a Brownout reset Not Bit Addressable (cid:0) 00h for other reset sources 7 6 5 4 3 2 1 0 SMOD1 SMOD0 BOF POF GF1 GF0 PD IDL BIT SYMBOL FUNCTION PCON.7 SMOD1 When set, this bit doubles the UART baud rate for modes 1, 2, and 3. PCON.6 SMOD0 This bit selects the function of bit 7 of the SCON SFR. When 0, SCON.7 is the SM0 bit. When 1, SCON.7 is the FE (Framing Error) flag. See Figure 26 for additional information. PCON.5 BOF Brown Out Flag. Set automatically when a brownout reset or interrupt has occurred. Also set at power on. Cleared by software. Refer to the Power Monitoring Functions section for additional information. PCON.4 POF Power On Flag. Set automatically when a power-on reset has occurred. Cleared by software. Refer to the Power Monitoring Functions section for additional information. PCON.3 GF1 General purpose flag 1. May be read or written by user software, but has no effect on operation. PCON.2 GF0 General purpose flag 0. May be read or written by user software, but has no effect on operation. PCON.1 PD Power Down control bit. Setting this bit activates Power Down mode operation. Cleared when the Power Down mode is terminated (see text). PCON.0 IDL Idle mode control bit. Setting this bit activates Idle mode operation. Cleared when the Idle mode is terminated (see text). SU01168 Figure 19. Power Control Register (PCON) 2001 Oct 26 25

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP Table 8. Sources of Wakeup from Power Down Mode Wakeup Source Conditions External Interrupt 0 or 1 The corresponding interrupt must be enabled. Keyboard Interrupt The keyboard interrupt feature must be enabled and properly set up. The corresponding interrupt must be enabled. Comparator 1 or 2 The comparator(s) must be enabled and properly set up. The corresponding interrupt must be enabled. Watchdog Timer Reset The watchdog timer must be enabled via the WDTE bit in the UCFG1 EPROM configuration byte. Watchdog Timer Interrupt The WDTE bit in the UCFG1 EPROM configuration byte must not be set. The corresponding interrupt must be enabled. Brownout Detect Reset The BOD bit in AUXR1 must not be set (brownout detect not disabled). The BOI bit in AUXR1 must not be set (brownout interrupt disabled). Brownout Detect Interrupt The BOD bit in AUXR1 must not be set (brownout detect not disabled). The BOI bit in AUXR1 must be set (brownout interrupt enabled). The corresponding interrupt must be enabled. Reset Input The external reset input must be enabled. 2001 Oct 26 26

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP Low Voltage EPROM Operation save external components and to be able to use pin P1.5 as a The EPROM array contains some analog circuits that are not general-purpose input pin. required when VDD is less than 4 V, but are required for a VDD The 87LPC762 can additionally be configured to use P1.5 as an greater than 4 V. The LPEP bit (AUXR.4), when set by software, will external active-low reset pin RST by programming the RPD bit in the power down these analog circuits resulting in a reduced supply User Configuration Register UCFG1 to 0. The internal reset is still current. LPEP is cleared only by power-on reset, so it may be set active on power-up of the device. While the signal on the RST pin is ONLY for applications that always operate with VDD less than 4 V. low, the 87LPC762 is held in reset until the signal goes high. Reset The watchdog timer on the LPC762 can act as an oscillator fail The 87LPC762 has an integrated power-on reset circuit which detect because it uses an independent, fully on-chip oscillator. always provides a reset when power is initially applied to the device. UCFG1 is described in the System Configuration Bytes section of It is recommended to use the internal reset whenever possible to this datasheet. UCFG1.RPD = 1 (default) UCFG1.RPD = 0 87LPC762 87LPC762 P1.5 RST Pin is used as Pin is used as digital input pin active-low reset pin Internal power-on Internal power-on Reset active Reset active SU01226 Figure 20. Using pin P1.5 as general purpose input pin or as low-active reset pin RPD (UCFG1.6) RST/VPP PIN WDTE (UCFG1.7) S WDT MODULE Q CHIP RESET R SOFTWARE RESET SRST (AUXR1.3) RESET TIMING POWER MONITOR CPU RESET CLOCK SU01170 Figure 21. Block Diagram Showing Reset Sources 2001 Oct 26 27

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP Timer/Counters machine cycle. When the samples of the pin state show a high in The 87LPC762 has two general purpose counter/timers which are one cycle and a low in the next cycle, the count is incremented. The upward compatible with the standard 80C51 Timer 0 and Timer 1. new count value appears in the register during the cycle following Both can be configured to operate either as timers or event counters the one in which the transition was detected. Since it takes 2 (see Figure 22). An option to automatically toggle the T0 and/or T1 machine cycles (12 CPU clocks) to recognize a 1-to-0 transition, the pins upon timer overflow has been added. maximum count rate is 1/6 of the CPU clock frequency. There are no restrictions on the duty cycle of the external input signal, but to In the “Timer” function, the register is incremented every machine ensure that a given level is sampled at least once before it changes, cycle. Thus, one can think of it as counting machine cycles. Since a it should be held for at least one full machine cycle. machine cycle consists of 6 CPU clock periods, the count rate is 1/6 of the CPU clock frequency. Refer to the section Enhanced CPU for The “Timer” or “Counter” function is selected by control bits C/T in a description of the CPU clock. the Special Function Register TMOD. In addition to the “Timer” or “Counter” selection, Timer 0 and Timer 1 have four operating In the “Counter” function, the register is incremented in response to modes, which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, a 1-to-0 transition at its corresponding external input pin, T0 or T1. 1, and 2 are the same for both Timers/Counters. Mode 3 is different. In this function, the external input is sampled once during every The four operating modes are described in the following text. TMOD Address: 89h Reset Value: 00h Not Bit Addressable 7 6 5 4 3 2 1 0 GATE C/T M1 M0 GATE C/T M1 M0 T1 T0 BIT SYMBOL FUNCTION TMOD.7 GATE Gating control for Timer 1. When set, Timer/Counter is enabled only while the INT1 pin is high and the TR1 control pin is set. When cleared, Timer 1 is enabled when the TR1 control bit is set. TMOD.6 C/T Timer or Counter Selector for Timer 1. Cleared for Timer operation (input from internal system clock.) Set for Counter operation (input from T1 input pin). TMOD.5, 4 M1, M0 Mode Select for Timer 1 (see table below). TMOD.3 GATE Gating control for Timer 0. When set, Timer/Counter is enabled only while the INT0 pin is high and the TR0 control pin is set. When cleared, Timer 0 is enabled when the TR0 control bit is set. TMOD.2 C/T Timer or Counter Selector for Timer 0. Cleared for Timer operation (input from internal system clock.) Set for Counter operation (input from T0 input pin). TMOD.1, 0 M1, M0 Mode Select for Timer 0 (see table below). M1, M0 Timer Mode 0 0 8048 Timer “TLn” serves as 5-bit prescaler. 0 1 16-bit Timer/Counter “THn” and “TLn” are cascaded; there is no prescaler. 1 0 8-bit auto-reload Timer/Counter. THn holds a value which is loaded into TLn when it overflows. 1 1 Timer 0 is a dual 8-bit Timer/Counter in this mode. TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer only, controlled by the Timer 1 control bits (see text). Timer 1 in this mode is stopped. SU01171 Figure 22. Timer/Counter Mode Control Register (TMOD) 2001 Oct 26 28

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP Mode 0 measurements). TRn is a control bit in the Special Function Register Putting either Timer into Mode 0 makes it look like an 8048 Timer, TCON (Figure 23). The GATE bit is in the TMOD register. which is an 8-bit Counter with a divide-by-32 prescaler. Figure 24 The 13-bit register consists of all 8 bits of THn and the lower 5 bits shows Mode 0 operation. of TLn. The upper 3 bits of TLn are indeterminate and should be In this mode, the Timer register is configured as a 13-bit register. As ignored. Setting the run flag (TRn) does not clear the registers. the count rolls over from all 1s to all 0s, it sets the Timer interrupt Mode 0 operation is the same for Timer 0 and Timer 1. See flag TFn. The count input is enabled to the Timer when TRn = 1 and Figure 24. There are two different GATE bits, one for Timer 1 either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the Timer to (TMOD.7) and one for Timer 0 (TMOD.3). be controlled by external input INTn, to facilitate pulse width TCON Address: 88h Reset Value: 00h Bit Addressable 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 BIT SYMBOL FUNCTION TCON.7 TF1 Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the interrupt is processed, or by software. TCON.6 TR1 Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off. TCON.5 TF0 Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors to the interrupt routine, or by software. TCON.4 TR0 Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off. TCON.3 IE1 Interrupt 1 Edge flag. Set by hardware when external interrupt 1 edge is detected. Cleared by hardware when the interrupt is processed, or by software. TCON.2 IT1 Interrupt 1 Type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. TCON.1 IE0 Interrupt 0 Edge flag. Set by hardware when external interrupt 0 edge is detected. Cleared by hardware when the interrupt is processed, or by software. TCON.0 IT0 Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. SU01172 Figure 23. Timer/Counter Control Register (TCON) OVERFLOW OSC/6 OR C/T = 0 OSC/12 TLn THn TFn INTERRUPT (5 BITS) (8 BITS) Tn PIN C/T = 1 CONTROL TRn TOGGLE GATE Tn PIN INTn PIN TnOE SU01173 Figure 24. Timer/Counter 0 or 1 in Mode 0 (13-Bit Counter) 2001 Oct 26 29

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP Mode 1 Timer 0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit Mode 1 is the same as Mode 0, except that all 16 bits of the timer counters. The logic for Mode 3 on Timer 0 is shown in Figure 27. register (THn and TLn) are used. See Figure 25 TL0 uses the Timer 0 control bits: C/T, GATE, TR0 and pin INT0, and TF0. TH0 is locked into a timer function (counting machine Mode 2 cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, Mode 2 configures the Timer register as an 8-bit Counter (TL1) with TH0 now controls the “Timer 1” interrupt. automatic reload, as shown in Figure 26. Overflow from TLn not only sets TFn, but also reloads TLn with the contents of THn, which must Mode 3 is provided for applications that require an extra 8-bit timer. be preset by software. The reload leaves THn unchanged. Mode 2 With Timer 0 in Mode 3, an 87LPC762 can look like it has three operation is the same for Timer 0 and Timer 1. Timer/Counters. When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it into and out of its own Mode 3. It can still Mode 3 be used by the serial port as a baud rate generator, or in any When Timer 1 is in Mode 3 it is stopped. The effect is the same as application not requiring an interrupt. setting TR1 = 0. OVERFLOW OSC/6 OR C/T = 0 OSC/12 TLn THn TFn INTERRUPT (8 BITS) (8 BITS) Tn PIN C/T = 1 CONTROL TRn TOGGLE GATE Tn PIN INTn PIN TnOE SU01174 Figure 25. Timer/Counter 0 or 1 in Mode 1 (16-Bit Counter) OSC/6 or C/T = 0 OSC/12 TLn OVERFLOW TFn INTERRUPT (8 BITS) Tn PIN C/T = 1 CONTROL RELOAD TRn TOGGLE GATE Tn PIN INTn PIN THn (8 BITS) TnOE SU01392 Figure 26. Timer/Counter 0 or 1 in Mode 2 (8-Bit Auto-Reload) 2001 Oct 26 30

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP OSC/6 OR C/T = 0 OSC/12 TL0 OVERFLOW TF0 INTERRUPT (8 BITS) T0 PIN C/T = 1 CONTROL TR0 TOGGLE GATE T0 PIN INT0 PIN T0OE OSC/6 OR TH0 OVERFLOW TF1 INTERRUPT OSC/12 (8 BITS) CONTROL TOGGLE TR1 T1 PIN T1OE SU01176 Figure 27. Timer/Counter 0 Mode 3 (Two 8-Bit Counters) Timer Overflow Toggle Output Mode 1 Timers 0 and 1 can be configured to automatically toggle a port 10 bits are transmitted (through TxD) or received (through RxD): a output whenever a timer overflow occurs. The same device pins that start bit (logical 0), 8 data bits (LSB first), and a stop bit (logical 1). are used for the T0 and T1 count inputs are also used for the timer When data is received, the stop bit is stored in RB8 in Special toggle outputs. This function is enabled by control bits T0OE and Function Register SCON. The baud rate is variable and is T1OE in the P2M1 register, and apply to Timer 0 and Timer 1 determined by the Timer 1 overflow rate. respectively. The port outputs will be a logic 1 prior to the first timer Mode 2 overflow when this mode is turned on. 11 bits are transmitted (through TxD) or received (through RxD): UART start bit (logical 0), 8 data bits (LSB first), a programmable 9th data The 87LPC762 includes an enhanced 80C51 UART. The baud rate bit, and a stop bit (logical 1). When data is transmitted, the 9th data source for the UART is timer 1 for modes 1 and 3, while the rate is bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for fixed in modes 0 and 2. Because CPU clocking is different on the example, the parity bit (P, in the PSW) could be moved into TB8. 87LPC762 than on the standard 80C51, baud rate calculation is When data is received, the 9th data bit goes into RB8 in Special somewhat different. Enhancements over the standard 80C51 UART Function Register SCON, while the stop bit is ignored. The baud include Framing Error detection and automatic address recognition. rate is programmable to either 1/16 or 1/32 of the CPU clock frequency, as determined by the SMOD1 bit in PCON. The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can Mode 3 commence reception of a second byte before a previously received 11 bits are transmitted (through TxD) or received (through RxD): a byte has been read from the SBUF register. However, if the first byte start bit (logical 0), 8 data bits (LSB first), a programmable 9th data still hasn’t been read by the time reception of the second byte is bit, and a stop bit (logical 1). In fact, Mode 3 is the same as Mode 2 complete, the first byte will be lost. The serial port receive and in all respects except baud rate. The baud rate in Mode 3 is variable transmit registers are both accessed through Special Function and is determined by the Timer 1 overflow rate. Register SBUF. Writing to SBUF loads the transmit register, and In all four modes, transmission is initiated by any instruction that reading SBUF accesses a physically separate receive register. uses SBUF as a destination register. Reception is initiated in Mode 0 The serial port can be operated in 4 modes: by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. Mode 0 Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted or received, LSB first. The baud rate is fixed at 1/6 of the CPU clock frequency. 2001 Oct 26 31

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP Serial Port Control Register (SCON) with the SM0 bit. Which bit appears in SCON at any particular time The serial port control and status register is the Special Function is determined by the SMOD0 bit in the PCON register. If SMOD0 = Register SCON, shown in Figure 28. This register contains not only 0, SCON.7 is the SM0 bit. If SMOD0 = 1, SCON.7 is the FE bit. the mode selection bits, but also the 9th data bit for transmit and Once set, the FE bit remains set until it is cleared by software. This receive (TB8 and RB8), and the serial port interrupt bits (TI and RI). allows detection of framing errors for a group of characters without the need for monitoring it for every character individually. The Framing Error bit (FE) allows detection of missing stop bits in the received data stream. The FE bit shares the bit position SCON.7 SCON Address: 98h Reset Value: 00h Bit Addressable 7 6 5 4 3 2 1 0 SM0/FE SM1 SM2 REN TB8 RB8 TI RI BIT SYMBOL FUNCTION SCON.7 FE Framing Error. This bit is set by the UART receiver when an invalid stop bit is detected. Must be cleared by software. The SMOD0 bit in the PCON register must be 1 for this bit to be accessible. See SM0 bit below. SCON.7 SM0 With SM1, defines the serial port mode. The SMOD0 bit in the PCON register must be 0 for this bit to be accessible. See FE bit above. SCON. 6 SM1 With SM0, defines the serial port mode (see table below). SM0, SM1 UART Mode Baud Rate 0 0 0: shift register CPU clock/6 0 1 1: 8-bit UART Variable (see text) 1 0 2: 9-bit UART CPU clock/32 or CPU clock/16 1 1 3: 9-bit UART Variable (see text) SCON.5 SM2 Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1, then Rl will not be activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2=1 then RI will not be activated if a valid stop bit was not received. In Mode 0, SM2 should be 0. SCON.4 REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. SCON.3 TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. SCON.2 RB8 In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, it SM2=0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. SCON.1 TI Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. SCON.0 RI Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. SU01157 Figure 28. Serial Port Control Register (SCON) 2001 Oct 26 32

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP Baud Rates application. The Timer itself can be configured for either “timer” or The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = CPU clock/6. “counter” operation, and in any of its 3 running modes. In the most The baud rate in Mode 2 depends on the value of bit SMOD1 in typical applications, it is configured for “timer” operation, in the Special Function Register PCON. If SMOD1 = 0 (which is the value auto-reload mode (high nibble of TMOD = 0010b). In that case the on reset), the baud rate is 1/32 of the CPU clock frequency. If baud rate is given by the formula: SMOD1 = 1, the baud rate is 1/16 of the CPU clock frequency. CPU clock frequency(cid:3) Mode 2 Baud Rate (cid:2) 1 (cid:0) SMOD1 x CPU clock frequency 192 (or 96 if SMOD1 (cid:2) 1) 32 Mode 1, 3 Baud Rate (cid:2) 256 (cid:1) (TH1) Using Timer 1 to Generate Baud Rates When Timer 1 is used as the baud rate generator, the baud rates in Tables 6 and 7 list various commonly used baud rates and how they Modes 1 and 3 are determined by the Timer 1 overflow rate and the can be obtained using Timer 1 as the baud rate generator. value of SMOD1. The Timer 1 interrupt should be disabled in this Table 9. Baud Rates, Timer Values, and CPU Clock Frequencies for SMOD1 = 0 Baud Rate TTiimmeerr CCoounntt 2400 4800 9600 19.2k 38.4k 57.6k –1 0.4608 0.9216 * 1.8432 * 3.6864 * 7.3728 * 11.0592 –2 0.9216 1.8432 * 3.6864 * 7.3728 * 14.7456 –3 1.3824 2.7648 5.5296 * 11.0592 – – –4 * 1.8432 * 3.6864 * 7.3728 * 14.7456 – – –5 2.3040 4.6080 9.2160 * 18.4320 – – –6 2.7648 5.5296 * 11.0592 – – – –7 3.2256 6.4512 12.9024 – – – –8 * 3.6864 * 7.3728 * 14.7456 – – – –9 4.1472 8.2944 16.5888 – – – –10 4.6080 9.2160 * 18.4320 – – – 2001 Oct 26 33

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP Table 10. Baud Rates, Timer Values, and CPU Clock Frequencies for SMOD1 = 1 Baud Rate TTiimmeerr CCoounntt 2400 4800 9600 19.2 k 38.4 k 57.6 k 115.2 k –1 0.2304 0.4608 0.9216 * 1.8432 * 3.6864 5.5296 * 11.0592 –2 0.4608 0.9216 * 1.8432 * 3.6864 * 7.3728 * 11.0592 – –3 0.6912 1.3824 2.7648 5.5296 * 11.0592 16.5888 – –4 0.9216 * 1.8432 * 3.6864 * 7.3728 * 14.7456 – – –5 1.1520 2.3040 4.6080 9.2160 * 18.4320 – – –6 1.3824 2.7648 5.5296 * 11.0592 – – – –7 1.6128 3.2256 6.4512 12.9024 – – – –8 * 1.8432 * 3.6864 * 7.3728 * 14.7456 – – – –9 2.0736 4.1472 8.2944 16.5888 – – – –10 2.3040 4.6080 9.2160 * 18.4320 – – – –11 2.5344 5.0688 10.1376 – – – – –12 2.7648 5.5296 * 11.0592 – – – – –13 2.9952 5.9904 11.9808 – – – – –14 3.2256 6.4512 12.9024 – – – – –15 3.4560 6.9120 13.8240 – – – – –16 * 3.6864 * 7.3728 * 14.7456 – – – – –17 3.9168 7.8336 15.6672 – – – – –18 4.1472 8.2944 16.5888 – – – – –19 4.3776 8.7552 17.5104 – – – – –20 4.6080 9.2160 * 18.4320 – – – – –21 4.8384 9.6768 19.3536 – – – – NOTES TO TABLES 9 AND 10: 1. Tables 9 and 10 apply to UART modes 1 and 3 (variable rate modes), and show CPU clock rates in MHz for standard baud rates from 2400 to 115.2k baud. 2. Table 9 shows timer settings and CPU clock rates with the SMOD1 bit in the PCON register = 0 (the default after reset), while Table 10 reflects the SMOD1 bit = 1. 3. The tables show all potential CPU clock frequencies up to 20 MHz that may be used for baud rates from 9600 baud to 115.2 k baud. Other CPU clock frequencies that would give only lower baud rates are not shown. 4. Table entries marked with an asterisk (*) indicate standard crystal and ceramic resonator frequencies that may be obtained from many sources without special ordering. 2001 Oct 26 34

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP More About UART Mode 0 More About UART Mode 1 Serial data enters and exits through RxD. TxD outputs the shift Ten bits are transmitted (through TxD), or received (through RxD): a clock. 8 bits are transmitted/received: 8 data bits (LSB first). The start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the baud rate is fixed at 1/6 the CPU clock frequency. Figure 29 shows stop bit goes into RB8 in SCON. In the 87LPC762 the baud rate is a simplified functional diagram of the serial port in Mode 0, and determined by the Timer 1 overflow rate. Figure 30 shows a associated timing. simplified functional diagram of the serial port in Mode 1, and associated timings for transmit receive. Transmission is initiated by any instruction that uses SBUF as a destination register. The “write to SBUF” signal at S6P2 also loads a Transmission is initiated by any instruction that uses SBUF as a 1 into the 9th position of the transmit shift register and tells the TX destination register. The “write to SBUF” signal also loads a 1 into Control block to commence a transmission. The internal timing is the 9th bit position of the transmit shift register and flags the TX such that one full machine cycle will elapse between “write to SBUF” Control unit that a transmission is requested. Transmission actually and activation of SEND. commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to SEND enables the output of the shift register to the alternate output the divide-by-16 counter, not to the “write to SBUF” signal.) function line of P1.1 and also enable SHIFT CLOCK to the alternate output function line of P1.0. SHIFT CLOCK is low during S3, S4, and The transmission begins with activation of SEND which puts the S5 of every machine cycle, and high during S6, S1, and S2. At start bit at TxD. One bit time later, DATA is activated, which enables S6P2 of every machine cycle in which SEND is active, the contents the output bit of the transmit shift register to TxD. The first shift pulse of the transmit shift are shifted to the right one position. occurs one bit time after that. As data bits shift out to the right, zeros come in from the left. When As data bits shift out to the right, zeros are clocked in from the left. the MSB of the data byte is at the output position of the shift register, When the MSB of the data byte is at the output position of the shift then the 1 that was initially loaded into the 9th position, is just to the register, then the 1 that was initially loaded into the 9th position is left of the MSB, and all positions to the left of that contain zeros. This just to the left of the MSB, and all positions to the left of that contain condition flags the TX Control block to do one last shift and then zeros. This condition flags the TX Control unit to do one last shift deactivate SEND and set T1. Both of these actions occur at S1P1 of and then deactivate SEND and set TI. This occurs at the 10th the 10th machine cycle after “write to SBUF.” Reception is initiated by divide-by-16 rollover after “write to SBUF.” the condition REN = 1 and R1 = 0. At S6P2 of the next machine Reception is initiated by a detected 1-to-0 transition at RxD. For this cycle, the RX Control unit writes the bits 11111110 t o the receive shift purpose RxD is sampled at a rate of 16 times whatever baud rate register, and in the next clock phase activates RECEIVE. has been established. When a transition is detected, the RECEIVE enable SHIFT CLOCK to the alternate output function line divide-by-16 counter is immediately reset, and 1FFH is written into of P1.0. SHIFT CLOCK makes transitions at S3P1 and S6P1 of every the input shift register. Resetting the divide-by-16 counter aligns its machine cycle. At S6P2 of every machine cycle in which RECEIVE is rollovers with the boundaries of the incoming bit times. active, the contents of the receive shift register are shifted to the left The 16 states of the counter divide each bit time into 16ths. At the one position. The value that comes in from the right is the value that 7th, 8th, and 9th counter states of each bit time, the bit detector was sampled at the P1.1 pin at S5P2 of the same machine cycle. samples the value of RxD. The value accepted is the value that was As data bits come in from the right, 1s shift out to the left. When the 0 seen in at least 2 of the 3 samples. This is done for noise rejection. that was initially loaded into the rightmost position arrives at the If the value accepted during the first bit time is not 0, the receive leftmost position in the shift register, it flags the RX Control block to do circuits are reset and the unit goes back to looking for another 1-to-0 one last shift and load SBUF. At S1P1 of the 10th machine cycle after transition. This is to provide rejection of false start bits. If the start bit the write to SCON that cleared RI, RECEIVE is cleared as RI is set. proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in mode 1 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated.: 1. R1 = 0, and 2. Either SM2 = 0, or the received stop bit = 1. If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At this time, whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in RxD. 2001 Oct 26 35

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP 80C51 INTERNAL BUS WRITE TO SBUF D S RxD Q SBUF P1.1 ALT OUTPUT CL FUNCTION ZERO DETECTOR START SHIFT TX CONTROL TxD S6 TX CLOCK TI SEND P1.0 ALT OUTPUT SERIAL PORT FUNCTION INTERRUPT SHIFT TX CLOCK RI RECEIVE CLOCK REN RX CONTROL START SHIFT RI 1 1 1 1 1 1 1 0 RXD P1.1 ALT INPUT SHIFT REGISTER INPUT FUNCTION LOAD SBUF SBUF READ SBUF 80C51 INTERNAL BUS S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 WRITE TO SBUF SEND SHIFT TRANSMIT RXD (DATA OUT) D0 D1 D2 D3 D4 D5 D6 D7 TXD (SHIFT CLOCK) TI WRITE TO SCON (CLEAR RI) RI RECEIVE RECEIVE SHIFT RxD (DATA IN) D0 D1 D2 D3 D4 D5 D6 D7 TxD (SHIFT CLOCK) SU01178 Figure 29. Serial Port Mode 0 2001 Oct 26 36

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP 80C51 INTERNAL BUS TB8 WRITE TO SBUF D S OVTEIMREFRL O1W Q SBUF P1T.0x DALT CL OUTPUT FUNCTION ÷2 ZERO DETECTOR SMOD1 = 0 SMOD1 = 1 START SHIFT TX CONTROL DATA ÷16 TX CLOCK TI SEND ÷16 SIENRTEIARLR PUOPRTT RX RI LOAD SBUF CLOCK 1-TO-0 TRANSITION START RX CONTROL SHIFT DETECTOR 1FFH BIT INPUT SHIFT REGISTER DETECTOR RxD LOAD P1.1 ALT SBUF INPUT FUNCTION SBUF READ SBUF 80C51 INTERNAL BUS TX CLOCK WRITE TO SBUF SEND DATA TRANSMIT SHIFT START TxD BIT D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT TI RX CLOCK START RxD ÷ 16 RESET BIT D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT BIT DETECTOR SAMPLE TIMES RECEIVE SHIFT RI SU01179 Figure 30. Serial Port Mode 1 2001 Oct 26 37

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP More About UART Modes 2 and 3 proves valid, it is shifted into the input shift register, and reception of Eleven bits are transmitted (through TxD), or received (through the rest of the frame will proceed. RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data As data bits come in from the right, 1s shift out to the left. When the bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be start bit arrives at the leftmost position in the shift register (which in assigned the value of 0 or 1. On receive, the 9the data bit goes into Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do RB8 in SCON. The baud rate is programmable to either 1/16 or 1/32 one last shift, load SBUF and RB8, and set RI. of the CPU clock frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer 1. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final Figures 31 and 32 show a functional diagram of the serial port in shift pulse is generated. 1. RI = 0, and 2. Either SM2 = 0, or the Modes 2 and 3. The receive portion is exactly the same as in Mode 1. received 9th data bit = 1. The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register. If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the Transmission is initiated by any instruction that uses SBUF as a received 9th data bit goes into RB8, and the first 8 data bits go into destination register. The “write to SBUF” signal also loads TB8 into SBUF. One bit time later, whether the above conditions were met the 9th bit position of the transmit shift register and flags the TX or not, the unit goes back to looking for a 1-to-0 transition at the Control unit that a transmission is requested. Transmission RxD input. commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to Multiprocessor Communications the divide-by-16 counter, not to the “write to SBUF” signal.) UART modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received or The transmission begins with activation of SEND, which puts the transmitted. When data is received, the 9th bit is stored in RB8. The start bit at TxD. One bit time later, DATA is activated, which enables UART can be programmed such that when the stop bit is received, the output bit of the transmit shift register to TxD. The first shift pulse the serial port interrupt will be activated only if RB8 = 1. This feature occurs one bit time after that. The first shift clocks a 1 (the stop bit) is enabled by setting bit SM2 in SCON. One way to use this feature into the 9th bit position of the shift register. Thereafter, only zeros in multiprocessor systems is as follows: are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When TB8 is at the output position of the When the master processor wants to transmit a block of data to one shift register, then the stop bit is just to the left of TB8, and all of several slaves, it first sends out an address byte which identifies positions to the left of that contain zeros. This condition flags the TX the target slave. An address byte differs from a data byte in that the Control unit to do one last shift and then deactivate SEND and set 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no TI. This occurs at the 11th divide-by-16 rollover after “write to SBUF.” slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received Reception is initiated by a detected 1-to-0 transition at RxD. For this byte and see if it is being addressed. The addressed slave will clear purpose RxD is sampled at a rate of 16 times whatever baud rate its SM2 bit and prepare to receive the data bytes that follow. The has been established. When a transition is detected, the slaves that weren’t being addressed leave their SM2 bits set and go divide-by-16 counter is immediately reset, and 1FFH is written to the on about their business, ignoring the subsequent data bytes. input shift register. SM2 has no effect in Mode 0, and in Mode 1 can be used to check At the 7th, 8th, and 9th counter states of each bit time, the bit the validity of the stop bit, although this is better done with the detector samples the value of R–D. The value accepted is the value Framing Error flag. In a Mode 1 reception, if SM2 = 1, the receive that was seen in at least 2 of the 3 samples. If the value accepted interrupt will not be activated unless a valid stop bit is received. during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. If the start bit 2001 Oct 26 38

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP 80C51 INTERNAL BUS TB8 WRITE TO SBUF PHASE 2 CLOCK D S (1/2 fOSC) Q SBUF TxD CL P1.0 ALT OUTPUT FUNCTION ÷2 ZERO DETECTOR SMOD1 = 0 SMOD1 = 1 START STOP BIT GEN. SHIFT TX CONTROL DATA ÷16 TX CLOCK TI SEND ÷16 SERIAL PORT INTERRUPT RX RI LOAD SBUF CLOCK 1-TO-0 TRANSITION START RX CONTROL SHIFT DETECTOR 1FFH BIT DETECTOR INPUT SHIFT REGISTER RxD LOAD P1.1 ALT SBUF INPUT FUNCTION SBUF READ SBUF 80C51 INTERNAL BUS TX CLOCK WRITE TO SBUF SEND DATA TRANSMIT SHIFT TxD STBAITRT D0 D1 D2 D3 D4 D5 D6 D7 TB8 STOP BIT TI STOP BIT GEN. RX CLOCK START RxD ÷ 16 RESET BIT D0 D1 D2 D3 D4 D5 D6 D7 RB8 STOP BIT BIT DETECTOR SAMPLE TIMES RECEIVE SHIFT RI SU01180 Figure 31. Serial Port Mode 2 2001 Oct 26 39

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP 80C51 INTERNAL BUS TB8 WRITE TO SBUF D S OVTEIMREFRLO 1W Q SBUF TPx1D.0 ALT CL OUTPUT FUNCTION ÷2 ZERO DETECTOR SMOD1 = 0 SMOD1 = 1 START SHIFT TX CONTROL DATA ÷16 TX CLOCK TI SEND ÷16 SERIAL PORT INTERRUPT RX RI LOAD SBUF CLOCK 1-TO-0 TRANSITION START RX CONTROL SHIFT DETECTOR 1FFH BIT INPUT SHIFT REGISTER DETECTOR RxD LOAD P1.1 ALT SBUF INPUT FUNCTION SBUF READ SBUF 80C51 INTERNAL BUS TX CLOCK WRITE TO SBUF SEND DATA TRANSMIT SHIFT TxD STBAITRT D0 D1 D2 D3 D4 D5 D6 D7 TB8 STOP BIT TI STOP BIT GEN. RX CLOCK START RxD ÷ 16 RESET BIT D0 D1 D2 D3 D4 D5 D6 D7 RB8 STOP BIT BIT DETECTOR SAMPLE TIMES RECEIVE SHIFT RI SU01181 Figure 32. Serial Port Mode 3 2001 Oct 26 40

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP Automatic Address Recognition will be FF hexadecimal. Upon reset SADDR and SADEN are loaded Automatic Address Recognition is a feature which allows the UART with 0s. This produces a given address of all “don’t cares” as well as to recognize certain addresses in the serial bit stream by using a Broadcast address of all “don’t cares”. This effectively disables the hardware to make the comparisons. This feature saves a great deal Automatic Addressing mode and allows the microcontroller to use of software overhead by eliminating the need for the software to standard UART drivers which do not make use of this feature. examine every serial address which passes by the serial port. This Watchdog Timer feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be When enabled via the WDTE configuration bit, the watchdog timer is automatically set when the received byte contains either the “Given” operated from an independent, fully on-chip oscillator in order to address or the “Broadcast” address. The 9 bit mode requires that provide the greatest possible dependability. When the watchdog the 9th information bit is a 1 to indicate that the received information feature is enabled, the timer must be fed regularly by software in is an address and not data. order to prevent it from resetting the CPU, and it cannot be turned off. When disabled as a watchdog timer (via the WDTE bit in the UCFG1 Using the Automatic Address Recognition feature allows a master to configuration register), it may be used as an interval timer and may selectively communicate with one or more slaves by invoking the generate an interrupt. The watchdog timer is shown in Figure 33. Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function The watchdog timeout time is selectable from one of eight values, Registers are used to define the slave’s address, SADDR, and the nominal times range from 25 milliseconds to 3.2 seconds. The address mask, SADEN. SADEN is used to define which bits in the frequency tolerance of the independent watchdog RC oscillator is SADDR are to be used and which bits are “don’t care”. The SADEN ±60%. The timeout selections and other control bits are shown in mask can be logically ANDed with the SADDR to create the “Given” Figure 34. When the watchdog function is enabled, the WDCON address which the master will use for addressing each of the slaves. register may be written once during chip initialization in order to set Use of the Given address allows multiple slaves to be recognized the watchdog timeout time. The recommended method of initializing while excluding others. The following examples will help to show the the WDCON register is to first feed the watchdog, then write to versatility of this scheme: WDCON to configure the WDS2–0 bits. Using this method, the watchdog initialization may be done any time within 10 milliseconds Slave 0 SADDR = 1100 0000 after startup without a watchdog overflow occurring before the SADEN = 1111 1101 initialization can be completed. Given = 1100 00X0 Since the watchdog timer oscillator is fully on-chip and independent Slave 1 SADDR = 1100 0000 of any external oscillator circuit used by the CPU, it intrinsically SADEN = 1111 1110 serves as an oscillator fail detection function. If the watchdog feature Given = 1100 000X is enabled and the CPU oscillator fails for any reason, the watchdog In the above example SADDR is the same and the SADEN data is timer will time out and reset the CPU. used to differentiate between the two slaves. Slave 0 requires a 0 in When the watchdog function is enabled, the timer is deactivated bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is temporarily when a chip reset occurs from another source, such as ignored. A unique address for Slave 0 would be 1100 0010 since a power on reset, brownout reset, or external reset. slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be Watchdog Feed Sequence selected at the same time by an address which has bit 0 = 0 (for If the watchdog timer is running, it must be fed before it times out in slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed order to prevent a chip reset from occurring. The watchdog feed with 1100 0000. sequence consists of first writing the value 1Eh, then the value E1h In a more complex system the following could be used to select to the WDRST register. An example of a watchdog feed sequence is slaves 1 and 2 while excluding slave 0: shown below. Slave 0 SADDR = 1100 0000 WDFeed: mov WDRST,#1eh ; First part of watchdog feed sequence. SADEN = 1111 1001 mov WDRST,#0e1h ; Second part of watchdog feed sequence. Given = 1100 0XX0 The two writes to WDRST do not have to occur in consecutive Slave 1 SADDR = 1110 0000 instructions. An incorrect watchdog feed sequence does not cause SADEN = 1111 1010 any immediate response from the watchdog timer, which will still Given = 1110 0X0X time out at the originally scheduled time if a correct feed sequence Slave 2 SADDR = 1110 0000 does not occur prior to that time. SADEN = 1111 1100 After a chip reset, the user program has a limited time in which to Given = 1110 00XX either feed the watchdog timer or change the timeout period. When In the above example the differentiation among the 3 slaves is in the a low CPU clock frequency is used in the application, the number of lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be instructions that can be executed before the watchdog overflows uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and may be quite small. it can be uniquely addressed by 1110 and 0101. Slave 2 requires Watchdog Reset that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 If a watchdog reset occurs, the internal reset is active for and 1 and exclude Slave 2 use address 1110 0100, since it is approximately one microsecond. If the CPU clock was still running, necessary to make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR code execution will begin immediately after that. If the processor and SADEN. Zeros in this result are treated as don’t-cares. In most was in Power Down mode, the watchdog reset will start the oscillator cases, interpreting the don’t-cares as ones, the broadcast address and code execution will resume after the oscillator is stable. 2001 Oct 26 41

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP 500 kHz R/C OSCILLATOR CLOCK OUT ENABLE (WWDCDOSN2–.20–0) 8 TO 1 MUX WATCHDOG RESET WDCLK * WDTE STATE CLOCK 8 MSBs WATCHDOG INTERRUPT 20-BIT COUNTER WDTE + WDRUN CLEAR WDTE (UCFG1.7) WATCHDOG FEED DETECT S WDOVF Q (WDCON.5) BOD (xxx.x) R POR (xxx.x) SU01182 Figure 33. Block Diagram of the Watchdog Timer WDCON Address: A7h Reset Value: (cid:0) 30h for a watchdog reset. Not Bit Addressable (cid:0) 10h for other rest sources if the watchdog is enabled via the WDTE configuration bit. (cid:0) 00h for other reset sources if the watchdog is disabled via the WDTE configuration bit. 7 6 5 4 3 2 1 0 — — WDOVF WDRUN WDCLK WDS2 WDS1 WDS0 BIT SYMBOL FUNCTION WDCON.7, 6 — Reserved for future use. Should not be set to 1 by user programs. WDCON.5 WDOVF Watchdog timer overflow flag. Set when a watchdog reset or timer overflow occurs. Cleared when the watchdog is fed. WDCON.4 WDRUN Watchdog run control. The watchdog timer is started when WDRUN = 1 and stopped when WDRUN = 0. This bit is forced to 1 (watchdog running) if the WDTE configuration bit = 1. WDCON.3 WDCLK Watchdog clock select. The watchdog timer is clocked by CPU clock/6 when WDCLK = 1 and by the watchdog RC oscillator when WDCLK = 0. This bit is forced to 0 (using the watchdog RC oscillator) if the WDTE configuration bit = 1. WDCON.2–0 WDS2–0 Watchdog rate select. WDS2–0 Timeout Clocks Minimum Time Nominal Time Maximum Time 0 0 0 8,192 10 ms 25 ms 40 ms 0 0 1 16,384 20 ms 50 ms 80 ms 0 1 0 32,768 41 ms 100 ms 160 ms 0 1 1 65,536 82 ms 200 ms 320 ms 1 0 0 131,072 165 ms 400 ms 640 ms 1 0 1 262,144 330 ms 800 ms 1280 ms 1 1 0 524,288 660 ms 1.60 sec 2.60 sec 1 1 1 1,048,576 1.3 sec 3.20 sec 5.30 sec SU01476 Figure 34. Watchdog Timer Control Register (WDCON) 2001 Oct 26 42

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP Additional Features • MOV DPTR, #data16 Load the Data Pointer with a 16-bit The AUXR1 register contains several special purpose control bits that constant. relate to several chip features. AUXR1 is described in Figure 35. • MOVCA, @A+DPTR Move code byte relative to DPTR to the Software Reset accumulator. The SRST bit in AUXR1 allows software the opportunity to reset the • MOVX A, @DPTR Move data byte the accumulator to data processor completely, as if an external reset or watchdog reset had occurred. If a value is written to AUXR1 that contains a 1 at bit memory relative to DPTR. • position 3, all SFRs will be initialized and execution will resume at MOVX @DPTR, A Move data byte from data memory program address 0000. Care should be taken when writing to relative to DPTR to the accumulator. AUXR1 to avoid accidental software resets. Also, any instruction that reads or manipulates the DPH and DPL Dual Data Pointers registers (the upper and lower bytes of the current DPTR) will be The dual Data Pointer (DPTR) adds to the ways in which the affected by the setting of DPS. The MOVX instructions have limited processor can specify the address used with certain instructions. application for the 87LPC762 since the part does not have an The DPS bit in the AUXR1 register selects one of the two Data external data bus. However, they may be used to access EPROM Pointers. The DPTR that is not currently selected is not accessible configuration information (see EPROM Characteristics section). to software unless the DPS bit is toggled. Bit 2 of AUXR1 is permanently wired as a logic 0. This is so that the Specific instructions affected by the Data Pointer selection are: DPS bit may be toggled (thereby switching Data Pointers) simply by • INC DPTR Increments the Data Pointer by 1. incrementing the AUXR1 register, without the possibility of • inadvertently altering other bits in the register. JMP @A+DPTR Jump indirect relative to DPTR value. AUXR1 Address: A2h Reset Value: 00h Not Bit Addressable 7 6 5 4 3 2 1 0 KBF BOD BOI LPEP SRST 0 — DPS BIT SYMBOL FUNCTION AUXR1.7 KBF Keyboard Interrupt Flag. Set when any pin of port 0 that is enabled for the Keyboard Interrupt function goes low. Must be cleared by software. AUXR1.6 BOD Brown Out Disable. When set, turns off brownout detection and saves power. See Power Monitoring Functions section for details. AUXR1.5 BOI Brown Out Interrupt. When set, prevents brownout detection from causing a chip reset and allows the brownout detect function to be used as an interrupt. See the Power Monitoring Functions section for details. AUXR1.4 LPEP Low Power EPROM control bit. Allows power savings in low voltage systems. Set by software. Can only be cleared by power-on or brownout reset. See the Power Reduction Modes section for details. AUXR1.3 SRST Software Reset. When set by software, resets the 87LPC762 as if a hardware reset occurred. AUXR1.2 — This bit contains a hard-wired 0. Allows toggling of the DPS bit by incrementing AUXR1, without interfering with other bits in the register. AUXR1.1 — Reserved for future use. Should not be set to 1 by user programs. AUXR1.0 DPS Data Pointer Select. Chooses one of two Data Pointers for use by the program. See text for details. SU01223 Figure 35. AUXR1 Register 2001 Oct 26 43

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP EPROM Characteristics 32-Byte Customer Code Space Programming of the EPROM on the 87LPC762 is accomplished with A small supplemental EPROM space is reserved for use by the a serial programming method. Commands, addresses, and data are customer in order to identify code revisions, store checksums, add a transmitted to and from the device on two pins after programming serial number to each device, or any other desired use. This area mode is entered. Serial programming allows easy implementation of exists in the code memory space from addresses FCE0h through in-circuit programming of the 87LPC762 in an application board. FCFFh. Code execution from this space is not supported, but it may be read as data through the use of the MOVC instruction with the The 87LPC762 contains three signature bytes that can be read and appropriate addresses. The memory may be programmed at the used by an EPROM programming system to identify the device. The same time as the rest of the code memory and UCFG bytes are signature bytes designate the device as an 87LPC762 manufactured programmed. by Philips. The signature bytes may be read by the user program at addresses FC30h, FC31h and FC60h with the MOVC instruction, System Configuration Bytes using the DPTR register for addressing. A number of user configurable features of the 87LPC762 must be defined at power up and therefore cannot be set by the program after A special user data area is also available for access via the MOVC start of execution. Those features are configured through the use of instruction at addresses FCE0h through FCFFh. This “customer two EPROM bytes that are programmed in the same manner as the code” space is programmed in the same manner as the main code EPROM program space. The contents of the two configuration bytes, EPROM and may be used to store a serial number, manufacturing UCFG1 and UCFG2, are shown in Figures 36 and 37. The values of date, or other application information. these bytes may be read by the program through the use of the MOVX instruction at the addresses shown in the figure. UCFG1 Address: FD00h Unprogrammed Value: FFh 7 6 5 4 3 2 1 0 WDTE RPD PRHI BOV CLKR FOSC2 FOSC1 FOSC0 BIT SYMBOL FUNCTION UCFG1.7 WDTE Watchdog timer enable. When programmed (0), disables the watchdog timer. The timer may still be used to generate an interrupt. UCFG1.6 RPD Reset pin disable. When 1 disables the reset function of pin P1.5, allowing it to be used as an input only port pin. UCFG1.5 PRHI Port reset high. When 1, ports reset to a high state. When 0, ports reset to a low state. UCFG1.4 BOV Brownout voltage select. When 1, the brownout detect voltage is 2.5V. When 0, the brownout detect voltage is 3.8V. This is described in the Power Monitoring Functions section. UCFG1.3 CLKR Clock rate select. When 0, the CPU clock rate is divided by 2. This results in machine cycles taking 12 CPU clocks to complete as in the standard 80C51. For full backward compatibility, this division applies to peripheral timing as well. UCFG1.2–0 FOSC2–FSOC0 CPU oscillator type select. See Oscillator section for additional information. Combinations other than those shown below should not be used. They are reserved for future use. FOSC2–FOSC0 Oscillator Configuration 1 1 1 External clock input on X1 (default setting for an unprogrammed part). 0 1 1 Internal RC oscillator, 6 MHz. For tolerance, see AC Electrical Characteristics table. 0 1 0 Low frequency crystal, 20 kHz to 100 kHz. 0 0 1 Medium frequency crystal or resonator, 100 kHz to 4 MHz. 0 0 0 High frequency crystal or resonator, 4 MHz to 20 MHz. SU01477 Figure 36. EPROM System Configuration Byte 1 (UCFG1) 2001 Oct 26 44

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP UCFG2 Address: FD01h Unprogrammed Value: FFh 7 6 5 4 3 2 1 0 SB2 SB1 — — — — — — BIT SYMBOL FUNCTION UCFG2.7, 6 SB2, SB1 EPROM security bits. See table entitled, “EPROM Security Bits” for details. UCFG2.5–0 — Reserved for future use. SU01186 Figure 37. EPROM System Configuration Byte 2 (UCFG2) Security Bits When neither of the security bits are programmed, the code in the EPROM can be verified. When only security bit 1 is programmed, all further programming of the EPROM is disabled. At that point, only security bit 2 may still be programmed. When both security bits are programmed, EPROM verify is also disabled. Table 11. EPROM Security Bits SB2 SB1 Protection Description 1 1 Both security bits unprogrammed. No program security features enabled. EPROM is programmable and verifiable. 1 0 Only security bit 1 programmed. Further EPROM programming is disabled. Security bit 2 may still be programmed. 0 1 Only security bit 2 programmed. This combination is not supported. 0 0 Both security bits programmed. All EPROM verification and programming are disabled. ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNIT Operating temperature under bias –55 to +125 °C Storage temperature range –65 to +150 °C Voltage on RST/VPP pin to VSS 0 to +11.0 V Voltage on any other pin to VSS –0.5 to VDD+0.5V V Maximum IOL per I/O pin 20 mA Power dissipation (based on package heat transfer, not device power consumption) 1.5 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification are not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 2001 Oct 26 45

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP DC ELECTRICAL CHARACTERISTICS VDD = 2.7 V to 6.0 V unless otherwise specified; Tamb = 0°C to +70°C or –40°C to +85°C, unless otherwise specified. LIMITS SSYYMMBBOOLL PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP1 MAX 5.0 V, 20 MHz11 15 25 mA IIDD PPoowweerr ssuuppppllyy ccuurrrreenntt, ooppeerraattiinngg 3.0 V, 10 MHz11 4 7 mA 5.0 V, 20 MHz11 6 10 mA IIID PPoowweerr ssuuppppllyy ccuurrrreenntt, IIddllee mmooddee 3.0 V, 10 MHz11 2 4 mA 5.0 V11 1 10 m A IIPD PPoowweerr ssuuppppllyy ccuurrrreenntt, PPoowweerr DDoowwnn mmooddee 3.0 V11 1 5 m A VRAM RAM keep-alive voltage 1.5 V 4.0 V < VDD < 6.0 V –0.5 0.2 VDD–0.1 V VVIL IInnppuutt llooww vvoollttaaggee ((TTTTLL iinnppuutt)) 2.7 V < VDD < 4.0 V –0.5 0.7 V VIL1 Negative going threshold (Schmitt input) –0.5 0.3 VDD V VIH Input high voltage (TTL input) 0.2 VDD+0.9 VDD+0.5 V VIH1 Positive going threshold (Schmitt input) 0.7VDD VDD+0.5 V HYS Hysteresis voltage 0.2 VDD V VOL Output low voltage all ports5, 9 IOL = 3.2 mA, VDD = 2.7 V 0.4 V VOL1 Output low voltage all ports5, 9 IOL = 20 mA, VDD = 2.7 V 1.0 V VVOOH OOuuttppuutt hhiigghh vvoollttaaggee, aallll ppoorrttss33 IIOOHH == ––2300 mm AA,, VVDDDD == 24..75 VV VVDDDD––00..77 VV VOH1 Output high voltage, all ports4 IOH = –1.0 mA, VDD = 2.7 V VDD–0.7 V CIO Input/Output pin capacitance10 15 pF IIL Logical 0 input current, all ports8 VIN = 0.4 V –50 m A ILI Input leakage current, all ports7 VIN = VIL or VIH ±2 m A IITL LLooggiiccaall 11 ttoo 00 ttrraannssiittiioonn ccuurrrreenntt, aallll ppoorrttss33,, 66 VVIINN == 12..50 VV aatt VVDDDD == 35..05 VV ––13500 ––265500 mm AA RRST Internal reset pull-up resistor 40 225 kW VBOLOW Brownout trip voltage with BOV = 112 2.35 2.69 V VBOHI Brownout trip voltage with BOV = 0 3.45 3.99 V VREF Reference voltage 1.11 1.26 1.41 V tC (VREF) Temperature coefficient tbd ppm/°C SS Supply sensitivity tbd %/V NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V. 2. See other Figures for details. Active mode: ICC(MAX) = tbd; Idle mode: ICC(MAX) = tbd 3. Ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups). Does not apply to open drain pins. 4. Ports in PUSH-PULL mode. Does not apply to open drain pins. 5. In all output modes except high impedance mode. 6. Port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. This current is highest when VIN is approximately 2 V. 7. Measured with port in high impedance mode. 8. Measured with port in quasi-bidirectional mode. 9. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 20 mA Maximum total IOL for all outputs: 80 mA Maximum total IOH for all outputs: 5 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 10.Pin capacitance is characterized but not tested. 11.The IDD, IID, and IPD specifications are measured using an external clock with the following functions disabled: comparators, brownout detect, and watchdog timer. For VDD = 3 V, LPEP = 1. Refer to the appropriate figures on the following pages for additional current drawn by each of these functions and detailed graphs for other frequency and voltage combinations. 12.Devices initially operating at VDD = 2.7 V or above, and at fOSC = 10 MHz or less, are guaranteed to continue to execute instructions correctly at the brownout trip point. Initial power-on operation below VDD = 2.7 V is not guaranteed. 13.Devices initially operating at VDD = 4.0 V or above and at fOSC = 20 MHz or less are guaranteed to continue to execute instructions correctly at the brownout trip point. Initial power-on operation below VDD = 4.0 V and fOSC > 10 MHz is not guaranteed. 2001 Oct 26 46

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP COMPARATOR ELECTRICAL CHARACTERISTICS VDD = 3.0 V to 6.0 V unless otherwise specified; Tamb = 0°C to +70°C or –40°C to +85°C, unless otherwise specified. LIMITS SSYYMMBBOOLL PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP MAX VIO Offset voltage comparator inputs1 ±10 mV VCR Common mode range comparator inputs 0 VDD–0.3 V CMRR Common mode rejection ratio1 –50 dB Response time 250 500 ns Comparator enable to output valid 10 m s IIL Input leakage current, comparator 0 < VIN < VDD ±10 m A NOTE: 1. This parameter is guaranteed by characterization, but not tested in production. AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VDD = 2.7 V to 6.0 V unless otherwise specified; VSS = 0 V1, 2, 3 LIMITS SSYYMMBBOOLL FFIIGGUURREE PPAARRAAMMEETTEERR UUNNIITT MIN MAX External Clock fC 39 Oscillator frequency (VDD = 4.0 V to 6.0 V) 0 20 MHz fC 39 Oscillator frequency (VDD = 2.7 V to 6.0 V) 0 10 MHz tC 39 Clock period and CPU timing cycle 1/fC ns On-chip RC oscillator tolerance. Applies to fCTOL P87LPC762BDH only.5 – 10 % On-chip RC oscillator tolerance. All other de- fCTOL vices. – 25 % tCHCX 39 Clock high-time4 fOSC = 20 MHz 20 ns fOSC = 10 MHz 40 ns tCLCX 39 Clock low-time4 fOSC = 20 MHz 20 ns fOSC = 10 MHz 40 ns Shift Register tXLXL 38 Serial port clock cycle time 6tC ns tQVXH 38 Output data setup to clock rising edge 5tC – 133 ns tXHQX 38 Output data hold after clock rising edge 1tC – 80 ns tXHDV 38 Input data setup to clock rising edge 5tC – 133 ns tXHDX 38 Input data hold after clock rising edge 0 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for all outputs = 80 pF. 3. Parts are guaranteed to operate down to 0 Hz. 4. Applies only to an external clock source, not when a crystal is connected to the X1 and X2 pins. 5. For availability of other devices with this specification, please contact Philips sales office. 2001 Oct 26 47

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP tXLXL CLOCK tXHQX tQVXH OUTPUT DATA 0 1 2 3 4 5 6 7 WRITE TO SBUF tXHDX tXHDV SET TI INPUT DATA VALID VALID VALID VALID VALID VALID VALID VALID CLEAR RI SET RI SU01187 Figure 38. Shift Register Mode Timing VDD – 0.5 0.2VDD + 0.9 0.2 VDD – 0.1 0.45V tCHCX tCHCL tCLCX tCLCH tC SU01188 Figure 39. External Clock Timing 100 1000 66..00 VV 6.0 V 55..00 VV 5.0 V A) 10 A) 100 4.0 V Idd (u 43..03 VV Idd (u 232...737 VVV 2.7 V 1 10 10 100 100 1,000 10,000 Frequency (kHz) Frequency (kHz) SU01202 SU01203 Figure 40. Typical Idd versus frequency (low frequency Figure 41. Typical Idd versus frequency (medium frequency oscillator, 25°C) oscillator, 25°C) 2001 Oct 26 48

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP 10,000 10,000 4.0 V 3.3 V 6.0 V 1,000 5.0 V 2.7 V uA)1,000 A) Idd ( 43..03 VV dd (u100 I 2.7 V 10 100 1 1 10 100 10 100 1,000 10,000 Frequency (kHz) Frequency (MHz) SU01204 SU01207 Figure 42. Typical Idd versus frequency (high frequency Figure 45. Typical Idle Idd versus frequency (external clock, oscillator, 25°C) 25°C, LPEP=1) 100,000 10,000 5.0 V 5.0 V 6.0 V 6.0 V 4.0 V 10,000 4.0 V 3.3 V 1,000 3.3 V Idd (uA) 1,000 2.7 V dd (uA) 2.7 V I 100 100 10 10 10 100 1,000 10,000 100,000 10 100 1,000 10,000 100,000 Frequency (kHz) Frequency (kHz) SU01205 SU01208 Figure 43. Typical Active Idd versus frequency (external clock, Figure 46. Typical Idle Idd versus frequency (external clock, 25°C, LPEP=0) 25°C, LPEP=0) 4.0 V 10,000 3.3 V 1,000 2.7 V uA)100 d ( d I 10 1 10 100 1,000 10,000 Frequency (kHz) SU01206 Figure 44. Typical Active Idd versus frequency (external clock, 25°C, LPEP=1) 2001 Oct 26 49

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 2001 Oct 26 50

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 2001 Oct 26 51

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 2001 Oct 26 52

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP REVISION HISTORY Date CPCN Description 2001 Oct 26 9397 750 09018 Removed external components from external reset descriptions in Figure 20. These components are not necessary. 2001 Apr 04 9397 750 08244 Previous release 2001 Oct 26 53

Philips Semiconductors Preliminary data Low power, low price, low pin count (20 pin) 87LPC762 microcontroller with 2 kbyte OTP Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011. Data sheet status Product Definitions Data sheet status[1] status[2] Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information  Koninklijke Philips Electronics N.V. 2001 For additional information please visit All rights reserved. Printed in U.S.A. http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 10-01 For sales offices addresses send e-mail to: Document order number: 9397 750 09018 sales.addresses@www.semiconductors.philips.com. (cid:0)(cid:5)(cid:6)(cid:7)(cid:6)(cid:11)(cid:13) (cid:1)(cid:4)(cid:8)(cid:6)(cid:2)(cid:10)(cid:9)(cid:3)(cid:15)(cid:2)(cid:14)(cid:10)(cid:12)(cid:13) 2001 Oct 26 54