Product Order Technical Tools & Support & Reference Folder Now Documents Software Community Design OPA180,OPA2180,OPA4180 SBOS584E–NOVEMBER2011–REVISEDJUNE2018 OPAx180 0.1-μV/°C Drift, Low-Noise, Rail-to-Rail Output, 36-V, Zero-Drift Operational Amplifiers 1 Features 3 Description • LowOffsetVoltage:75 μV(Maximum) The OPA180, OPA2180 and OPA4180 operational 1 amplifiers (op amps) use TI's proprietary zero-drift • Zero-Drift:0.1 μV/°C techniques to simultaneously provide low offset • LowNoise:10nV/√Hz voltage (75 μV), and near zero-drift over time and • VeryLow1/fNoise temperature. These miniature, high-precision, low- quiescent-current op amps offer high input • ExcellentDCPrecision: impedance and rail-to-rail output swing within 18 mV – PSRR:126dB of the rails. The input common-mode range includes – CMRR:114dB the negative rail. Single- or dual-supplies ranging from4Vto36V(±2Vto ±18V)canbeused. – Open-LoopGain(A ):120dB OL • QuiescentCurrent:525 μA(Maximum) The dual-channel version is offered in VSSOP-8 packages and SOIC-8 packages. The quad-channel • WideSupplyRange:±2Vto ±18V version is offered in SOIC-14 and TSSOP-14 • Rail-to-RailOutput: packages. The single and quad package offerings InputIncludesNegativeRail (OPA180 and OPA4180) are specified from –40°C to • LowBiasCurrent:250pA(Typical) +125°C, and the dual package (OPA2180) is specifiedfrom–40°Cto+105°C. • RFIFilteredInputs • MicroSIZEPackages DeviceInformation(1) DEVICENAME PACKAGE BODYSIZE(NOM) 2 Applications SOT-23(5) 1.60mm×2.90mm • BridgeAmplifiers OPA180 VSSOP,MSOP(8) 3.00mm×3.00mm • StrainGauges SOIC(8) 4.90mm×3.91mm • TestEquipment VSSOP,MSOP(8) 3.00mm×3.00mm OPA2180 • TransducerApplications SOIC(8) 4.90mm×3.91mm • TemperatureMeasurement TSSOP(14) 5.00mm×4.40mm OPA4180 • ElectronicScales SOIC(14) 8.65mm×3.91mm • MedicalInstrumentation (1) For all available packages, see the orderable addendum at theendofthedatasheet. • ResisterThermalDetectors • PrecisionActiveFilters space space space LowNoise (Peak-to-PeakNoise=250nV) div V/ n 0 5 Time (1 s/div) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

OPA180,OPA2180,OPA4180 SBOS584E–NOVEMBER2011–REVISEDJUNE2018 www.ti.com Table of Contents 1 Features.................................................................. 1 8.1 Overview.................................................................17 2 Applications........................................................... 1 8.2 FunctionalBlockDiagram.......................................17 3 Description............................................................. 1 8.3 FeatureDescription.................................................18 8.4 DeviceFunctionalModes........................................20 4 RevisionHistory..................................................... 2 9 ApplicationandImplementation........................ 21 5 DeviceComparisonTable..................................... 4 9.1 ApplicationInformation............................................21 6 PinConfigurationandFunctions......................... 5 9.2 TypicalApplications................................................21 7 Specifications......................................................... 8 10 PowerSupplyRecommendations..................... 25 7.1 AbsoluteMaximumRatings......................................8 11 Layout................................................................... 26 7.2 ESDRatings............................................................8 11.1 LayoutGuidelines.................................................26 7.3 RecommendedOperatingConditions.......................8 11.2 LayoutExample....................................................26 7.4 ThermalInformation:OPA180..................................9 12 DeviceandDocumentationSupport................. 27 7.5 ThermalInformation:OPA2180................................9 7.6 ThermalInformation:OPA4180................................9 12.1 RelatedLinks........................................................27 7.7 ElectricalCharacteristics:V =±2Vto±18V(V = 12.2 Trademarks...........................................................27 S S 4Vto36V)..............................................................10 12.3 ElectrostaticDischargeCaution............................27 7.8 TypicalCharacteristics:TableofGraphs................12 12.4 Glossary................................................................27 7.9 TypicalCharacteristics............................................13 13 Mechanical,Packaging,andOrderable 8 DetailedDescription............................................ 17 Information........................................................... 27 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionD(May2014)toRevisionE Page • ChangedOPA180andOPA4180operatingtemperaturefrom"–40°Cto+105°C"to"–40°Cto+125°C"in Descriptionsection................................................................................................................................................................. 1 • AddedstoragetemperatureparameterasthelastrowintheAbsoluteMaximumRatingstable ......................................... 8 • Changedmaximumoperatingtemperaturevaluefrom105°Cto125°CinAbsoluteMaximumRatingstable .....................8 • Changedmaximumoperatingtemperaturevaluefrom105°Cto125°CinRecommendedOperatingConditionstable......8 • ChangedinputoffsetvoltagedrifttemperaturerangefromT =–40°Cto105°CtoT =–40°Cto+125°Cin A A ElectricalCharacteristicstable............................................................................................................................................. 10 • ChangedpowersupplyrejectionratiotemperaturerangefromT =–40°Cto105°CtoT =–40°Cto+125°Cin A A ElectricalCharacteristicstable............................................................................................................................................. 10 • ChangedOPA180inputbiascurrenttemperaturerangefromT =–40°Cto105°CtoT =–40°Cto+125°Cin A A ElectricalCharacteristicstable............................................................................................................................................. 10 • AddedminimumOPA2180inputbiascurrentvalueof18nAinElectricalCharacteristicstable........................................ 10 • AddedminimumOPA180inputbiascurrentvalueof18nAinElectricalCharacteristicstable........................................... 10 • ChangedOPA180inputoffsetcurrenttemperaturerangefromT =–40°Cto105°CtoT =–40°Cto+125°Cin A A ElectricalCharacteristicstable............................................................................................................................................. 10 • AddedminimumOPA2180inputoffsetcurrentvalueof6nAinElectricalCharacteristicstable ....................................... 10 • AddedminimumOPA180inputoffsetcurrentvalueof6nAinElectricalCharacteristicstable ......................................... 10 • Changedcommon-moderejectionratiotemperaturerangefromT =–40°Cto105°CtoT =–40°Cto+125°Cin A A ElectricalCharacteristicstable............................................................................................................................................. 10 • Changedopen-loopvoltagegaintemperaturerangefromT =–40°Cto105°CtoT =–40°Cto+125°CinElectrical A A Characteristicstable............................................................................................................................................................. 10 • ChangedvoltageoutputswingfromrailtemperaturerangefromT =–40°Cto105°CtoT =–40°Cto+125°Cin A A ElectricalCharacteristicstable............................................................................................................................................. 11 • ChangedquiescentcurrenttemperaturerangefromT =–40°Cto105°CtoT =–40°Cto+125°CinElectrical A A Characteristicstable............................................................................................................................................................. 11 • Changedoperatingtemperaturefrom"–40°Cto+105°C"to"–40°Cto+125°C"inFeatureDescriptionsection..............18 • UpdatedFigure34................................................................................................................................................................ 24 2 SubmitDocumentationFeedback Copyright©2011–2018,TexasInstrumentsIncorporated ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 www.ti.com SBOS584E–NOVEMBER2011–REVISEDJUNE2018 Revision History (continued) • Changedoperatingtemperaturefrom"–40°Cto+105°C"to"–40°Cto+125°C"inPowerSupplyRecommendations section.................................................................................................................................................................................. 25 ChangesfromRevisionC(December2012)toRevisionD Page • Changedformattomeetlatestdatasheetstandards;addedDeviceFunctionalModes,Applicationand Implementation,andPowerSupplyRecommendationssections,andmovedexistingsections........................................... 1 • AddedOPA180todocument.................................................................................................................................................. 1 • AddedDeviceInformationtable ............................................................................................................................................ 1 • DeletedPackageInformationtable........................................................................................................................................ 5 • OPA180pinoutdrawings ....................................................................................................................................................... 5 • AddedPinFunctionstable..................................................................................................................................................... 5 • AddedPinFunctionstable..................................................................................................................................................... 6 • AddedPinFunctionstable..................................................................................................................................................... 7 • AddedRecommendedOperatingConditionstable................................................................................................................ 8 • AddedThermalInformation:OPA180table............................................................................................................................ 9 • ChangedOffsetVoltage,Long-termstabilityparametertypicalspecificationinElectricalCharacteristicstable.................10 • ChangedlastsentenceofEMIRejectionsection................................................................................................................. 18 ChangesfromRevisionB(December2011)toRevisionC Page • ChangedproductstatusfromMixedStatustoProductionData............................................................................................ 1 • ChangedOPA4180statustoProductionData....................................................................................................................... 1 • AddedpackagemarkingtoOPA2180VSSOP-8rowinPackageInformationtable.............................................................. 5 • DeletedorderingnumberandtransportmediacolumnsfromPackageInformationtable..................................................... 5 • ChangedInputBiasCurrentsectioninElectricalCharacteristics(V =+4Vto+36V)table............................................. 10 S ChangesfromRevisionA(November2011)toRevisionB Page • Changedfootnote1ofElectricalCharacteristicstable......................................................................................................... 10 • UpdatedFigure7 ................................................................................................................................................................. 13 Copyright©2011–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 SBOS584E–NOVEMBER2011–REVISEDJUNE2018 www.ti.com 5 Device Comparison Table Table1.Zero-DriftAmplifierPortfolio OFFSETVOLTAGE OFFSETVOLTAGEDRIFT BANDWIDTH VERSION PRODUCT (µV) (µV/°C) (MHz) OPA188(4Vto36V) 25 0.085 2 OPA180(4Vto36V) 75 0.35 2 Single OPA333(5V) 10 0.05 0.35 OPA378(5V) 50 0.25 0.9 OPA735(12V) 5 0.05 1.6 OPA2188(4Vto36V) 25 0.085 2 OPA2180(4Vto36V) 75 0.35 2 Dual OPA2333(5V) 10 0.05 0.35 OPA2378(5V) 50 0.25 0.9 OPA2735(12V) 5 0.05 1.6 OPA4188(4Vto36V) 25 0.085 2 Quad OPA4180(4Vto36V) 75 0.35 2 OPA4330(5V) 50 0.25 0.35 4 SubmitDocumentationFeedback Copyright©2011–2018,TexasInstrumentsIncorporated ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 www.ti.com SBOS584E–NOVEMBER2011–REVISEDJUNE2018 6 Pin Configuration and Functions OPA180DBVPackage 5-PinSOT-23 (TopView) OUT 1 5 V+ V- 2 +IN 3 4 -IN PinFunctions PIN I/O DESCRIPTION NAME NO. –IN 4 I Invertinginput +IN 3 I Noninvertinginput OUT 1 O Output V– 2 — Negativesupplyorground(forsingle-supplyoperation) V+ 5 — Positivesupplyorground(forsingle-supplyoperation) OPA180D,DGKPackages 8-PinSO,MSOP TopView NC(1) 1 8 NC(1) -IN 2 7 V+ +IN 3 6 OUT V- 4 5 NC(1) (1) NC-nointernalconnection PinFunctions:OPA180 PIN DESCRIPTION NAME NO. –IN 2 Invertinginput +IN 3 Noninvertinginput NC 1,5,8 Noconnection OUT 6 Output V– 4 Negativepowersupply V+ 7 Positivepowersupply Copyright©2011–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 SBOS584E–NOVEMBER2011–REVISEDJUNE2018 www.ti.com OPA2180D,DGKPackages 8-PinSOIC,VSSOP TopView OUT A 1 8 V+ A -IN A 2 7 OUT B +IN A 3 B 6 -IN B V- 4 5 +IN B PinFunctions:OPA2180 PIN DESCRIPTION NAME NO. –INA 2 Invertinginput,channelA +INA 3 Noninvertinginput,channelA –INB 6 Invertinginput,channelB +INB 5 Noninvertinginput,channelB OUTA 1 Output,channelA OUTB 7 Output,channelB V– 4 Negativepowersupply V+ 8 Positivepowersupply 6 SubmitDocumentationFeedback Copyright©2011–2018,TexasInstrumentsIncorporated ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 www.ti.com SBOS584E–NOVEMBER2011–REVISEDJUNE2018 OPA4180D,PWPackages 14-PinSOIC,TSSOP (TopView) OUT A 1 14 OUT D -IN A 2 A D 13 -IN D +IN A 3 12 +IN D V+ 4 11 V- +IN B 5 10 +IN C B C -IN B 6 9 -IN C OUT B 7 8 OUT C PinFunctions:OPA4180 PIN DESCRIPTION NAME NO. –INA 2 Invertinginput,channelA +INA 3 Noninvertinginput,channelA –INB 6 Invertinginput,channelB +INB 5 Noninvertinginput,channelB –INC 9 Invertinginput,channelC +INC 10 Noninvertinginput,channelC –IND 13 Invertinginput,channelD +IND 12 Noninvertinginput,channelD OUTA 1 Output,channelA OUTB 7 Output,channelB OUTC 8 Output,channelC OUTD 14 Output,channelD V– 11 Negativesupplyorground(forsingle-supplyoperation) V+ 4 Positivesupplyorground(forsingle-supplyoperation) Copyright©2011–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 SBOS584E–NOVEMBER2011–REVISEDJUNE2018 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT ±20,±40 Supplyvoltage V (single-supply) Voltage (V–)–0.5 (V+)+0.5 V Signalinputterminals Current ±10 mA Outputshort-circuit(2) Continuous Operatingtemperature –55 125 °C T Junctiontemperature 150 °C J T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Short-circuittoground,oneamplifierperpackage. 7.2 ESD Ratings MIN MAX UNIT T Storagetemperaturerange –65 150 °C stg Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,all pins(1) –1.5 1.5 V Electrostaticdischarge kV (ESD) Chargeddevicemodel(CDM),perJEDECspecification JESD22-C101,allpins(2) –1 1 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted),R =10kΩconnectedtoV /2,andV =V =V / L S COM OUT S 2,(unlessotherwisenoted) MIN NOM MAX UNIT Single-supply 4.5 36 V Supplyvoltage[(V+)–(V–)] Bipolar-supply ±2.25 ±18 V Operatingtemperature –40 125 °C 8 SubmitDocumentationFeedback Copyright©2011–2018,TexasInstrumentsIncorporated ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 www.ti.com SBOS584E–NOVEMBER2011–REVISEDJUNE2018 7.4 Thermal Information: OPA180 OPA180 THERMALMETRIC(1) D(SOIC) DBV(SOT-23) DGK(MSOP) UNIT 8PINS 5PINS 8PINS RθJA Junction-to-ambientthermalresistance 115.8 158.8 180.4 °C/W RθJC(top) Junction-to-case(top)thermalresistance 60.1 60.7 67.9 °C/W RθJB Junction-to-boardthermalresistance 56.4 44.8 102.1 °C/W ψJT Junction-to-topcharacterizationparameter 12.8 1.6 10.4 °C/W ψJB Junction-to-boardcharacterizationparameter 55.9 4.2 100.3 °C/W RθJC(bot) Junction-to-case(bottom)thermalresistance N/A N/A N/A °C/W (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. 7.5 Thermal Information: OPA2180 OPA2180 THERMALMETRIC(1) D(SOIC) DGK(MSOP) UNIT 8PINS 8PINS R Junction-to-ambientthermalresistance 111 159.3 °C/W θJA R Junction-to-case(top)thermalresistance 54.9 37.4 °C/W θJC(top) R Junction-to-boardthermalresistance 51.7 48.5 °C/W θJB ψ Junction-to-topcharacterizationparameter 9.3 1.2 °C/W JT ψ Junction-to-boardcharacterizationparameter 51.1 77.1 °C/W JB R Junction-to-case(bottom)thermalresistance N/A N/A °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. 7.6 Thermal Information: OPA4180 OPA4180 THERMALMETRIC(1) D(SOIC) PW(TSSOP) UNIT 14PINS 14PINS R Junction-to-ambientthermalresistance 93.2 106.9 °C/W θJA R Junction-to-case(top)thermalresistance 51.8 24.4 °C/W θJC(top) R Junction-to-boardthermalresistance 49.4 59.3 °C/W θJB ψ Junction-to-topcharacterizationparameter 13.5 0.6 °C/W JT ψ Junction-to-boardcharacterizationparameter 42.2 54.3 °C/W JB R Junction-to-case(bottom)thermalresistance N/A N/A °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. Copyright©2011–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 SBOS584E–NOVEMBER2011–REVISEDJUNE2018 www.ti.com 7.7 Electrical Characteristics: V = ±2 V to ±18 V (V = 4 V to 36 V) S S atT =25°C,R =10kΩconnectedtoV /2,andV =V =V /2,unlessotherwisenoted. A L S COM OUT S PARAMETER CONDITIONS MIN TYP MAX UNIT OFFSETVOLTAGE VIO Inputoffsetvoltage 15 75 μV dVIO/dT Inputoffsetvoltagedrift TA=–40°Cto+125°C 0.1 0.35 μV/°C VS=4Vto36V, 0.1 0.5 μV/V VCM=VS/2 PSRR Powersupplyrejectionratio TA=–40°Cto+125°C, 0.5 μV/V VS=4Vto36V,VCM=VS/2 Long-termstability 4(1) μV Channelseparation,DC 1 μV/V INPUTBIASCURRENT OPA2180 ±0.25 ±1 nA OPA2180:TA=–40°Cto+105°C 18 ±5 nA IIB Inputbiascurrent OPA180,OPA4180 ±0.25 ±1.7 nA OPA180,OPA4180:TA=–40°Cto+125°C 18 ±6 nA OPA2180 ±0.5 ±2 nA OPA2180:TA=–40°Cto+105°C 6 ±2.5 nA IIO Inputoffsetcurrent OPA180,OPA4180 ±3.4 nA OPA180,OPA4180:TA=–40°Cto+125°C 6 ±3 nA NOISE Inputvoltagenoise ƒ=0.1Hzto10Hz 0.25 μVPP en Inputvoltagenoisedensity ƒ=1kHz 10 nV/√Hz in Inputcurrentnoisedensity ƒ=1kHz 10 fA/√Hz INPUTVOLTAGERANGE VCM Common-modevoltagerange V– (V+)–1.5 V (V–)<VCM<(V+)–1.5V 104 114 dB CMRR Common-moderejectionratio TA=–40°Cto+125°C, 100 104 dB (V–)+0.5V<VCM<(V+)–1.5V INPUTIMPEDANCE zid Differential 100||6 MΩ||pF zic Common-mode 6||9.5 1012Ω||pF OPEN-LOOPGAIN (V–)+500mV<VO<(V+)–500mV 110 120 dB RL=10kΩ AOL Open-loopvoltagegain TA=–40°Cto+125°C (V–)+500mV<VO<(V+)–500mV, 104 114 dB RL=10kΩ FREQUENCYRESPONSE GBW Gainbandwidthproduct 2 MHz SR Slewrate G=1 0.8 V/μs 0.1% VS=±18V,G=1,10-Vstep 22 μs ts Settlingtime 0.01% VS=±18V,G=1,10-Vstep 30 μs tor Overloadrecoverytime VIN×G=VS 1 μs THD+N Totalharmonicdistortion+noise ƒ=1kHz,G=1,VOUT=1VRMS 0.0001% (1) 1000-hourlifetestat125°Cdemonstratedrandomlydistributedvariationintherangeofmeasurementlimits,orapproximately4μV. 10 SubmitDocumentationFeedback Copyright©2011–2018,TexasInstrumentsIncorporated ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 www.ti.com SBOS584E–NOVEMBER2011–REVISEDJUNE2018 Electrical Characteristics: V = ±2 V to ±18 V (V = 4 V to 36 V) (continued) S S atT =25°C,R =10kΩconnectedtoV /2,andV =V =V /2,unlessotherwisenoted. A L S COM OUT S PARAMETER CONDITIONS MIN TYP MAX UNIT OUTPUT Noload 8 18 mV Voltageoutputswingfromrail RL=10kΩ 250 300 mV TA=–40°Cto+125°C 325 360 mV RL=10kΩ IOS Short-circuitcurrent ±18 mA ro Outputresistance(openloop) ƒ=2MHz,IO=0mA 120 Ω CLOAD Capacitiveloaddrive 1 nF POWERSUPPLY VS Operatingvoltagerange ±2(or4) ±18(or36) V 450 525 μA IQ Quiescentcurrent(peramplifier) TA=–40°Cto+125°C 600 μA IO=0mA TEMPERATURE Specifiedrange –40 105 °C Operatingrange –40 105 °C Copyright©2011–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 SBOS584E–NOVEMBER2011–REVISEDJUNE2018 www.ti.com 7.8 Typical Characteristics: Table of Graphs Table2.CharacteristicPerformanceMeasurements DESCRIPTION FIGURE I andI vsCommon-ModeVoltage Figure1 B OS InputBiasCurrentvsTemperature Figure2 OutputVoltageSwingvsOutputCurrent(MaximumSupply) Figure3 CMRRvsTemperature Figure4 0.1-Hzto10-HzNoise Figure5 InputVoltageNoiseSpectralDensityvsFrequency Figure6 Open-LoopGainandPhasevsFrequency Figure7 Open-LoopGainvsTemperature Figure8 Open-LoopOutputImpedancevsFrequency Figure9 Small-SignalOvershootvsCapacitiveLoad(100-mVOutputStep) Figure10,Figure11 NoPhaseReversal Figure12 PositiveOverloadRecovery Figure13 NegativeOverloadRecovery Figure14 Small-SignalStepResponse(100mV) Figure15,Figure16 Large-SignalStepResponse Figure17,Figure18 Large-SignalSettlingTime(10-VPositiveStep) Figure19 Large-SignalSettlingTime(10-VNegativeStep) Figure20 Short-CircuitCurrentvsTemperature Figure21 MaximumOutputVoltagevsFrequency Figure22 ChannelSeparationvsFrequency Figure23 EMIRRIN+vsFrequency Figure24 12 SubmitDocumentationFeedback Copyright©2011–2018,TexasInstrumentsIncorporated ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 www.ti.com SBOS584E–NOVEMBER2011–REVISEDJUNE2018 7.9 Typical Characteristics V =±18V,V =V /2,R =10kΩconnectedtoV /2,andC =100pF,unlessotherwisenoted. S CM S LOAD S L 500 4000 +IIB IIB+ 400 -IIB 3000 IIB- 300 IIO pA) IIO A) 200 nt ( 2000 p e (O urr Iand IIBI 1000 ut Bias C 10000 -100 np I -1000 -200 -300 -2000 -20 -15 -10 -5 0 5 10 15 20 -55 -35 -15 5 25 45 65 85 105 125 V (V) Temperature (°C) CM Figure1.I andI vsCommon-ModeVoltage Figure2.InputBiasCurrentvsTemperature IB IO 20 40 V) 11117698 -8145205°C°°CC Ratio (V/V)m 3350 ((VV--)) <+ V0.C5M V< < ( VV+C)M-<1 (.V5 +V)-1.5 V Output Voltage ( ---1111154456 Mode Rejection 221505 -17 n- 10 o -18 m m 5 -19 o C -20 0 0 2 4 6 8 10 12 14 16 18 20 22 24 -55 -35 -15 5 25 45 65 85 105 125 Output Current (mA) Temperature (°C) V =±2V SUPPLY Figure3.OutputVoltageSwingvsOutputCurrent Figure4.CMRRvsTemperature (MaximumSupply) 100 )z H Ö V/ n y ( nV/div Densit 10 0 e 5 s oi N e g a olt V 1 Time (1 s/div) 0.1 1 10 100 1k 10k 100k Peak-to-PeakNoise=250nV Frequency (Hz) Figure5.0.1-Hzto10-HzNoise Figure6.InputVoltageNoiseSpectralDensityvsFrequency Copyright©2011–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 SBOS584E–NOVEMBER2011–REVISEDJUNE2018 www.ti.com Typical Characteristics (continued) V =±18V,V =V /2,R =10kΩconnectedtoV /2,andC =100pF,unlessotherwisenoted. S CM S LOAD S L 140 180 3 Gain V = 4 V, R = 10 kW SUPPLY L 120 Phase 2.5 VSUPPLY= 36 V, RL= 10 kW 100 135 Gain (dB) 468000 90 Phase (°) (V/V)mOL 1.25 A 20 45 1 0 0.5 −20 0 10 100 1k 10k 100k 1M 10M 100M Frequency (Hz) G007 0 -55 -35 -15 5 25 45 65 85 105 125 Temperature (°C) Figure7.Open-LoopGainandPhasevsFrequency Figure8.Open-LoopGainvsTemperature 10k 40 R = 0W OUT 35 R = 25W 1k OUT 30 R = 50W OUT %) 25 W) 100 ot ( Z(O 10 Oversho 2105 G = 1 18 V 10 Device ROUT 1 5 -18 V RL CL 1m 0 1 10 100 1k 10k 100k 1M 10M 0 100 200 300 400 500 600 700 800 900 1000 Frequency (Hz) Capacitive Load (pF) R =10kΩ L Figure9.Open-LoopOutputImpedancevsFrequency Figure10.Small-SignalOvershootvsCapacitiveLoad (100-mVOutputStep) 40 ROUT= 0W 18 V 35 R = 25W OUT Device 30 R = 50W OUT -18 V ot (%) 25 div 3S(±7i1n V8e. P5WP Vav)e sho 20 5 V/ er v 15 O RI=10 kW RF= 10 kW G =-1 10 18 V 5 Device ROUT CL VVIO -18 V 0 0 100 200 300 400 500 600 700 800 900 1000 Time (100ms/div) Capacitive Load (pF) R =10kΩ L Figure11.Small-SignalOvershootvsCapacitiveLoad Figure12.NoPhaseReversal (100-mVOutputStep) 14 SubmitDocumentationFeedback Copyright©2011–2018,TexasInstrumentsIncorporated ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 www.ti.com SBOS584E–NOVEMBER2011–REVISEDJUNE2018 Typical Characteristics (continued) V =±18V,V =V /2,R =10kΩconnectedtoV /2,andC =100pF,unlessotherwisenoted. S CM S LOAD S L VO VI 20 kW 20 kW 2 kW 18 V V/div VI Device VO V/div 2 kW Devic1e8 V VO 5 -1G8 V =-10 5 VI -18G V =-10 V V O I Time (5ms/div) Time (5ms/div) Figure13.PositiveOverloadRecovery Figure14.NegativeOverloadRecovery v v di di V/ V/ 0 m 0 m RI=2 kW RF=2 kW 2 G = 1 2 +18 V 18 V Device Device -18 V RL CL -18 V CL G =-1 Time (1ms/div) Time (20ms/div) RL=10kΩ CL=10pF RL=10kΩ CL=10pF Figure15.Small-SignalStepResponse Figure16.Small-SignalStepResponse(100mV) (100mV) V/div V/div 5 5 Time (50ms/div) Time (50ms/div) G=1 R =10kΩ C =10pF G=–1 R =10kΩ C =10pF L L L L Figure17.Large-SignalStepResponse Figure18.Large-SignalStepResponse Copyright©2011–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 SBOS584E–NOVEMBER2011–REVISEDJUNE2018 www.ti.com Typical Characteristics (continued) V =±18V,V =V /2,R =10kΩconnectedtoV /2,andC =100pF,unlessotherwisenoted. S CM S LOAD S L 10 10 8 8 6 6 V) V) m 4 m 4 e ( 12-Bit Settling e ( 12-Bit Settling alu 2 alu 2 V V al 0 al 0 n n Fi -2 Fi -2 m (±1/2 LSB =±0.024%) m (±1/2 LSB =±0.024%) o -4 o -4 fr fr D D -6 -6 -8 -8 -10 -10 0 10 20 30 40 50 60 0 10 20 30 40 50 60 Time (ms) Time (ms) G=–1 G=–1 Figure19.Large-SignalSettlingTime(10-VPositiveStep) Figure20.Large-SignalSettlingTime(10-VNegativeStep) 30 15 V =±15 V S 20 12.5 )P 10 VP 10 Maximum output voltage without mA) ISC, Source age ( slew-rate induced distortion. (C 0 ISC, Sink Volt 7.5 IS ut VS=±5 V -10 utp 5 O -20 2.5 V =±2.25 V S -30 0 -55 -35 -15 5 25 45 65 85 105 125 1k 10k 100k 1M 10M Temperature (°C) Frequency (Hz) Figure21.Short-CircuitCurrentvsTemperature Figure22.MaximumOutputVoltagevsFrequency -60 160 ChannelAto B -70 Channel B toA 140 dB) -80 120 n ( -90 B) aratio -100 N+ (d 100 nnel Sep --112100 EMIRR I 8600 a Ch -130 40 -140 20 -150 0 1 10 100 1k 10k 100k 1M 10M 100M 10M 100M 1G 10G Frequency (Hz) Frequency (Hz) Figure23.ChannelSeparationvsFrequency Figure24.EMIRRIN+vsFrequency 16 SubmitDocumentationFeedback Copyright©2011–2018,TexasInstrumentsIncorporated ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 www.ti.com SBOS584E–NOVEMBER2011–REVISEDJUNE2018 8 Detailed Description 8.1 Overview The OPAx180 family of operational amplifiers combine precision offset and drift with excellent overall performance, making them designed for many precision applications. The precision offset drift of only 0.1 µV/°C provides stability over the entire temperature range. In addition, the devices offer excellent overall performance with high CMRR, PSRR, and A . As with all amplifiers, applications with noisy or OL high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitorsareadequate. 8.2 Functional Block Diagram V+ C2 Notch CHOP1 GM1 CHOP2 Filter GM2 (cid:14) GM3 (cid:14) (cid:14) +IN (cid:16) OUT (cid:16) (cid:14) -IN (cid:16) (cid:16) C1 (cid:14) (cid:16) GM_FF V- Copyright © 2017, Texas Instruments Incorporated Copyright©2011–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 SBOS584E–NOVEMBER2011–REVISEDJUNE2018 www.ti.com 8.3 Feature Description 8.3.1 OperatingCharacteristics The OPAx180 family of amplifiers is specified for operation from 4 V to 36 V (±2 V to ±18 V). Many of the specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operatingvoltageortemperaturearepresentedintheTypicalCharacteristics. 8.3.2 EMIRejection The OPAx180 family uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI interference from sources such as wireless communications and densely populated boards with a mix of analog signal chain and digital components. EMI immunity can improve with circuit design techniques; the OPAx180 family benefits from these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure 25 shows the results of this testing on the OPAx180 family . For more detailed information, see the EMI Rejection Ratio of Operational Amplifiers application report, available for download from www.ti.com. 160 140 120 B) d 100 + ( N R I 80 R MI 60 E 40 20 0 10M 100M 1G 10G Frequency (Hz) Figure25. OPAx180EMIRRTesting 8.3.3 Phase-ReversalProtection The OPAx180 family has an internal phase-reversal protection. Many op amps exhibit a phase reversal when the input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The input of the OPAx180 prevents phase reversal with excessive common-mode voltage.Instead,theoutputlimitsintotheappropriaterail.ThisperformanceisshowninFigure26. 18 V Device -18 V 3S7in Ve PWPave div (±18.5 V) V/ 5 V I V O Time (100ms/div) Figure26. NoPhaseReversal 18 SubmitDocumentationFeedback Copyright©2011–2018,TexasInstrumentsIncorporated ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 www.ti.com SBOS584E–NOVEMBER2011–REVISEDJUNE2018 Feature Description (continued) 8.3.4 CapacitiveLoadandStability The dynamic characteristics of the OPAx180 are optimized for a range of common operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output. The simplest way to achieve this isolation is to add a small resistor (for example, R equal to 50 Ω) in series OUT with the output. Figure 27 and Figure 28 illustrate graphs of small-signal overshoot versus capacitive load for several values of R . See the Feedback Plots Define Op Amp AC Performance, application report, available OUT fordownloadfromtheTIwebsite,fordetailsofanalysistechniquesandapplicationcircuits. 40 40 R = 0W R = 0W OUT OUT 35 R = 25W 35 R = 25W OUT OUT 30 R = 50W 30 R = 50W OUT OUT %) 25 %) 25 ot ( ot ( ho 20 ho 20 s s er er Ov 1150 De1v8i cVe ROUT G = 1 Ov 1150 RI=10 kW RF1=8 1 V0 kW G =-1 5 -18 V RL CL 5 Device ROUT CL -18 V 0 0 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 Capacitive Load (pF) Capacitive Load (pF) 100-mVoutput 100-mVoutput R =10kΩ R =10kΩ L step L step Figure27.Small-SignalOvershootVersusCapacitiveLoad Figure28.Small-SignalOvershootVersusCapacitiveLoad 8.3.5 ElectricalOverstress Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress. These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidentalESDeventsbothbeforeandduringproductassembly. TheseESDprotectiondiodesalsoprovidein-circuit,inputoverdriveprotection,aslongasthecurrentislimitedto 10 mA as stated in the Absolute Maximum Ratings table. Figure 29 shows how a series input resistor may be added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier inputandthevaluemustbekepttoaminimuminnoise-sensitiveapplications. V+ I OVERLOAD 10 mAmax V OUT V IN Device 5 kW Figure29. InputCurrentProtection An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, high- current pulse as the pulse discharges through a semiconductor device. The ESD protection circuits are designed to provide a current path around the operational amplifier core to protect the core from damage. The energy absorbedbytheprotectioncircuitryisthendissipatedasheat. Copyright©2011–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 SBOS584E–NOVEMBER2011–REVISEDJUNE2018 www.ti.com Feature Description (continued) When the operational amplifier connects into a circuit, the ESD protection components are intended to remain inactiveandnotbecomeinvolvedintheapplicationcircuitoperation.However,circumstancesmayarisewhenan applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there is a risk that some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow occursthroughESDcellsandrarelyinvolvestheabsorptiondevice. If there is an uncertainty about the ability of the supply to absorb this current, external zener diodes may be added to the supply pins. The zener voltage must be selected so the diode does not turn on during normal operation. However, the zener voltage must be low enough so that the zener diode conducts if the supply pin begins to rise abovethesafeoperatingsupplyvoltagelevel. 8.4 Device Functional Modes The OPAx180, OPA2180 , and OPA4180 devices are powered on when the supply is connected. These devices can operate as a single-supply operational amplifier or dual-supply amplifier depending on the application. In single-supply operation with V– at ground (0 V), V+ can be any value between 4 V and 36 V. In dual-supply operation, the supply voltage difference between V– and V+ is from 4 V to 36 V. Typical examples of dual-supply configuration are ±5 V, ±10 V, ±15 V, and ±18 V. However, the supplies must not be symmetrical. Less common examples are V– at –3 V and V+ at 9 V, or V– at –16 V and V+ at 5 V. Any combination where the difference between V– and V+ is at least 4 V and no greater than 36 V is within the normal operating capabilities of these devices. 20 SubmitDocumentationFeedback Copyright©2011–2018,TexasInstrumentsIncorporated ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 www.ti.com SBOS584E–NOVEMBER2011–REVISEDJUNE2018 9 Application and Implementation 9.1 Application Information The OPAx180 family offers excellent DC precision and AC performance. These devices operate up to 36-V supply rails and offer rail-to-rail output, ultra-low offset voltage, offset voltage drift and 2-MHz bandwidth. These featuresmaketheOPAx180arobust,high-performanceamplifierforhigh-voltageindustrialapplications. 9.2 Typical Applications TheseapplicationexampleshighlightafewofthecircuitswheretheOPAx180familycanbeused. 9.2.1 Bipolar±10-VAnalogOutputfromaUnipolarVoltageOutputDAC This design is used for conditioning a unipolar digital-to-analog converter (DAC) into an accurate bipolar signal source using the OPAx180 family and three resistors. The circuit is designed with reactive load stability in mind, andiscompensatedtodrivenearlyanyconventionalcapacitiveloadassociatedwithlongcablelengths. RG1 RFB CCOMP VREF RG2 VOUT DAC8560 + RISO CLOAD Device Copyright © 2017, Texas Instruments Incorporated Figure30. CircuitSchematic 9.2.1.1 DesignRequirements Thedesignrequirementsareasfollows: • DACsupplyvoltage:+5-Vdc • Amplifiersupplyvoltage: ±15-Vdc • Input:3-wire,24-bitSPI • Output: ±10-Vdc Copyright©2011–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 SBOS584E–NOVEMBER2011–REVISEDJUNE2018 www.ti.com Typical Applications (continued) 9.2.1.2 DetailedDesignProcedure 9.2.1.2.1 ComponentSelection DAC: For convenience, devices with an external reference option or devices with accessible internal references are desirable in this application because the reference creates an offset. The DAC selection in this design must primarily be based on DC error contributions typically described by offset error, gain error, and integral nonlinearity error. Occasionally, additional specifications are provided that summarize end-point errors of the DAC typically called zero-code and full-scale errors. For AC applications, slew rate and settling time may require additionalconsideration. Amplifier:Amplifierinputoffsetvoltage(V )isakeyconsiderationforthisdesign.V ofanoperationalamplifier IO IO is a typical data sheet specification, but in-circuit performance is also affected by drift over temperature, the common-mode rejection ratio (CMRR), and power-supply rejection ratio (PSRR); thus consideration should be given to these parameters as well. For ac operation, additional considerations should be made concerning slew rate and settling time. Input bias current (I ) can also be a factor, but typically the resistor network is IB implementedwithsufficientlysmallresistorvaluesthattheeffectsofinputbiascurrentarenegligible. Passive: Resistor matching for the op-amp resistor network is critical for the success of this design; components with tight tolerances must be selected. For this design, 0.1% resistor values are implemented, but this constraint may be adjusted based on application-specific design goals. Resistor matching contributes to offset error and gain error in this design; see Bipolar ±10V Analog Output from a Unipolar Voltage Output DAC for further details. ThetoleranceoftheR andC stabilitycomponentsisnotcritical,and1%componentsareacceptable. ISO COMP 9.2.1.3 ApplicationCurves Figure31. Full-ScaleOutputWaveform 22 SubmitDocumentationFeedback Copyright©2011–2018,TexasInstrumentsIncorporated ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 www.ti.com SBOS584E–NOVEMBER2011–REVISEDJUNE2018 Typical Applications (continued) Figure32. DCTransferCharacteristic Forstep-by-stepdesignprocedure,circuitschematics,billofmaterials,PCBfiles,simulationresults,andtest results,refertoTIPrecisionDesignTIPD125,Bipolar±10VAnalogOutputfromaUnipolarVoltageOutputDAC Copyright©2011–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 SBOS584E–NOVEMBER2011–REVISEDJUNE2018 www.ti.com 9.2.2 DiscreteINA+Attenuation The OPAx180 family can be used as a high-voltage, high-impedance front-end for a precision, discrete instrumentation amplifier with attenuation. The INA159 in Figure 33 provides the attenuation that allows this circuittosimplyinterfacewith3.3-Vor5-Vanalog-to-digitalconverters(ADCs). 15 V U2 ½ OPA2180 VOUTP 3.3 V VDIFF/2 -15 V 1R k5W Ref 1 Ref 2 + R50G0W 1R k7W INAU1159 VOUT VCM Sense 10 -V /2 -15 V DIFF U5 ½ OPA2180 VOUTN 15 V Figure33. DiscreteINA+AttenuationforADCWitha3.3-VSupply 9.2.3 RTDAmplifier The OPAx180 is excellent for use in analog linearization of resistance temperature detectors (RTDs). The circuit below (Figure 34) combines the precision of the OPAx180 amplifier and the precision reference of the REF5050 tolinearizeaPt100RTD. 15 V (5 V) Out In REF5050 1 µF R2 49.1 k(cid:13)(cid:3) 1 µF 4.9R91 k(cid:13)(cid:3) R3 60.4 k(cid:13)(cid:3) – ½ 0°C = 0 V O+PA2180 VOUT 200°C = 5 V RTD Pt100 R5 105.8 k(cid:13)(cid:3) R4 1 k(cid:13)(cid:3) Copyright © 2017, Texas Instruments Incorporated (1) R providespositive-varyingexcitationtolinearizeoutput. 5 Figure34. RTDAmplifierwithLinearization 24 SubmitDocumentationFeedback Copyright©2011–2018,TexasInstrumentsIncorporated ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 www.ti.com SBOS584E–NOVEMBER2011–REVISEDJUNE2018 10 Power Supply Recommendations The OPAx180 family is specified for operation from 4 V to 36 V (±2 V to ±18 V); many specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperaturearepresentedinLayout CAUTION Supply voltages larger than 40 V can permanently damage the device; see the AbsoluteMaximumRatings. Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high- impedancepowersupplies.Formoredetailedinformationonbypasscapacitorplacement,seeLayout . Copyright©2011–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 SBOS584E–NOVEMBER2011–REVISEDJUNE2018 www.ti.com 11 Layout 11.1 Layout Guidelines Forbestoperationalperformanceofthedevice,usegoodprintedcircuitboard(PCB)layoutpractices,including: • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sourceslocaltotheanalogcircuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single- supplyapplications. • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are typically devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to physically separatedigitalandanaloggrounds,payingattentiontotheflowofthegroundcurrent. • In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep the input traces separate, it is much better to cross the sensitive traceperpendicularasopposedtoinparallelwiththenoisytrace. • Place the external components as close to the device as possible. As shown in Figure 35, keeping RF andRGclosetotheinvertinginputminimizesparasiticcapacitance. • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitivepartofthecircuit. • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduceleakagecurrentsfromnearbytracesthatareatdifferentpotentials. 11.2 Layout Example Place components close Run the input traces to device and to each VS+ as far away from other to reduce parasitic the supply lines errors as possible RF NC NC Use a low-ESR, RG ceramic bypass GND –IN V+ capacitor VIN +IN OUTPUT V– NC GND VS– GND VOUT Ground (GND) plane on another layer Use low-ESR, ceramic bypass capacitor Figure35. OperationalAmplifierBoardLayoutforNoninvertingConfiguration 26 SubmitDocumentationFeedback Copyright©2011–2018,TexasInstrumentsIncorporated ProductFolderLinks:OPA180 OPA2180 OPA4180

OPA180,OPA2180,OPA4180 www.ti.com SBOS584E–NOVEMBER2011–REVISEDJUNE2018 12 Device and Documentation Support 12.1 Related Links Table 3 lists quick access links. Categories include technical documents, support and community resources, toolsandsoftware,andquickaccesstosampleorbuy. Table3.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER ORDERNOW DOCUMENTS SOFTWARE COMMUNITY OPA180 Clickhere Clickhere Clickhere Clickhere Clickhere OPA2180 Clickhere Clickhere Clickhere Clickhere Clickhere OPA4180 Clickhere Clickhere Clickhere Clickhere Clickhere 12.2 Trademarks Alltrademarksarethepropertyoftheirrespectiveowners. 12.3 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.4 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2011–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:OPA180 OPA2180 OPA4180

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) OPA180ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 OPA180 & no Sb/Br) OPA180IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 SHJ & no Sb/Br) OPA180IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 SHJ & no Sb/Br) OPA180IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 SHK & no Sb/Br) OPA180IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 SHK & no Sb/Br) OPA180IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 OPA180 & no Sb/Br) OPA2180ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 2180 & no Sb/Br) OPA2180IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 105 2180 & no Sb/Br) OPA2180IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 105 2180 & no Sb/Br) OPA2180IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 2180 & no Sb/Br) OPA4180ID ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 OPA4180 & no Sb/Br) OPA4180IDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 OPA4180 & no Sb/Br) OPA4180IPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 OPA4180 & no Sb/Br) OPA4180IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 105 OPA4180 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF OPA180, OPA2180 : •Automotive: OPA180-Q1, OPA2180-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) OPA180IDBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 OPA180IDBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 OPA180IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA180IDGKT VSSOP DGK 8 250 177.8 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA180IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA2180IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA2180IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA4180IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 OPA4180IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) OPA180IDBVR SOT-23 DBV 5 3000 223.0 270.0 35.0 OPA180IDBVT SOT-23 DBV 5 250 223.0 270.0 35.0 OPA180IDGKR VSSOP DGK 8 2500 346.0 346.0 29.0 OPA180IDGKT VSSOP DGK 8 250 223.0 270.0 35.0 OPA180IDR SOIC D 8 2500 367.0 367.0 35.0 OPA2180IDGKR VSSOP DGK 8 2500 366.0 364.0 50.0 OPA2180IDR SOIC D 8 2500 367.0 367.0 35.0 OPA4180IDR SOIC D 14 2500 367.0 367.0 38.0 OPA4180IPWR TSSOP PW 14 2000 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

None

None

None

None

None

None

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated