Ultralow Power, Rail-to-Rail Output Operational Amplifiers OP281/OP481 FEATURES PIN CONFIGURATIONS Low supply current: 4 μA/amplifier maximum OUT A 1 8 V+ Single-supply operation: 2.7 V to 12 V –IN A 2 OP281 7 OUT B Wide input voltage range +IN A 3 (NToOt Pto V SIEcaWle) 6 –IN B RLoawil- tooff-rsaeitl vooulttpaugte :s w1.i5n mg V V– 4 5 +IN B 00291-001 No phase reversal Figure 1. 8-Lead Narrow-Body SOIC APPLICATIONS (R Suffix) Comparator OUT A 1 8 V+ Battery-powered instrumentation –IN A 2 OP281 7 OUT B Safety monitoring TOP VIEW +IN A 3 (Not to Scale) 6 –IN B RLoewm ovotelt saegnes sotrrsa in gage amplifiers V– 4 5 +IN B 00291-002 Figure 2. 8-Lead TSSOP GENERAL DESCRIPTION (RU Suffix) The OP281 and OP481 are dual and quad ultralow power OUT A 1 14 OUT D single-supply amplifiers featuring rail-to-rail outputs. Each –IN A 2 13 –IN D operates from supplies as low as 2.0 V and is specified at +3 V +IN A 3 OP481 12 +IN D and +5 V single supplies as well as ±5 V dual supplies. V+ 4 TOP VIEW 11 V– (Not to Scale) +IN B 5 10 +IN C Fabricated on Analog Devices’ CBCMOS process, the –IN B 6 9 –IN C OthPat2 8sw1/iOngPs4 t8o1 w feitahtuinr em ai lplirveoclitssio onf tbhipe osluapr pinlipesu,t c aonndti annu ionugt ptou t OUT B 7 8 OUT C 00291-003 Figure 3. 14-Lead sink or source current up to a voltage equal to the supply voltage. Narrow-Body SOIC Applications for these amplifiers include safety monitoring, (R Suffix) portable equipment, battery and power supply control, and OUT A 1 14 OUT D signal conditioning and interfacing for transducers in very low –IN A 2 13 –IN D power systems. +IN A 3 OP481 12 +IN D The output’s ability to swing rail-to-rail and not increase supply V+ 4 (NToOt Pto V SIEcaWle) 11 V– current when the output is driven to a supply voltage enables +IN B 5 10 +IN C the OP281/OP481 to be used as comparators in very low power –IN B 6 9 –IN C sPyrsotpemagsa.t Tiohni sd iesl aeynsh aarnec 2e5d0 b μys t.h eir fast saturation recovery time. OUT B 7 8 OUT C 00291-004 Figure 4. 14-Lead TSSOP The OP281/OP481 are specified over the extended industrial (RU Suffix) temperature range (−40°C to +85°C). The OP281 dual amplifier is available in 8-lead SOIC surface-mount and TSSOP packages. The OP481 quad amplifier is available in narrow 14-lead SOIC and TSSOP packages. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©1996–2008 Analog Devices, Inc. All rights reserved.

OP281/OP481 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation .................................................................. 13 Applications ....................................................................................... 1 Input Overvoltage Protection ................................................... 13 Pin Configurations ........................................................................... 1 Input Offset Voltage ................................................................... 13 General Description ......................................................................... 1 Input Common-Mode Voltage Range ..................................... 13 Revision History ............................................................................... 2 Capacitive Loading ..................................................................... 14 Specifications ..................................................................................... 3 Micropower Reference Voltage Generator .............................. 14 Electrical Specifications ............................................................... 3 Window Comparator ................................................................. 14 Absolute Maximum Ratings ............................................................ 6 Low-Side Current Monitor ....................................................... 15 Thermal Resistance ...................................................................... 6 Low Voltage Half-Wave and Full-Wave Rectifiers ................. 15 ESD Caution .................................................................................. 6 Battery-Powered Telephone Headset Amplifier ..................... 15 Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 17 Applications ..................................................................................... 13 Ordering Guide .......................................................................... 18 REVISION HISTORY 9/08—Rev. C to Rev. D 2/03—Rev. 0 to Rev. A Changes to Figure 40 ...................................................................... 14 Updated Format .................................................................. Universal Changes to Low-Side Current Monitor Section ......................... 15 Deleted OP181 .................................................................... Universal Changes to Figure 42 ...................................................................... 15 Updated Package Options ................................................. Universal Deleted OP181 Pin Configurations ................................................ 1 10/07—Rev. B to Rev. C Deleted Epoxy DIP Pin Configurations ......................................... 1 Updated Format .................................................................. Universal Changes to Absolute Maximum Ratings ........................................ 5 Changes to Offset Voltage Drift Condition .................................. 3 Changes to Ordering Guide ............................................................. 5 Changes to Slew Rate Symbol ......................................................... 5 Changes to Input Offset Voltage ................................................... 10 Changes to Figure 8 .......................................................................... 7 Deleted Former Figure 33 ............................................................. 10 Deleted SPICE Macro-Model Section ......................................... 13 Deleted Overdrive Recovery Time Section ................................. 11 Updated Outline Dimensions ....................................................... 17 Deleted Former Figure 36 ............................................................. 11 Changes to Ordering Guide .......................................................... 18 Deleted 8-Lead and 14-Lead Plastic DIP (N-8 and N-14) 3/03—Rev. A to Rev. B Outline Dimensions ....................................................................... 14 Updated Outline Dimensions ....................................................... 14 Changes to Features .......................................................................... 1 Rev. D | Page 2 of 20

OP281/OP481 SPECIFICATIONS ELECTRICAL SPECIFICATIONS V = 3.0 V, V = 1.5 V, T = 25°C, unless otherwise noted. S CM A Table 1. Parameter Symbol Condition Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage1 V 1.5 mV OS −40°C ≤ T ≤ +85°C 2.5 mV A Input Bias Current I −40°C ≤ T ≤ +85°C 3 10 nA B A Input Offset Current I −40°C ≤ T ≤ +85°C 0.1 7 nA OS A Input Voltage Range 0 2 V Common-Mode Rejection Ratio CMRR V = 0 V to 2.0 V, −40°C ≤ T ≤ +85°C 65 95 dB CM A Large-Signal Voltage Gain A R = 1 MΩ, V = 0.3 V to 2.7 V 5 13 V/mV VO L O −40°C ≤ T ≤ +85°C 2 V/mV A Offset Voltage Drift ΔV /∆T −40°C to +85°C 10 μV/°C OS Bias Current Drift ΔI/ΔT 20 pA/°C B Offset Current Drift ΔI /ΔT 2 pA/°C OS OUTPUT CHARACTERISTICS Output Voltage High V R = 100 kΩ to GND, −40°C ≤ T ≤ +85°C 2.925 2.96 V OH L A Output Voltage Low V R = 100 kΩ to V+, −40°C ≤ T ≤ +85°C 25 75 mV OL L A Short-Circuit Limit I ±1.1 mA SC POWER SUPPLY Power Supply Rejection Ratio PSRR V = 2.7 V to 12 V, −40°C ≤ T ≤ +85°C 76 95 dB S A Supply Current/Amplifier I V = 0 V 3 4 μA SY O −40°C ≤ T ≤ +85°C 5 μA A DYNAMIC PERFORMANCE Slew Rate SR R = 100 kΩ, C = 50 pF 25 V/ms L L Turn-On Time A = 1, V = 1 V 40 μs V O A = 20, V = 1 V 50 μs V O Saturation Recovery Time 65 μs Gain Bandwidth Product GBP 95 kHz Phase Margin φ 70 Degrees M NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 10 μV p-p n Voltage Noise Density e f = 1 kHz 75 nV/√Hz n Current Noise Density i <1 pA/√Hz n 1 VOS is tested under a no load condition. Rev. D | Page 3 of 20

OP281/OP481 V = 5.0 V, V = 2.5 V, T = 25°C, unless otherwise noted. S CM A Table 2. Parameter Symbol Condition Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage1 V 0.1 1.5 mV OS −40°C ≤ T ≤ +85°C 2.5 mV A Input Bias Current I −40°C ≤ T ≤ +85°C 3 10 nA B A Input Offset Current I −40°C ≤ T ≤ +85°C 0.1 7 nA OS A Input Voltage Range 0 4 V Common-Mode Rejection Ratio CMRR V = 0 V to 4.0 V, −40°C ≤ T ≤ +85°C 65 90 dB CM A Large-Signal Voltage Gain A R = 1 MΩ, V = 0.5 V to 4.5 V 5 15 V/mV VO L O −40°C ≤ T ≤ +85°C 2 V/mV A Offset Voltage Drift ΔV /ΔT −40°C to +85°C 10 μV/°C OS Bias Current Drift ΔI/ΔT 20 pA/°C B Offset Current Drift ΔI /ΔT 2 pA/°C OS OUTPUT CHARACTERISTICS Output Voltage High V R = 100 kΩ to GND, −40°C ≤ T ≤ +85°C 4.925 4.96 V OH L A Output Voltage Low V R = 100 kΩ to V+, −40°C ≤ T ≤ +85°C 25 75 mV OL L A Short-Circuit Limit I ±3.5 mA SC POWER SUPPLY Power Supply Rejection Ratio PSRR V = 2.7 V to 12 V, −40°C ≤ T ≤ +85°C 76 95 dB S A Supply Current/Amplifier I V = 0 V 3.2 4 μA SY O −40°C ≤ T ≤ +85°C 5 μA A DYNAMIC PERFORMANCE Slew Rate SR R = 100 kΩ, C = 50 pF 27 V/ms L L Saturation Recovery Time 120 μs Gain Bandwidth Product GBP 100 kHz Phase Margin φ 74 Degrees M NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 10 μV p-p n Voltage Noise Density e f = 1 kHz 75 nV/√Hz n Current Noise Density i <1 pA/√Hz n 1 VOS is tested under a no load condition. Rev. D | Page 4 of 20

OP281/OP481 V = ±5.0 V, T = +25°C, unless otherwise noted. S A Table 3. Parameter Symbol Condition Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage1 V 0.1 1.5 mV OS –40°C ≤ T ≤ +85°C 2.5 mV A Input Bias Current I –40°C ≤ T ≤ +85°C 3 10 nA B A Input Offset Current I –40°C ≤ T ≤ +85°C 0.1 7 nA OS A Input Voltage Range –5 +4 V Common-Mode Rejection CMRR V = –5.0 V to +4.0 V, –40°C ≤ T ≤ +85°C 65 95 dB CM A Large-Signal Voltage Gain A R = 1 MΩ, V = ±4.0 V, 5 13 V/mV VO L O –40°C ≤ T ≤ +85°C 2 V/mV A Offset Voltage Drift ΔV /ΔT –40°C to +85°C 10 μV/°C OS Bias Current Drift ΔI/ΔT 20 pA/°C B Offset Current Drift ΔI /ΔT 2 pA/°C OS OUTPUT CHARACTERISTICS Output Voltage Swing V R = 100 kΩ to GND, –40°C ≤ T ≤ +85°C ±4.925 ±4.98 V O L A Short-Circuit Limit I 12 mA SC POWER SUPPLY Power Supply Rejection Ratio PSRR V = ±1.35 V to ±6 V, –40°C ≤ T ≤ +85°C 76 95 dB S A Supply Current/Amplifier I V = 0 V 3.3 5 μA SY O –40°C ≤ T ≤ +85°C 6 μA A DYNAMIC PERFORMANCE Slew Rate SR R = 100 kΩ, C = 50 pF 28 V/ms L L Gain Bandwidth Product GBP 105 kHz Phase Margin φ 75 Degrees M NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 10 μV p-p n Voltage Noise Density e f = 1 kHz 85 nV/√Hz n f = 10 kHz 75 nV/√Hz Current Noise Density i <1 pA/√Hz n 1 VOS is tested under a no load condition. Rev. D | Page 5 of 20

OP281/OP481 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Rating Table 5. Thermal Resistance Supply Voltage 16 V Package Type θ 1 θ Unit JA JC Input Voltage GND to VS + 10 V 8-Lead SOIC (R Suffix) 158 43 °C/W Differential Input Voltage ±3.5 V 8-Lead TSSOP (RU Suffix) 240 43 °C/W Output Short-Circuit Duration to GND Indefinite 14-Lead SOIC (R Suffix) 120 36 °C/W Storage Temperature Range −65°C to +150°C 14-Lead TSSOP (RU Suffix) 240 43 °C/W Operating Temperature Range −40°C to +85°C Junction Temperature Range −65°C to +150°C 1 θJA is specified for the worst-case conditions, that is, θJA is specified for device soldered in circuit board for TSSOP and SOIC packages. Lead Temperature Range (Soldering, 60 sec) 300°C ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. D | Page 6 of 20

OP281/OP481 TYPICAL PERFORMANCE CHARACTERISTICS 45 0 VS = 2.7V VS = 5V 40 TA = 25°C –0.5 –1.0 35 A) ers) 30 T (n –1.5 mplifi 25 RREN –2.0 NTITY (A 20 BIAS CU ––32..05 UA 15 UT –3.5 Q P N 10 I –4.0 5 –4.5 0 –5.0 –1.0 –0.8 –0.6 I–N0P.4UT– O0F.2FSE0T VO0L.2TAG0E.4 (mV0).6 0.8 1.0 00291-005 –40 –20 0 2T0EMPE4R0ATURE60 (°C) 80 100 120 00291-008 Figure 5. Input Offset Voltage Distribution Figure 8. Input Bias Current vs. Temperature 50 1.0 VS = 5V VS = 5V 45 TA = 25°C 0.5 TA = 25°C 40 0 A) ers) 35 T (n–0.5 mplifi 30 RREN–1.0 NTITY (A 2205 BIAS CU–1.5 QUA 15 PUT –2.0 N 10 I–2.5 5 –3.0 0 –3.5 –1.0 –0.8 –0.6 I–N0P.4UT– O0.F2FSE0T VO0L.2TAG0E.4 (mV0).6 0.8 1.0 00291-006 0 0.5 1.0 CO1.M5MO2N.0-MOD2.E5 VO3L.T0AGE3 .(5V) 4.0 4.5 5.0 00291-009 Figure 6. Input Offset Voltage Distribution Figure 9. Input Bias Current vs. Common-Mode Voltage 2000 0.5 VS = 5V VS = 5V 1800 0.4 V) 1600 A) 0.3 E (µ 1400 T (n G N 0.2 A E T 1200 R L R O U 0.1 T V 1000 T C FSE 800 FSE 0 F F O O–0.1 T 600 T U U INP 400 INP–0.2 200 –0.3 0 –0.4 –40 –20 0 2T0EMPE4R0ATURE60 (°C) 80 100 120 00291-007 –40 –20 0 2T0EMPE4R0ATURE60 (°C) 80 100 120 00291-010 Figure 7. Input Offset Voltage vs. Temperature Figure 10. Input Offset Current vs. Temperature Rev. D | Page 7 of 20

OP281/OP481 10000 70 VS = 3V VS = 5V TA = 25°C 60 TA = 25°C RL = 100kΩ 1000 50 OLTAGE (mV) 100 SOURCE OP GAIN (dB) 432000 94005 Degrees) OUTPUT V 10 SINK OPEN-LO 100 113850 SE SHIFT ( A 1 –10 225 H P –20 270 0.1 –30 1 1L0OAD CURRENT (µA10)0 100000291-011 100 1k FREQU1E0NkCY (Hz) 100k 1M 00291-014 Figure 11. Output Voltage to Supply Rail vs. Load Current Figure 14. Open-Loop Gain and Phase vs. Frequency 1000 70 VTAS == 255V°C 60 VTAS == 235V°C RL = 100kΩ 50 OUTPUT VOLTAGE (mV) 101001 SOURCE SINK OPEN-LOOP GAIN (dB) 432100000 94110053850 SE SHIFT (Degrees) A –10 225 H P –20 270 0.1 –30 1 1L0OAD CURRENT (µA10)0 100000291-012 100 1k FREQU1E0NkCY (Hz) 100k 1M 00291-015 Figure 12. Output Voltage to Supply Rail vs. Load Current Figure 15. Open-Loop Gain and Phase vs. Frequency 1000 70 VS = ±5V VS = 2.7V TA = 25°C 60 TA = 25°C RL = 100kΩ 50 OLTAGE (mV) 10100 SOURCE SINK OP GAIN (dB) 432000 94005 Degrees) OUTPUT V 1 OPEN-LO 100 113850 SE SHIFT ( A –10 225 H P –20 270 0.1 –30 1 1L0OAD CURRENT (µA10)0 100000291-013 100 1k FREQU1E0NkCY (Hz) 100k 1M 00291-016 Figure 13. Output Voltage to Supply Rail vs. Load Current Figure 16. Open-Loop Gain and Phase vs. Frequency Rev. D | Page 8 of 20

OP281/OP481 70 90 60 VTRASL === 2±1550°V0CkΩTO GROUND 80 VS = ±5V TA = 25°C 50 70 dB) 40 0 60 VS = +5V OP GAIN ( 3200 9405 Degrees) RR (dB) 5400 VS = +3V OPEN-LO 100 113850 E SHIFT ( CM 3200 S A –10 225 H 10 P –20 270 0 –30100 1k FREQU1E0NkCY (Hz) 100k 1M 00291-017 –101k 10k FREQU1E00NkCY (Hz) 1M 10M 00291-020 Figure 17. Open-Loop Gain and Phase vs. Frequency Figure 20. CMRR vs. Frequency 60 160 VS = 5V VS = ±5V, +5V, +3V, +2.7V 50 TRAL == 2∞5°C 140 TRAL == 2∞5°C 40 120 B) d 30 100 N ( GAI 20 B) 80 OOP 10 RR (d 60 D-L 0 PS 40 E S LO–10 20 C –20 0 –30 –20 –40 –40 10 100 F1RkEQUENCY1 (0Hkz) 100k 1M 00291-018 10 100 F1RkEQUENCY1 (0Hkz) 100k 1M 00291-021 Figure 18. Closed-Loop Gain vs. Frequency Figure 21. PSRR vs. Frequency 50 VS = 5V VS = +5V TA = 25°C 45 VIN = ±50mV MARKER @ 67nV/√Hz RL = 100kΩ %) 40 TA = 25°C –OS T ( OO 35 +OS H 50nV/√Hz/DIV) GNAL OVERS 322050 ( SI L 15 L A M 10 S 5 0 0 2 FR4EQUENCY (k6Hz) 8 10 00291-019 10 LOAD CAPA1C00ITANCE (pF) 100000291-022 Figure 19. Voltage Noise Density vs. Frequency Figure 22. Small-Signal Overshoot vs. Load Capacitance Rev. D | Page 9 of 20

OP281/OP481 5 4.5 VS = 5V VS = 5V VIN = 4V p-p 4.0 V p-p) 4 TRAL == 2∞5°C R (µA) 3.5 UT SWING ( 3 T/AMPLIFIE 32..05 P N T E 2.0 U R O 2 R M CU 1.5 MAXIMU 1 UPPLY 1.0 S 0.5 0 0 10 100 FREQUE1NkCY (Hz) 10k 100k00291-023 –40 –20 0 2T0EMPE4R0ATUR6E0 (°C) 80 100 120 00291-026 Figure 23. Maximum Output Swing vs. Frequency Figure 26. Supply Current/Amplifier vs. Temperature 3 3.50 VVSIN == 32VV p-p 3.25 TA = 25°C WING (V p-p) 2 RTAL == 2∞5°C PLIFIER (µA) 3222....02750550 S M 2.00 UT T/A 1.75 P N UT RE 1.50 O R M 1 CU 1.25 AXIMU PPLY 01..7050 M U S 0.50 0.25 0 0 10 100 FREQUE1NkCY (Hz) 10k 100k00291-024 0 0.5 1.0 1.5 2S.U0PP2L.5Y V3O.L0TA3G.5E (±4V.0) 4.5 5.0 5.5 6.0 00291-027 Figure 24. Maximum Output Swing vs. Frequency Figure 27. Supply Current/Amplifier vs. Supply Voltage 4.0 µA) 3.5 VS = 3V A2 0mV VARSVL === 1±120.05kVΩ R ( 3.0 100 CL = 50pF E 90 TA = 25°C FI PLI 2.5 M A T/ 2.0 N E R UR 1.5 C Y PL 1.0 P 10 U S 0.5 0% 0–40 –20 0 2T0EMPE4R0ATURE60 (°C) 80 100 120 00291-025 50mV 100µs 00291-028 Figure 25. Supply Current/Amplifier vs. Temperature Figure 28. Small-Signal Transient Response Rev. D | Page 10 of 20

OP281/OP481 A2 0mV VS = ±1.35V A2 0.5V VS = 2.75V AV = 1 AV = 1 RL = 100kΩ RL = 100kΩ 100 CL = 50pF 100 CL = 50pF 90 TA = 25°C 90 TA = 25°C 10 10 0% 0% 50mV 100µs 00291-029 500mV 100µs 00291-031 Figure 29. Small-Signal Transient Response Figure 31. Large-Signal Transient Response A2 2.5V VS = 5V A2 2.5V VS = 5V AV = 1 TA = 25°C RL = 100kΩ 100 CL = 50pF 100 90 TA = 25°C 90 10 10 0% 0% 1V 100µs 00291-030 1V 1V 200µs 00291-032 Figure 30. Large-Signal Transient Response Figure 32. No Phase Reversal Rev. D | Page 11 of 20

OP281/OP481 120 VS = 5V A2 0V VS = ±1.35V VIN = ±1V p-p 105 TA = 25°C RL =∞ AT = 2kHz RL = ∞ 90 100 B) d 90 N ( 75 O TI 60 A R PA 45 E S L 30 E N N 15 A H 10 C 0 0% –15 500mV 500mV 50µs 00291-033 –30100 1k FREQU1E0NkCY (Hz) 100k 1M 00291-035 Figure 33. Saturation Recovery Time Figure 35. Channel Separation vs. Frequency A2 0V CIRCUIT = AVOL VS = 2.5V TA = 25°C 100 RL =∞ 90 10 0% 1V 500mV 100µs 00291-034 Figure 34. Saturation Recovery Time Rev. D | Page 12 of 20

OP281/OP481 APPLICATIONS THEORY OF OPERATION to the lowest possible input signal excursion and can be found using the following formula: The OPx81 family of op amps is comprised of extremely low powered, rail-to-rail output amplifiers, requiring less than 4 μA of V −V R= EE IN,MIN quiescent current per amplifier. Many other competitors’ devices 0.5×10−3 may be advertised as low supply current amplifiers but draw where: significantly more current as the outputs of these devices are driven V is the negative power supply for the amplifier. to a supply rail. The supply current of the OPx81 remains under EE V is the lowest input voltage excursion expected. 4 μA even when the output is driven to either supply rail. Supply IN, MIN currents should meet the specification as long as the inputs and For example, a single channel of the OPx81 should be used with a outputs remain within the range of the power supplies. single-supply voltage of +5 V if the input signal may go as low as −1 V. Because the amplifier is powered from a single supply, V is Figure 36 shows a simplified schematic of a single channel for EE the ground; therefore, the necessary series resistance should be 2 kΩ. the OPx81. A bipolar differential pair is used in the input stage. PNP transistors are used to allow the input stage to remain INPUT OFFSET VOLTAGE linear with the common-mode range extending to ground. This The OPx81 family of op amps was designed for low offset is an important consideration for single-supply applications. voltages (less than 1 mV). The bipolar front end also contributes less noise than a MOS 100kΩ front end with only nanoamps of bias currents. The output of the op amp consists of a pair of CMOS transistors in a common +3V source configuration. This setup allows the output of the 100kΩ amplifier to swing to within millivolts of either supply rail. The 100kΩ VOUT –0.27V OP281 headroom required by the output stage is limited by the amount + VIN = 1kHz AT of current being driven into the load. The lower the output – 400mV p-p 100kΩ cFuigrurerne t1, 1th, Fe icgluorsee r1 2th, ea nodu tFpiugtu crea n1 3g os htoow ei tthheer o suutpppulty v roalitla. g e –0.1V 00291-037 headroom vs. the load current. This behavior is typical of rail- Figure 37. Single OPx81 Channel Configured as a Difference Amplifier to-rail output amplifiers. Operating at VCM < 0 V VCC INPUT COMMON-MODE VOLTAGE RANGE The OPx81 is rated with an input common-mode voltage range from V to 1 V less than V . However, the op amp can operate EE CC with a common-mode voltage that is slightly less than V . EE Figure 37 shows a single OPx81 channel configured as a difference amplifier with a single-supply voltage of 3 V. Negative dc voltages OUT are applied at both input terminals, creating a common-mode +IN voltage that is less than ground. A 400 mV p-p input signal is then applied to the noninverting input. Figure 38 shows the –IN resulting input and output waves. Notice how the output of the amplifier also drops slightly negative without distortion. VEE 00291-036 0.2ms Figure 36. Simplified Schematic of a Single OPx81 Channel 100 VOUT 90 INPUT OVERVOLTAGE PROTECTION The input stage to the OPx81 family of op amps consists of a PNP differential pair. If the base voltage of either of these input 0V transistors drops to more than 0.6 V below the negative supply, VIN the input ESD protection diodes become forward-biased, and large currents begin to flow. In addition to possibly damaging the 10 device, this creates a phase reversal effect at the output. To prevent 0% tThhisis, tchaen ibnep udto cnuer breyn sti mshpoluy lpdl abcei nligm ait reeds itsot oler sisn t shearnie 0s. 5w imthA t.h e 0.1V 00291-038 input to the device. The size of the resistor should be proportional Figure 38. Input and Output Signals with VCM < 0 V Rev. D | Page 13 of 20

OP281/OP481 CAPACITIVE LOADING WINDOW COMPARATOR Most low supply current amplifiers have difficulty driving The extremely low power supply current demands of the OPx81 capacitive loads due to the higher currents required from the family make it ideal for use in long-life battery-powered output stage for such loads. Higher capacitance at the output applications such as a monitoring system. Figure 41 shows a will increase the amount of overshoot and ringing in the amplifier’s circuit that uses the OP281 as a window comparator. step response and may affect the stability of the device. However, 3V 3V through careful design of the output stage and its high phase 3V margin, the OPx81 family can tolerate some degree of capacitive 5.1kΩ R1 loading. Figure 39 shows the step response of a single channel VH VOUT D1 10kΩ with a 10 nF capacitor connected at the output. Notice that the A1 Q1 R2 overshoot of the output does not exceed more than 10% with OP281-A 5.1kΩ such a load, even with a supply voltage of only 3 V. VIN 2kΩ 3V 3V D2 100 R3 VL A2 90 OP281-B R4 00291-041 Figure 41. Using the OP281 as a Window Comparator The threshold limits for the window are set by V and V, H L provided that V > V. The output of the first OP281 (A1) will H L 10 stay at the negative rail, in this case ground, as long as the input 0% voltage is less than V . Similarly, the output of the second H 00291-039 OhiPgh28er1 t(hAa2n) VwLi.l lA sst alyo nagt garso VuInNd r eams laoinngs btheetw inepenu tV vLo altnadg eV iHs , the Figure 39. Ringing and Overshoot of the Output of the Amplifier outputs of both op amps will be 0 V. With no current flowing in MICROPOWER REFERENCE VOLTAGE GENERATOR either D1 or D2, the base of Q1 will stay at ground, putting the transistor in cutoff and forcing V to the positive supply rail. Many single-supply circuits are configured with the circuit biased OUT If the input voltage rises above V , the output of A2 stays at to half of the supply voltage. In these cases, a false ground reference H ground, but the output of A1 goes to the positive rail and D1 can be created by using a voltage divider buffered by an amplifier. conducts current. This creates a base voltage that turns on Q1 Figure 40 shows the schematic for such a circuit. and drives V low. The same condition occurs if V falls OUT IN The two 1 MΩ resistors generate the reference voltage while below V with A2’s output going high and D2 conducting L drawing only 1.5 μA of current from a 3 V supply. A capacitor current. Therefore, V is high if the input voltage is between OUT connected from the inverting terminal to the output of the op amp V and V , but low if the input voltage moves outside of that range. L H provides compensation to allow a bypass capacitor to be The R1 and R2 voltage divider sets the upper window voltage, connected at the reference output. This bypass capacitor helps and the R3 and R4 voltage divider sets the lower voltage for the to establish an ac ground for the reference output. The entire window. For the window comparator to function properly, V reference generator draws less than 5 μA from a 3 V supply source. H must be a greater voltage than V . L 3V TO 12V R2 V = H R1+R2 10kΩ R4 0.022µF V = L R3+R4 The 2 kΩ resistor connects the input voltage of the input 2 8 terminals to the op amps. This protects the OP281 from 1MΩ OP281 1 100Ω 1V.R5EVF TO 6V possible excess current flowing into the input stages of the 3 4 1µF devices. D1 and D2 are small-signal switching diodes (1N4446 or equivalent), and Q1 is a 2N2222 or an equivalent NPN 1MΩ 1µF 00291-040 transistor. Figure 40. Single Channel Configured as a Micropower Bias Voltage Generator Rev. D | Page 14 of 20

OP281/OP481 LOW-SIDE CURRENT MONITOR R1 R2 100kΩ 100kΩ In the design of power-supply control circuits, a great deal of 3V 3V design effort is focused on ensuring the long-term reliability of 2kΩ FULL-WAVE a pass transistor over a wide range of load current conditions. A2 RECTIFIED As a result, monitoring and limiting device power dissipation is VIN = 2V p-p A1 OP281-B OUTPUT OP281-A of primary importance in these designs. Figure 42 shows an HALF-WAVE einxcaomrpploer aotfe ad 5in Vt,o s tihneg ldee-ssuigpnp loyf cau vroreltnatg em roengiutolart othr awt ictahn f obled - ROEUCTTPIUFTIED 00291-043 back current limiting or a high current power supply with Figure 43. Single-Supply Full-Wave and Half-Wave Rectifiers Using an OP281 crowbar protection. The design capitalizes on the OPx81’s common-mode range extending to ground. Current is monitored in the power-supply return path, where a 0.1 Ω shunt resistor, R , creates a very small voltage drop. The 100 SENSE 90 SCALE voltage at the inverting terminal becomes equal to the voltage at 0.1V/DIV the noninverting terminal through the feedback of Q1, which is a 2N2222 or an equivalent NPN transistor. This makes the voltage drop across R1 equal to the voltage drop across R . SENSE Therefore, the current through Q1 becomes directly proportional to the current through R , and the output SENSE 10 SCALE voltage is given by the following equation: 0.1ms/DIV 0% VOUT =VCC −⎜⎝⎛RR12×RSENSE ×IL⎟⎠⎞ 00291-044 Figure 44. Full-Wave Rectified Signal The voltage drop across R2 increases as I increases; therefore, L V decreases if a higher supply current is sensed. For the Amplifier A1 is used as a voltage follower that tracks the input OUT element values shown, the V transfer characteristic is voltage only when it is greater than 0 V. This provides a half- OUT −2.5 V/A, decreasing from V . wave rectification of the input signal to the noninverting CC VCC terminal of Amplifier A2. When A1’s output is following the input, the inverting terminal of A2 also follows the input from R2 the virtual ground between the inverting and noninverting 2.49kΩ terminals of A2. With no potential difference across R1, no VOUT current flows through either R1 or R2; therefore, the output of Q1 A2 also follows the input. When the input voltage goes below VCC 0 V, the noninverting terminal of A2 becomes 0 V. This makes A2 work as an inverting amplifier with a gain of 1 and provides SINGLE R1 COHPAx8N1NEL a full-wave rectified version of the input signal. A 2 kΩ resistor 100Ω in series with A1’s noninverting input protects the device when R0S.E1NΩSE RGERTOUURNND TO00291-042 tBhAe TinTpEutR sYig-nPaOl bWecEoRmEesD l eTssE tLhEanP HgrOouNnEd. HEADSET Figure 42. Low-Side Load Current Monitor AMPLIFIER LOW VOLTAGE HALF-WAVE AND FULL-WAVE RECTIFIERS Figure 45 shows how the OP281 can be used as a two-way amplifier in a telephone headset. One side of the OP281 can be Because of its quick overdrive recovery time, an OP281 can be used as an amplifier for the microphone, and the other side can configured as a full-wave rectifier for low frequency (<500 Hz) be used to drive the speaker. A typical telephone headset uses a applications. Figure 43 shows the schematic. 600 Ω speaker and an electret microphone that requires a supply voltage and a biasing resistor. Rev. D | Page 15 of 20

OP281/OP481 0.1µF11kΩ 300kΩ audio bandwidth. A 2.2 kΩ resistor is used to bias the electret microphone. This resistor value may vary depending on the 3V 3V 3V specifications of the microphone. The output of the microphone is 1µF 2.2kΩ 1µF 1MΩ MIC OUT ac-coupled to the noninverting terminal of the op amp. Two 1 MΩ resistors are used to provide the dc offset for single-supply use. OP281-A ELECTRET1MΩ MIC The OP281-B amplifier (see Figure 45) can provide up to 15 dB of gain for the headset speaker. Incoming audio signals are ac-coupled 1µF 10kΩ 50kΩ to a 10 kΩ potentiometer that is used to adjust the volume. Again, two 1 MΩ resistors provide the dc offset with a 1 μF capacitor 3V establishing an ac ground for the volume-control potentiometer. Because the OP281 is a rail-to-rail output amplifier, it would have difficulty driving a 600 Ω speaker directly. Here, a Class AB buffer 20kΩ 3V is used to isolate the load from the amplifier and to provide the Q1 INPUT1µF necessary current to drive the speaker. By placing the buffer in 1µF the feedback loop of the op amp, crossover distortion can be 3V 1P0OkΩT. OP281-B minimized. Q1 and Q2 should have minimum betas of 100. The Q2 600 Ω speaker is ac-coupled to the emitters to prevent quiescent 600Ω 1M1ΩµF 1MΩ 20kΩ SPEAKER 00291-045 cmuarkreens ta fnr oemqu filvoawleinntg h iingtho- tphaes ss pfieltaekre cr.u Ttohfef a1t μ2F6 5c oHuzp wlinitgh c aa p6a0c0i tΩor Figure 45. Two-Way Amplifier in a Battery-Powered Telephone Headset load attached. Again, this does not pose a problem because it is outside the frequency range for telephone audio signals. The OP281-A op amp provides about 29 dB of gain for audio signals coming from the microphone. The gain is set by the The circuit in Figure 45 draws around 250 μA of current. The 300 kΩ and 11 kΩ resistors. The gain bandwidth product of the Class AB buffer has a quiescent current of 140 μA, and roughly amplifier is 95 kHz, which yields a −3 dB rolloff at 3.4 kHz for 100 μA is drawn by the microphone itself. A CR2032 3 V the set gain of 28. This is acceptable because telephone audio is lithium battery has a life expectancy of 160 mA hours, which band limited for 300 kHz to 3 kHz signals. If higher gain is means this circuit can run continuously for 640 hours on a required for the microphone, an additional gain stage should be single battery. used, because adding more gain to the OP281 would limit the Rev. D | Page 16 of 20

OP281/OP481 OUTLINE DIMENSIONS 5.00(0.1968) 4.80(0.1890) 8 5 4.00 (0.1574) 6.20 (0.2441) 3.80 (0.1497) 1 4 5.80 (0.2284) 1.27 (0.0500) 0.50 (0.0196) BSC 1.75 (0.0688) 0.25 (0.0099) 45° 0.25 (0.0098) 1.35 (0.0532) 8° 0.10 (0.0040) 0° COPLANARITY 0.51 (0.0201) 0.10 SEATING 0.31 (0.0122) 0.25 (0.0098) 10..2470 ((00..00510507)) PLANE 0.17 (0.0067) COMPLIANTTO JEDEC STANDARDS MS-012-AA C(RINOEFNPETARRREOENNLCLTEIHN EOGSN DELSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO MPFRIFLO LMPIIMRLELIATIMTEEER TFSEO; RIRN ECUQHSU EDI VIINMA LEDENENSSTIIOGSN NFS.OR 012407-A Figure 46. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 8.75 (0.3445) 8.55 (0.3366) 4.00 (0.1575) 14 8 6.20 (0.2441) 3.80 (0.1496) 1 7 5.80 (0.2283) 1.27 (0.0500) 0.50 (0.0197) BSC 1.75 (0.0689) 0.25 (0.0098) 45° 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.10 0.51 (0.0201) PLANE 0.25 (0.0098) 1.27 (0.0500) 0.31 (0.0122) 0.17 (0.0067) 0.40 (0.0157) COMPLIANTTO JEDEC STANDARDS MS-012-AB C(RINOEFNPETARRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO MPFRIFLO LMPIIMRLELIATIMTEEER TFSEO; RIRN ECUQHSU EDI VIINMA LEDENENSSTIIOGSN NFS.OR 060606-A Figure 47. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) Rev. D | Page 17 of 20

OP281/OP481 3.10 3.00 2.90 8 5 4.50 4.40 6.40 BSC 4.30 1 4 PIN 1 0.65 BSC 0.15 1.20 0.05 MAX 8° COPLANARITY 0.30 SEATING 0.20 0° 0.75 0.10 0.19 PLANE 0.09 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AA Figure 48. 8-Lead Thin Shrink Small Outline Package [TSSOP] (RU-8) Dimensions shown in millimeters 5.10 5.00 4.90 14 8 4.50 4.40 6.40 BSC 4.30 1 7 PIN 1 1.05 0.65 1.00 BSC 0.20 0.80 1M.A20X 0.09 0.75 00..1055 00..3109 SPELAANTIENG COPLANARITY80°° 00..6405 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 49. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option OP281GRU-REEL –40°C to +85°C 8-Lead TSSOP RU-8 OP281GRUZ-REEL1 –40°C to +85°C 8-Lead TSSOP RU-8 OP281GS –40°C to +85°C 8-Lead SOIC_N R-8 OP281GS-REEL –40°C to +85°C 8-Lead SOIC_N R-8 OP281GS-REEL7 –40°C to +85°C 8-Lead SOIC_N R-8 OP281GSZ1 –40°C to +85°C 8-Lead SOIC_N R-8 OP281GSZ-REEL1 –40°C to +85°C 8-Lead SOIC_N R-8 OP281GSZ-REEL71 –40°C to +85°C 8-Lead SOIC_N R-8 OP481GRU-REEL –40°C to +85°C 14-Lead TSSOP RU-14 OP481GRUZ-REEL1 –40°C to +85°C 14-Lead TSSOP RU-14 OP481GS –40°C to +85°C 14-Lead SOIC_N R-14 OP481GS-REEL –40°C to +85°C 14-Lead SOIC_N R-14 OP481GS-REEL7 –40°C to +85°C 14-Lead SOIC_N R-14 OP481GSZ1 –40°C to +85°C 14-Lead SOIC_N R-14 OP481GSZ-REEL1 –40°C to +85°C 14-Lead SOIC_N R-14 OP481GSZ-REEL71 –40°C to +85°C 14-Lead SOIC_N R-14 1 Z = RoHS Compliant Part. Rev. D | Page 18 of 20

OP281/OP481 NOTES Rev. D | Page 19 of 20

OP281/OP481 NOTES ©1996–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00291-0-9/08(D) Rev. D | Page 20 of 20

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: OP281GSZ-REEL7 OP281GRUZ-REEL OP481GSZ-REEL7 OP481GRUZ-REEL OP481GSZ OP281GSZ