NCP5106A, NCP5106B High Voltage, High and Low Side Driver The NCP5106 is a high voltage gate driver IC providing two outputs for direct drive of 2 N−channel power MOSFETs or IGBTs arranged in a half−bridge configuration version B or any other high−side + low−side configuration version A. www.onsemi.com It uses the bootstrap technique to ensure a proper drive of the high−side power switch. The driver works with 2 independent inputs. MARKING Features DIAGRAMS • High Voltage Range: Up to 600 V 1 8 • dV/dt Immunity ±50 V/nsec SOIC−8 5106x • Negative Current Injection Characterized Over the Temperature Range D SUFFIX ALYW CASE 751 (cid:2) • Gate Drive Supply Range from 10 V to 20 V 1 • High and Low Drive Outputs • Output Source / Sink Current Capability 250 mA / 500 mA • 3.3 V and 5 V Input Logic Compatible NCP5106x 1 • AWL Up to VCC Swing on Input Pins PDIP−8 YYWWG • Extended Allowable Negative Bridge Pin Voltage Swing to −10 V P SUFFIX CASE 626 for Signal Propagation • Matched Propagation Delays Between Both Channels • Outputs in Phase with the Inputs • 1 5106x Independent Logic Inputs to Accommodate All Topologies (Version A) DFN10 ALYW(cid:2) • Cross Conduction Protection with 100 ns Internal Fixed Dead Time MN SUFFIX (cid:2) CASE 506DJ (Version B) • Under VCC LockOut (UVLO) for Both Channels NCP5106 = Specific Device Code • x = A or B version Pin−to−Pin Compatible with Industry Standards A = Assembly Location • These are Pb−Free Devices L or WL = Wafer Lot Y or YY = Year Typical Applications W or WW = Work Week • Half−Bridge Power Converters G or (cid:2) = Pb−Free Package • Any Complementary Drive Converters (Asymmetrical Half−Bridge, (Note: Microdot may be in either location) Active Clamp) (A Version Only). • Full−Bridge Converters PINOUT INFORMATION VCC 1 VBOOT IN_HI DRV_HI IN_LO BRIDGE GND DRV_LO 8 Pin Package VCC 1 VBOOT IN_HI NC IN_LO DRV_HI GND NC DRV_LO BRIDGE 10 Pin DFN Package ORDERING INFORMATION See detailed ordering and shipping information on page 16 of this data sheet. © Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: February, 2017 − Rev. 9 NCP5106/D

NCP5106A, NCP5106B + Vbulk C1 GND D4 Q1 T1 D1 L1 Out+ Vcc C3 U1 C4 + GND C3 Vcc VBOOT IN_HI DRV_HI Lf NCP1395 Out− IN_LO Bridge D2 GND DRV_LO C6 NCP5106 Q2 GND GND GND R1 D3 GND U2 Figure 1. Typical Application Resonant Converter (LLC type) + Vbulk C1 C5 GND D4 Q1 Vcc C3 T1 D1 L1 Out+ GND U1 C4 + Vcc VBOOT C3 IN_HI DRV_HI MC34025 IN_LO Bridge Out− GND DRV_LO D2 C6 NCP5106 GND Q2 GND GND R1 D3 GND U2 Figure 2. Typical Application Half Bridge Converter www.onsemi.com 2

NCP5106A, NCP5106B VCC VCC VBOOT UV DETECT IN_HI PULSE LEVEL S Q DRV_HI TRIGGER SHIFTER R Q BRIDGE GND UV GND DETECT VCC IN_LO DRV_LO DELAY GND GND GND GND GND Figure 3. Detailed Block Diagram: Version A VCC VCC VBOOT UV DETECT IN_HI PULSE LEVEL S Q DRV_HI TRIGGER SHIFTER R Q BRIDGE CROSS GND UV GND CONDUCTION DETECT VCC PREVENTION DRV_LO IN_LO DELAY GND GND GND Figure 4. Detailed Block Diagram: Version B PIN DESCRIPTION Pin Name Description ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ IN_HI Logic Input for High Side Driver Output in Phase ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ IN_LO Logic Input for Low Side Driver Output in Phase ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ GND Ground ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DRV_LO Low Side Gate Drive Output ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁVÁÁCCÁÁÁÁÁÁÁÁÁÁÁÁÁÁLowÁÁ SideÁÁ andÁÁ MaÁÁin PoÁÁwerÁÁ SupÁÁply ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁVÁÁBOOÁÁT ÁÁÁÁÁÁÁÁÁÁÁÁBooÁÁtstraÁÁp PoÁÁwer ÁÁSuppÁÁly ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DRV_HI High Side Gate Drive Output ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BRIDGE Bootstrap Return or High Side Floating Supply Return ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ NC Removed for creepage distance (DFN package only) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ www.onsemi.com 3

NCP5106A, NCP5106B MAXIMUM RATINGS Rating Symbol Value Unit VCC Main power supply voltage −0.3 to 20 V VCC_transient Main transient power supply voltage: 23 V IVCC_max = 5 mA during 10 ms VBRIDGE VHV: High Voltage BRIDGE pin −1 to 600 V VBRIDGE Allowable Negative Bridge Pin Voltage for IN_LO Signal Propagation to DRV_LO −10 V (see characterization curves for detailed results) VBOOT−VBRIDGE VHV: Floating supply voltage −0.3 to 20 V VDRV_HI VHV: High side output voltage VBRIDGE − 0.3 to V VBOOT + 0.3 VDRV_LO Low side output voltage −0.3 to VCC + 0.3 V dVBRIDGE/dt Allowable output slew rate 50 V/ns VIN_XX Inputs IN_HI, IN_LO −1.0 to VCC + 0.3 V ESD Capability: − HBM model (all pins except pins 6−7−8 in 8 pins 2 kV package or 11−12−13 in 14 pins package) − Machine model (all pins except pins 6−7−8 in 8 pins 200 V package or 11−12−13 in 14 pins package) Latch up capability per JEDEC JESD78 R(cid:2)JA Power dissipation and Thermal characteristics °C/W PDIP−8: Thermal Resistance, Junction−to−Air 100 SO−8: Thermal Resistance, Junction−to−Air 178 DFN10 4x4: Thermal Resistance, Junction−to−Ambient 1 Oz Cu 162 DFN10 4x4: 50 mm2 Printed Circuit Copper Clad TST Storage Temperature Range −55 to +150 °C TJ_max Maximum Operating Junction Temperature +150 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 4

NCP5106A, NCP5106B ELECTRICAL CHARACTERISTIC (VCC = Vboot = 15 V, VGND = Vbridge, −40°C < TJ < 125°C, Outputs loaded with 1 nF) TJ −40°C to 125°C Rating Symbol Min Typ Max Units OUTPUT SECTION Output high short circuit pulsed current VDRV = 0 V, PW (cid:2) 10 (cid:3)s (Note 1) IDRVsource − 250 − mA Output low short circuit pulsed current VDRV = VCC, PW (cid:2) 10 (cid:3)s (Note 1) IDRVsink − 500 − mA Output resistor (Typical value @ 25°C) Source ROH − 30 60 (cid:4) Output resistor (Typical value @ 25°C) Sink ROL − 10 20 (cid:4) High level output voltage, VBIAS−VDRV_XX @ IDRV_XX = 20 mA VDRV_H − 0.7 1.6 V Low level output voltage VDRV_XX @ IDRV_XX = 20 mA VDRV_L − 0.2 0.6 V DYNAMIC OUTPUT SECTION Turn−on propagation delay (Vbridge = 0 V) tON − 100 170 ns Turn−off propagation delay (Vbridge = 0 V or 50 V) (Note 2) tOFF − 100 170 ns Output voltage rise time (from 10% to 90% @ VCC = 15 V) with 1 nF load tr − 85 160 ns Output voltage fall time (from 90% to 10% @VCC = 15 V) with 1 nF load tf − 35 75 ns Propagation delay matching between the High side and the Low side @ 25°C (Note 3) (cid:5)t − 20 35 ns Internal fixed dead time (only valid for B version) (Note 4) DT 65 100 190 ns Minimum input width that changes the output tPW1 − − 50 ns Maximum input width that does not change the output SOIC−8, PDIP−8 tPW2 20 − − ns DFN10 15 − − INPUT SECTION Low level input voltage threshold VIN − − 0.8 V Input pull−down resistor (VIN < 0.5 V) RIN − 200 − k(cid:4) High level input voltage threshold VIN 2.3 − − V Logic “1” input bias current @ VIN_XX = 5 V @ 25°C IIN+ − 5 25 (cid:3)A Logic “0” input bias current @ VIN_XX = 0 V @ 25°C IIN− − − 2.0 (cid:3)A SUPPLY SECTION VCC UV Start−up voltage threshold VCC_stup 8.0 8.9 9.9 V VCC UV Shut−down voltage threshold VCC_shtdwn 7.3 8.2 9.1 V Hysteresis on VCC VCC_hyst 0.3 0.7 − V Vboot Start−up voltage threshold reference to bridge pin Vboot_stup 8.0 8.9 9.9 V (Vboot_stup = Vboot − Vbridge) Vboot UV Shut−down voltage threshold Vboot_shtdwn 7.3 8.2 9.1 V Hysteresis on Vboot Vboot_hyst 0.3 0.7 − V Leakage current on high voltage pins to GND IHV_LEAK − 5 40 (cid:3)A (VBOOT = VBRIDGE = DRV_HI = 600 V) Consumption in active mode (VCC = Vboot, fsw = 100 kHz and 1 nF load on both driv- ICC1 − 4 5 mA er outputs) Consumption in inhibition mode (VCC = Vboot) ICC2 − 250 400 (cid:3)A VCC current consumption in inhibition mode ICC3 − 200 − (cid:3)A Vboot current consumption in inhibition mode ICC4 − 50 − (cid:3)A 1. Parameter guaranteed by design. 2. Turn−off propagation delay @ Vbridge = 600 V is guaranteed by design. 3. See characterization curve for (cid:5)t parameters variation on the full range temperature. 4. Version B integrates a dead time in order to prevent any cross conduction between DRV_HI and DRV_LO. See timing diagram of Figure 10. 5. Timing diagram definition see: Figure 7, Figure 8 and Figure 9. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 5

NCP5106A, NCP5106B IN_HI IN_LO DRV_HI DRV_LO Figure 5. Input/Output Timing Diagram (A Version) IN_HI IN_LO DRV_HI DRV_LO Figure 6. Input/Output Timing Diagram (B Version) IN_HI 50% 50% (IN_LO) tr tf ton toff 90% 90% DRV_HI (DRV_LO) 10% 10% Figure 7. Propagation Delay and Rise / Fall Time Definition www.onsemi.com 6

NCP5106A, NCP5106B IN_LO & 50% 50% IN_HI ton_HI toff_HI Delta_t 90% DRV_HI 10% ton_LO Delta_t toff_LO 90% DRV_LO Matching Delay 1 = ton_HI − ton_LO 10% Matching Delay 2 = toff_LO − toff_HI Figure 8. Matching Propagation Delay (A Version) IN_HI 50% 50% toff_HI ton_HI 90% DRV_HI 10% Matching Delay1=ton_HI−ton_LO Matching Delay2=toff_HI−toff_LO IN_LO 50% 50% toff_LO ton_LO 90% DRV_LO 10% Figure 9. Matching Propagation Delay (B Version) www.onsemi.com 7

NCP5106A, NCP5106B IN_HI IN_LO DRV_HI DRV_LO Internal Deadtime Internal Deadtime Figure 10. Input/Output Cross Conduction Output Protection Timing Diagram (B Version) www.onsemi.com 8

NCP5106A, NCP5106B CHARACTERIZATION CURVES 140 140 ns) 120 ns) 120 TON Low Side Y ( TON High Side Y ( A A L 100 L 100 E E D D N 80 N 80 O O TI TI A A G 60 G 60 PA PA TON High Side RO 40 TON Low Side RO 40 P P , ON 20 , ON 20 T T 0 0 10 12 14 16 18 20 −40 −20 0 20 40 60 80 100 120 VCC, VOLTAGE (V) TEMPERATURE (°C) Figure 11. Turn ON Propagation Delay vs. Figure 12. Turn ON Propagation Delay vs. Supply Voltage (V = V ) Temperature CC BOOT 140 140 ns) 120 ns) 120 LAY ( 100 TOFF Low Side LAY ( 100 TOFF Low Side E E D D ON 80 ON 80 TOFF High Side TI TI A A G 60 G 60 A A P P RO 40 TOFF High Side RO 40 P P , F , F OF 20 OF 20 T T 0 0 10 12 14 16 18 20 −40 −20 0 20 40 60 80 100 120 VCC, VOLTAGE (V) TEMPERATURE (°C) Figure 13. Turn OFF Propagation Delay vs. Figure 14. Turn OFF Propagation Delay vs. Supply Voltage (V = V ) Temperature CC BOOT 140 160 ns) 120 ns) 140 Y ( Y ( A A 120 L 100 L E E ON D 80 ON D 100 TI TI 80 A A G 60 G A A 60 P P O O PR 40 PR 40 , ON 20 OFF 20 T T 0 0 0 10 20 30 40 50 0 10 20 30 40 50 BRIDGE PIN VOLTAGE (V) BRIDGE PIN VOLTAGE (V) Figure 15. High Side Turn ON Propagation Figure 16. High Side Turn OFF Propagation Delay vs. VBRIDGE Voltage Delay vs. VBRIDGE Voltage www.onsemi.com 9

NCP5106A, NCP5106B CHARACTERIZATION CURVES 160 140 140 120 s)120 ME (n100 tr High Side E (ns) 100 tr Low Side TI M 80 RISE 80 SETI 60 , N 60 RI tr High Side TO 40 T, ON 40 tr Low Side 20 20 0 0 10 12 14 16 18 20 −40 −20 0 20 40 60 80 100 120 VCC, VOLTAGE (V) TEMPERATURE (°C) Figure 17. Turn ON Risetime vs. Supply Figure 18. Turn ON Risetime vs. Temperature Voltage (V = V ) CC BOOT 80 70 70 60 60 s) s) 50 E (n 50 tf Low Side E (n tf High Side M M 40 TI 40 TI L L AL AL 30 F 30 F , F , F TOF 20 TOF 20 10 tf High Side 10 tf Low Side 0 0 10 12 14 16 18 20 −40 −20 0 20 40 60 80 100 120 VCC, VOLTAGE (V) TEMPERATURE (°C) Figure 19. Turn OFF Falltime vs. Supply Figure 20. Turn OFF Falltime vs. Temperature Voltage (V = V ) CC BOOT 20 200 s) n G ( 180 N 160 HI 15 C AT s) 140 Y M E (n 120 ELA 10 TIM 100 D D 80 N A O DE 60 ATI 5 G 40 A P O 20 R P 0 0 −40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 21. Propagation Delay Matching Figure 22. Dead Time vs. Temperature Between High Side and Low Side Driver vs. Temperature www.onsemi.com 10

NCP5106A, NCP5106B CHARACTERIZATION CURVES 1.4 1.4 V) OLD ( 1.2 E 1.2 G H ES 1 LTA 1.0 R OV) E TH 0.8 UT VLD ( 0.8 G PO LTA 0.6 L INESH 0.6 O ER T V 0.4 EVTH 0.4 PU W L N 0.2 O 0.2 L I L E EV 0 0.0 L 10 12 14 16 18 20 −40 −20 0 20 40 60 80 100 120 W O VCC, VOLTAGE (V) TEMPERATURE (°C) L Figure 23. Low Level Input Voltage Threshold Figure 24. Low Level Input Voltage Threshold vs. Supply Voltage (V = V ) vs. Temperature CC BOOT 2.5 2.5 E E G 2 G 2.0 A A T T L L OV) OV) T VD (1.5 T VD ( 1.5 UL UL PO PO NH NH L IES 1 L IES 1.0 ER ER VH VH LET LET H 0.5 H 0.5 G G HI HI 0 0.0 10 12 14 16 18 20 −40 −20 0 20 40 60 80 100 120 VCC, VOLTAGE (V) TEMPERATURE (°C) Figure 25. High Level Input Voltage Threshold Figure 26. High Level Input Voltage Threshold vs. Supply Voltage (V = V ) vs. Temperature CC BOOT 4 6 5.5 A)3.5 A) (cid:3)NT ( 3 (cid:3)NT ( 4.55 RE RE 4 R2.5 R U U 3.5 C C T 2 T 3 U U P P 2.5 N1.5 N C “0” I 1 C “0” I 1.52 GI GI 1 O0.5 O L L 0.5 0 0 10 12 14 16 18 20 −40 −20 0 20 40 60 80 100 120 VCC, VOLTAGE (V) TEMPERATURE (°C) Figure 27. Logic “0” Input Current vs. Supply Figure 28. Logic “0” Input Current vs. Voltage (V = V ) Temperature CC BOOT www.onsemi.com 11

NCP5106A, NCP5106B CHARACTERIZATION CURVES 8 10 A) 7 A) (cid:3) (cid:3) NT ( 6 NT ( 8 E E R R UR 5 UR 6 C C T 4 T U U NP 3 NP 4 1” I 1” I C “ 2 C “ GI GI 2 O 1 O L L 0 0 10 12 14 16 18 20 −40 −20 0 20 40 60 80 100 120 VCC, VOLTAGE (V) TEMPERATURE (°C) Figure 30. Logic “1” Input Current vs. Figure 29. Logic “1” Input Current vs. Supply Temperature Voltage (V = V ) CC BOOT 1 1.0 E V) TAG 0.8 GE (0.8 L A VOV) LT UT D ( 0.6 VO0.6 UTPHOL PUT OS T VEL THRE 0.4 L OU0.4 E E L V W 0.2 E0.2 L O W L O 0 L0.0 10 12 14 16 18 20 −40 −20 0 20 40 60 80 100 120 VCC, VOLTAGE (V) TEMPERATURE (°C) Figure 31. Low Level Output Voltage vs. Figure 32. Low Level Output Voltage vs. Supply Voltage (V = V ) Temperature CC BOOT 1.6 1.6 E V) TAG GE ( L 1.2 A1.2 O T UTPUT VHOLD (V) 0.8 PUT VOL0.8 L ORES OUT VEH L ET E L 0.4 V0.4 H LE G H HI G HI 0 0.0 10 12 14 16 18 20 −40 −20 0 20 40 60 80 100 120 VCC, VOLTAGE (V) TEMPERATURE (°C) Figure 33. High Level Output Voltage vs. Figure 34. High Level Output Voltage vs. Supply Voltage (V = V ) Temperature CC BOOT www.onsemi.com 12

NCP5106A, NCP5106B CHARACTERIZATION CURVES 400 400 A) A) T (m 350 Isrc High Side T (m 350 Isrc High Side N 300 N 300 E E R R UR 250 UR 250 C C E 200 Isrc Low Side E 200 C C OUR 150 OUR 150 Isrc Low Side S S UT 100 UT 100 P P T T U 50 U 50 O O 0 0 10 12 14 16 18 20 −40 −20 0 20 40 60 80 100 120 VCC, VOLTAGE (V) TEMPERATURE (°C) Figure 35. Output Source Current vs. Supply Figure 36. Output Source Current vs. Voltage (V = V ) Temperature CC BOOT 600 600 Isink High Side Isink High Side mA) 500 A) 500 NT ( T (m E 400 N 400 R E UR Isink Low Side RR C 300 U 300 NK K C Isink Low Side UT SI 200 T SIN 200 P U T P U 100 T 100 O U O 0 0 10 12 14 16 18 20 −40 −20 0 20 40 60 80 100 120 VCC, VOLTAGE (V) TEMPERATURE (°C) Figure 37. Output Sink Current vs. Supply Figure 38. Output Sink Current vs. Voltage (V = V ) Temperature CC BOOT 0.2 20 N O A) T H(cid:3) RENA)0.16 HIGND (15 UR(cid:3)D ( ON o G E CGN0.12 NT V) t SIDE LEAKAGHV PINS TO 00..0048 KAGE CURREGE PINS (600 105 GH EALTA HI LVO 0 0 0 100 200 300 400 500 600 −40 −20 0 20 40 60 80 100 120 HV PINS VOLTAGE (V) TEMPERATURE (°C) Figure 39. Leakage Current on High Voltage Figure 40. Leakage Current on High Voltage Pins (600 V) to Ground vs. V Voltage Pins (600 V) to Ground vs. Temperature BRIDGE (V = V = V ) (VBRIDGE = V = V = 600 V) BRIGDE BOOT DRV_HI BOOT DRv_HI www.onsemi.com 13

NCP5106A, NCP5106B CHARACTERIZATION CURVES 100 100 (cid:3)NT (A) 80 (cid:3)PLY (A) 80 E P R U R 60 S 60 CU NT Y E L R P 40 R 40 SUPOOT 20 OOT CU 20 B B V V 0 0 0 4 8 12 16 20 −40 −20 0 20 40 60 80 100 120 VBOOT, VOLTAGE (V) TEMPERATURE (°C) Figure 41. V Supply Current vs. Bootstrap Figure 42. V Supply Current vs. BOOT BOOT Supply Voltage Temperature 240 400 A)200 A) (cid:3)NT (160 (cid:6)(cid:3)LY 300 E P R P R U U S C120 T 200 Y N L E P R P 80 R U U V SCC 40 V CCC100 0 0 0 4 8 12 16 20 −40 −20 0 20 40 60 80 100 120 VCC, VOLTAGE (V) TEMPERATURE (°C) Figure 43. V Supply Current vs. V Supply Figure 44. V Supply Current vs. Temperature CC CC CC Voltage 10.0 9.0 9.8 8.8 VCC UVLO Shutdown GE (V) 9.6 VCC UVLO Startup E (V) 8.6 A 9.4 G 8.4 T A L T O 9.2 L 8.2 V O UP 9.0 N V 8.0 ART 8.8 OW 7.8 VBOOT UVLO Shutdown T D S 8.6 T 7.6 VLO 8.4 VBOOT UVLO Startup SHU 7.4 U O 8.2 L 7.2 V U 8.0 7.0 −40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 45. UVLO Startup Voltage vs. Figure 46. UVLO Shutdown Voltage vs. Temperature Temperature www.onsemi.com 14

NCP5106A, NCP5106B CHARACTERIZATION CURVES 25 40 mA) CLOAD = 1 nF/Q = 15 nC mA) 35 CLOAD = 2.2 nF/Q = 33 nC RGATE = 0 R Y ( 20 Y ( PL PL 30 P P U U S S 25 T 15 T RGATE = 10 R N N E E 20 R R UR 10 UR 15 RGATE = 22 R C C OOT OOT 10 B 5 B + IC RGATE = 0 R to 22 R + IC 5 C C I I 0 0 0 100 200 300 400 500 600 0 100 200 300 400 500 600 SWITCHING FREQUENCY (kHz) SWITCHING FREQUENCY (kHz) Figure 47. I Consumption vs. Switching Figure 48. I Consumption vs. Switching CC1 CC1 Frequency with 15 nC Load on Each Driver @ Frequency with 33 nC Load on Each Driver @ V = 15 V V = 15 V CC CC 70 120 Y (mA) 60 CLOAD = 3.3 nF/Q = 50 nC RGATE = 0 R Y (mA) 100 CLOAD = 6.6 nF/Q = 100 nC RGATE = 0 R L L PP 50 PP U U 80 S S T 40 T EN RGATE = 10 R EN 60 RGATE = 10 R R R R 30 R U U C RGATE = 22 R C 40 OT 20 OT RGATE = 22 R O O + IB 10 + IB 20 C C C C I I 0 0 0 100 200 300 400 500 600 0 100 200 300 400 500 600 SWITCHING FREQUENCY (kHz) SWITCHING FREQUENCY (kHz) Figure 49. I Consumption vs. Switching Figure 50. I Consumption vs. Switching CC1 CC1 Frequency with 50 nC Load on Each Driver @ Frequency with 100 nC Load on Each Driver @ V = 15 V V = 15 V CC CC 0 0 V) V) E ( −5 −40°C E ( −5 −40°C G G A A T −10 T −10 OL 25°C OL V V 25°C E −15 E −15 S S L L PU −20 125°C PU −20 E E 125°C V V TI −25 TI −25 A A G G NE −30 NE −30 −35 −35 0 100 200 300 400 500 600 0 100 200 300 400 500 600 NEGATIVE PULSE DURATION (ns) NEGATIVE PULSE DURATION (ns) Figure 51. NCP5106A, Negative Voltage Safe Figure 52. NCP5106B, Negative Voltage Safe Operating Area on the Bridge Pin Operating Area on the Bridge Pin www.onsemi.com 15

NCP5106A, NCP5106B APPLICATION INFORMATION Negative Voltage Safe Operating Area Summary: When the driver is used in a half bridge configuration, it • If the negative pulse characteristic (negative voltage is possible to see negative voltage appearing on the bridge level & pulse width) is above the curves the driver pin (pin 6) during the power MOSFETs transitions. When runs in safe operating area. the high−side MOSFET is switched off, the body diode of • If the negative pulse characteristic (negative voltage the low−side MOSFET starts to conduct. The negative level & pulse width) is below one or all curves the voltage applied to the bridge pin thus corresponds to the driver will NOT run in safe operating area. forward voltage of the body diode. However, as pcb copper Note, each curve of the Figure 51 (or 52) represents the tracks and wire bonding introduce stray elements negative voltage and width level where the driver starts to (inductance and capacitor), the maximum negative voltage fail at the corresponding die temperature. of the bridge pin will combine the forward voltage and the If in the application the bridge pin is too close of the safe oscillations created by the parasitic elements. As any operating limit, it is possible to limit the negative voltage CMOS device, the deep negative voltage of a selected pin to the bridge pin by inserting one resistor and one diode as can inject carriers into the substrate, leading to an erratic follows: behavior of the concerned component. ON Semiconductor provides characterization data of its half−bridge driver to Vcc D2 show the maximum negative voltage the driver can safely Vbulk operate with. To prevent the negative injection, it is the MUR160 U1 C1 designer duty to verify that the amount of negative voltage NCP5106A 100n M1 pertinent to his/her application does not exceed the 1 8 VCC VBOOT characterization curve we provide, including some safety 2 7 IN_Hi IN_HI DRV_HI margin. R1 3 6 In order to estimate the maximum negative voltage IN_LO IN_LO BRIDGE accepted by the driver, this parameter has been 0 4 GND DRV_LO 5 10R M2 characterized over full the temperature range of the component. A test fixture has been developed in which we purposely negatively bias the bridge pin during the D1 MUR160 freewheel period of a buck converter. When the upper gate voltage shows signs of an erratic behavior, we consider the 0 limit has been reached. Figure 53. R1 and D1 Improves the Robustness of the Figure 51 (or 52), illustrates the negative voltage safe Driver operating area. Its interpretation is as follows: assume a negative 10 V pulse featuring a 100 ns width is applied on R1 and D1 should be placed as close as possible of the the bridge pin, the driver will work correctly over the whole driver. D1 should be connected directly between the bridge die temperature range. Should the pulse swing to −20 V, pin (pin 6) and the ground pin (pin 4). By this way the keeping the same width of 100 ns, the driver will not work negative voltage applied to the bridge pin will be limited properly or will be damaged for temperatures below by D1 and R1 and will prevent any wrong behavior. 125°C. ORDERING INFORMATION Device Package Shipping† NCP5106APG PDIP−8 (Pb−Free) 50 Units / Rail NCP5106ADR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel NCP5106BPG PDIP−8 (Pb−Free) 50 Units / Rail NCP5106BDR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel NCP5106AMNTWG DFN10 (Pb−Free) 4000 / Tape & Reel NCP5106BMNTWG DFN10 (Pb−Free) 4000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 16

NCP5106A, NCP5106B PACKAGE DIMENSIONS 8 LEAD PDIP CASE 626−05 ISSUE N D A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. E 2. CONTROLLING DIMENSION: INCHES. H 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK- AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 8 5 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT E1 TO EXCEED 0.10 INCH. 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM 1 4 PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE NOTE 8 c LEADS UNCONSTRAINED. b2 B 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE END VIEW LEADS, WHERE THE LEADS EXIT THE BODY. TOP VIEW WITH LEADS CONSTRAINED 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). NOTE 5 INCHES MILLIMETERS A2 DIM MIN MAX MIN MAX e/2 A A −−−− 0.210 −−− 5.33 NOTE 3 A1 0.015 −−−− 0.38 −−− A2 0.115 0.195 2.92 4.95 L b 0.014 0.022 0.35 0.56 b2 0.060 TYP 1.52 TYP C 0.008 0.014 0.20 0.36 D 0.355 0.400 9.02 10.16 SEATING A1 PLANE D1 0.005 −−−− 0.13 −−− E 0.300 0.325 7.62 8.26 C M E1 0.240 0.280 6.10 7.11 D1 e 0.100 BSC 2.54 BSC e eB eB −−−− 0.430 −−− 10.92 L 0.115 0.150 2.92 3.81 8Xb END VIEW M −−−− 10° −−− 10° 0.010 M C A M B M NOTE 6 SIDE VIEW www.onsemi.com 17

NCP5106A, NCP5106B PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 NOTES: ISSUE AK −X− 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. A 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) 8 5 PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL 1 IN EXCESS OF THE D DIMENSION AT −Y− 4 K 6. M75A1X−I0M1U TMH RMUA T7E51R−IA06L CAROEN DOIBTSIOONL.ETE. NEW STANDARD IS 751−07. G MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.80 5.00 0.189 0.197 C NX 45(cid:3) B 3.80 4.00 0.150 0.157 SEATING C 1.35 1.75 0.053 0.069 PLANE D 0.33 0.51 0.013 0.020 −Z− G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 0.10 (0.004) J 0.19 0.25 0.007 0.010 H D M J K 0.40 1.27 0.016 0.050 M 0 (cid:3) 8 (cid:3) 0 (cid:3) 8 (cid:3) N 0.25 0.50 0.010 0.020 0.25 (0.010)M Z Y S X S S 5.80 6.20 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 4.0 0.275 0.155 0.6 1.270 0.024 0.050 (cid:3) (cid:4) mm SCALE 6:1 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 18

NCP5106A, NCP5106B PACKAGE DIMENSIONS DFN10 4x4, 0.8P CASE 506DJ ISSUE O D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. L L 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM THE L1 TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS ÇÇÇÇ ALTERNATE A−1 ALTERNATE A−2 WELL AS THE TERMINALS. PIN ONE E DETAIL A 5. FOR DEVICE OPN CONTAINING W OPTION, DETAIL A REFERENCEÇÇÇÇ ALTERNATE TERMINAL ALTERNATE CONSTRUCTION A−2 AND DETAIL B AL- CONSTRUCTIONS TERNATE CONSTRUCTION B−2 ARE NOT APPLICABLE. ÇÇÇÇ MILLIMETERS 2X A3 DIM MIN MAX 0.10 CÇÇÇÇ A1ÉÉ EXPOSEDÉ Cu ÉÉMOLD CMPD A 0.80 1.00 A1 0.00 0.05 ÉÇÉÇ ÉÇÉÇÉÇ A3 0.20 REF 2X 0.10 C TOP VIEW b 0.25 0.35 D 4.00 BSC D2 2.90 3.10 0.10 C DETAIL B A ALTERNATE B−1 ALTERNATE B−2 E 4.00 BSC E2 1.85 2.05 DETAIL B E3 0.375 BSC 10X COANLSTTERRUNCATTIOENS Ke 0.09.080 BS−C−− 0.08 C A3 L 0.35 0.45 NOTE 4 SIDE VIEW A1 C SPELAATNIENG L1 0.00 0.15 0.10 C A BB DETAIL A D2 10XL RECOMMENDED 1 5 MOUNTING FOOTPRINT 10X 0.10 C A BB 3.20 0.60 PACKAGE OUTLINE E3 E2 4.30 0.75 2.15 K 10 6 e 10Xb 1 0.10 C A BB 0.80 010.4X2 BOTTOM VIEW 0.05 C NOTE 3 PITCH DIMENSIONS: MILLIMETERS ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative ◊ www.onsemi.com NCP5106/D 19

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: O N Semiconductor: NCP5106APG NCP5106ADR2G NCP5106AMNTWG