MCP6V26/7/8 620 µA, 2 MHz Auto-Zeroed Op Amps Features Description • High DC Precision: The Microchip Technology Inc. MCP6V26/7/8 family of - V Drift: ±50nV/°C (maximum) operational amplifiers provides input offset voltage OS correction for very low offset and offset drift. These - V : ±2µV (maximum) OS devices have a wide gain bandwidth product (2MHz, - A : 125dB (minimum) OL typical) and strongly reject switching noise. They are - PSRR: 125dB (minimum) unity gain stable, have no 1/fnoise, and have good - CMRR: 120dB (minimum) power supply rejection ratio (PSRR) and common - E : 1.0µV (typical), f=0.1Hz to 10Hz mode rejection ratio (CMRR). These products operate ni P-P - E : 0.32µV (typical), f=0.01Hz to 1Hz with a single supply voltage as low as 2.3V, while ni P-P drawing 620µA/amplifier (typical) of quiescent current. • Low Power and Supply Voltages: - I : 620µA/amplifier (typical) The Microchip Technology Inc. MCP6V26/7/8 op amps Q are offered as a single (MCP6V26), single with Chip - Wide Supply Voltage Range: 2.3V to 5.5V Select (CS) (MCP6V28) and dual (MCP6V27). They • Easy to Use: were designed using an advanced CMOS process. - Rail-to-Rail Input/Output - Gain Bandwidth Product: 2MHz (typical) Package Types (top view) - Unity Gain Stable MCP6V26 MCP6V26 - Available in Single and Dual MSOP,SOIC 2×3TDFN* - Single with Chip Select (CS): MCP6V28 NC 1 8 NC NC 1 8 NC • Extended Temperature Range: -40°C to +125°C VIN– 2 7 VDD VIN– 2 EP 7 VDD Typical Applications VIN+ 3 6 VOUT VIN+ 3 9 6 VOUT VSS 4 5 NC VSS 4 5 NC • Portable Instrumentation • Sensor Conditioning MCP6V27 MCP6V27 MSOP,SOIC 4×4DFN* • Temperature Measurement • DC Offset Correction VOUTA 1 8 VDD VOUTA 1 8 VDD • Medical Instrumentation VINA– 2 7 VOUTB VINA– 2 EP 7 VOUTB VINA+ 3 6 VINB– VINA+ 3 9 6 VINB– Design Aids VSS 4 5 VINB+ VSS 4 5 VINB+ • SPICE Macro Models MCP6V28 MCP6V28 • FilterLab® Software MSOP,SOIC 2×3TDFN* • Microchip Advanced Part Selector (MAPS) NC 1 8 CS NC 1 8 CS • Analog Demonstration and Evaluation Boards VIN– 2 7 VDD VIN– 2 EP 7 VDD • Application Notes VIN+ 3 6 VOUT VIN+ 3 9 6 VOUT VSS 4 5 NC VSS 4 5 NC Related Parts *Includes Exposed Thermal Pad (EP); see Table3-1. Parts with lower power, lower bandwidth and higher noise: • MCP6V01/2/3: Spread clock • MCP6V06/7/8: Non-spread clock © 2011 Microchip Technology Inc. DS25007B-page 1

MCP6V26/7/8 Typical Application Circuit 10kΩ 10kΩ V V IN OUT 10kΩ 10nF 500kΩ U 2 MCP661 10kΩ 5kΩ VDD/2 U1 V /2 MCP6V26 DD OffsetVoltageCorrectionforPowerDriver DS25007B-page 2 © 2011 Microchip Technology Inc.

MCP6V26/7/8 1.0 ELECTRICAL †Notice: Stresses above those listed under “Absolute CHARACTERISTICS Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other 1.1 Absolute Maximum Ratings † conditions above those indicated in the operational listings of this specification is not implied. Exposure to V –V ..............................................................................6.5V DD SS maximum rating conditions for extended periods may Current at Input Pins†† ......................................................±2mA affect device reliability. Analog Inputs (V + and V –)†† ..........V –1.0V to V +1.0V IN IN SS DD All other Inputs and Outputs ..................VSS–0.3V to VDD+0.3V ††See Section4.2.1, Rail-to-Rail Inputs. Difference Input voltage .............................................|V –V | DD SS Output Short Circuit Current .......................................Continuous Current at Output and Supply Pins ...................................±30mA Storage Temperature ..........................................-65°C to +150°C Max. Junction Temperature ..............................................+150°C ESD protection on all pins (HBM, CDM, MM) ≥4kV,1.5 kV, 300V 1.2 Specifications TABLE 1-1: DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +2.3V to +5.5V, V = GND, A DD SS V = V /3, V =V /2, V =V /2, R = 10kΩ to V and CS = GND (refer to Figure1-5 and Figure1-6). CM DD OUT DD L DD L L Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage V -2 — +2 µV T = +25°C (Note1) OS A Input Offset Voltage Drift TC -50 — +50 nV/°C T = -40 to +125°C 1 A with Temperature (linear Temp. Co.) (Note1) Input Offset Voltage Quadratic TC — ±0.2 — nV/°C2 T = -40 to +125°C 2 A Temperature Coefficient Power Supply Rejection PSRR 125 142 — dB (Note1) Input Bias Current and Impedance Input Bias Current I — +7 — pA B Input Bias Current across I — +110 — pA T = +85°C B A Temperature I — +1.2 +5 nA T = +125°C B A Input Offset Current I — ±70 — pA OS Input Offset Current across I — ±50 — pA T = +85°C OS A Temperature I — ±60 — pA T = +125°C OS A Common Mode Input Impedance Z — 1013||12 — Ω||pF CM Differential Input Impedance Z — 1013||12 — Ω||pF DIFF Note 1: Set by design and characterization. Due to thermal junction and other effects in the production environment, these parts can only be screened in production (except TC ; see Appendix B: “Offset 1 Related Test Screens”). 2: Figure2-18 shows how V and V changed across temperature for the first production lot. CML CMH © 2011 Microchip Technology Inc. DS25007B-page 3

MCP6V26/7/8 TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +2.3V to +5.5V, V = GND, A DD SS V = V /3, V =V /2, V =V /2, R = 10kΩ to V and CS = GND (refer to Figure1-5 and Figure1-6). CM DD OUT DD L DD L L Parameters Sym Min Typ Max Units Conditions Common Mode Common-Mode Input V — — V −0.15 V (Note2) CML SS Voltage Range Low Common-Mode Input V V +0.2 — — V (Note2) CMH DD Voltage Range High Common-Mode Rejection CMRR 120 136 — dB V = 2.3V, DD V = -0.15V to 2.5V CM (Note1, Note2) CMRR 125 142 — dB V = 5.5V, DD V = -0.15V to 5.7V CM (Note1, Note2) Open-Loop Gain DC Open-Loop Gain (large signal) A 125 147 — dB V =2.3V, OL DD V = 0.2V to 2.1V OUT (Note1) A 133 155 — dB V =5.5V, OL DD V = 0.2V to 5.3V OUT (Note1) Output Minimum Output Voltage Swing V — V +5 V +15 mV G = +2, 0.5V OL SS SS input overdrive Maximum Output Voltage Swing V V –15 V −5 — mV G = +2, 0.5V OH DD DD input overdrive Output Short Circuit Current I — ±12 — mA V =2.3V SC DD I — ±22 — mA V =5.5V SC DD Power Supply Supply Voltage V 2.3 — 5.5 V DD Quiescent Current per amplifier I 450 620 800 µA I = 0 Q O POR Trip Voltage V 1.15 — 1.65 V POR Note 1: Set by design and characterization. Due to thermal junction and other effects in the production environment, these parts can only be screened in production (except TC ; see Appendix B: “Offset 1 Related Test Screens”). 2: Figure2-18 shows how V and V changed across temperature for the first production lot. CML CMH DS25007B-page 4 © 2011 Microchip Technology Inc.

MCP6V26/7/8 TABLE 1-2: AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +2.3V to +5.5V, V = GND, A DD SS V = V /3, V =V /2, V =V /2, R = 10kΩ to V , C = 60pF and CS = GND (refer to Figure1-5 and CM DD OUT DD L DD L L L Figure1-6). Parameters Sym Min Typ Max Units Conditions Amplifier AC Response Gain Bandwidth Product GBWP — 2.0 — MHz Slew Rate SR — 1.0 — V/µs Phase Margin PM — 65 — ° G = +1 Amplifier Noise Response Input Noise Voltage E — 0.32 — µV f = 0.01Hz to 1Hz ni P-P E — 1.0 — µV f = 0.1Hz to 10Hz ni P-P Input Noise Voltage Density e — 50 — nV/√Hz f < 5kHz ni e — 29 — nV/√Hz f = 100kHz ni Input Noise Current Density i — 0.6 — fA/√Hz ni Amplifier Distortion (Note1) Intermodulation Distortion (AC) IMD — 40 — µV V tone = 50mV at 1kHz, PK CM PK G = 1 N Amplifier Step Response Start Up Time t — 75 — µs G = +1, V within 50µV of its final value STR OS (Note2) Offset Correction Settling Time t — 150 — µs G = +1, V step of 2V, STL IN V within 50µV of its final value OS Output Overdrive Recovery Time t — 45 — µs G = -100, ±0.5V input overdrive to V /2, ODR DD V 50% point to V 90% point IN OUT (Note3) Note 1: These parameters were characterized using the circuit in Figure1-7. In Figure2-37 and Figure2-38, there is an IMD tone at DC, a residual tone at 1kHz, other IMD tones and clock tones. 2: High gains behave differently; see Section4.3.3, Offset at Power Up. 3: t includes some uncertainty due to clock edge timing. ODR © 2011 Microchip Technology Inc. DS25007B-page 5

MCP6V26/7/8 TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +2.3V to +5.5V, V = GND, A DD SS V = V /3, V =V /2, V =V /2, R = 10kW to V , C = 60 pF, and CS=GND (refer to Figure1-5 and CM DD OUT DD L DD L L L Figure1-6). Parameters Sym Min Typ Max Units Conditions CS Pull-Down Resistor (MCP6V28) CS Pull-Down Resistor R 3 5 — MΩ PD CS Low Specifications (MCP6V28) CS Logic Threshold, Low V V — 0.3V V IL SS DD CS Input Current, Low ICSL — 5 — pA CS = VSS CS High Specifications (MCP6V28) CS Logic Threshold, High V 0.7V — V V IH DD DD CS Input Current, High ICSH — VDD/RPD — pA CS = VDD CS Input High, ISS — -0.4 — µA CS = VDD, VDD = 2.3V GND Current per amplifier ISS — -1 — µA CS = VDD, VDD = 5.5V Amplifier Output Leakage, IO_LEAK — 20 — pA CS = VDD CS High CS Dynamic Specifications (MCP6V28) CS Low to Amplifier Output On tON — 4 50 µs CS Low = VSS+0.3V, G = +1V/V, Turn-on Time V = 0.9V /2 OUT DD CS High to Amplifier Output tOFF — 1 — µs CS High = VDD–0.3V, G = +1V/V, High-Z V = 0.1V /2 OUT DD Internal Hysteresis V — 0.2 — V HYST TABLE 1-4: TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, all limits are specified for: V = +2.3V to +5.5V, V = GND. DD SS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T -40 — +125 °C A Operating Temperature Range T -40 — +125 °C (Note1) A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 8L-4x4DFN θ — 48 — °C/W (Note2) JA Thermal Resistance, 8L-MSOP θ — 211 — °C/W JA Thermal Resistance, 8L-SOIC θ — 150 — °C/W JA Thermal Resistance, 8L-2x3 TDFN θ — 53 — °C/W (Note2) JA Note 1: Operation must not cause T to exceed Maximum Junction Temperature specification (+150°C). J 2: Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias. DS25007B-page 6 © 2011 Microchip Technology Inc.

MCP6V26/7/8 1.3 Timing Diagrams 1.4 Test Circuits The circuits used for the DC and AC tests are shown in 2.3Vto5.5V Figure1-5 and Figure1-6. Lay the bypass capacitors 2.3V V 0V out as discussed in Section4.3.10, Supply Bypass- DD ing and Filtering. R is equal to the parallel combina- N tSTR VOS+50µV tion of RF and RG to minimize bias current effects. VOS V –50µV V OS DD 1µF VIN RN RISO VOUT FIGURE 1-1: Amplifier Start Up. U 1 MCP6V2X 100nF CL RL V /3 V DD IN V tSTL V +50µV RG RF L OS FIGURE 1-5: AC and DC Test Circuit for V OS Most Non-Inverting Gain Conditions. V +50µV OS V DD 1µF FIGURE 1-2: Offset Correction Settling Time. VDD/3 RN RISO VOUT U 1 MCP6V2X V C R IN 100nF L L V IN tODR R R VL G F VDD FIGURE 1-6: AC and DC Test Circuit for t Most Inverting Gain Conditions. ODR V OUT V /2 The circuit in Figure1-7 tests the op amp input’s DD dynamic behavior (i.e., IMD, t , t and t ). The V STR STL ODR SS potentiometer balances the resistor network (V OUT should equal V at DC). The op amp’s common FIGURE 1-3: Output Overdrive Recovery. REF mode input voltage is V =V /2. The error at the CM IN input (V ) appears at V with a noise gain of ERR OUT 10V/V. CS V V IL IH t t ON OFF 20.0kΩ 20.0kΩ 50Ω 0.1% 0.1% 25turn VOUT High-Z High-Z VREF V 1µA 1µA DD Ω 1µF IDD (typical) 300µA (typical) 9k (typical) 2.4 RISO VOUT 300µA V Ω ISS -(2typµiAcal) (typical) (ty-p2icµaAl) IN 49k 100nF CL RL 2. U MCP6V2X 5pA 1 V L ICS VDD/5MΩ (typical) VDD/5MΩ 20.0kΩ 20.0kΩ 24.9Ω (typical) (typical) 0.1% 0.1% FIGURE 1-4: Chip Select (MCP6V28). FIGURE 1-7: Test Circuit for Dynamic Input Behavior. © 2011 Microchip Technology Inc. DS25007B-page 7

MCP6V26/7/8 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T =+25°C, V =+2.3V to 5.5V, V =GND, V =V /3, V =V /2, A DD SS CM DD OUT DD V =V /2, R =10kΩ to V , C = 60pF and CS = GND. L DD L L L 2.1 DC Input Precision 40% s 20 Samples ce 35% TA = +25°C urren 30% VDD = 2.3V and 5.5V c 25% c O of 20% ge 15% a nt 10% e c er 5% P 0% 0 0 0 0 0 2. 1. 0. 1. 2. - - Input Offset Voltage (µV) FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Input Offset Voltage vs. Power Supply Voltage with V =V . CM CML 30% s 20 Samples ce25% VDD = 2.3V and 5.5V n e urr20% c c O of 15% e ag10% nt e c 5% er P 0% 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 1 2 3 4 5 - - - - - Input Offset Voltage Drift; TC (nV/°C) 1 FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-5: Input Offset Voltage vs. Power Supply Voltage with V =V . CM CMH 5 Representative Part 4 V) µ 3 e ( 2 g a olt 1 VDD= 2.3V V 0 Offset --21 VDD = 5.5V ut -3 p In -4 -5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V) FIGURE 2-3: Input Offset Voltage FIGURE 2-6: Input Offset Voltage vs. Quadratic Temperature Coefficient. Output Voltage. DS25007B-page 8 © 2011 Microchip Technology Inc.

MCP6V26/7/8 Note: Unless otherwise indicated, T =+25°C, V =+2.3V to 5.5V, V =GND, V =V /3, V =V /2, A DD SS CM DD OUT DD V =V /2, R =10kΩ to V , C = 60pF and CS = GND. L DD L L L 5 30% ge (µV) 234 VRDeDp r=e 2s.e3nVtative Part urrences 2205%% 2T0A =S a+m25p°lCes a c olt 1 Oc Input Offset V----43210 ++-428055°°°CCC Percentage of 11055%%% +125°C 0% -5 4 3 2 1 0 1 2 3 4 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -0. -0. -0. -0. 0. 0. 0. 0. 0. Input Common Mode Voltage (V) 1/PSRR (µV/V) FIGURE 2-7: Input Offset Voltage vs. FIGURE 2-10: PSRR. Common Mode Voltage with V =2.3V. DD 5 100% set Voltage (µV)-101234 VRDeDp r=e 5s.e5nVtative Part +++1-24285055°°°°CCCC ge of Occurrences 456789000000%%%%%% 2T0A S= a+m25p°lCes VDD = 2.3V VDD = 5.5V Input Off---432 Percenta 123000%%% -5 0% -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 Input Common Mode Voltage (V) 1/A (µV/V) OL FIGURE 2-8: Input Offset Voltage vs. FIGURE 2-11: DC Open-Loop Gain. Common Mode Voltage with V =5.5V. DD 35% 160 s 20 Samples urrence2350%% TA = +25°C dB)115505 PSRR Occ20% RR (145 ge of 15% VDD = 5.5V VDD = 2.3V R, PS113450 ercenta105%% CMR112350 VVDDDD== 52..53VV CMRR P 0% 120 5 3 0 3 5 0. 0. 0. 0. 0. -50 -25 0 25 50 75 100 125 - - 1/CMRR (µV/V) Ambient Temperature (°C) FIGURE 2-9: CMRR. FIGURE 2-12: CMRR and PSRR vs. Ambient Temperature. © 2011 Microchip Technology Inc. DS25007B-page 9

MCP6V26/7/8 Note: Unless otherwise indicated, T =+25°C, V =+2.3V to 5.5V, V =GND, V =V /3, V =V /2, A DD SS CM DD OUT DD V =V /2, R =10kΩ to V , C = 60pF and CS = GND. L DD L L L 160 10,0100n0 B)155 s (A) VDD= 5.5V Gain (d114550 VVDDDD == 52..53VV Current1,001n0 en-Loop 113450 s, Offset 11000p0 -IOS DC Op112350 put Bia 110p0 IB n 120 I 1p1 -50 -25 0 25 50 75 100 125 25 35 45 55 65 75 85 95 105 115 125 Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-13: DC Open-Loop Gain vs. FIGURE 2-16: Input Bias and Offset Ambient Temperature. Currents vs. Ambient Temperature with V =+5.5V. DD 200 1.E10-0m2 A) TA = +85°C nts (p 150 VDD = 5.5V de (A)11..1EE0--1000m43µ urre 100 nitu1.E1-005µ et C 50 IB Mag1.E-016µ Input Bias, Offs -1-50000 IOS Input Current 11111.....11EEEEE0101-----0010011000nnppn10987 +++1-28245550°°°°CCCC 5 0 5 0 5 0 5 0 5 0 5 0 5 0 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 - Common Mode Input Voltage (V) Input Voltage (V) FIGURE 2-14: Input Bias and Offset FIGURE 2-17: Input Bias Current vs. Input Currents vs. Common Mode Input Voltage with Voltage (below V ). SS T =+85°C. A 2000 s (pA) 11680000 TVAD D= = + 51.255V°C nt 1400 e urr 1200 C 1000 set 800 IB Off 600 as, 240000 put Bi -2000 IOS In -400 5 0 5 0 5 0 5 0 5 0 5 0 5 0 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. - Common Mode Input Voltage (V) FIGURE 2-15: Input Bias and Offset Currents vs. Common Mode Input Voltage with T =+125°C. A DS25007B-page 10 © 2011 Microchip Technology Inc.

MCP6V26/7/8 Note: Unless otherwise indicated, T =+25°C, V =+2.3V to 5.5V, V =GND, V =V /3, V =V /2, A DD SS CM DD OUT DD V =V /2, R =10kΩ to V , C = 60pF and CS = GND. L DD L L L 2.2 Other DC Voltages and Currents 0.4 40 age 0.3 1 Wafer Lot ent 30 +-4205°°CC Volt 0.2 Upper ( VCMH – VDD) Curr 20 ++12855°°CC mon Mode adroom (V)-000...101 ort Circuit (mA)-11000 me h put CoH--00..32 Lower (VCML – VSS) utput S --3200 +++1282555°°°CCC n O -40°C I -0.4 -40 0 5 0 5 0 5 0 5 0 5 0 5 0 5 -50 -25 0 25 50 75 100 125 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. 6. Ambient Temperature (°C) Power Supply Voltage (V) FIGURE 2-18: Input Common Mode FIGURE 2-21: Output Short Circuit Current Voltage Headroom (Range) vs. Ambient vs. Power Supply Voltage. Temperature. 1000 800 oom (mV) VVDDDD == 52..53VV amplifier)670000 dr A/500 a µ e He 100 ent (400 +125°C Voltag VDD – VOH VOL – VSS y Curr230000 ++-824550°°°CCC utput Suppl100 O 10 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0.1 1 10 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. 6. Output Current Magnitude (mA) Power Supply Voltage (V) FIGURE 2-19: Output Voltage Headroom FIGURE 2-22: Supply Current vs. Power vs. Output Current. Supply Voltage. 10 40% mV) 89 RL = 10 kΩ ences 3305%% 81T2 AW0 = aS +fae2mr5 L°pColets m ( 7 curr 25% o 6 c Headro 45 VDD = 5.5V VOL – VSS VDD – VOH ge of O 1250%% Output 123 VDD = 2.3V Percenta 1005%%% 0 5 6 7 8 9 0 1 2 3 4 5 2 2 2 2 2 3 3 3 3 3 3 -50 -25 0 25 50 75 100 125 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. 1. Ambient Temperature (°C) POR Trip Voltage (V) FIGURE 2-20: Output Voltage Headroom FIGURE 2-23: Power On Reset Trip vs. Ambient Temperature. Voltage. © 2011 Microchip Technology Inc. DS25007B-page 11

MCP6V26/7/8 Note: Unless otherwise indicated, T =+25°C, V =+2.3V to 5.5V, V =GND, V =V /3, V =V /2, A DD SS CM DD OUT DD V =V /2, R =10kΩ to V , C = 60pF and CS = GND. L DD L L L 1.8 1.6 V) 1.4 ge ( 1.2 a olt 1.0 V p 0.8 Tri 0.6 R O 0.4 P 0.2 0.0 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) FIGURE 2-24: Power On Reset Voltage vs. Ambient Temperature. DS25007B-page 12 © 2011 Microchip Technology Inc.

MCP6V26/7/8 Note: Unless otherwise indicated, T =+25°C, V =+2.3V to 5.5V, V =GND, V =V /3, V =V /2, A DD SS CM DD OUT DD V =V /2, R =10kΩ to V , C = 60pF and CS = GND. L DD L L L 2.3 Frequency Response 110 z) 3.0 100 100 HMH SRR (dB) 67890000 CMRR uct (Produh 2121...5505 GBWP VDD= 5.5V 97870000 °)argin (°Ma CMRR, P 23450000 dwidtn Band 10..50 PM VDD= 2.3V 6500 hase Ph 10 PSRR+ ia 0 PSRR- G 0.0 40 1.E1+0002 1.E1+k03 1.E1+0k04 1.1E0+00k5 1.E1+M06 -5500 -2255 00 2255 5500 7755 110000 112255 Frequency (Hz) Ambient Temperature (°C) FIGURE 2-25: CMRR and PSRR vs. FIGURE 2-28: Gain Bandwidth Product Frequency. and Phase Margin vs. Ambient Temperature. 70 0 z) 4.0 120 oop Gain (dB) 2345600000 VCDL∠ D=A = O6 2L0. 3pVF -----119635200000oop Phase (°) Huct (MHh Produwidth 221233.....055050 VDD= 2.3V GBWP VDD= 5.5V 18978110000000°)argin (se M en-L 10 | AOL | -180en-L ndan 1.0 60 haPh p 0 -210p B PM O O n 0.5 50 -10 -240 aia G 0.0 40 -20 -270 1.E1+k03 1.E10+k04 11.E0+00k5 1.E1+M06 1.1E0+M07 0.50 0.00 0.50 .01 .51 2.02 2.52 3.03 3.53 4.04 4.54 5.05 5.55 6.06 Frequency (Hz) - Common Mode Input Voltage (V) FIGURE 2-26: Open-Loop Gain vs. FIGURE 2-29: Gain Bandwidth Product Frequency with V =2.3V. and Phase Margin vs. Common Mode Input DD Voltage. Open-Loop Gain (dB) 123456700000000 | AOL | VCDL D= = 6 ∠50.A 5pOVFL -------0211196318520000000 Open-Loop Phase (°) Hz)uct (MHProdudwidth Band 43322121.......00505500 VDD= 2.3V GPMBWP VDD= 5.5V 1897861110000020000°)argin (°hase MaPh -10 -240 n 00..55 5500 iai -20 -270 G 0.0 40 1k 10k 100k 1M 10M 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 00.0000.5511.0011.5522.0022.5533.0033.5544.0044.5555.0055.55 Frequency (Hz) Output Voltage (V) FIGURE 2-27: Open-Loop Gain vs. FIGURE 2-30: Gain Bandwidth Product Frequency with V =5.5V. and Phase Margin vs. Output Voltage. DD © 2011 Microchip Technology Inc. DS25007B-page 13

MCP6V26/7/8 Note: Unless otherwise indicated, T =+25°C, V =+2.3V to 5.5V, V =GND, V =V /3, V =V /2, A DD SS CM DD OUT DD V =V /2, R =10kΩ to V , C = 60pF and CS = GND. L DD L L L 1.E+1004k VDD = 2.3V Ω) 1e (.E+013k pc on oa Ld sed-1mpe.E+10020 Clout I 1utp.E+0110 O G = 1 V/V G = 11 V/V G = 101 V/V 1.E+001 1.01E00+k05 1.01EM+06 1.01E0+M07 1.100E0+M08 Frequency (Hz) FIGURE 2-31: Closed-Loop Output FIGURE 2-33: Channel-to-Channel Impedance vs. Frequency with V =2.3V. Separation vs. Frequency. DD 1.E+1004k 10 VDD= 2.3V e 1.E+013k oltag VDD = 5.5V put VV)P-P VDD = 2.3V 1.E+10020 utg ( 1 On m wi uS 1.E+0110 xim G = 1 V/V a M G = 11 V/V 1.E+001 G = 101 V/V 0.1 1k 10k 100k 1M 1.100E0+k05 1.01EM+06 1.01E0+M07 1.100E0+M08 1.E+03 1.E+04 1.E+05 1.E+06 Frequency (Hz) Frequency (Hz) FIGURE 2-32: Closed-Loop Output FIGURE 2-34: Maximum Output Voltage Impedance vs. Frequency with V =5.5V. Swing vs. Frequency. DD DS25007B-page 14 © 2011 Microchip Technology Inc.

MCP6V26/7/8 Note: Unless otherwise indicated, T =+25°C, V =+2.3V to 5.5V, V =GND, V =V /3, V =V /2, A DD SS CM DD OUT DD V =V /2, R =10kΩ to V , C = 60pF and CS = GND. L DD L L L 2.4 Input Noise and Distortion 10,000 1,000 100 ;Density;ltage Dise VolNo/(cid:2)Hz)e(nV/ni1,011000000 eni VVDDDD== 52..53VV 1110000 oltage;oise Vonput Nod In)E(μVE-PniP Spectrum, RTI (µV)PK101 IMD tone at DC 1 kVVHDDzDD t==o 52n..e53VV put np rategr IMD GDM = 1 V/V I 10 Eni(0 Hz to f) 1 nte 0.1 VDD tone = 50 mVP-P, f = 1 kHz 1111.00EE+0011 1111.00EE00+0022 11.11EEkk+0033 11.11EE00+kk0044 11.11EE00+0000kk55 I 1.E10+002 1.E1+k03 1.E1+0k04 1.1E0+00k5 Frequency (Hz) Frequency (Hz) FIGURE 2-35: Input Noise Voltage Density FIGURE 2-38: Intermodulation Distortion and Integrated Input Noise Voltage vs. vs. Frequency with V Disturbance (see DD Frequency. Figure1-7). 100 e Density 789000 f < 5 kHz e; e(t)ni VDD= 2.3V Noise Voltag(nV/(cid:2)Hz) 34560000 VDD = 2.3V VDD = 5.5V Noise Voltag(0.2 µV/div) NPBW = 10 Hz ut 20 ut p p n 10 n I I 0 NPBW = 1 Hz 5 0 5 0 5 0 5 0 5 0 5 0 5 0 0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. 0 10 20 30 40 50 60 70 80 90 100 - Common Mode Input Voltage (V) t (s) FIGURE 2-36: Input Noise Voltage Density FIGURE 2-39: Input Noise vs. Time with vs. Input Common Mode Voltage. 1Hz and 10Hz Filters and V =2.3V. DD 100 VDD= 5.5V )PK IMD tone at DC (t)ni pectrum, RTI (µV 101 residual 1 kHzVV tDDoDDn e== 25..35VV Noise Voltage; e(0.2 µV/div) NPBW = 10 Hz D S put IM 0.1 GVCDMM t=o n1e V =/V 50 mVPK, f = 1 kHz In NPBW = 1 Hz 1.E10+002 1.E1+k03 1.E10+k04 1.1E0+00k5 0 10 20 30 40 50 60 70 80 90 100 Frequency (Hz) t (s) FIGURE 2-37: Intermodulation Distortion FIGURE 2-40: Input Noise vs. Time with vs. Frequency with V Disturbance (see 1Hz and 10Hz Filters and V =5.5V. CM DD Figure1-7). © 2011 Microchip Technology Inc. DS25007B-page 15

MCP6V26/7/8 Note: Unless otherwise indicated, T =+25°C, V =+2.3V to 5.5V, V =GND, V =V /3, V =V /2, A DD SS CM DD OUT DD V =V /2, R =10kΩ to V , C = 60pF and CS = GND. L DD L L L 2.5 Time Response 6 100 nput Offset Voltage (µV) -1----08642024 TuseminpgTVe PhOrCeaSBatut rgeu inn cforera 1s0e dse bcyonds. 2345678900000000 PCB Temperature (°C) utput Voltage (10 mV/div) VGD =D =1 5.5V I -12 10 O -14 0 0 20 40 60 80 100 120 140 160 180 0 1 2 3 4 5 6 7 8 9 10 Time (s) Time (µs) FIGURE 2-41: Input Offset Voltage vs. FIGURE 2-44: Non-inverting Small Signal Time with Temperature Change. Step Response. 90 6 5.5 Input Offset Voltage (µV) 12345678000000000 POGR = TV 1rOiSp Point VDD ---012345321 Power Supply Voltage (V) Output Voltage (V)0112233445..........5050505050 VGD =D =1 5.5V -10 -4 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 5 10 15 20 25 30 35 40 45 50 Time (ms) Time (µs) FIGURE 2-42: Input Offset Voltage vs. FIGURE 2-45: Non-inverting Large Signal Time at Power Up. Step Response. 7 ges (V) 56 VIN VGD =D =1 5.5V mV/div) VGD =D =-1 5.5V Output Volta 234 VOUT Voltage (10 ut, 1 put Inp 0 Out -1 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 Time (ms) Time (µs) FIGURE 2-43: The MCP6V26/7/8 Device FIGURE 2-46: Inverting Small Signal Step Shows No Input Phase Reversal with Overdrive. Response. DS25007B-page 16 © 2011 Microchip Technology Inc.

MCP6V26/7/8 Note: Unless otherwise indicated, T =+25°C, V =+2.3V to 5.5V, V =GND, V =V /3, V =V /2, A DD SS CM DD OUT DD V =V /2, R =10kΩ to V , C = 60pF and CS = GND. L DD L L L 5.5 6.0 6 5.0 VDD = 5.5V G = -1 5.0 5 ge (V)344...505 e (V) 4.0 G VIN VOUT 4 G (V/V) Volta23..50 oltag 3.0 3 ge × Output 112...050 Output V 12..00 VOUT VG0.D 5=DV =- 1O 50v.05e VVrd/Vrive G VIN 12 nput Volta 0.5 0.0 0 I 0.0 0 5 10 15 20 25 30 35 40 45 50 -1.0 -1 Time (µs) Time (50 µs/div) FIGURE 2-47: Inverting Large Signal Step FIGURE 2-49: Output Overdrive Recovery Response. vs. Time with G=-100V/V. 1.6 1000 1.4 Falling Edge VDD = 5.5V e (µs) 0.5V Output Overdrive m ate (V/µs)011...802 covery Ti 100 tODR, highVDD = 5.5V R e Slew 00..46 Rising Edge VDD = 2.3V drive R 10 0.2 Over tODR, low VDD = 2.3V 0.0 1 -50 -25 0 25 50 75 100 125 1 10 100 1000 Ambient Temperature (°C) Inverting Gain Magnitude (V/V) FIGURE 2-48: Slew Rate vs. Ambient FIGURE 2-50: Output Overdrive Recovery Temperature. Time vs. Inverting Gain. © 2011 Microchip Technology Inc. DS25007B-page 17

MCP6V26/7/8 Note: Unless otherwise indicated, T =+25°C, V =+2.3V to 5.5V, V =GND, V =V /3, V =V /2, A DD SS CM DD OUT DD V =V /2, R =10kΩ to V , C = 60pF, and CS=GND. L DD L L L 2.6 Chip Select Response (MCP6V28 only) 1.0 1.0 0.9 CS = VDD 0.9 VDD= 5.5V nt (μA)00..78 nt (μA)00..78 urre0.6 urre0.6 Select C000...345 Select C000...345 hip 0.2 hip 0.2 C0.1 C0.1 0.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) Chip Select Voltage (V) FIGURE 2-51: Chip Select Current vs. FIGURE 2-54: Chip Select Current vs. Chip Power Supply Voltage. Select Voltage. 700 A)600 VGD=D =1 2.3V 2.5 y Current (μ450000 Othueprrn eAsm opn Othueprrn eAsm opffVVILN== 01V.15V otage (V)12..50 VOUTOn VOUTOff wer Suppl230000 Hysteresis tput VOut10..05 VGD =D V=+O 12U .VT3/OVVff CCSS Po100 VRILN== 1V0D Dk(cid:3)tied to VDD/2 0 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 0 5 10 15 20 25 30 35 40 45 50 Chip Select Voltage (V) Time (5 μs/div) FIGURE 2-52: Power Supply Current vs. FIGURE 2-55: Chip Select Voltage, Output Chip Select Voltage with V =2.3V. Voltage vs. Time with V =2.3V. DD DD 800 5.5 A)700 VGD=D =1 5.5V 5.0 VOUTOn nt (μ600 VVILN== 02V.75V V)44..05 Power Supply Curre123450000000000 Othueprrn eAsm opn HOthyuepsrrn teAesrm eospffis utput Votage (Ou2233011.......0505505 VVGVRDIL N=D== =+ 1V 1550V D.V O55Dk/UVV(cid:3)VTOtieffd to VDD/2 CS VOUTOff 0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 5 10 15 20 25 30 35 40 45 50 Chip Select Voltage (V) Time (5 μs/div) FIGURE 2-53: Power Supply Current vs. FIGURE 2-56: Chip Select Voltage, Output Chip Select Voltage with V =5.5V. Voltage vs. Time with V =5.5V. DD DD DS25007B-page 18 © 2011 Microchip Technology Inc.

MCP6V26/7/8 Note: Unless otherwise indicated, T =+25°C, V =+2.3V to 5.5V, V =GND, V =V /3, V =V /2, A DD SS CM DD OUT DD V =V /2, R =10kΩ to V , C = 60pF, and CS=GND. L DD L L L s; 70% 7 ect Logic LevelHigh (V/V)55660505%%%% VIH/VDD VDD= 5.5V (cid:2)Resistor (M)456 ve Chip SelLow and 344505%%% VIL/VDD VDD= 2.3V Pull-down 123 elati 30% 0 R -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-57: Chip Select Relative Logic FIGURE 2-60: Chip Select’s Pull-down Thresholds vs. Ambient Temperature. Resistor (R ) vs. Ambient Temperature. PD 0.40 1.4 V) 0.35 A)1.2 CReSp =r eVsDeDntative Part esis ( 0.30 ent (μ1.0 +125°C Hyster 00..2205 VDD= 5.5V y Curr0.8 ++-482550°°°CCC Chip Select 000...011505 VDD= 2.3V Power Suppl000...246 0.00 0.0 -50 -25 0 25 50 75 100 125 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Ambient Temperature (°C) Power Supply Voltage (V) FIGURE 2-58: Chip Select Hysteresis. FIGURE 2-61: Quiescent Current in Shutdown vs. Power Supply Voltage. 7 s) e (μ6 m Ti5 On 4 VDD= 5.5V n Tur3 ct ele2 p S1 VDD= 2.3V hi C 0 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) FIGURE 2-59: Chip Select Turn On Time vs. Ambient Temperature. © 2011 Microchip Technology Inc. DS25007B-page 19

MCP6V26/7/8 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE MCP6V26 MCP6V27 MCP6V28 Symbol Description TDFN MSOP,SOIC DFN MSOP,SOIC TDFN MSOP,SOIC 6 6 1 1 6 6 V , V Output (op amp A) OUT OUTA 2 2 2 2 2 2 V –, V – Inverting Input (op amp A) IN INA 3 3 3 3 3 3 V +, V + Non-inverting Input (op amp A) IN INA 4 4 4 4 4 4 V Negative Power Supply SS — — 5 5 — — V + Non-inverting Input (op amp B) INB — — 6 6 — — V – Inverting Input (op amp B) INB — — 7 7 — — V Output (op amp B) OUTB 7 7 8 8 7 7 V Positive Power Supply DD — — — — 8 8 CS Chip Select (op amp A) 1, 5, 8 1, 5, 8 — — 1, 5 1, 5 NC No Internal Connection 9 — 9 — 9 — EP Exposed Thermal Pad (EP); must be connected to V SS 3.1 Analog Outputs 3.4 Chip Select (CS) Digital Input The analog output pins (V ) are low-impedance This pin (CS) is a CMOS, Schmitt-triggered input that OUT voltage sources. places the MCP6V28 op amp into a low power mode of operation. 3.2 Analog Inputs 3.5 Exposed Thermal Pad (EP) The non-inverting and inverting inputs (V +, V –, …) IN IN are high-impedance CMOS inputs with low bias There is an internal connection between the Exposed currents. Thermal Pad (EP) and the V pin; they must be SS connected to the same potential on the Printed Circuit 3.3 Power Supply Pins Board (PCB). This pad can be connected to a PCB ground plane to The positive power supply (V ) is 2.3V to 5.5V higher DD provide a larger heat sink. This improves the package than the negative power supply (V ). For normal SS thermal resistance (θ ). operation, the other pins are between V and V . JA SS DD Typically, these parts are used in a single (positive) supply configuration. In this case, V is connected to SS ground and V is connected to the supply. V will DD DD need bypass capacitors. DS25007B-page 20 © 2011 Microchip Technology Inc.

MCP6V26/7/8 4.0 APPLICATIONS 4.1 Overview of Auto-Zeroing Operation The MCP6V26/7/8 family of auto-zeroed op amps are manufactured using Microchip’s state-of-the-art CMOS Figure4-1 shows a simplified diagram of the process. This family is designed for low cost, low power MCP6V26/7/8 auto-zeroed op amps. This will be used and high precision applications. Its low supply voltage, to explain how the DC voltage errors are reduced in this low quiescent current and wide bandwidth make the architecture. MCP6V26/7/8 devices ideal for battery-powered appli- cations. V + IN VIN– Main Amp. NC Output CFW Buffer VOUT V REF Null Null Input φ Output 1 Switches Switches Null Amp. C H POR Null Correct Switches φ1 Digital Oscillator φ Control 2 φ 2 FIGURE 4-1: Simplified Auto-Zeroed Op Amp Functional Diagram. 4.1.1 BUILDING BLOCKS All of these switches are make-before-break in order to minimize glitch-induced errors. They are driven by two The Null Amplifier and Main Amplifier are designed for clock phases (φ and φ ) that select between normal high gain and accuracy using a differential topology. 1 2 mode and auto-zeroing mode. They have a main input pair (+ and - pins at their top left) used for the signal. They have an auxiliary input The clock is derived from an internal R-C oscillator pair (+ and - pins at their bottom left) used for correcting running at a rate of fOSC1=850kHz. The oscillator’s the offset voltages. Both input pairs are added together output is divided down to the desired rate. internally. The capacitors at the auxiliary inputs (CFW The internal POR ensures the part starts up in a known and C ) hold the corrected values during normal H good state. It also provides protection against power operation. supply brown-out events. The Output Buffer is designed to drive external loads at The Digital Control circuitry takes care of all of the the V pin. It also produces a single-ended output OUT housekeeping details of the switching operation. It also voltage (V is an internal reference voltage). REF takes care of POR events. © 2011 Microchip Technology Inc. DS25007B-page 21

MCP6V26/7/8 4.1.2 AUTO-ZEROING ACTION offset voltage on overall performance. Essentially, the Null Amplifier and Main Amplifier behave as a regular Figure4-2 shows the connections between amplifiers op amp with very high gain (A ) and very low offset during the Normal Mode of operation (φ ). The hold OL 1 voltage (V ). capacitor (C ) corrects the Null Amplifier’s input offset. OS H Since the Null Amplifier has very high gain, it dominates the signal seen by the Main Amplifier. This greatly reduces the impact of the Main Amplifier’s input V + IN VIN– Main Amp. NC Output CFW Buffer VOUT Null VREF Amp. C H FIGURE 4-2: Normal Mode of Operation (φ); Equivalent Amplifier Diagram. 1 Figure4-3 shows the connections between amplifiers Since these corrections happen every 40µs, or so, we during the Auto-zeroing Mode of operation (φ ). The also minimize slow errors, including offset drift with 2 signal goes directly through the Main Amplifier, and the temperature (ΔV /ΔT ), 1/f noise, and input offset OS A flywheel capacitor (C ) maintains a constant correc- aging. FW tion on the Main Amplifier’s offset. The Null Amplifier uses its own high open loop gain to drive the voltage across C to the point where its input H offset voltage is almost zero. Because the signal input pair is connected to V +, the auto-zeroing action IN corrects the offset at the current common mode input voltage (V ) and supply voltage (V ). This makes CM DD the DC CMRR and PSRR very high also. V + IN VIN– Main Amp. NC Output CFW Buffer VOUT V Null REF Amp. C H FIGURE 4-3: Auto-zeroing Mode of Operation (φ); Equivalent Diagram. 2 4.1.3 INTERMODULATION DISTORTION frequencies. Each of the square wave clock’s (IMD) harmonics has a series of IMD tones centered on it. See Figure2-37 and Figure2-38. The MCP6V26/7/8 op amps will show intermodulation distortion (IMD), products when an AC signal is present. The signal and clock can be decomposed into sine wave tones (Fourier series components). These tones interact with the auto-zeroing circuitry’s non-linear response to produce IMD tones at sum and difference DS25007B-page 22 © 2011 Microchip Technology Inc.

MCP6V26/7/8 4.2 Other Functional Blocks The input ESD diodes clamp the inputs when they try to go more than one diode drop below V . They also SS 4.2.1 RAIL-TO-RAIL INPUTS clamp any voltages that are well above V ; their DD breakdown voltage is high enough to allow normal The input stage of the MCP6V26/7/8 op amps use two operation, but not low enough to protect against slow differential CMOS input stages in parallel. One over-voltage (beyond V ) events. Very fast ESD operates at low common mode input voltage (V , DD CM events (that meet the spec) are limited so that damage which is approximately equal to V + and V – in IN IN does not occur. normal operation) and the other at high V . With this CM topology, the input operates with V up to V +0.2V, In some applications, it may be necessary to prevent CM DD and down to V –0.15V, at +25°C (see Figure2-18). excessive voltages from reaching the op amp inputs; SS The input offset voltage (V ) is measured at Figure4-5 shows one approach to protecting these OS VCM=VSS–0.15V and VDD+0.2V to ensure proper inputs. D1 and D2 may be small signal silicon diodes, operation. Schottky diodes for lower clamping voltages or diode- connected FETs for low leakage. The transition between the input stages occurs when V ≈V –1.2V (see Figure2-7 and Figure2-8). For CM DD the best distortion and gain linearity, with non-inverting V DD gains, avoid this region of operation. 4.2.1.1 Phase Reversal D1 U1 MCP6V2X The input devices are designed to not exhibit phase V 1 inversion when the input pins exceed the supply D V 2 OUT voltages. Figure2-43 shows an input voltage V 2 exceeding both supplies with no phase inversion. 4.2.1.2 Input Voltage Limits FIGURE 4-5: Protecting the Analog Inputs In order to prevent damage and/or improper operation Against High Voltages. of these amplifiers, the circuit must limit the voltages at the input pins (see Section1.1, Absolute Maximum 4.2.1.3 Input Current Limits Ratings†). This requirement is independent of the In order to prevent damage and/or improper operation current limits discussed later on. of these amplifiers, the circuit must limit the currents The ESD protection on the inputs can be depicted as into the input pins (see Section1.1, Absolute shown in Figure4-4. This structure was chosen to Maximum Ratings†). This requirement is protect the input transistors against many (but not all) independent of the voltage limits previously discussed. over-voltage conditions, and to minimize input bias Figure4-6 shows one approach to protecting these current (I ). B inputs. The resistors R and R limit the possible 1 2 current in or out of the input pins (and into D and D ). 1 2 The diode currents will dump onto V . Bond DD V DD Pad V DD Bond Input Bond VIN+ Pad Stage Pad VIN– D1 U1 MCP6V2X V 1 R1 D2 VOUT V Bond V2 SS Pad R 2 FIGURE 4-4: Simplified Analog Input ESD V –min(V ,V ) SS 1 2 min(R ,R )> Structures. 1 2 2mA max(V ,V )–V 1 2 DD min(R ,R )> 1 2 2mA FIGURE 4-6: Protecting the Analog Inputs Against High Currents. © 2011 Microchip Technology Inc. DS25007B-page 23

MCP6V26/7/8 It is also possible to connect the diodes to the left of 4.3.2 DC GAIN PLOTS resistors R and R . In this case, the currents through 1 2 Figure2-9, Figure2-10 and Figure2-11 are histograms diodes D and D need to be limited by some other 1 2 of the reciprocals (in units of µV/V) of CMRR, PSRR mechanism. The resistors then serve as in-rush current and A , respectively. They represent the change in limiters; the DC current into the input pins (V + and OL IN input offset voltage (V ) with a change in common V –) should be very small. OS IN mode input voltage (V ), power supply voltage (V ) CM DD A significant amount of current can flow out of the and output voltage (V ). OUT inputs (through the ESD diodes) when the common The 1/A histogram is centered near 0µV/V because mode voltage (V ) is below ground (V ); see OL CM SS the measurements are dominated by the op amp’s Figure2-17. input noise. The negative values shown represent noise, not unstable behavior. We validate the op amps’ 4.2.2 RAIL-TO-RAIL OUTPUT stability by making multiple measurements of V ; an OS The output voltage range of the MCP6V26/7/8 unstable part would fail, because it would show either zero-drift op amps is VDD–15mV (minimum) and greater variability in VOS, or the output stuck at one of VSS+15mV (maximum) when RL=10kΩ is the rails. connected to V /2 and V =5.5V. Refer to DD DD Figure2-19 and Figure2-20. 4.3.3 OFFSET AT POWER UP This op amp is designed to drive light loads; use When these parts power up, the input offset (V ) OS another amplifier to buffer the output from heavy loads. starts at its uncorrected value (usually less than ±5mV). Circuits with high DC gain can cause the 4.2.3 CHIP SELECT (CS) output to reach one of the two rails. In this case, the The single MCP6V28 has a Chip Select (CS) pin. time to a valid output is delayed by an output overdrive When CS is pulled high, the supply current for the time (like tODR), in addition to the startup time (like corresponding op amp drops to about 1µA (typical), tSTR). and is pulled through the CS pin to VSS. When this It can be simple to avoid this extra startup time. happens, the amplifier is put into a high impedance Reducing the gain is one method. Adding a capacitor state. By pulling CS low, the amplifier is enabled. If the across the feedback resistor (R ) is another method. F CS pin is left floating, the internal pull-down resistor (about 5MΩ) will keep the part on. Figure1-4 shows 4.3.4 SOURCE RESISTANCES the output voltage and supply current response to a CS The input bias currents have two significant pulse. components; switching glitches that dominate at room temperature and below, and input ESD diode leakage 4.3 Application Tips currents that dominate at +85°C and above. 4.3.1 INPUT OFFSET VOLTAGE OVER Make the resistances seen by the inputs small and equal. This minimizes the output offset caused by the TEMPERATURE input bias currents. Table1-1 gives both the linear and quadratic The inputs should see a resistance on the order of 10Ω temperature coefficients (TC and TC ) of input offset 1 2 to 1kΩ at high frequencies (i.e., above 1MHz). This voltage. The input offset voltage, at any temperature in helps minimize the impact of switching glitches, which the specified range, can be calculated as follows: are very fast, on overall performance. In some cases, it may be necessary to add resistors in series with the EQUATION 4-1: inputs to achieve this improvement in performance. 2 V (T ) = V +TC ΔT+TC ΔT Small input resistances are needed for high gains. OS A OS 1 2 Where: Without them, parasitic capacitances can cause positive feedback and instability. ΔT = T –25°C A V (T ) = input offset voltage at T 4.3.5 SOURCE CAPACITANCE OS A A V = input offset voltage at +25°C The capacitances seen by the two inputs should be OS TC = linear temperature coefficient small and matched. The internal switches connected to 1 the inputs dump charges on these capacitors; an offset TC = quadratic temperature 2 can be created if the capacitances do not match. Large coefficient input capacitances and source resistances, together with high gain, can lead to positive feedback and instability. DS25007B-page 24 © 2011 Microchip Technology Inc.

MCP6V26/7/8 4.3.6 CAPACITIVE LOADS 4.3.7 STABILIZING OUTPUT LOADS Driving large capacitive loads can cause stability This family of auto-zeroed op amps has an output problems for voltage feedback op amps. As the load impedance (Figure2-31 and Figure2-32) that has a capacitance increases, the feedback loop’s phase double zero when the gain is low. This can cause a margin decreases and the closed-loop bandwidth is large phase shift in feedback networks that have low reduced. This produces gain peaking in the frequency resistance near the part’s bandwidth. This large phase response, with overshoot and ringing in the step shift can cause stability problems. response. These auto-zeroed op amps have a different Figure4-9 shows that the load on the output is output impedance than most op amps, due to their (R +R )||(R +R ), where R is before the load L ISO F G ISO unique topology. (like Figure4-7). This load needs to be large enough to When driving a capacitive load with these op amps, a maintain stability; it should be at least (2kΩ)/G . N series resistor at the output (R in Figure4-7) ISO improves the feedback loop’s phase margin (stability) R R G F by making the output load resistive at higher V OUT frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. R C L L U 1 RISO MCP6V2X V OUT FIGURE 4-9: Output Load. C L 4.3.8 GAIN PEAKING Figure4-10 shows an op amp circuit that represents U 1 non-inverting amplifiers (V is a DC voltage and V is MCP6V2X M P the input) or inverting amplifiers (V is a DC voltage P and V is the input). The capacitances C and C rep- FIGURE 4-7: Output Resistor, R , M N G ISO resent the total capacitance at the input pins; they Stabilizes Capacitive Loads. include the op amp’s common mode input capacitance Figure4-8 gives recommended RISO values for (CCM), board parasitic capacitance and any capacitor different capacitive loads and gains. The x-axis is the placed in parallel. The capacitance CFP represents the normalized load capacitance (C /G 2). The y-axis is parasitic capacitance coupling the output and L N the normalized resistance (G R ). non-inverting input pins. N ISO G is the circuit’s noise gain. For non-inverting gains, N G and the Signal Gain are equal. For inverting gains, N G is 1+|Signal Gain| (e.g., -1 V/V gives G = +2 V/V). N N C N RN CFP 10010k VP (cid:4)) U1 R (ISO 110000 MCP6V2X N G V V d M OUT nde RG RF omme 1100 GGNN == 12 CG ec GN = 5 R GN (cid:5) 10 11 FIGURE 4-10: Amplifier with Parasitic 100p 1n 10n 100n 1μ 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 C/G 2 (F) Capacitance. L N C acts in parallel with R (except for a gain of +1V/V), FIGURE 4-8: Recommended R values G G ISO which causes an increase in gain at high frequencies. for Capacitive Loads. C also reduces the phase margin of the feedback G After selecting RISO for your circuit, double check the loop, which becomes less stable. This effect can be resulting frequency response peaking and step reduced by either reducing C or R ||R . G F G response overshoot. Modify R 's value until the ISO C and R form a low-pass filter that affects the signal response is reasonable. Bench evaluation and N N at V . This filter has a single real pole at 1/(2πR C ). simulations with the MCP6V26/7/8 SPICE macro P N N model are helpful. © 2011 Microchip Technology Inc. DS25007B-page 25

MCP6V26/7/8 The largest value of R that should be used depends supplies. Smaller resistors and capacitors are a better F on noise gain (see G in Section4.3.6, Capacitive choice for designs where the power supply is not as N Loads), C and the open-loop gain’s phase shift. An noisy. G approximate limit for R is: F V EQUATION 4-2: S_ANA 50Ω 50Ω 1/4W 1/10W 12 pF 2 RF≤2 kΩ×----C-----------×GN 0.1µF G 100µF 100µF U 1 Some applications may modify these values to reduce MCP6V2X either output loading or gain peaking (step response tootheranalogparts overshoot). At high gains, R and C need to be small in order to G G FIGURE 4-11: Additional Supply Filtering. prevent positive feedback and oscillations. 4.3.11 PCB DESIGN FOR DC PRECISION 4.3.9 REDUCING UNDESIRED NOISE AND SIGNALS In order to achieve DC precision on the order of ±1µV, many physical errors need to be minimized. The design Reduce undesired noise and signals with: of the Printed Circuit Board (PCB), the wiring and the • Low bandwidth signal filters: thermal environment has a strong impact on the - Minimizes random analog noise precision achieved. A poor PCB design can easily be more than 100 times worse than the MCP6V26/7/8 op - Reduces interfering signals amps minimum and maximum specifications. • Good PCB layout techniques: - Minimizes crosstalk 4.3.11.1 PCB Layout - Minimizes parasitic capacitances and Any time two dissimilar metals are joined together, a inductances that interact with fast switching temperature dependent voltage appears across the edges junction (the Seebeck or thermo-junction effect). This • Good power supply design: effect is used in thermocouples to measure tempera- - Provides isolation from other parts ture. The following are examples of thermo-junctions - Filters interference on supply line(s) on a PCB: • Components (resistors, op amps, …) soldered to 4.3.10 SUPPLY BYPASSING AND a copper pad FILTERING • Wires mechanically attached to the PCB With this family of op amps, the power supply pin (VDD • Jumpers for single supply) should have a local bypass capacitor • Solder joints (i.e., 0.01µF to 0.1µF) within 2mm of the pin for good • PCB vias high-frequency performance. Typical thermo-junctions have temperature to voltage These parts also need a bulk capacitor (i.e., 1µF or conversion coefficients of 10 to 100µV/°C (sometimes larger) within 100mm to provide large, slow currents. higher). This bulk capacitor can be shared with other low noise, analog parts. Microchip’s AN1258 (“Op Amp Precision Design: PCB Layout Techniques”) contains in depth information on In some cases, high-frequency power supply noise PCB layout techniques that minimize thermo-junction (e.g., switched mode power supplies) may cause effects. It also discusses other effects, such as undue intermodulation distortion, with a DC offset shift; crosstalk, impedances, mechanical stresses and this noise needs to be filtered. Adding a resistor into the humidity. supply connection can be helpful. This resistor needs to be small enough to prevent a large drop in V for DD the op amp, which would cause a reduced output range and possible load-induced power supply noise. It also needs to be large enough to dissipate little power when V is turned on and off quickly. Figure4-11 shows a DD circuit with resistors in the supply connections. It gives good rejection out to 1MHz for switched mode power DS25007B-page 26 © 2011 Microchip Technology Inc.

MCP6V26/7/8 4.3.11.2 Crosstalk 4.4 Typical Applications DC crosstalk causes offsets that appear as a larger 4.4.1 WHEATSTONE BRIDGE input offset voltage. Common causes include: Many sensors are configured as Wheatstone bridges. • Common mode noise (remote sensors) Strain gauges and pressure sensors are two common • Ground loops (current return paths) examples. These signals can be small and the • Power supply coupling common mode noise large. Amplifier designs with high Interference from the mains (usually 50Hz or 60Hz), differential gain are desirable. and other AC sources, can also affect the DC perfor- Figure4-12 shows how to interface to a Wheatstone mance. Non-linear distortion can convert these signals bridge with a minimum of components. Because the to multiple tones, including a DC shift in voltage. When circuit is not symmetric, the ADC input is single ended, the signal is sampled by an ADC, these AC signals can there is a minimum of filtering, and the CMRR is good also be aliased to DC, causing an apparent shift in enough for moderate common mode noise. offset. To reduce interference: V 0.01C 3kΩ V DD DD - Keep traces and wires as short as possible - Use shielding (e.g., encapsulant) R R 0.2R 100R ADC - Use ground plane (at least a star ground) - Place the input signal source near to the DUT R R - Use good PCB layout techniques 0.2R - Use a separate power supply filter (bypass U 1 capacitors) for these auto-zeroed op amps MCP6V26 4.3.11.3 Miscellaneous Effects FIGURE 4-12: Simple Design. Keep the resistances seen by the input pins as small Figure4-13 shows a higher performance circuit for and as near to equal as possible, to minimize bias Wheatstone bridges. This circuit is symmetric and has current-related offsets. high CMRR. Using a differential input to the ADC helps with the CMRR. Make the (trace) capacitances seen by the input pins small and equal. This is helpful in minimizing switching glitch-induced offset voltages. U 1A Bending a coax cable with a radius that is too small ½ MCP6V27 causes a small voltage drop to appear on the center 200Ω conductor (the tribo-electric effect). Make sure the bending radius is large enough to keep the conductors V DD and insulation in full contact. 1µF Mechanical stresses can make some capacitor types R R 10nF 20kΩ (such as ceramic) to output small voltages. Use more appropriate capacitor types in the signal path and 200Ω 3kΩ VDD minimize mechanical stresses and vibration. R R 1µF ADC Humidity can cause electro-chemical potential voltages to appear in a circuit. Proper PCB cleaning helps, as 200Ω 3kΩ does the use of encapsulants. 10nF 20kΩ 1µF 200Ω U 1B ½ MCP6V27 FIGURE 4-13: High Performance Design. © 2011 Microchip Technology Inc. DS25007B-page 27

MCP6V26/7/8 4.4.2 RTD SENSOR 4.4.3 THERMOCOUPLE SENSOR The ratiometric circuit in Figure4-14 conditions a three Figure4-15 shows a simplified diagram of an amplifier wire RTD. It corrects for the sensor’s wiring resistance and temperature sensor used in a thermocouple by subtracting the voltage across the middle R . The application. The type K thermocouple senses the W top R does not change the output voltage; it balances temperature at the hot junction (T ), and produces a 1 HJ the op amp inputs. Failure (open) of the RTD is voltage at V proportional to T (in °C). The amplifier’s 1 HJ detected by an out-of-range voltage. gain is set so that V /T is 10mV/°C. V represents 4 HJ 3 the output of a temperature sensor, which produces a voltage proportional to the temperature (in °C) at the U 1A cold junction (T ), and with a 0.50V offset. V is set so ½ MCP6V27 CJ 2 that V is 0.50V when T –T is 0°C. 4 HJ CJ 2.49kΩ EQUATION 4-3: V DD 100nF V ≈T (40µV/°C) 1 HJ R T V =(1.00V) 2 R 20kΩ R W 3 V =T (10mV/°C)+(0.50V) 100kΩ 3kΩ 3 CJ 10nF 2.4R91kΩ R2 VDD V4=≈(21500Vm1V+/°C(V)2(T–V3–)T )+(0.50V) HJ CJ 2.55kΩ R 1µF ADC RTD 100Ω 10nF R1 R2.255kΩ (hotjunction RTH = Thevenin Equivalent Resistance 2.49kΩ atT ) (R ) (R ) R 3kΩ HJ TH TH 3 V RW RB 100kΩ T40ypµeVK/°C 2 C 20kΩ (R )/250 U Thermocouple TH 1 R 100nF MCP6V26 W V 1 V 4 2.49kΩ (R )/250 TH (coldjunction C U½1 MBCP6V27 atTCJ) V3 (R ) (R ) TH TH FIGURE 4-14: RTD Sensor. FIGURE 4-15: Thermocouple Sensor; Simplified Circuit. The voltages at the input of the ADC can be calculated with the following: Figure4-16 shows a more complete implementation of this circuit. The dashed red arrow indicates a thermally conductive connection between the thermocouple and G = 1+2⋅R ⁄R RTD 3 2 the MCP9700A; it needs to be very short and have low G = G –R ⁄R W RTD 3 1 thermal resistance. V = G (V –V )+G V DM RTD T B W W V +V +(G +1–G )V V = ----T--------------B-----------------R---T---D------------------------W-----------W-- RTH = Thevenin Equivalent Resistance (e.g., 10kΩ) CM 2 V DD Where: 4.100(RTH) 0.5696(RTH) VREF VT = Voltage at the top of RRTD U1 C V = Voltage at the bottom of R MCP1541 B RTD TypeK (RTH)/250 U3 VW = Voltage across top and middle RW’s MCP6V26 V V = ADC’s common mode input 1 CM V = ADC’s differential mode input DM U2 V (RTH)/250 DD MCP9700A C V 4 Temp.Sensor (R ) (R ) 3kΩ TH TH FIGURE 4-16: Thermocouple Sensor. DS25007B-page 28 © 2011 Microchip Technology Inc.

MCP6V26/7/8 The MCP9700A senses the temperature at its physical location. It needs to be at the same temperature as the cold junction (T ), and produces V (Figure4-15). CJ 3 The MCP1541 produces a 4.10V output, assuming V is at 5.0V. This voltage, tied to a resistor ladder of DD 4.100(R ) and 1.3224(R ), would produce a TH TH Thevenin equivalent of 1.00V and 250(R ). The TH 1.3224(R ) resistor is combined in parallel with the TH top right R resistor (in Figure4-15), producing the TH 0.5696(R ) resistor. TH V should be converted to digital, then corrected for the 4 thermocouple’s non-linearity. The ADC can use the MCP1541 as its voltage reference. Alternately, an absolute reference inside a PICmicro® device can be used instead of the MCP1541. 4.4.4 OFFSET VOLTAGE CORRECTION Figure4-17 shows an MCP6V27 correcting the input offset voltage of another op amp. R and C integrate 2 2 the offset error seen at the other op amp’s input; the integration needs to be slow enough to be stable (with the feedback provided by R and R ). 1 3 R R 1 3 V V IN OUT R 2 C2 R4 U 2 MCP661 R2 R5 V /2 DD V /2 U DD 1 MCP6V26 FIGURE 4-17: Offset Correction. 4.4.5 PRECISION COMPARATOR Use high gain before a comparator to improve the latter’s performance. Do not use MCP6V26/7/8 as a comparator by itself; the V correction circuitry does OS not operate properly without a feedback loop. U 1 VIN MCP6V26 R 1 R2 R3 R4 R 1kΩ 5 V OUT V /2 DD U 2 MCP6541 FIGURE 4-18: Precision Comparator. © 2011 Microchip Technology Inc. DS25007B-page 29

MCP6V26/7/8 NOTES: DS25007B-page 30 © 2011 Microchip Technology Inc.

MCP6V26/7/8 5.0 DESIGN AIDS 5.4 Analog Demonstration and Evaluation Boards Microchip provides the basic design aids needed for the MCP6V26/7/8 family of op amps. Microchip offers a broad spectrum of Analog Demon- stration and Evaluation Boards that are designed to 5.1 SPICE Macro Model help customers achieve faster time to market. For a complete listing of these boards and their correspond- The latest SPICE macro model for the MCP6V26/7/8 ing user’s guides and technical information, visit the family of op amps is available on the Microchip web site Microchip web site at www.microchip.com/analogtools. at www.microchip.com. This model is intended to be an Some boards that are especially useful are: initial design tool that works well in the op amp’s linear region of operation over the temperature range. See • MCP6V01 Thermocouple Auto-Zeroed Reference the model file for information on its capabilities. Design Bench testing is a very important part of any design and • MCP6XXX Amplifier Evaluation Board 1 cannot be replaced with simulations. Also, simulation • MCP6XXX Amplifier Evaluation Board 2 results using this macro model need to be validated by • MCP6XXX Amplifier Evaluation Board 3 comparing them to the data sheet specifications and • MCP6XXX Amplifier Evaluation Board 4 characteristic curves. • Active Filter Demo Board Kit 5.2 FilterLab® Software • P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board Microchip’s FilterLab® software is an innovative • P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP software tool that simplifies analog active filter (using Evaluation Board op amps) design. Available at no cost from the Microchip web site at www.microchip.com/filterlab, the 5.5 Application Notes Filter-Lab design tool provides full schematic diagrams of the filter circuit with component values. It also The following Microchip Application Notes are outputs the filter circuit in SPICE format, which can be available on the Microchip web site at www.microchip. used with the macro model to simulate actual filter com/appnotes and are recommended as supplemental performance. reference resources. ADN003: “Select the Right Operational Amplifier for 5.3 Microchip Advanced Part Selector your Filtering Circuits”, DS21821 (MAPS) AN722: “Operational Amplifier Topologies and DC Specifications”, DS00722 MAPS is a software tool that helps efficiently identify Microchip devices that fit a particular design require- AN723: “Operational Amplifier AC Specifications and ment. Available at no cost from the Microchip website Applications”, DS00723 at www.microchip.com/maps, the MAPS is an overall AN884: “Driving Capacitive Loads With Op Amps”, selection tool for Microchip’s product portfolio that DS00884 includes Analog, Memory, MCUs and DSCs. Using this tool, a customer can define a filter to sort features for a AN990: “Analog Sensor Conditioning Circuits – An parametric search of devices and export side-by-side Overview”, DS00990 technical comparison reports. Helpful links are also AN1177: “Op Amp Precision Design: DC Errors”, provided for Data sheets, Purchase and Sampling of DS01177 Microchip parts. AN1228: “Op Amp Precision Design: Random Noise”, DS01228 AN1258: “Op Amp Precision Design: PCB Layout Techniques”, DS01258 These application notes and others are listed in the design guide: “Signal Chain Design Guide”, DS21825 © 2011 Microchip Technology Inc. DS25007B-page 31

MCP6V26/7/8 NOTES: DS25007B-page 32 © 2011 Microchip Technology Inc.

MCP6V26/7/8 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead DFN (4x4x0.9 mm) (MCP6V27) Example XXXXXX 6V27 XXXXXX E/MDe3 YYWW 1129 256 NNN PIN 1 PIN 1 8-Lead MSOP (3x3 mm) Example 6V27E 129256 8-Lead SOIC (3.90 mm) Example MCP6V27E SN^e^31129 NNN 256 8-Lead TDFN (2x3x0.75 mm) (MCP6V26, MCP6V28) Example Device Code ABA 129 MCP6V26T-E/MNY ABA 25 MCP6V28T-E/MNY ABB Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e 3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2011 Microchip Technology Inc. DS25007B-page 33

MCP6V26/7/8 8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging MicrochipTechnologyDrawingC04-131E Sheet 1 of 2 DS25007B-page 34 © 2011 Microchip Technology Inc.

MCP6V26/7/8 8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging MicrochipTechnologyDrawingC04-131E Sheet 2 of 2 © 2011 Microchip Technology Inc. DS25007B-page 35

MCP6V26/7/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25007B-page 36 © 2011 Microchip Technology Inc.

MCP6V26/7/8 (cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:14)(cid:15)(cid:17)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:11)(cid:11)(cid:9)(cid:21)(cid:22)(cid:13)(cid:11)(cid:14)(cid:23)(cid:6)(cid:9)(cid:10)(cid:7)(cid:15)(cid:24)(cid:7)(cid:25)(cid:6)(cid:9)(cid:26)(cid:16)(cid:19)(cid:27)(cid:9)(cid:28)(cid:16)(cid:19)(cid:21)(cid:10)(cid:29) (cid:30)(cid:18)(cid:13)(cid:6)(cid:31) 1(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)2(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)2(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)033)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&3(cid:12)(cid:28)(cid:8)2(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 e b c A A2 φ A1 L1 L 4(cid:15)(cid:7)% (cid:6)(cid:19)55(cid:19)(cid:6)*(cid:13)*(cid:26)(cid:22) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)5(cid:7)&(cid:7)% (cid:6)(cid:19)6 67(cid:6) (cid:6)(cid:25)8 6!&((cid:14)(cid:9)(cid:2)(cid:10)$(cid:2)(cid:30)(cid:7)(cid:15) 6 9 (cid:30)(cid:7)%(cid:8)(cid:11) (cid:14) (cid:4)(cid:20):+(cid:2).(cid:22)/ 7(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2);(cid:14)(cid:7)(cid:17)(cid:11)% (cid:25) < < (cid:29)(cid:20)(cid:29)(cid:4) (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)2(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)2(cid:15)(cid:14) (cid:25)(cid:3) (cid:4)(cid:20)(cid:5)+ (cid:4)(cid:20)9+ (cid:4)(cid:20)(cid:24)+ (cid:22)%(cid:28)(cid:15)"(cid:10)$$(cid:2) (cid:25)(cid:29) (cid:4)(cid:20)(cid:4)(cid:4) < (cid:4)(cid:20)(cid:29)+ 7(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)"%(cid:11) * (cid:23)(cid:20)(cid:24)(cid:4)(cid:2).(cid:22)/ (cid:6)(cid:10)(cid:16)"(cid:14)"(cid:2)(cid:30)(cid:28)(cid:8)2(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)"%(cid:11) *(cid:29) ,(cid:20)(cid:4)(cid:4)(cid:2).(cid:22)/ 7(cid:31)(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)5(cid:14)(cid:15)(cid:17)%(cid:11) (cid:21) ,(cid:20)(cid:4)(cid:4)(cid:2).(cid:22)/ 1(cid:10)(cid:10)%(cid:2)5(cid:14)(cid:15)(cid:17)%(cid:11) 5 (cid:4)(cid:20)(cid:23)(cid:4) (cid:4)(cid:20):(cid:4) (cid:4)(cid:20)9(cid:4) 1(cid:10)(cid:10)%(cid:12)(cid:9)(cid:7)(cid:15)% 5(cid:29) (cid:4)(cid:20)(cid:24)+(cid:2)(cid:26)*1 1(cid:10)(cid:10)%(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)> < 9> 5(cid:14)(cid:28)"(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)2(cid:15)(cid:14) (cid:8) (cid:4)(cid:20)(cid:4)9 < (cid:4)(cid:20)(cid:3), 5(cid:14)(cid:28)"(cid:2)=(cid:7)"%(cid:11) ( (cid:4)(cid:20)(cid:3)(cid:3) < (cid:4)(cid:20)(cid:23)(cid:4) (cid:30)(cid:18)(cid:13)(cid:6)(cid:12)(cid:31) (cid:29)(cid:20) (cid:30)(cid:7)(cid:15)(cid:2)(cid:29)(cid:2)(cid:31)(cid:7) !(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)"(cid:14)#(cid:2)$(cid:14)(cid:28)%!(cid:9)(cid:14)(cid:2)&(cid:28)(cid:18)(cid:2)(cid:31)(cid:28)(cid:9)(cid:18)’(cid:2)(!%(cid:2)&! %(cid:2)((cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2))(cid:7)%(cid:11)(cid:7)(cid:15)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)%(cid:8)(cid:11)(cid:14)"(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)"(cid:2)*(cid:29)(cid:2)"(cid:10)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)!"(cid:14)(cid:2)&(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)"(cid:2)$(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)%(cid:9)! (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)%(cid:2)(cid:14)#(cid:8)(cid:14)(cid:14)"(cid:2)(cid:4)(cid:20)(cid:29)+(cid:2)&&(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)"(cid:14)(cid:20) ,(cid:20) (cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)"(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)*(cid:2)-(cid:29)(cid:23)(cid:20)+(cid:6)(cid:20) .(cid:22)/0 .(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)%(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)#(cid:28)(cid:8)%(cid:2)(cid:31)(cid:28)(cid:16)!(cid:14)(cid:2) (cid:11)(cid:10))(cid:15)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:26)*10 (cid:26)(cid:14)$(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)&(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)’(cid:2)! !(cid:28)(cid:16)(cid:16)(cid:18)(cid:2))(cid:7)%(cid:11)(cid:10)!%(cid:2)%(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)’(cid:2)$(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)$(cid:10)(cid:9)&(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)!(cid:9)(cid:12)(cid:10) (cid:14) (cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28))(cid:7)(cid:15)(cid:17)/(cid:4)(cid:23)(cid:27)(cid:29)(cid:29)(cid:29). © 2011 Microchip Technology Inc. DS25007B-page 37

MCP6V26/7/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25007B-page 38 © 2011 Microchip Technology Inc.

MCP6V26/7/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc. DS25007B-page 39

MCP6V26/7/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25007B-page 40 © 2011 Microchip Technology Inc.

MCP6V26/7/8 (cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:19)(cid:20)(cid:7)(cid:11)(cid:11)(cid:9)(cid:21)(cid:22)(cid:13)(cid:11)(cid:14)(cid:23)(cid:6)(cid:9)(cid:26)(cid:19)(cid:30)(cid:27)(cid:9) (cid:9)(cid:30)(cid:7)(cid:17)(cid:17)(cid:18)!"(cid:9)#$%&(cid:9)(cid:20)(cid:20)(cid:9)’(cid:18)(cid:8)((cid:9)(cid:28)(cid:19)(cid:21))*(cid:29) (cid:30)(cid:18)(cid:13)(cid:6)(cid:31) 1(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)2(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)2(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)033)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&3(cid:12)(cid:28)(cid:8)2(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) © 2011 Microchip Technology Inc. DS25007B-page 41

MCP6V26/7/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25007B-page 42 © 2011 Microchip Technology Inc.

MCP6V26/7/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc. DS25007B-page 43

MCP6V26/7/8 (cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)+(cid:22)(cid:7)(cid:11)(cid:9),(cid:11)(cid:7)(cid:13)"(cid:9)(cid:30)(cid:18)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)(cid:24)(cid:7)(cid:25)(cid:6)(cid:9)(cid:26)(cid:16)(cid:30)(cid:27)(cid:9) (cid:9)-.#.&$/0(cid:9)(cid:20)(cid:20)(cid:9)’(cid:18)(cid:8)((cid:9)(cid:28)1+,(cid:30)(cid:29) (cid:30)(cid:18)(cid:13)(cid:6)(cid:31) 1(cid:10)(cid:9)(cid:2)%(cid:11)(cid:14)(cid:2)&(cid:10) %(cid:2)(cid:8)!(cid:9)(cid:9)(cid:14)(cid:15)%(cid:2)(cid:12)(cid:28)(cid:8)2(cid:28)(cid:17)(cid:14)(cid:2)"(cid:9)(cid:28))(cid:7)(cid:15)(cid:17) ’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)%(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:30)(cid:28)(cid:8)2(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)$(cid:7)(cid:8)(cid:28)%(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)%(cid:14)"(cid:2)(cid:28)%(cid:2) (cid:11)%%(cid:12)033)))(cid:20)&(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)&3(cid:12)(cid:28)(cid:8)2(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS25007B-page 44 © 2011 Microchip Technology Inc.

MCP6V26/7/8 APPENDIX A: REVISION HISTORY Revision B (August 2011) The following is the list of modifications: 1. Added the MCP6V26 and MCP6V28 single op amps. a) Updated package drawings on page 1. b) Updated the pinout table (Table3-1). c) Added 8-lead, 2×3TDFN package to the Thermal Characteristics Table (Table1-4). d) Added 8-lead, 2×3TDFN package to Section6.0 “Packaging Information”. e) Added parts numbers to Product Identifica- tion System. 2. Added Chip Select (CS) information. a) Added Digital Electrical Specifications table (Table1-3). b) Added Timing Diagram (Figure1-4). c) Added Section2.6 “Chip Select Response (MCP6V28 only)” to the Typical Performance Curves. d) Added Section4.2.3 “Chip Select (CS)” to the applications write up. 3. Added information on positive feedback and parasitic feedback capacitance. a) Added to Section4.3.4 “Source Resistances”. b) Added to Section4.3.5 “Source Capacitance”. c) Modified Figure4-10. d) Added to Section4.3.8 “Gain Peaking”. 4. Other minor typographical corrections. Revision A (March 2011) • Original data sheet for the MCP6V27 dual op amps. © 2011 Microchip Technology Inc. DS25007B-page 45

MCP6V26/7/8 APPENDIX B: OFFSET RELATED We use production screens to ensure the quality of our TEST SCREENS outgoing products. These screens are set at wider limits to eliminate any fliers; see TableB-1. Input offset voltage-related specifications in the DC spec table (Table1-1) are based on bench measurements (see Section2.1 “DC Input Precision”). These measurements are much more accurate because: • More compact circuit • Soldered parts on the PCB (to validate other measurements) • More time spent averaging (reduces noise) • Better temperature control - Reduced temperature gradients - Greater accuracy TABLE B-1: OFFSET RELATED TEST SCREENS Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +2.3V to +5.5V, V = GND, A DD SS V = V /3, V =V /2, V =V /2, R = 10kΩ to V and CS = GND (refer to Figure1-5 and Figure1-6). CM DD OUT DD L DD L L Parameters Sym Min Max Units Conditions Input Offset Input Offset Voltage V -10 +10 µV T = +25°C (Note1, Note2) OS A Input Offset Voltage Drift with Temperature TC — — nV/°C T = -40 to +125°C (Note3) 1 A (linear Temp. Co.) Power Supply Rejection PSRR 115 — dB (Note1) Common Mode Common Mode Rejection CMRR 106 — dB V = 2.3V, V = -0.15V to 2.5V (Note1) DD CM CMRR 116 — dB V = 5.5V, V = -0.15V to 5.7V (Note1) DD CM Open-Loop Gain DC Open-Loop Gain (large signal) A 114 — dB V =2.3V, V = 0.2V to 2.1V (Note1) OL DD OUT A 122 — dB V =5.5V, V = 0.2V to 5.3V (Note1) OL DD OUT Note 1: Due to thermal junctions and other errors in the production environment, these specifications are only screened in production. 2: V is also sample screened at +125°C. OS 3: TC is not measured in production. 1 DS25007B-page 46 © 2011 Microchip Technology Inc.

MCP6V26/7/8 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Examples: PART NO. –X /XX a) MCP6V26T-E/MNY: Extended temperature, Device Temperature Package 8LD 2×3 TDFN Range package b) MCP6V26-E/MS: Extended temperature, 8LD MSOP package Device: MCP6V26 Single Op Amp a) MCP6V26T-E/SN: Tape and Reel, MCP6V26T Single Op Amp (Tape and Reel) Extended temperature, MCP6V27 Dual Op Amp 8LD SOIC package MCP6V27T Dual Op Amp (Tape and Reel) a) MCP6V27-E/MD: Extended temperature, MCP6V28 Single Op Amp with Chip Select 8LD 4x4 DFN package MCP6V28T Single Op Amp with Chip Select (Tape and Reel) b) MCP6V27-E/MS: Extended temperature, 8LD MSOP package c) MCP6V27-E/SN: Extended temperature, Temperature Range: E = -40°C to +125°C 8LD SOIC package a) MCP6V28T-E/MNY: Extended temperature, 8LD 2×3 TDFN Package: MD = Plastic Dual Flat, No-Lead (4×4x0.9), 8-lead package MNY* = Plastic Dual Flat, No-Lead (2×3x0.75), 8-lead MS = Plastic Micro Small Outline Package, 8-lead b) MCP6V28-E/MS: Extended temperature, SN = Plastic SOIC (150mil Body), 8-lead 8LD MSOP package c) MCP6V28T-E/SN: Tape and Reel, *Y=Nickel Palladium gold manufacturing designator. Only Extended temperature, available on the TDFN package. 8LD SOIC package © 2011 Microchip Technology Inc. DS25007B-page 47

MCP6V26/7/8 NOTES: DS25007B-page 48 © 2011 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, chipKIT, devices in life support and/or safety applications is entirely at chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, hold harmless Microchip from any and all damages, claims, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, suits, or expenses resulting from such use. No licenses are Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, conveyed, implicitly or otherwise, under any Microchip MPLINK, mTouch, Omniscient Code Generation, PICC, intellectual property rights. PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-503-0 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2011 Microchip Technology Inc. DS25007B-page 49

Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Asia Pacific Office India - Bangalore Austria - Wels 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-3090-4444 Tel: 43-7242-2244-39 Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-3090-4123 Fax: 43-7242-2244-393 Tel: 480-792-7200 Harbour City, Kowloon India - New Delhi Denmark - Copenhagen Fax: 480-792-7277 Hong Kong Tel: 91-11-4160-8631 Tel: 45-4450-2828 Technical Support: Tel: 852-2401-1200 Fax: 91-11-4160-8632 Fax: 45-4485-2829 http://www.microchip.com/ support Fax: 852-2401-3431 India - Pune France - Paris Web Address: Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20 www.microchip.com Tel: 61-2-9868-6733 Fax: 91-20-2566-1513 Fax: 33-1-69-30-90-79 Atlanta Fax: 61-2-9868-6755 Japan - Yokohama Germany - Munich Duluth, GA China - Beijing Tel: 81-45-471- 6166 Tel: 49-89-627-144-0 Tel: 86-10-8569-7000 Fax: 49-89-627-144-44 Tel: 678-957-9614 Fax: 81-45-471-6122 Fax: 678-957-1455 Fax: 86-10-8528-2104 Korea - Daegu Italy - Milan Boston China - Chengdu Tel: 82-53-744-4301 Tel: 39-0331-742611 Westborough, MA Tel: 86-28-8665-5511 Fax: 82-53-744-4302 Fax: 39-0331-466781 Tel: 774-760-0087 Fax: 86-28-8665-7889 Korea - Seoul Netherlands - Drunen Fax: 774-760-0088 China - Chongqing Tel: 82-2-554-7200 Tel: 31-416-690399 Chicago Tel: 86-23-8980-9588 Fax: 82-2-558-5932 or Fax: 31-416-690340 Itasca, IL Fax: 86-23-8980-9500 82-2-558-5934 Spain - Madrid Tel: 630-285-0071 China - Hangzhou Malaysia - Kuala Lumpur Tel: 34-91-708-08-90 Fax: 630-285-0075 Tel: 86-571-2819-3187 Tel: 60-3-6201-9857 Fax: 34-91-708-08-91 Cleveland Fax: 86-571-2819-3189 Fax: 60-3-6201-9859 UK - Wokingham Independence, OH China - Hong Kong SAR Malaysia - Penang Tel: 44-118-921-5869 Tel: 216-447-0464 Tel: 852-2401-1200 Tel: 60-4-227-8870 Fax: 44-118-921-5820 Fax: 216-447-0643 Fax: 852-2401-3431 Fax: 60-4-227-4068 Dallas China - Nanjing Philippines - Manila Addison, TX Tel: 86-25-8473-2460 Tel: 63-2-634-9065 Tel: 972-818-7423 Fax: 86-25-8473-2470 Fax: 63-2-634-9069 Fax: 972-818-2924 China - Qingdao Singapore Detroit Tel: 86-532-8502-7355 Tel: 65-6334-8870 Farmington Hills, MI Fax: 86-532-8502-7205 Fax: 65-6334-8850 Tel: 248-538-2250 Fax: 248-538-2260 China - Shanghai Taiwan - Hsin Chu Tel: 86-21-5407-5533 Tel: 886-3-5778-366 Indianapolis Fax: 86-21-5407-5066 Fax: 886-3-5770-955 Noblesville, IN Tel: 317-773-8323 China - Shenyang Taiwan - Kaohsiung Fax: 317-773-5453 Tel: 86-24-2334-2829 Tel: 886-7-536-4818 Fax: 86-24-2334-2393 Fax: 886-7-330-9305 Los Angeles Mission Viejo, CA China - Shenzhen Taiwan - Taipei Tel: 86-755-8203-2660 Tel: 886-2-2500-6610 Tel: 949-462-9523 Fax: 949-462-9608 Fax: 86-755-8203-1760 Fax: 886-2-2508-0102 China - Wuhan Thailand - Bangkok Santa Clara Santa Clara, CA Tel: 86-27-5980-5300 Tel: 66-2-694-1351 Tel: 408-961-6444 Fax: 86-27-5980-5118 Fax: 66-2-694-1350 Fax: 408-961-6445 China - Xian Tel: 86-29-8833-7252 Toronto Mississauga, Ontario, Fax: 86-29-8833-7256 Canada China - Xiamen Tel: 905-673-0699 Tel: 86-592-2388138 Fax: 905-673-6509 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 08/02/11 Fax: 86-756-3210049 DS25007B-page 50 © 2011 Microchip Technology Inc.