MCP4801/4811/4821 8/10/12-Bit Voltage Output Digital-to-Analog Converter with Internal V and SPI Interface REF Features Description • MCP4801: 8-Bit Voltage Output DAC The MCP4801/4811/4821 devices are single channel • MCP4811: 10-Bit Voltage Output DAC 8-bit, 10-bit and 12-bit buffered voltage output Digital-to-Analog Converters (DACs), respectively. The • MCP4821: 12-Bit Voltage Output DAC devices operate from a single 2.7V to 5.5V supply with • Rail-to-Rail Output an SPI compatible Serial Peripheral Interface. • SPI Interface with 20MHz Clock Support The devices have a high precision internal voltage • Simultaneous Latching of the DAC Output reference (V = 2.048V). The user can configure the REF with LDAC Pin full-scale range of the device to be 2.048V or 4.096V by • Fast Settling Time of 4.5µs setting the Gain Selection Option bit (gain of 1 of 2). • Selectable Unity or 2x Gain Output The devices can be operated in Active or Shutdown • 2.048V Internal Voltage Reference mode by setting a Configuration register bit or using the • 50ppm/°C V Temperature Coefficient SHDN pin. In Shutdown mode, most of the internal REF circuits, including the output amplifier, are turned off for • 2.7V to 5.5V Single-Supply Operation power savings, while the amplifier output (V ) stage is OUT • Extended Temperature Range:-40°C to +125°C configured to present a known high resistance output load (500ktypical. Applications The devices include double-buffered registers, • Set Point or Offset Trimming allowing a synchronous update of the DAC output using the LDAC pin. These devices also incorporate a • Sensor Calibration Power-on Reset (POR) circuit to ensure reliable power- • Precision Selectable Voltage Reference up. • Portable Instrumentation (Battery-Powered) The devices utilize a resistive string architecture, with • Calibration of Optical Communication Devices its inherent advantages of low DNL error, low ratio metric temperature coefficient and fast settling time. Related Products(1) These devices are specified over the extended temperature range (+125°C). DAC No. of Voltage The devices provide high accuracy and low noise P/N Resolution Channel Reference performance for consumer and industrial applications (VREF) where calibration or compensation of signals (such as MCP4801 8 1 temperature, pressure and humidity) are required. MCP4811 10 1 The MCP4801/4811/4821 devices are available in the PDIP, SOIC, MSOP and DFN packages. MCP4821 12 1 Internal MCP4802 8 2 (2.048V) MCP4812 10 2 MCP4822 12 2 MCP4901 8 1 MCP4911 10 1 MCP4921 12 1 External MCP4902 8 2 MCP4912 10 2 MCP4922 12 2 Note1: The products listed here have similar AC/DC performances.  2010 Microchip Technology Inc. DS22244B-page 1

MCP4801/4811/4821 Package Types PDIP, SOIC, MSOP DFN (2x3)* VDD 1 8 VOUT VDD 1 8 VOUT 1 CS 2 8X 7 VSS CS 2 7 VSS 4 9 SCK 3 P 6 SHDN SCK 3 6 SHDN C SDI 4 M 5 LDAC SDI 4 5 LDAC MCP4801: 8-bit single DAC MCP4811: 10-bit single DAC MCP4821: 12-bit single DAC * Includes Exposed Thermal Pad (EP); see Table3-1. Block Diagram LDAC CS SDI SCK Interface Logic Power-on VDD Reset Input Register V SS DAC VREF Register (2.048V) String DAC Gain Output Logic Op Amp Output Logic SHDN VOUT DS22244B-page 2  2010 Microchip Technology Inc.

MCP4801/4811/4821 1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is CHARACTERISTICS a stress rating only and functional operation of the device at those or any other conditions above those indicated in the Absolute Maximum Ratings † operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods VDD............................................................................................................. 6.5V may affect device reliability. All inputs and outputs .....................V – 0.3V to V + 0.3V SS DD Current at Input Pins ....................................................±2mA Current at Supply Pins ...............................................±50mA Current at Output Pins ...............................................±25mA Storage temperature.....................................-65°C to +150°C Ambient temp. with power applied................-55°C to +125°C ESD protection on all pins 4kV (HBM), 400V (MM) Maximum Junction Temperature (T )..........................+150°C J ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V = 5V, V = 0V, V = 2.048V, DD SS REF Output Buffer Gain (G) = 2x, RL = 5k to GND, C = 100pF, T = -40 to +85°C. Typical values are at +25°C. L A Parameters Sym Min Typ Max Units Conditions Power Requirements Operating Voltage V 2.7 — 5.5 DD Operating Current I — 330 400 µA All digital inputs are grounded, DD analog output (V ) is OUT unloaded. Code=000h Hardware Shutdown Current I — 0.3 2 µA POR circuit is turned off SHDN Software Shutdown Current I — 3.3 6 µA POR circuit remains turned on SHDN_SW Power-on Reset Threshold V — 2.0 — V POR DC Accuracy MCP4801 Resolution n 8 — — Bits INL Error INL -1 ±0.125 1 LSb DNL DNL -0.5 ±0.1 +0.5 LSb Note1 MCP4811 Resolution n 10 — — Bits INL Error INL -3.5 ±0.5 3.5 LSb DNL DNL -0.5 ±0.1 +0.5 LSb Note1 MCP4821 Resolution n 12 — — Bits INL Error INL -12 ±2 12 LSb DNL DNL -0.75 ±0.2 +0.75 LSb Note1 Offset Error V -1 ±0.02 1 % of FSR Code = 0x000h OS Offset Error Temperature — 0.16 — ppm/°C -45°C to +25°C V /°C Coefficient OS — -0.44 — ppm/°C +25°C to +85°C Gain Error g -2 -0.10 2 % of FSR Code = 0xFFFh, E not including offset error Gain Error Temperature G/°C — -3 — ppm/°C Coefficient Note 1: Guaranteed monotonic by design over all codes. 2: This parameter is ensured by design, and not 100% tested.  2010 Microchip Technology Inc. DS22244B-page 3

MCP4801/4811/4821 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, V = 5V, V = 0V, V = 2.048V, DD SS REF Output Buffer Gain (G) = 2x, RL = 5k to GND, C = 100pF, T = -40 to +85°C. Typical values are at +25°C. L A Parameters Sym Min Typ Max Units Conditions Internal Voltage Reference (V ) REF Internal Reference Voltage V 2.008 2.048 2.088 V V when G = 1x and REF OUT Code = 0xFFFh Temperature Coefficient — 125 325 ppm/°C -40°C to 0°C (Note2) — 0.25 0.65 LSb/°C -40°C to 0°C V /°C REF — 45 160 ppm/°C 0°C to +85°C — 0.09 0.32 LSb/°C 0°C to +85°C Output Noise (V Noise) E — 290 — µV Code = 0xFFFh, G = 1x REF NREF p-p (0.1-10Hz) Output Noise Density e — 1.2 — µV/Hz Code = 0xFFFh, G = 1x NREF (1kHz) e — 1.0 — µV/Hz Code = 0xFFFh, G = 1x NREF (10kHz) 1/f Corner Frequency f — 400 — Hz CORNER Output Amplifier Output Swing V — 0.01 to — V Accuracy is better than 1LSb OUT V – 0.04 for V = 10mV to DD OUT (V –40mV) DD Phase Margin PM — 66 — Degree (°) C = 400 pF, R =  L L Slew Rate SR — 0.55 — V/µs Short Circuit Current I — 15 24 mA SC Settling Time t — 4.5 — µs Within ½LSb of final value SETTLING from ¼ to ¾ full-scale range Dynamic Performance (Note2) Major Code Transition Glitch — 45 — nV-s 1LSb change around major carry (0111...1111 to 1000...0000) Digital Feedthrough — <10 — nV-s Note 1: Guaranteed monotonic by design over all codes. 2: This parameter is ensured by design, and not 100% tested. DS22244B-page 4  2010 Microchip Technology Inc.

MCP4801/4811/4821 ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE Electrical Specifications: Unless otherwise indicated, V = 5V, V = 0V, V = 2.048V, Output Buffer Gain (G) = 2x, DD SS REF R = 5k to GND, C = 100pF. Typical values are at +125°C by characterization or simulation. L L Parameters Sym Min Typ Max Units Conditions Power Requirements Operating Voltage V 2.7 — 5.5 DD Operating Current I — 350 — µA All digital inputs are grounded, DD analog output (V ) is OUT unloaded. Code=000h Hardware Shutdown I — 1.5 — µA POR circuit is turned off SHDN Current Software Shutdown Current I — 5 — µA POR circuit remains turned on SHDN_SW Power-on Reset threshold V — 1.85 — V POR DC Accuracy MCP4801 Resolution n 8 — — Bits INL Error INL — ±0.25 — LSb DNL DNL — ±0.2 — LSb Note1 MCP4811 Resolution n 10 — — Bits INL Error INL — ±1 — LSb DNL DNL — ±0.2 — LSb Note1 MCP4821 Resolution n 12 — — Bits INL Error INL — ±4 — LSb DNL DNL — ±0.25 — LSb Note1 Offset Error V — ±0.02 — % of FSR Code = 0x000h OS Offset Error Temperature V /°C — -5 — ppm/°C +25°C to +125°C OS Coefficient Gain Error g — -0.10 — % of FSR Code = 0xFFFh, E not including offset error Gain Error Temperature G/°C — -3 — ppm/°C Coefficient Internal Voltage Reference (V ) REF Internal Reference Voltage V — 2.048 — V V when G = 1x and REF OUT Code = 0xFFFh Temperature Coefficient V /°C — 125 — ppm/°C -40°C to 0°C REF (Note2) — 0.25 — LSb/°C -40°C to 0°C — 45 — ppm/°C 0°C to +85°C — 0.09 — LSb/°C 0°C to +85°C Output Noise (V Noise) E — 290 — µV Code = 0xFFFh, G = 1x REF NREF p-p (0.1 – 10Hz) Output Noise Density eNREF — 1.2 — µV/Hz Code = 0xFFFh, G = 1x (1kHz) eNREF — 1.0 — µV/Hz Code = 0xFFFh, G = 1x (10kHz) 1/f Corner Frequency f — 400 — Hz CORNER Note 1: Guaranteed monotonic by design over all codes. 2: This parameter is ensured by design, and not 100% tested.  2010 Microchip Technology Inc. DS22244B-page 5

MCP4801/4811/4821 ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE (CONTINUED) Electrical Specifications: Unless otherwise indicated, V = 5V, V = 0V, V = 2.048V, Output Buffer Gain (G) = 2x, DD SS REF R = 5k to GND, C = 100pF. Typical values are at +125°C by characterization or simulation. L L Parameters Sym Min Typ Max Units Conditions Output Amplifier Output Swing V — 0.01 to — V Accuracy is better than 1LSb OUT V – 0.04 for V = 10mV to (V – DD OUT DD 40mV) Phase Margin PM — 66 — Degree (°) C = 400pF, R =  L L Slew Rate SR — 0.55 — V/µs Short Circuit Current I — 17 — mA SC Settling Time t — 4.5 — µs Within ½ LSb of final value from SETTLING ¼ to ¾ full-scale range Dynamic Performance (Note2) Major Code Transition — 45 — nV-s 1 LSb change around major Glitch carry (0111...1111 to 1000...0000) Digital Feedthrough — <10 — nV-s Note 1: Guaranteed monotonic by design over all codes. 2: This parameter is ensured by design, and not 100% tested. AC CHARACTERISTICS (SPI TIMING SPECIFICATIONS) Electrical Specifications: Unless otherwise indicated, V = 2.7V – 5.5V, T = -40 to +125°C. Typical values are at +25°C. DD A Parameters Sym Min Typ Max Units Conditions Schmitt Trigger High-Level Input V 0.7V — — V IH Voltage (All digital input pins) DD Schmitt Trigger Low-Level Input V — — 0.2V V IL DD Voltage (All digital input pins) Hysteresis of Schmitt Trigger Inputs V — 0.05V — HYS DD Input Leakage Current I -1 — 1 A SHDN = LDAC = CS = SDI = LEAKAGE SCK = V or V DD SS Digital Pin Capacitance C , — 10 — pF V = 5.0V, T = +25°C, IN DD A (All inputs/outputs) C f = 1MHz (Note1) OUT CLK Clock Frequency F — — 20 MHz T = +25°C (Note1) CLK A Clock High Time t 15 — — ns Note1 HI Clock Low Time t 15 — — ns Note1 LO CS Fall to First Rising CLK Edge t 40 — — ns Applies only when CS falls with CSSR CLK high. (Note1) Data Input Setup Time t 15 — — ns Note1 SU Data Input Hold Time t 10 — — ns Note1 HD SCK Rise to CS Rise Hold Time t 15 — — ns Note1 CHS CS High Time t 15 — — ns Note1 CSH LDAC Pulse Width t 100 — — ns Note1 LD LDAC Setup Time t 40 — — ns Note1 LS SCK Idle Time before CS Fall t 40 — — ns Note1 IDLE Note 1: This parameter is ensured by design and not 100% tested. DS22244B-page 6  2010 Microchip Technology Inc.

MCP4801/4811/4821 t CSH CS t IDLE tCSSR tHI tLO tCHS Mode 1,1 SCK Mode 0,0 t t SU HD SDI MSb in LSb in LDAC t t LS LD FIGURE 1-1: SPI Input Timing Data. TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V =+2.7V to +5.5V, V =GND. DD SS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T -40 — +125 °C A Operating Temperature Range T -40 — +125 °C Note1 A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 8L-DFN (2x3)  — 68 — °C/W JA Thermal Resistance, 8L-MSOP  — 211 — °C/W JA Thermal Resistance, 8L-PDIP  — 90 — °C/W JA Thermal Resistance, 8L-SOIC  — 150 — °C/W JA Note 1: The MCP4801/4811/4821 devices operate over this extended temperature range, but with reduced performance. Operation in this range must not cause T to exceed the maximum junction temperature J of +150°C.  2010 Microchip Technology Inc. DS22244B-page 7

MCP4801/4811/4821 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = 2.048V, Gain = 2, R = 5k, C = 100pF. A DD SS REF L L 0.3 5 Ambient Temperature 4 0.2 125C 85 25 3 NL (LSB) 0.01 L (LSB) -1012 D -0.1 N I -2 -0.2 -3 -4 -0.3 -5 0 1024 2048 3072 4096 0 1024 2048 3072 4096 Code (Decimal) Code (Decimal) FIGURE 2-1: DNL vs. Code (MCP4821). FIGURE 2-4: INL vs. Code and Temperature (MCP4821). 2.5 0.2 2 0.1 B) S NL (LSB) 0 ute INL (L 1.15 D ol -0.1 bs 0.5 A 0 -0.2 -40 -20 0 20 40 60 80 100 120 0 1024 2048 3072 4096 Code (Decimal) 125C 85C 25C Ambient Temperature (ºC) FIGURE 2-2: DNL vs. Code and FIGURE 2-5: Absolute INL vs. Temperature (MCP4821). Temperature (MCP4821). 0.0766 2 0.0764 SB) 0.0762 0 L e DNL ( 0.00.705786 L (LSB) -2 solut 00..00775546 IN -4 b A 0.0752 0.075 -6 -40 -20 0 20 40 60 80 100 120 0 1024 2048 3072 4096 Ambient Temperature (ºC) Code (Decimal) FIGURE 2-3: Absolute DNL vs. FIGURE 2-6: INL vs. Code (MCP4821). Temperature (MCP4821). Note: Single device graph for illustration of 64 code effect. DS22244B-page 8  2010 Microchip Technology Inc.

MCP4801/4811/4821 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = 2.048V, Gain = 2, R = 5k, C = 100pF. A DD SS REF L L 0.3 0.6 - 40oC - 40oC 0.5 0.2 0.4 85oC B) 0.1 B) 0.3 S S 0.2 DNL (L -0.10 INL (L 0.01 -0.1 125oC 25oC -0.2 -0.2 +25oC to +125oC -0.3 -0.3 0 32 64 96 128 160 192 224 256 0 128 256 384 512 640 768 896 1024 Code Code FIGURE 2-7: DNL vs. Code and FIGURE 2-10: INL vs. Code and Temperature (MCP4811). Temperature (MCP4801). 1.5 2.050 1 2.049 0.5 V) 2.048 0 85oC (UT 2.047 B) VO 2.046 INL (LS--10-..551 ull Scale 222...000444345 VVVDDDDDD::: 432VV.7V -2 25oC F 2.042 -2.5 - 40oC 2.041 125oC 2.040 -3 -40 -20 0 20 40 60 80 100 120 0 128 256 384 512 640 768 896 1024 Code Ambient Temperature (°C) FIGURE 2-8: INL vs. Code and FIGURE 2-11: Full-Scale V vs. Ambient OUT Temperature (MCP4811). Temperature and V . Gain = 1x. DD 0.15 4.100 Temperature: - 40oC to +125oC 0.1 4.096 V) B) 0.05 (UT4.092 NL (LS 0 34 cale VO4.088 VVDDDD:: 55.V5V D-0.05 ull S 4.084 -0.1 F 4.080 -0.15 4.076 0 32 64 96 128 160 192 224 256 -40 -20 0 20 40 60 80 100 120 Code Ambient Temperature (°C) FIGURE 2-9: DNL vs. Code and FIGURE 2-12: Full-Scale V vs. Ambient OUT Temperature (MCP4801). Temperature and V . Gain = 2x. DD  2010 Microchip Technology Inc. DS22244B-page 9

MCP4801/4811/4821 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = 2.048V, Gain = 2, R = 5k, C = 100pF. A DD SS REF L L 20 11.E0-004 nsity 1168 e D e 14 ge 1.E1-005 nc 12 Noise Volta(µV/Hz)1.E-106 Occurre 14680 ut 2 utp 0 O 1.0E.-107 65 70 75 80 85 90 95 00 05 10 15 20 20 2 2 2 2 2 2 2 3 3 3 3 3 3 10E.1-1 1E1+0 11E0+1 11E0+02 11Ek+3 11E0+k4 11E00+k5 > I (µA) Frequency (Hz) DD FIGURE 2-13: Output Noise Voltage FIGURE 2-16: IDD Histogram (VDD = 2.7V). Density (V Noise Density) vs. Frequency. REF Gain = 1x. 1.E1-00.20 18 V) 16 m 14 e Voltage (1.E1-.0030 Eni (in VP-P) currence 11802 ois Oc 6 N1.E0-.0140 4 put Eni (in VRMS) 2 Out 0 Maximum Measurement Time = 10s 1.E0-.0051 85 90 95 00 05 10 15 20 25 30 35 40 45 50 50 11E0+02 1E1k+3 11E0+k4 11E00+k5 11EM+6 2 2 2 3 3 3I3 (3µA)3 3 3 3 3 3 >3 Bandwidth (Hz) DD FIGURE 2-14: Output Noise Voltage FIGURE 2-17: I Histogram (V = 5.0V). DD DD (V Noise Voltage) vs. Bandwidth. Gain = 2x. REF 340 5.5V 320 5.0V 4.0V 300 3.0V 2.7V A)280 VDD (µD260 D I240 220 200 180 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (°C) FIGURE 2-15: I vs. Temperature and V . DD DD DS22244B-page 10  2010 Microchip Technology Inc.

MCP4801/4811/4821 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = 2.048V, Gain = 2, R = 5k, C = 100pF. A DD SS REF L L 0.7 5.5V -0.05 0.6 5.0V -0.1 4.0V VDD (µA)SHDN000...345 V32..D07DVV n Error (%) --00--..0021..5532 54532.....50007VVVVV I ai -0.35 0.2 G -0.4 0.1 -0.45 0 -0.5 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) Ambient Temperature (ºC) FIGURE 2-18: Hardware Shutdown Current FIGURE 2-21: Gain Error vs. Temperature vs. Temperature and V . and V . DD DD 4 5.5V 4 VDD 3.5 5.0V 5.5V 3.5 V) 5.0V A) 3 4.0V d ( 3 µ ol I (SHDN_SW2.52 V32D..07DVV Hi ThreshN 2.52 43..00VV 1.5 VI 1.5 2.7V 1 1 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) Ambient Temperature (ºC) FIGURE 2-19: Software Shutdown Current FIGURE 2-22: V High Threshold vs. IN vs. Temperature and V . Temperature and V . DD DD 0.11 1.6 VDD Offset Error (%)-000000......000000113579 5V5..D50DVV V Low Threshold (V)IN11111.....112345 5543....5000VVVV 4.0V 0.9 3.0V 2.7V -0.03 2.7V 0.8 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) Ambient Temperature (ºC) FIGURE 2-20: Offset Error vs. Temperature FIGURE 2-23: V Low Threshold vs. IN and V . Temperature and V . DD DD  2010 Microchip Technology Inc. DS22244B-page 11

MCP4801/4811/4821 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = 2.048V, Gain = 2, R = 5k, C = 100pF. A DD SS REF L L 2.5 16 2.25 VDD 55..50VV steresis (V) 11..127.5525 545...500VVV (mA)ORTED 111345 V432...D007DVVV y H V_ HINSPI 0.07.515 32..07VV IOUT_HI_S 1112 0.25 0 10 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) Ambient Temperature (ºC) FIGURE 2-24: Input Hysteresis vs. FIGURE 2-27: I High Short vs. OUT Temperature and V . Temperature and V . DD DD 0.035 6.0 4.0V 0.033 V) 0.031 5.0 mit (V-Y)(DD 000...000222579 3.0V (V)OUT 34..00 OuVtRpEuFt = S 4h.0o9rt6eVd to VDD Li 0.023 2.7V V 2.0 V OUT_HI 000...000112791 VDD 1.0 Output Shorted to VSS 0.0 0.015 -40 -20 0 20 40 60 80 100 120 0 2 4 6 8 10 12 14 16 Ambient Temperature (ºC) IOUT (mA) FIGURE 2-25: V High Limit FIGURE 2-28: I vs. V . Gain = 2x. OUT OUT OUT vs.Temperature and V . DD 0.0028 VDD V) 0.0026 )(S 0.0024 5.5V S AV 0.0022 5.0V Y- 0.0020 mit ( 0.0018 4.0V LiW 0.0016 32..07VV OUT_LO 00..00001124 V 0.0010 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) FIGURE 2-26: V Low Limit vs. OUT Temperature and V . DD DS22244B-page 12  2010 Microchip Technology Inc.

MCP4801/4811/4821 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = 2.048V, Gain = 2, R = 5k, C = 100pF. A DD SS REF L L V OUT V OUT SCK LDAC LDAC Time (1µs/div) Time (1µs/div) FIGURE 2-29: V Rise Time. FIGURE 2-32: V Rise Time. OUT OUT V OUT V OUT SCK SCK LDAC LDAC Time (1µs/div) Time (1µs/div) FIGURE 2-30: V Fall Time. FIGURE 2-33: V Rise Time Exit OUT OUT Shutdown. ) B d n ( o VOUT cti e SCK ej R e pl p Ri LDAC Time (1µs/div) Frequency (Hz) FIGURE 2-31: V Rise Time. FIGURE 2-34: PSRR vs. Frequency. OUT  2010 Microchip Technology Inc. DS22244B-page 13

MCP4801/4811/4821 NOTES: DS22244B-page 14  2010 Microchip Technology Inc.

MCP4801/4811/4821 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table3-1. TABLE 3-1: PIN FUNCTION TABLE FOR MCP4801/4811/4821 MCP4801/4811/4821 Symbol Description MSOP, PDIP, DFN SOIC, DFN 1 1 V Supply Voltage Input (2.7V to 5.5V) DD 2 2 CS Chip Select Input 3 3 SCK Serial Clock Input 4 4 SDI Serial Data Input 5 5 LDAC DAC Output Synchronization Input. This pin is used to transfer the input register (DAC settings) to the output register (V ) OUT 6 6 SHDN Hardware Shutdown Input 7 7 V Ground reference point for all circuitry on the device SS 8 8 V DAC Analog Output OUT — 9 EP Exposed thermal pad. This pad must be connected to V in application SS 3.1 Supply Voltage Pins (V V ) 3.4 Serial Data Input (SDI) DD, SS V is the positive supply voltage input pin. The input SDI is the SPI compatible serial data input pin. DD supply voltage is relative to V and can range from SS 2.7V to 5.5V. The power supply at the VDD pin should 3.5 Latch DAC Input (LDAC) be as clean as possible for good DAC performance. Using an appropriate bypass capacitor of about 0.1µF LDAC (latch DAC synchronization input) pin is used to (ceramic) to ground is recommended. An additional transfer the input latch register to the DAC register (out- 10µF capacitor (tantalum) in parallel is also recom- put latches, VOUT). When this pin is low, VOUT is mended to further attenuate high-frequency noise updated with input register content. This pin can be tied present in application boards. to low (VSS) if the VOUT update is desired at the rising edge of the CS pin. This pin can be driven by an exter- V is the analog ground pin and the current return SS nal control device such as an MCU I/O pin. path of the device. The user must connect the V pin SS to a ground plane through a low-impedance 3.6 Analog Output (V ) connection. If an analog ground path is available in the OUT application Printed Circuit Board (PCB), it is highly V is the DAC analog output pin. The DAC output OUT recommended that the VSS pin be tied to the analog has an output amplifier. The full-scale range of the DAC ground path or isolated within an analog ground plane output is from V toG*V , where G is the gain SS REF of the circuit board. selection option (1x or 2x). The DAC analog output cannot go higher than the supply voltage (V ). DD 3.2 Chip Select (CS) 3.7 Exposed Thermal Pad (EP) CS is the Chip Select input pin, which requires an active low to enable serial clock and data functions. There is an internal electrical connection between the exposed thermal pad (EP) and the V pin. They must SS 3.3 Serial Clock Input (SCK) be connected to the same potential on the PCB. SCK is the SPI compatible serial clock input pin.  2010 Microchip Technology Inc. DS22244B-page 15

MCP4801/4811/4821 NOTES: DS22244B-page 16  2010 Microchip Technology Inc.

MCP4801/4811/4821 4.0 GENERAL OVERVIEW 1LSb is the ideal voltage difference between two successive codes. Table4-1 illustrates the LSb The MCP4801, MCP4811 and MCP4821 are single calculation of each device. channel voltage-output 8-bit, 10-bit and 12-bit DAC devices, respectively. These devices include rail-to-rail TABLE 4-1: LSb OF EACH DEVICE output amplifier, internal voltage reference, shutdown Gain and reset-management circuitry. The devices use an Device Selection LSb Size SPI serial communication interface and operate with a single supply voltage from 2.7V to 5.5V. MCP4801 1x 2.048V/256 = 8 mV (n = 8) 2x 4.096V/256 = 16 mV The DAC input coding of these devices is straight binary. Equation4-1 shows the DAC analog output MCP4811 1x 2.048V/1024 = 2 mV voltage calculation. (n = 10) 2x 4.096V/1024 = 4 mV MCP4821 1x 2.048V/4096 = 0.5 mV EQUATION 4-1: ANALOG OUTPUT (n = 12) 2x 4.096V/4096 = 1 mV VOLTAGE (V ) OUT 4.0.1 INL ACCURACY 2.048VD  V = -------------------------------n----G Integral Non-Linearity (INL) error is the maximum OUT n 2 deviation between an actual code transition point and Where: its corresponding ideal transition point once offset and gain errors have been removed. The two endpoints 2.048V = Internal voltage reference method (from 0x000 to 0xFFF) is used for the D = DAC input code calculation. Figure4-1 shows the details. n G = Gain selection A positive INL error represents transition(s) later than = 2 for <GA> bit = 0 ideal. A negative INL error represents transition(s) ear- lier than ideal. = 1 for <GA> bit = 1 n = DAC Resolution = 8 for MCP4801 INL < 0 = 10 for MCP4811 111 Actual = 12 for MCP4821 110 Transfer Function 101 The ideal output range of each device is: • MCP4801 (n = 8) Digital 100 Input (a) 0.0V to 255/256 * 2.048V when gain setting=1x. Code 011 Ideal Transfer (b) 0.0V to 255/256 * 4.096V when gainsetting=2x. Function • MCP4811 (n = 10) 010 (a) 0.0V to 1023/1024 * 2.048V when gain setting=1x. 001 (b) 0.0V to 1023/1024 * 4.096V when gainsetting=2x. 000 • MCP4821 (n = 12) INL < 0 (a) 0.0V to 4095/4096 * 2.048V when gain setting=1x. (b) 0.0V to 4095/4096 * 4.096V when gain setting=2x. DAC Output FIGURE 4-1: Example for INL Error. Note: See the output swing voltage specification in Section1.0 “Electrical Characteristics”.  2010 Microchip Technology Inc. DS22244B-page 17

MCP4801/4811/4821 4.0.2 DNL ACCURACY 4.1 Circuit Descriptions A Differential Non-Linearity (DNL) error is the measure 4.1.1 OUTPUT AMPLIFIER of the variations in code widths from the ideal code width. A DNL error of zero indicates that every code is The analog DAC output is buffered with a low-power, exactly 1LSb wide. precision CMOS amplifier. This amplifier provides low offset voltage and low noise. The output stage enables the device to operate with output voltages close to the power supply rails. Refer to Section1.0 “Electrical 111 Actual Characteristics” for the analog output voltage range Transfer and load conditions. 110 Function In addition to resistive load-driving capability, the amplifier will also drive high capacitive loads without 101 oscillation. The amplifier’s strong output allows V to OUT Digital 100 be used as a programmable voltage reference in a Input Ideal Transfer system. Code 011 Function 4.1.1.1 Programmable Gain Block 010 The rail-to-rail output amplifier has two configurable 001 gain options: a gain of 1x (<GA> = 1) or a gain of 2x Wide Code, >1LSb (<GA> = 0). The default setting is a gain of 2x. This 000 results in an ideal full-scale output of 0.000V to 4.096V Narrow Code, <1LSb due to the internal reference (V = 2.048V). REF DAC Output 4.1.2 VOLTAGE REFERENCE FIGURE 4-2: Example for DNL Error. The MCP4801/4811/4821 devices utilize internal 2.048V voltage reference. The voltage reference has a 4.0.3 OFFSET ERROR low temperature coefficient and low noise characteristics. Refer to Section1.0 “Electrical Char- Offset error is the deviation from zero voltage output acteristics” for the voltage reference specifications. when the digital input code is zero. 4.0.4 GAIN ERROR Gain error is the deviation from the ideal output, V –1LSb, excluding the effects of offset error. REF DS22244B-page 18  2010 Microchip Technology Inc.

MCP4801/4811/4821 4.1.3 POWER-ON RESET CIRCUIT 4.1.4 SHUTDOWN MODE The internal Power-on Reset (POR) circuit monitors the The user can shut down the device using a software power supply voltage (VDD) during the device command (<SHDN> = 0) or SHDN pin. During operation. The circuit also ensures that the DAC shutdown mode, most of the internal circuits, including powers up with high output impedance (<SHDN> = 0, the output amplifier, are turned off for power savings. typically 500k. The devices will continue to have a The internal reference is not affected by the shutdown high-impedance output until a valid write command is command. The serial interface also remains active, received, and the LDAC pin meets the input low allowing a write command to bring the device out of threshold. Shutdown mode. There will be no analog output at the V pin, which is internally switched to a known resis- If the power supply voltage is less than the POR OUT tive load (500ktypical. Figure4-4 shows the analog threshold (V = 2.0V, typical), the DAC will be held POR output stage during Shutdown mode. in the Reset state. It will remain in that state until V >V and a subsequent write command is The condition of the Power-on Reset circuit during DD POR received. Shutdown is as follows: Figure4-3 shows a typical power supply transient a) Turned off if shutdown occurred from the SHDN pulse and the duration required to cause a reset to pin occur, as well as the relationship between the duration b) Remains turned on if the shutdown occurred and trip voltage. A 0.1µF decoupling capacitor, through software mounted as close as possible to the V pin, can DD The device will remain in Shutdown mode until the provide additional transient immunity. <SHDN> bit = 1 is latched into the device or SHDN pin is changed to logic high. When the device is changed from Shutdown to Active mode, the output settling time 5V takes <10µs, but greater than the standard active s e mode settling time (4.5µs). ag VPOR t ol VDD - VPOR V V y OP OUT pl Transient Duration Amp p u S Power-Down Time Control Circuit 10 s) TA = +25°C µ Resistive n ( 8 Load 500k o rati 6 Resistive String DAC u D nt 4 FIGURE 4-4: Output Stage for Shutdown e Transients above the curve si will cause a reset Mode. n 2 a Tr Transients below the curve will NOT cause a reset 0 1 2 3 4 5 V - V (V) DD POR FIGURE 4-3: Typical Transient Response.  2010 Microchip Technology Inc. DS22244B-page 19

MCP4801/4811/4821 NOTES: DS22244B-page 20  2010 Microchip Technology Inc.

MCP4801/4811/4821 5.0 SERIAL INTERFACE 5.2 Write Command The write command is initiated by driving the CS pin 5.1 Overview low, followed by clocking the four Configuration bits and the 12data bits into the SDI pin on the rising edge of The MCP4801/4811/4821 devices are designed to SCK. The CS pin is then raised, causing the data to be interface directly with the Serial Peripheral Interface latched into the DAC’s input register. (SPI) port, available on many microcontrollers, and supports Mode 0,0 and Mode 1,1. Commands and data The MCP4801/4811/4821 devices utilize a double- are sent to the device via the SDI pin, with data being buffered latch structure to allow the DAC output to be clocked-in on the rising edge of SCK. The synchronized with the LDAC pin, if desired. communications are unidirectional and, thus, data By bringing down the LDAC pin to a low state, the cannot be read out of the MCP4801/4811/4821 content stored in the DAC’s input register is transferred devices. The CS pin must be held low for the duration into the DAC’s output register (V ), and V is OUT OUT of a write command. The write command consists of updated. 16bits and is used to configure the DAC’s control and data latches. Register5-1 to Register5-3 detail the All writes to the MCP4801/4811/4821 devices are input register that is used to configure and load the 16-bit words. Any clocks after the first 16th clock will be ignored. The Most Significant four bits are DAC register for each device. Figure5-1 to Figure5-3 show the write command for each device. Configuration bits. The remaining 12bits are data bits. No data can be transferred into the device with CS Refer to Figure1-1 and the SPI Timing Specifications high. The data transfer will only occur if 16 clocks have Table for detailed input and output timing specifications been transferred into the device. If the rising edge of for both Mode 0,0 and Mode 1,1 operation. CS occurs prior, shifting of data into the input register will be aborted.  2010 Microchip Technology Inc. DS22244B-page 21

MCP4801/4811/4821 REGISTER 5-1: WRITE COMMAND REGISTER FOR MCP4821 (12-BIT DAC) W-x W-x W-x W-0 W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x 0 — GA SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 bit 15 bit 0 REGISTER 5-2: WRITE COMMAND REGISTER FOR MCP4811 (10-BIT DAC) W-x W-x W-x W-0 W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x 0 — GA SHDN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 x x bit 15 bit 0 REGISTER 5-3: WRITE COMMAND REGISTER FOR MCP4801 (8-BIT DAC) W-x W-x W-x W-0 W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x 0 — GA SHDN D7 D6 D5 D4 D3 D2 D1 D0 x x x x bit 15 bit 0 Where: bit 15 (1) 0 = Write to DAC register 1 = Ignore this command bit 14 — Don’t Care bit 13 GA: Output Gain Selection bit 1 = 1x (VOUT = VREF * D/4096) 0 = 2x (VOUT = 2 * VREF * D/4096), where internal VREF = 2.048V. bit 12 SHDN: Output Shutdown Control bit 1 = Active mode operation. VOUT is available.  0 = Shutdown the device. Analog output is not available. VOUT pin is connected to 500ktypical) bit 11-0 D11:D0: DAC Input Data bits. Bit x is ignored. Legend R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown Note 1: This bit must be ‘0’. The device ignores the write command if this MSB bit is not ‘0’. DS22244B-page 22  2010 Microchip Technology Inc.

MCP4801/4811/4821 CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (Mode 1,1) SCK (Mode 0,0) config bits 12 data bits SDI 0 — GA SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LDAC V OUT FIGURE 5-1: Write Command for MCP4821 (12-bit DAC). CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (Mode 1,1) SCK (Mode 0,0) config bits 12 data bits SDI 0 — GA SHDN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X LDAC V OUT Note: X = “don’t care” bits. FIGURE 5-2: Write Command for MCP4811 (10-bit DAC). CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (Mode 1,1) SCK (Mode 0,0) config bits 12 data bits SDI 0 — GA SHDN D7 D6 D5 D4 D3 D2 D1 D0 X X X X LDAC V OUT Note: X = “don’t care” bits. FIGURE 5-3: Write Command for MCP4801 (8-bit DAC).  2010 Microchip Technology Inc. DS22244B-page 23

MCP4801/4811/4821 NOTES: DS22244B-page 24  2010 Microchip Technology Inc.

MCP4801/4811/4821 6.0 TYPICAL APPLICATIONS 6.3 Output Noise Considerations The MCP4801/4811/4821 family of devices are general The voltage noise density (in µV/Hz) is illustrated in purpose, single channel voltage output DACs for Figure2-13. This noise appears at VOUT, and is various applications where a precision operation with primarily a result of the internal reference voltage. low-power and internal voltage reference is required. Its1/fcorner (fCORNER) is approximately 400Hz. Applications generally suited for the devices are: Figure2-14 illustrates the voltage noise (in mVRMS or mV ). A small bypass capacitor on V is an • Set Point or Offset Trimming P-P OUT effective method to produce a single-pole Low-Pass • Sensor Calibration Filter (LPF) that will reduce this noise. For instance, a • Precision Selectable Voltage Reference bypass capacitor sized to produce a 1kHz LPF would • Portable Instrumentation (Battery-Powered) result in an E of about 100 µV . This would be NREF RMS • Calibration of Optical Communication Devices necessary when trying to achieve the low DNL error performance (at G=1x) that the MCP4801/4811/4821 6.1 Digital Interface devices are capable of. The tested range for stability is.001µF through 4.7µF. The MCP4801/4811/4821 devices utilize a 3-wire synchronous serial protocol to transfer the DAC’s setup V V DD DD and input codes from the digital devices. The serial protocol can be interfaced to SPI or Microwire C1 = 10µF peripherals which are common on many microcon- C2 = 0.1µF C1 C2 C1 C2 troller units (MCUs), including Microchip’s PIC® MCUs and dsPIC® DSCs. VDD V OUT CS In addition to the three serial connections (CS, SCK 1µF 1 and SDI), the LDAC signal synchronizes the DAC C1 x SDI output with LDAC pin event. By bringing the LDAC pin C2 48 P r down “low”, the DAC input codes and settings in the MC olle DAC input register are latched into the output register, r nt and the DAC analog output is updated. Figure6-1 o c shows an example of the pin connections. Note that the o r LDAC pin can be tied low (VSS) to reduce the required VOUT x1 SDI AVSS SDO Mic connections from 4 to 3 I/O pins. In this case, the DAC 48 SCK ® output can be immediately updated when a valid P C 1p6in chloacsk b tereann srmaiissesdio.n has been received and the CS 1µF MC LDAC PI 6.2 Power Supply Considerations CS0 The typical application will require a bypass capacitor AV V to filter out noise in the power supply traces. The noise SS SS can be induced onto the power supply’s traces from FIGURE 6-1: Typical Connection various events such as digital switching or as a result Diagram. of changes on the DAC’s output. The bypass capacitor helps minimize the effect of these noise sources. 6.4 Layout Considerations Figure6-1 illustrates an appropriate bypass strategy. In this example, two bypass capacitors are used in paral- Inductively-coupled AC transients and digital switching lel: (a) 0.1µF (ceramic) and (b)10µF (tantalum). These noises can degrade the output signal integrity, and capacitors should be placed as close to the device potentially reduce the device performance. Careful power pin (V ) as possible (within 4mm). DD board layout will minimize these effects and increase The power source supplying these devices should be the Signal-to-Noise Ratio (SNR). Bench testing has as clean as possible. If the application circuit has shown that a multi-layer board utilizing a separate digital and analog power supplies, V and low-inductance ground plane, isolated inputs and DD V of the device should reside on the analog plane. isolated outputs with proper decoupling, is critical for SS the best performance. Particularly harsh environments may require shielding of critical signals. Breadboards and wire-wrapped boards are not recommended if low noise is desired.  2010 Microchip Technology Inc. DS22244B-page 25

MCP4801/4811/4821 6.5 Single-Supply Operation 6.5.1.1 Decreasing Output Step Size The MCP4801/4811/4821 devices are rail-to-rail If the application is calibrating the bias voltage of a voltage output DAC devices designed to operate with a diode or transistor, a bias voltage range of 0.8V may be V range of 2.7V to 5.5V. Its output amplifier is robust desired with about 200µV resolution per step. Two DD enough to drive small-signal loads directly. Therefore, it common methods to achieve a 0.8V range are to either does not require any external output buffer for most reduce VREF to 0.82V (using the MCP49XX family applications. device that uses external reference) or use a voltage divider on the DAC’s output. 6.5.1 DC SET POINT OR CALIBRATION Using a V is an option if the V is available with REF REF A common application for the devices is a digitally- the desired output voltage range. However, controlled set point and/or calibration of variable occasionally, when using a low-voltage VREF, the noise parameters, such as sensor offset or slope. For floor causes SNR error that is intolerable. Using a example, the MCP4821 and MCP4822 provide voltage divider method is another option and provides 4096output steps. If G=1x is selected, the internal some advantages when VREF needs to be very low or 2.048V V would produce 500µV of resolution. If when the desired output voltage is not available. In this REF G=2x is selected, the internal 2.048 VREF would case, a larger value VREF is used while two resistors produce 1mV of resolution. scale the output range down to the precise desired level. Example6-1 illustrates this concept. Note that the bypass capacitor on the output of the voltage divider plays a critical function in attenuating the output noise of the DAC and the induced noise from the environment. EXAMPLE 6-1: EXAMPLE CIRCUIT OF SET POINT OR THRESHOLD CALIBRATION V DD (a) Single Output DAC: MCP4801 MCP4811 MCP4821 V + CC (b) Dual Output DAC: RSENSE V DD MCP4802 MCP4812 Comparator MCP4822 VOUT R1 VTRIP DAC V – R 0.1µF CC 2 SPI 3-wire D V = 2.048G-----n- G = Gain selection (1x or 2x) OUT N 2 D = Digital value of DAC (0-255) for MCP4801/MCP4802 n = Digital value of DAC (0-1023) for MCP4811/MCP4812  R2  = Digital value of DAC (0-4095) for MCP4821/MCP4822 V = V -------------------- trip OUTR1+R2 N = DAC bit resolution DS22244B-page 26  2010 Microchip Technology Inc.

MCP4801/4811/4821 6.5.1.2 Building a “Window” DAC If the threshold is not near V , 2V or V , then REF REF SS creating a “window” around the threshold has several When calibrating a set point or threshold of a sensor, advantages. One simple method to create this typically only a small portion of the DAC output range is “window” is to use a voltage divider network with a pull- utilized. If the LSb size is adequate enough to meet the up and pull-down resistor. Example6-2 and application’s accuracy needs, the unused range is Example6-4 illustrate this concept. sacrificed without consequences. If greater accuracy is needed, then the output range will need to be reduced to increase the resolution around the desired threshold. EXAMPLE 6-2: SINGLE-SUPPLY “WINDOW” DAC (a) Single Output DAC: MCP4801 MCP4811 MCP4821 (b) Dual Output DAC: MCP4802 MCP4812 V MCP4822 VCC+ RSENSE CC+ V DD R 3 Comparator R VOUT 1 VTRIP DAC V R 0.1µF CC- 2 SPI 3-wire V CC- D V = 2.048G-----n- OUT N 2 G = Gain selection (1x or 2x) D = Digital value of DAC (0-255) for MCP4801/MCP4802 n = Digital value of DAC (0-1023) for MCP4811/MCP4812 = Digital value of DAC (0-4095) for MCP4821/MCP4822 N = DAC bit resolution R R R = --------2------3----- R1 23 R +R Thevenin 2 3 VOUT VO Equivalent V R +V R  CC+ 2 CC- 3 V = ------------------------------------------------------ R 23 R +R 23 2 3 V R +V R OUT 23 23 1 Vtrip = ------------R--------+-----R-------------------- V23 1 23  2010 Microchip Technology Inc. DS22244B-page 27

MCP4801/4811/4821 6.6 Bipolar Operation Example6-3 illustrates a simple bipolar voltage source configuration. R and R allow the gain to be selected, 1 2 Bipolar operation is achievable using the while R and R shift the DAC’s output to a selected 3 4 MCP4801/4811/4821 family of devices by utilizing an offset. Note that R4 can be tied to V , instead of V , DD SS external operational amplifier (op amp). This if a higher offset is desired. Also note that a pull-up to configuration is desirable due to the wide variety and V could be used instead of R , or in addition to R , if DD 4 4 availability of op amps. This allows a general purpose a higher offset is desired. DAC, with its cost and availability advantages, to meet almost any desired output voltage range, power and noise performance. EXAMPLE 6-3: DIGITALLY-CONTROLLED BIPOLAR VOLTAGE SOURCE R 2 (a) Single Output DAC: V MCP4801 DD V MCP4811 DD V + R CC 1 MCP4821 (b) Dual Output DAC: VOUT R3 VO DAC MCP4802 V + IN V – CC MCP4812 R 0.1µF 4 MCP4822 SPI 3-wire D n V = 2.048G------ OUT 2N G = Gain selection (1x or 2x) D = Digital value of DAC (0-255) for MCP4801/MCP4802 V R n OUT 4 V = -------------------- = Digital value of DAC (0-1023) for MCP4811/MCP4812 IN+ R +R 3 4 = Digital value of DAC (0-4095) for MCP4821/MCP4822 R R N = DAC bit resolution  2  2 V = V 1+------ –V ------ O IN+ R  DDR  1 1 6.6.1 DESIGN EXAMPLE: DESIGN A The equation can be simplified to: BIPOLAR DAC USING EXAMPLE6-3 WITH 12-BIT MCP4821 OR –----R----2- = --–----2---.-0---5---- R----2-- = 1--- MCP4822 R 4.096V R 2 1 1 An output step magnitude of 1mV, with an output range If R = 20k and R = 10k, the gain will be 0.5. of ±2.05V, is desired for a particular application. 1 2 Step 1: Calculate the range: +2.05V – (-2.05V) = 4.1V. Step 4: Next solve for R and R by setting the DAC to Step 2: Calculate the resolution needed: 3 4 4096, knowing that the output needs to be +2.05V. 4.1V/1mV = 4100 Since 212 = 4096, 12-bit resolution is desired. R4 2.05V+0.54.096V 2 ------------------------ = ------------------------------------------------------- = --- Step 3: The amplifier gain (R /R ), multiplied by full- R +R  1.54.096V 3 2 1 3 4 scale V (4.096V), must be equal to the desired OUT minimum output to achieve bipolar operation. If R4 = 20k, then R3 = 10k Since any gain can be realized by choosing resistor values (R +R ), the V value must be 1 2 REF selected first. If a V of 4.096V is used (G=2), REF solve for the amplifier’s gain by setting the DAC to 0, knowing that the output needs to be -2.05V. DS22244B-page 28  2010 Microchip Technology Inc.

MCP4801/4811/4821 6.7 Selectable Gain and Offset Bipolar This circuit is typically used for linearizing a sensor Voltage Output whose slope and offset varies. The equation to design a bipolar “window” DAC would In some applications, precision digital control of the be utilized if R , R and R are populated. output range is desirable. Example6-4 illustrates how 3 4 5 to use the MCP4801/4811/4821 family of devices to achieve this in a bipolar or single-supply application. EXAMPLE 6-4: BIPOLAR VOLTAGE SOURCE WITH SELECTABLE GAIN AND OFFSET R 2 V DD V + CC R V 1 OUTA DAC A (DAC for Gain Adjust) V + A CC VDD VO R 5 R V 3 V + OUTB IN DAC B (DAC for Offset Adjust) B SPI R 4 0.1µF V – 3 CC Dn VCC– V = 2.048G ------ OUTA A N 2 D G = Gain selection (1x or 2x) V = 2.048G -----n- OUTB B N N = DAC bit resolution 2 D = Digital value of DAC (0-255) for MCP4801 n VOUTBR4+VCC-R3 = Digital value of DAC (0-1023) for MCP4811 V = ------------------------------------------------- IN+ R3+R4 = Digital value of DAC (0-4095) for MCP4821 R R V = V 1+----2-- –V ----2-- O IN+ R  OUTAR  1 1 Offset Adjust Gain Adjust Bipolar “Window” DAC using R and R 4 5 Thevenin V R +V R R R CC+ 4 CC- 5 4 5 V = --------------------------------------------- R = ------------------- Equivalent 45 R +R 45 R +R 4 5 4 5 V R +V R R R OUTB 45 45 3  2  2 V = ------------------------------------------------ V = V 1+------ –V ------ IN+ R +R O IN+ R  OUTAR  3 45 1 1 Offset Adjust Gain Adjust  2010 Microchip Technology Inc. DS22244B-page 29

MCP4801/4811/4821 6.8 Designing a Double-Precision Step 1: Calculate the resolution needed: DAC 4.1V/1µV=4.1x106. Since 222=4.2x106, 22-bit resolution is desired. Since Example6-5 illustrates how to design a single-supply DNL=±0.75LSb, this design can be done with voltage output capable of up to 24-bit resolution by the 12-bit MCP4821 or MCP4822 DAC devices. using 12-bit DACs. This design is simply a voltage divider with a buffered output. Step 2: Since DACB’s VOUTB has a resolution of 1mV, its output only needs to be “pulled” 1/1000 to meet As an example, if an application similar to the one the 1µV target. Dividing V by 1000 would developed in Section6.6.1 “Design Example: OUTA allow the application to compensate for DAC ’s Design a Bipolar DAC Using Example6-3 with 12- B DNL error. bit MCP4821 or MCP4822” required a resolution of 1µV instead of 1mV, and a range of 0V to 4.1V, then Step 3: If R2 is 100, then R1 needs to be 100k. 12-bit resolution would not be adequate. Step 4: The resulting transfer function is shown in the equation of Example6-5. EXAMPLE 6-5: SIMPLE, DOUBLE-PRECISION DAC WITH MCP4821 V DD V + CC V for Fine Adjustment DAC OUTA A R1 VO R >> R 1 2 V DD V – CC R 0.1µF V for Fine Adjustment 2 DAC OUTB B SPI 3-wire D A VOUTA = 2.048GA----1--2- Gx = Gain selection (1x or 2x) 2 DB Dn = Digital value of DAC (0-4096) V = 2.048G ------- OUTB B 12 2 V R +V R OUTA 2 OUTB 1 V = ------------------------------------------------------ O R +R 1 2 DS22244B-page 30  2010 Microchip Technology Inc.

MCP4801/4811/4821 6.9 Building Programmable Current However, this also reduces the resolution that the Source current can be controlled with. The voltage divider, or “window”, DAC configuration would allow the range to Example6-6 shows an example of building a be reduced, thus increasing resolution around the programmable current source using a voltage follower. range of interest. When working with very small sensor The current sensor (sensor resistor) is used to convert voltages, plan on eliminating the amplifier’s offset error the DAC voltage output into a digitally-selectable by storing the DAC’s setting under known sensor current source. conditions. Adding the resistor network from Example6-2 would be advantageous in this application. The smaller R is, the less power dissipated across it. SENSE EXAMPLE 6-6: DIGITALLY-CONTROLLED CURRENT SOURCE V or V DD REF (a) Single Output DAC: V DD Load MCP4801 V + CC MCP4811 V I OUT L MCP4821 DAC (b) Dual Output DAC: I b MCP4802 SPI V – CC MCP4812 3-wire MCP4822 R SENSE I L I = ---- G = Gain selection (1x or 2x) b  D = Digital value of DAC (0-255) for MCP4801/MCP4802 n VOUT  = Digital value of DAC (0-1023) for MCP4811/MCP4812 I = ---------------------------- L R +1 = Digital value of DAC (0-4095) for MCP4821/MCP4822 sense where Common-Emitter Current Gain N = DAC bit resolution  2010 Microchip Technology Inc. DS22244B-page 31

MCP4801/4811/4821 NOTES: DS22244B-page 32  2010 Microchip Technology Inc.

MCP4801/4811/4821 7.0 DEVELOPMENT SUPPORT 7.1 Evaluation & Demonstration Boards The Mixed Signal PICtail™ Demo Board supports the MCP4801/4811/4821 family of devices. Refer to www.microchip.com for further information on this product’s capabilities and availability.  2010 Microchip Technology Inc. DS22244B-page 33

MCP4801/4811/4821 NOTES: DS22244B-page 34  2010 Microchip Technology Inc.

MCP4801/4811/4821 8.0 PACKAGING INFORMATION 8.1 Package Marking Information 8-Lead DFN (2x3) Example: XXX AHS YWW 010 NN 25 8-Lead MSOP Example: XXXXXX 4801E YWWNNN 010256 8-Lead PDIP (300 mil) Example: XXXXXXXX MCP4821 XXXXXNNN E/Pe^3256 YYWW 1010 8-Lead SOIC (150 mil) Example: XXXXXXXX MCP4811E XXXXYYWW SN^e^31010 NNN 256 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010 Microchip Technology Inc. DS22244B-page 35

MCP4801/4811/4821 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)(cid:17)(cid:10)(cid:6)(cid:12)(cid:18)(cid:8)(cid:19)(cid:20)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)(cid:21)(cid:6)(cid:22)(cid:5)(cid:8)(cid:23)(cid:24)(cid:25)(cid:26)(cid:8)(cid:27)(cid:8)(cid:28)(cid:29)(cid:30)(cid:29)(cid:31) !(cid:8)""(cid:8)#(cid:20)(cid:7)$(cid:8)%(cid:15)(cid:17)(cid:19)& (cid:19)(cid:20)(cid:12)(cid:5)’ 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)133)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&3(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) D e b N N L K E E2 EXPOSEDPAD NOTE1 NOTE1 1 2 2 1 D2 TOPVIEW BOTTOMVIEW A NOTE2 A3 A1 4(cid:24)(cid:18)% (cid:17)(cid:27)55(cid:27)(cid:17),(cid:23),(cid:8)(cid:3) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:14)5(cid:18)&(cid:18)% (cid:17)(cid:27)6 67(cid:17) (cid:17)(cid:7)8 6!&((cid:13)(cid:20)(cid:14)(cid:21)$(cid:14)(cid:30)(cid:18)(cid:24) 6 9 (cid:30)(cid:18)%(cid:19)(cid:22) (cid:13) (cid:4)(cid:28).(cid:4)(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14):(cid:13)(cid:18)(cid:12)(cid:22)% (cid:7) (cid:4)(cid:28)9(cid:4) (cid:4)(cid:28)(cid:6)(cid:4) (cid:29)(cid:28)(cid:4)(cid:4) (cid:3)%(cid:11)(cid:24)"(cid:21)$$(cid:14) (cid:7)(cid:29) (cid:4)(cid:28)(cid:4)(cid:4) (cid:4)(cid:28)(cid:4)(cid:15) (cid:4)(cid:28)(cid:4). 0(cid:21)(cid:24)%(cid:11)(cid:19)%(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)*(cid:24)(cid:13) (cid:7)+ (cid:4)(cid:28)(cid:15)(cid:4)(cid:14)(cid:8),2 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)5(cid:13)(cid:24)(cid:12)%(cid:22) (cid:2) (cid:15)(cid:28)(cid:4)(cid:4)(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14);(cid:18)"%(cid:22) , +(cid:28)(cid:4)(cid:4)(cid:14)/(cid:3)0 ,#(cid:10)(cid:21) (cid:13)"(cid:14)(cid:30)(cid:11)"(cid:14)5(cid:13)(cid:24)(cid:12)%(cid:22) (cid:2)(cid:15) (cid:29)(cid:28)+(cid:4) < (cid:29)(cid:28).. ,#(cid:10)(cid:21) (cid:13)"(cid:14)(cid:30)(cid:11)"(cid:14);(cid:18)"%(cid:22) ,(cid:15) (cid:29)(cid:28).(cid:4) < (cid:29)(cid:28)(cid:16). 0(cid:21)(cid:24)%(cid:11)(cid:19)%(cid:14);(cid:18)"%(cid:22) ( (cid:4)(cid:28)(cid:15)(cid:4) (cid:4)(cid:28)(cid:15). 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MCP4801/4811/4821 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)(cid:17)(cid:10)(cid:6)(cid:12)(cid:18)(cid:8)(cid:19)(cid:20)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)(cid:21)(cid:6)(cid:22)(cid:5)(cid:8)(cid:23)(cid:24)(cid:25)(cid:26)(cid:8)(cid:27)(cid:8)(cid:28)(cid:29)(cid:30)(cid:29)(cid:31) !(cid:8)""(cid:8)#(cid:20)(cid:7)$(cid:8)%(cid:15)(cid:17)(cid:19)& (cid:19)(cid:20)(cid:12)(cid:5)’ 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)133)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&3(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)  2010 Microchip Technology Inc. DS22244B-page 37

MCP4801/4811/4821 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:24)(cid:13)(cid:14)((cid:20)(cid:8))"(cid:6)(cid:10)(cid:10)(cid:8)*(cid:16)(cid:12)(cid:10)(cid:13)+(cid:5)(cid:8)(cid:9)(cid:6)(cid:14)(cid:21)(cid:6)(cid:22)(cid:5)(cid:8)(cid:23)(cid:24))(cid:26)(cid:8)%(cid:24))*(cid:9)& (cid:19)(cid:20)(cid:12)(cid:5)’ 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)133)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&3(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) D N E E1 NOTE1 1 2 e b c φ A A2 A1 L1 L 4(cid:24)(cid:18)% (cid:17)(cid:27)55(cid:27)(cid:17),(cid:23),(cid:8)(cid:3) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:14)5(cid:18)&(cid:18)% (cid:17)(cid:27)6 67(cid:17) (cid:17)(cid:7)8 6!&((cid:13)(cid:20)(cid:14)(cid:21)$(cid:14)(cid:30)(cid:18)(cid:24) 6 9 (cid:30)(cid:18)%(cid:19)(cid:22) (cid:13) (cid:4)(cid:28)>.(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14):(cid:13)(cid:18)(cid:12)(cid:22)% (cid:7) < < (cid:29)(cid:28)(cid:29)(cid:4) (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)*(cid:24)(cid:13) (cid:7)(cid:15) (cid:4)(cid:28)(cid:16). (cid:4)(cid:28)9. (cid:4)(cid:28)(cid:6). (cid:3)%(cid:11)(cid:24)"(cid:21)$$(cid:14) (cid:7)(cid:29) (cid:4)(cid:28)(cid:4)(cid:4) < (cid:4)(cid:28)(cid:29). 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14);(cid:18)"%(cid:22) , (cid:5)(cid:28)(cid:6)(cid:4)(cid:14)/(cid:3)0 (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14);(cid:18)"%(cid:22) ,(cid:29) +(cid:28)(cid:4)(cid:4)(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)5(cid:13)(cid:24)(cid:12)%(cid:22) (cid:2) +(cid:28)(cid:4)(cid:4)(cid:14)/(cid:3)0 2(cid:21)(cid:21)%(cid:14)5(cid:13)(cid:24)(cid:12)%(cid:22) 5 (cid:4)(cid:28)(cid:5)(cid:4) (cid:4)(cid:28)>(cid:4) (cid:4)(cid:28)9(cid:4) 2(cid:21)(cid:21)%(cid:10)(cid:20)(cid:18)(cid:24)% 5(cid:29) (cid:4)(cid:28)(cid:6).(cid:14)(cid:8),2 2(cid:21)(cid:21)%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13) (cid:3) (cid:4)? < 9? 5(cid:13)(cid:11)"(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)*(cid:24)(cid:13) (cid:19) (cid:4)(cid:28)(cid:4)9 < (cid:4)(cid:28)(cid:15)+ 5(cid:13)(cid:11)"(cid:14);(cid:18)"%(cid:22) ( (cid:4)(cid:28)(cid:15)(cid:15) < (cid:4)(cid:28)(cid:5)(cid:4) (cid:19)(cid:20)(cid:12)(cid:5)(cid:11)’ (cid:29)(cid:28) (cid:30)(cid:18)(cid:24)(cid:14)(cid:29)(cid:14)(cid:31)(cid:18) !(cid:11)(cid:25)(cid:14)(cid:18)(cid:24)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:20)(cid:13)(cid:14)&(cid:11)(cid:26)(cid:14)(cid:31)(cid:11)(cid:20)(cid:26)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14))(cid:18)%(cid:22)(cid:18)(cid:24)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:22)(cid:11)%(cid:19)(cid:22)(cid:13)"(cid:14)(cid:11)(cid:20)(cid:13)(cid:11)(cid:28) (cid:15)(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24) (cid:14)(cid:2)(cid:14)(cid:11)(cid:24)"(cid:14),(cid:29)(cid:14)"(cid:21)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:18)(cid:24)(cid:19)(cid:25)!"(cid:13)(cid:14)&(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:28)(cid:14)(cid:17)(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:14) (cid:22)(cid:11)(cid:25)(cid:25)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:13)#(cid:19)(cid:13)(cid:13)"(cid:14)(cid:4)(cid:28)(cid:29).(cid:14)&&(cid:14)(cid:10)(cid:13)(cid:20)(cid:14) (cid:18)"(cid:13)(cid:28) +(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:18)(cid:24)(cid:12)(cid:14)(cid:11)(cid:24)"(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:18)(cid:24)(cid:12)(cid:14)(cid:10)(cid:13)(cid:20)(cid:14)(cid:7)(cid:3)(cid:17),(cid:14)-(cid:29)(cid:5)(cid:28).(cid:17)(cid:28) /(cid:3)01 /(cid:11) (cid:18)(cid:19)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:28)(cid:14)(cid:23)(cid:22)(cid:13)(cid:21)(cid:20)(cid:13)%(cid:18)(cid:19)(cid:11)(cid:25)(cid:25)(cid:26)(cid:14)(cid:13)#(cid:11)(cid:19)%(cid:14)(cid:31)(cid:11)(cid:25)!(cid:13)(cid:14) (cid:22)(cid:21))(cid:24)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13) (cid:28) (cid:8),21 (cid:8)(cid:13)$(cid:13)(cid:20)(cid:13)(cid:24)(cid:19)(cid:13)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)’(cid:14)! !(cid:11)(cid:25)(cid:25)(cid:26)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13)’(cid:14)$(cid:21)(cid:20)(cid:14)(cid:18)(cid:24)$(cid:21)(cid:20)&(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:10)!(cid:20)(cid:10)(cid:21) (cid:13) (cid:14)(cid:21)(cid:24)(cid:25)(cid:26)(cid:28) (cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:23)(cid:13)(cid:19)(cid:22)(cid:24)(cid:21)(cid:25)(cid:21)(cid:12)(cid:26)(cid:2)(cid:20)(cid:11))(cid:18)(cid:24)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:29)(cid:29)(cid:29)/ DS22244B-page 38  2010 Microchip Technology Inc.

MCP4801/4811/4821 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010 Microchip Technology Inc. DS22244B-page 39

MCP4801/4811/4821 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8),+(cid:3)(cid:4)(cid:13)+(cid:5)(cid:8)(cid:23)(cid:9)(cid:26)(cid:8)(cid:27)(cid:8)(cid:30)(cid:31)(cid:31)(cid:8)"(cid:13)(cid:10)(cid:8)#(cid:20)(cid:7)$(cid:8)%(cid:9)(cid:15),(cid:9)& (cid:19)(cid:20)(cid:12)(cid:5)’ 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)133)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&3(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) N NOTE1 E1 1 2 3 D E A A2 L A1 c e eB b1 b 4(cid:24)(cid:18)% (cid:27)60:,(cid:3) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:14)5(cid:18)&(cid:18)% (cid:17)(cid:27)6 67(cid:17) (cid:17)(cid:7)8 6!&((cid:13)(cid:20)(cid:14)(cid:21)$(cid:14)(cid:30)(cid:18)(cid:24) 6 9 (cid:30)(cid:18)%(cid:19)(cid:22) (cid:13) (cid:28)(cid:29)(cid:4)(cid:4)(cid:14)/(cid:3)0 (cid:23)(cid:21)(cid:10)(cid:14)%(cid:21)(cid:14)(cid:3)(cid:13)(cid:11)%(cid:18)(cid:24)(cid:12)(cid:14)(cid:30)(cid:25)(cid:11)(cid:24)(cid:13) (cid:7) < < (cid:28)(cid:15)(cid:29)(cid:4) (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)*(cid:24)(cid:13) (cid:7)(cid:15) (cid:28)(cid:29)(cid:29). (cid:28)(cid:29)+(cid:4) (cid:28)(cid:29)(cid:6). /(cid:11) (cid:13)(cid:14)%(cid:21)(cid:14)(cid:3)(cid:13)(cid:11)%(cid:18)(cid:24)(cid:12)(cid:14)(cid:30)(cid:25)(cid:11)(cid:24)(cid:13) (cid:7)(cid:29) (cid:28)(cid:4)(cid:29). < < (cid:3)(cid:22)(cid:21)!(cid:25)"(cid:13)(cid:20)(cid:14)%(cid:21)(cid:14)(cid:3)(cid:22)(cid:21)!(cid:25)"(cid:13)(cid:20)(cid:14);(cid:18)"%(cid:22) , (cid:28)(cid:15)(cid:6)(cid:4) (cid:28)+(cid:29)(cid:4) (cid:28)+(cid:15). (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14);(cid:18)"%(cid:22) ,(cid:29) (cid:28)(cid:15)(cid:5)(cid:4) (cid:28)(cid:15).(cid:4) (cid:28)(cid:15)9(cid:4) 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)5(cid:13)(cid:24)(cid:12)%(cid:22) (cid:2) (cid:28)+(cid:5)9 (cid:28)+>. (cid:28)(cid:5)(cid:4)(cid:4) (cid:23)(cid:18)(cid:10)(cid:14)%(cid:21)(cid:14)(cid:3)(cid:13)(cid:11)%(cid:18)(cid:24)(cid:12)(cid:14)(cid:30)(cid:25)(cid:11)(cid:24)(cid:13) 5 (cid:28)(cid:29)(cid:29). (cid:28)(cid:29)+(cid:4) (cid:28)(cid:29).(cid:4) 5(cid:13)(cid:11)"(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)*(cid:24)(cid:13) (cid:19) (cid:28)(cid:4)(cid:4)9 (cid:28)(cid:4)(cid:29)(cid:4) (cid:28)(cid:4)(cid:29). 4(cid:10)(cid:10)(cid:13)(cid:20)(cid:14)5(cid:13)(cid:11)"(cid:14);(cid:18)"%(cid:22) ((cid:29) (cid:28)(cid:4)(cid:5)(cid:4) (cid:28)(cid:4)>(cid:4) (cid:28)(cid:4)(cid:16)(cid:4) 5(cid:21))(cid:13)(cid:20)(cid:14)5(cid:13)(cid:11)"(cid:14);(cid:18)"%(cid:22) ( (cid:28)(cid:4)(cid:29)(cid:5) (cid:28)(cid:4)(cid:29)9 (cid:28)(cid:4)(cid:15)(cid:15) 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)(cid:8)(cid:21))(cid:14)(cid:3)(cid:10)(cid:11)(cid:19)(cid:18)(cid:24)(cid:12)(cid:14)(cid:14)@ (cid:13)/ < < (cid:28)(cid:5)+(cid:4) (cid:19)(cid:20)(cid:12)(cid:5)(cid:11)’ (cid:29)(cid:28) (cid:30)(cid:18)(cid:24)(cid:14)(cid:29)(cid:14)(cid:31)(cid:18) !(cid:11)(cid:25)(cid:14)(cid:18)(cid:24)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:20)(cid:13)(cid:14)&(cid:11)(cid:26)(cid:14)(cid:31)(cid:11)(cid:20)(cid:26)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14))(cid:18)%(cid:22)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:22)(cid:11)%(cid:19)(cid:22)(cid:13)"(cid:14)(cid:11)(cid:20)(cid:13)(cid:11)(cid:28) (cid:15)(cid:28) @(cid:14)(cid:3)(cid:18)(cid:12)(cid:24)(cid:18)$(cid:18)(cid:19)(cid:11)(cid:24)%(cid:14)0(cid:22)(cid:11)(cid:20)(cid:11)(cid:19)%(cid:13)(cid:20)(cid:18) %(cid:18)(cid:19)(cid:28) +(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24) (cid:14)(cid:2)(cid:14)(cid:11)(cid:24)"(cid:14),(cid:29)(cid:14)"(cid:21)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:18)(cid:24)(cid:19)(cid:25)!"(cid:13)(cid:14)&(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:28)(cid:14)(cid:17)(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:14) (cid:22)(cid:11)(cid:25)(cid:25)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:13)#(cid:19)(cid:13)(cid:13)"(cid:14)(cid:28)(cid:4)(cid:29)(cid:4)A(cid:14)(cid:10)(cid:13)(cid:20)(cid:14) (cid:18)"(cid:13)(cid:28) (cid:5)(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:18)(cid:24)(cid:12)(cid:14)(cid:11)(cid:24)"(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:18)(cid:24)(cid:12)(cid:14)(cid:10)(cid:13)(cid:20)(cid:14)(cid:7)(cid:3)(cid:17),(cid:14)-(cid:29)(cid:5)(cid:28).(cid:17)(cid:28) /(cid:3)01(cid:14)/(cid:11) (cid:18)(cid:19)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:28)(cid:14)(cid:23)(cid:22)(cid:13)(cid:21)(cid:20)(cid:13)%(cid:18)(cid:19)(cid:11)(cid:25)(cid:25)(cid:26)(cid:14)(cid:13)#(cid:11)(cid:19)%(cid:14)(cid:31)(cid:11)(cid:25)!(cid:13)(cid:14) (cid:22)(cid:21))(cid:24)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13) (cid:28) (cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:23)(cid:13)(cid:19)(cid:22)(cid:24)(cid:21)(cid:25)(cid:21)(cid:12)(cid:26)(cid:2)(cid:20)(cid:11))(cid:18)(cid:24)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:4)(cid:29)9/ DS22244B-page 40  2010 Microchip Technology Inc.

MCP4801/4811/4821 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8))"(cid:6)(cid:10)(cid:10)(cid:8)*(cid:16)(cid:12)(cid:10)(cid:13)+(cid:5)(cid:8)(cid:23))(cid:19)(cid:26)(cid:8)(cid:27)(cid:8)(cid:19)(cid:6)(((cid:20)-(cid:18)(cid:8)(cid:30) !(cid:31)(cid:8)""(cid:8)#(cid:20)(cid:7)$(cid:8)%)*,(cid:25)& (cid:19)(cid:20)(cid:12)(cid:5)’ 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)133)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&3(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) D e N E E1 NOTE1 1 2 3 α b h h c A A2 φ A1 L L1 β 4(cid:24)(cid:18)% (cid:17)(cid:27)55(cid:27)(cid:17),(cid:23),(cid:8)(cid:3) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:14)5(cid:18)&(cid:18)% (cid:17)(cid:27)6 67(cid:17) (cid:17)(cid:7)8 6!&((cid:13)(cid:20)(cid:14)(cid:21)$(cid:14)(cid:30)(cid:18)(cid:24) 6 9 (cid:30)(cid:18)%(cid:19)(cid:22) (cid:13) (cid:29)(cid:28)(cid:15)(cid:16)(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14):(cid:13)(cid:18)(cid:12)(cid:22)% (cid:7) < < (cid:29)(cid:28)(cid:16). (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)*(cid:24)(cid:13) (cid:7)(cid:15) (cid:29)(cid:28)(cid:15). < < (cid:3)%(cid:11)(cid:24)"(cid:21)$$(cid:14)(cid:14)@ (cid:7)(cid:29) (cid:4)(cid:28)(cid:29)(cid:4) < (cid:4)(cid:28)(cid:15). 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14);(cid:18)"%(cid:22) , >(cid:28)(cid:4)(cid:4)(cid:14)/(cid:3)0 (cid:17)(cid:21)(cid:25)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14);(cid:18)"%(cid:22) ,(cid:29) +(cid:28)(cid:6)(cid:4)(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:20)(cid:11)(cid:25)(cid:25)(cid:14)5(cid:13)(cid:24)(cid:12)%(cid:22) (cid:2) (cid:5)(cid:28)(cid:6)(cid:4)(cid:14)/(cid:3)0 0(cid:22)(cid:11)&$(cid:13)(cid:20)(cid:14)B(cid:21)(cid:10)%(cid:18)(cid:21)(cid:24)(cid:11)(cid:25)C (cid:22) (cid:4)(cid:28)(cid:15). < (cid:4)(cid:28).(cid:4) 2(cid:21)(cid:21)%(cid:14)5(cid:13)(cid:24)(cid:12)%(cid:22) 5 (cid:4)(cid:28)(cid:5)(cid:4) < (cid:29)(cid:28)(cid:15)(cid:16) 2(cid:21)(cid:21)%(cid:10)(cid:20)(cid:18)(cid:24)% 5(cid:29) (cid:29)(cid:28)(cid:4)(cid:5)(cid:14)(cid:8),2 2(cid:21)(cid:21)%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13) (cid:3) (cid:4)? < 9? 5(cid:13)(cid:11)"(cid:14)(cid:23)(cid:22)(cid:18)(cid:19)*(cid:24)(cid:13) (cid:19) (cid:4)(cid:28)(cid:29)(cid:16) < (cid:4)(cid:28)(cid:15). 5(cid:13)(cid:11)"(cid:14);(cid:18)"%(cid:22) ( (cid:4)(cid:28)+(cid:29) < (cid:4)(cid:28).(cid:29) (cid:17)(cid:21)(cid:25)"(cid:14)(cid:2)(cid:20)(cid:11)$%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13)(cid:14)(cid:23)(cid:21)(cid:10) (cid:4) .? < (cid:29).? (cid:17)(cid:21)(cid:25)"(cid:14)(cid:2)(cid:20)(cid:11)$%(cid:14)(cid:7)(cid:24)(cid:12)(cid:25)(cid:13)(cid:14)/(cid:21)%%(cid:21)& (cid:5) .? < (cid:29).? (cid:19)(cid:20)(cid:12)(cid:5)(cid:11)’ (cid:29)(cid:28) (cid:30)(cid:18)(cid:24)(cid:14)(cid:29)(cid:14)(cid:31)(cid:18) !(cid:11)(cid:25)(cid:14)(cid:18)(cid:24)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:20)(cid:13)(cid:14)&(cid:11)(cid:26)(cid:14)(cid:31)(cid:11)(cid:20)(cid:26)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14))(cid:18)%(cid:22)(cid:18)(cid:24)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:22)(cid:11)%(cid:19)(cid:22)(cid:13)"(cid:14)(cid:11)(cid:20)(cid:13)(cid:11)(cid:28) (cid:15)(cid:28) @(cid:14)(cid:3)(cid:18)(cid:12)(cid:24)(cid:18)$(cid:18)(cid:19)(cid:11)(cid:24)%(cid:14)0(cid:22)(cid:11)(cid:20)(cid:11)(cid:19)%(cid:13)(cid:20)(cid:18) %(cid:18)(cid:19)(cid:28) +(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24) (cid:14)(cid:2)(cid:14)(cid:11)(cid:24)"(cid:14),(cid:29)(cid:14)"(cid:21)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:18)(cid:24)(cid:19)(cid:25)!"(cid:13)(cid:14)&(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:28)(cid:14)(cid:17)(cid:21)(cid:25)"(cid:14)$(cid:25)(cid:11) (cid:22)(cid:14)(cid:21)(cid:20)(cid:14)(cid:10)(cid:20)(cid:21)%(cid:20)! (cid:18)(cid:21)(cid:24) (cid:14) (cid:22)(cid:11)(cid:25)(cid:25)(cid:14)(cid:24)(cid:21)%(cid:14)(cid:13)#(cid:19)(cid:13)(cid:13)"(cid:14)(cid:4)(cid:28)(cid:29).(cid:14)&&(cid:14)(cid:10)(cid:13)(cid:20)(cid:14) (cid:18)"(cid:13)(cid:28) (cid:5)(cid:28) (cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:18)(cid:24)(cid:12)(cid:14)(cid:11)(cid:24)"(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:18)(cid:24)(cid:12)(cid:14)(cid:10)(cid:13)(cid:20)(cid:14)(cid:7)(cid:3)(cid:17),(cid:14)-(cid:29)(cid:5)(cid:28).(cid:17)(cid:28) /(cid:3)01 /(cid:11) (cid:18)(cid:19)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)(cid:28)(cid:14)(cid:23)(cid:22)(cid:13)(cid:21)(cid:20)(cid:13)%(cid:18)(cid:19)(cid:11)(cid:25)(cid:25)(cid:26)(cid:14)(cid:13)#(cid:11)(cid:19)%(cid:14)(cid:31)(cid:11)(cid:25)!(cid:13)(cid:14) (cid:22)(cid:21))(cid:24)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13) (cid:28) (cid:8),21 (cid:8)(cid:13)$(cid:13)(cid:20)(cid:13)(cid:24)(cid:19)(cid:13)(cid:14)(cid:2)(cid:18)&(cid:13)(cid:24) (cid:18)(cid:21)(cid:24)’(cid:14)! !(cid:11)(cid:25)(cid:25)(cid:26)(cid:14))(cid:18)%(cid:22)(cid:21)!%(cid:14)%(cid:21)(cid:25)(cid:13)(cid:20)(cid:11)(cid:24)(cid:19)(cid:13)’(cid:14)$(cid:21)(cid:20)(cid:14)(cid:18)(cid:24)$(cid:21)(cid:20)&(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:10)!(cid:20)(cid:10)(cid:21) (cid:13) (cid:14)(cid:21)(cid:24)(cid:25)(cid:26)(cid:28) (cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:23)(cid:13)(cid:19)(cid:22)(cid:24)(cid:21)(cid:25)(cid:21)(cid:12)(cid:26)(cid:2)(cid:20)(cid:11))(cid:18)(cid:24)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:4).(cid:16)/  2010 Microchip Technology Inc. DS22244B-page 41

MCP4801/4811/4821 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8))"(cid:6)(cid:10)(cid:10)(cid:8)*(cid:16)(cid:12)(cid:10)(cid:13)+(cid:5)(cid:8)(cid:23))(cid:19)(cid:26)(cid:8)(cid:27)(cid:8)(cid:19)(cid:6)(((cid:20)-(cid:18)(cid:8)(cid:30) !(cid:31)(cid:8)""(cid:8)#(cid:20)(cid:7)$(cid:8)%)*,(cid:25)& (cid:19)(cid:20)(cid:12)(cid:5)’ 2(cid:21)(cid:20)(cid:14)%(cid:22)(cid:13)(cid:14)&(cid:21) %(cid:14)(cid:19)!(cid:20)(cid:20)(cid:13)(cid:24)%(cid:14)(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:20)(cid:11))(cid:18)(cid:24)(cid:12) ’(cid:14)(cid:10)(cid:25)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:22)(cid:13)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:14)(cid:30)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:19)(cid:18)$(cid:18)(cid:19)(cid:11)%(cid:18)(cid:21)(cid:24)(cid:14)(cid:25)(cid:21)(cid:19)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:22)%%(cid:10)133)))(cid:28)&(cid:18)(cid:19)(cid:20)(cid:21)(cid:19)(cid:22)(cid:18)(cid:10)(cid:28)(cid:19)(cid:21)&3(cid:10)(cid:11)(cid:19)*(cid:11)(cid:12)(cid:18)(cid:24)(cid:12) DS22244B-page 42  2010 Microchip Technology Inc.

MCP4801/4811/4821 APPENDIX A: REVISION HISTORY Revision A (April 2010) • Original Release of this Document. Revision B (April 2010) • Corrected the “Related Products” table on page1.  2010 Microchip Technology Inc. DS22244B-page 43

MCP4801/4811/4821 NOTES: DS22244B-page 44  2010 Microchip Technology Inc.

MCP4801/4811/4821 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Examples: PART NO. X /XX a) MCP4801-E/MC: Extended temperature, Device Temperature Package DFN package Range b) MCP4801T-E/MC: Extended temperature, DFN package, Tape and Reel Device MCP4801: 8-Bit Voltage Output DAC c) MCP4801-E/MS: Extended temperature, MCP4801T: 8-Bit Voltage Output DAC MSOP package. (Tape and Reel, DFN, MSOP and SOIC only) d) MCP4801T-E/MS: Extended temperature, MCP4811: 10-Bit Voltage Output DAC MSOP package, MCP4811T: 10-Bit Voltage Output DAC Tape and Reel. (Tape and Reel, DFN, MSOP and SOIC only) e) MCP4801-E/P: Extended temperature, MCP4821: 12-Bit Voltage Output DAC PDIP package. MCP4821T: 12-Bit Voltage Output DAC f) MCP4801-E/SN: Extended temperature, (Tape and Reel, DFN, MSOP and SOIC only) SOIC package. g) MCP4801T-E/SN: Extended temperature, SOIC package, Temperature Range E = -40C to +125C (Extended) Tape and Reel. a) MCP4811-E/MC: Extended temperature, Package MC = 8-Lead Plastic Dual Flat, No Lead Package - DFN package 2x3x0.9mm Body (DFN) MS = 8-Lead Plastic Micro Small Outline (MSOP) b) MCP4811T-E/MC: Extended temperature, P = 8-Lead Plastic Dual In-Line (PDIP) DFN package, SN = 8-Lead Plastic Small Outline - Narrow, 150mil Tape and Reel (SOIC) c) MCP4811-E/MS: Extended temperature, MSOP package. d) MCP4811T-E/MS: Extended temperature, MSOP package, Tape and Reel. e) MCP4811-E/P: Extended temperature, PDIP package. f) MCP4811-E/SN: Extended temperature, SOIC package. g) MCP4811T-E/SN: Extended temperature, SOIC package, Tape and Reel. a) MCP4821-E/MC: Extended temperature, DFN package b) MCP4821T-E/MC: Extended temperature, DFN package, Tape and Reel c) MCP4821-E/MS: Extended temperature, MSOP package. d) MCP4821T-E/MS: Extended temperature, MSOP package, Tape and Reel. e) MCP4821-E/P: Extended temperature, PDIP package. f) MCP4821-E/SN: Extended temperature, SOIC package. g) MCP4821T-E/SN: Extended temperature, SOIC package, Tape and Reel.  2010 Microchip Technology Inc. DS22244B-page 45

MCP4801/4811/4821 NOTES: DS22244B-page 46  2010 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-124-6 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2010 Microchip Technology Inc. DS22244B-page 47

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