MCP3221 2 Low-Power 12-Bit A/D Converter with I C Interface Features General Description • 12-bit Resolution Microchip’s MCP3221 is a successive approximation • ±1LSB DNL, ±2LSB INL maximum A/D converter (ADC) with a 12-bit resolution. Available in the SOT-23 package, this device provides one sin- • 250µA Max Conversion Current gle-ended input with very low-power consumption. • 5nA Typical Standby Current, 1µA maximum Based on an advanced CMOS technology, the • I2C Compatible Serial Interface MCP3221 provides a low maximum conversion current - 100kHz I2C Standard mode and standby current of 250µA and 1µA, respectively. - 400kHz I2C Fast mode Low-current consumption, combined with the small • Up to 8 Devices on a Single 2-wire Bus SOT-23 package, make this device ideal for battery- • 22.3ksps in I2C Fast mode powered and remote data acquisition applications. • Single-Ended Analog Input Channel Communication to the MCP3221 is performed using a 2-wire, I2C compatible interface. Standard (100kHz) • On-Chip Sample and Hold and Fast (400kHz) I2C modes are available with the • On-Chip Conversion Clock device. An on-chip conversion clock enables • Single-Supply Specified Operation: 2.7V to 5.5V independent timing for the I2C and conversion clocks. • Temperature Range: The device is also addressable, allowing up to eight - Extended: -40°C to +125°C devices on a single 2-wire bus. • Small SOT-23-5 package The MCP3221 runs on a single-supply voltage that operates over a broad range of 2.7V to 5.5V. This Applications device also provides excellent linearity of ±1LSB differential nonlinearity (DNL) and ±2LSB integral • Data Logging nonlinearity (INL), maximum. • Multi-Zone Monitoring • Handheld Portable Applications Package Type • Battery-Powered Test Equipment 5-Pin SOT-23 • Remote or Isolated Data Acquisition V 1 5 SCL DD M C P V 2 3 SS 2 2 1 A 3 4 SDA IN  2002-2017 Microchip Technology Inc. DS20001732E-page 1

MCP3221 Functional Block Diagram V V DD SS DAC Comparator – Sample 12-bit SAR A and + IN Hold Clock Control Logic I2C Interface SCL SDA DS20001732E-page 2  2002-2017 Microchip Technology Inc.

MCP3221 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † V ...........................................................................................................................................................................+7.0V DD Analog input pin w.r.t. V ..................................................................................................................-0.6V to V +0.6V SS DD SDA and SCL pins w.r.t. V ...............................................................................................................-0.6V to V +1.0V SS DD Storage Temperature............................................................................................................................. -65°C to +150°C Ambient Temperature with power applied...............................................................................................-65°C to +125°C Maximum Junction Temperature...........................................................................................................................+150°C ESD protection on all pins (HBM).......................................................................................................................... ≥4kV † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at V = 5.0V, V = GND, R = 2k DD SS PU T = -40°C to +85°C, I2C Fast Mode Timing: f = 400kHz (Note3). A SCL Parameter Sym. Min. Typ. Max. Units Conditions DC Accuracy Resolution — 12 bits Integral Nonlinearity INL — ±0.75 ±2 LSB Differential Nonlinearity DNL — ±0.5 ±1 LSB No missing codes Offset Error — — ±0.75 ±2 LSB Gain Error — — -1 ±3 LSB Dynamic Performance Total Harmonic Distortion THD — -82 — dB V = 0.1V to 4.9V @ 1kHz IN Signal-to-Noise and Distortion SINAD — 72 — dB V = 0.1V to 4.9V @ 1kHz IN Spurious Free Dynamic Range SFDR — 86 — dB V = 0.1V to 4.9V @ 1kHz IN Analog Input Input Voltage Range — V -0.3 — V +0.3 V 2.7V  V  5.5V SS DD DD Leakage Current — -1 — +1 µA SDA/SCL (open-drain output) Data Coding Format — Straight Binary — High-Level Input Voltage V 0.7 V — — V IH DD Low-Level Input Voltage V — — 0.3 V V IL DD Low-Level Output Voltage V — — 0.4 V I = 3mA, R = 1.53k OL OL PU Hysteresis of Schmitt Trigger Inputs V — 0.05V — V f = 400kHz only HYST DD SCL Input Leakage Current I -1 — +1 µA V = 0.1V and 0.9V LI IN DD DD Output Leakage Current I -1 — +1 µA V = 0.1V and LO OUT SS 0.9V DD Note 1: Sample time is the time between conversions once the address byte has been sent to the converter. Refer to Figure5-6. 2: This parameter is periodically sampled and not 100% tested. 3: R = Pull-up resistor on SDA and SCL. PU 4: SDA and SCL = V to V at 400kHz. SS DD 5: t and t are dependent on internal oscillator timing. See Figure5-5 and Figure5-6 in relation to ACQ CONV SCL.  2002-2017 Microchip Technology Inc. DS20001732E-page 3

MCP3221 DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at V = 5.0V, V = GND, R = 2k DD SS PU T = -40°C to +85°C, I2C Fast Mode Timing: f = 400kHz (Note3). A SCL Parameter Sym. Min. Typ. Max. Units Conditions Pin Capacitance C , — — 10 pF T = 25°C, f = 1MHz; IN A (all inputs/outputs) C (Note2) OUT Bus Capacitance C — — 400 pF SDA drive low, 0.4V B Power Requirements Operating Voltage V 2.7 — 5.5 V DD Conversion Current I — 175 250 µA DD Standby Current I — 0.005 1 µA SDA, SCL = V DDS DD Active Bus Current I — — 120 µA Note4 DDA Conversion Rate Conversion Time t — 8.96 — µs Note5 CONV Analog Input Acquisition Time t — 1.12 — µs Note5 ACQ Sample Rate f — — 22.3 ksps f = 400kHz (Note1) SAMP SCL Note 1: Sample time is the time between conversions once the address byte has been sent to the converter. Refer to Figure5-6. 2: This parameter is periodically sampled and not 100% tested. 3: R = Pull-up resistor on SDA and SCL. PU 4: SDA and SCL = V to V at 400kHz. SS DD 5: t and t are dependent on internal oscillator timing. See Figure5-5 and Figure5-6 in relation to ACQ CONV SCL. TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at V = 5.0V, V = GND. DD SS Parameter Sym. Min. Typ. Max. Units Conditions Temperature Ranges Operating Temperature Range T -40 — +125 °C A Extended Temperature Range T -40 — +125 °C A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, SOT-23  — 256 — °C/W JA DS20001732E-page 4  2002-2017 Microchip Technology Inc.

MCP3221 TIMING SPECIFICATIONS Electrical Characteristics: All parameters apply at V = 2.7V - 5.5V, V = GND, T = -40°C to +85°C. DD SS A Parameter Sym. Min. Typ. Max. Units Conditions I2C Standard Mode Clock Frequency f 0 — 100 kHz SCL Clock High Time T 4000 — — ns HIGH Clock Low Time T 4700 — — ns LOW SDA and SCL Rise Time T — — 1000 ns From V to V (Note1) R IL IH SDA and SCL Fall Time T — — 300 ns From V to V (Note1) F IL IH Start Condition Hold Time T 4000 — — ns HD:STA Start Condition Setup Time T 4700 — — ns SU:STA Data Input Setup Time T 250 — — ns SU:DAT Stop Condition Setup Time T 4000 — — ns SU:STO Stop Condition Hold time T 4000 — — ns HD:STD Output Valid from Clock T — — 3500 ns AA Bus Free Time T 4700 — — ns Note2 BUF Input Filter Spike Suppression T — — 50 ns SDA and SCL pins (Note1) SP I2C Fast Mode Clock Frequency F 0 — 400 kHz SCL Clock High Time T 600 — — ns HIGH Clock Low Time T 1300 — — ns LOW SDA and SCL Rise Time T 20 + 0.1C — 300 ns From V to V (Note1) R B IL IH SDA and SCL Fall Time T 20 + 0.1C — 300 ns From V to V (Note1) F B IL IH Start Condition Hold Time T 600 — — ns HD:STA Start Condition Setup Time T 600 — — ns SU:STA Data Input Hold Time T 0 — 0.9 ms HD:DAT Data Input Setup Time T 100 — — ns SU:DAT Stop Condition Setup Time T 600 — — ns SU:STO Stop Condition Hold Time T 600 — — ns HD:STD Output Valid from Clock T — — 900 ns AA Bus Free Time T 1300 — — ns Note2 BUF Input Filter Spike Suppression T — — 50 ns SDA and SCL pins (Note1) SP Note 1: This parameter is periodically sampled and not 100% tested. 2: Time the bus must be free before a new transmission can start. T HIGH V TF HYS TR SCL T SU:STA TLOW THD:DAT TSU:DAT TSU:STO SDA T IN T HD:STA SP T BUF T AA SDA OUT FIGURE 1-1: Standard and Fast Mode Bus Timing Data.  2002-2017 Microchip Technology Inc. DS20001732E-page 5

MCP3221 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, V = 5V, V = 0V, I2C Fast Mode Timing (SCL = 400kHz), Continuous Conversion DD SS Mode (f = 22.3ksps), T = +25°C. SAMP A 1 1 0.8 0.8 0.6 Positive INL 0.6 0.4 0.4 Positive INL B) 0.2 B) 0.2 S S L 0 L 0 NL (-0.2 NL (-0.2 I-0.4 Negative INL I-0.4 -0.6 -0.6 Negative INL -0.8 -0.8 -1 -1 0 100 200 300 400 0 100 200 300 400 IC Bus Rate (kHz) IC Bus Rate (kHz) 2 2 FIGURE 2-1: INL vs. Clock Rate. FIGURE 2-4: INL vs. Clock Rate (V =2.7V). DD 1 1 0.8 0.8 0.6 Positive INL 0.6 0.4 0.4 Positive INL B) 0.2 B) 0.2 S S L 0 L 0 NL (-0.2 NL ( -0.2 I-0.4 Negative INL I -0.4 Negative INL -0.6 -0.6 -0.8 -0.8 -1 -1 2.5 3 3.5 4 4.5 5 5.5 2.5 3 3.5 4 4.5 5 5.5 VDD (V) VDD (V) FIGURE 2-2: INL vs. V - I2C Standard FIGURE 2-5: INL vs. V - I2C Fast Mode DD DD Mode (f = 100kHz). (f = 400kHz). SCL SCL 2 2 1.5 1.5 1 1 B) 0.5 B) 0.5 S S L (L 0 L (L 0 N-0.5 N-0.5 I I -1 -1 -1.5 -1.5 -2 -2 0 1024 2048 3072 4096 0 1024 2048 3072 4096 Digital Code Digital Code FIGURE 2-3: INL vs. Code FIGURE 2-6: INL vs. Code (Representative Part). (Representative Part, V = 2.7V). DD DS20001732E-page 6  2002-2017 Microchip Technology Inc.

MCP3221 Note: Unless otherwise indicated, V = 5V, V = 0V, I2C Fast Mode Timing (SCL = 400kHz), Continuous Conversion DD SS Mode (f = 22.3ksps), T = +25°C. SAMP A 1 1 0.8 0.8 Positive INL 0.6 0.6 Positive INL 0.4 0.4 B) 0.2 B) 0.2 S S L 0 L 0 L ( -0.2 L ( -0.2 N N I -0.4 Negative INL I -0.4 -0.6 -0.6 Negative INL -0.8 -0.8 -1 -1 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) FIGURE 2-7: INL vs. Temperature. FIGURE 2-10: INL vs. Temperature (V =2.7V). DD 1 1 0.8 0.8 0.6 0.6 0.4 Positive DNL 0.4 NL (LSB) -00..202 NL (LSB) -00..202 Positive DNL D -0.4 D -0.4 Negative DNL -0.6 Negative DNL -0.6 -0.8 -0.8 -1 -1 0 100 200 300 400 0 100 200 300 400 I2C Bus Rate (kHz) I2C Bus Rate (kHz) FIGURE 2-8: DNL vs. Clock Rate. FIGURE 2-11: DNL vs. Clock Rate (V =2.7V). DD 1 1 0.8 0.8 0.6 0.6 0.4 Positive DNL 0.4 Positive DNL SB) 0.2 SB) 0.2 NL (L -0.20 NL (L -0.20 D -0.4 Negative DNL D -0.4 -0.6 -0.6 Negative DNL -0.8 -0.8 -1 -1 2.5 3 3.5 4 4.5 5 5.5 2.5 3 3.5 4 4.5 5 5.5 VDD (V) VDD (V) FIGURE 2-9: DNL vs. V - I2C Standard FIGURE 2-12: DNL vs. V - I2C Fast DD DD Mode (f = 100kHz). Mode (f = 400kHz). SCL SCL  2002-2017 Microchip Technology Inc. DS20001732E-page 7

MCP3221 Note: Unless otherwise indicated, V = 5V, V = 0V, I2C Fast Mode Timing (SCL = 400kHz), Continuous Conversion DD SS Mode (f = 22.3ksps), T = +25°C. SAMP A 1 1 0.8 0.8 0.6 0.6 NL (LSB)-000...0242 NL (LSB)-000...2024 D-0.4 D-0.4 -0.6 -0.6 -0.8 -0.8 -1 -1 0 1024 2048 3072 4096 0 1024 2048 3072 4096 Digital Code Digital Code FIGURE 2-13: DNL vs. Code FIGURE 2-16: DNL vs. Code (Representative Part). (Representative Part, V = 2.7V). DD 1 1 0.8 0.8 0.6 0.6 0.4 Positive DNL 0.4 Positive DNL B) 0.2 B) 0.2 S S NL (L -0.20 NL (L -0.20 D -0.4 D -0.4 Negative DNL -0.6 Negative DNL -0.6 -0.8 -0.8 -1 -1 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) FIGURE 2-14: DNL vs. Temperature. FIGURE 2-17: DNL vs. Temperature (V =2.7V). DD 0 1 -0.1 0.9 fSCL = 100 kHz & 400 kHz -0.2 0.8 SB) -0.3 SB) 0.7 ain Error (L ----0000....7654 F(faSCsLt= M 1o0d0e kHz) S(ftSaCnL=d a4r0d0 MkHodz)e set Error (L 0000....3456 G -0.8 Off 0.2 -0.9 0.1 -1 0 2.5 3 3.5 4 4.5 5 5.5 2.5 3 3.5 4 4.5 5 5.5 VDD (V) VDD (V) FIGURE 2-15: Gain Error vs. V . FIGURE 2-18: Offset Error vs. V . DD DD DS20001732E-page 8  2002-2017 Microchip Technology Inc.

MCP3221 Note: Unless otherwise indicated, V = 5V, V = 0V, I2C Fast Mode Timing (SCL = 400kHz), Continuous Conversion DD SS Mode (f = 22.3ksps), T = +25°C. SAMP A 3 2 1.8 2 Gain Error (LSB) --2101 VDD = 2.7V Offset Error (LSB) 000111......4681246 VDD = 5V 0.2 VDD = 5V VDD = 2.7V -3 0 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) FIGURE 2-19: Gain Error vs. Temperature. FIGURE 2-22: Offset Error vs. Temperature. 100 100 90 VDD = 5V 90 VDD = 5V 80 80 70 70 R (dB) 5600 VDD = 2.7V D (dB) 5600 VDD = 2.7V SN 40 NA 40 30 SI 30 20 20 10 10 0 0 1 10 1 10 Input Frequency (kHz) Input Frequency (kHz) FIGURE 2-20: SNR vs. Input Frequency. FIGURE 2-23: SINAD vs. Input Frequency. 0 80 -10 70 VDD = 5V -20 60 -30 THD (dB) ----76540000 VDD = 2.7V VDD = 5V SINAD (dB) 345000 VDD = 2.7V 20 -80 -90 10 -100 0 1 10 -40 -30 -20 -10 0 Input Frequency (kHz) Input Signal Level (dB) FIGURE 2-21: THD vs. Input Frequency. FIGURE 2-24: SINAD vs. Input Signal Level.  2002-2017 Microchip Technology Inc. DS20001732E-page 9

MCP3221 Note: Unless otherwise indicated, V = 5V, V = 0V, I2C Fast Mode Timing (SCL = 400kHz), Continuous Conversion DD SS Mode (f = 22.3ksps), T = +25°C. SAMP A 12 12 11.95 11.5 11.9 ms) 1111.8.58 ms) 11 VDD = 2.7V B (r 11.75 B (r10.5 VDD = 5V ENO 1111.6.57 ENO 10 11.6 9.5 11.55 11.5 9 2.5 3 3.5 4 4.5 5 5.5 1 10 VDD (V) Input Frequency (kHz) FIGURE 2-25: ENOB vs. V . FIGURE 2-28: ENOB vs. Input Frequency. DD 100 90 VDD = 5V 10 fSAMP = 5.6 ksps 80 -10 70 B) -30 R (dB) 5600 VDD = 2.7V ude (d -50 SFD 3400 mplit --9700 A 20 -110 10 -130 0 0 500 1000 1500 2000 2500 1 10 Input Frequency (kHz) Frequency (Hz) FIGURE 2-26: SFDR vs. Input Frequency. FIGURE 2-29: Spectrum Using I2C Standard Mode (Representative Part, 1kHz Input Frequency). 250 10 -10 200 B) -30 e (d -50 µA) 150 plitud -70 I (DD100 m -90 A 50 -110 0 -130 0 2000 4000 6000 8000 10000 2.5 3 3.5 4 4.5 5 5.5 Frequency (Hz) VDD (V) FIGURE 2-27: Spectrum Using I2C Fast FIGURE 2-30: I (Conversion) vs. V . DD DD Mode (Representative Part, 1kHz Input Frequency). DS20001732E-page 10  2002-2017 Microchip Technology Inc.

MCP3221 Note: Unless otherwise indicated, V = 5V, V = 0V, I2C Fast Mode Timing (SCL = 400kHz), Continuous Conversion DD SS Mode (f = 22.3ksps), T = +25°C. SAMP A 200 100 180 90 160 80 140 70 A) 120 A) 60 I (µDD 10800 VDD = 5V I (µDDA 4500 VDD = 5V 60 30 40 20 VDD = 2.7V 20 VDD = 2.7V 10 0 0 0 100 200 300 400 0 100 200 300 400 I2C Clock Rate (kHz) I2C Clock Rate (kHz) FIGURE 2-31: I (Conversion) vs. Clock FIGURE 2-34: I (Active Bus) vs. Clock DD DDA Rate. Rate. 250 100 90 200 80 VDD = 5V VDD = 5V 70 A) 150 µA) 60 (µDD 100 (DDA 4500 I VDD = 2.7V I 30 50 20 VDD = 2.7V 10 0 0 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) FIGURE 2-32: I (Conversion) vs. FIGURE 2-35: I (Active Bus) vs. DD DDA Temperature. Temperature. 100 60 90 80 50 70 40 A) 60 A) µ p (DDA 4500 (DDS 30 I 30 I 20 20 10 10 0 0 2.5 3 3.5 4 4.5 5 5.5 2.5 3 3.5 4 4.5 5 5.5 V (V) V (V) DD DD FIGURE 2-33: I (Active Bus) vs. V . FIGURE 2-36: I (Standby) vs. V . DDA DD DDS DD  2002-2017 Microchip Technology Inc. DS20001732E-page 11

MCP3221 Note: Unless otherwise indicated, V = 5V, V = 0V, I2C Fast Mode Timing (SCL = 400kHz), Continuous Conversion DD SS Mode (f = 22.3ksps), T = +25°C. SAMP A 2.1 Test Circuits 1000 100 V = 5V 10 DD A) 1 n (DS 0.1 ID 10µF 0.1µF 0.01 2k 2k 0.001 0.0001 A VDDSDA IN -50 -25 0 25 50 75 100 125 MCP3221 V SCL Temperature (°C) V SS IN FIGURE 2-37: I (Standby) vs. DDS Temperature. V = 2.5V CM 2 A) 1.8 e (n 1.6 FIGURE 2-39: Typical Test Configuration. g 1.4 a ak 1.2 e L 1 put 0.8 n g I 0.6 alo 0.4 An 0.2 0 -50 -25 0 25 50 75 100 125 Temperature (°C) FIGURE 2-38: Analog Input Leakage vs. Temperature. DS20001732E-page 12  2002-2017 Microchip Technology Inc.

MCP3221 3.0 PIN FUNCTIONS 3.3 Serial Data (SDA) Table3-1 lists the function of the pins. SDA is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open-drain TABLE 3-1: PIN FUNCTION TABLE terminal, therefore, the SDA bus requires a pull-up resistor to V (typically 10k for 100kHz and 2k DD Name Function for 400kHz SCL clock speeds). Refer to Section6.2 V +2.7V to 5.5V Power Supply “Connecting to the I2C Bus” for more information. DD V Ground For normal data transfer, SDA is allowed to change only SS A Analog Input during SCL low. Changes during SCL high are reserved IN for indicating the Start and Stop conditions. Refer to SDA Serial Data In/Out Section5.1 “I2C Bus Characteristics” for more infor- SCL Serial Clock In mation. 3.1 V and V 3.4 Serial Clock (SCL) DD SS The VDD pin, with respect to VSS, provides power to the SCL is an input pin used to synchronize the data trans- device as well as a voltage reference for the conversion fer to and from the device on the SDA pin and is an process. Refer to Section6.4 “Device Power and open-drain terminal. Therefore, the SCL bus requires a Layout Considerations” for tips on power and pull-up resistor to V (typically 10k for 100kHz and DD grounding. 2k for 400kHz SCL clock speeds. Refer to Section6.2 “Connecting to the I2C Bus” for more 3.2 Analog Input (A ) IN information. A is the input pin to the sample and hold circuitry of For normal data transfer, SDA is allowed to change IN the Successive Approximation Register (SAR) con- only during SCL low. Changes during SCL high are verter. Care should be taken in driving this pin. Refer to reserved for indicating the Start and Stop conditions. Section6.1 “Driving the Analog Input” for more Refer to Section6.1 “Driving the Analog Input” for information. For proper conversions, the voltage on this more information. pin can vary from V to V . SS DD  2002-2017 Microchip Technology Inc. DS20001732E-page 13

MCP3221 4.0 DEVICE OPERATION 4.2 Conversion Time (t ) CONV The MCP3221 employs a classic SAR architecture. The conversion time is the time required to obtain the This architecture uses an internal sample and hold digital result once the analog input is disconnected capacitor to store the analog input while the conversion from the holding capacitor. With the MCP3221, the is taking place. At the end of the acquisition time, the specified conversion time is typically 8.96µs. This time input switch of the converter opens and the device uses is dependent on the internal oscillator and is the collected charge on the internal sample and hold independent of SCL. capacitor to produce a serial 12-bit digital output code. 4.3 Acquisition Time (t ) The acquisition time and conversion is self-timed using ACQ an internal clock. After each conversion, the results are The acquisition time is the amount of time the sample stored in a 12-bit register that can be read at any time. cap array is acquiring charge. Communication with the device is accomplished with a The acquisition time is, typically, 1.12µs. This time is 2-wire, I2C interface. Maximum sample rates of dependent on the internal oscillator and independent of 22.3ksps are possible with the MCP3221 in a continu- SCL. ous-conversion mode and an SCL clock rate of 400kHz. 4.4 Sample Rate 4.1 Digital Output Code Sample rate is the inverse of the maximum amount of time that is required from the point of acquisition of the The digital output code produced by the MCP3221 is a first conversion to the point of acquisition of the second function of the input signal and power supply voltage, conversion. V . As the V level is reduced, the LSB size is DD DD reduced accordingly. The theoretical LSB size is shown The sample rate can be measured either by single or below. continuous conversions. A single conversion includes a Start bit, Address byte, two data bytes and a Stop bit. EQUATION This sample rate is measured from one Start bit to the next Start bit. V DD LSB SIZE = ------------ For continuous conversions (requested by the Master 4096 by issuing an Acknowledge after a conversion), the maximum sample rate is measured from conversion to V = Supply voltage DD conversion or a total of 18 clocks (two data bytes and two Acknowledge bits). Refer to Section5.2 “Device The output code of the MCP3221 is transmitted serially Addressing” for more information. with MSB first. The format of the code is straight binary. Output Code 1111 1111 1111 (4095) 1111 1111 1110 (4094) 0000 0000 0011 (3) 0000 0000 0010 (2) 0000 0000 0001 (1) 0000 0000 0000 (0) A IN .5LSB V -1.5 LSB DD 1.5LSB V -2.5 LSB 2.5LSB DD FIGURE 4-1: Transfer Function. DS20001732E-page 14  2002-2017 Microchip Technology Inc.

MCP3221 4.5 Differential Non-Linearity (DNL) 4.8 Gain Error In the ideal A/D converter transfer function, each code Gain error determines the amount of deviation from the has a uniform width. That is, the difference in analog ideal slope of the A/D converter transfer function. input voltage is constant from one code transition point Before the gain error is determined, the offset error is to the next. Differential nonlinearity (DNL) specifies the measured and subtracted from the conversion result. deviation of any code in the transfer function from an The gain error can then be determined by finding the ideal code width of 1LSB. The DNL is determined by location of the last code transition and comparing that subtracting the locations of successive code transition location to the ideal location. The ideal location of the points after compensating for any gain and offset last code transition is 1.5LSBs below full-scale or V . DD errors. A positive DNL implies that a code is longer than the ideal code width, whereas a negative DNL implies 4.9 Conversion Current (IDD) that a code is shorter than the ideal width. Conversion current is the average amount of current 4.6 Integral Non-Linearity (INL) over the time required to perform a 12-bit conversion. Integral nonlinearity (INL) is a result of cumulative DNL 4.10 Active Bus Current (IDDA) errors and specifies how much the overall transfer The average amount of current over the time required function deviates from a linear response. The method to monitor the I2C bus. Any current that the device con- of measurement used in the MCP3221 A/D converter sumes while it is not being addressed is referred to as to determine INL is the end-point method. Active Bus current. 4.7 Offset Error 4.11 Standby Current (I ) DDS Offset error is defined as a deviation of the code transi- The average amount of current required while no con- tion points that are present across all output codes. version is occurring and no data is being output (i.e., This has the effect of shifting the entire A/D transfer SCL and SDA lines are quiet). function. The offset error is measured by finding the dif- ference between the actual location of the first code 4.12 I2C Standard Mode Timing transition and the desired location of the first transition. The ideal location of the first code transition is located I2C specification where the frequency of SCL is at 1/2LSB above VSS. 100kHz. 4.13 I2C Fast Mode Timing I2C specification where the frequency of SCL is 400kHz.  2002-2017 Microchip Technology Inc. DS20001732E-page 15

MCP3221 5.0 SERIAL COMMUNICATIONS Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of data 5.1 I2C Bus Characteristics bytes being transferred between the Start and Stop conditions is determined by the master device and is The following bus protocol are defined: unlimited. • Data transfer may be initiated only when the bus 5.1.5 ACKNOWLEDGE is not busy. • During data transfer, the data line must remain Each receiving device, when addressed, is obliged to stable whenever the clock line is high. Changes in generate an Acknowledge bit after the reception of the data line while the clock line is high will be each byte. The master device must generate an extra interpreted as a Start or Stop condition. clock pulse that is associated with this Acknowledge bit. Accordingly, the following bus conditions are defined (refer to Figure5-1). The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a 5.1.1 BUS NOT BUSY (A) way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Setup Both data and clock lines remain high. and hold times must be taken into account. During 5.1.2 START DATA TRANSFER (B) reads, a master device must signal an end of data to the slave by not generating an Acknowledge bit on the A high-to-low transition of the SDA line while the clock last byte that is clocked out of the slave (NAK). In this (SCL) is high determines a Start condition. All case, the slave (MCP3221) releases the bus to allow commands must be preceded by a Start condition. the master device to generate the Stop condition. 5.1.3 STOP DATA TRANSFER (C) The MCP3221 supports a bidirectional, 2-wire bus and data transmission protocol. The device that sends data A low-to-high transition of the SDA line while the clock onto the bus is the transmitter and the device receiving (SCL) is high determines a Stop condition. All data is the receiver. The bus has to be controlled by a operations must be ended with a Stop condition. master device that generates the serial clock (SCL), controls the bus access and generates the Start and 5.1.4 DATA VALID (D) Stop conditions, whereas the MCP3221 works as a slave device. Both master and slave devices can oper- The state of the data line represents valid data when ate as either transmitter or receiver, but the master after a START condition, the data line is stable for the device determines which mode is activated. duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. (A) (B) (D) (D) (C) (A) SCL SDA START ADDRESS OR DATA STOP CONDITION ACKNOWLEDGE ALLOWED CONDITION VALID TO CHANGE FIGURE 5-1: Data Transfer Sequence on the Serial Bus. DS20001732E-page 16  2002-2017 Microchip Technology Inc.

MCP3221 5.2 Device Addressing 5.3 Executing a Conversion The address byte is the first byte received following the This section describes the details of communicating Start condition from the master device. The first part of with the MCP3221 device. Initiating the sample and the control byte consists of a 4-bit device code, which hold acquisition, reading the conversion data, and is set to 1001 for the MCP3221. The device code is fol- executing multiple conversions are discussed. lowed by three address bits: A2, A1 and A0. The default address bits are 101. Contact the Microchip factory for 5.3.1 INITIATING THE SAMPLE AND additional address bit options. The address bits allow HOLD up to eight MCP3221 devices on the same bus and are The acquisition and conversion of the input signal used to determine which device is accessed. begins with the falling edge of the R/W bit of the The eighth bit of the slave address determines if the address byte. At this point, the internal clock initiates master device wants to read conversion data or write to the sample, hold and conversion cycle, all of which are the MCP3221. When set to a 1, a read operation is internal to the ADC. selected. When set to a 0, a write operation is selected. There are no writable registers on the MCP3221, there- fore, this bit must be set to a 1 to initiate a conversion. tACQ + tCONV is initiated here The MCP3221 is a slave device that is compatible with the 2-wire I2C serial interface protocol. A hardware Address Byte connection diagram is shown in Figure6-2. Communi- cation is initiated by the microcontroller (master device), which sends a Start bit followed by the address SCL 1 2 3 4 5 6 7 8 9 byte. On completion of the conversion(s) performed by the K MCP3221, the microcontroller must send a Stop bit to SDA 1 0 0 1 A2 A1 A0R/W AC end the communication. Start The last bit in the device address byte is the R/W bit. bit Device bits Address bits When this bit is a logic 1, a conversion is executed. Set- ting this bit to logic 0 also results in an Acknowledge (ACK) from the MCP3221, with the device then releas- FIGURE 5-3: Initiating the Conversion, ing the bus. This can be used for device polling. Refer Address Byte. to Section6.3 “Device Polling” for more information. START READ/WRITE t + t is ACQ CONV initiated here SLAVE ADDRESS R/W A Lower Data Byte (n) 17 18 19 20 21 22 23 24 2526 SCL 1 0 0 1 1 0 1 K K SDA D8 C D7D6D5 D4D3 D2D2D0 C Device code Address bits(1) A A Note 1: Contact Microchip for additional address bits. FIGURE 5-4: Initiating the Conversion, Continuous Conversions. FIGURE 5-2: Device Addressing.  2002-2017 Microchip Technology Inc. DS20001732E-page 17

MCP3221 The input signal is initially sampled with the first falling 5.3.2 READING THE CONVERSION DATA edge of the clock following the transmission of a After the MCP3221 acknowledges the address byte, the logic-high R/W bit. Additionally, with the rising edge of device transmits four 0 bits followed by the upper four the SCL, the ADC transmits an Acknowledge bit (ACK data bits of the conversion. The master device acknowl- = 0). The master must release the data bus during this edges this byte with an ACK = Low. With the following clock pulse to allow the MCP3221 to pull the line low eight clock pulses, the MCP3221 transmits the lower (refer to Figure5-3). eight data bits from the conversion. The master sends For consecutive samples, sampling begins on the fall- an ACK = high, indicating to the MCP3221 that no more ing edge of the LSB of the conversion result, which is data is requested. The master can send a Stop bit to two bytes long. Refer to Figure5-6 for the timing end the transmission. diagram. tACQ + tCONV is initiated here 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 SCL S T S A Address Byte Upper Data Byte Lower Data Byte T R O T P SDA S 1 0 0 1 A A A R/ AC 0 0 0 0 D D D D AC D D D D D D D D NA P 2 1 0 W K 11 10 9 8 K 7 6 5 4 3 2 1 0 K Device bits Address bits FIGURE 5-5: Executing a Conversion. 5.3.3 CONSECUTIVE CONVERSIONS For consecutive samples, sampling begins on the fall- ing edge of the LSB of the conversion result. See Figure5-6 for timing. tACQ + tCONV is tACQ + tCONV is initiated here initiated here fSAMP = 22.3ksps (fCLK = 400kHz) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SCL S T Address Byte Upper Data Byte (n) Lower Data Byte (n) A R T SDA S 1 0 0 1 A2 A1 A0 R/ AC 0 0 0 0 D D D D AC D D D D D D D D AC 0 W K 11 10 9 8 K 7 6 5 4 3 2 1 0 K Device bits Address bits FIGURE 5-6: Continuous Conversion. DS20001732E-page 18  2002-2017 Microchip Technology Inc.

MCP3221 6.0 APPLICATIONS INFORMATION The analog input model is shown in Figure6-1. In this diagram, the source impedance (R ) adds to the inter- SS 6.1 Driving the Analog Input nal sampling switch (RS) impedance, directly affecting the time required to charge the capacitor (C ). SAMPLE The MCP3221 has a single-ended analog input (AIN). Consequently, a larger source impedance increases For proper conversion results, the voltage at the AIN pin the offset error, gain error and integral linearity errors of must be kept between VSS and VDD. If the converter the conversion. Ideally, the impedance of the signal has no offset error, gain error, INL or DNL errors, and source should be near zero. This is achievable with an the voltage level of AIN is equal to or less than operational amplifier such as the MCP6022, which has VSS + 1/2LSB, the resultant code is 000h. Addition- a closed-loop output impedance of tens of ohms. ally, if the voltage at A is equal to or greater than IN VDD - 1.5LSB, the output code is FFFh. V DD Sampling Switch V = 0.6V RSS AIN T SS RS = 1k C SAMPLE VA 7CPpIFN VT = 0.6V I±L1EAnKAAGE == 2D0ACpF capacitance V SS Legend VA = signal source R = source impedance SS A = analog input pad IN C = analog input pin capacitance PIN V = threshold voltage T I = leakage current at the pin LEAKAGE due to various junctions SS = sampling switch R = sampling switch resistor S C = sample/hold capacitance SAMPLE FIGURE 6-1: Analog Input Model, A . IN 6.2 Connecting to the I2C Bus The number of devices connected to the bus is only limited by the maximum bus capacitance of 400pF. A The I2C bus is an open collector bus, requiring pull-up possible configuration using multiple devices is shown resistors connected to the SDA and SCL lines. This in Figure6-3. configuration is shown in Figure6-2. SDA SCL V DD PIC16F876 Microcontroller er MCP3221 oll RPU RPU 24LC01 ®PICocontr SSDCAL AIN Analog MCP3221 EEPROM cr Input 12-bit ADC Mi Signal TC74 Temperature R is typically: 10k for f = 100kHz PU SCL Sensor 2k for f = 400kHz SCL FIGURE 6-2: Pull-up Resistors on I2C Bus. FIGURE 6-3: Multiple Devices on I2C Bus.  2002-2017 Microchip Technology Inc. DS20001732E-page 19

MCP3221 6.3 Device Polling 6.4.2 LAYOUT CONSIDERATIONS In some instances, it may be necessary to test for When laying out a printed circuit board for use with MCP3221 presence on the I2C bus without performing analog components, care should be taken to reduce a conversion as described in Figure6-4 where the R/W noise wherever possible. A bypass capacitor from VDD bit in the address byte is set to a zero. The MCP3221 to ground must be used always with this device and acknowledges by pulling SDA low during the ACK clock placed as close as possible to the device pin. A bypass and then release the bus back to the I2C master. A Stop capacitor value of 0.1µF is recommended. or repeated Start bit can be issued from the master and Digital and analog traces should be separated as much I2C communication can continue. as possible on the board, with no traces running underneath the device or the bypass capacitor. Extra Address Byte precautions should be taken to keep traces with high- frequency signals (such as clock lines) as far as SCL 1 2 3 4 5 6 7 8 9 possible from analog traces. Use of an analog ground plane is recommended in K SDA 1 0 0 1 A2A1A0 0 AC order to keep the ground potential the same for all devices on the board. Providing V connections to DD Start R/W Start devices in a Star configuration can also reduce noise bit Device bits Address bits bit by eliminating current return paths and associated errors (Figure6-6). For more information on layout tips MCP3221 response when using the MCP3221 or other ADC devices, refer to the Microchip Technology Application Note, “AN688 FIGURE 6-4: Device Polling. Layout Tips for 12-Bit A/D Converter Application” 6.4 Device Power and Layout (DS00688). Considerations V DD Connection 6.4.1 POWERING THE MCP3221 V supplies the power to the device and the reference DD voltage. A bypass capacitor value of 0.1µF is recom- mended. Adding a 10µF capacitor in parallel is recom- Device 4 mended to attenuate higher frequency noise that is Device 1 present in some systems. V DD Device 3 V DD Device 2 10µF 0.1µF VDD SCL RPU RPU FIGURE 6-6: V traces arranged in a AIN MCP3221 To Star configuration in oDrdDer to reduce errors SDA Microcontroller caused by current return paths. FIGURE 6-5: Powering the MCP3221. Note: When power-down of the MCP3221 is needed during applications (after power- up), it is highly recommended to bring down the V to V level. This can guar- DD SS antee a Full Reset of the device for the next power-up cycle. DS20001732E-page 20  2002-2017 Microchip Technology Inc.

MCP3221 6.4.3 USING A REFERENCE FOR SUPPLY The MCP3221 uses V as power and also as a refer- DD ence. In some applications, it may be necessary to use a stable reference to achieve the required accuracy. Figure6-7 shows an example using the MCP1541 as a 4.096V, 2% reference. V DD F µ VDD 1 1µF 0. MCP1541 C L R4e.0fe9r6eVnce VDD RPU oller AIN MCP32SS2DC1AL Tocontr o cr Mi FIGURE 6-7: Stable Power and Reference Configuration.  2002-2017 Microchip Technology Inc. DS20001732E-page 21

MCP3221 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 5-Pin SOT-23 3 2 1 1 2 3 4 4 5 Part Number Address Option SOT-23 MCP3221A0T-E/OT 000 GE MCP3221A1T-E/OT 001 GH MCP3221A2T-E/OT 010 GB MCP3221A3T-E/OT 011 GC MCP3221A4T-E/OT 100 GD MCP3221A5T-E/OT 101 GA * MCP3221A6T-E/OT 110 GF MCP3221A7T-E/OT 111 GG * Default option. Contact Microchip Factory for other address options. Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS20001732E-page 22  2002-2017 Microchip Technology Inc.

MCP3221 5-Lead Plastic Small Outline Transistor (OT) (SOT-23) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p B p1 D n 1  c A A2  A1 L  Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 5 5 Pitch p .038 0.95 Outside lead pitch (basic) p1 .075 1.90 Overall Height A .035 .046 .057 0.90 1.18 1.45 Molded Package Thickness A2 .035 .043 .051 0.90 1.10 1.30 Standoff A1 .000 .003 .006 0.00 0.08 0.15 Overall Width E .102 .110 .118 2.60 2.80 3.00 Molded Package Width E1 .059 .064 .069 1.50 1.63 1.75 Overall Length D .110 .116 .122 2.80 2.95 3.10 Foot Length L .014 .018 .022 0.35 0.45 0.55 Foot Angle f 0 5 10 0 5 10 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .014 .017 .020 0.35 0.43 0.50 Mold Draft Angle Top a 0 5 10 0 5 10 Mold Draft Angle Bottom b 0 5 10 0 5 10 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. EIAJ Equivalent: SC-74A Drawing No. C04-091 Revised 09-12-05  2002-2017 Microchip Technology Inc. DS20001732E-page 23

MCP3221 NOTES: DS20001732E-page 24  2002-2017 Microchip Technology Inc.

MCP3221 APPENDIX A: REVISION HISTORY Revision E (January 2017) • Added a note to Section6.4.1 “Powering the MCP3221”. • Fixed Section7.1 “Package Marking Informa- tion” format to reflect the correct package mark- ing as “1 2 3 4” instead of “1 10 10 10”. • Updated Temperature Specifiations table to remove information on Industrial Temperature Range Revision D (January 2013) • Added a note to each package outline drawing. Revision C (July 2006) • Updated Section5.2 “Device Addressing”: changed 4-bit device code to “1001”. Changed three address bits to “101”. Revision B (May 2003) • Numerous changes throughout document. Revision A (November 2002) • Original Release of this Document.  2002-2017 Microchip Technology Inc. DS20001732E-page 25

MCP3221 NOTES: DS20001732E-page 26  2002-2017 Microchip Technology Inc.

MCP3221 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XX X /XX Examples: a) MCP3221A0T-E/OT: Extended, A0 Address, Device Address Temperature Package Tape and Reel Options Range b) MCP3221A1T-E/OT: Extended, A1 Address, Tape and Reel c) MCP3221A2T-E/OT: Extended, A2 Address, Device: MCP3221T: 12-Bit 2-Wire Serial A/D Converter (Tape and Reel) Tape and Reel d) MCP3221A3T-E/OT: Extended, A3 Address, Tape and Reel Temperature Range: E= -40C to +125C e) MCP3221A4T-E/OT: Extended, A4 Address, Tape and Reel Address Options: XX A2 A1 A0 f) MCP3221A5T-E/OT: Extended, A5 Address, A0 = 0 0 0 Tape and Reel g) MCP3221A6T-E/OT: Extended, A6 Address, A1 = 0 0 1 Tape and Reel A2 = 0 1 0 h) MCP3221A7T-IE/OT: Extended, A7 Address, A3 = 0 1 1 Tape and Reel A4 = 1 0 0 A5 * = 1 0 1 A6 = 1 1 0 A7 = 1 1 1 * Default option. Contact Microchip factory for other address options Package: OT = SOT-23, 5-lead (Tape and Reel)  2002-2017 Microchip Technology Inc. DS20001732E-page 27

MCP3221 NOTES: DS20001732E-page 28  2002-2017 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, AVR, and may be superseded by updates. It is your responsibility to AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, ensure that your application meets with your specifications. CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, MICROCHIP MAKES NO REPRESENTATIONS OR KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, WARRANTIES OF ANY KIND WHETHER EXPRESS OR maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, IMPLIED, WRITTEN OR ORAL, STATUTORY OR OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip OTHERWISE, RELATED TO THE INFORMATION, Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST INCLUDING BUT NOT LIMITED TO ITS CONDITION, Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered QUALITY, PERFORMANCE, MERCHANTABILITY OR trademarks of Microchip Technology Incorporated in the U.S.A. FITNESS FOR PURPOSE. Microchip disclaims all liability and other countries. arising from this information and its use. Use of Microchip ClockWorks, The Embedded Control Solutions Company, devices in life support and/or safety applications is entirely at EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, the buyer’s risk, and the buyer agrees to defend, indemnify and mTouch, Precision Edge, and Quiet-Wire are registered hold harmless Microchip from any and all damages, claims, trademarks of Microchip Technology Incorporated in the U.S.A. suits, or expenses resulting from such use. No licenses are Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any conveyed, implicitly or otherwise, under any Microchip Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, intellectual property rights unless otherwise stated. CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in Microchip received ISO/TS-16949:2009 certification for its worldwide the U.S.A. headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California Silicon Storage Technology is a registered trademark of Microchip and India. The Company’s quality system processes and procedures Technology Inc. in other countries. are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and GestIC is a registered trademark of Microchip Technology analog products. In addition, Microchip’s quality system for the design Germany II GmbH & Co. KG, a subsidiary of Microchip Technology and manufacture of development systems is ISO 9001:2000 certified. Inc., in other countries. All other trademarks mentioned herein are property of their QUALITY MANAGEMENT SYSTEM respective companies. © 2002-2017, Microchip Technology Incorporated, All Rights CERTIFIED BY DNV Reserved. ISBN: 978-1-5224-1291-5 == ISO/TS 16949 ==  2002-2017 Microchip Technology Inc. DS20001732E-page 11

Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Asia Pacific Office China - Xiamen Austria - Wels 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 86-592-2388138 Tel: 43-7242-2244-39 Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 86-592-2388130 Fax: 43-7242-2244-393 Tel: 480-792-7200 Harbour City, Kowloon China - Zhuhai Denmark - Copenhagen Fax: 480-792-7277 Hong Kong Tel: 86-756-3210040 Tel: 45-4450-2828 Technical Support: Tel: 852-2943-5100 Fax: 86-756-3210049 Fax: 45-4485-2829 http://www.microchip.com/ Fax: 852-2401-3431 India - Bangalore Finland - Espoo support Australia - Sydney Tel: 91-80-3090-4444 Tel: 358-9-4520-820 Web Address: www.microchip.com Tel: 61-2-9868-6733 Fax: 91-80-3090-4123 France - Paris Fax: 61-2-9868-6755 India - New Delhi Tel: 33-1-69-53-63-20 Atlanta China - Beijing Tel: 91-11-4160-8631 Fax: 33-1-69-30-90-79 Duluth, GA Tel: 678-957-9614 Tel: 86-10-8569-7000 Fax: 91-11-4160-8632 France - Saint Cloud Fax: 678-957-1455 Fax: 86-10-8528-2104 India - Pune Tel: 33-1-30-60-70-00 China - Chengdu Tel: 91-20-3019-1500 Germany - Garching Austin, TX Tel: 512-257-3370 Tel: 86-28-8665-5511 Japan - Osaka Tel: 49-8931-9700 Fax: 86-28-8665-7889 Tel: 81-6-6152-7160 Germany - Haan Boston China - Chongqing Fax: 81-6-6152-9310 Tel: 49-2129-3766400 Westborough, MA Tel: 86-23-8980-9588 Tel: 774-760-0087 Japan - Tokyo Germany - Heilbronn Fax: 86-23-8980-9500 Tel: 81-3-6880- 3770 Tel: 49-7131-67-3636 Fax: 774-760-0088 China - Dongguan Fax: 81-3-6880-3771 Germany - Karlsruhe Chicago Itasca, IL Tel: 86-769-8702-9880 Korea - Daegu Tel: 49-721-625370 Tel: 630-285-0071 China - Guangzhou Tel: 82-53-744-4301 Germany - Munich Fax: 630-285-0075 Tel: 86-20-8755-8029 Fax: 82-53-744-4302 Tel: 49-89-627-144-0 China - Hangzhou Korea - Seoul Fax: 49-89-627-144-44 Dallas Tel: 86-571-8792-8115 Tel: 82-2-554-7200 Addison, TX Germany - Rosenheim Tel: 972-818-7423 Fax: 86-571-8792-8116 Fax: 82-2-558-5932 or Tel: 49-8031-354-560 Fax: 972-818-2924 China - Hong Kong SAR 82-2-558-5934 Israel - Ra’anana Detroit Tel: 852-2943-5100 Malaysia - Kuala Lumpur Tel: 972-9-744-7705 Fax: 852-2401-3431 Tel: 60-3-6201-9857 Novi, MI Italy - Milan Tel: 248-848-4000 China - Nanjing Fax: 60-3-6201-9859 Tel: 39-0331-742611 Houston, TX Tel: 86-25-8473-2460 Malaysia - Penang Fax: 39-0331-466781 Fax: 86-25-8473-2470 Tel: 60-4-227-8870 Tel: 281-894-5983 Italy - Padova Fax: 60-4-227-4068 Indianapolis China - Qingdao Tel: 39-049-7625286 Noblesville, IN Tel: 86-532-8502-7355 Philippines - Manila Netherlands - Drunen Fax: 86-532-8502-7205 Tel: 63-2-634-9065 Tel: 317-773-8323 Tel: 31-416-690399 Fax: 63-2-634-9069 Fax: 317-773-5453 China - Shanghai Fax: 31-416-690340 Tel: 317-536-2380 Tel: 86-21-3326-8000 Singapore Norway - Trondheim Fax: 86-21-3326-8021 Tel: 65-6334-8870 Los Angeles Tel: 47-7289-7561 Mission Viejo, CA China - Shenyang Fax: 65-6334-8850 Poland - Warsaw Tel: 949-462-9523 Tel: 86-24-2334-2829 Taiwan - Hsin Chu Tel: 48-22-3325737 Fax: 949-462-9608 Fax: 86-24-2334-2393 Tel: 886-3-5778-366 Tel: 951-273-7800 China - Shenzhen Fax: 886-3-5770-955 Romania - Bucharest Tel: 40-21-407-87-50 Raleigh, NC Tel: 86-755-8864-2200 Taiwan - Kaohsiung Tel: 919-844-7510 Fax: 86-755-8203-1760 Tel: 886-7-213-7830 Spain - Madrid Tel: 34-91-708-08-90 New York, NY China - Wuhan Taiwan - Taipei Fax: 34-91-708-08-91 Tel: 631-435-6000 Tel: 86-27-5980-5300 Tel: 886-2-2508-8600 Fax: 86-27-5980-5118 Fax: 886-2-2508-0102 Sweden - Gothenberg San Jose, CA Tel: 46-31-704-60-40 Tel: 408-735-9110 China - Xian Thailand - Bangkok Tel: 408-436-4270 Tel: 86-29-8833-7252 Tel: 66-2-694-1351 Sweden - Stockholm Fax: 86-29-8833-7256 Fax: 66-2-694-1350 Tel: 46-8-5090-4654 Canada - Toronto Tel: 905-695-1980 UK - Wokingham Fax: 905-695-2078 Tel: 44-118-921-5800 Fax: 44-118-921-5820 DS20001732E-page 30  2002-2017 Microchip Technology Inc. 11/07/16