MC74HC573A Octal 3-State Noninverting Transparent Latch High−Performance Silicon−Gate CMOS The MC74HC573A is identical in pinout to the LS573. The devices www.onsemi.com are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched. SOIC−20 TSSOP−20 The HC573A is identical in function to the HC373A but has the data DW SUFFIX DT SUFFIX inputs on the opposite side of the package from the outputs to facilitate CASE 751D CASE 948E PC board layout. PIN ASSIGNMENT Features OUTPUT • Output Drive Capability: 15 LSTTL Loads ENABLE 1 20 VCC • D0 2 19 Q0 Outputs Directly Interface to CMOS, NMOS and TTL D1 3 18 Q1 • Operating Voltage Range: 2.0 to 6.0 V D2 4 17 Q2 • Low Input Current: 1.0 (cid:2)A D3 5 16 Q3 D4 6 15 Q4 • In Compliance with the JEDEC Standard No. 7.0 A Requirements D5 7 14 Q5 • Chip Complexity: 218 FETs or 54.5 Equivalent Gates D6 8 13 Q6 • D7 9 12 Q7 NLV Prefix for Automotive and Other Applications Requiring GND 10 11 LATCH Unique Site and Control Change Requirements; AEC−Q100 ENABLE Qualified and PPAP Capable • These Devices are Pb−Free and are RoHS Compliant MARKING DIAGRAMS 20 20 LOGIC DIAGRAM HC 74HC573A 573A 2 19 AWLYYWWG ALYW(cid:2) D0 Q0 (cid:2) 3 18 D1 Q1 4 17 1 1 D2 Q2 SOIC−20 TSSOP−20 DATA D3 5 16 Q3 NONINVERTING A = Assembly Location INPUTS D4 6 15 Q4 OUTPUTS WL, L = Wafer Lot 7 14 YY, Y = Year D5 Q5 WW, W = Work Week 8 13 D6 Q6 G or (cid:2) = Pb−Free Package 9 12 D7 Q7 (Note: Microdot may be in either location) 11 LATCH ENABLE FUNCTION TABLE 1 PIN 20 = VCC Inputs Output OUTPUT ENABLE PIN 10 = GND Output Latch Enable Enable D Q Design Criteria Value Units L H H H L H L L Internal Gate Count* 54.5 ea. L L X No Change Internal Gate Progation Delay 1.5 ns H X X Z Internal Gate Power Dissipation 5.0 (cid:2)W X = Don’t Care Z = High Impedance Speed Power Product 0.0075 pJ ORDERING INFORMATION *Equivalent to a two−input NAND gate. See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: May, 2018 − Rev. 17 MC74HC573A/D

MC74HC573A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol Parameter Value Unit This device contains protection VCC DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V circuitry to guard against damage due to high static voltages or electric Vin DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V fields. However, precautions must Vout DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V be taken to avoid applications of any Iin DC Input Current, per Pin ±20 mA voltage higher than maximum rated Iout DC Output Current, per Pin ±35 mA voltages to this high−impedance cir- ICC DC Supply Current, VCC and GND Pins ±75 mA cVuoiutt. Fshoor upldro pbeer coopnesrtartaioinne, dV tino athned PD Power Dissipation in Still Air, SOIC Package† 500 mW range GND (cid:2) (Vin or Vout) (cid:2) VCC. TSSOP Package† 450 Unused inputs must always be Tstg Storage Temperature –65 to +150 (cid:3)C tied to an appropriate logic voltage TL Lead Temperature, 1 mm from Case for 10 Seconds (cid:3)C Ulenvuesl e(de .ogu.,t puetitsh meru sGt NbeD leoftr opVeCnC.). (TSSOP or SOIC Package) 260 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating: SOIC Package: –7 mW/(cid:3)C from 65(cid:3) to 125(cid:3)C TSSOP Package: −6.1 mW/°C from 65(cid:3) to 125(cid:3)C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V TA Operating Temperature, All Package Types –55 +125 (cid:3)C tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns (Figure 1) VCC = 4.5 V 0 500 VCC = 6.0 V 0 400 Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit VCC –55 to Symbol Parameter Test Conditions V 25(cid:3)C (cid:2)85(cid:3)C (cid:2)125(cid:3)C Unit VIH Minimum High−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V 2.0 1.5 1.5 1.5 V |Iout| (cid:2) 20 (cid:2)A 3.0 2.1 2.1 2.1 4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 VIL Maximum Low−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V 2.0 0.5 0.5 0.5 V |Iout| (cid:2) 20 (cid:2)A 3.0 0.9 0.9 0.9 4.5 1.35 1.35 1.35 6.0 1.8 1 8 1.8 VOH Minimum High−Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V Voltage |Iout| (cid:2) 20 (cid:2)A 4.5 4.4 4.4 4.4 6.0 5.9 5.9 5.9 Vin = VIH or VIL |Iout| ≤ 2.4mA 3.0 2.48 2.34 2.2 |Iout| (cid:2) 6.0 mA 4.5 3.98 3.84 3.7 |Iout| (cid:2) 7.8 mA 6.0 5.48 5.34 5.2 VOL Maximum Low−Level Output Vout = 0.1 V or VCC – 0.1 V 2.0 0.1 0.1 0.1 V Voltage |Iout| (cid:2) 20 (cid:2)A 4.5 0.1 0.1 0.1 6.0 0.1 0.1 0.1 Vin = VIH or VIL |Iout| ≤ 2.4mA 3.0 0.26 0.33 0.4 |Iout| (cid:2) 6.0 mA 4.5 0.26 0.33 0.4 |Iout| (cid:2) 7.8 mA 6.0 0.26 0.33 0.4 Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 (cid:2)A IOZ Maximum Three−State Leakage Output in High−Impedance State 6.0 ±0.5 ±5.0 ±10 (cid:2)A Current Vin = VIL or VIH Vout = VCC or GND ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 4.0 40 160 (cid:2)A Current (per Package) IIoutI = 0 (cid:2)A www.onsemi.com 2

MC74HC573A AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) VCC Guaranteed Limit Symbol Parameter V –55 to 25(cid:3)C (cid:2)85(cid:3)C (cid:2)125(cid:3)C Unit tPLH, Maximum Propagation Delay, Input D to Q 2.0 150 190 225 ns tPHL (Figures 1 and 5) 3.0 100 140 180 4.5 30 38 45 6.0 26 33 38 tPLH, Maximum Propagation Delay, Latch Enable to Q 2.0 160 200 240 ns tPHL (Figures 2 and 5) 3.0 105 145 190 4.5 32 40 48 6.0 27 34 41 tPLZ, Maximum Propagation Delay, Output Enable to Q 2.0 150 190 225 ns tPHZ (Figures 3 and 6) 3.0 100 125 150 4.5 30 38 45 6.0 26 33 38 tPZL, Maximum Propagation Delay, Output Enable to Q 2.0 150 190 225 ns tPZH (Figures 3 and 6) 3.0 100 125 150 4.5 30 38 45 6.0 26 33 38 tTLH, Maximum Output Transition Time, Any Output 2.0 60 75 90 ns tTHL (Figures 1 and 5) 3.0 27 32 36 4.5 12 15 18 6.0 10 13 15 Cin Maximum Input Capacitance 10 10 10 pF Cout Maximum 3−State Output Capacitance (Output in High−Impedance State) 15 15 15 pF Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Enabled Output)* 23 pF *Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit –55 to 25(cid:3)C (cid:2)85(cid:3)C (cid:2)125(cid:3)C VCC Symbol Parameter Figure V Min Max Min Max Min Max Unit tsu Minimum Setup Time, Input D to Latch Enable 4 2.0 50 65 75 ns 3.0 40 50 60 4.5 10 13 15 6.0 9.0 11 13 th Minimum Hold Time, Latch Enable to Input D 4 2.0 5.0 5.0 5.0 ns 3.0 5.0 5.0 5.0 4.5 5.0 5.0 5.0 6.0 5.0 5.0 5.0 tw Minimum Pulse Width, Latch Enable 2 2.0 75 95 110 ns 3.0 60 80 90 4.5 15 19 22 6.0 13 16 19 tr, tf Maximum Input Rise and Fall Times 1 2.0 1000 1000 1000 ns 3.0 800 800 800 4.5 500 500 500 6.0 400 400 400 www.onsemi.com 3

MC74HC573A SWITCHING WAVEFORMS VCC LATCH tr tf ENABLE 50% 90% VCC GND INPUT D 50% 10% GND tw tPLH tPHL 90% Q 50% tPLH tPHL 10% tTLH tTHL Q 50% Figure 1. Figure 2. OUTPUT VCC ENABLE 50% VALID GND tPZL tPLZ HIGH INPUT D 50% VCC GND Q VM IMPEDANCE tPZH tPHZ 10% VOL tSU th VCC 90% VOH LATCH 50% Q VM HIGH ENABLE GND IMPEDANCE MC74HC573A: VM = VOH x 0.5 MC74HCT573A: VM = 1.3 V @ VCC = 3 V Figure 3. Figure 4. 2 D0 D 19 Q Q0 TEST POINT LE 3 D1 D 18 OUTPUT Q Q1 LE DEVICE 4 UNDER D2 D 17 TEST CL* Q Q2 LE 5 D3 D 16 Q Q3 LE *Includes all probe and jig capacitance D4 6 D 15 Q Q4 Figure 5. Test Circuit LE 7 D5 D 14 Q Q5 LE 8 D6 D 13 TEST POINT Q Q6 LE OUTPUT 1 k(cid:3) CTEOSNTNINEGCT tP TLOZ AVNCDC WtPZHLE.N D7 9 D Q 12Q7 DEVICE CONNECT TO GND WHEN LE UNDER TESTING tPHZ AND tPZH. TEST CL* 11 LATCH ENABLE 1 OUTPUT ENABLE *Includes all probe and jig capacitance Figure 6. Test Circuit Figure 7. EXPANDED LOGIC DIAGRAM www.onsemi.com 4

MC74HC573A ORDERING INFORMATION Device Package Shipping† MC74HC573ADWG SOIC−20 WIDE 38 Units / Rail (Pb−Free) MC74HC573ADWR2G SOIC−20 WIDE 1000 Tape & Reel (Pb−Free) MC74HC573ADTG TSSOP−20 75 Units / Rail (Pb−Free) MC74HC573ADTR2G TSSOP−20 2500 Tape & Reel (Pb−Free) NLV74HC573ADTR2G* TSSOP−20 2500 Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. www.onsemi.com 5

MC74HC573A PACKAGE DIMENSIONS TSSOP−20 DT SUFFIX CASE 948E ISSUE D NOTES: 20X K REF K 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 0.15 (0.006) T U S 0.10 (0.004) M T U S V S K1 2. CONTROLLING DIMENSION: ÍÍÍÍ MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE ÍÍÍÍ MOLD FLASH, PROTRUSIONS OR GATE 20 11 J J1 BURRS. MOLD FLASH OR GATE BURRS 2X L/2 ÍÍÍÍ SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE B SECTION N−N INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION L −U− SHALL NOT EXCEED 0.25 (0.010) PER SIDE. PIN 1 0.25 (0.010) 5. DIMENSION K DOES NOT INCLUDE IDENT N DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 1 10 (0.003) TOTAL IN EXCESS OF THE K M DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR 0.15 (0.006) T U S REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE A N DETERMINED AT DATUM PLANE −W−. −V− F MILLIMETERS INCHES DIM MIN MAX MIN MAX DETAIL E A 6.40 6.60 0.252 0.260 B 4.30 4.50 0.169 0.177 C --- 1.20 --- 0.047 −W− D 0.05 0.15 0.002 0.006 C F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC G H 0.27 0.37 0.011 0.015 D H J 0.09 0.20 0.004 0.008 DETAIL E J1 0.09 0.16 0.004 0.006 0.100 (0.004) K 0.19 0.30 0.007 0.012 −T− SPELAATNIENG KML1 00.61 (cid:3).940 BSC08.2 (cid:3)5 0.0000 (cid:3).2752 B0S.C081 (cid:3)0 SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 16X 0.36 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 6

MC74HC573A PACKAGE DIMENSIONS SOIC−20 DW SUFFIX CASE 751D−05 ISSUE H D NOTES: A (cid:2) 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD 20 11 M PROTRUSION. B 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. (cid:3) 5. DIMENSION B DOES NOT INCLUDE DAMBAR H M 45 PROTRUSION. ALLOWABLE PROTRUSION 10X 0.25 E hX SDCHIOMANELDNLI STBIIOEO NN0.. 1A3T TMOATXAILM IUNM E MXCATEESRSI AOLF B 1 10 MILLIMETERS DIM MIN MAX A 2.35 2.65 B A1 0.10 0.25 20X B B 0.35 0.49 C 0.23 0.32 0.25 M T A S B S D 12.65 12.95 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 A L 0.50 0.90 L (cid:2) 0 (cid:3) 7 (cid:3) SEATING 18X e A1 TPLANE C RECOMMENDED SOLDERING FOOTPRINT* 20X 20X 1.30 0.52 20 11 11.00 1 10 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada For additional information, please contact your local Email: orderlit@onsemi.com Sales Representative ◊ www.onsemi.com MC74HC573A/D 7