19-1803; Rev 3; 3/09 Single/Dual LVDS Line Receivers with Ultra-Low Pulse Skew in SOT23 General Description Features M The MAX9111/MAX9113 single/dual low-voltage differen- (cid:2) Low 300ps (max) Pulse Skew for High-Resolution A tial signaling (LVDS) receivers are designed for high- Imaging and High-Speed Interconnect X speed applications requiring minimum power (cid:2) Space-Saving 8-Pin SOT23 and SO Packages consumption, space, and noise. Both devices support 9 switching rates exceeding 500Mbps while operating from (cid:2) Pin-Compatible Upgrades to DS90LV018A and 1 a single +3.3V supply, and feature ultra-low 300ps (max) DS90LV028A (SO Packages Only) 1 pulse skew required for high-resolution imaging applica- (cid:2) Guaranteed 500Mbps Data Rate 1 tions such as laser printers and digital copiers. (cid:2) Low 29mW Power Dissipation at 3.3V / The MAX9111 is a single LVDS receiver, and the (cid:2) Conform to EIA/TIA-644 Standard M MAX9113 is a dual LVDS receiver. (cid:2) Single +3.3V Supply A Both devices conform to the EIA/TIA-644 LVDS standard (cid:2) Flow-Through Pinout Simplifies PCB Layout X and convert LVDS to LVTTL/CMOS-compatible outputs. A fail-safe feature sets the outputs high when the inputs (cid:2) Fail-Safe Circuit Sets Output High for Undriven 9 are undriven and open, terminated, or shorted. The Inputs 1 MAX9111/MAX9113 are available in space-saving 8-pin (cid:2) High-Impedance LVDS Inputs when Powered Off 1 SOT23 and SO packages. Refer to the MAX9110/ 3 MAX9112 data sheet for single/dual LVDS line drivers. Ordering Information ________________________Applications TEMP PIN- TOP PART RANGE PACKAGE MARK Laser Printers Network Switches/Routers MAX9111EKA -40°C to +85°C 8 SOT23 AAEE Digital Copiers LCD Displays MAX9111ESA -40°C to +85°C 8 SO — Cellular Phone Backplane Interconnect MAX9113EKA -40°C to +85°C 8 SOT23 AAED Base Stations Clock Distribution MAX9113ESA -40°C to +85°C 8 SO — Telecom Switching MAX9113ASA/V+ -40°C to +125°C 8 SO — Equipment /V denotes an automotive qualified part. +Denotes a lead(Pb)-free/RoHS-compliant package. Typical Operating Circuit appears at end of data sheet. Pin Configurations/Functional Diagrams/Truth Table MAX9111 MAX9111 MAX9113 MAX9113 IN- 1 8 VCC VCC 1 8 IN- IN1- 1 8 VCC VCC 1 8 IN1- IN+ 2 7 OUT GND 2 7 IN+ IN1+ 2 7 OUT1 GND 2 7 IN1+ N.C. 3 6 N.C. OUT 3 6 N.C. IN2+ 3 6 OUT2 OUT1 3 6 IN2+ MAX9111 N.C. 4 5 GND N.C. 4 5 N.C. IN2- 4 5 GND OUT2 4 5 IN2- SO SOT23 SO SOT23 (IN_+) - (IN_-) OUT_ ≥ 100mV H ≥ -100mV L H = LOGIC LEVEL HIGH OPEN H L = LOGIC LEVEL LOW SHORT H 100Ω PARALLEL TERMINATION (UNDRIVEN) H ________________________________________________________________Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.

Single/Dual LVDS Line Receivers with Ultra-Low Pulse Skew in SOT23 3 ABSOLUTE MAXIMUM RATINGS 1 VCCto GND..............................................................-0.3V to +4V 8-Pin SO (derate 5.88mW°C above +70°C).................471mW 1 IN_ _ to GND.........................................................-0.3V to +3.9V Operating Temperature Ranges 9 OUT_ _ to GND...........................................-0.3V to (VCC+ 0.3V) MAX911_E.......................................................-40°C to +85°C ESD Protection All Pins MAX911_A.....................................................-40°C to +125°C X (Human Body Model, IN_+, IN_-)..................................±11kV Storage Temperature Range.............................-65°C to +150°C A Continuous Power Dissipation (TA= +70°C) Lead Temperature (soldering, 10s).................................+300°C 8-Pin SOT23 (derate 8.9mW/°C above +70°C)............714mW M / 1 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to 1 absolute maximum rating conditions for extended periods may affect device reliability. 1 9 ELECTRICAL CHARACTERISTICS X A (VCC = +3.0V to +3.6V, magnitude of input voltage, |VID| = +0.1V to +1.0V, VCM = |VID|/2 to (2.4V - (|VID|/2)), TA = TMIN to TMAX. Typical values are at VCC= +3.3V and TA= +25°C, unless otherwise noted.) (Notes 1, 2) M PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Differential Input High Threshold (Note 3) VTH VCM = 0.05V, 1.2V, 2.75V at 3.3V 100 mV Differential Input Low Threshold (Note 3) VTL VCM = 0.05V, 1.2V, 2.75V at 3.3V -100 mV Differential Input Resistance RDIFF VCM = 0.2V or 2.2V, VID = ±0.4V, 5 18 kΩ VCC = 0 or 3.6V VID = +200mV 2.7 Inputs shorted, 2.7 undriven Output High Voltage (OUT_) VOH IOH = -4mA V 100Ω parallel termination, 2.7 undriven Output Low Voltage (OUT_) VOL IOL = 4mA, VID = -200mV 0.4 Output Short-Circuit Current IOS VID = +200mV, VOUT_ = 0 -100 mA MAX9111 4.2 6 No-Load Supply Current ICC mA MAX9113 8.7 11 2 _______________________________________________________________________________________

Single/Dual LVDS Line Receivers with Ultra-Low Pulse Skew in SOT23 SWITCHING CHARACTERISTICS M (VCC= +3.0V to +3.6V, TA= TMINto TMAX. Typical values are at VCC= +3.3V and TA= +25°C, unless otherwise noted.) (Notes 4, 5, 6) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS X Differential Propagation Delay CL = 15pF, VID = TA = +85°C 1.0 1.77 2.5 9 High to Low tPHLD ±200mV, VCM = 1.2V ns 1 (Figures 1, 2) TA = +125°C 3.0 1 Differential Propagation Delay CL = 15pF, VID = TA = +85°C 1.0 1.68 2.5 1 Low to High tPLHD ±200mV, VCM = 1.2V ns / (Figures 1, 2) TA = +125°C 3.0 M Differential Pulse Skew A tSKD1 90 300 ps |tPLHD - tPHLD| (Note 7) X Differential Channel-to-Channel 9 Skew; Same Device (MAX9113 tSKD2 140 400 ps 1 only) (Note 8) CL = 15pF, VID = ±200mV, VCM = 1.2V (Figures 1, 2) 1 Differential Part-to-Part Skew 3 tSKD3 1 ns (Note 9) Differential Part-to-Part Skew tSKD4 1.5 ns (MAX9113 only) (Note 10) CL = 15pF, VID = TA = +85°C 0.6 0.8 Rise Time tTLH ±200mV, VCM = 1.2V ns (Figures 1, 2) TA = +125°C 1.0 CL = 15pF, VID = TA = +85°C 0.6 0.8 Fall Time tTHL ±200mV, VCM = 1.2V ns (Figures 1, 2) TA = +125°C 1.0 All channels switching, CL = 15pF, Maximum Operating Frequency fMAX VOL (max) = 0.4V, VOH (min) = 2.7V, 250 300 MHz 40% < duty cycle < 60% (Note 6) Note 1: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at TA= +25°C. Note 2: Current into the device is defined as positive. Current out of the devices is defined as negative. All voltages are referenced to ground except VTHand VTL. Note 3: Guaranteed by design, not production tested. Note 4: ACparameters are guaranteed by design and characterization. Note 5: CLincludes probe and test jig capacitance. Note 6: fMAXgenerator output conditions: tR= tF< 1ns (0 to 100%), 50% duty cycle, VOH= 1.3V, VOL= 1.1V. Note 7: tSKD1is the magnitude difference of differential propagation delays in a channel. tSKD1= |tPLHD - tPHLD|. Note 8: tSKD2is the magnitude difference of the tPLHDor tPHLDof one channel and the tPLHDor tPHLDof the other channel on the same device. Note 9: tSKD3is the magnitude difference of any differential propagation delays between devices at the same VCCand within 5°C of each other. Note 10: tSKD4, is the magnitude difference of any differential propagation delays between devices operating over the rated supply and temperature ranges. _______________________________________________________________________________________ 3

Single/Dual LVDS Line Receivers with Ultra-Low Pulse Skew in SOT23 3 Test Circuit Diagrams 1 1 9 IN_+ X GENERATOR IN_- R OUT_ A CL M 50Ω 50Ω / 1 1 1 Figure 1. Receiver Propagation Delay and Transition Time Test Circuit 9 X A M IN_- +1.3V 0V DIFFERENTIAL VID = 200mV +1.2V IN_+ +1.1V tPLHD tPHLD 80% 80% VOH 50% 50% 20% 20% OUT_ VOL tTLH tTHL Figure 2. Receiver Propagation Delay and Transition Time Waveforms 4 _______________________________________________________________________________________

Single/Dual LVDS Line Receivers with Ultra-Low Pulse Skew in SOT23 Typical Operating Characteristics M (VCC = 3.3V, |VID| = 200mV, VCM = 1.2V, fIN = 200MHz, CL = 15pF, TA = +25°C and over recommended operating conditions, A unless otherwise specified.) X OUTPUT HIGH VOLTAGE OUTPUT LOW VOLTAGE OUTPUT SHORT-CIRCUIT CURRENT 9 vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE 1 OUTPUT HIGH VOLTAGE (V) 22233333333...........78901234567 IOUT_ = 4mA MAX9111 toc01 OUTPUT LOW VOLTAGE (mV) 111132100000 IOUT_ = 4mA MAX9111 toc02 UTPUT SHORT-CIRCUIT CURRENT (mA) 55667788383833 VID = 200mV MAX9111 toc03 11/MAX91 2.6 O 1 2.5 90 48 3 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) DIFFERENTIAL THRESHOLD VOLTAGE MAX9113 POWER-SUPPLY CURRENT POWER-SUPPLY CURRENT vs. SUPPLY VOLTAGE vs. FREQUENCY vs. TEMPERATURE NTIAL THRESHOLD VOLTAGE (mV) 21220824 LOW-HIGHHIGH-LOW MAX9111 toc04 WER-SUPPLY CURRENT (mA) 2435600000 BOTH CHANNELS SWITCHING MAX9111 toc05 WER-SUPPLY CURRENT (mA) 6677777777..........8901234567 fBINO T=H 1 MCHHAzNNELS SWITCHING MAX9111 toc06 FERE 16 PO 10 PO 6.7 F DI 6.6 ONE SWITCHING 14 0 6.5 3.0 3.1 3.2 3.3 3.4 3.5 3.6 0.01 0.1 1 10 100 1000 -40 -15 10 35 60 85 SUPPLY VOLTAGE (V) FREQUENCY (MHz) TEMPERATURE (°C) DIFFERENTIAL PROPAGATION DELAY DIFFERENTIAL PROPAGATION DELAY DIFFERENTIAL PULSE SKEW vs. SUPPLY VOLTAGE vs. TEMPERATURE vs. SUPPLY VOLTAGE DIFFERENTIAL PROPAGATION DELAY (ns) 111111111222............656778899001055050505050 tPLHD tPHLD MAX9111 toc07 DIFFERENTIAL PROPAGATION DELAY (ns) 11111111212222..............6567788909011205550050055050 tPHLD tPLHD MAX9111 toc08 DIFFERENTIAL SKEW (ns) 1186200000 MAX9111 toc09 1.50 1.50 40 3.0 3.1 3.2 3.3 3.4 3.5 3.6 -40 -15 10 35 60 85 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) TEMPERATURE (°C) SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 5

Single/Dual LVDS Line Receivers with Ultra-Low Pulse Skew in SOT23 3 Typical Operating Characteristics (continued) 1 (VCC = 3.3V, |VID| = 200mV, VCM = 1.2V, fIN = 200MHz, CL = 15pF, TA = +25°C and over recommended operating conditions, 1 unless otherwise specified.) 9 X DIFFERENTIAL PULSE SKEW DIFFERENTIAL PROPAGATION DELAY DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE vs. DIFFERENTIAL INPUT VOLTAGE vs. COMMON-MODE VOLTAGE 1/MA W (ps) 220500 MAX9111 toc10 ON DELAY (ns) 2223....4680 fIN = 20MHz tPHLD MAX9111 toc11 ON DELAY (ns) 222...012 fIN = 20MHz MAX91111 toc12 11 TIAL SKE 150 OPAGATI 22..02 OPAGATI 1.9 X9 DIFFEREN 100 ENTIAL PR 11..68 ENTIAL PR 1.8 tPHLD A 50 FER 1.4 tPLHD FER 1.7 F F M DI 1.2 DI tPLHD 0 1.0 1.6 -40 -15 10 35 60 85 0 500 1000 1500 2000 2500 0 0.5 1.0 1.5 2.0 2.5 3.0 TEMPERATURE (°C) DIFFERENTIAL INPUT VOLTAGE (mV) COMMON-MODE VOLTAGE (V) DIFFERENTIAL PROPAGATION DELAY TRANSITION TIME vs. TEMPERATURE vs. LOAD 663800 tTHL MAX9111 toc14 ELAY (ns) 223...791 MAX9111 toc15 NSITION TIME (ps) 545388000 tTLH L PROPAGATION D 222...315 tPHLD A A TR 430 RENTI 1.9 tPLHD E F 380 DIF 1.7 330 1.5 -40 -15 10 35 60 85 10 15 20 25 30 35 40 45 50 TEMPERATURE (°C) LOAD (pF) TRANSITION TIME vs. LOAD 2200 MAX9111 toc16 ps)1800 ME ( tTHL N TI1400 O TI SI AN1000 tTLH R T 600 200 10 15 20 25 30 35 40 45 50 LOAD (pF) 6 _______________________________________________________________________________________

Single/Dual LVDS Line Receivers with Ultra-Low Pulse Skew in SOT23 Pin Description M A PIN X MAX9111 MAX9113 NAME FUNCTION 9 SOT23-8 SO-8 SOT23-8 SO-8 1 1 8 1 8 VCC Power Supply 1 1 2 5 2 5 GND Ground / M 8 1 8 1 IN-/IN1- Receiver Inverting Differential Input A 7 2 7 2 IN+/IN1+ Receiver Noninverting Differential Input X — — 5 4 IN2- Receiver Inverting Differential Input 9 — — 6 3 IN2+ Receiver Noninverting Differential Input 1 3 7 3 7 OUT/OUT1 Receiver Output 1 3 — — 4 6 OUT2 Receiver Output 4, 5, 6 3, 4, 6 — — N.C. No Connection. Not internally connected. _______________Detailed Description ESD Protection As with all Maxim devices, ESD-protection structures are LVDS Inputs incorporated on all pins to protect against electrostatic The MAX9111/MAX9113 feature LVDS inputs for inter- discharges encountered during handling and assembly. facing high-speed digital circuitry. The LVDS interface The receiver inputs of the MAX9111/MAX9113 have extra standard is a signaling method intended for point-to- protection against static electricity. Maxim’s engineers point communication over a controlled impedance have developed state-of-the-art structures to protect media, as defined by the ANSI/EIA/TIA-644 standards. these pins against ESD of ±11kV without damage. The The technology uses low-voltage signals to achieve fast ESD structures withstand high ESD in all states: normal transition times, minimize power dissipation, and noise operation, shutdown, and powered down. immunity. Receivers such as the MAX9111/MAX9113 ESD protection can be tested in various ways; the convert LVDS signals to CMOS/LVTTL signals at rates receiver inputs of this product family are characterized in excess of 500Mbps. The devices are capable of detecting differential signals as low as 100mV and as for protection to the limit of ±11kV using the Human high as 1V within a 0V to 2.4V input voltage range. The Body Model. LVDS standard specifies an input voltage range of 0 to Human Body Model 2.4V referenced to ground. Figure 3a shows the Human Body Model, and Figure 3b shows the current waveform it generates when dis- charged into a low impedance. This model consists of a Fail-Safe 100pF capacitor charged to the ESD voltage of interest, The fail-safe feature sets the output to a high state which is then discharged into the test device through a when the inputs are undriven and open, terminated, or 1.5kΩresistor. shorted. When using one channel in the MAX9113, leave the unused channel open. The fail-safe feature is not guaranteed to be operational above +85°C. _______________________________________________________________________________________ 7

Single/Dual LVDS Line Receivers with Ultra-Low Pulse Skew in SOT23 3 1 RC RD 1MΩ 1500Ω IP 100% Ir PEAK-TO-PEAK RINGING 1 90% (NOT DRAWN TO SCALE) 9 CHARGE-CURRENT DISCHARGE LIMIT RESISTOR RESISTANCE X AMPERES A HIGH- DEVICE 36.8% VOLTAGE Cs STORAGE UNDER M DC 100pF CAPACITOR TEST 10% SOURCE 0 / 0 TIME 1 tRL tDL 1 CURRENT WAVEFORM 1 Figure 3a. Human Body ESD Test Modules Figure 3b. Human Body Current Waveform 9 X A __________Applications Information Termination M The MAX9111/MAX9113 input differential voltage Supply Bypassing depends on the driver current and termination resis- Bypass VCC with high-frequency surface-mount ceram- tance. Refer to the MAX9110/MAX9112 differential dri- ic 0.1µF and 0.001µF capacitors in parallel, as close to ver data sheet for this information. the device as possible, with the 0.001µF valued capaci- Minimize the distance between the termination resistor tor the closest to the device. For additional supply and receiver inputs. Use a single 1% to 2% surface- bypassing, place a 10µF tantalum or ceramic capacitor mount resistor across the receiver inputs. at the point where power enters the circuit board. Board Layout Differential Traces For LVDS applications, a four-layer PCB that provides Output trace characteristics affect the performance of separate power, ground, LVDS signals, and input sig- the MAX9111/MAX9113. Use controlled impedance nals is recommended. Isolate the input and LVDS sig- traces to match trace impedance to both transmission nals from each other to prevent coupling. For best medium impedance and the termination resistor. results, separate the input and LVDS signal planes with Eliminate reflections and ensure that noise couples as the power and ground planes. common mode by running the differential traces close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. Maintain the distance between the differential traces to avoid discontinuities in differential impedance. Avoid 90° turns and minimize the number of vias to further prevent impedance discontinuities. Cables and Connectors Transmission media should have a differential charac- teristic impedance of about 100Ω. Use cables and con- nectors that have matched impedance to minimize impedance discontinuities. Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by the LVDS receiver. 8 _______________________________________________________________________________________

Single/Dual LVDS Line Receivers with Ultra-Low Pulse Skew in SOT23 Typical Operating Circuit M A X +3.3V +3.3V 9 0.001μF 0.1μF 0.001μF 0.1μF 1 1 1 / DIN_ DRIVER RT = 100Ω RECEIVER OUT_ M A LVDS X 9 MAX9110 MAX9111 1 MAX9112 MAX9113 1 3 Chip Information Package Information PROCESS: CMOS For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 8 SOT23 K8-1 21-0078 8 SO S8-2 21-0041 _______________________________________________________________________________________ 9

Single/Dual LVDS Line Receivers with Ultra-Low Pulse Skew in SOT23 3 Revision History 1 1 REVISION REVISION PAGES DESCRIPTION NUMBER DATE CHANGED 9 X 0 — Initial release — A 1 2/07 — 1, 2, 8, 10, 11 Updated Ordering Information, temperature, Switching Characteristics, Fail-Safe M 2 12/07 1, 2, 3, 7 section. / 1 3 3/09 Added /V designation to Ordering Information and updated Termination section. 1, 8 1 1 9 X A M Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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