EVALUATION KIT AVAILABLE MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter General Description Features The MAX7057 frequency-programmable UHF transmitter ● Programmable Frequency Operation with Single is designed to transmit ASK/FSK data at a wide range Crystal of frequencies from 300MHz to 450MHz. The MAX7057 ● Internal Variable Capacitor for Antenna Tuning with has internal tuning capacitors at the output of the power Single-Matching Network amplifier that are programmable for matching to an ● 100kbps Data Rate (NRZ) antenna or load. This allows the user to change to a new frequency and match the antenna at the new frequency ● +2.1V to +3.6V Single-Supply Operation simultaneously. The MAX7057 transmits at a data rate up ● < 12.5mA (FSK), < 8.5mA (ASK) DC Current Drain to 100kbps nonreturn-to-zero (NRZ) (50kbps Manchester ● < 1µA Standby Current coded). Typical transmitted power into a 50Ω load is +9.2dBm with a +2.7V supply. The device operates from ● ASK/FSK Modulation +2.1V to +3.6V and typically draws under 12.5mA of ● 47% Carrier Tuning Range Using One Crystal current in FSK mode (8.5mA in ASK mode) when the antenna-matching network is designed to operate over Ordering Information the 315MHz to 433.92MHz frequency range. For narrower operating frequency ranges, the matching network can be PART TEMP RANGE PIN-PACKAGE redesigned to improve efficiency. The standby current is MAX7057ASE+ -40°C to +125°C 16 SO less than 1µA at room temperature. +Denotes a lead(Pb)-free/RoHs-compliant package. The MAX7057 reference frequency from the crystal oscil- lator is multiplied by a fully integrated fractional-N phase- Pin Configuration locked loop (PLL). The multiplying factor of the PLL is set by a 16-bit number, with 4 bits for integer and 12 bits for fraction; the multiplying factor can be anywhere between TOP VIEW 19 and 28. The 12-bit fraction in the synthesizer sets a tuning resolution equal to the reference frequency divided CS 1 + 16 DVDD by 4096; frequency deviation can be set as low as ±2kHz SDI 2 15 GPO and as high as ±100kHz. The fractional-N synthesizer MAX7057 eliminates the problems associated with oscillator-pull- SCLK 3 14 DGND ing FSK signal generation. The MAX7057 has a serial PAGND 4 13 DIN peripheral interface (SPI) for selecting all the necessary PAOUT 5 12 ENABLE settings. ROUT 6 11 AGND The MAX7057 is available in a 16-pin SO package and is specified to operate in the -40°C to +125°C automotive PAVDD 7 10 XTAL1 temperature range. AVDD 8 9 XTAL2 Applications ● RF Remote Controls ● Wireless Game Consoles ● Garage Door Openers ● Wireless Computer ● Home Automation Peripherals Typical Application Circuit and Functional Diagram appear ● Wireless Sensors ● Security Systems at end of data sheet. 19-4093; Rev 2; 7/14

MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter Absolute Maximum Ratings Supply Voltage, PAVDD, AVDD, DVDD to AGND, Operating Temperature ....................................-40°C to +125°C DGND, PAGND.................................................-0.3V to +4.0V Storage Temperature Range ............................-65°C to +150°C All Other Pins............................_GND - 0.3V to _VDD + 0.3V Lead Temperature (soldering, 10s) .................................+300°C Continuous Power Dissipation (TA = +70°C) Soldering Temperature (reflow) .......................................+260°C 16-Pin SO (derate 8.7mW/°C above +70°C) ............695.7mW Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (Typical Application Circuit, 50Ω system impedance, tuned for 315MHz to 433.92MHz operation, VAVDD = VDVDD = VPAVDD = +2.1V to +3.6V, fRF = 300MHz to 450MHz, fCRYSTAL = 16MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VPAVDD = +2.7V, TA = +25°C, unless otherwise noted. All min and max values are 100% tested at TA = +125°C, and guaranteed by design and characterization over temperature, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PAVDD, AVDD, and DVDD connected to Supply Voltage VDD 2.1 2.7 3.6 V power supply, VDD PA off, VDIN at 0% fRF = 315MHz 3.9 6.5 duty cycle (ASK) fRF = 433.92MHz 4.5 7.5 Supply Current IDD VDIN at 50% duty fRF = 315MHz 8.1 15.1 mA cycle (ASK) (Notes 1, 2, 3) fRF = 433.92MHz 8.5 15.0 VDIN at 100% duty fRF = 315MHz 12.2 23.7 cycle (FSK) (Note 1) fRF = 433.92MHz 12.4 22.4 TA = +25°C (Note 3) 0.8 Standby Current ISTDBY VENABLE < VIL TA < +85°C (Note 3) 1 6.4 µA TA < +125°C 6.2 20.1 DIGITAL I/O 0.9 x Input High Threshold VIH V VDVDD 0.1 x Input Low Threshold VIL V VDVDD Input Pulldown Sink Current 13 µA Input Pullup Source Current 9 µA Output-Voltage High VOH ISINK = 500µA (GPO) V0D.3D7 - V Output-Voltage Low VOL ISOURCE = 500µA (GPO) 0.36 V www.maximintegrated.com Maxim Integrated │ 2

MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter AC Electrical Characteristics (Typical Application Circuit, 50Ω system impedance, tuned for 315MHz to 433.92MHz operation, VAVDD = VDVDD = VPAVDD = +2.1V to +3.6V, fRF = 300MHz to 450MHz, fCRYSTAL = 16MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VPAVDD = +2.7V, TA = +25°C, unless otherwise noted. All min and max values are 100% tested at TA = +125°C, and guaranteed by design and characterization over temperature, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS GENERAL CHARACTERISTICS Frequency Range 300 450 MHz ENABLE transition low-to-high, frequency 120 settled to within 50kHz of the desired carrier Power-On Time tON µs ENABLE transition low-to-high, frequency 260 settled to within 5kHz of the desired carrier Manchester encoded 50 ASK mode Nonreturn-to-Zero 100 Maximum Data Rate kbps Manchester encoded 50 FSK mode Nonreturn-to-Zero 100 Time from end of SPI write to frequency Frequency Switching Time 70 µs settled to within 5kHz of desired carrier PHASE-LOCKED LOOP (PLL) VCO Gain KVCO 320 MHz/V 10kHz offset -78 fRF = 315MHz 1MHz offset -98 PLL Phase Noise dBc/Hz 10kHz offset -73 fRF = 433.92MHz 1MHz offset -98 Loop Bandwidth 300 kHz Reference Frequency Input Level 500 mVP-P Frequency-Divider Range 19 28 Frequency Deviation (FSK) ±2 ±100 kHz CRYSTAL OSCILLATOR Crystal Frequency fXTAL 10.71 16 23.68 MHz Frequency Pulling by VDD 4 ppm/V Crystal Load Capacitance (Note 4) 10 pF POWER AMPLIFIER (PA) TA = +25°C (Note 3) 3.8 9.2 16.4 TA = +125°C, VAVDD = VDVDD = VPAVDD = 2.4 5.2 Output Power (Note 1) POUT +2.1V dBm TA = -40°C, VAVDD = VDVDD = VPAVDD = 12.6 17.0 +3.6V (Note 3) Modulation Depth 71 dB With output matching fRF = 315MHz -29 Maximum Carrier Harmonics dBc network fRF = 433.92MHz -44 Reference Spur -45 dBc www.maximintegrated.com Maxim Integrated │ 3

MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter AC Electrical Characteristics (continued) (Typical Application Circuit, 50Ω system impedance, tuned for 315MHz to 433.92MHz operation, VAVDD = VDVDD = VPAVDD = +2.1V to +3.6V, fRF = 300MHz to 450MHz, fCRYSTAL = 16MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VPAVDD = +2.7V, TA = +25°C, unless otherwise noted. All min and max values are 100% tested at TA = +125°C, and guaranteed by design and characterization over temperature, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SERIAL INTERFACE (SPI) TIMING CHARACTERISTICS (Figure 1) Minimum SCLK Low to Falling- tSC 10 ns Edge of CS Setup Time Minimum CS Low to Rising-Edge tCSS 5 ns of SCLK Setup Time Minimum SCLK Low to Rising- tHCS 20 ns Edge of CS Setup Time Minimum SCLK Low After Rising- tHS 5 ns Edge of CS Hold Time Minimum Data Valid to SCLK tDS 10 ns Rising-Edge Setup Time Minimum Data Valid to SCLK tDH 5 ns Rising-Edge Hold Time Minimum SCLK High Pulse Width tCH 40 ns Minimum SCLK Low Pulse Width tCL 40 ns Minimum CS High Pulse Width tCSH 40 ns Maximum Transition Time from CL = 10pF load capacitance from GPO to tCSG 50 ns Falling-Edge of CS to Valid GPO DGND Maximum Transition Time from CL = 10pF load capacitance from GPO to Falling-Edge of SCLK to Valid tCG 50 ns DGND GPO Note 1: Supply current and output power are greatly dependent on board layout and PAOUT match. Note 2: 50% duty cycle at 10kHz ASK data (Manchester coded). Note 3: Guaranteed by design and characterization, not production tested. Note 4: Dependent on PCB trace capacitance. CS tCSH tSC tCSS tHCS SCLK tCL tCH tDS tDH tHS SDI tCSG tCG GPO Figure 1. SPI Timing Diagram www.maximintegrated.com Maxim Integrated │ 4

MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter Typical Operating Characteristics (50Ω system impedance, VAVDD = VDVDD = VPAVDD = +2.1V to +3.6V, fRF = 300MHz to 450MHz, TA = -40°C to +125°C, unless other- wise noted. Typical values are at VAVDD = VDVDD = VPAVDD = +2.7V, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT SUPPLY CURRENT SUPPLY CURRENT vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE RENT (mA) 1111145678 PfRAF OT=A N3 =15 +M1H25z°C TA = +85°C MAX7057 toc01 RENT (mA) 1110129 5fR0F% =T DA3U 1=5T M+Y1 HC2z5Y°CCLE TA = +85°C MAX7057 toc02 RENT (mA) 4565....5005 PfRATF A O= = F3 F+1152M5H°zC TA = +85°C MAX7057 toc03 UR 13 UR UR 4.0 C C C PLY 12 TA = +25°C PLY 8 TA = +25°C PLY 3.5 TA = +25°C P P P SU 11019 TA = -40°C SU 67 TA = -40°C SU 23..50 TA = -40°C 8 5 2.0 2.1 2.4 2.7 3.0 3.3 3.6 2.1 2.4 2.7 3.0 3.3 3.6 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SUPPLY CURRENT SUPPLY CURRENT SUPPLY CURRENT vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE 111678 PfRAF O= N433.92MHz TA = +85°C MAX7057 toc04 1112 5fR0F% = D4U33T.Y9 2CMYHCzLE TA = +85°C MAX7057 toc05 76..05 PfRAF O= F4F33.92MHz MAX7057 toc06 A) A) A) 6.0 TA = +85°C RENT (m 1145 TA = +125°C RENT (m 109 TA = +125°C RENT (m 5.5 TA = +125°C UR 13 UR UR 5.0 PLY C 12 TA = +25°C PLY C 8 TA = +25°C PLY C 4.5 P P P SU 11 SU 7 SU 4.0 TA = +25°C 10 TA = -40°C TA = -40°C 9 6 3.5 TA = -40°C 8 5 3.0 2.1 2.4 2.7 3.0 3.3 3.6 2.1 2.4 2.7 3.0 3.3 3.6 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) OUTPUT POWER OUTPUT POWER SUPPLY CURRENT AND OUTPUT POWER vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE vs. EXTERNAL RESISTOR R (dBm) 111042 PfRAF TO=A N3 =1 5-M40H°zC TA = +25°C MAX7057 toc07 R (dBm) 111042 PfRAF O= N43T3A.9 =2 M-4H0z°C, +25°C MAX7057 toc08 NT (mA)111042 OUTPUT MPAOX7W057E toRc09 051150 R (dBm) OUTPUT POWE 468 TA = +125°CTA = +85°C OUTPUT POWE 468 TA = +125°C TA = +85°C SUPPLY CURRE 468 SUPPLY CURRENT ---11550 OUTPUT POWE 2 2 2 fRF = 315MHz -20 PA ON 0 0 0 -25 2.1 2.4 2.7 3.0 3.3 3.6 2.1 2.4 2.7 3.0 3.3 3.6 0.1 1 10 100 1000 10,000 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) EXTERNAL RESISTOR (Ω) www.maximintegrated.com Maxim Integrated │ 5

MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter Typical Operating Characteristics(continued) (50Ω system impedance, VAVDD = VDVDD = VPAVDD = +2.1V to +3.6V, fRF = 300MHz to 450MHz, TA = -40°C to +125°C, unless other- wise noted. Typical values are at VAVDD = VDVDD = VPAVDD = +2.7V, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT AND OUTPUT POWER SUPPLY CURRENT AND OUTPUT POWER vs. EXTERNAL RESISTOR vs. EXTERNAL RESISTOR 9 MAX7057 toc10 10 14 MAX7057 toc11 15 SUPPLY CURRENT SUPPLY CURRENT 8 5 12 10 NT (mA) 67 0 R (dBm) NT (mA)10 05 R (dBm) RE 5 -5 WE RE 8 WE SUPPLY CUR 43 OUTPUT POWER --1150 OUTPUT PO SUPPLY CUR 46 OUTPUT POWER ---11550 OUTPUT PO 2 1 fRF = 315MHz -20 2 fRF = 433.92MHz -20 50% DUTY CYCLE PA ON 0 -25 0 -25 0.1 1 10 100 1000 10,000 0.1 1 10 100 1000 10,000 EXTERNAL RESISTOR (Ω) EXTERNAL RESISTOR (Ω) SUPPLY CURRENT AND OUTPUT POWER vs. EXTERNAL RESISTOR PHASE NOISE vs. OFFSET FREQUENCY RENT (mA) 68957 SUPPLY CMUARX7R05E7 NtocT12 -05150 WER (dBm) E (dBc/Hz) ----67890000 fRF = 315MHz MAX7057 toc13 SUPPLY CUR 43 OUTPUT POWER ---112500 OUTPUT PO PHASE NOIS---111012000 2 1 fRF = 433.92MHz -25 -130 50% DUTY CYCLE 0 -30 -140 0.1 1 10 100 1000 10,000 100 1k 10k 100k 1M 10M EXTERNAL RESISTOR (Ω) OFFSET FREQUENCY (Hz) REFERENCE SPUR MAGNITUDE PHASE NOISE vs. OFFSET FREQUENCY vs. SUPPLY VOLTAGE --5600 fRF = 433.92MHz MAX7057 toc14 E (dBc) --3350 MAX7057 toc15 E (dBc/Hz) --7800 MAGNITUD -40 fRF = 433.92MHz OIS -90 UR -45 N P SE -100 E S HA NC -50 fRF = 315MHz P-110 RE E EF -55 -120 R -130 -60 100 1k 10k 100k 1M 10M 2.1 2.4 2.7 3.0 3.3 3.6 OFFSET FREQUENCY (Hz) SUPPLY VOLTAGE (V) www.maximintegrated.com Maxim Integrated │ 6

MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter Typical Operating Characteristics(continued) (50Ω system impedance, VAVDD = VDVDD = VPAVDD = +2.1V to +3.6V, fRF = 300MHz to 450MHz, TA = -40°C to +125°C, unless other- wise noted. Typical values are at VAVDD = VDVDD = VPAVDD = +2.7V, TA = +25°C, unless otherwise noted.) FREQUENCY STABILITY EFFICIENCY vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE pm) 1680 MAX7057 toc16 3305 PfRAF O= N315MHzTA = -40°C TA = +25°C MAX7057 toc17 p BILITY ( 24 fRF = 315MHz Y (%) 25 A C ST 0 EN UENCY -2 fRF = 433.92MHz EFFICI 20 TA = +85°C Q -4 E FR -6 15 TA = +125°C -8 -10 10 2.1 2.4 2.7 3.0 3.3 3.6 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) EFFICIENCY EFFICIENCY vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE 2253 5fR0F% = D3U15TMY HCzYCLE TA = -40°C TA = +25°C MAX7057 toc18 3305 PfRAF O= N433.92MTAH z= -40°C TA = +25°C MAX7057 toc19 21 %) %) Y ( 19 Y ( 25 C C N N E 17 E CI CI EFFI 15 TA = +85°C EFFI 20 TA = +85°C 13 15 TA = +125°C 11 TA = +125°C 9 10 2.1 2.4 2.7 3.0 3.3 3.6 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) EFFICIENCY vs. SUPPLY VOLTAGE FSK SPECTRUM 2213 5fR0FT% A= D=4 U3-43T0.Y9° 2CCMYHCzLE TA = +25°C MAX7057 toc20 +++12444 RVVBIBDWWE O== A1100VkkGHH zOzN MAX7057 toc21 %) 19 -6 NCY ( 17 m) -16 E B -26 FFICI 15 (d -36 E 13 -46 TA = +85°C -56 11 TA = +125°C -66 100kHz DEVIATION, 4kHz SQUARE-WAVE 9 -76 MODULATION. SPAN = 1.00MHz 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V) www.maximintegrated.com Maxim Integrated │ 7

MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter Pin Description PIN NAME FUNCTION 1 CS Serial Interface Active-Low Chip Select. Internally pulled up to DVDD. 2 SDI Serial Interface Data Input. Internally pulled down to GND. 3 SCLK Serial Interface Clock Input. Internally pulled down to GND. 4 PAGND Power Amplifier Ground Power Amplifier Output. Requires a pullup inductor to the supply voltage or ROUT. The pullup inductor can 5 PAOUT be part of the output-matching network. Envelope-Shaping Output. ROUT controls the power amplifier envelope’s rise and fall times. Connect 6 ROUT ROUT to the PA pullup inductor or to an optional power-adjust resistor. Bypass the inductor to GND as close as possible to the inductor with 680pF and 220pF capacitors. Power Amplifier Supply Voltage. Bypass to ground with 0.01µF and 220pF capacitors placed as close as 7 PAVDD possible to the pin. Analog Positive Supply Voltage. Bypass to ground with 0.1µF and 0.01µF capacitors placed as close as 8 AVDD possible to the pin. 9 XTAL2 Crystal Input 2. XTAL2 can be driven from an AC-coupled external reference. 10 XTAL1 Crystal Input 1. Bypass to ground if XTAL2 is driven from an AC-coupled external reference. 11 AGND Analog Ground Enable Pin. Drive high for normal operation; drive low or leave unconnected to put the device in standby 12 ENABLE mode. Internally pulled down to GND. ASK/FSK Data Input. Use the control register (address: 0x00) to select the type of modulation. Internally 13 DIN pulled down to GND. 14 DGND Digital Ground General-Purpose Output. Can be configured to output various digital signals (SPI serial data output—SDO, 15 GPO CLKOUT—reference oscillator frequency divided by 1, 2, 4, or 8 for microprocessor clock, etc). Digital positive supply voltage. Bypass to ground with 0.1µF and 0.01µF capacitors placed as close as 16 DVDD possible to the pin. Detailed Description a superheterodyne receiver such as the MAX1471, MAX1473, MAX7033, MAX7034, or MAX7042. The MAX7057 is frequency programmable from 300MHz to 450MHz, by using a fractional-N phase-locked loop Frequency Programming (PLL), and transmits data using either ASK or FSK mod- The MAX7057 is a crystal-referenced phased-locked ulation. The MAX7057 has integrated tuning capacitors loop (PLL) VHF/UHF transmitter that transmits data over at the output of the power amplifier (PA) to ensure high- the frequency range of 300MHz to 450MHz in ASK or power efficiency at various programmable frequencies FSK mode. The transmit frequency is set by the crystal with a single-matching network. frequency and the programmable divider in the PLL; The crystal-based architecture of the MAX7057 elimi- the programmable-divide ratios can be set anywhere nates many of the common problems with SAW trans- from 19 to 28, which means that with a crystal frequen- mitters by providing greater modulation depth, faster cy of 16MHz, the output frequency range can be from frequency settling, tighter transmit frequency tolerance, 304MHz to 448MHz. and reduced temperature dependence. In particular, The fractional-N architecture of the PLL in the MAX7057 the tighter transmit frequency tolerance means that a allows the FSK signal to be programmed for exact fre- superheterodyne receiver with a narrower IF bandwidth quency deviations and rapid, transient-free frequency (therefore lower noise bandwidth) can be used. The settling time. This modulation method completely elimi- payoff is better overall receiver performance when using www.maximintegrated.com Maxim Integrated │ 8

MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter nates the problems associated with crystal-pulling FSK Variable Capacitor signal generation. The multiplying factor of the PLL is The MAX7057 has a set of internal variable shunt capac- set by a 16-bit number, with 4 bits for integer and 12 itors that can be switched in and out to present different bits for fraction. The 12-bit fraction in the synthesizer capacitor values at the PA output. The capacitors are con- results in a tuning resolution that is equal to the refer- nected from the PA output to ground. This allows changing ence frequency divided by 4096. the tuning network along with the synthesizer divide ratio The MAX7057 has an internal variable shunt capacitor each time the transmitted frequency changes, making it connected at the PA output. This capacitor is controlled possible to maintain maximum transmitter power while using the SPI to maintain highly efficient transmission at moving rapidly from one frequency to another. any frequency within a 1.47 to 1 (28/19) tuning range. When the particular capacitance control bit is high, the This means that it is possible to change the frequency corresponding amount of shunt capacitance is added and retune the antenna to the new frequency in a at PAOUT. The 32 capacitor values are selected using very short time. The combination of rapid-antenna the SPI; the capacitance resolution is 0.25pF. The total tuning ability with rapid-synthesizer tuning makes the capacitance can vary from 0 to 7.75pF. For example, if MAX7057 a true frequency-agile transmitter. The tun- cap[1] and cap[3] are high, and cap[4], cap[2], and cap[0] ing capacitor has a resolution of 0.25pF. The MAX7057 are low, this circuit will add 2.5pF at PAOUT. See Table 1 also features adjustable output power through an exter- for variable capacitor values and control bits. nal resistor to nearly +10dBm into a 50Ω load at +2.7V. Fractional-N Phase-Locked Loop (PLL) The MAX7057 supports data rates up to 100kbps NRZ in both ASK and FSK modes. In FSK mode, the fre- The MAX7057 utilizes a fully integrated fractional-N PLL quency deviation can be programmed as low as ±2kHz for its transmit frequency synthesizer. All PLL compo- and as high as ±100kHz. nents, including the loop filter, are included on-chip. The loop bandwidth is programmable to either 300kHz or Power Amplifier (PA) 600kHz. See Tables 2, 3, and 4 for “pllbw” bit description. The PA of the MAX7057 is a high-efficiency, open-drain The 16-bit fractional-N topology allows the transmit fre- switching-mode amplifier. In a switching-mode ampli- quency to be adjusted in increments of fXTAL/4096. The fier, the gate of the final-stage FET is driven with a very allowable range of the fRF/fXTAL ratio is approximately sharp 25% duty-cycle square wave at the transmit fre- 19 to 28. quency. This square wave is derived from the synthe- The fractional-N topology also allows exact FSK fre- sizer circuit. When the matching network is tuned quency deviations to be programmed, completely correctly, the output FET resonates the attached match- eliminating the problems associated with generating ing circuit with a minimum amount of power dissipated frequency deviations by crystal oscillator pulling. in the FET. With a proper output-matching network, the The integer and fractional portions of the PLL divider PA can drive a wide range of antenna impedances, ratio set the transmit frequency. The following exam- which include a small-loop PCB trace and a 50Ω anten- ple shows how to determine the correct values to be na. The output-matching network suppresses the carr- loaded to registers HIFREQ1, HIFREQ0, LOFREQ1, and ier harmonics and transforms the antenna impedance LOFREQ0. See Tables 2, 3, and 7–10 for a detailed to an optimal impedance at PAOUT, which is from 125Ω description of these registers. to 250Ω. When the output-matching network is properly tuned, Table 1. Variable Capacitor Values and the PA transmits power with a high overall efficiency of up to 25%. The efficiency of the PA itself is more than Control Bits 39%. The output power can be adjusted by changing the impedance seen by the PA or by adjusting the SPI REGISTER BITS INCREMENTAL SHUNT CAPACITANCE (pF) value of an external resistor at PAOUT. cap[0] 0.25 Envelope Shaping cap[1] 0.5 The MAX7057 features an internal envelope-shaping cap[2] 1.0 resistor for ASK modulation, which connects between PAVDD and ROUT. When connected to the PA pullup cap[3] 2.0 inductor, the envelope-shaping resistor slows the turn- cap[4] 4.0 on/-off time of the PA and results in a smaller spectral width of the modulated PA output signal. www.maximintegrated.com Maxim Integrated │ 9

MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter Due to the nature of the transmit PLL frequency divider, 6pF between XTAL1 and XTAL2. In most cases, this a fixed offset of 16 must be subtracted from the trans- corresponds to an 8pF load capacitance applied to the mit PLL divider ratio for programming the MAX7057’s external crystal when typical PCB parasitics are added. transmit frequency registers. To determine the value to The MAX7057 is designed to operate with a typical program the MAX7057’s transmit frequency registers, 10pF load capacitance crystal. It is very important to convert the decimal value of the following equation to use a crystal with a load capacitance that is equal to the nearest hexadecimal value: the capacitance of the MAX7057 crystal oscilla- tor plus PCB parasitics and optional external load  fRF -16 × 4096 = Decimal value to program capacitors. If a crystal designed to oscillate with a dif- fXTAL  transmit frequency registers ferent load capacitance is used, the crystal is pulled away from its stated operating frequency, introducing Assume that the ASK transmit frequency = 315MHz an error in the reference frequency. A crystal designed and fXTAL = 16MHz. In this example, the rounded to operate at a higher load capacitance than the value decimal value is 15,104, or 0x3B00 hexadecimal. The specified for the oscillator is always pulled higher in upper 2 bytes (0x3B) are loaded into the LOFREQ1 frequency. Adding capacitance to increase the load register, and the low 2 bytes (0x00) are loaded into the capacitance on the crystal increases the startup time LOFREQ0 register. In ASK mode, the transmit frequen- and can prevent oscillation altogether. cy equals the lower frequency programmed into the In actuality, the oscillator pulls every crystal. The crys- MAX7057’s transmit frequency registers (see Tables 2, tal’s natural frequency is below its specified frequency, 3, and 9–12). but when loaded with the specified load capacitance, In FSK mode, the transmit frequencies equal the upper the crystal is pulled and oscillates at its specified fre- (HIFREQ1 and HIFREQ0) and lower (LOFREQ1 and quency. This pulling is already accounted for in the LOFREQ0) frequencies programmed into the MAX7057’s specification of the load capacitance. transmit frequency registers. Calculate the upper and Additional pulling can be calculated if the electrical lower frequency in the same way as shown above. FSK parameters of the crystal are known. The frequency pull- deviations as low as ±2kHz and as high as ±100kHz are ing is given by: programmable (see Tables 2, 3, and 8–12). The exact min and max values for the transmit frequen- fp=C2mCcase1+Cload−Ccase+1Cspec ×1 06 cy registers (HIFREQ1/0, LOFREQ1/0) are 2.9596 where: (0x2F42) and 12.0220 (0xC05A), yielding a synthesizer ratio of 18.9596 and 28.0220, respectively. These limits fp is the amount the crystal frequency is pulled in ppm MUST be followed to prevent the delta-sigma modula- tor from overflowing. Cm is the motional capacitance of the crystal Ccase is the case capacitance Whenever all of the fractional bits in the HIFREQ1/0 and Cspec is the specified load capacitance LOFREQ1/0 registers are zero (fhi[11:0] and flo[11:0]), Cload is the actual load capacitance only an integer divider is used, and the delta-sigma modulator is not in operation. This allows lower current When the crystal is loaded as specified (i.e., Cload = operation. The 600kHz PLL bandwidth should be used Cspec), the frequency pulling equals zero. in this mode to reduce phase noise. Communication Protocol Any change to the transmit frequency registers must be The MAX7057 registers are programmed through an SPI followed by writing a “1” to the self-reset frequency load interface. Figure 2 shows the timing diagram of the SPI. register (see Tables 2, 3, and 12). The GPO must be properly configured to act as an SPI data output (SDO) by setting the configuration 1 register Crystal (XTAL) Oscillator (see Tables 2, 3, 15, and 16). The crystal (XTAL) oscillator in the MAX7057 is The SPI operates on a byte format, according to Figure 2. designed to present a capacitance of approximately www.maximintegrated.com Maxim Integrated │ 10

MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter CS SCLK SDI D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DATA 1 DATA N Figure 2. SPI Format CS SCLK A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 SDI WRITE COMMAND (0x01) INITIAL ADDRESS (A[7:0]) DATA 0 DATA N Figure 3. SPI Write Command Format Depending on the command, byte 1 through byte N may Using a byte descriptive notation, the write command assume different functions. They may either be a direct can be viewed as the following sequence: command (write, read, read all, reset), or an address or SDI: <0x01> <Initial Address> <Data 0> <Data 1> … <Data N> data contents. The commands available in the MAX7057 SPI are described in detail below: Data 0 is then written to the register addressed by Write: The write command (0x01) is used to program <Initial Address>, Data 1 is written to <Initial Address + the MAX7057 registers (see Tables 2 and 3). The format 1>, and so on. shown in Figure 3 must be followed, allowing all the reg- isters to be programmed within one CS cycle. Read: To execute an SPI read operation, the general- purpose output (GPO) pin must be configured to either a CKOUT_SDO or SDO function (see Tables 15 and 16 for details). www.maximintegrated.com Maxim Integrated │ 11

MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter CS SCLK SDI A7 A6 A5 A4 A3 A2 A1 A0 A7 A6 A5 A4 A3 A2 A1 A0 A7 A0 ADDRESS READ COMMAND (0x02) ADDRESS 0 ADDRESS 1 N 0x00 GPO D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D0 DATA 0 DATA DATA N N - 1 Figure 4. SPI Read Command Format CS SCLK SDI A7 A6 A5 A4 A3 A2 A1 A0 READ ALL COMMAND (0x03) ADDRESS N GPO D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D0 DATA DATA DATA N N + 1 N + n Figure 5. SPI Read-All Command Format Using a byte descriptive notation, the read command Using a byte descriptive notation, the read command can be viewed as the following sequence, within the can be viewed as the following sequence, within two same CS cycle: CS cycles: SDI : <0x02> <Address 0> <Address 1> <Address2> … < A ddress N > < 0x00 > CS cycle 1 CS cycle 2 GPO: < XX >< XX >< Data 0 >< Data 1 > …< Data N - 1 >< Data N> SDI : <0x03> <Address N>< XX >< XX >< XX >…< XX > GPO: <Data N><DataN + 1><DataN + 2>…<Data N + n> With this command, all the registers can be read within the same cycle of CS. The addresses can be given in Reset: The MAX7057 can be reset to its power-up state any order. through the reset command. Read-All: To execute an SPI read-all operation, GPO must be configured to either a CKOUT_SDO or SDO function (see Tables 15 and 17 for details). www.maximintegrated.com Maxim Integrated │ 12

MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter Variable Capacitor The internal variable shunt capacitor, which is instrumen- tal in matching the PA to the antenna, is controlled by CS setting 5 bits in the configuration 0 register. This allows for 32 levels of shunt capacitance control. Since the control SCLK of these 5 bits is independent of the other settings, any capacitance value can be chosen at any frequency, mak- SDI ing it possible to maintain maximum transmitter efficiency while moving rapidly from one frequency to another. RESET COMMAND (0x04) Clock Output The MAX7057 has a buffered clock output that can serve Figure 6. Reset Command Format as a clock for a microprocessor. The divide ratio is set through the configuration 0 register (see Tables 5 and 6). Using a byte descriptive notation, the reset command The divide settings are 1 (no division), 2, 4, 8, or 16; the can be viewed as the following sequence, within the original undivided frequency is based on the reference same CS cycle: frequency generated by the external crystal. The buffered SDI: <0x04> clock output is available at GPO when enabled by setting the configuration 1 register (see Tables 2, 3, 15, and 16). Features and Settings Values and parameters are set through registers in the Mode Select and Crystal Shutdown MAX7057 that are addressable through the SPI. These The transmission mode is selected by writing to a register. registers contain bits that either turn functions on and off The default mode is ASK and the mode can be changed or program numerical settings. The following settings are to FSK by writing a 1 to the mode bit in the control reg- controlled through the SPI. ister. This register is also used to keep the crystal circuit powered up in the shutdown mode. Registers The following tables provide information on the MAX7057 registers. Table 2. Register Summary ADDRESS REGISTER NAME DESCRIPTION Control register. Controls the mode (ASK/FSK), crystal clock output, envelope-shaping, PLL 0x00 CONTRL bandwidth, and SPI enable. Configuration 0 register. Controls the capacitance at the PA output and clock output 0x01 CONFIG0 frequency divider. 0x02 HIFREQ1 High-frequency 1 register (upper byte). Sets the high frequency in FSK transmission. 0x03 HIFREQ0 High-frequency 0 register (lower byte). Sets the high frequency in FSK transmission. Low-frequency 1 register (upper byte). Sets the low frequency in FSK transmission, or 0x04 LOFREQ1 carrier frequency in ASK transmission. Low-frequency 0 register (lower byte). Sets the low frequency in FSK transmission, or carrier 0x05 LOFREQ0 frequency in ASK transmission. 0x06 FLOAD Frequency load register. Performs the frequency load function. 0x07 DATAIN Data in register. SPI equivalent of DIN pin. 0x08 EN Enable register. SPI equivalent of ENABLE pin. 0x09 CONFIG1 Configuration 1 register. GPO selector. 0x0C STATUS Status register. www.maximintegrated.com Maxim Integrated │ 13

MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter Table 3. Register Configuration DATA NAME ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 MODE CONTRL 0x00 0 0 spioffsht pllbw shape ckouts ckouton mode R/W CONFIG0 0x01 ckdiv[2] ckdiv[1] ckdiv[0] cap[4] cap[3] cap[2] cap[1] cap[0] R/W HIFREQ1 0x02 fhi[15] fhi[14] fhi[13] fhi[12] fhi[11] fhi[10] fhi[9] fhi[8] R/W HIFREQ0 0x03 fhi[7] fhi[6] fhi[5] fhi[4] fhi[3] fhi[2] fhi[1] fhi[0] R/W LOFREQ1 0x04 flo[15] flo[14] flo[13] flo[12] flo[11] flo[10] flo[9] flo[8] R/W LOFREQ0 0x05 flo[7] flo[6] flo[5] flo[4] flo[3] flo[2] flo[1] flo[0] R/W FLOAD 0x06 — — — — — — — fload R/W DATAIN 0x07 — — — — — — — datain_bit R/W EN 0x08 — — — — — — — enable_bit R/W CONFIG1 0x09 0 0 0 0 0 gposel[2] gposel[1] gposel[0] R/W STATUS 0x0C fhi/lo[15] fhi/lo[14] fhi/lo[13] fhi/lo[12] X 0 TxREADY NoXTAL R Table 4. Control Register (Address: 0x00) BIT NAME FUNCTION 0 mode ASK(0) or FSK(1) 1 ckouton Crystal clock output enable(1) on GPO output 2 ckouts Crystal clock output enable(1) while part is in shutdown mode 3 shape Disable(0) or enable(1) transmitter envelope-shaping resistor PLL bandwidth setting, low(0) = 300kHz or high(1) = 600kHz; 300kHz is recommended for fractional-N 4 pllbw and 600kHz for fixed-N 5 spioffsht Enable(0) or disable(1) SPI communication during shutdown Table 5. Configuration 0 Register (Address: 0x01) BIT NAME FUNCTION 4-0 cap[4:0] 5-bit capacitor setting 7-5 ckdiv[2:0] 3-bit clock output frequency divider www.maximintegrated.com Maxim Integrated │ 14

MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter Table 6. ckdiv[2:0] of Configuration 0 Register (Address: 0x01) DECIMAL BINARY CRYSTAL FREQUENCY DIVIDED BY 0 000 1 1 001 2 2 010 4 3 011 8 4-7 1XX 16 Table 7. High-Frequency 1 Register (Address: 0x02) BIT NAME FUNCTION 7-0 fhi[15:8] 8-bit upper byte of high-frequency divider for FSK The 4 MSBs of HIFREQ1 (fhi[15:12]) are the integer por- tion of the divider, excluding offset of 16. The 12 LSBs (fhi[11:0]) are the fractional part of the divider. Table 8. High-Frequency 0 Register (Address: 0x03) BIT NAME FUNCTION 7-0 fhi[7:0] 8-bit lower byte of high-frequency divider for FSK Table 9. Low-Frequency 1 Register (Address: 0x04) BIT NAME FUNCTION 7-0 flo[15:8] 8-bit upper byte of low-frequency divider for FSK/ASK The 4 MSBs of LOFREQ1 (flo[15:12]) are the integer portion of the divider, excluding offset of 16. The 12 LSBs (flo[11:0]) are the fractional part of the divider. Valid values for the divider are shown in Table 11. Table 10. Low-Frequency 0 Register (Address: 0x05) BIT NAME FUNCTION 7-0 flo[7:0] 8-bit lower byte of low-frequency divider for FSK/ASK Table 11. Maximum and Minimum Values for Frequency Divide DECIMAL VALUE fhi[15:12], flo[15:12] fhi[11:0], flo[11:0] 12.0220 0xC 0x05A 2.9536 0x2 0xF42 www.maximintegrated.com Maxim Integrated │ 15

MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter These values are internally summed with 16, and thus, Whenever all of the fhi[11:0] and flo[11:0] are zero, only the min and max divider becomes approximately 19 and an integer divider is used, and the delta-sigma modulator 28. These limits MUST be followed, to prevent the del- is not in operation. This allows lower current operation. ta-sigma number generator from overflowing. The 600kHz PLL bandwidth could be used in this mode to reduce phase noise. Table 12. Frequency Load Register (Address: 0x06) BIT NAME FUNCTION Effectively changes the PLL frequency to the ones written in registers 2–5. This is a self-reset bit, 0 fload and is reset to zero after the operation is completed. Table 13. Data In Register (Address: 0x07) BIT NAME FUNCTION SPI equivalent of DIN, where the transmitted data can be controlled through the SPI interface. It 0 datain_bit should be kept low (0) if only the external DIN pin is used. The external DIN pin should also be kept low (0) if the SPI datain_bit is used. Table 14. Enable Register (Address: 0x08) BIT NAME FUNCTION SPI equivalent of ENABLE. It should be kept low (0) if the external ENABLE pin is used. The external 0 enable_bit ENABLE pin should also be kept low (0) if the SPI enable_bit is used. Table 15. Configuration 1 Register (Address: 0x09) BIT NAME FUNCTION 2-0 gposel[2:0] 3-bit GPO selector 7-3 RESERVED “0” RESERVED. Set to 0 for normal operation. Table 16. General-Purpose Output Selector (gposel[2:0]) for Configuration 1 Register DECIMAL BINARY GPO DESCRIPTION Clock/SDO Output. Outputs clock when CS is high and clock output is enabled; 0 000 CKOUT_SDO outputs SDO when CS is low. 1 001 SDO SPI Serial Data Output (SDO) 2 010 CKOUT Clock Output 3 011 RESERVED RESERVED 4 100 RESERVED RESERVED 5 101 NoXTAL Internal Crystal Oscillator Status. High means oscillator is NOT in operation. Transmitter Ready Status. High means PLL is locked and MAX7057 is ready to 6 110 TxREADY transmit data. 7 111 datain_bit A copy of datain_bit www.maximintegrated.com Maxim Integrated │ 16

MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter Table 17. Status Register (Address: 0x0C) BIT NAME FUNCTION 0 NoXTAL Internal Crystal Oscillator Status. High means oscillator is not in operation. 1 TxREADY Transmitter Ready Status. High means PLL is locked and MAX7057 is ready to transmit data. 2 RESERVED “0” RESERVED. Set to 0 for normal operation. 3 X RESERVED ASK mode: Outputs flo[15:12]. 7-4 fhi/lo[15]–fhi/lo[12] FSK mode: when datain pin/bit is high, outputs fhi[15:12]; when datain pin/bit is low, outputs flo[15:12]. Applications Information antenna has an inherent loop inductance associated with it (assuming the antenna is terminated to ground). In a Output Matching to 50Ω typical application, the inductance of the loop antenna is When matched to a 50Ω system, the MAX7057’s PA is approximately 50nH to 100nH. The radiative and lossy capable of delivering +9.2dBm of output power at PAVDD impedances can be anywhere from a few tenths of an = +2.7V with a broadband match. The output of the PA ohm to 5Ω or 10Ω. is an open-drain transistor, which has internal selectable Layout Considerations shunt tuning capacitors (see the Variable Capacitor sec- tion) for impedance matching. It is connected to PAVDD A properly designed PCB is an essential part of any RF/ or ROUT through a pullup inductor for proper biasing. microwave circuit. At high-frequency inputs and outputs, The internal selectable shunt capacitors make it easy for use controlled-impedance lines and keep them as short tuning when changing the output frequency. The pullup as possible to minimize losses and radiation. At high inductor from the PA to PAVDD or ROUT serves three frequencies, trace lengths that are in the order of λ/10 or main purposes: resonating the capacitive PA output, pro- longer act as antennas, where λ is the wavelength. viding biasing for the PA, and acting as a high-frequency Keeping the traces short also reduces parasitic induc- choke to prevent RF energy from coupling onto the supply tance. Generally, 1in of PCB trace adds about 20nH of voltage. The pi network between the PA output and the parasitic inductance. The parasitic inductance can have antenna also forms a lowpass filter that provides attenua- a dramatic effect on the effective inductance of a passive tion for the higher-order harmonics. component. For example, a 0.5in trace connecting to a 100nH inductor adds an extra 10nH of inductance, or Output Matching to PCB Loop Antenna 10%. In many applications, the MAX7057 must be imped- ance-matched to a small-loop antenna. The antenna is To reduce parasitic inductance, use wider traces and usually fabricated out of a copper trace on a PCB in a a solid ground or power plane below the signal traces. rectangular, circular, or square pattern. The antenna has Using a solid ground plane can reduce the parasitic an impedance that consists of a lossy component and a inductance from approximately 20nH/in to 7nH/in. Also, radiative component. To achieve high radiating efficiency, use low-inductance connections to the ground plane, and the radiative component should be as high as possible, place decoupling capacitors as close as possible to all while minimizing the lossy component. In addition, a loop VDD pins. www.maximintegrated.com Maxim Integrated │ 17

MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter Typical Application Circuit SCLK SDI CS 2 1 VDD SDI CS 3 16 SCLK DVDD 4 C12 C13 PAGND RFOUT L1 C1 5 PAOUT MAX7057 GPO 15 GPO C3 C2 14 L2 DGND R1 6 ROUT DIN 13 DIN C5 C4 VDD ENABLE 12 ENABLE 7 11 PAVDD AGND AVDD XTAL2 XTAL1 C7 C6 8 9 10 VDD C10 C11 C9 C8 C15 Y1 C14 Component List DESIGNATION QTY DESCRIPTION 10pF ±5%, 50V C0G ceramic capacitors (0603) C1, C2 1 Murata GRM1885C1H100J 6.8pF ±5%, 50V C0G ceramic capacitor (0603) C3 1 Murata GRM1885C1H6R8J 220pF ±5%, 50V C0G ceramic capacitors (0603) C4, C7 2 Murata GRM1885C1H221J 680pF ±5%, 50V C0G ceramic capacitor (0603) C5 1 Murata GRM1885C1H681J 10nF ±10%, 50V X7R ceramic capacitors (0603) C6, C9, C12 3 Murata GRM188R71H103K 100nF ±10%, 50V X7R ceramic capacitors (0603) C8, C13 2 Murata GRM188R71H104K 100pF ±5%, 50V C0G ceramic capacitors (0603) C10, C11 2 Murata GRM1885C1H101J 4pF ±5%, 50V C0G ceramic capacitors (0603) C14, C15 2 Murata GRM1885C1H4R0C 22nH ±5% wire-wound inductor (0603) L1 1 Murata LQW18AN22NJ00 13nH ±5% wire-wound inductor (0603) L2 1 Murata LQW18AN13NJ00 R1 1 0Ω resistor (0603) 16MHz crystal Y1 1 Crystek 17466, Suntsu SCX284 www.maximintegrated.com Maxim Integrated │ 18

MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter Functional Diagram SCLK SDI CS DVDD 3 2 1 16 MAX7057 14 DGND SERIAL INTERFACE AND DIGITAL CONTROL 13 DIN PAGND 4 12 ENABLE DELTA-SIGMA MODULATOR FREQUENCY 15 GPO DIVIDER PAOUT 5 PA VCO PFD ROUT 6 ENVELOPE LOOP CHARGE CRYSTAL 11 AGND SHAPING FILTER PUMP OSCILLATOR 7 8 9 10 PAVDD AVDD XTAL2 XTAL1 Chip Information Package Information PROCESS: CMOS For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE PACKAGE LAND OUTLINE NO. TYPE CODE PATTERN NO. 16 SO S16+3 21-0041 90-0097 www.maximintegrated.com Maxim Integrated │ 19

MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter Revision History REVISION REVISION PAGES DESCRIPTION NUMBER DATE CHANGED 0 5/08 Initial release — Added reflow soldering information to Absolute Maximum Ratings, added bandwidth 1 4/11 2, 7, 11 notation to TOC21, and corrected SPI format in Figure 2 2 7/14 Removed automotive reference from data sheet 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2014 Maxim Integrated Products, Inc. │ 20

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