MAX7034 315MHz/434MHz ASK Superheterodyne Receiver General Description Features The MAX7034 fully integrated low-power CMOS super- ● Optimized for 315MHz or 433.92MHz Band heterodyne receiver is ideal for receiving amplitude-shift- ● Operates from Single +3.3V/+5.0V Supply keyed (ASK) data in the 300MHz to 450MHz frequency ● Selectable Image-Rejection Center Frequency range (including the popular 315MHz and 433.92MHz fre- quencies). The receiver has an RF sensitivity of -114dBm. ● Selectable x64 or x32 fLO/fXTAL Ratio With few external components and a low-current power- ● Low (< 6.7mA) Operating Supply Current down mode, it is ideal for cost-sensitive and power-sensi- ● < 3.0μA Low-Current Power-Down Mode for Efficient tive applications typical in the automotive and consumer Power Cycling markets. The MAX7034 consists of a low-noise amplifier (LNA), a fully differential image-rejection mixer, an on- ● 250μs Startup Time chip phase-locked loop (PLL) with integrated voltage- ● Built-In 44dB RF Image Rejection controlled oscillator (VCO), a 10.7MHz IF limiting amplifier ● Excellent Receive Sensitivity Over Temperature stage with received-signal-strength indicator (RSSI), and analog baseband data-recovery circuitry. ● -40°C to +125°C Operation The MAX7034 is available in a 28-pin (9.7mm x 4.4mm) ● -40°C to +105°C Operation (3.0V to 3.6V Supply) TSSOP package and is specified over the automotive (-40°C to +125°C) temperature range. Ordering Information and Typical Application Circuit appear at end of data sheet. Applications ● Automotive Remote ● Home Automation Keyless Entry ● Remote Controls ● Security Systems ● Local Telemetry Pin Configuration ● Garage Door Openers ● Wireless Sensors TOP VIEW + XTAL1 1 28 XTAL2 AVDD 2 27 SHDN LNAIN 3 26 PDOUT LNASRC 4 25 DATAOUT AGND 5 24 VDD5 MAX7034 LNAOUT 6 23 DSP AVDD 7 22 DFFB MIXIN1 8 21 OPP MIXIN2 9 20 DSN AGND 10 19 DFO IRSEL 11 18 IFIN2 MIXOUT 12 17 IFIN1 DGND 13 16 XTALSEL DVDD 14 15 EN_REG TSSOP 19-3109; Rev 4; 11/16

MAX7034 315MHz/434MHz ASK Superheterodyne Receiver Absolute Maximum Ratings VDD5 to AGND .....................................................-0.3V to +6.0V Continuous Power Dissipation (TA = +70°C) AVDD to AGND ....................................................-0.3V to +4.0V 28-Pin TSSOP (derate 12.8mW/°C above +70°C) ..1025.6mW DVDD to DGND ....................................................-0.3V to +4.0V Operating Temperature Range .........................-40°C to +125°C AGND to DGND ...................................................-0.1V to +0.1V Storage Temperature Range ............................-65°C to +150°C IRSEL, DATAOUT, XTALSEL, Junction Temperature ......................................................+150°C SHDN, EN_REG to AGND .................-0.3V to (VDD5 + 0.3V) Lead Temperature (soldering, 10s) .................................+300°C All Other Pins to AGND ........................-0.3V to (VDVDD + 0.3V) Soldering Temperature (reflow) .......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (Typical Application Circuit, VDD5 = +4.5V to +5.5V, no RF signal applied. TA = -40°C to +125°C, unless otherwise noted. Typical values are at VDD5 = +5.0V and TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VDD5 +5.0V nominal supply voltage 4.5 5.0 5.5 V fRF = 315MHz 6.7 8.2 Supply Current IDD VSHDN = VDD5 mA fRF = 433MHz 7.2 8.7 Shutdown Supply Current ISHDN VSHDN = 0V 3 8 µA Input-Voltage Low VIL 0.4 V EN_REG, SHDN VDD5 - 0.4 Input-Voltage High VIH V XTALSEL VDVDD - 0.4 Input Logic Current High IIH 15 µA fRF = 433MHz, VIRSEL = VDVDD V-D 0V.D4D Image-Reject Select Voltage (Note 2) fRF = 375MHz, VIRSEL = VDVDD/2 1.1 V-D 1V.D5D V fRF = 315MHz, VIRSEL = 0V 0.4 DATAOUT Voltage-Output Low VOL ISINK = 10µA 0.125 V DATAOUT Voltage-Output High VOH ISOURCE = 10µA V0D.1D255 - V www.maximintegrated.com Maxim Integrated │ 2

MAX7034 315MHz/434MHz ASK Superheterodyne Receiver AC Electrical Characteristics (Typical Application Circuit, VDD5 = +4.5V to +5.5V, all RF inputs are referenced to 50Ω, fRF = 433.92MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VDD5 = +5.0V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS GENERAL CHARACTERISTICS Time for valid signal detection after VSHDN Startup Time tON = VDD5. Does not include baseband filter 250 µs settling. Receiver Input Frequency Range fRF 300 450 MHz Maximum Receiver Input Level 0 dBm 315MHz -114 Sensitivity at TA = +25°C (Note 3) dBm 434MHz -113 Sensitivity at TA = +125°C 315MHz -113 dBm (Note 3) 434MHz -110 Manchester coded 33 Maximum Data Rate kbps NRZ coded 66 LNA/MIXER LNA/Mixer Voltage Gain (Note 4) 330Ω IF filter load 45 dB LNA/Mixer Input-Referred 1dB -50 dBm Compression Point Mixer Output Impedance ZOUT_MIX 330 Ω fRF = 434MHz, VIRSEL = VDVDD 42 Mixer Image Rejection fRF = 375MHz, VIRSEL = VDVDD/2 44 dB fRF = 315MHz, VIRSEL = 0V 44 INTERMEDIATE FREQUENCY (IF) Input Impedance ZIN_IF 330 Ω Operating Frequency fIF Bandpass response 10.7 MHz 3dB Bandwidth 10 MHz RSSI Linearity ±0.5 dB RSSI Dynamic Range 80 dB PRFIN < -120dBm 1.15 RSSI Level V PRFIN > -40dBm 2.2 www.maximintegrated.com Maxim Integrated │ 3

MAX7034 315MHz/434MHz ASK Superheterodyne Receiver AC Electrical Characteristics (continued) (Typical Application Circuit, VDD5 = +4.5V to +5.5V, all RF inputs are referenced to 50Ω, fRF = 433.92MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VDD5 = +5.0V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DATA FILTER Maximum Bandwidth 50 kHz DATA SLICER Comparator Bandwidth 100 kHz Output High Voltage VDD5 V Output Low Voltage 0 V CRYSTAL OSCILLATOR VXTALSEL = 0V 6.6128 fRF = 433.92MHz VXTALSEL = VDVDD 13.2256 Crystal Frequency (Note 5) fXTAL MHz VXTALSEL = 0V 4.7547 fRF = 315MHz VXTALSEL = VDVDD 9.5094 Crystal Tolerance 50 ppm Input Capacitance From each pin to ground 6.2 pF Maximum Load Capacitance CLOAD 10 pF Note 1: 100% tested at TA = +125°C. Guaranteed by design and characterization over entire temperature range. Note 2: IRSEL is internally set to 375MHz IR mode. It can be left open when the 375MHz image-rejection setting is desired. Bypass to AGND with a 1nF capacitor in a noisy environment. Note 3: Peak power level. BER = 2 x 10-3, Manchester encoded, data rate = 4kbps, IF bandwidth = 280kHz. Note 4: The voltage conversion gain is measured with the LNA input matching inductor and the LNA/Mixer resonator in place, and does not include the IF filter insertion loss. Note 5: Crystal oscillator frequency for other RF carrier frequency within the 300MHz to 450MHz range is (fRF - 10.7MHz)/64 for XTALSEL = 0V, and (fRF - 10.7MHz)/32 for XTALSEL = VDVDD. www.maximintegrated.com Maxim Integrated │ 4

MAX7034 315MHz/434MHz ASK Superheterodyne Receiver Typical Operating Characteristics (Typical Application Circuit, VDD5 = +5.0V, fRF = 433.92MHz, TA = +25°C, unless otherwise noted.) BIT-ERROR RATE SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. RF FREQUENCY vs. PEAK RF INPUT POWER 77..68 MAX7034 toc01 89..50 +125°C +85°C +105°C MAX7034 toc02 100.00 433.92MHz MAX7034 toc03 mA) mA) 8.0 %)10.00 NT ( 7.4 +125°C NT ( 7.5 TE ( E +105°C E A R +85°C R R SUPPLY CUR 77..02 +25°C -40°C SUPPLY CUR 667...050 +25°C BIT-ERROR 01..1000 315MHz 6.8 5.5 -40°C 6.6 5.0 0.01 4.5 4.7 4.9 5.1 5.3 5.5 250 300 350 400 450 500 -130 -125 -120 -115 -110 SUPPLY VOLTAGE (V) RF FREQUENCY (MHz) PEAK RF INPUT POWER (dBm) SENSITIVITY vs. TEMPERATURE RSSI vs. RF INPUT POWER RSSI AND DELTA vs. IF INPUT POWER ---111000642 MAX7034 toc04 22..2400 IF BANDWIDTH = 280kHz MAX7034 toc05 22..2400 RSMSAIX7034 toc06 1105 5 m)-108 433.92MHz 2.00 2.00 dB 0 Y (-110 315MHz V)1.80 V)1.80 A NSITIVIT-112 RSSI (1.60 RSSI (1.60 DELTA --150DELT E-114 S 1.40 1.40 -15 -116 -118 1.20 1.20 -20 -120 1.00 1.00 -25 -40 -15 10 35 60 85 110 -140 -120 -100 -80 -60 -40 -20 0 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 TEMPERATURE (°C) RF INPUT POWER (dBm) IF INPUT POWER (dBm) LNA/MIXER VOLTAGE GAIN vs. IF FREQUENCY IMAGE REJECTION vs. RF FREQUENCY IMAGE REJECTION vs. TEMPERATURE dB) 5655 UPPER SIDEBAND MAX7034 toc07 5600 fRF = 315MHz MAX7034 toc08 5502 MAX7034 toc09 E GAIN ( 45 49.7dB ON (dB) 40 ON (dB) 48 315MHz VOLTAG 2355 REIJMEACGTEION REJECTI 30 REJECTI 46 MIXER 15 MAGE 20 fRF = 433.92MHz MAGE 44 433.92MHz NA/ LOWER SIDEBAND I I L 5 10 42 -5 0 40 0 5 10 15 20 25 30 280 300 320 340 360 380 400 420 440 460 480 -40 -15 10 35 60 85 110 IF FREQUENCY (MHz) RF FREQUENCY (MHz) TEMPERATURE (°C) www.maximintegrated.com Maxim Integrated │ 5

MAX7034 315MHz/434MHz ASK Superheterodyne Receiver Typical Operating Characteristics (continued) (Typical Application Circuit, VDD5 = +5.0V, fRF = 433.92MHz, TA = +25°C, unless otherwise noted.) NORMALIZED IF GAIN S11 MAGNITUDE PLOT OF RFIN vs. IF FREQUENCY vs. FREQUENCY B) 05 MAX7034 toc10 345000 MAX7034 toc11 S11 SMITH5 0C0HMAHRzT PLOT OF MRAXF70I3N4 toc12 F GAIN (d -1-05 UDE (dB) 1200 WMAITTHC IHNIPNUGT ALIZED I -15 MAGNIT-100 315MHz NORM -20 S 11-20 3-2145.M1dHBz 200MHz -30 -25 -40 -30 -50 1 10 100 200 230 260 290 320 350 380 410 440 470 500 IF FREQUENCY (MHz) FREQUENCY (MHz) PHASE NOISE PHASE NOISE vs. OFFSET FREQUENCY vs. OFFSET FREQUENCY -200 fRF = 315MHz MAX7033 toc13 -200 fRF = 433.92MHz MAX7033 toc14 Hz) -40 Hz) -40 Bc/ Bc/ d d E ( -60 E ( -60 S S OI OI E N -80 E N -80 S S A A H H P-100 P-100 -120 -120 -140 -140 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (Hz) OFFSET FREQUENCY (Hz) Pin Description PIN NAME FUNCTION 1 XTAL1 Crystal Input 1 Positive Analog Supply Voltage. For +5V operation, pin 2 is the output of an on-chip +3.4V low- dropout regulator, and should be bypassed to AGND with a 0.1µF capacitor as close as possible to 2, 7 AVDD the pin. Pin 7 must be externally connected to the supply from pin 2, and bypassed to AGND with a 0.01µF capacitor as close as possible to the pin (see the Voltage Regulator section and the Typical Application Circuit). 3 LNAIN Low-Noise Amplifier Input. See the Low-Noise Amplifier section. www.maximintegrated.com Maxim Integrated │ 6

MAX7034 315MHz/434MHz ASK Superheterodyne Receiver Pin Description (continued) PIN NAME FUNCTION Low-Noise Amplifier Source for external Inductive Degeneration. Connect inductor to ground to set 4 LNASRC LNA input impedance. See the Low-Noise Amplifier section. 5, 10 AGND Analog Ground Low-Noise Amplifier Output. Connect to mixer input through an LC tank filter. See the Low-Noise 6 LNAOUT Amplifier section. 1st Differential Mixer Input. Connect to LC tank filter from LNAOUT through a 100pF capacitor. See 8 MIXIN1 the Typical Application Circuit. 9 MIXIN2 2nd Differential Mixer Input. Connect to VDD3 side of the LC tank filter through a 100pF capacitor. See the Typical Application Circuit. Image-Rejection Select. Set VIRSEL = 0V to center image rejection at 315MHz. Leave IRSEL 11 IRSEL unconnected to center image rejection at 375MHz. Set VIRSEL = DVDD to center image rejection at 434MHz. See the Mixer section. 12 MIXOUT 330Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter. 13 DGND Digital Ground Positive Digital Supply Voltage. Connect to both of the AVDD pins. Bypass to DGND with a 0.01µF 14 DVDD capacitor as close as possible to the pin (see the Typical Application Circuit). 15 EN_REG Regulator Enable. Connect to VDD5 to enable internal regulator. Pull this pin low to allow device operation between +3.0V and +3.6V. See the Voltage Regulator section. 16 XTALSEL Crystal Divider Ratio Select. Drive XTALSEL low to select fLO/fXTAL ratio of 64, or drive XTALSEL high to select fLO/fXTAL ratio of 32. 1st Differential Intermediate-Frequency Limiter Amplifier Input. Connect to the output of a 10.7MHz 17 IFIN1 bandpass filter. 2nd Differential Intermediate-Frequency Limiter Amplifier Input. Bypass to AGND with a 1500pF 18 IFIN2 capacitor as close as possible to the pin. 19 DFO Data Filter Output 20 DSN Negative Data Slicer Input 21 OPP Noninverting Op-Amp Input for the Sallen-Key Data Filter 22 DFFB Data Filter Feedback Node. Input for the feedback of the Sallen-Key data filter. 23 DSP Positive Data Slicer Input +5V Supply Voltage. Bypass to AGND with a 0.01µF capacitor as close as possible to the pin. For +5V 24 VDD5 operation, VDD5 is the input to an on-chip voltage regulator whose +3.4V output appears at AVDD pin 2. (see the Voltage Regulator section and the Typical Application Circuit). 25 DATAOUT Digital Baseband Data Output 26 PDOUT Peak-Detector Output Power-Down Select Input. Drive high to power up the IC. Internally pulled down to AGND with a 27 SHDN 100kΩ resistor. 28 XTAL2 Crystal Input 2. Can also be driven with an external reference oscillator. See the Crystal Oscillator section. www.maximintegrated.com Maxim Integrated │ 7

MAX7034 315MHz/434MHz ASK Superheterodyne Receiver Functional Diagram LNASRC EN_REGLNAOUT MIXIN1 MIXIN2 IRSEL MIXOUT IFIN1 IFIN2 4 15 6 8 9 11 12 17 18 0˚ IF LIMITING 3 LNAIN LNA Q AMPS IMAGE REJECTION 2 AVDD 90˚ VDD5 24 3.4V REG I MAX7034 RSSI AVDD 7 DIVIDE DATA DVDD 14 BY 64 VCO FILTER RDF2 RDF1 100kΩ 100kΩ 13 PHASE LOOP DGND DETECTOR FILTER DATA AGND 5, 10 1 CRYSTAL POWER- SLICER 2 DRIVER DOWN 16 1 28 27 25 20 23 19 26 21 22 XTALSEL XTAL1 XTAL2 SHDN DATAOUT DSN DSP DFO PDOUT OPP DFFB Detailed Description Low-Noise Amplifier The MAX7034 CMOS superheterodyne receiver and a few The LNA is an nMOS cascode amplifier with off-chip external components provide the complete receive chain inductive degeneration. The gain and noise figures are from the antenna to the digital output data. Depending on dependent on both the antenna matching network at the signal power and component selection, data rates can be LNA input and the LC tank network between the LNA out- as high as 33kbps Manchester (66kbps NRZ). put and the mixer inputs. The MAX7034 is designed to receive binary ASK data The off-chip inductive degeneration is achieved by con- modulated in the 300MHz to 450MHz frequency range. necting an inductor from LNASRC to AGND. This inductor ASK modulation uses a difference in amplitude of the car- sets the real part of the input impedance at LNAIN, allow- rier to represent logic 0 and logic 1 data. ing for a more flexible input impedance match, such as a typical printed-circuit board (PCB) trace antenna. A nomi- Voltage Regulator nal value for this inductor with a 50Ω input impedance is For operation with a single +4.5V to +5.5V supply voltage, 15nH, but is affected by the PCB trace. connect VDD5 and the EN_REG pin to the supply voltage. The LC tank filter connected to LNAOUT comprises L1 An on-chip voltage regulator drives one of the AVDD pins and C9 (see the Typical Application Circuit). Select L1 (pin 2) to approximately +3.4V. For proper operation, and C9 to resonate at the desired RF input frequency. The DVDD and both AVDD pins must be connected together. resonant frequency is given by: For operation with a single +3.0V to +3.6V supply voltage, connect both the AVDD pins, DVDD, and VDD5 to the sup- 1 f = ply voltage and connect the EN_REG pin to ground (which RF 2π L × C TOTAL TOTAL disables the internal voltage regulator). If the MAX7034 is powered from +3.0V to +3.6V, the performance is limited where: to the -40°C to +105°C range. LTOTAL = L1 + LPARASITICS. In either supply voltage mode, bypass VDD5, DVDD, and CTOTAL = C9 + CPARASITICS. the pin 7 AVDD pin to AGND with 0.01μF capacitors, and the pin 2 AVDD to AGND with a 0.1μF capacitor, all placed as close as possible to the pins. www.maximintegrated.com Maxim Integrated │ 8

MAX7034 315MHz/434MHz ASK Superheterodyne Receiver LPARASITICS and CPARASITICS include inductance and Intermediate Frequency and RSSI capacitance of the PCB traces, package pins, mixer input The IF section presents a differential 330Ω load to provide impedance, etc. These parasitics at high frequencies can- matching for the off-chip ceramic filter. The six internal not be ignored, and can have a dramatic effect on the tank AC-coupled limiting amplifiers produce an overall gain of filter center frequency. The total parasitic capacitance is approximately 65dB, with a bandpass-filter-type response generally between 4pF and 6pF. centered near the 10.7MHz IF frequency with a 3dB band- width of approximately 10MHz. The RSSI circuit demodu- Mixer lates the IF by producing a DC output proportional to the A unique feature of the MAX7034 is the integrated image log of the IF signal level, with a slope of approximately rejection of the mixer. This device eliminates the need 14.2mV/dB. for a costly front-end SAW filter for most applications. Advantages of not using a SAW filter are increased sen- Applications Information sitivity, simplified antenna matching, less board space, and lower cost. Crystal Oscillator The mixer cell is a pair of double balanced mixers that The crystal oscillator in the MAX7034 is designed to perform an IQ downconversion of the RF input to the present a capacitance of approximately 3pF between the 10.7MHz IF from a low-side injected LO (i.e., fLO = fRF XTAL1 and XTAL2. If a crystal designed to oscillate with - fIF). The image-rejection circuit then combines these a different load capacitance is used, the crystal is pulled signals to achieve 44dB of image rejection. Low-side away from its intended operating frequency, introducing injection is required due to the on-chip image-rejection an error in the reference frequency. Crystals designed to architecture. The IF output is driven by a source follower operate with higher differential load capacitance always biased to create a driving-point impedance of 330Ω; this pull the reference frequency higher. For example, a provides a good match to the off-chip 330Ω ceramic 4.7547MHz crystal designed to operate with a 10pF load IF filter. capacitance oscillates at 4.7563MHz with the MAX7034, causing the receiver to be tuned to 315.1MHz rather than The IRSEL pin is a logic input that selects one of the 315.0MHz, an error of about 100kHz, or 320ppm. It is three possible image-rejection frequencies. When VIRSEL very important to use a crystal with a load capaci- = 0V, the image rejection is tuned to 315MHz. VIRSEL tance that is equal to the capacitance of the MAX7034 = VDVDD/2 tunes the image rejection to 375MHz, and crystal oscillator plus PCB parasitics. VIRSEL = VDVDD tunes the image rejection to 434MHz. The IRSEL pin is internally set to VDVDD/2 (image rejec- In actuality, the oscillator pulls every crystal. The crystal’s tion at 375MHz) when it is left unconnected, thereby elimi- natural frequency is really below its specified frequency, nating the need for an external VDVDD/2 voltage. but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. Phase-Locked Loop This pulling is already accounted for in the specification of The PLL block contains a phase detector, charge pump, the load capacitance. Additional pulling can be calculated integrated loop filter, VCO, asynchronous 64x clock if the electrical parameters of the crystal are known. The divider, and crystal oscillator driver. Besides the crystal, frequency pulling is given by: this PLL does not require any external components. The VCO generates a low-side LO. The relationship between fP =CM 1 - 1 ×106 the RF, IF, and crystal frequencies is given by: 2 CCASE+CLOAD CCASE+CSPEC where: f - f f XTAL = R32F × M IF fP is the amount the crystal frequency pulled in ppm. where: CM is the motional capacitance of the crystal. M = 1 (VXTALSEL = VDVDD) or 2 (VXTALSEL = 0V) CCASE is the case capacitance. To allow the smallest possible IF bandwidth (for best sen- CSPEC is the specified load capacitance. sitivity), minimize the tolerance of the reference crystal. CLOAD is the actual load capacitance. When the crystal is loaded as specified (i.e., CLOAD = CSPEC), the frequency pulling equals zero. www.maximintegrated.com Maxim Integrated │ 9

MAX7034 315MHz/434MHz ASK Superheterodyne Receiver It is possible to use an external reference oscillator in voltage. One input is supplied by the data filter output. Both place of a crystal to drive the VCO. AC-couple the exter- comparator inputs are accessible off-chip to allow for dif- nal oscillator to XTAL2 with a 1000pF capacitor. Drive ferent methods of generating the slicing threshold, which is XTAL2 with a signal level of approximately 500mVP-P. applied to the second comparator input. AC-couple XTAL1 to ground with a 1000pF capacitor. The suggested data slicer configuration uses a resistor (R1) connected between DSN and DSP with a capacitor Data Filter (C8) from DSN to DGND (Figure 2). This configuration The data filter is implemented as a 2nd-order lowpass averages the analog output of the filter and sets the Sallen-Key filter. The pole locations are set by the threshold to approximately 50% of that amplitude. With combination of two on-chip resistors and two external this configuration, the threshold automatically adjusts as capacitors. Adjusting the value of the external capacitors the analog signal varies, minimizing the possibility for changes the corner frequency to optimize for different errors in the digital data. The values of R1 and C8 affect data rates. The corner frequency should be set to approxi- how fast the threshold tracks to the analog amplitude. Be mately 1.5 times the fastest expected data rate from the sure to keep the corner frequency of the RC circuit much transmitter. Keeping the corner frequency near the data lower than the lowest expected data rate. rate rejects any noise at higher frequencies, resulting in an increase in receiver sensitivity. Note that a long string of zeros or ones can cause the threshold to drift. This configuration works best if a coding The configuration shown in Figure 1 can create a scheme, such as Manchester coding, which has an equal Butterworth or Bessel response. The Butterworth filter number of zeros and ones, is used. offers a very flat amplitude response in the passband and a rolloff rate of 40dB/decade for the two-pole filter. The To prevent continuous toggling of DATAOUT in the Bessel filter has a linear phase response, which works absence of an RF signal due to noise, add hysteresis to well for filtering digital data. To calculate the value of C7 the data slicer as shown in Figure 3. and C6, use the following equations, along with the coef- ficients in Table 1: Table 1. Coefficents to Calculate C7 and C6 b FILTER TYPE a b C7 = a(100k)(π)(f ) Butterworth (Q = 0.707) 1.414 1.000 C a Bessel (Q = 0.577) 1.3617 0.618 C6 = 4(100k)(π)(f ) C where fC is the desired 3dB corner frequency. For example, to choose a Butterworth filter response with a corner frequency of 5kHz: MAX7034 1.000 C7 = ≈450pF RSSI (1.414)(100kΩ)(3.14)(5kHz) 1.414 RDF2 RDF1 C6 = ≈225pF 100kΩ 100kΩ (4)(100kΩ)(3.14)(5kHz) Choosing standard capacitor values changes C7 to 470pF 19 21 22 DFO OPP DFFB and C6 to 220pF, as shown in the Typical Application Circuit. C6 C7 Data Slicer The data slicer takes the analog output of the data filter and converts it to a digital signal. This is achieved by using a comparator and comparing the analog input to a threshold Figure 1. Sallen-Key Lowpass Data Filter www.maximintegrated.com Maxim Integrated │ 10

MAX7034 315MHz/434MHz ASK Superheterodyne Receiver Peak Detector The peak-detector output (PDOUT), in conjunction with an external RC filter, creates a DC output voltage equal to the MAX7034 peak value of the data signal. The resistor provides a path for the capacitor to discharge, allowing the peak detector to dynamically follow peak changes of the data-filter output DATA voltage. For faster data slicer response, use the circuit SLICER shown in Figure 4. For more details on hysteresis and peak-detector applications, refer to Maxim Application Note 25 20 23 19 3671, Data Slicing Techniques for UHF ASK Receivers. DATAOUT DSN DSP DFO Layout Considerations R1 A properly designed PCB is an essential part of any RF/ C8 microwave circuit. On high-frequency inputs and outputs, use controlled-impedance lines and keep them as short as possible to minimize losses and radiation. At high Figure 2. Generating Data Slicer Threshold frequencies, trace lengths that are on the order of λ/10 or longer act as antennas. Keeping the traces short also reduces parasitic induc- tance. Generally, 1 inch of a PCB trace adds about 20nH MAX7034 of parasitic inductance. The parasitic inductance can have a dramatic effect on the effective inductance of a passive DATA component. For example, a 0.5 inch trace connecting a SLICER 100nH inductor adds an extra 10nH of inductance or 10%. To reduce the parasitic inductance, use wider traces and 25 23 20 19 a solid ground or power plane below the signal traces. DATAOUT DSP DSN DFO R1 Also, use low-inductance connections to ground on all R2 GND pins, and place decoupling capacitors close to all R3 power-supply pins. Control Interface Considerations R* *OPTIONAL C8 When operating the MAX7034 with a +4.5V to +5.5V supply voltage, the SHDN pin can be driven by a micro- controller with either +3.0V or +5V interface logic levels. Figure 3. Generating Data Slicer Hysteresis When operating the MAX7034 with a +3.0V to +3.6V sup- ply, only +3.0V logic from the microcontroller is allowed. MAX7034 DATA SLICER 25 20 23 19 26 DATAOUT DSN DSP DFO PDOUT 25kΩ 47nF Figure 4. Using PDOUT for Faster Startup www.maximintegrated.com Maxim Integrated │ 11

MAX7034 315MHz/434MHz ASK Superheterodyne Receiver Typical Application Circuit IF VDD IS THEN VDD3 IS AND EN_REG IS 3.0V TO 3.6V CONNECTED TO VDD GROUNDED CREATED BY LDO, 4.5V TO 5.5V AVAILABLE AT AVDD CONNECTED TO VDD (PIN 2) VDD3 VDD (SEE TABLE) X1 C11 C13 C12 1 28 XTAL1 XTAL2 RF INPUT TO/FROM µP 2 27 AVDD SHDN POWER-DOWN C1 L1 DATA OUT 3 26 LNAIN PDOUT L2 R2 4 25 LNASRC DATAOUT C15 5 24 AGND MAX7034 VDD5 R3 6 23 VDD3 C14 LNAOUT DSP L3 7 22 AVDD DFFB C3 C2 8 21 MIXIN1 OPP C7 9 20 MIXIN2 DSN C4 10 19 C9 AGND DFO VDD 11 18 IRSEL IFIN2 12 17 R1 MIXOUT IFIN1 ** 13 16 DGND XTALSEL 14 15 DVDD EN_REG C5 C6 C8 *** * Y1 C10 IF FILTER IN OUT GND COMPONENT VALUES IN TABLE 2 ***SEE THE MIXER SECTION. *SEE THE PHASE-LOCKED **SEE THE VOLTAGE LOOP SECTION. REGULATOR SECTION. www.maximintegrated.com Maxim Integrated │ 12

MAX7034 315MHz/434MHz ASK Superheterodyne Receiver Table 2. Component Values for Typical Application Circuit VALUE FOR VALUE FOR COMPONENT DESCRIPTION fRF = 433MHz fRF = 315MHz C1 100pF 100pF 5% C2 Open Open ±0.1pF C3 100pF 100pF 5% C4 100pF 100pF 5% C5 1500pF 1500pF 10% C6 220pF 220pF 5% C7 470pF 470pF 5% C8 0.47µF 0.47µF 20% C9 220pF 220pF 10% C10 0.01µF 0.01µF 20% C11 0.1µF 0.1µF 20% C12 100pF 100pF 5% C13 100pF 100pF 5% C14 0.01µF 0.01µF 20% C15 0.01µF 0.01µF 20% L1 56nH 120nH 5% or better** L2 15nH 15nH 5% or better** L3 27nH 51nH 5% or better** R1 5.1kΩ 5.1kΩ 5% R2 Open Open — R3 0Ω 0Ω — X1 (÷64) 6.6128MHz* 4.7547MHz* NDK or Suntsu X1 (÷32) 13.2256MHz* 9.5094MHz* NDK or Suntsu Y1 10.7MHz ceramic filter 10.7MHz ceramic filter Murata *Crystal frequencies shown are for ÷64 (VXTALSEL = 0V) and ÷32 (VXTALSEL = VDD). **Wire wound recommended. Chip Information Ordering Information PROCESS: CMOS PART TEMP RANGE PIN-PACKAGE MAX7034AUI/V+T -40°C to +125°C 28 TSSOP Package Information /V denotes an automotive qualified part. For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note +Denotes a lead(Pb)-free/RoHS-compliant package. that a “+”, “#”, or “-” in the package code indicates RoHS status T = Tape and reel. only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE PACKAGE OUTLINE LAND TYPE CODE NO. PATTERN NO. 28 TSSOP U28+1 21-0066 90-0171 www.maximintegrated.com Maxim Integrated │ 13

MAX7034 315MHz/434MHz ASK Superheterodyne Receiver Revision History REVISION REVISION PAGES DESCRIPTION NUMBER DATE CHANGED 0 1/08 Initial release — 1 3/09 Added /V designation to part number. 1 Updated Pin Description, Functional Diagram, Voltage Regulator section, Typical Application 2 5/11 7, 8, 11, 12, 13 Circuit, and Package Information; added Control Interface Considerations section Updated capacitors in Data Filter section; updated Table 1 to reflect correct capacitor; updated 3 6/12 10, 11, 13 Figures 1, 2, 3; updated Table 2 component values and wire wound recommendation 4 11/16 Updated Electrical Characteristics table 1, 3, 4 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2016 Maxim Integrated Products, Inc. │ 14

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