19-1387; Rev 2; 10/05 +2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin µMAX General Description Features M The MAX144/MAX145 low-power, 12-bit analog-to- ♦ Single-Supply Operation (+2.7V to +5.25V) A digital converters (ADCs) are available in 8-pin µMAX® and DIP packages. Both devices operate with a single ♦ Two Single-Ended Channels (MAX144) One X +2.7V to +5.25V supply and feature a 7.4µs succes- Pseudo-Differential Channel (MAX145) 1 sive-approximation ADC, automatic power-down, fast ♦ Low Power 4 wake-up (2.5µs), an on-chip clock, and a high-speed, 0.9mA (108ksps, +3V Supply) 4 3-wire serial interface. 100µA (10ksps, +3V Supply) / Power consumption is only 3.2mW (VDD= +3.6V) at the 10µA (1ksps, +3V Supply) M maximum sampling rate of 108ksps. At slower through- 0.2µA (Power-Down Mode) A put rates, the automatic shutdown (0.2µA) further reduces power consumption. ♦ Internal Track/Hold X The MAX144 provides 2-channel, single-ended opera- ♦ 108ksps Sampling Rate 1 tion and accepts input signals from 0 to VREF. The ♦ SPI/QSPI/MICROWIRE-Compatible 3-Wire Serial 4 MAX145 accepts pseudo-differential inputs ranging 5 Interface from 0 to VREF. An external clock accesses data- through the 3-wire serial interface, which is SPI™, ♦ Space-Saving 8-Pin µMAX Package QSPI™, and MICROWIRE™-compatible. ♦ Pin-Compatible 10-Bit Versions Available Excellent dynamic performance and low power, com- bined with ease of use and small package size, make Ordering Information these converters ideal for battery-powered and data- acquisition applications, or for other circuits with TEMP PIN- INL PKG demanding power-consumption and space require- PART RANGE PACKAGE (LSB) CODE ments. For pin-compatible 10-bit ADCs, see the MAX157 and MAX159 data sheets. 0°C to MAX144ACUA 8 µMAX ±0.5 U8-1 +70°C Applications 0°C to MAX144BCUA 8 µMAX ±1 U8-1 Battery-Powered Systems Instrumentation +70°C 0°C to Portable Data Logging Test Equipment MAX144ACPA 8 Plastic DIP ±0.5 P8-1 +70°C Isolated Data Acquisition Medical Instruments 0°C to MAX144BCPA 8 Plastic DIP ±1 P8-1 Process-Control Monitoring System Supervision +70°C 0°C to MAX144BC/D Dice* ±1 — +70°C Pin Configuration -40°C to MAX144AEUA 8 µMAX ±0.5 U8-1 +85°C TOP VIEW MAX144BEUA -40°C to 8 µMAX ±1 U8-1 +85°C -40°C to MAX144AEPA 8 Plastic DIP ±0.5 P8-1 VDD 1 8 SCLK +85°C -40°C to CH0 (CH+) 2 7 DOUT MAX144BEPA 8 Plastic DIP ±1 P8-1 MAX144 +85°C CH1 (CH-) 3 MAX145 6 CS/SHDN -55°C to MAX144AMJA 8 CERDIP** ±0.5 J8-2 +125°C GND 4 5 REF -55°C to MAX144BMJA 8 CERDIP** ±1 J8-2 +125°C ( ) ARE FOR MAX145 ONLY µMAX/DIP *Dice are specified at TA= +25°C, DC parameters only. **Contact factory for availability. µMAX is a registered trademark of Maxim Integrated Products, Inc. Ordering Information continued at end of data sheet. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________Maxim Integrated Products 1 For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin µMAX 5 ABSOLUTE MAXIMUM RATINGS 4 VDDto GND..............................................................-0.3V to +6V Plastic DIP (derate 9.09mW/°C above +70°C)............727mW 1 CH0, CH1 (CH+, CH-) to GND ................. -0.3V to (VDD+ 0.3V) CERDIP (derate 8.00mW/°C above +70°C) ............... 640mW X REF to GND .............................................. -0.3V to (VDD+ 0.3V) Operating Temperature Ranges (TA) Digital Inputs to GND.............................................. -0.3V to +6V MAX144/MAX145_C_A.......................................0°C to +70°C A DOUT to GND............................................ -0.3V to (VDD+ 0.3V) MAX144/MAX145_E_A....................................-40°C to +85°C DOUT Sink Current ........................................................... 25mA MAX144/MAX145_M_A ................................ -55°C to +125°C M Continuous Power Dissipation (TA= +70°C) Storage Temperature Range.............................-65°C to +150°C / µMAX (derate 4.1mW/°C above +70°C) .................... 330mW Lead Temperature (soldering, 10s) .................................+300°C 4 4 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional 1 operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. X A ELECTRICAL CHARACTERISTICS M (VDD = +2.7V to +5.25V, VREF = 2.5V, 0.1µF capacitor at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps), CH- = GND for MAX145, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY(Note 1) Resolution RES 12 Bits MAX14_A ±0.5 Relative Accuracy (Note 2) INL LSB MAX14_B ±1 Differential Nonlinearity DNL No missing codes over temperature ±0.75 LSB Offset Error ±3 LSB Gain Error (Note 3) ±3 LSB Gain Temperature Coefficient ±0.8 ppm/°C Channel-to-Channel Offset ±0.05 LSB Matching Channel-to-Channel Gain ±0.05 LSB Matching DYNAMIC SPECIFICATIONS(fIN(sine-wave)= 10kHz, VIN= 2.5Vp-p, 108ksps, fSCLK= 2.17MHz, CH- = GND for MAX145) Signal-to-Noise Plus SINAD 70 dB Distortion Ratio Total Harmonic Distortion THD -80 dB (including 5th-order harmonic) Spurious-Free Dynamic Range SFDR 80 dB Channel-to-Channel Crosstalk fIN= 65kHz, VIN= 2.5Vp-p (Note 4) -85 dB Small-Signal Bandwidth -3dB rolloff 2.25 MHz Full-Power Bandwidth 1.0 MHz CONVERSION RATE External clock, fSCLK= 2.17MHz, 7.4 Conversion Time (Note 5) tCONV 16 clocks/conversion cycle µs Internal clock 5 7 T/H Acquisition Time tACQ 2.5 µs Aperture Delay 25 ns Aperture Jitter <50 ps External clock mode 0.1 2.17 Serial Clock Frequency fSCLK MHz Internal clock mode, for data transfer only 0 5 2 _______________________________________________________________________________________

+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin µMAX ELECTRICAL CHARACTERISTICS (continued) M (VDD = +2.7V to +5.25V, VREF = 2.5V, 0.1µF capacitor at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps), CH- = GND for MAX145, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS X ANALOG INPUTS 1 4 Analog Input Voltage Range VIN (Note 6) 0 VREF V 4 Multiplexer Leakage Current On/off leakage current, VIN= 0 to VDD ±0.01 ±1 µA / M Input Capacitance CIN 16 pF EXTERNAL REFERENCE A Input Voltage Range VREF (Note 7) 0 + V5D0mD V V X 1 Input Current VREF= 2.5V 100 140 µA 4 Input Resistance 18 25 kΩ 5 Shutdown REF Input Current 0.01 10 µA DIGITAL INPUTS (CS/SHDN) AND OUTPUT (DOUT) VDD≤3.6V 2.0 Input High Voltage VIH V VDD> 3.6V 3.0 Input Low Voltage VIL 0.8 V Input Hysteresis VHYS 0.2 V Input Leakage Current IIN VIN= 0 or VDD ±1 µA Input Capacitance CIN (Note 8) 15 pF ISINK= 5mA 0.4 Output Low Voltage VOL V ISINK= 16mA 0.5 Output High Voltage VOH ISOURCE= 0.5mA VDD- 0.5 V Three-State Output Leakage Current CS/SHDN = VDD ±10 µA Three-State Output Capacitance COUT CS/SHDN = VDD(Note 8) 15 pF POWER REQUIREMENTS Positive Supply Voltage VDD 2.7 5.25 V Operating mode 0.9 2.0 mA Positive Supply Current IDD Shutdown, CS/SHDN = GND 0.2 5 µA Power-Supply Rejection PSR VDD= 2.7V to 5.25V, ±0.15 mV VREF = 2.5V, full-scale input (Note 9) _______________________________________________________________________________________ 3

+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin µMAX 5 TIMING CHARACTERISTICS (Figure 7) 4 (VDD= +2.7V to +5.25V, VREF= 2.5V, 0.1µF capacitor at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps), CH-= GND 1 for MAX145, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) X PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS A Wake-Up Time 2.5 µs M CS/SHDN Fall to Output Enable tDV CL = 100pF 120 ns CS /SHDN Rise to Output Disable tTR CL = 100pF, Figure 1 120 ns / 4 SCLK Fall to Output Data Valid tDO CL = 100pF, Figure 1 20 120 ns 4 External clock 0.1 2.17 1 SCLK Clock Frequency fSCLK MHz Internal clock, SCLK for data transfer only 0 5 X External clock 215 A SCLK Pulse Width High tCH Internal clock, SCLK for data transfer only ns M (Note 8) 50 External clock 215 SCLK Pulse Width Low tCL Internal clock, SCLK for data transfer only ns 50 (Note 8) SCLK to CS /SHDN Setup tSCLKS 60 ns CS /SHDN Pulse Width tCS 60 ns Note 1: Tested at VDD= +2.7V. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been calibrated. Note 3: Offset nulled. Note 4: "On" channel is grounded; sine wave applied to "off" channel (MAX144 only). Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle. Note 6: The common-mode range for the analog inputs is from GND to VDD(MAX145 only). Note 7: ADC performance is limited by the converter’s noise floor, typically 300µVp-p. Note 8: Guaranteed by design. Not subject to production testing. Note 9: Measured as VFS(2.7V) -VFS(5.25V). 4 _______________________________________________________________________________________

+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin µMAX Typical Operating Characteristics M (VDD= +3.0V, VREF= 2.5V, 0.1µF at REF, fSCLK= 2.17MHz, 16 clocks/conversion cycle (108ksps), CH- = GND for MAX145, TA= +25°C, A unless otherwise noted.) X SUPPLY CURRENT SUPPLY CURRENT SUPPLY CURRENT 1 vs. SUPPLY VOLTAGE vs. TEMPERATURE vs. SAMPLING RATE 4 A)11350000 VRCCRLLO E =D=F E¥5= 0 =Vp 1DF0D1010100000 MAX144/5-01 A)11255000 VRCCRLLO E =D=F E¥5= 0 =Vp 1DF0D1010100000 MAX144/5-02 A)101,000000 VCCDLO DD= =E2 0V=p R1FE0F1010100000 MAX144/5-03 4/M mRENT (1100 mRENT ( mRENT ( 100 A UR UR1000 UR X C C C PLY 900 PLY PLY 10 1 P P P U U U S S S 4 750 700 1 5 500 500 0.1 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -60 -40 -20 0 20 40 60 80 100 120 140 0.1 1 10 100 1k 10k 100k SUPPLY VOLTAGE (V) TEMPERATURE (°C) SAMPLING RATE (sps) SHUTDOWN CURRENT SHUTDOWN CURRENT OFFSET ERROR vs. SUPPLY VOLTAGE vs. TEMPERATURE vs. SUPPLY VOLTAGE HUTDOWN CURRENT (nA)1468000000000 VREF = VDD MAX144/5-04 HUTDOWN CURRENT (nA)1468000000000 VREF = VDD MAX144/5-05 OFFSET ERROR (LSB) 0001....4680 MAX144/5-06 S S 200 200 0.2 0 0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -60 -40 -20 0 20 40 60 80 100 120 140 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) TEMPERATURE (°C) SUPPLY VOLTAGE (V) OFFSET ERROR GAIN ERROR GAIN ERROR vs. TEMPERATURE vs. SUPPLY VOLTAGE vs. TEMPERATURE 1.0 0.5 0.5 00..98 MAX144/5-07 00..43 MAX144/5-08 00..43 MAX144/5-09 OFFSET ERROR (LSB) 00000.....43657 GAIN ERROR (LSB) --0000....01212 GAIN ERROR (LSB) --0000....01212 0.2 -0.3 -0.3 0.1 -0.4 -0.4 0 -0.5 -0.5 -60 -35 -10 15 40 65 90 115 140 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -60 -35 -10 15 40 65 90 115 140 TEMPERATURE (°C) VDD (V) TEMPERATURE (°C) _______________________________________________________________________________________ 5

+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin µMAX 5 Typical Operating Characteristics (continued) 4 (VDD= +3.0V, VREF= 2.5V, 0.1µF at REF, fSCLK= 2.17MHz, 16 clocks/conversion cycle (108ksps), CH- = GND for MAX145, TA= +25°C, 1 unless otherwise noted.) X A INTEGRAL NONLINEARITY INTEGRAL NONLINEARITY INTEGRAL NONLINEARITY vs. OUTPUT CODE vs. SUPPLY VOLTAGE vs. TEMPERATURE M 0.20 0.5 0.5 4/ 0.15 MAX144/5-10 0.4 MAX144/5-11 0.4 MAX144/5-12 0.10 4 1 B) 0.05 B) 0.3 B) 0.3 S S S X NL (L 0 NL (L NL (L A I -0.05 I 0.2 I 0.2 M -0.10 0.1 0.1 -0.15 -0.20 0 0 0 1024 2048 3072 4096 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -60 -35 -10 15 40 65 90 115 140 OUTPUT CODE VDD (V) TEMPERATURE (°C) EFFECTIVE NUMBER OF BITS FFT PLOT vs. FREQUENCY 20 -200 VffISNDA DM= =P1L 0+Ek2 H=.7 z1V08ksps MAX144/5-13 BITS 1121..08 VDD = +2.7V MAX144/5-14 UDE (dB) --6400 MBER OF 11.6 MPLIT -80 VE NU 11.4 A CTI -100 EFFE 11.2 -120 -140 11.0 0 27 54 1 10 100 FREQUENCY (kHz) FREQUENCY (kHz) Pin Description PIN NAME FUNCTION 1 VDD Positive Supply Voltage, +2.7V to +5.25V 2 CH0 (CH+) Analog Input: MAX144 = single-ended (CH0); MAX145 = differential (CH+) 3 CH1 (CH-) Analog Input: MAX144 = single-ended (CH1); MAX145 = differential (CH-) 4 GND Analog and Digital Ground External Reference Voltage Input. Sets the analog voltage range. Bypass with a 100nF capacitor close to 5 REF the device. Active-Low Chip-Select Input/Active-High Shutdown Input. Pulling CS/SHDN high puts the device into 6 CS/SHDN shutdown with a maximum current of 5µA. Serial Data Output. Data changes state atSCLK’s falling edge. High impedance whenCS/SHDN 7 DOUT is high. 8 SCLK Serial Clock Input. DOUT changes on the falling edge of SCLK. 6 _______________________________________________________________________________________

+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin µMAX M VDD A DOUT 6k X DOUT 6k CL 1 CL 4 GND GND 4 a) HIGH-Z TO V0H, V0L TO V0H, AND VOH TO HIGH-Z b) HIGH-Z TO V0L, V0H TO V0L, AND VOL TO HIGH-Z / M Figure 1. Load Circuits for Enable and Disable Time A _______________Detailed Description X CS/SHDN The MAX144/MAX145 analog-to-digital converters SCLK 1 (ADCs) use a successive-approximation conversion 4 INTERNAL (SAR) technique and on-chip track-and-hold (T/H) CLOCK 5 structure to convert an analog signal to a serial 12-bit DOUT CONTROL OUTPUT digital output data stream. LOGIC REGISTER This flexible serial interface provides easy interface to CH0 microprocessors (µPs). Figure 2 shows a simplified (CH+) SCLK functional diagram of the internal architecture for both ANALOG 12-BIT the MAX144 (2 channels, single-ended) and the MAX145 CH1 INMPUUXT T/H IN ASDARC OUT MAX144 (1 channel, pseudo-differential). (CH-) (2 CHANNEL) MAX145 Analog Inputs: Single-Ended (MAX144) REF ( ) ARE FOR MAX145 and Pseudo-Differential (MAX145) Figure 2. Simplified Functional Diagram The sampling architecture of the ADC’s analog com- parator is illustrated in the equivalent input circuit of Figure 3. In single-ended mode (MAX144), both chan- 12-BIT CAPACITIVE DAC nels CH0 and CH1 are referred to GND and can be REF MAX144 connected to two different signal sources. Following the MAX145 power-on reset, the ADC is set to convert CH0. After CH0 CHOLD CH0 has been converted, CH1 will be converted and (CH+) INPUT 16pF COMPARATOR the conversions will continue to alternate between CH1 MUX ZERO TO SAR channels. Channel switching is performed by toggling (CH-) RIN the CS/SHDN pin. Conversions can be performed on 9kW the same channel by toggling CS/SHDN twice between conversions. If only one channel is required, CH0 and CSWITCH TRACK HOLD CH1 may be connected together; however, the output T/H data will still contain the channel identification bit GND (before the MSB). CONTROL LOGIC SINGLE-ENDED MODE: CH0, CH1 = IN+; GND = IN- For the MAX145, the input channels form a single differ- DIFFERENTIAL-ENDED MODE: CH+ = IN+; CH- = IN- ( ) ARE FOR MAX145 ential channel pair (CH+, CH-). This configuration is Figure 3. Analog Input Channel Structure pseudo-differential to the effect that only the signal at IN+ is sampled. The return side IN- must remain stable clock mode) or from when CS/SHDN falls to the first within ±0.5LSB (±0.1LSB for optimum results) with falling edge of SCLK (internal clock mode). At the end respect to GND during a conversion. To accomplish of the acquisition interval, the T/H switch opens, retain- this, connect a 0.1µF capacitor from IN- to GND. ing charge on CHOLDas a sample of the signal at IN+. During the acquisition interval, the channel selected as The conversion interval begins with the input multiplex- the positive input (IN+) charges capacitor CHOLD. The er switching CHOLD from the positive input (IN+) to the acquisition interval spans from when CS/SHDN falls to negative input (IN-). This unbalances node ZERO at the the falling edge of the second clock cycle (external comparator’s positive input. _______________________________________________________________________________________ 7

+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin µMAX 5 The capacitive digital-to-analog converter (DAC) Higher source impedances can be used if a 0.01µF 4 adjusts during the remainder of the conversion cycle capacitor is connected to the individual analog inputs. to restore node ZERO to 0V within the limits of 12-bit Together with the input impedance, this capacitor 1 resolution. This action is equivalent to transferring a forms an RC filter, limiting the ADC’s signal bandwidth. X 16pF · [(VIN+) - (VIN-)] charge from CHOLD to the bina- A ry-weighted capacitive DAC, which in turn forms a digi- Input Bandwidth The MAX144/MAX145 T/H stage offers a 2.25MHz M tal representation of the analog input signal. small-signal and a 1MHz full-power bandwidth, which / Track/Hold (T/H) make it possible to use the parts for digitizing high- 4 The ADC’s T/H stage enters its tracking mode on the speed transients and measuring periodic signals with 4 falling edge of CS/SHDN. For the MAX144 (single- bandwidths exceeding the ADCs sampling rate by 1 ended inputs), IN- is connected to GND and the con- using undersampling techniques. To avoid high-fre- X verter samples the positive (“+”) input. For the MAX145 quency signals being aliased into the frequency band (pseudo-differential inputs), IN- connects to the nega- of interest, anti-alias filtering is recommended. Most A tive input (“-”) and the difference of [(VIN+) - (VIN-)] is aliasing problems can be fixed easily with an external M sampled. At the end of the conversion, the positive resistor and a capacitor. However, if DC precision is input connects back to IN+ and CHOLD charges to the required, it is usually best to choose a continuous or input signal. switched-capacitor filter, such as the MAX7410/ MAX7414 (Figure 4). Their Butterworth characteristic The time required for the T/H stage to acquire an input generally provides the best compromise (with regard to signal is a function of how fast its input capacitance is rolloff and attenuation) in filter configurations, is easy to charged. If the input signal’s source impedance is high, design, and provides a maximally flat passband response. the acquisition time lengthens, and more time must be allowed between conversions. The acquisition time, Analog Input Protection tACQ, is the maximum time the device takes to acquire Internal protection diodes, which clamp the analog input the signal, and is also the minimum time required for to VDD and GND, allow each input channel to swing the signal to be acquired. Calculate this with the follow- within GND - 300mV to VDD + 300mV without damage. ing equation: However, for accurate conversions, both inputs must not tACQ= 9(RS+ RIN)CIN exceed VDD+ 50mV or be less than GND - 50mV. where RS is the source impedance of the input signal, If an off-channel analog input voltage exceeds the RIN (9kΩ) is the input resistance, and CIN (16pF) is the supplies, limit the input current to 4mA. input capacitance of the ADC. Source impedances below 1kΩhave no significant impact on the AC perfor- mance of the MAX144/MAX145. VDD 4 1 VDD SHDN 7 0.1m F 2 CH0 VDD REF 5 EXTERNAL REFERENCE 470W ** 5 MAX7410 OUT MAX144 2 IN MAX7414 CLK 8 3 CH1 DOUT 7 fC = 15kHz 0.01m F** 8 6 SCLK CS/SHDN m P/m C COM OS GND GND 1 6 3 4 0.01m F 1.5MHz OSCILLATOR **USED TO ATTENUATE SWITCHED-CAPACITOR FILTER CLOCK NOISE Figure 4. Analog Input with Anti-Aliasing Filter Structure 8 _______________________________________________________________________________________

+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin µMAX Selecting Clock Mode External Clock (fSCLK= 100kHz to 2.17MHz) M To start the conversion process on the MAX144/ The external clock mode (Figure 6) is selected by tran- MAX145, pull CS/SHDN low. At CS/SHDN’s falling sitioning CS/SHDN from high to low while SCLK is low. A edge, the part wakes up and the internal T/H enters The external clock signal not only shifts data out, but X track mode. In addition, the state of SCLK at also drives the analog-to-digital conversion. The input 1 CS/SHDN’s falling edge selects internal (SCLK = high) is sampled and conversion begins on the falling edge or external (SCLK = low) clock mode. of the second clock pulse. Conversion must be com- 4 pleted within 140µs to prevent degradation in the con- 4 Internal Clock (fSCLK< 100kHz or fSCLK> 2.17MHz) version results caused by droop on the T/H capacitors. / In internal clock mode, the MAX144/MAX145 run from External clock mode provides the best throughput for M an internal, laser-trimmed oscillator to within 20% of the clock frequencies between 100kHz and 2.17MHz. A 2MHz specified clock rate. This releases the system microprocessor from running the SAR conversion clock Output Data Format X and allows the conversion results to be read back at Table 1 illustrates the 16-bit, serial data stream output 1 the processor’s convenience, at any clock rate from 0 format for both the MAX144 and MAX145. The first 4 to 5MHz. Operating the MAX144/MAX145 in internal three bits are always logic high (including the EOC bit clock mode is necessary for serial interfaces operating for internal clock mode), followed by the channel identi- 5 with clock frequencies lower than 100kHz or greater fication (CHID = 0 for CH0, CHID = 1 for CH1, CHID = 0 than 2.17MHz. Select internal clock mode (Figure 5), by for the MAX145), and then 12 bits of data in MSB-first holding SCLK high during a high/low transition of format. After the last bit has been read out, additional CS/SHDN. The first SCLK falling edge samples the data SCLK pulses will clock out trailing zeros. DOUT transi- and initiates a conversion using the integrated on-chip tions on the falling edge of SCLK. The output remains oscillator. After the conversion, the oscillator shuts off high-impedance when CS/SHDN is high. and DOUT goes high, signaling the end of conversion (EOC). Data can then be read out with SCLK. ACTIVE POWER ACTIVE DOWN tCS tWAKE tCONV (tACQ) CS/SHDN SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HIGH-Z HIGH-Z EOC 1 1 CHID MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DOUT SAMPLING INSTANT Figure 5. Internal Clock Mode Timing ACTIVE POWER ACTIVE ACTIVE POWER DOWN DOWN SAMPLING INSTANT tCS tWAKE (tACQ) CS/SHDN SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HIGH-Z HIGH-Z CHID MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DOUT Figure 6. External Clock Mode Timing _______________________________________________________________________________________ 9

+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin µMAX 5 Table 1. Serial Output Data Stream for Internal and External Clock Mode 4 SCLK CYCLE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 DOUT (Internal Clock) EOC 1 1 CHID D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X DOUT (External Clock) 1 1 1 CHID D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A M External Reference Effective Number of Bits (ENOB) / An external reference is required for both the MAX144 ENOB indicates the global accuracy of an ADC at a 4 and the MAX145. At REF, the DC input resistance is a specific input frequency and sampling rate. An ideal 4 minimum of 18kΩ. During a conversion, a reference ADC’s error consists only of quantization noise. With an 1 must be able to deliver 250µA of DC load current and input range equal to the full-scale range of the ADC, the X have an output impedance of 10Ω or less. Use a 0.1µF effective number of bits can be calculated as follows: bypass capacitor for best performance. The reference A ENOB = (SINAD - 1.76) / 6.02 input structure allows a voltage range of 0 to VDD + M 50mV, although noise levels will decrease effective res- Total Harmonic Distortion (THD) olution at lower reference voltages. THD is the ratio of the RMS sum of the first five harmon- ics of the input signal to the fundamental itself. This is Automatic Power-Down Mode expressed as: Whenever the MAX144/MAX145 are not selected (CS/SHDN = VDD), the parts enter their shutdown (cid:230) (cid:230) (cid:246) (cid:246) mode. In shutdown all internal circuitry turns off, reduc- (cid:231) Ł V22 +V32 +V42 +V52 ł (cid:247) ing supply current to typically less than 0.2µA. With an THD = 20 x log (cid:231) (cid:247) (cid:231) (cid:247) external reference stable to within 1LSB, the wake-up (cid:231) V1 (cid:247) time is 2.5µs. If the external reference is not stable with- Ł ł in 1LSB, the wake-up time must be increased to allow the reference to stabilize. where V1is the fundamental amplitude, and V2through V5 are the amplitudes of the 2nd- through 5th-order __________Applications Information harmonics. Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) For a waveform perfectly reconstructed from digital SFDR is the ratio of RMS amplitude of the fundamental samples, the theoretical maximum SNR is the ratio of (maximum signal component) to the RMS value of the full-scale analog input (RMS value) to the RMS quanti- next largest spurious component, excluding DC offset. zation error (residual error). The ideal, theoretical mini- mum analog-to-digital noise is caused by quantization Connection to Standard Interfaces error only and results directly from the ADC’s resolution The MAX144/MAX145 interface is fully compatible with (N bits): SPI, QSPI, and MICROWIRE standard serial interfaces. SNR(MAX) = (6.02 x N + 1.76)dB If a serial interface is available, establish the CPU’s seri- al interface as master so that the CPU generates the In reality, there are other noise sources besides quanti- serial clock for the MAX144/MAX145. Select a clock fre- zation noise: thermal noise, reference noise, clock jitter, quency from 100kHz to 2.17MHz (external clock mode). etc. Therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise which includes all 1) Use a general-purpose I/O line on the CPU to pull spectral components minus the fundamental, the first CS/SHDN low while SCLK is low. five harmonics, and the DC offset. 2) Wait for the minimum wake-up time (tWAKE) speci- fied before activating SCLK. Signal-to-Noise Plus Distortion (SINAD) SINAD is the ratio of the fundamental input frequency’s 3) Activate SCLK for a minimum of 16 clock cycles. RMS amplitude to RMS equivalent of all other ADC out- The serial data stream of three leading ones, the put signals: channel identification, and the MSB of the digitized Ø ø input signal begin at the first falling clock edge. SINAD(dB) = 20 x log Œ SIGNALRMS œ DOUT transitions on SCLK’s falling edge and is º (Noise + Distortion)RMSß available in MSB-first format. Observe the SCLK to 10 ______________________________________________________________________________________

+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin µMAX DOUT valid timing characteristic. Data should be padded with three leading ones and the channel identi- M clocked into the µP on SCLK’s rising edge. fication before the MSB. If the serial clock hasn’t been A idled after the last LSB and CS/SHDN is kept low, 4) Pull CS/SHDN high at or after the 16th falling clock DOUT sends trailing zeros. X edge. If CS/SHDN remains low, trailing zeros will be clocked out after the LSB. 1 SPI and MICROWIRE Interface 5) With CS/SHDN high, wait at least 60ns (tCS) before When using SPI (Figure 8a) or MICROWIRE (Figure 8b) 4 starting a new conversion by pulling CS/SHDN low. interfaces, set CPOL = 0 and CPHA = 0. Conversion 4 A conversion can be aborted by pulling CS/SHDN begins with a falling edge on CS/SHDN (Figure 8c). / M high before the conversion ends; wait at least 60ns Two consecutive 8-bit readings are necessary to obtain before starting a new conversion. the entire 12-bit result from the ADC. DOUT data transi- A tions on the serial clock’s falling edge and is clocked Data can be output in two 8-bit sequences or continu- X into the µP on SCLK’s rising edge. The first 8-bit data ously. The bytes will contain the result of the conversion stream contains three leading ones, the channel identi- 1 4 5 CS/SHDN • • • tSCLKS tCH tCS tCL SCLK • • • tDV tDO tTR HIGH-Z HIGH-Z DOUT • • • Figure 7. Detailed Serial-Interface Timing Sequence I/O CS/SHDN I/O CS/SHDN SCK SCLK SK SCLK MISO DOUT SI DOUT SPI VDD MICROWIRE MAX144 MAX145 MAX144 SS MAX145 Figure 8a. SPI Connections 8b. MICROWIRE Connections 1ST BYTE READ 2ND BYTE READ SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CS/SHDN HIGH-Z DOUT* CHID D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SAMPLING INSTANT MSB LSB *WHEN CS/SHDN IS HIGH, DOUT = HIGH-Z Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0) ______________________________________________________________________________________ 11

+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin µMAX 5 fication, and the first four data bits starting with the PIC16 with SSP Module and PIC17 Interface 4 MSB. The second 8-bit data stream contains the The MAX144/MAX145 are compatible with a PIC16/ remaining bits, D7 through D0. PIC17 controller (µC), using the synchronous serial-port 1 (SSP) module. X QSPI Interface To establish SPI communication, connect the controller A Using the high-speed QSPI interface with CPOL = 0 as shown in Figure 10a and configure the PIC16/PIC17 and CPHA = 0, the MAX144/MAX145 support a maxi- M as system master by initializing its synchronous serial- mum fSCLK of 2.17MHz. The QSPI circuit in Figure 9a port control register (SSPCON) and synchronous serial- / can be programmed to perform a conversion on each 4 port status register (SSPSTAT) to the bit patterns shown of the two channels for the MAX144. Figure 9b shows 4 the QSPI interface timing. in Tables 2 and 3. 1 In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data to be synchronously transmitted and received simulta- X neously. Two consecutive 8-bit readings (Figure 10b) A CS CS/SHDN are necessary to obtain the entire 12-bit result from the SCK SCLK M ADC. DOUT data transitions on the serial clock’s falling MISO DOUT QSPI VDD edge and is clocked into the µC on SCLK’s rising edge. The first 8-bit data stream contains three leading ones, MAX144 the channel identification, and the first four data bits MAX145 starting with the MSB. The second 8-bit data stream SS contains the remaining bits, D7 through D0. Figure 9a. QSPI Connections SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CS/SHDN HIGH-Z DOUT CHID D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SAMPLING INSTANT MSB LSB *WHEN CS/SHDN IS HIGH, DOUT = HIGH-Z Figure 9b. QSPI Interface Timing Sequence (CPOL = CPHA = 0) Table 2. Detailed SSPCON Register Contents MAX144/MAX145 CONTROL BIT SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON) SETTINGS WCOL BIT7 X Write Collision Detection Bit SSPOV BIT6 X Receive Overflow Detect Bit Synchronous Serial-Port Enable Bit. SSPEN BIT5 1 0: Disables serial port and configures these pins as I/O port pins. 1: Enables serial port and configures SCK, SDO and SCI pins as serial port pins. CKP BIT4 0 Clock Polarity Select Bit. CKP = 0 for SPI master mode selection. SSPM3 BIT3 0 SSPM2 BIT2 0 Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and selects SSPM1 BIT1 0 fCLK= fOSC/ 16. SSPM0 BIT0 1 X = Don’t care 12 ______________________________________________________________________________________

+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin µMAX Table 3. Detailed SSPSTAT Register Contents M MAX144/MAX145 A CONTROL BIT SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT) SETTINGS X SPI Data Input Sample Phase. Input data is sampled at the middle of the data output SMP BIT7 0 1 time. 4 CKE BIT6 1 SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock. 4 D/A BIT5 X Data Address Bit / M P BIT4 X Stop Bit S BIT3 X Start Bit A R/W BIT2 X Read/Write Bit Information X UA BIT1 X Update Address 1 BF BIT0 X Buffer Full Status Bit 4 X = Don’t care 5 Layout, Grounding, and Bypassing (analog and digital). For lowest-noise operation, ensure For best performance, use printed circuit boards the ground return to the star ground’s power supply is (PCBs). Wire-wrap configurations are not recommend- low impedance and as short as possible. Route digital ed, since the layout should ensure proper separation of signals far away from sensitive analog and reference analog and digital traces. Run analog and digital lines inputs. anti-parallel to each other, and don’t lay out digital sig- High-frequency noise in the power supply VDD could nal paths underneath the ADC package. Use separate influence the proper operation of the ADC’s fast com- analog and digital PCB ground sections with only one parator. Bypass VDD to the star ground with a network star-point (Figure 11) connecting the two ground systems of two parallel capacitors (0.1µF and 1µF) located as close as possible to the power supply pin of MAX144/ MAX145. Minimize capacitor lead length for best sup- VDD VDD ply-noise rejection and add an attenuation resistor (10Ω) if the power supply is extremely noisy. SCLK SCK DOUT SDI CS/SHDN I/O MAX144 PIC16/17 MAX145 GND GND Figure 10a. SPI Interface Connection for a PIC16/PIC17 Controller 1ST BYTE READ 2ND BYTE READ SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CS/SHDN HIGH-Z DOUT* CHID D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SAMPLING INSTANT MSB LSB *WHEN CS/SHDN IS HIGH, DOUT = HIGH-Z Figure 10b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3–SSPM0 = 0001) ______________________________________________________________________________________ 13

+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin µMAX 5 Ordering Information (continued) 4 1 POWER SUPPLIES PART TEMP PIN- INL PKG RANGE PACKAGE (LSB) CODE X +3V +3V GND 0°C to A MAX145ACUA 8 µMAX ±0.5 U8-1 +70°C R* = 10 W M 0°C to 1mF MAX145BCUA 8 µMAX ±1 U8-1 +70°C / 4 0°C to MAX145ACPA 8 Plastic DIP ±0.5 P8-1 4 +70°C 0.1mF 0°C to 1 VDD GND +3V DGND MAX145BCPA +70°C 8 Plastic DIP ±1 P8-1 X 0°C to DIGITAL MAX145BC/D Dice* ±1 — A MAX144 CIRCUITRY +70°C M MAX145 -40°C to MAX145AEUA 8 µMAX ±0.5 U8-1 +85°C * OPTIONAL FILTER RESISTOR -40°C to MAX145BEUA 8 µMAX ±1 U8-1 +85°C Figure 11. Power-Supply Bypassing and Grounding -40°C to MAX145AEPA 8 Plastic DIP ±0.5 P8-1 +85°C -40°C to MAX145BEPA 8 Plastic DIP ±1 P8-1 +85°C Chip Information 55°C to MAX145AMJA 8 CERDIP** ±0.5 J8-2 TRANSISTOR COUNT: 2,058 +125°C SUBSTRATE CONNECTED TO GND 55°C to MAX145BMJA 8 CERDIP** ±1 J8-2 +125°C *Dice are specified at TA= +25°C, DC parameters only. **Contact factory for availability. 14 ______________________________________________________________________________________

+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin µMAX M ________________________________________________________Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, A go to www.maxim-ic.com/packages.) X PS 1 E D. 4 X A M 4 U L 8 / M A X 1 4 5 ______________________________________________________________________________________ 15

+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin µMAX 5 Package Information (continued) 4 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, 1 go to www.maxim-ic.com/packages.) X A M PS E N. P / DI 4 P 4 1 X A M Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16_________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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