19-1155; Rev 5; 8/10 EVAALVUAAILTAIOBNL EKIT +2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO __________________General Description ________________________________Features M The MAX1240/MAX1241 low-power, 12-bit analog-to- ♦ Single-Supply Operation: A digital converters (ADCs) are available in 8-pin pack- +2.7V to +3.6V (MAX1240) ages. The MAX1240 operates with a single +2.7V to +2.7V to +5.25V (MAX1241) X +3.6V supply, and the MAX1241 operates with a single ♦ 12-Bit Resolution 1 +2.7V to +5.25V supply. Both devices feature a 7.5µs ♦ Internal 2.5V Reference (MAX1240) 2 successive-approximation ADC, a fast track/hold ♦ Small Footprint: 8-Pin PDIP/SO Packages 4 (1.5µs), an on-chip clock, and a high-speed, 3-wire ser- ♦ Low Power: 3.7µW (73ksps, MAX1240) 0 ial interface. 3mW (73ksps, MAX1241) / Power consumption is only 37mW (VDD = 3V) at the 66µW (1ksps, MAX1241) M 73ksps maximum sampling speed. A 2µA shutdown 5µW (power-down mode) mode reduces power at slower throughput rates. ♦ Internal Track/Hold A The MAX1240 has an internal 2.5V reference, while the ♦ SPI/QSPI/MICROWIRE 3-Wire Serial Interface X MAX1241 requires an external reference. The MAX1241 ♦ Internal Clock 1 accepts signals from 0V to VREF, and the reference Ordering Information 2 input range includes the positive supply rail. An exter- 4 nal clock accesses data from the 3-wire interface, PIN - INL which connects directly to standard microcontroller I/O PART* TEMP RANGE PAC KA GE (LSB) 1 ports. The interface is compatible with SPI™, QSPI™, MAX1240ACPA+ 0°C to +70°C 8 PDIP ±1/2 and MICROWIRE™. MAX1240BCPA+ 0°C to +70°C 8 PDIP ±1 Excellent AC characteristics and very low power com- bined with ease of use and small package size make MAX1240CCPA+ 0°C to +70°C 8 PDIP ±1 these converters ideal for remote-sensor and data- MAX1240ACSA+ 0°C to +70°C 8 SO ±1/2 acquisition applications, or for other circuits with MAX1240BCSA+ 0°C to +70°C 8 SO ±1 demanding power consumption and space require- MAX1240CCSA+ 0°C to +70°C 8 SO ±1 ments. The MAX1240/MAX1241 are available in 8-pin MAX1240CC/D 0°C to +70°C Dice* ±1 PDIP and SO packages. MAX1240AESA/V+** -40°C to +85°C 8 SO ±1/2 Applications MAX1240BESA/V+ -40°C to +85°C 8 SO ±1 Ordering Information continued at end of data sheet. Battery-Powered Systems *Dice are specified at TA=+25°C, DC parameters only. Portable Data Logging **Future product—contact factory for availability. /V denotes an automotive qualified part. Isolated Data Acquisition +Denotes a lead(Pb)-free/RoHS-compliant package. Process Control Functional Diagram Instrumentation VDD 1 Pin Configuration 7 CS 8 SCLK TOP VIEW SHDN 3 CONTROL INT LOGIC CLOCK OUTPUT 6 SHIFT DOUT VDD 1 8 SCLK REGISTER AIN 2 7 CS SHDN 3 MMAAXX11224401 6 DOUT AIN 2 T/H 1S2-ABRIT REF 4 5 GND 2.5V REFERENCE MAX1240 4 (MAX1240 ONLY) MAX1241 REF PDIP/SO 5 GND SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO 1 ABSOLUTE MAXIMUM RATINGS 4 VDDto GND.............................................................-0.3V to +6V Operating Temperature Ranges 2 AIN to GND................................................-0.3V to (VDD + 0.3V) MAX1240_C_A/MAX1241_C_A.........................0°C to +70°C 1 REF to GND...............................................-0.3V to (VDD + 0.3V) MAX1240_E_ A/MAX1241_E_ A.....................-40°C to +85°C Digital Inputs to GND...............................................-0.3V to +6V MAX1240_MJA/MAX1241_MJA...................-55°C to +125°C X DOUT to GND............................................-0.3V to (VDD + 0.3V) Storage Temperature Range............................-60°C to +150°C A DOUT Current..................................................................±25mA Lead Temperature (soldering, 10s)................................+300°C Continuous Power Dissipation (TA = +70°C) Soldering Temperature (reflow) M Plastic DIP (derate 9.09mW/°C above +70°C)...........727mW PDIP, SO.....................................................................+260°C SO (derate 5.88mW/°C above +70°C)........................471mW CDIP...........................................................................+250°C / 0 CERDIP (derate 8.00mW/°C above +70°C)................640mW 4 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional 2 operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to 1 absolute maximum rating conditions for extended periods may affect device reliability. X ELECTRICAL CHARACTERISTICS A M (VDD= +2.7V to +3.6V (MAX1240); VDD= +2.7V to +5.25V (MAX1241); 73ksps, fSCLK= 2.1MHz (50% duty cycle); MAX1240—4.7µF capacitor at REF pin, MAX1241—external reference; VREF= 2.500V applied to REF pin; TA= TMINto TMAX; unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY(Note 1) Resolution 12 Bits MAX124_A ±0.5 Relative Accuracy (Note 2) INL LSB MAX124_B/C ±1.0 Differential Nonlinearity DNL No missing codes over temperature ±1 LSB MAX124_A ±0.5 ±3.0 Offset Error LSB MAX124_B/C ±0.5 ±4.0 Gain Error (Note 3) ±0.5 ±4.0 LSB Gain Temperature Coefficient ±0.25 ppm/°C DYNAMIC SPECIFICATIONS(10kHz sine-wave input, 0V to 2.500Vp-p, 73ksps, fSCLK= 2.1MHz) Signal-to-Noise Plus MAX124_A/B 70 SINAD dB Distortion Ratio MAX124_C 71.5 MAX124_A/B -80 Total Harmonic Distortion THD Up to the 5th harmonic dB MAX124_C -88 MAX124_A/B 80 Spurious-Free Dynamic Range SFDR dB MAX124_C 88 Small-Signal Bandwidth -3dB rolloff 2.25 MHz Full-Power Bandwidth 1.0 MHz CONVERSION RATE Conversion Time tCONV 5.5 7.5 µs Track/Hold Acquisition Time tACQ 1.5 µs Throughput Rate fSCLK= 2.1MHz 73 ksps Aperture Delay tAPR Figure 8 30 ns Aperture Jitter <50 ps ANALOG INPUT Input Voltage Range 0 VREF V Input Capacitance 16 pF 2 _______________________________________________________________________________________

+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO ELECTRICAL CHARACTERISTICS (continued) M (VDD= +2.7V to +3.6V (MAX1240); VDD= +2.7V to +5.25V (MAX1241); 73ksps, fSCLK= 2.1MHz (50% duty cycle); MAX1240—4.7µF A capacitor at REF pin, MAX1241—external reference; VREF= 2.500V applied to REF pin; TA= TMINto TMAX; unless otherwise noted.) X PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1 INTERNAL REFERENCE(MAX1240 only) 2 REF Output Voltage TA= +25°C 2.480 2.500 2.520 V 4 REF Short-Circuit Current 30 mA 0 MAX1240AC/BC ±30 ±50 / MAX1240AE/BE ±30 ±60 M REF Temperature Coefficient ppm/°C MAX1240AM/BM ±30 ±80 ppm/°C A MAX1240C ±30 X Load Regulation (Note 4) 0mA to 0.2mA output load 0.35 1 Capacitive Bypass at REF 4.7 µF 2 EXTERNAL REFERENCE(VREF= 2.500V) 4 Input Voltage Range 1.00 VDD + V 1 50mV Input Current 100 150 µA Input Resistance 18 25 kΩ REF Input Current in Shutdown VSHDN= 0V ±0.01 10 µA Capacitive Bypass at REF 0.1 µF DIGITAL INPUTS: SCLK, CCSS, SSHHDDNN VDD≤3.6V 2.0 SCLK, CSInput High Voltage VIH V VDD> 3.6V (MAX1241) 3.0 SCLK, CSInput Low Voltage VIL 0.8 V SCLK, CSInput Hysteresis VHYST 0.2 V SCLK, CSInput Leakage IIN VIN= 0V or VDD ±0.01 ±1 µA SCLK, CSInput Capacitance CIN (Note 5) 15 pF SHDNInput High Voltage VSH VDD - 0.4 V SHDNInput Low Voltage VSL 0.4 V SHDNInput Current VSHDN= 0V or VDD ±4.0 µA SHDNInput Mid Voltage VSM 1.1 VDD - 1.1 V SHDNVoltage, Unconnected VFLT SHDN= unconnected VDD/2 V SHDNMax Allowed Leakage, SHDN= unconnected ±100 nA Mid Input DIGITAL OUTPUT: DOUT ISINK= 5mA 0.4 Output Voltage Low VOL V ISINK= 16mA 0.8 Output Voltage High VOH ISOURCE= 0.5mA VDD - 0.5 V Three-State Leakage Current IL CS= VDD ±0.01 ±10 µA Three-State Output Capacitance COUT CS= VDD (Note 5) 15 pF _______________________________________________________________________________________ 3

+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO 1 ELECTRICAL CHARACTERISTICS (continued) 4 (VDD= +2.7V to +3.6V (MAX1240); VDD= +2.7V to +5.25V (MAX1241); 73ksps, fSCLK= 2.1MHz (50% duty cycle); MAX1240—4.7µF 2 capacitor at REF pin, MAX1241—external reference; VREF= 2.500V applied to REF pin; TA= TMINto TMAX; unless otherwise noted.) 1 PARAMETERS SYMBOL CONDITIONS MIN TYP MAX UNITS X POWER REQUIREMENTS A MAX1240 2.7 3.6 M Supply Voltage VDD MAX1241 2.7 5.25 V / MAX1240A/B VDD = 3.6V 1.4 2.0 0 VDD = 3.6V MAX1240C 1.4 3.5 4 Operating VDD = 3.6V 0.9 1.5 2 MAX1241A/B mA mode VDD = 5.25V 1.6 2.5 1 Supply Current IDD X MAX1241C VDD = 3.6V 0.9 2.8 VDD = 5.25V 1.6 3.8 A Power-down, digital inputs VDD = 3.6V 1.9 10 M µA at 0V or VDD VDD = 5.25V 3.5 15 Supply Rejection PSR (Note 5) ±0.3 mV TIMING CHARACTERISTICS (Figure 8) (VDD= +2.7V to +3.6V (MAX1240); VDD= +2.7V to +5.25V (MAX1241); TA= TMINto TMAX, unless otherwise noted.) PARAMETERS SYMBOL CONDITIONS MIN TYP MAX UNITS Acquisition Time tACQ CS= VDD(Note 6) 1.5 µs Figure 1, MAX124_ _C/E 20 200 SCLK Fall to Output Data Valid tDO CLOAD= 50pF MAX124_ _M 20 240 ns CSFall to Output Enable tDV Figure 1, CLOAD= 50pF 240 ns CSRise to Output Disable tTR Figure 2, CLOAD= 50pF 240 ns SCLK Clock Frequency fSCLK 0 2.1 MHz SCLK Pulse Width High tCH 200 ns SCLK Pulse Width Low tCL 200 ns SCLK Low to CSFall Setup Time tCS0 50 ns DOUT Rise to SCLK Rise (Note 5) tSTR 0 ns CSPulse Width tCS 240 ns Note 1: Tested at VDD= +2.7V. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offset have been calibrated. Note 3: MAX1240—internal reference, offset nulled; MAX1241—external reference (VREF= +2.500V), offset nulled. Note 4: External load should not change during conversion for specified accuracy. Note 5: Guaranteed by design. Not subject to production testing. Note 6: Measured as [VFS(2.7V) - VFS(VDD(MAX)]. Note 7: To guarantee acquisition time, tACQ is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired. 4 _______________________________________________________________________________________

+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO M +2.7V A 6k X DOUT DOUT 1 2 6k CLOAD = 50pF CLOAD = 50pF 4 0 DGND DGND / M a) High-Z to V and V to V b) High-Z to V and V to V OH OL OH OL OH OL A Figure 1. Load Circuits for DOUT Enable Time X 1 +2.7V 2 4 6k 1 DOUT DOUT 6k CLOAD = 50pF CLOAD = 50pF DGND DGND a) VOH to High-Z b) VOLto High-Z Figure 2. Load Circuits for DOUT Disable Time __________________________________________Typical Operating Characteristics (VDD= 3.0V, VREF= 2.5V, fSCLK= 2.1MHz, CL= 20pF, TA = +25°C, unless otherwise noted.) OPERATING SUPPLY CURRENT OFFSET ERROR vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. TEMPERATURE vs. SUPPLY VOLTAGE ATING SUPPLY CURRENT (mA) 00111112........68024680 RCLO =D E∞ = 10101010M0A00X01240 MAX1241 MAX1241-D SUPPLY CURRENT (mA) 1111....0123 MAX1241 MAX1240 MAX1241-A/NEW OFFSET ERROR (LSB) 00000001........34567890 MAX1241-03 R PE 0.4 0.9 0.2 O 0.2 RLOAD = ∞ 0.1 CODE = 10101010000 0 0.8 0 2 3 4 5 6 -60 -20 20 60 100 140 2.25 2.75 3.25 3.75 4.25 4.75 5.25 SUPPLY VOLTAGE (V) TEMPERATURE (°C) SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 5

+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO 1 ____________________________Typical Operating Characteristics (continued) 4 (VDD= 3.0V, VREF= 2.5V, fSCLK= 2.1MHz, CL= 20pF, TA = +25°C, unless otherwise noted.) 2 1 SHUTDOWN SUPPLY CURRENT SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE vs. TEMPERATURE OFFSET ERROR vs. TEMPERATURE X 0/MA μCURRENT (A) 2433....5005 MAX1241-C/NEW μCURRENT (A) 33445.....05050 MAX1241-B R (LSB) 0000....5678 VDD = 2.7V MAX1241-06 4 UPPLY 2.0 UPPLY 2.5 T ERRO 0.4 2 WN S 1.5 WN S 2.0 FFSE 0.3 1 TDO 1.0 TDO 1.5 O 0.2 X HU HU 1.0 S 0.5 S 0.5 0.1 A 0 0 0 M 2.25 2.75 3.25 3.75 4.25 4.75 5.25 -60 -20 20 60 100 140 -55 -30 -5 20 45 70 95 120 145 SUPPLY VOLTAGE (V) TEMPERATURE (°C) TEMPERATURE (°C) MAX1240 GAIN ERROR GAIN ERROR INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE vs. TEMPERATURE vs. SUPPLY VOLTAGE 00..78 MAX1241-07 00..78 VDD = 2.7V MAX1241-08 22..55001250 MAX1241-0X 0.6 0.6 B) B) 2.5010 RROR (LS 00..45 RROR (LS 00..45 REF (V)2.5005 N E N E V GAI 0.3 GAI 0.3 2.5000 0.2 0.2 2.4995 0.1 0.1 0 0 2.4990 2.25 2.75 3.25 3.75 4.25 4.75 5.25 -55 -30 -5 20 45 70 95 120 145 2.25 2.75 3.25 3.75 4.25 4.75 5.25 SUPPLY VOLTAGE (V) TEMPERATURE (°C) VDD (V) MAX1240 INTERNAL REFERENCE VOLTAGE INTEGRAL NONLINEARITY INTEGRAL NONLINEARITY vs. TEMPERATURE vs. SUPPLY VOLTAGE vs. TEMPERATURE 22..550001 VDD = 3.6V MAX1241-0Y 11..02 MAX1241-09/NEW 11..02 VDD = 2.7V MAX1241-10/NEW 2.499 VDD = 2.7V 0.8 0.8 VREF (V)22..449978 INL (LSB) 0.6 INL (LSB) 0.6 0.4 MAX1240 0.4 2.496 MAX1240 2.495 0.2 MAX1241 0.2 MAX1241 2.494 0 0 -60 -20 20 60 100 140 2.25 2.75 3.25 3.75 4.25 4.75 5.25 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) SUPPLY VOLTAGE (V) TEMPERATURE (°C) 6 _______________________________________________________________________________________

+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO ____________________________Typical Operating Characteristics (continued) M (VDD= 3.0V, REF = 2.5V, fSCLK= 2.1MHz, CL= 20pF, TA = +25°C, unless otherwise noted.) A X INTEGRAL NONLINEARITY vs. CODE FFT PLOT 1 00..46 MAX1241-11A/NEW 200 ffASIANM =P L1E0 =kH 7z3, k2s.p5sVP-P MAX1241-TOC12A 240 -20 0.2 / B) -40 M INL (LSB) 0 MPLITUDE (d --6800 AX -0.2 A -100 1 -0.4 -120 2 4 -0.6 -140 0 1024 2048 3072 4096 0 18.75 37.50 1 CODE FREQUENCY (kHz) _______________________________________________________________________Pin Description PIN NAME FUNCTION 1 VDD Positive Supply Voltage: 2.7V to 3.6V, (MAX1240); 2.7V to 5.25V (MAX1241) 2 AIN Sampling Analog Input, 0V to VREFrange Three-Level Shutdown Input. Pulling SHDNlow shuts the MAX1240/MAX1241 down to 15µA (max) supply current. Both the MAX1240 and MAX1241 are fully operational with either SHDNhigh or 3 SHDN unconnected. For the MAX1240, pulling SHDNhigh enables the internal reference, and letting SHDN open disables the internal reference and allows for the use of an external reference. Reference Voltage for Analog-to-Digital Conversion. Internal 2.5V reference output for MAX1240; 4 REF bypass with 4.7µF capacitor. External reference voltage input for MAX1241, or for MAX1240 with the internal reference disabled. Bypass REF with a minimum of 0.1µF when using an external reference. 5 GND Analog and Digital Ground Serial Data Output. Data changes state at SCLK’s falling edge. DOUT is high impedance when CSis 6 DOUT high. Active-Low Chip Select initiates conversions on the falling edge. When CSis high, DOUT is high 7 CS impedance. 8 SCLK Serial Clock Input. SCLK clocks data out at rates up to 2.1MHz. _______________________________________________________________________________________ 7

+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO 1 +2.7V to +3.6V* *VDD,MAX = +5.25V (MAX1241) 4 **4.7μF (MAX1240) 12-BIT CAPACITIVE DAC 0.1μF (MAX1241) 2 REF 1 4.7μF 0.1μF 1 8 C COMPARATOR X VDD SCLK AIN TRACK INPUT HOLD ZERO - + A ANALOG INPUT 2 AIN MAX1240 CS 7 SERIAL 16pF 0V TO VREF MAX1241 INTERFACE HOLD 9k M SHUTDOWN 3 SHDN DOUT 6 CSWITCH RIN / INPUT HOLD 0 TRACK 4 5 AT THE SAMPLING INSTANT, 4 REFERENCE REF GND THE INPUT SWITCHES FROM 2 (MAX1241 OINNPLUYT) C** GND AIN TO GND. 1 X Figure 3. Operational Diagram Figure 4. Equivalent Input Circuit A M _______________Detailed Description During acquisition, the analog input (AIN) charges capacitor C . Bringing CS low ends the acquisition HOLD Converter Operation interval. At this instant, the T/H switches the input side The MAX1240/MAX1241 use an input track/hold (T/H) of C to GND. The retained charge on C repre- HOLD HOLD and successive-approximation register (SAR) circuitry sents a sample of the input, unbalancing node ZERO at to convert an analog input signal to a digital 12-bit out- the comparator’s input. put. No external-hold capacitor is needed for the T/H. In hold mode, the capacitive digital-to-analog converter Figure 3 shows the MAX1240/MAX1241 in its simplest (DAC) adjusts during the remainder of the conversion configuration. The MAX1240/MAX1241 convert input cycle to restore node ZERO to 0V within the limits of 12- signals in the 0V to V range in 9µs, including T/H REF bit resolution. This action is equivalent to transferring a acquisition time. The MAX1240’s internal reference is charge from C to the binary-weighted capacitive trimmed to 2.5V, while the MAX1241 requires an external HOLD DAC, which in turn forms a digital representation of the reference. Both devices accept voltages from 1.0V to analog input signal. At the conversion’s end, the input VDD. The serial interface requires only three digital lines side of C switches back to AIN, and C (SCLK, CS, and DOUT) and provides an easy interface HOLD HOLD charges to the input signal again. to microprocessors (µPs). The time required for the T/H to acquire an input signal The MAX1240/MAX1241 have two modes: normal and is a function of how quickly its input capacitance is shutdown. Pulling SHDNlow shuts the device down and charged. If the input signal’s source impedance is high, reduces supply current below 10µA (VDD ≤3.6V), while the acquisition time lengthens and more time must be pulling SHDN high or leaving it open puts the device allowed between conversions. The acquisition time into operational mode. Pulling CSlow initiates a conver- (tACQ) is the maximum time the device takes to acquire sion. The conversion result is available at DOUT in the signal, and is also the minimum time needed for the unipolar serial format. The serial data stream consists signal to be acquired. Acquisition time is calculated by: of a high bit, signaling the end of conversion (EOC), fol- lowed by the data bits (MSB first). tACQ= 9(RS+ RIN) x 16pF where R = 9kΩ, R = the input signal’s source imped- Analog Input IN S ance, and t is never less than 1.5µs. Source imped- Figure 4 illustrates the sampling architecture of the ana- ances belowAC 1QkΩ do not significantly affect the ADC’s log-to-digital converter’s (ADC’s) comparator. The full- AC performance. scale input voltage is set by the voltage at REF. Higher source impedances can be used if a 0.01µF Track/Hold capacitor is connected to the analog input. Note that In track mode, the analog signal is acquired and stored the input capacitor forms an RC filter with the input in the internal hold capacitor. In hold mode, the T/H source impedance, limiting the ADC’s input signal switch opens and maintains a constant input to the bandwidth. ADC’s SAR section. 8 _______________________________________________________________________________________

+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO Input Bandwidth External Reference M The ADCs’ input tracking circuitry has a 2.25MHz small- The MAX1240/MAX1241 operate with an external refer- signal bandwidth, so it is possible to digitize high- ence at the REF pin. To use the MAX1240 with an A speed transient events and measure periodic signals external reference, disable the internal reference by let- X with bandwidths exceeding the ADC’s sampling rate by ting SHDN open. Stay within the +1.0V to V voltage DD 1 using undersampling techniques. To avoid aliasing of range to achieve specified accuracy. The minimum unwanted high-frequency signals into the frequency input impedance is 18kΩ for DC currents. During con- 2 band of interest, anti-alias filtering is recommended. version, the external reference must be able to deliver 4 up to 250µA of DC load current and have an output 0 Analog Input Protection impedance of 10Ω or less. The recommended mini- / Internal protection diodes, which clamp the analog mum value for the bypass capacitor is 0.1µF. If the ref- M input to VDD and GND, allow the input to swing from erence has higher output impedance or is noisy, A GND - 0.3V to V + 0.3V without damage. However, DD bypass it close to the REF pin with a 4.7µF capacitor. for accurate conversions near full scale, the input must X not exceed V by more than 50mV, or be lower than ____________________Serial Interface DD 1 GND by 50mV. Initialization after Power-Up and 2 If the analog input exceeds 50mV beyond the sup- Starting a Conversion 4 plies, limit the input current to 2mA. When power is first applied, and if SHDN is not pulled 1 Internal Reference (MAX1240) low, it takes the fully discharged 4.7µF reference The MAX1240 has an on-chip voltage reference bypass capacitor up to 20ms to provide adequate trimmed to 2.5V. The internal reference output is con- charge for specified accuracy. With an external refer- nected to REF and also drives the internal capacitive ence, the internal reset time is 10µs after the power DAC. The output can be used as a reference voltage supplies have stabilized. No conversions should be source for other components and can source up to performed during these times. 400µA. Bypass REF with a 4.7µF capacitor. Larger To start a conversion, pull CS low. At CS’s falling edge, capacitors increase wake-up time when exiting shut- the T/H enters its hold mode and a conversion is initiat- down (see the section Using SHDNto Reduce Supply ed. After an internally timed conversion period, the end Current). The internal reference is enabled by pulling the of conversion is signaled by DOUT pulling high. Data SHDNpin high. Letting SHDNopen disables the internal can then be shifted out serially with the external clock. reference, which allows the use of an external reference, as described in theExternal Referencesection. COMPLETE CONVERSION SEQUENCE CS tWAKE SHDN DOUT CONVERSION 0 CONVERSION 1 POWERED UP POWERED DOWN POWERED UP Figure 5. Shutdown Sequence _______________________________________________________________________________________ 9

+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO 1 Using SHDN to Reduce Supply Current 24 Psvehoruwstietoinrn gsc .o dFnoisgwuunmr ept h6tei os nMh ocAwaXsn1 2ab4 ep0 l/orMet dAoufX ca1ev2de4r 1as gibgeen tsiwfuicepaepnnlyt l ycc oubnry-- 10 VRCDLOODDA =ED V ==R 0E∞1F, 0 =C1 30L.O10A0VD1 0=0 5000p F MAX1241 FIG. 06a 1 rent versus conversion rate. Because the MAX1241 mA) 1 X uses an external reference voltage (assumed to be pre- ET ( N R A sent continuously), it “wakes up” from shutdown more UR 0.1 C M quickly (in 4µs) and therefore provides lower average LY MAX1240 supply currents. The wake-up time (tWAKE) is the time UPP / from when SHDNis deasserted to the time when a con- S 0.01 0 version may be initiated (Figure 5). For the MAX1240, MAX1241 4 this time depends on the time in shutdown (Figure 7) 2 because the external 4.7µF reference bypass capacitor 0.001 0.1 1 10 100 1k 10k 100k 1 loses charge slowly during shutdown. CONVERSION RATE (Hz) X External Clock Figure 6. Average Supply Current vs. Conversion Rate A The actual conversion does not require the external clock. This allows the conversion result to be read back M at the µP’s convenience at any clock rate from up to 2c.lo1cMkH pz.h aTshee icsl oact kl edaustty 2c0y0cnles . isD ou nnreost trruicnte tdh eif celaocchk 1.0 MAX1240/41-07a while a conversion is in progress. 0.8 ms) Timing and Control Y ( A 0.6 Conversion-start and data-read operations are controlled EL D by the CS and SCLK digital inputs. The timing diagrams UP of Figures 8 and 9 outline serial-interface operation. ER- 0.4 W O A CS falling edge initiates a conversion sequence: the P T/H stage holds the input voltage, the ADC begins to 0.2 convert, and DOUT changes from high impedance to logic low. SCLK must be kept low during the conver- 0.0 sion. An internal register stores the data when the con- 0.001 0.01 0.1 1 10 version is in progress. TIME IN SHUTDOWN (sec) Figure 7. Typical Reference Power-Up Delay vs. Time in Shutdown CS 1 4 8 12 16 SCLK DOUT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 EOC CONVERSION TRAILING INTERFACE IDLE EOC CLOCK OUT SERIAL DATA IDLE IN PROGRESS ZEROS TRACK/HOLD STATE TRACK HOLD TRACK HOLD 0.24μs 7.5μs (tCONV) 0μs 12.5 × 0.476μs = 5.95μs 0μs (tCS) CYCLE TIME TOTAL = 13.7μs Figure 8. Interface Timing Sequence 10 ______________________________________________________________________________________

+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO M tCS CS A … tCS0 X tCH … 1 SCLK tDO 2 tCL tTR 4 tDV tCONV … 0 DOUT B2 B1 B0 tAPR tSTR /M INTERNAL (TRACK/ACQUIRE) (HOLD) … (TRACK/ACQUIRE) A T/H X 1 Figure 9. Detailed Serial-Interface Timing 2 End of conversion (EOC) is signaled by DOUT going the conversion’s LSB. After the specified minimum time 4 high. DOUT’s rising edge can be used as a framing (tCS), CS can be pulled low again to initiate the next 1 signal. SCLK shifts the data out of this register any time conversion. after the conversion is complete. DOUT transitions on Output Coding and Transfer Function SCLK’s falling edge. The next falling clock edge pro- The data output from the MAX1240/MAX1241 is binary, duces the MSB of the conversion at DOUT, followed by and Figure 10 depicts the nominal transfer function. the remaining bits. Since there are 12 data bits and one Code transitions occur halfway between successive- leading high bit, at least 13 falling clock edges are needed to shift out these bits. Extra clock pulses occur- integer LSB values. If VREF = +2.500V, then 1 LSB = 610µV or 2.500V/4096. ring after the conversion result has been clocked out, and prior to a rising edge of CS, produce trailing zeros ____________Applications Information at DOUT and have no effect on converter operation. Connection to Standard Interfaces Minimum cycle time is accomplished by using DOUT’s rising edge as the EOC signal. Clock out the data with The MAX1240/MAX1241 serial interface is fully compat- 12.5 clock cycles at full speed. Pull CShigh after reading ible with SPI/QSPI and MICROWIRE standard serial interfaces (Figure 11). If a serial interface is available, set the CPU’s serial OUTPUT CODE FULL-SCALE interface in master mode so the CPU generates the ser- 11…111 TRANSITION ial clock. Choose a clock frequency up to 2.1MHz. 11…110 1) Use a general-purpose I/O line on the CPU to pull CS 11…101 low. Keep SCLK low. 2) Wait the for the maximum conversion time specified before activating SCLK. Alternatively, look for a DOUT FS = VREF - 1 LSB rising edge to determine the end of conversion. 1 LSB = VREF 3) Activate SCLK for a minimum of 13 clock cycles. The 4096 first falling clock edge produces the MSB of the DOUT conversion. DOUT output data transitions on 00…011 SCLK’s falling edge and is available in MSB-first for- 00…010 mat. Observe the SCLK to DOUT valid timing char- 00…001 acteristic. Data can be clocked into the µP on 00…000 SCLK’s rising edge. 0 1 2 3 FS 4) Pull CS high at or after the 13th falling clock edge. If INPUT VOLTAGE (LSBs) FS - 3/2 LSB CS remains low, trailing zeros are clocked out after the LSB. Figure 10. Unipolar Transfer Function, Full Scale (FS) = VREF- 1 LSB, Zero Scale (ZS) = GND ______________________________________________________________________________________ 11

+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO 1 5) With CS= high, wait the minimum specified time, tCS, 4 before initiating a new conversion by pulling CS low. If a conversion is aborted by pulling CS high before I/O CS 2 the conversion’s end, wait for the minimum acquisi- SCK SCLK 1 tion time, tACQ, before starting a new conversion. MISO DOUT X +3V CS must be held low until all data bits are clocked out. A Data can be output in two bytes or continuously, as MAX1240 MAX1241 M shown in Figure 8. The bytes contain the result of the SS conversion padded with one leading 1, and trailing 0s. / a) SPI 0 SPI and MICROWIRE 4 When using SPI or MICROWIRE, set CPOL = 0 and CS CS 2 CPHA = 0. Conversion begins with a CS falling edge. SCK SCLK 1 DOUT goes low, indicating a conversion in progress. Wait until DOUT goes high or until the maximum specified MISO DOUT X +3V 7.5µs conversion time elapses. Two consecutive 1-byte A reads are required to get the full 12 bits from the ADC. MAX1240 M DOUT output data transitions on SCLK’s falling edge and MAX1241 SS is clocked into the µP on SCLK’s rising edge. b) QSPI The first byte contains a leading 1, and seven bits of con- version result. The second byte contains the remaining five bits and three trailing zeros. See Figure 11 for con- I/O CS nections and Figure 12 for timing. SK SCLK SI DOUT QSPI Set CPOL = CPHA = 0. Unlike SPI, which requires two 1-byte reads to acquire the 12 bits of data from the ADC, MAX1240 QSPI allows the minimum number of clock cycles neces- MAX1241 sary to clock in the data. The MAX1240/MAX1241 requires 13 clock cycles from the µP to clock out the 12 c) MICROWIRE bits of data with no trailing zeros (Figure 13). The maxi- mum clock frequency to ensure compatibility with QSPI is Figure 11. Common Serial-Interface Connections to the 2.097MHz. MAX1241 Layout, Grounding, and Bypassing system ground should be connected to this single-point For best performance, use printed circuit boards. Wire- analog ground. The ground return to the power supply for wrap boards are not recommended. Board layout should this ground should be low impedance and as short as ensure that digital and analog signal lines are separated possible for noise-free operation. from each other. Do not run analog and digital (especially High-frequency noise in the V power supply may affect clock) lines parallel to one another, or digital lines under- DD the ADC’s high-speed comparator. Bypass this supply to neath the ADC package. the single-point analog ground with 0.1µF and 4.7µF Figure 14 shows the recommended system ground con- bypass capacitors. Minimize capacitor lead lengths for nections. Establish a single-point analog ground (“star” best supply-noise rejection. If the power supply is very ground point) at GND, separate from the logic ground. noisy, a 10Ωresistor can be connected as a lowpass filter Connect all other analog grounds and DGND to this star to attenuate supply noise (Figure 14). ground point for further noise reduction. No other digital 12 ______________________________________________________________________________________

+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO M 1ST BYTE READ 2ND BYTE READ A SCLK X CS tCONV 1 DOUT* D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 HIGH-Z 2 MSB LSB 4 0 EOC / *WHEN CS IS HIGH, DOUT = HIGH -Z M Figure 12. SPI/MICROWIRE Serial Interface Timing (CPOL = CPHA = 0) A X 1 2 SCLK 4 CS 1 tCONV HIGH-Z DOUT* D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB EOC *WHEN CS IS HIGH, DOUT = HIGH -Z Figure 13. QSPI Serial Interface Timing (CPOL = CPHA = 0) SUPPLIES +3V +3V GND R* = 10Ω 4.7μF 0.1μF VDD GND +3V DGND DIGITAL MAX1240 CIRCUITRY MAX1241 *OPTIONAL Figure 14. Power-Supply Grounding Condition ______________________________________________________________________________________ 13

+2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO 1 __Ordering Information (continued) Chip Information 4 PROCESS: BiCMOS 2 PART TEMP RANGE PIN- INL PACKAGE (LSB) SUBSTRATE CONNECTED TOGND 1 MAX1240AEPA+ -40°C to +85°C 8 PDIP ±1/2 X MAX1240BEPA+ -40°C to +85°C 8 PDIP ±1 A MAX1240CEPA+ -40°C to +85°C 8 PDIP ±1 Package Information M MAX1240AESA+ -40°C to +85°C 8 SO ±1/2 For the latest package outline information and land / MAX1240BESA+ -40°C to +85°C 8 SO ±1 0 patterns, go to www.maxim-ic.com/packages. Note MAX1240CESA+ -40°C to +85°C 8 SO ±1 4 that a “+”, “#”, or “-” in the package code indicates MAX1240AMJA+ -55°C to +125°C 8 CERDIP† ±1/2 RoHS status only. Package drawings may show a dif- 2 MAX1240BMJA+ -55°C to +125°C 8 CERDIP† ±1 ferent suffix character, but the drawing pertains to the 1 MAX1240CMJA+ -55°C to +125°C 8 CERDIP† ±1 package regardless of RoHS status. X MAX1241ACPA+ 0°C to +70°C 8 PDIP ±1/2 A PACKAGE PACKAGE OUTLINE LAND MAX1241BCPA+ 0°C to +70°C 8 PDIP ±1 TYPE CODE NO. PATTERN NO. M MAX1241CCPA+ 0°C to +70°C 8 PDIP ±1 8 PDIP P8+2 21-004 3 — MAX1241ACSA+ 0°C to +70°C 8 SO ±1/2 8 SO S8+5 21-004 1 90-0096 MAX1241BCSA + 0°C to +70°C 8 SO ±1 8 CERDIP J8+2 21-004 5 — MAX1241CCSA+ 0°C to +70°C 8 SO ±1 MAX1241BC/D 0°C to +70°C Dice* ±1 MAX1241AEPA+ -40°C to +85°C 8 PDIP ±1/2 MAX1241BEPA+ -40°C to +85°C 8 PDIP ±1 MAX1241CEPA+ -40°C to +85°C 8 PDIP ±1 MAX1241AESA+ -40°C to +85°C 8 SO ±1/2 MAX1241BESA+ -40°C to +85°C 8 SO ±1 MAX1241CESA+ -40°C to +85°C 8 SO ±1 MAX1241AMJA+ -55°C to +125°C 8 CERDIP† ±1/2 MAX1241BMJA+ -55°C to +125°C 8 CERDIP† ±1 MAX1241CMJA+ -55°C to +125°C 8 CERDIP† ±1 +Denotes lead(Pb)-free/RoHS-compliant package. *Dice are specified at TA=+25°C, DC parameters only. †Contact factory for availability and processing to MIL-STD-883. 14 ______________________________________________________________________________________

2.7V, Low-Power, 12-Bit Serial ADCs in 8-Pin SO Revision History M A REVISION REVISION PAGES DESCRIPTION NUMBER DATE CHANGED X 1 1, 2, 3, 7, 9, 14, 3 3/10 Added automotive grade to data sheet 15, 16 2 4 4 6/10 Future product note removed from one part in the Ordering Information 1 0 5 8/10 Removed MAX1240BC/D and add MAX1240CC/D 1 / M A X 1 2 4 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 15 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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