LT1175 500mA Negative Low Dropout Micropower Regulator FEATURES D ESCRIPTION n Operating Current: 45μA The LT®1175 is a negative micropower low dropout n Adjustable Current Limit regulator. It features 45μA quiescent current, dropping n Low Voltage Linear Dropout Characteristics to 10μA in shutdown. A new reference amplifi er topology n Stable with Wide Range of Output Capacitors gives precision DC characteristics along with the ability to n Shutdown Current: 10μA maintain good loop stability with an extremely wide range n Positive or Negative Shutdown Logic of output capacitors. Very low dropout voltage and high n Fixed 5V and Adjustable Versions effi ciency are obtained with a unique power transistor n Tolerates Reverse Output Voltage anti-saturation design. Adjustable and fi xed 5V versions n Available in 8-pin PDIP and SO Packages, 3-lead are available. SOT-223, 5-Pin Surface Mount DD and Through-Hole Several new features make the LT1175 very user-friendly. TO-220 Packages The SHDN pin can interface directly to either positive or negative logic levels. Current limit is user-selectable at APPLICATIONS 200mA, 400mA, 600mA and 800mA. The output can be forced to reverse voltage without damage or latchup. Un- n Analog Systems like some earlier designs, the increase in quiescent current n Modems during a dropout condition is actively limited. n Instrumentation n A/D and D/A Converters The LT1175 has complete blowout protection with current n Interface Drivers limiting, power limiting and thermal shutdown. Special n Battery-Powered Systems attention was given to the problem of high temperature L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear operation with micropower operating currents, preventing Technology Corporation. All other trademarks are the property of their respective owners. output voltage rise under no-load conditions. The LT1175 is available in 8-pin PDIP and SO packages, 3-lead SOT- 223 as well as 5-pin surface mount DD and through-hole TO-220 packages. The 8-pin SO package is specially constructed for low thermal resistance. TYPICAL APPLICATION Minimum Input-to-Output Voltage 1.0 Typical LT1175 Connection TJ = 25°C E (V) 0.8 ILIM2, ILIM4 TIED TO VIN + + AG CIN* C≥ O0U.1TμF VOLT 0.6 SHDN GND T U –VIN VIN SENSE –U5PV TO 500mA UTP O 0.4 ILIM2 LT1175-5 O- T ILIM4 OUTPUT UT- P 0.2 N I *CINIS NEEDED ONLY IF REGULATOR IS MORE THAN 6" FROM INPUT SUPPLY CAPACITOR. SEE APPLICATIONS INFORMATION 0 SECTION FOR DETAILS 1175 TA01 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 OUTPUT CURRENT (A) 1175 TA02 1175ff 1

LT1175 ABSOLUTE MAXIMUM RATINGS (Note 1) Input Voltage (Transient 1 sec, Note 12) ...................25V Output Reverse Voltage ..............................................2V Input Voltage (Continuous) .......................................20V SHDN Pin to GND Pin Voltage (Note 3) ........13.5V, –20V Input-to-Output Differential Voltage (Note 13) ..........20V SHDN Pin to V Pin Voltage .............................30V, –5V IN 5V SENSE Pin (with Respect to GND Pin) .........2V, –10V Operating Junction Temperature Range (Note 2) ADJ SENSE Pin LT1175C .................................................0°C to 125°C (with Respect to OUTPUT Pin) ...................20V, –0.5V LT1175I ..............................................–40°C to 125°C 5V SENSE Pin LT1175MP ..........................................–55°C to 125°C (with Respect to OUTPUT Pin) ......................20V, –7V Storage Temperature Range ..................–65°C to 150°C Lead Temperature (Soldering, 10 sec)...................300°C PIN CONFIGURATION FRONT VIEW TOP VIEW FRONT VIEW 3 GND VIN 1 8 VIN 5 SHDN TAB 4 GND TAB IS ILIM2 2 7 ILIM4 IS 3 VIN VIN 2 VIN OUTPUT 3 6 SHDN VIN 2 SENSE SENSE 4 5 GND 1 OUTPUT 1 OUTPUT Q PACKAGE ST PACKAGE N8 PACKAGE 5-LEAD PLASTIC DD-PAK 3-LEAD PLASTIC SOT-223 θJA = 880-°LCE/AWD T POD 1IP20°C/W DEPθEJNA D=I N27G° CO/NW P TCO M 6O0U°CN/TWIN G. WITH BAθCJKAP =L A50N°EC A/WND 10cm2 DEPENDING ON PC BOARD LAYOUT SEE DATA SHEET FOR DETAILS TOPSIDE LAND SOLDERED TO TAB TOP VIEW VIN 1 8 VIN FRONT VIEW ILIM2 2 7 ILIM4 OUTPUT 3 6 SHDN 5 SHDN 4 GND SENSE 4 5 GND 3 VIN 2 SENSE S8 PACKAGE 8-LEAD PLASTIC SO 1 OUTPUT θJA = 60°C/W TO 100°C/W TAB IS DEPENDING ON PC BOARD LAYOUT VIN T PACKAGE 5-LEAD PLASTIC TO-220 PINS 1, 8 ARE INTERNALLY CONNECTED TO DIE ATTACH PADDLE FOR HEAT SINKING. ELECTRICAL CONTACT CAN BE MADE TO EITHER PIN. FOR BEST THERMAL RESISTANCE, θJA = 50°C/W, θJC = 5°C/W PINS 1, 8 SHOULD BE CONNECTED TO AN EXPANDED LAND THAT IS OVER AN INTERNAL OR BACKSIDE PLANE. SEE APPLICATIONS INFORMATION 1175ff 2

LT1175 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT1175CN8#PBF LT1175CN8#TRPBF LT1175CN8 8-Lead Plastic Dip 0°C to 125°C LT1175CN8-5#PBF LT1175CN8-5#TRPBF LT1175CN8-5 8-Lead Plastic Dip 0°C to 125°C LT1175CS8#PBF LT1175CS8#TRPBF 1175 8-Lead Plastic SO 0°C to 125°C LT1175CS8-5#PBF LT1175CS8-5#TRPBF 11755 8-Lead Plastic SO 0°C to 125°C LT1175CST-5#PBF LT1175CST-5#TRPBF 11755 3-Lead Plastic SOT-223 0°C to 125°C LT1175CQ#PBF LT1175CQ#TRPBF LT1175CQ 5-Lead Plastic DD-Pak 0°C to 125°C LT1175CQ-5#PBF LT1175CQ-5#TRPBF LT1175CQ-5 5-Lead Plastic DD-Pak 0°C to 125°C LT1175CT#PBF LT1175CT#TRPBF LT1175CT 5-Lead Plastic TO-220 0°C to 125°C LT1175CT-5#PBF LT1175CT-5#TRPBF LT1175CT-5 5-Lead Plastic TO-220 0°C to 125°C LT1175IN8#PBF LT1175IN8#TRPBF LT1175IN8 8-Lead Plastic Dip –40°C to 125°C LT1175IN8-5#PBF LT1175IN8-5#TRPBF LT1175IN8-5 8-Lead Plastic Dip –40°C to 125°C LT1175IS8#PBF LT1175IS8#TRPBF 1175I 8-Lead Plastic SO –40°C to 125°C LT1175IS8-5#PBF LT1175IS8-5#TRPBF 1175I5 8-Lead Plastic SO –40°C to 125°C LT1175IST-5#PBF LT1175IST-5#TRPBF 1175I5 3-Lead Plastic SOT-223 –40°C to 125°C LT1175IQ#PBF LT1175IQ#TRPBF LT1175IQ 5-Lead Plastic DD-Pak –40°C to 125°C LT1175IQ-5#PBF LT1175IQ-5#TRPBF LT1175IQ-5 5-Lead Plastic DD-Pak –40°C to 125°C LT1175IT#PBF LT1175IT#TRPBF LT1175IT 5-Lead Plastic TO-220 –40°C to 125°C LT1175IT-5#PBF LT1175IT-5#TRPBF LT1175IT-5 5-Lead Plastic TO-220 –40°C to 125°C LT1175MPS8#PBF LT1175MPS8#TRPBF 1175MP 8-Lead Plastic SO –55°C to 125°C LT1175MPS8-5#PBF LT1175MPS8-5#TRPBF 175MP5 8-Lead Plastic SO –55°C to 125°C LT1175MPQ#PBF LT1175MPQ#TRPBF LT1175MPQ 5-Lead Plastic DD-Pak –55°C to 125°C LT1175MPQ-5#PBF LT1175MPQ-5#TRPBF LT1175MPQ-5 5-Lead Plastic DD-Pak –55°C to 125°C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT1175CN8 LT1175CN8#TR LT1175CN8 8-Lead Plastic Dip 0°C to 125°C LT1175CN8-5 LT1175CN8-5#TR LT1175CN8-5 8-Lead Plastic Dip 0°C to 125°C LT1175CS8 LT1175CS8#TR 1175 8-Lead Plastic SO 0°C to 125°C LT1175CS8-5 LT1175CS8-5#TR 11755 8-Lead Plastic SO 0°C to 125°C LT1175CST-5 LT1175CST-5#TR 11755 3-Lead Plastic SOT-223 0°C to 125°C LT1175CQ LT1175CQ#TR LT1175CQ 5-Lead Plastic DD-Pak 0°C to 125°C LT1175CQ-5 LT1175CQ-5#TR LT1175CQ-5 5-Lead Plastic DD-Pak 0°C to 125°C LT1175CT LT1175CT#TR LT1175CT 5-Lead Plastic TO-220 0°C to 125°C LT1175CT-5 LT1175CT-5#TR LT1175CT-5 5-Lead Plastic TO-220 0°C to 125°C LT1175IN8 LT1175IN8#TR LT1175IN8 8-Lead Plastic Dip –40°C to 125°C LT1175IN8-5 LT1175IN8-5#TR LT1175IN8-5 8-Lead Plastic Dip –40°C to 125°C LT1175IS8 LT1175IS8#TR 1175I 8-Lead Plastic SO –40°C to 125°C LT1175IS8-5 LT1175IS8-5#TR 1175I5 8-Lead Plastic SO –40°C to 125°C LT1175IST-5 LT1175IST-5#TR 1175I5 3-Lead Plastic SOT-223 –40°C to 125°C LT1175IQ LT1175IQ#TR LT1175IQ 5-Lead Plastic DD-Pak –40°C to 125°C LT1175IQ-5 LT1175IQ-5#TR LT1175IQ-5 5-Lead Plastic DD-Pak –40°C to 125°C 1175ff 3

LT1175 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT1175IT LT1175IT#TR LT1175IT 5-Lead Plastic TO-220 –40°C to 125°C LT1175IT-5 LT1175IT-5#TR LT1175IT-5 5-Lead Plastic TO-220 –40°C to 125°C LT1175MPS8 LT1175MPS8#TR 1175MP 8-Lead Plastic SO –55°C to 125°C LT1175MPS8-5 LT1175MPS8-5#TR 175MP5 8-Lead Plastic SO –55°C to 125°C LT1175MPQ LT1175MPQ#TR LT1175MPQ 5-Lead Plastic DD-Pak –55°C to 125°C LT1175MPQ-5 LT1175MPQ-5#TR LT1175MPQ-5 5-Lead Plastic DD-Pak –55°C to 125°C Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V = 5V, V = 7V, I = 0, V = 3V, I and I tied to V . A OUT IN OUT SHDN LIM2 LIM4 IN To avoid confusion with “min” and “max” as applied to negative voltages, all voltages are shown as absolute values except where polarity is not obvious. PARAMETER CONDITIONS MIN TYP MAX UNITS Feedback Sense Voltage Adjustable Part 3.743 3.8 3.857 V Fixed 5V Part 4.93 5.0 5.075 V Output Voltage Initial Accuracy Adjustable, Measured at 3.8V Sense 0.5 1.5 % Fixed 5V 0.5 1.5 % Output Voltage Accuracy (All Conditions) V – V = 1V to V = 20V, I = 0A to 500mA l 1.5 2.5 % IN OUT IN OUT P = 0 to P , T = T to T (Note 4) MAX J MIN MAX Quiescent Input Supply Current V – V ≤ 12V 45 65 μA IN OUT l 80 μA GND Pin Current Increase with Load (Note 5) l 10 20 μA/mA Input Supply Current in Shutdown V = 0V 10 20 μA SHDN l 25 μA Shutdown Thresholds (Note 10) Either Polarity On SHDN Pin (C-, I-Grades) l 0.8 2.5 V Either Polarity On SHDN Pin (MP-Grade) l 0.8 2.6 V SHDN Pin Current (Note 3) V = 0V to 10V (Flows Into Pin) l 4 8 μA SHDN V = –15V to 0V (Flows Into Pin) 1 4 μA SHDN Output Bleed Current in Shutdown (Note 7) V = 0V, V = 15V 0.1 1 μA OUT IN l 1 5 μA SENSE Pin Input Current (Adjustable Part Only, Current Flows Out of Pin) l 75 150 nA (Fixed Voltage Only, Current Flows Out of Pin) l 12 20 μA Dropout Voltage (Note 8) I = 25mA l 0.1 0.2 V OUT I = 100mA l 0.18 0.26 V OUT I = 500mA l 0.5 0.7 V OUT I Open, I = 300mA l 0.33 0.5 V LIM2 OUT I Open, I = 200mA l 0.3 0.45 V LIM4 OUT I , I Open, I = 100mA l 0.26 0.45 V LIM2 LIM4 OUT 1175ff 4

LT1175 ELECTRICAL CHARACTERISTICS The l denotes specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V = 5V, V = 7V, I = 0, V = 3V, I and I tied to V . A OUT IN OUT SHDN LIM2 LIM4 IN To avoid confusion with “min” and “max” as applied to negative voltages, all voltages are shown as absolute values except where polarity is not obvious. PARAMETER CONDITIONS MIN TYP MAX UNITS Current Limit (Note 12) V – V = 1V to 12V l 520 800 1300 mA IN OUT I Open l 390 600 975 mA LIM2 I Open l 260 400 650 mA LIM4 I , I Open l 130 200 325 mA LIM2 LIM4 Line Regulation (Note 11) V – V = 1V to V = 20V l 0.003 0.015 %/V IN OUT IN Load Regulation (Note 6, 11) I = 0mA to 500mA l 0.1 0.35 % OUT Thermal Regulation P = 0 to P (Notes 4, 9) 5-Pin Packages 0.04 0.1 %/W MAX 8-Pin Packages 0.1 0.2 %/W Output Voltage Temperature Drift T = 25°C to T , or 25°C to T 0.25 1.25 % J JMIN JMAX Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 7: This is the current required to pull the output voltage to within 1V may cause permanent damage to the device. Exposure to any Absolute of ground during shutdown. Maximum Rating condition for extended periods may affect device Note 8: Dropout voltage is measured by setting the input voltage equal to reliability and lifetime. the normal regulated output voltage and measuring the difference between Note 2: The LT1175 regulators are tested and specifi ed under pulse load V and V . For currents between 100mA and 500mA, with both I IN OUT LIM conditions such that T T . The LT1175C is 100% production tested pins tied to V , maximum dropout can be calculated from J A IN at T = 25°C. Performance at 0°C and 125°C is assured by design, V = 0.15 + 1.1Ω (I ). A DO OUT characterization and correlation with statistical process controls. The Note 9: Thermal regulation is a change in the output voltage caused by LT1175I is guaranteed over the full –40°C to 125°C operating junction die temperature gradients, so it is proportional to chip power dissipation. temperature range. The LT1175MP is 100% tested and guaranteed over Temperature gradients reach fi nal value in less than 100ms. Output voltage the –55°C to 125°C operating junction temperature range. changes after 100ms are due to absolute die temperature changes and Note 3: SHDN pin maximum positive voltage is 30V with respect to reference voltage temperature coeffi cient. –VIN and 13.5V with respect to GND. Maximum negative voltage is –20V Note 10: The lower limit of 0.8V is guaranteed to keep the regulator in with respect to GND and –5V with respect to –VIN. shutdown. The upper limit of 2.5V is guaranteed to keep the regulator Note 4: P = 1.5W for 8-pin packages, and 6W for 5-pin packages. active. Either polarity may be used, referenced to GND pin. MAX This power level holds only for input-to-output voltages up to 12V, beyond Note 11: Load and line regulation are measured on a pulse basis with which internal power limiting may reduce power. See Guaranteed Current pulse width of 20ms or less to keep chip temperature constant. DC Limit curve in Typical Performance Characteristics section. Note that all regulation will be affected by thermal regulation (Note 8) and chip conditions must be met. temperature changes. Load regulation specifi cation also holds for currents Note 5: GND pin current increases because of power transistor base up to the specifi ed current limit when I or I are left open. LIM2 LIM4 drive. At low input-to-output voltages (<1V) where the power transistor Note 12: Current limit is reduced for input-to-output voltage above 12V. is in saturation, GND pin current will be slightly higher. See Typical See the graph in Typical Performance Characteristics for guaranteed limits Performance Characteristics. above 12V. Note 6: With ILOAD = 0, at TJ > 125°C, power transistor leakage could Note 13: Operating at very large input-to-output differential voltages increase higher than the 10μA to 25μA drawn by the output divider or fi xed (>15V) with load currents less than 5mA requires an output capacitor with voltage SENSE pin, causing the output to rise above the regulated value. an ESR greater than 1Ω to prevent low level output oscillations. To prevent this condition, an internal active pull-up will automatically turn on, but supply current will increase. 1175ff 5

LT1175 TYPICAL PERFORMANCE CHARACTERISTICS Typical Current Limit Characteristics Guaranteed Current Limit Output Voltage Temperature Drift 1.0 0.6 5.05 CURRENT LIMIT CHANGES ONLY SLIGHTLY CURVES REPRE- WITH TEMPERATURE SO CURVES ARE ILIM2, ILIM4 TIED TO VIN SENT MINIMUM OUTPUT REPRESENTATIVE OF ALL TEMPERATURES 0.5 GUARANTEED FIXED 5V PART 0.8 5.00 LIMITS AT ALL ILIM2, ILIM4 TIED TO VIN 0.4 ILIM4TIED TO VIN TEMPERATURES RENT (A) 0.6 ILIM4TIED TO VIN RENT (A) 0.3 ILIM2TIED TO VIN TAGE (V)4.95 R R L U 0.4 U O3.84 C ILIM2TIED TO VIN C 0.2 V FEEDBACK VOLTAGE ILIM2, ILIM4 OPEN ADJUSTABLE PART 0.2 3.80 ILIM2, ILIM4 OPEN 0.1 0 0 3.76 0 5 10 15 20 25 0 5 10 15 20 25 –50 –25 0 25 50 75 100 125 INPUT-TO-OUTPUT DIFFERENTIAL VOLTAGE (V) INPUT-TO-OUTPUT DIFFERENTIAL VOLTAGE (V) JUNCTION TEMPERATURE (°C) 1175 G01 1175 G02 1175 G03 SENSE Bias Current Minimum Input-to-Output Voltage Minimum Input-to-Output Voltage (Adjustable Part) 1.0 1.0 100 TJ = 25°C VIN REDUCED UNTIL OUTPUT VIN REDUCED VOLTAGE DROPS 1%. E (V) 0.8 UVONLTTILA GOEUTPUT E (V) 0.8 ILIM2, ILIM4 TIED TO VIN 80 AG DROPS 1% ILIM2TIED AG PUT VOLT 0.6 ILIM2, OILPIEMN4 TO VIN PUT VOLT 0.6 TJ = 125°C ENT (nA) 60 T T R OU 0.4 OU 0.4 UR 40 O- ILIM4TIED O- C UT-T TO VIN UT-T TJ = 25°C NP 0.2 ILIM2, ILIM4 NP 0.2 TJ = –55°C 20 I TIED TO VIN I 0 0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 –50 –25 0 25 50 75 100 125 OUTPUT CURRENT (A) OUTPUT CURRENT (A) TEMPERATURE (°C) 1175 G04 1175 G05 1175 G06 1175ff 6

LT1175 TYPICAL PERFORMANCE CHARACTERISTICS Shutdown Input Current Shutdown Thresholds SHDN Pin Characteristics 25 2.5 15 VIN = 25V CHARACTERISTICS DO NOT POSITIVE THRESHOLD CHANGE SIGNIFICANTLY WITH 20 2.0 10 TEMPERATURE, SO A SINGLE CURRENT (μA) 15 TJ = 125°C TJ = 25°C ESHOLD (V) 1.5 NEGATIVE THRESHOLD URRENT (μA) 5 CCSUUHRRDVRNEE P NIISNT SFLHOOWWSN .I NPTOOSITIVE UT 10 HR 1.0 N C 0 NP TJ = –55°C T PI IF SHDN PIN IS NEGATIVE WITH I RESPECT TO INPUT VOLTAGE AND 5 0.5 –5 INPUT VOLTAGE IS LESS THAN 15V, DEVICE IS OFF NEGATIVE BREAKOVER POINT WILL BELOW THRESHOLD BE ABOUT 8V BELOW –VIN 0 0 –10 0 5 10 15 20 25 –50 –25 0 25 50 75 100 125 –25 –20–15–10 –5 0 5 10 15 20 25 INPUT VOLTAGE (V) TEMPERATURE (°C) SHUTDOWN TO GROUND VOLTAGE (V) 1175 G07 1175 G08 1175 G09 GND Pin Current Ripple Rejection 20 100 VOUT = 12V (ADJUSTABLE) A) 16 80 WITH 0.1μF ACROSS m DIVIDER RESISTOR UND PIN CURRENT ( 128 TINR TADJNR =SPO IO–SP5WTO5OEU°RRCT VINT –J V=O 2U5T° C= 2V REJECTION (dB) 6400 (ADVJUOUSTT A=B 1L2EV) V(FOIXUTE D=) 5V RO TJ = 25°C G 4 20 IOUT = 100mA 0 VTJIN = – 2 V5O°CUT ≥ 3V 0 VCIONU –T =V O1UμTF =T A2NVT 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 10 100 1k 10k 100k 1M OUTPUT CURRENT (A) FREQUENCY (Hz) 1175 G10 RIPPLE REJECTION IS RELATIVELY INDEPENDENT OF INPUT VOLTAGE AND LOAD FOR CURRENTS BETWEEN 25mA AND 500mA. LARGER OUTPUT CAPACITORS DO NOT IMPROVE REJECTION FOR FREQUENCIES BELOW 50kHz. AT VERY LIGHT LOADS, REJECTION WILL IMPROVE WITH LARGER OUTPUT CAPACITORS 1175 G11 1175ff 7

LT1175 PIN FUNCTIONS (N8/Q/ST/S8/T) V (Pins 1, 8/Pin 3, Tab/Pin 2, Tab/Pins 1, 8/Pin 3, Tab): 3.8V at the SENSE pin. Input bias current is typically 75nA IN Power is supplied to the device through this pin. A bypass fl owing out of the pin. Maximum forced voltage on the capacitor is required on this pin if the device is more than SENSE pin is 2V and –10V with respect to GND pin. six inches away from the main fi lter capacitor. In general, The fi xed 5V version utilizes the SENSE pin to give true the impedance of a battery rises with frequency, so it is Kelvin connections to the load or to drive an external pass advisable to include a bypass capacitor in battery-powered transistor for higher output currents. Bias current out circuits. A 1μF or larger tantalum capacitor is suggested of the 5V SENSE pin is approximately 12μA. Separating for all applications, but if low ESR capacitors such as the SENSE and OUTPUT pins also allows for a new loop ceramic or fi lm are used for the output and input capaci- compensation technique described in the Applications tors, the input capacitor should be three times the value Information section. of the output capacitor. GND (Pin 5/Pin 4/Pin 3/Pin 5/Pin 4): The GND pin has a I , I (Pins 2, 7/NA/NA/Pins 2, 7/NA): The two LIM2 LIM4 quiescent current of 45μA at zero load current, increas- current limit pins are emitter sections of the power transis- ing by approximately 10μA per mA of output current. At tor. When left open, they fl oat several hundred millivolts 500mA output current, GND pin current is about 5mA. above the negative input voltage. When shorted to the Current fl ows into the GND pin. input voltage, they increase current limit by a minimum of 200mA for I and 400mA for I . These pins must SHDN (Pin 6/Pin 5/NA/Pin 6/Pin 5): The SHDN pin is LIM2 LIM4 be connected only to the input voltage, either directly or specially confi gured to allow it to be driven from either through a resistor. positive voltage logic or with negative only logic. Forc- ing the SHDN pin 2V either above or below the GND OUTPUT (Pin 3/Pin 1/Pin 1/Pin 3/Pin 1): The OUTPUT pin pin will turn the regulator on. This makes it simple to is the collector of the NPN power transistor. It can be forced connect directly to positive logic signals for active low to the input voltage, to ground or up to 2V positive with shutdown. If no positive voltages are available, the respect to ground without damage or latchup (see Output SHDN pin can be driven below the GND pin to turn the Voltage Reversal in Applications Information section). The regulator on. When left open, the SHDN pin will default LT1175 has foldback current limit, so maximum current at low to a regulator “on” condition. For all voltages below the OUTPUT pin is a function of input-to-output voltage. absolute maximum ratings, the SHDN pin draws only a See Typical Performance Characteristics. few microamperes of current (see Typical Performance SENSE (Pin 4/Pin 2/NA/Pin 4/Pin 2): The SENSE pin is Characteristics). Maximum voltage on the SHDN pin is 15V, used in the adjustable version to allow custom selection –20V with respect to the GND pin and 35V, –5V with of output voltage, with an external divider set to generate respect to the negative input pin. 1175ff 8

LT1175 APPLICATIONS INFORMATION The LT1175-5 is a fi xed 5V design with the SENSE pin Note to Reader: To avoid confusion when working with acting as a Kelvin connection to the output. Normally the negative voltages (is –6V more or less than –5V?), I have SENSE pin and the OUTPUT pin are connected directly decided to treat the LT1175 as if it were a positive regulator together, either close to the regulator or at the remote and express all voltages as positive values, both in text and load point. in formulas. If you do the same and simply add a negative sign to the eventual answer, confusion should be avoided. SHUTDOWN > 2V OR < –2V TO Please don’t give me a hard time about “preciseness” or LOGIC TURN REGULATOR ON “correctness.” I have to fi eld phone calls from around + the world and this is my way of dealing with a multitude + R1 of conventions. Thanks for your patience. CIN 383k SHDN GND 1% Setting Output Voltage VIN SENSE R2 C≥ O0U.1TμF LT1175 ILIM2 825k 1% The LT1175 adjustable version has a feedback sense ILIM4 OUTPUT V–1O2UVT voltage of 3.8V with a bias current of approximately 75nA 1175 F01 fl owing out of the SENSE pin. To avoid output voltage Figure 1. Typical LT1175 Adjustable Connection errors caused by this current, the output divider string (see Figure 1) should draw about 25μA. Table 1 shows Setting Current Limit suggested resistor values for a range of output voltages. The LT1175 uses two I pins to set current limit (typical) LIM The second part of the table shows resistor values which at 200mA, 400mA, 600mA or 800mA. The corresponding draw only 10μA of current. Output voltage error caused minimum guaranteed currents are 130mA, 260mA, 390mA by bias current with the lower valued resistors is about and 520mA. This allows the user to select a current limit 0.4% maximum and with the higher values, about 1% tailored to his specifi c application and prevents the situa- maximum. A formula is also shown for calculating the tion where short-circuit current is many times higher than resistors for any output voltage. full-load current. Problems with input supply overload or excessive power dissipation in a faulted load are prevented. Table 1. Suggested Divider Resistors Power limiting in the form of foldback current limit is built OUTPUT R1 R2 R1 R2 VOLTAGE I = 25μA NEAREST 1% I = 10μA NEAREST 1% in and reduces current limit as a function of input-to-output DIV DIV 5V 150k 47.5k 383k 121k voltage differential for differentials exceeding 14V. See the 6V 150k 86.6k 383k 221k graph in Typical Performance Characteristics. The LT1175 8V 150k 165k 383k 422k is guaranteed to be blowout-proof regardless of current 10V 150k 243k 383k 619k limit setting. The power limiting combined with thermal shutdown protects the device from destructive junction 12V 150k 324k 383k 825k temperatures under all load conditions. 15V 150k 442k 383k 1.13M 3.8V Shutdown R1= I In shutdown, the LT1175 draws only about 10μA. Special DIV( ) R1 V −3.8V ( ) circuitry is used to minimize increases in shutdown cur- OUT R2= Simple formula rent at high temperatures, but a slight increase is seen ( 3.8V ) above 125°C. One option not taken was to actively pull R1 VOUT −3.8V ⎛Taking SENSE pin bias⎞ down on the output during shutdown. This means that the R2= ( ) ⎜ ⎟ output will fall slowly after shutdown is initiated, at a rate 3.8V+R1I ⎝current into account ⎠ FB determined by load current plus the 12μA internal load, I =Desired divider current and the size of the output capacitor. Active pull-down is DIV 1175ff 9

LT1175 APPLICATIONS INFORMATION normally a good thing when the regulator is used by itself, yet allows the power transistor to approach its theoretical but it prevents the user from shutting down the regulator saturation limit. when a second power source is connected to the LT1175 output. If active output pull-down is needed in shutdown, Output Capacitor it can be added externally with a depletion mode PFET as Several new regulator design techniques are used to make shown in Figure 2. Note that the maximum pinch-off volt- the LT1175 extremely tolerant of output capacitor selection. age of the PFET must be less than the positive logic high Like most low dropout designs which use a collector or level to ensure that the device is completely off when the drain of the power transistor to drive the output node, the regulator is active. The Motorola J177 device has 300Ω LT1175 uses the output capacitor as part of the overall on resistance for zero gate source voltage. loop compensation. Older regulators generally required the output capacitor to have a minimum value of 1μF to 3V TO 5V 100μF, a maximum ESR (Effective Series Resistance) of 0.1Ω to 1Ω and a minimum ESR in the range of 0.03Ω to 0.3Ω. These restrictions usually could be met only with good quality solid tantalum capacitors. Aluminum capaci- s + Q1* tors have problems with high ESR unless much higher d values of capacitance are used (physically large). The ESR SHDN GND COUT –VIN VIN SENSE ≥ 0.1μF of ceramic or fi lm capacitors was too low, which made LT1175-5 the capacitance/ESR zero frequency too high to maintain ILIM2 phase margin in the regulator. Even with optimum capaci- ILIM4 OUTPUT tors, loop phase margin was very low in previous designs * MOTOROLA J177 when output current was low. These problems led to a new PINCH-OFF VOLTAGE MUST BE LESS THAN POSITIVE LOGIC HIGH VOLTAGE 1175 F02 design technique for the LT1175 error amplifi er and internal frequency compensation as shown in Figure 3. Figure 2. Active Output Pull-Down During Shutdown A conventional regulator loop consists of error amplifi er Minimum Dropout Voltage A1, driver transistor Q2 and power transistor Q1. Added Dropout voltage is the minimum voltage required between to this basic loop are secondary loops generated by Q3 input and output to maintain proper output regulation. and C . A DC negative feedback current fed into the error F For older 3-terminal regulator designs, dropout voltage amplifi er through Q3 and R causes overall loop current N was typically 1.5V to 3V. The LT1175 uses a saturating gain to be very low at light load currents. This is not a power transistor design which gives much lower dropout problem because very little gain is needed at light loads. voltage, typically 100mV at light loads and 450mV at full In addition to low gain, the parasitic pole frequency at Q2 load. Special precautions were taken to ensure that this base is extended by the DC feedback. The combination of technique does not cause quiescent supply current to be these two effects dramatically improves loop phase margin high under light load conditions. When the regulator input at light loads and makes the loop tolerant of large ESR in voltage is too low to maintain a regulated output, the pass the output capacitor. With heavy loads, loop phase and gain transistor is driven hard by the error amplifi er as it tries are not nearly as troublesome and large negative feedback to maintain regulation. The current drawn by the driver could degrade regulation. The logarithmic behavior of the transistor could be tens of milliamperes even with little or base emitter voltage of Q1 reduces Q3 negative feedback no load on the output. This indeed was the case for older at heavy loads to prevent poor regulation. IC designs that did not actively limit driver current when In a conventional design, even with the nonlinear feedback, the power transistor saturated. The LT1175 uses a new poor loop phase margin would occur at medium to heavy antisaturation technique that prevents high driver current, loads if the ESR of the output capacitor fell below 0.3Ω. 1175ff 10

LT1175 APPLICATIONS INFORMATION GND LT1175 + 3.8V R1 – A1 COUT + LOAD ESR R2 SENSE Q2 AC FEEDFORWARD PATH CF OUTPUT 20pF OUTPUT RC 0.5Ω NEGATIVE DC PARASITIC FEEDBACK COLLECTOR AT LIGHT Q3 Q1 RESISTANCE LOADS POWER RN TRANSISTOR RLIM CURRENT LIMIT SENSE RESISTOR 1175 F03 VIN Figure 3 This condition can occur with ceramic or fi lm capacitors The end result of all this attention to loop stability is that which often have an ESR under 0.1Ω. With previous de- the output capacitor used with the LT1175 can range in signs, the user was forced to add a real resistor in series value from 0.1μF to hundreds of microfarads, with an ESR with the capacitor to guarantee loop stability. The LT1175 from 0Ω to 10Ω. This range allows the use of ceramic, uses a unique AC feedforward technique to eliminate solid tantalum, aluminum and fi lm capacitors over a wide this problem. C is a conventional feedforward capacitor range of values. F often used in regulators to cancel the pole formed by the The optimum output capacitor type for the LT1175 is output capacitor. It would normally be connected from the still solid tantalum, but there is considerable leeway in regulated output node to the feedback node at the R1/R2 selecting the exact unit. If large load current transients junction or to an internal node on the amplifi er as shown. are expected, larger capacitors with lower ESR may be In this case, however, the capacitor is connected to the needed to control worst-case output variation during internal structure of the power transistor. R is the unavoid- C transients. If transients are not an issue, the capacitor able parasitic collector resistance of the power transistor. can be chosen for small physical size, low price, etc. Access to the node at the bottom of R is available only C Concerns about surge currents in tantalum capacitors are in monolithic structures where Kelvin connections can not an issue for the output capacitor because the LT1175 be made to the NPN buried collector layer. The loop now limits inrush current to well below the level which can responds as if R were in series with the output capacitor C cause capacitor damage. Surges caused by shorting the and good loop stability is achieved even with extremely regulator output are also not a problem because tantalum low ESR in the output capacitor. 1175ff 11

LT1175 APPLICATIONS INFORMATION capacitors do not fail during a “shorting out” surge, only voltage when the regulator output is being pulled high. If during a “charge up” surge. a 4.8V output is pulled to 5V, for instance, the load on the primary regulator would be (5V – 4.8V)/2kΩ = 100μA. The output capacitor should be located within several This also means that if the internal pass transistor leaks inches of the regulator. If remote sensing is used, the output 50μA, the output voltage will be (50μA)(2kΩ) = 100mV capacitor can be located at the remote sense node, but the high. This condition will not occur under normal operating GND pin of the regulator should also be connected to the conditions, but could occur immediately after an output remote site. The basic rule is to keep SENSE and GND pins short circuit had overheated the chip. close to the output capacitor, regardless of where it is. Operating at very large input-to-output differential volt- Thermal Considerations ages (>15V) with load currents less than 5mA requires an The LT1175 is available in a special 8-pin surface mount output capacitor with an ESR greater than 1Ω to prevent package which has Pins 1 and 8 connected to the die attach low level output oscillations. paddle. This reduces thermal resistance when Pins 1 and 8 are connected to expanded copper lands on the PC board. Input Capacitor Table 2 shows thermal resistance for various combinations The LT1175 requires a separate input bypass capacitor of copper lands and backside or internal planes. Table 2 only if the regulator is located more than six inches from also shows thermal resistance for the 5-pin DD surface the raw supply output capacitor. A 1μF or larger tantalum mount package and the 8-pin DIP and package. capacitor is suggested for all applications, but if low ESR Table 2. Package Thermal Resistance (°C/W) capacitors such as ceramic or fi lm are used for the out- put and input capacitors, the input capacitor should be LAND AREA DIP ST SO Q at least three times the value of the output capacitor. If a Minimum 140 90 100 60 solid tantalum or aluminum electrolytic output capacitor Minimum with 110 70 80 50 Backplane is used, the input capacitor is very noncritical. 1cm2 Top Plane with 100 64 75 35 Backplane High Temperature Operation 10cm2 Top Plane 80 50 60 27 The LT1175 is a micropower design with only 45μA qui- with Backplane escent current. This could make it perform poorly at high To calculate die temperature, maximum power dissipation temperatures (>125°C), where power transistor leakage or maximum input voltage, use the following formulas might exceed the output node loading current (5μA to with correct thermal resistance numbers from Table 2. 15μA). To avoid a condition where the output voltage For through-hole TO-220 applications use θ = 50°C/W drifts uncontrolled high during a high temperature no-load JA without a heat sink and θ = 5°C/W + heat sink thermal condition, the LT1175 has an active load which turns on JA resistance when using a heat sink. when the output is pulled above the nominal regulated ( )( ) voltage. This load absorbs power transistor leakage and Die Temp=T +θ V −V I A JA IN OUT LOAD maintains good regulation. There is one downside to this T −T feature, however. If the output is pulled high deliberately, as Maximum PowerDissipation= MAX A θ it might be when the LT1175 is used as a backup to a slightly JA higher output from a primary regulator, the LT1175 will act Maximum Input Voltage T −T as an unwanted load on the primary regulator. Because of for Thermal Considerations =θMA(XI AA)+VOUT JA LOAD this, the active pull-down is deliberately “weak.” It can be modeled as a 2k resistor in series with an internal clamp 1175ff 12

LT1175 APPLICATIONS INFORMATION T = Maximum ambient temperature between the input and output of the regulator. Reverse A voltages between input and output above 1V will damage T = Maximum LT1175 die temperature (125°C for MAX the regulator if large currents are allowed to fl ow. Simply commercial and industrial grades) disconnecting the input source with the output held up θJA = LT1175 thermal resistance, junction to ambient will not cause damage even though the input-to-output voltage will become slightly reversed. V = Maximum continuous input voltage at maximum IN load current High Frequency Ripple Rejection I = Maximum load current LOAD The LT1175 will sometimes be powered from switching Example: LT1175S8 with ILOAD = 200mA, VOUT = 5V, regulators that generate the unregulated or quasi-regulated VIN = 7V, TA = 60°C. Maximum die temperature for the input voltage. This voltage will contain high frequency ripple LT1175S8 is 125°C. Thermal resistance from Table 2 is that must be rejected by the linear regulator. Special care found to be 80°C/W. was taken with the LT1175 to maximize high frequency ripple rejection, but as with any micropower design, Die Temperature = 60 + 80 (0.2A)(8 – 5) = 108°C rejection is strongly affected by ripple frequency. The Maximum Power Dissipation = 125–60 =0.81W graph in the Typical Performance Characteristics section 80 shows 60dB rejection at 1kHz, but only 15dB rejection at Maximum Continuous 125–60 100kHz for the 5V part. Photographs in Figures 4a and 4b I n p u t V o l t a g e = ( ) +5=9V show actual output ripple waveforms with square wave 80 0.2 (for Thermal Considerations) and triwave input ripple. Output Voltage Reversal The LT1175 is designed to tolerate an output voltage COUT = 4.7μF TANT reversal of up to 2V. Reversal might occur, for instance, OUTPUT 20mV/DIV COUT = 1μF TANT if the output was shorted to a positive 5V supply. This would almost surely destroy IC devices connected to the negative output. Reversal could also occur during start- INPUT up if the positive supply came up fi rst and loads were RIPPLE f = 50kHz 100mV/DIV connected between the positive and negative supplies. For these reasons, it is always good design practice to 5μs/DIV 1175 F04a add a reverse biased diode from each regulator output to ground to limit output voltage reversal. The diode should Figure 4a. be rated to handle full negative load current for start-up situations, or the short-circuit current of the positive supply if supply-to-supply shorts must be tolerated. OUTPUT COUT = 4.7μF TANT Input Voltage Lower Than Output 100mV/DIV COUT = 1μF TANT Linear Technology’s positive low dropout regulators LT1121 and LT1129, will not draw large currents if the INPUT input voltage is less than the output. These devices use a RIPPLE f = 100kHz 100mV/DIV lateral PNP power transistor structure that has 40V emitter base breakdown voltage. The LT1175, however, uses an 2μs/DIV 1175 F04b NPN power transistor structure that has a parasitic diode Figure 4b. 1175ff 13

LT1175 APPLICATIONS INFORMATION To estimate regulator output ripple under different loads, larger resistors and smaller capacitors can be used conditions, the following general comments should be to save space. At heavier loads an inductor may have to helpful: be used in place of the resistor. The value of the inductor can be calculated from: 1. Output ripple at high frequency is only weakly affected by load current or output capacitor size for medium ESR L = ( ) to heavy loads. At very light loads (<10mA), higher FIL 2π(f)10rr/20 frequency ripple may be reduced by using larger output capacitors. ESR = Effective series resistance of fi lter capacitor. This 2. A feedforward capacitor across the resistor divider used assumes that the capacitive reactance is small com- with the adjustable part is effective in reducing ripple pared to ESR, a reasonable assumption for solid only for output voltages greater than 5V and only for tantalum capacitors above 2.2μF and 50kHz. frequencies less than 100kHz. f = Ripple frequency 3. Input-to-output voltage differential has little effect on rr = Ripple rejection ratio of fi lter in dB ripple rejection until the regulator actually enters a dropout condition of 0.2V to 0.6V. Example: ESR = 1.2Ω, f = 100kHz, rr = –25dB. If ripple rejection needs to be improved, an input fi lter can 1.2 L = =34μH be added. This fi lter can be a simple RC fi lter using a 1Ω FIL ⎛ 5⎞⎛ −25/20⎞ 6.3 10 10 ⎝ ⎠⎝ ⎠ to 10Ω resistor. A 3.3Ω resistor for instance, combined with a 0.3Ω ESR solid tantalum capacitor, will give an ad- ditional 20dB ripple rejection. The size of the resistor will Solid tantalum capacitors are suggested for the fi lter to be dictated by maximum load current. If the maximum keep fi lter Q fairly low. This prevents unwanted ringing at voltage drop allowable across the resistor is “V ,” and the resonant frequency of the fi lter and oscillation problems R maximum load current is I , R = V /I . At light with the fi lter/regulator combination. LOAD R LOAD 1175ff 14

LT1175 PACKAGE DESCRIPTION N8 Package 8-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) .400* (10.160) MAX 8 7 6 5 .255 ± .015* (6.477 ± 0.381) 1 2 3 4 .300 – .325 .045 – .065 .130 ± .005 (7.620 – 8.255) (1.143 – 1.651) (3.302 ± 0.127) .065 (1.651) .008 – .015 TYP (0.203 – 0.381) .120 (3.048) .020 +.035 MIN (0.508) ( .325–.015 ) .100 .018 ± .003 MIN 8.255+0.889 (2.54) (0.457 ± 0.076) –0.381 BSC N8 1002 NOTE: INCHES 1. DIMENSIONS ARE MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) 1175ff 15

LT1175 PACKAGE DESCRIPTION Q Package 5-Lead Plastic DD Pak (Reference LTC DWG # 05-08-1461) .060 (1.524) .390 – .415 .256 .060 TYP (9.906 – 10.541) .165 – .180 (6.502) (1.524) (4.191 – 4.572) .045 – .055 15° TYP (1.143 – 1.397) +.008 .004 .060 .183 .330 – .370 .059 ( –.004 ) (1.524) (4.648) (1.499) +0.203 (8.382 – 9.398) 0.102 TYP –0.102 .095 – .115 (2.413 – 2.921) .075 (1.905) .067 .050 ± .012 .300 .143+.012 (1.702) .013 – .023 (1.270 ± 0.305) (7.620) ( –.020) BSC (0.330 – 0.584) .028 – .038 +0.305 BOTTOM VIEW OF DD PAK 3.632–0.508 (0.711 – 0.965) Q(DD5) 0502 HATCHED AREA IS SOLDER PLATED TYP COPPER HEAT SINK .420 .080 .420 .276 .350 .325 .205 .565 .565 .320 .090 .090 .067 .042 .067 .042 RECOMMENDED SOLDER PAD LAYOUT RECOMMENDED SOLDER PAD LAYOUT FOR THICKER SOLDER PASTE APPLICATIONS NOTE: 1. DIMENSIONS IN INCH/(MILLIMETER) 2. DRAWING NOT TO SCALE 1175ff 16

LT1175 PACKAGE DESCRIPTION S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .189 – .197 .045 ±.005 (4.801 – 5.004) .050 BSC NOTE 3 8 7 6 5 .245 MIN .160 ±.005 .150 – .157 .228 – .244 (3.810 – 3.988) (5.791 – 6.197) NOTE 3 .030 ±.005 TYP 1 2 3 4 RECOMMENDED SOLDER PAD LAYOUT .010 – .020 × 45° .053 – .069 (0.254 – 0.508) (1.346 – 1.752) .004 – .010 .008 – .010 (0.203 – 0.254) 0°– 8° TYP (0.101 – 0.254) .016 – .050 .014 – .019 .050 (0.406 – 1.270) (0.355 – 0.483) (1.270) NOTE: INCHES TYP BSC 1. DIMENSIONS IN (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) SO8 0303 ST Package 3-Lead Plastic SOT-223 (Reference LTC DWG # 05-08-1630) .248 – .264 .129 MAX (6.30 – 6.71) .114 – .124 (2.90 – 3.15) .059 MAX .264 – .287 .248 BSC (6.70 – 7.30) .130 – .146 (3.30 – 3.71) .039 MAX .059 MAX .090 BSC .181 MAX .0905 .033 – .041 RECOMMENDED SOLDER PAD LAYOUT (2.30) (0.84 – 1.04) BSC 10° – 16° .010 – .014 .071 10° (0.25 – 0.36) (1.80) MAX MAX 10° – 16° .024 – .033 .012 .0008 – .0040 (0.60 – 0.84) (0.31) (0.0203 – 0.1016) .181 MIN (4.60) ST3 (SOT-233) 0502 BSC 1175ff 17

LT1175 PACKAGE DESCRIPTION T Package 5-Lead Plastic TO-220 (Standard) (Reference LTC DWG # 05-08-1421) .147 – .155 .165 – .180 .390 – .415 (3.734 – 3.937) (4.191 – 4.572) .045 – .055 (9.906 – 10.541) DIA (1.143 – 1.397) .230 – .270 (5.842 – 6.858) .570 – .620 .620 .460 – .500 (14.478 – 15.748) (15.75) (11.684 – 12.700) .330 – .370 TYP .700 – .728 (8.382 – 9.398) (17.78 – 18.491) .095 – .115 SEATING PLANE (2.413 – 2.921) .152 – .202 .260 – .320 (3.861 – 5.131) .155 – .195* (3.937 – 4.953) (6.60 – 8.13) .013 – .023 (0.330 – 0.584) .067 BSC .028 – .038 .135 – .165 (1.70) (0.711 – 0.965) (3.429 – 4.191) * MEASURED AT THE SEATING PLANE T5 (TO-220) 0801 1175ff 18

LT1175 REVISION HISTORY (Revision history begins at Rev E) REV DATE DESCRIPTION PAGE NUMBER E 11/09 Revised Typical Application. 1 Revised Pin Confi guration drawings and layout. 2 Updated Order Information. 3 V added and pin numbers added to Pin Functions. 7 IN Title added to Table 1. 8 Revised Figures 1, 2, 3, 4a and 4b. 8, 9, 10, 12 Value correction in fi nal paragraph of the Output Capacitor section. 11 F 7/10 Added MP-grade. 2–4 Replaced Note 2, renumbered all other notes and revised shutdown thresholds in the Electrical Characteristics section. 4, 5 Updated Related Parts. 20 1175ff Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 19 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LT1175 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1121 150mA Positive Micropower Low Dropout Regulator with Shutdown SOT-223, 8-Lead SO, TO-92 Packages LT1129 700mA Positive Micropower Low Dropout Regulator with Shutdown DD-Pak, SOT-223, 8-Lead SO, TO-220, 20-Lead TSSOP Packages LT1185 3A Negative Low Dropout Regulator DD-Pak, TO-220 Packages LT1521 300mA Positive Micropower Low Dropout Regulator with Shutdown SOT-223, 8-Lead SO, 8-Lead MSOP Packages LT1529 3A Positive Micropower Low Dropout Regulator with Shutdown DD-Pak, TO-220 Packages LT1964 200mA Negative Low Dropout Linear Regulator 5-Lead TSOT-23, 8-Lead (3mm × 3mm) DFN Packages 1175ff 20 Linear Technology Corporation LT 0710 REV F • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 1995