DATASHEET ISL95311 FN8084 Digitally Controlled Potentiometer (XDCP™), Rev 2.00 Terminal Voltage 0V to 13.2V, 128 Taps I2C Interface August 13, 2015 The Intersil ISL95311 is a digitally controlled potentiometer Features (XDCP). The device consists of a resistor array, wiper • Non-volatile solid-state potentiometer switches, a control section, and nonvolatile memory. The wiper position is controlled by an I2C interface. • I2C serial interface The potentiometer is implemented by a resistor array • DCP terminal voltage, 0V to +13.2V composed of 127 resistive elements and a wiper switching • 128 wiper tap points - 0.8% resolution network. Between each element and at either end are tap - Wiper position stored in nonvolatile memory and points accessible to the wiper terminal. The wiper of the recalled on power-up potentiometer has an associated volatile Wiper Counter Register (WR) and a non-volatile Initial Value Register (IVR) • 127 resistive elements that can be directly written to and read by the user. The - Temperature compensated contents of the WR controls the position of the wiper on the - Low wiper resistance 70 typical @ 3.3V resistor array through the switches. At power-up, the device • Low power CMOS recalls the contents of the IVR to the corresponding WR. - Standby current, 2µA @ VCC = +3.6V The device can be used as a three-terminal potentiometer or • High reliability as a two-terminal variable resistor in a wide variety of - Endurance, 200,000 data changes per bit applications, including: - Register data retention 50 years @ T  +75°C • LCD contrast control • RTOTAL values = 10k50k • Parameter and bias adjustments • 10 Ld MSOP package • Industrial and automotive control • Pb-free (RoHS compliant) • Mechanical pot replacement Pinout ISL95311 (10-LD MSOP) TOP VIEW SDA 1 10 SCL GND 2 9 V+ VCC 3 8 RL A1 4 7 RW A0 5 6 RH Ordering Information PART NUMBER RESISTANCE OPTION TEMP RANGE PACKAGE (Note) PART MARKING () (°C) (Pb-Free) PKG. DWG. # ISL95311WIU10Z AJE 10k -40 to +85 10-Ld MSOP M10.118 Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN8084 Rev 2.00 Page 1 of 12 August 13, 2015

ISL95311 Block Diagram 7-BIT SDA WIPER REGISTER 127 RH VCC V+ SCL (VOLATILE) 126 SDA RH 125 SCL 7-BIT 124 CONTROL NONVOLATILE AND RW MEMORY ONE A1 MEMORY OF TRANSFER RESISTOR A0 128 GATES ARRAY RL DECODER 2 STORE AND GND RECALL 1 CONTROL SIMPLE BLOCK DIAGRAM CIRCUITRY 0 A1 SLAVE RL ADDRESS RW A0 DECODE DETAILED BLOCK DIAGRAM Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1 SDA Data I/O for I2C serial interface; it has an open drain output and may be wire-or’d with other open drain active low outputs 2 GND Ground 3 VCC Positive logic supply voltage 4 A1 Address select pin used to set the slave address for the I2C serial interface 5 A0 Address select pin used to set the slave address for the I2C serial interface 6 RH A fixed terminal for one end of the potentiometer resistor 7 RW The wiper terminal, which is equivalent to the movable terminal of a potentiometer 8 RL A fixed terminal for one end of the potentiometer resistor 9 V+ Positive bias voltage for the potentiometer wiper control 10 SCL Clock input for the I2C serial interface FN8084 Rev 2.00 Page 2 of 12 August 13, 2015

ISL95311 Absolute Maximum Ratings Recommended Operating Conditions Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Temperature Range (Industrial). . . . . . . . . . . . . . . . .-40°C to +85°C Voltage on SDA, SCL, A0, A1 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V to 5.5V with respect to GND. . . . . . . . . . . . . . . . . . . .-0.3V to VCC + 0.3V V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.0V to 13.2V Voltage on V+ (referenced to GND). . . . . . . . . . . . . . . . . . . . +13.2V Wiper current of DCP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA V = |V(RH) - V(RL)| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+ Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below RH, RL, RW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+ http://www.intersil.com/pbfree/Pb-FreeReflow.asp IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V Power rating of DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mW CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Analog Specifications Over recommended operating conditions, unless otherwise stated. MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 15) (Note1) (Note 15) UNIT RTOTAL RH to RL Resistance W option 10 k U option 50 k RH to RL Resistance Tolerance -20 +20 % VRH RH Terminal Voltage VRL = 0V 0 V+ V RW Wiper Resistance V+ = 12.0V, wiper current = V+/RTOTAL 70 200  CH/CL/CW Potentiometer Capacitance 10/10/25 pF ILkgDCP Leakage on DCP Pins Voltage at pin from GND to V+ 0.1 1 µA VOLTAGE DIVIDER MODE (0V @ RL; V+ @ RH; measured at RW, unloaded) INL Integral Non-Linearity W and U option -1 1 LSB (Note 6) (Note 2) DNL Differential Non-Linearity W and U option -0.5 0.5 LSB (Note 5) (Note 2) ZSerror Zero-Scale Error W option 0 1 7 LSB (Note3) (Note 2) U option 0 0.5 2 FSerror Full-Scale Error W option -7 -1 0 LSB (Note4) (Note 2) U option -2 -0.5 0 TCV Ratiometric Temperature Coefficient DCP register set to 40 hex ±4 ppm/°C (Note 7) RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected) RINL Integral Non-Linearity DCP register set between 20 hex and 7F hex; -1.0 1.0 MI (Note11) monotonic over all tap positions (Note8) RDNL Differential Non-Linearity W and U option -0.5 0.5 MI (Note10) (Note8) Roffset Offset DCP Register set to 00 hex, W option 0 1 7 MI (Note9) (Note8) DCP Register set to 00 hex, U option 0 0.5 2 TCR Resistance Temperature Coefficient DCP register set between 20 hex and 7F hex ±45 ppm/°C (Note12) FN8084 Rev 2.00 Page 3 of 12 August 13, 2015

ISL95311 Operating Specifications Over the recommended operating conditions unless otherwise specified. MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 15) (Note1) (Note 15) UNIT ICC1 VCC Supply Current, Volatile fSCL = 400kHz; SDA = Open; (for I2C, active, 1 mA Write/read read, and volatile write states only) ICC2 VCC Supply Current, Nonvolatile fSCL = 400kHz; SDA = Open; (for I2C, active, 3 mA Write nonvolatile write states only) ISB VCC Current, Standby VCC = +5.5V, I2C interface in standby state 5 µA VCC = +3.6V, I2C interface in standby state 2 µA IV+ V+ Bias Current V+ = 13.2V, VCC = +5.5V 1 µA ILkgDig Leakage Current, at Pins SDA, SCL, Voltage at pin from GND to VCC -10 10 µA A0, and A1 Pins tDCP DCP Wiper Response Time SCL falling edge of last bit of DCP data byte to 1 µs wiper change Vpor Power-On Recall Voltage VCC range at which memory recall occurs 1.5 1.8 2.6 V VCCRamp VCC Ramp Rate 0.2 V/ms tD Power-Up Delay VCC above Vpor, to DCP initial value register 3 ms recall completed, and I2C Interface in standby state EEPROM SPECS EEPROM Endurance 200,000 Cycles EEPROM Retention Temperature  +75°C 50 Years SERIAL INTERFACE SPECS VIL A0, A1, SDA, and SCL Input Buffer -0.3 0.3* V LOW Voltage VCC VIH A0, A1, SDA, and SCL Input Buffer 0.7* VCC+ V HIGH Voltage VCC 0.3 Hysteresis SDA and SCL Input Buffer Hysteresis 0.05* V VCC VOL SDA Output Buffer LOW Voltage, 0 0.4 V Sinking 4mA Cpin A0, A1, SDA, and SCL Pin 10 pF Capacitance fSCL SCL Frequency 400 kHz tIN Pulse Width Suppression Time at Any pulse narrower than the max spec is 50 ns SDA and SCL Inputs suppressed tAA SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of VCC, until 900 ns Valid SDA exits the 30% to 70% of VCC window tBUF Time the Bus Must be Free Before the SDA crossing 70% of VCC during a STOP 1300 ns Start of a New Transmission condition, to SDA crossing 70% of VCC during the following START condition tLOW Clock LOW Time Measured at the 30% of VCC crossing 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VCC crossing 600 ns tSU:STA START Condition Set-up Time SCL rising edge to SDA falling edge; both 600 ns crossing 70% of VCC tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VCC to 600 ns SCL falling edge crossing 70% of VCC tSU:DAT Input Data Set-up Time From SDA exiting the 30% to 70% of VCC 100 ns window, to SCL rising edge crossing 30% of VCC FN8084 Rev 2.00 Page 4 of 12 August 13, 2015

ISL95311 Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued) MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 15) (Note1) (Note 15) UNIT tHD:DAT Input Data Hold Time From SCL rising edge crossing 30% of VCC to 0 ns SDA entering the 30% to 70% of VCC window tSU:STO STOP Condition Set-up time From SCL rising edge crossing 70% of VCC, to 600 ns SDA rising edge crossing 30% of VCC tHD:STO STOP Condition Hold Time From SDA rising edge to SCL falling edge. Both 600 ns crossing 70% of VCC tDH Output Data Hold Time From SCL falling edge crossing 30% of VCC, 0 ns until SDA enters the 30% to 70% of VCC window tR SDA and SCL Rise Time From 30% to 70% of VCC 20 + 250 ns (Note14) 0.1 * Cb tF SDA and SCL Fall Time From 70% to 30% of VCC 20 + 250 ns (Note14) 0.1 * Cb Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF (Note14) Rpu SDA and SCL Bus Pull-Up Resistor Maximum is determined by tR and tF, 1 k (Note14) Off-Chip For Cb = 400pF, max is about 2k~2.5k. For Cb = 40pF, max is about 15k~20k. tWP Non-Volatile Write Cycle Time 12 20 ms (Notes13) tSU:A A0, A1 Set-up Time Before START condition 600 ns tHD:A A0, A1 Hold Time After STOP condition 600 ns NOTES: 1. Typical values are for TA = +25°C and 3.3V supply voltage. 2. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 3. ZS error = V(RW)0/LSB. 4. FS error = [V(RW)127 – V+]/LSB. 5. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 6. INL = V(RW)i – (i • LSB – V(RW)0) for i = 1 to 127. 7. TC = -------M-----a----x------V-------R-----W--------i-----–-----M-----i--n------V-------R-----W--------i-------------1---0----6------ V MaxVRW+MinVRW2 125°C i i for i = 16 to 120 decimal, T = -40°C to 85°C. Max( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 8. MI = |R127 – R0|/127. R127 and R0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively. 9. Roffset = R0/MI, when measuring between RW and RL. Roffset = R127/MI, when measuring between RW and RH. 10. RDNL = (Ri – Ri-1)/MI, for i = 16 to 127. 11. RINL = [Ri – (MI • i) – R0]/MI, for i = 16 to 127. 6 MaxRi–MinRi 10 12. TC = --------------------------------------------------------------------------------- R MaxRi+MinRi2 125°C for i = 16 to 127, T = -40°C to +85°C. Max( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over the temperature range. 13. tWP is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a valid STOP condition at the end of a Write sequence of a I2C serial interface Write operation, to the end of the self-timed internal non-volatile write cycle. 14. Recommended operating limits and are not production tested. 15. Parts are 100% tested at +85°C. Over temperature limits established by characterization and are not production tested. FN8084 Rev 2.00 Page 5 of 12 August 13, 2015

ISL95311 SDA vs SCL Timing tF tHIGH tLOW tR SCL tSU:DAT tSU:STA tHD:DAT tSU:STO tHD:STA SDA (INPUT TIMING) tAA tDH tBUF SDA (OUTPUT TIMING) A0, A1 Pin Timing START STOP SCL CLK 1 SDA IN tSU:A tHD:A A0, A1 Pin Descriptions DEVICE ADDRESS (A1–A0) The Address inputs are used to set the least significant 2 bits Potentiometer Pins of the 8-bit I2C interface slave address. A match in the slave RH and RL address serial data stream must be made with the Address RL and RH are referenced to the relative position of the input pins in order to initiate communication with the wiper and not the voltage potential on the terminals. With ISL95311. A maximum of four ISL95311 devices may occupy WR set to 127, the wiper will be closest to RH, and with the the I2C serial bus. WR set to 00, the wiper is closest to RL. Principles of Operation R W The ISL95311 is an integrated circuit incorporating one DCP RW is the wiper terminal and is equivalent to the movable with their associated register, non-volatile memory, and a terminal of a mechanical potentiometer. The position of the I2C serial interface providing direct communication between wiper within the array is determined by the WR. a host and the potentiometers and memory. The resistor Bus Interface Pins array is comprised of 127 individual resistors connected in series. At either end of the array and between each resistor SERIAL DATA INPUT/OUTPUT (SDA) is an electronic switch between that point and the wiper. The SDA is a bidirectional serial data input/output pin for the The wiper, when at either fixed terminal, acts like its I2C interface. It receives device address, operation code, mechanical equivalent and does not move beyond the last wiper register address and data from a I2C external master position. That is, the counter does not wrap around when device at the rising edge of the serial clock SCL, and it shifts clocked to either extreme. out data after each falling edge of the serial clock SCL. The electronic switches on the device operate in a “make SDA requires an external pull-up resistor, since it’s an open before break” mode when the wiper changes tap positions. drain input/output. When the device is powered-down, the last wiper position SERIAL CLOCK (SCL) stored will be maintained in the nonvolatile memory. When This input is the serial clock of the I2C serial interface. power is restored, the contents of the memory are recalled and the wiper is set to the value last stored. SCL requires an external pull-up resistor, since it’s an open drain input. FN8084 Rev 2.00 Page 6 of 12 August 13, 2015

ISL95311 On applying power to the ISL95311, the VCC supply should The volatile WR, and the non-volatile IVR of a DCP are have a monotonic ramp to the specified operating voltage. It accessed with the same address. is important that once VCC reaches 1V that it increases to at The Access Control Register (ACR) determines which word least 2.5V in less than 7.5ms (0.2V/ms). The ramp rate at address 00h is accessed (IVR or WR). The volatile ACR before and after these thresholds is not important. must be set as follows: VCC must be applied prior to, or simultaneously, with V+. When the ACR is all zeroes, which is the default at power-up: Under no condition should V+ be applied without VCC. While the sequence of applying V+ and VCC to the ISL95311 does • A read operation to address 0 outputs the value of the not affect the proper recall of the wiper position, applying V+ non-volatile IVR. before VCC powers the electronic switches of the DCP • A write operation to address 0 writes the identical values before the electronic switch control signals are applied. This to the WR and IVR of the DCP. can result in multiple electronic switches being turned on, • When the ACR is 80h: which could load the power supply and cause brief, unexpected potentiometer wiper settings. • A read operation to address 0 outputs the value of the volatile WR. To prevent unknown wiper positions on the ISL95311 on power-down, it is recommended that V+ turn off before or • A write operation to address 0 only writes to the simultaneously with VCC. If V+ remains on after VCC turns volatile WR. off, the wiper position can remain unchanged from its It is not possible to write to an IVR without writing the same previous setting or it can go to an undefined state. value to its WR. DCP Description 00h and 80h are the only values that should be written to The DCP is implemented with a combination of resistor address 2. All other values are reserved and must not be elements and CMOS switches. The physical ends of the written to address 2. DCP are equivalent to the fixed terminals of a mechanical TABLE 1. MEMORY MAP potentiometer (RH and RL pins). The RW pin is connected to intermediate nodes, and is equivalent to the wiper terminal ADDRESS NON-VOLATILE VOLATILE of a mechanical potentiometer. The position of the wiper 2 - ACR terminal within the DCP is controlled by a 7-bit volatile Wiper 1 Reserved Register (WR). When the WR contains all zeroes (00h), the wiper terminal (RW) is closest to its “Low” terminal (RL). 0 IVR WR When the WR contains all ones (7Fh), the wiper terminal WR: Wiper Register, IVR: Initial value Register. (RW) is closest to its “High” terminal (RH). As the value of the WR increases from all zeroes (00h) to all ones (7Fh), the The ISL95311 is pre-programmed with 40h in the IVR. wiper moves monotonically from the position closest to RL to 2 the position closest to RH. At the same time, the resistance I C Serial Interface between RW and RL increases monotonically, while the The ISL95311 supports a bidirectional bus oriented protocol. resistance between RH and RW decreases monotonically. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. While the ISL95311 is being powered up, the WR is reset to The device controlling the transfer is a master and the 20h (64 decimal), which locates the RW at the center between device being controlled is the slave. The master always RL and RH. Soon after the power supply voltage becomes initiates data transfers and provides the clock for both large enough for reliable non-volatile memory reading, the transmit and receive operations. Therefore, the ISL95311 ISL95311 reads the value stored on a non-volatile Initial Value operates as a slave device in all applications. Register (IVR) and loads it into the WR. The WR and IVR can be read from or written to directly using All communication over the I2C interface is conducted by the I2C serial interface as described in the following sending the MSB of each byte of data first. sections. Protocol Conventions Memory Description Data states on the SDA line can change only during SCL The ISL95311 contains 1 non-volatile byte know as the Initial LOW periods. SDA state changes during SCL HIGH are Value Register (IVR). It is accessed by the I2C interface reserved for indicating START and STOP conditions (see Figure 1). On power-up of the ISL95311, the SDA pin is in operations with Address 00h. The IVR contains the value which is loaded into the Volatile Wiper Register (WR) at the input mode. power-up. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while FN8084 Rev 2.00 Page 7 of 12 August 13, 2015

ISL95311 SCL is HIGH. The ISL95311 continuously monitors the SDA The byte at address 02h determines if the Data Byte is to be and SCL lines for the START condition and does not written to volatile and/or non-volatile memory (see “Memory respond to any command until this condition is met (see Description” on page 7). Figure 1). A START condition is ignored during the power-up Data Protection sequence and during internal non-volatile write cycles. All I2C interface operations must be terminated by a STOP A STOP condition also acts as a protection of non-volatile memory. A valid Identification Byte, Address Byte, and total condition, which is a LOW to HIGH transition of SDA while number of SCL pulses act as a protection of both volatile SCL is HIGH (see Figure 1). A STOP condition at the end of and non-volatile registers. During a Write sequence, the a read operation, or at the end of a write operation to volatile Data Byte is loaded into an internal shift register as it is bytes only places the device in its standby mode. A STOP received. If the Address Byte is 0 or 2, the Data Byte is condition during a write operation to a non-volatile byte, transferred to the Wiper Register (WR) or to the Access initiates an internal non-volatile write cycle. The device Control Register respectively, at the falling edge of the SCL enters its standby state when the internal non-volatile write pulse that loads the last bit (LSB) of the Data Byte. If the cycle is completed. Address Byte is 0, and the Access Control Register is all An ACK, Acknowledge, is a software convention used to zeros (default), then the STOP condition initiates the internal indicate a successful data transfer. The transmitting device, write cycle to non-volatile memory. either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the Read Operation receiver pulls the SDA line LOW to acknowledge the A Read operation consists of a three byte instruction reception of the eight bits of data (see Figure 2). followed by one or more Data Bytes (See Figure 4). The The ISL95311 responds with an ACK after recognition of a master initiates the operation issuing the following START condition followed by a valid Identification Byte, and sequence: a START, the Identification byte with the R/W bit once again after successful receipt of an Address Byte. The set to “0”, an Address Byte, a second START, and a second ISL95311 also responds with an ACK after receiving a Data Identification byte with the R/W bit set to “1”. After each of Byte of a write operation. The master must respond with an the three bytes, the ISL95311 responds with an ACK; then ACK after receiving a Data Byte of a read operation the ISL95311 transmits the Data Byte. The master then terminates the read operation (issuing a STOP condition) A valid Identification Byte contains 01010 as the five MSBs, following the last bit of the Data Byte (See Figure 4). and the following two bits matching the logic values present at pins A1, and A0. The LSB is in the Read/Write bit. Its The byte at address 02h determines if the Data Bytes being value is “1” for a Read operation, and “0” for a Write read are from volatile or non-volatile memory. (see “Memory operation (see Table 2.) Description” on page7.) LOGIC VALUES AT PINS A1, AND A0 RESPECTIVELY 0 1 0 1 0 A1 A0 R/W (MSB) (LSB) TABLE 2. DENTIFICATION BYTE FORMAT Write Operation A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition (see Figure 3). After each of the three bytes, the ISL95311 responds with an ACK. At this time, if the Data Byte is to be written only to volatile registers, then the device enters its standby state. If the Data Byte is to be written also to non-volatile memory, the ISL95311 begins its internal write cycle to non-volatile memory. During the internal non-volatile write cycle, the device ignores transitions at the SDA and SCL pins, and the SDA output is at a high impedance state. When the internal non-volatile write cycle is completed, the ISL95311 enters its standby state. FN8084 Rev 2.00 Page 8 of 12 August 13, 2015

ISL95311 SCL SDA START DATA DATA DATA STOP STABLE CHANGE STABLE FIGURE 1. VALID DATA CHANGES, START, AND STOP CONDITIONS SCL FROM MASTER 1 8 9 SDA OUTPUT FROM HIGH IMPEDANCE TRANSMITTER SDA OUTPUT FROM HIGH IMPEDANCE RECEIVER START ACK FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER WRITE S SIGNALS FROM T S THE MASTER A IDENTIFICATION ADDRESS DATA T R BYTE BYTE BYTE O T P SIGNAL AT SDA 0 1 0 1 0 A1A0 0 0 0 0 0 0 0 0 SIGNALS FROM A A A THE ISL95311 C C C K K K FIGURE 3. BYTE WRITE SEQUENCE S S SIGNALS T T S FROM THE A IDENTIFICATION A IDENTIFICATION A A T MASTER R BYTE WITH ADDRESS R BYTE WITH C C O T R/W = 0 BYTE T R/W = 1 K K P SIGNAL AT SDA 0 1 0 1 0 A1A00 0 0 0 0 0 0 0 0 1 0 1 0 A1A0 1 A A A SIGNALS FROM C C C FIRST READ LAST READ THE SLAVE K K K DATA BYTE DATA BYTE FIGURE 4. READ SEQUENCE FN8084 Rev 2.00 Page 9 of 12 August 13, 2015

ISL95311 Communicating with the ISL95311 Register Description: IVR and WR There are 3 register addresses in the ISL95311, of which two The ISL95311 has a single potentiometer. The wiper of the can be used. Address 00h and address 02h are used to potentiometer is controlled directly by the WR. Writes and control the device. Address 01h is reserved and should not reads can be made directly to this register to control and be used. Address 00h contains the nonvolatile Initial Value monitor the wiper position without any nonvolatile memory Register (IVR), and the volatile Wiper Register (WR). changes. This is done by setting address 02h to data 80h, Address 02h contains only a volatile word and is used as a then writing the data. pointer to either the IVR or WR. See Table 1. The nonvolatile IVR stores the power-up value of the wiper. Register Descriptions: Access Control On power-up, the contents of the IVR are transferred to the WR. The Access Control Register (ACR) is volatile and is at address 02h. It is 8-bits, and only the MSB is significant, all To write to the IVR, first address 02h is set to data 00h, then other bits should be zero (0). The ACR controls which word the data is written. Writing a new value to the IVR register is accessed at register 00h as follows: will set a new power-up position for the wiper. Also, writing to this register will load the same value into the WR as the IVR. 00h = Nonvolatile IVR So, if a new value is loaded into the IVR, not only will the 80h = Volatile WR non-volatile IVR change, but the WR will also contain the same value after the write, and the wiper position will All other bits of the ACR should be written to as zeros. Only change. Reading from the IVR will not change the WR, if its the MSB can be either 0 or 1. Power-up default for this contents are different. address is 00h. Example 1 WRITING A NEW VALUE (77H) TO THE IVR: Write to ACR first 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 1 0 A 0 0 0 0 0 0 0 0 A Then, write to IVR 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 0 0 A 0 1 1 1 0 1 1 1 A (Note that the WR will also reflect this new value since both registers get written to at the same time) Example 2 READING FROM THE WR: Write to the ACR first (to index the WR) 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 1 0 A 0 0 0 0 0 0 1 0 A Then, Set the WR address 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 0 0 A Read from the WR 0 1 0 1 0 0 0 1 A x x x x x x x x Notes: A = acknowledge, x = data bit read FN8084 Rev 2.00 Page 10 of 12 August 13, 2015

ISL95311 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE August 13, 2015 FN8084.2 Updated Ordering Information Table on page1. Added Revision History and About Intersil sections. Updated POD M10.118 to latest rev. Changes: Updated to new POD template. Added land pattern About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support © Copyright Intersil Americas LLC 2005-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8084 Rev 2.00 Page 11 of 12 August 13, 2015

ISL95311 Package Outline Drawing M10.118 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 1, 4/12 5 3.0±0.05 A DETAIL "X" D 10 1.10 MAX SIDE VIEW 2 0.09 - 0.20 4.9±0.15 3.0±0.05 5 PIN# 1 ID 0.95 REF 1 2 0.50 BSC B GAUGE TOP VIEW PLANE 0.25 3°±3° 0.55 ± 0.15 0.85±010 H DETAIL "X" C SEATING PLANE 0.18 - 0.27 0.08MCA-BD 0.10 ± 0.05 0.10C SIDE VIEW 1 (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-BA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. (0.50) 4. Plastic interlead protrusions of 0.15mm max per side are not included. (0.29) 5. Dimensions are measured at Datum Plane "H". (1.40) 6. Dimensions in ( ) are for reference only. TYPICAL RECOMMENDED LAND PATTERN FN8084 Rev 2.00 Page 12 of 12 August 13, 2015