DATASHEET ICL3221, ICL3222, ICL3223, ICL3232, ICL3241, ICL3243 FN4805 One Microamp Supply-Current, +3V to +5.5V, 250kbps, RS-232 Rev 22.00 Transmitters/Receivers September 1, 2015 The Intersil ICL32XX devices are 3.0V to 5.5V powered Features RS-232 transmitters/receivers which meet ElA/TIA-232 and • Pb-Free Plus Anneal Available as an Option V.28/V.24 specifications, even at VCC=3.0V. Targeted (RoHS Compliant) (See Ordering Info) applications are PDAs, Palmtops, and notebook and laptop computers where the low operational, and even lower • 15kV ESD Protected (Human Body Model) standby, power consumption is critical. Efficient on-chip • Drop in Replacements for MAX3221, MAX3222, charge pumps, coupled with manual and automatic MAX3223, MAX3232, MAX3241, MAX3243, SP3243 powerdown functions (except for the ICL3232), reduce the • ICL3221 is Low Power, Pin Compatible Upgrade for 5V standby supply current to a 1A trickle. Small footprint MAX221 packaging, and the use of small, low value capacitors ensure • ICL3222 is Low Power, Pin Compatible Upgrade for 5V board space savings as well. Data rates greater than MAX242, and SP312A 250kbps are guaranteed at worst case load conditions. This family is fully compatible with 3.3V only systems, mixed 3.3V • ICL3232 is Low Power Upgrade for HIN232/ICL232 and and 5.0V systems, and 5.0V only systems. Pin Compatible Competitor Devices The ICL324X are 3-driver, 5-receiver devices that provide a • RS-232 Compatible with VCC = 2.7V complete serial port suitable for laptop or notebook • Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V computers. Both devices also include noninverting always- • Latch-Up Free active receivers for “wake-up” capability. • On-Chip Voltage Converters Require Only Four External The ICL3221, ICL3223 and ICL3243, feature an 0.1F Capacitors automatic powerdown function which powers down the • Manual and Automatic Powerdown Features (Except on-chip power-supply and driver circuits. This occurs when ICL3232) an attached peripheral device is shut off or the RS-232 • Guaranteed Mouse Driveability (ICL324X Only) cable is removed, conserving system power automatically without changes to the hardware or operating system. • Receiver Hysteresis For Improved Noise Immunity These devices power up again when a valid RS-232 • Guaranteed Minimum Data Rate. . . . . . . . . . . . . 250kbps voltage is applied to any receiver input. • Guaranteed Minimum Slew Rate. . . . . . . . . . . . . . . 6V/s Table 1 summarizes the features of the devices represented • Wide Power Supply Range . . . . . . . Single +3V to +5.5V by this data sheet, while Application Note AN9863 summarizes the features of each device comprising the • Low Supply Current in Powerdown State. . . . . . . . . . .1A ICL32XX 3V family. Applications • Any System Requiring RS-232 Communication Ports - Battery Powered, Hand-Held, and Portable Equipment - Laptop Computers, Notebooks, Palmtops - Modems, Printers and other Peripherals - Digital Cameras - Cellular/Mobile Phones TABLE 1. SUMMARY OF FEATURES NO. OF DATA MANUAL AUTOMATIC NO. OF NO. OF MONITOR Rx. RATE Rx. ENABLE READY POWER- POWERDOWN PART NUMBER Tx. Rx. (ROUTB) (kbps) FUNCTION? OUTPUT? DOWN? FUNCTION? ICL3221 1 1 0 250 Yes No Yes Yes ICL3222 2 2 0 250 Yes No Yes No ICL3223 2 2 0 250 Yes No Yes Yes ICL3232 2 2 0 250 No No No No ICL3241 3 5 2 250 Yes No Yes No ICL3243 3 5 1 250 No No Yes Yes FN4805 Rev 22.00 Page 1 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Ordering Information PART NUMBER (NOTE 1) PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # ICL3221CAZ (Note 2) ICL3221CAZ 0 to 70 16 Ld SSOP (Pb-free) M16.209 ICL3221CVZ (Note 2) 3221CVZ 0 to 70 16 Ld TSSOP (Pb-free) M16.173 ICL3221IAZ (Note2) ICL3221IAZ -40 to 85 16 Ld SSOP (Pb-free) M16.209 ICL3222CAZ (Note2) ICL3222CAZ 0 to 70 20 Ld SSOP (Pb-free) M20.209 ICL3222CBZ (Note2) 3222CBZ 0 to 70 18 Ld SOIC (Pb-free) M18.3 ICL3222CPZ (Note2) (No ICL3222CPZ 0 to 70 18 Ld PDIP* (Pb-free) E18.3 longer available or supported) ICL3222CVZ (Note2) ICL3222CVZ 0 to 70 20 Ld TSSOP (Pb-free) M20.173 ICL3222IAZ (Note2) ICL3222IAZ -40 to 85 20 Ld SSOP (Pb-free) M20.209 ICL3222IVZ (Note2) ICL3222IVZ -40 to 85 20 Ld TSSOP (Pb-free) M20.173 ICL3223CAZ (Note2) ICL3223CAZ 0 to 70 20 Ld SSOP (Pb-free) M20.209 ICL3223CPZ (Note2) (No ICL3223CPZ 0 to 70 20 Ld PDIP* (Pb-free) E20.3 longer available, recommended replacement:ICL3223ECVZ) ICL3223IAZ (Note2) ICL3223IAZ -40 to 85 20 Ld SSOP (Pb-free) M20.209 ICL3223IVZ (Note2) ICL3223IVZ -40 to 85 20 Ld TSSOP (Pb-free) M20.173 ICL3232CAZ (Note2) 3232CAZ 0 to 70 16 Ld SSOP (Pb-free) M16.209 ICL3232CBZ (Note2) 3232CBZ 0 to 70 16 Ld SOIC (Pb-free) M16.3 ICL3232CBNZ (Note 2) 3232CBNZ 0 to 70 16 Ld SOIC (N) (Pb-free) M16.15 ICL3232CPZ (Note 2) ICL3232CPZ 0 to 70 16 Ld PDIP* (Pb-free) E16.3 ICL3232CVZ (Note2) 3232CVZ 0 to 70 16 Ld TSSOP (Pb-free) M16.173 ICL3232IAZ (Note2) 3232IAZ -40 to 85 16 Ld SSOP (Pb-free) M16.209 ICL3232IBZ (Note2) 3232IBZ -40 to 85 16 Ld SOIC (Pb-free) M16.3 ICL3232IBNZ (Note2) 3232IBNZ -40 to 85 16 Ld SOIC (N) (Pb-free) M16.15 ICL3232IVZ (Note2) 3232IVZ -40 to 85 16 Ld TSSOP (Pb-free) M16.173 ICL3241CAZ (Note2) ICL3241CAZ 0 to 70 28 Ld SSOP (Pb-free) M28.209 ICL3241CBZ (Note2) (No ICL3241CBZ 0 to 70 28 Ld SOIC (Pb-free) M28.3 longer available, recommended replacement:ICL3241EIVZ) ICL3241CVZ (Note2) ICL3241CVZ 0 to 70 28 Ld TSSOP (Pb-free) M28.173 ICL3241IAZ (Note2) ICL3241IAZ -40 to 85 28 Ld SSOP (Pb-free) M28.209 ICL3241IBZ (Note2) (No ICL3241IBZ -40 to 85 28 Ld SOIC (Pb-free) M28.3 longer available, recommended replacement:ICL3241EIVZ ICL3243CAZ (Note2) ICL3243CAZ 0 to 70 28 Ld SSOP (Pb-free) M28.209 ICL3243CBZ (Note2) ICL3243CBZ 0 to 70 28 Ld SOIC (Pb-free) M28.3 ICL3243CVZ (Note 2) ICL3243CVZ 0 to 70 28 Ld TSSOP (Pb-free) M28.173 ICL3243IAZ (Note 2) ICL3243IAZ -40 to 85 28 Ld SSOP (Pb-free) M28.209 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTES: 1. Most surface mount devices are available on tape and reel; add “-T” to suffix. 2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN4805 Rev 22.00 Page 2 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Pinouts ICL3221 (SSOP, TSSOP) ICL3222 (PDIP, SOIC) TOP VIEW TOP VIEW EN 1 18 SHDN EN 1 16 FORCEOFF C1+ 2 17 VCC C1+ 2 15 VCC V+ 3 16 GND V+ 3 14 GND C1- 4 15 T1OUT C1- 4 13 T1OUT C2+ 5 14 R1IN C2+ 5 12 FORCEON C2- 6 13 R1OUT C2- 6 11 T1IN V- 7 12 T1IN V- 7 10 INVALID T2OUT 8 11 T2IN R1IN 8 9 R1OUT R2IN 9 10 R2OUT ICL3222 (SSOP, TSSOP) ICL3223 (PDIP, SSOP, TSSOP) TOP VIEW TOP VIEW EN 1 20 SHDN EN 1 20 FORCEOFF C1+ 2 19 VCC C1+ 2 19 VCC V+ 3 18 GND V+ 3 18 GND C1- 4 17 T1OUT C1- 4 17 T1OUT C2+ 5 16 R1IN C2+ 5 16 R1IN C2- 6 15 R1OUT C2- 6 15 R1OUT V- 7 14 NC V- 7 14 FORCEON T2OUT 8 13 T1IN T2OUT 8 13 T1IN R2IN 9 12 T2IN R2IN 9 12 T2IN R2OUT 10 11 NC R2OUT 10 11 INVALID ICL3232 (PDIP, SOIC, SSOP, TSSOP) ICL3241 (SOIC, SSOP, TSSOP) TOP VIEW TOP VIEW C1+ 1 16 VCC C2+ 1 28 C1+ V+ 2 15 GND C2- 2 27 V+ C1- 3 14 T1OUT V- 3 26 VCC C2+ 4 13 R1IN R1IN 4 25 GND C2- 5 12 R1OUT R2IN 5 24 C1- V- 6 11 T1IN R3IN 6 23 EN T2OUT 7 10 T2IN R4IN 7 22 SHDN R2IN 8 9 R2OUT R5IN 8 21 R1OUTB T1OUT 9 20 R2OUTB T2OUT 10 19 R1OUT T3OUT 11 18 R2OUT T3IN 12 17 R3OUT T2IN 13 16 R4OUT T1IN 14 15 R5OUT FN4805 Rev 22.00 Page 3 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Pinouts (Continued) ICL3243 (SOIC, SSOP, TSSOP) TOP VIEW C2+ 1 28 C1+ C2- 2 27 V+ V- 3 26 VCC R1IN 4 25 GND R2IN 5 24 C1- R3IN 6 23 FORCEON R4IN 7 22 FORCEOFF R5IN 8 21 INVALID T1OUT 9 20 R2OUTB T2OUT 10 19 R1OUT T3OUT 11 18 R2OUT T3IN 12 17 R3OUT T2IN 13 16 R4OUT T1IN 14 15 R5OUT Pin Descriptions PIN FUNCTION VCC System power supply input (3.0V to 5.5V). V+ Internally generated positive transmitter supply (+5.5V). V- Internally generated negative transmitter supply (-5.5V). GND Ground connection. C1+ External capacitor (voltage doubler) is connected to this lead. C1- External capacitor (voltage doubler) is connected to this lead. C2+ External capacitor (voltage inverter) is connected to this lead. C2- External capacitor (voltage inverter) is connected to this lead. TIN TTL/CMOS compatible transmitter Inputs. TOUT RS-232 level (nominally 5.5V) transmitter outputs. RIN RS-232 compatible receiver inputs. ROUT TTL/CMOS level receiver outputs. ROUTB TTL/CMOS level, noninverting, always enabled receiver outputs. INVALID Active low output that indicates if no valid RS-232 levels are present on any receiver input. EN Active low receiver enable control; doesn’t disable ROUTB outputs. SHDN Active low input to shut down transmitters and on-board power supply, to place device in low power mode. FORCEOFF Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (See Table 2). FORCEON Active high input to override automatic powerdown circuitry thereby keeping transmitters active. (FORCEOFF must be high). FN4805 Rev 22.00 Page 4 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Typical Operating Circuits ICL3221 ICL3222 C3 (OPTIONAL CONNECTION, NOTE) C3 (OPTIONAL CONNECTION, NOTE) +3.3V + +3.3V + 0.1F + 0.1F + 15 17 0.1CF1 +24 C1+ VCC V+ 3 + 0C.31F 0.1CF1 + 24 C1+ VCC V+ 3 +0C.31F C1- C1- 0.1CF2 +65 C2+ V- 7 C4 0.1CF2 + 56 C2+ V- 7 C4 C2- +0.1F C2- +0.1F MOSELS T1IN 11 T1 13 T1OUT T1IN 12 T1 15 T1OUT TTL/CGIC LEV R1OUT 9 8 R1IN RS-232LEVELS MOSELS T2IN 11 T2 8 T2OUT LO 1 EN R1 5k TTL/CGIC LEV R1OUT 13 14 R1IN RS-232LEVELS FORCEOFF 16 VCC LO R1 5k 9 10 12 FORCEON INVALID 10 TO POWER R2OUT R2IN GND CLOOGNITCROL 1 EN R2 5k 14 18 SHDN VCC GND NOTE: The negative terminal of C3 can be connected to either VCC or GND 16 NOTE: The negative terminal of C3 can be connected to either VCC or GND ICL3223 ICL3232 +3.3V + C3 (OPTIONAL CONNECTION, NOTE) 0.1F 19 +3.3V + 0.1CCF12 +245 CCC112+-+ VCC V+ 3 +0C.31F 0.1CF1 + 130.1CF1+ VC1C6 V+ 2+ +0C.31F 0.1F 1+36 C2- T1 V- 177 +0C.41F 0.1CF2 + 45 CCC122-+- V- 6 C0.41F T1IN T1OUT 11 T1 14 + S 12 T2 8 T1IN T1OUT TTL/CMOSLOGIC LEVEL RR12TOO2UUINTT 1105 R1 5k 196 TRR212OIINNUT RS-232LEVELS TTL/CMOSLOGIC LEVELS R1TO2UINT 1120 R1T2 5k 713 TR21OINUT RS-232LEVELS 1 EN R2 5k R2OUT 9 8 R2IN FORCEOFF 20 VCC R2 5k 14 11 TO POWER FORCEON INVALID GND CONTROL LOGIC GND 15 18 NOTE: The negative terminal of C3 can be connected to either VCC or GND FN4805 Rev 22.00 Page 5 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Typical Operating Circuits (Continued) ICL3241 ICL3243 +3.3V + +3.3V + 0.1F 0.1F 26 26 28 0.1CF1 +2284 C1+ VCC V+ 27 +0C.31F 0.1CF1 +24 CC11+- VCC V+ 27 +0C.31F 0.1CF2 + 12 CC12-+ V- 3 C4 0.1CF2 + 12 CC22+- V- 3 C0.41F C2- 0.1F + T1IN 14 T1 9 +T1OUT T1IN 14 T1 9 T1OUT T2IN 1132 TT23 1110 T2OUT RS-232LEVELS T2IN 1132 TT23 1110 T2OUT RS-232LEVELS T3IN T3OUT T3IN T3OUT 21 R1OUTB 20 R2OUTB 20 LS R2OUTB 19 4 L/CMOSC LEVE R1OUT 19 R1 5k 4 R1IN MOSEVELS R1OUT R1 5k R1IN TTOGI L/CC L 18 5 L R2OUT 18 5 R2IN TTOGI R2OUT R2IN L R2 5k R2 5k R3OUT 17 R3 5k 6 R3IN RS-232LEVELS R3OUT 1176 R3 5k 67 R3IN RS-232LEVELS 16 7 R4OUT R4IN R4OUT R4IN R4 5k R4 5k 15 8 15 8 R5OUT R5IN R5OUT R5IN 23 R5 5k R5 5k FORCEON 23 EN C 22 GIVCC FORCEOFF 22 RO VCC SHDN GND OWEOL L 21 INVALID GND 25 TO PNTR 25 O C FN4805 Rev 22.00 Page 6 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Absolute Maximum Ratings Thermal Information VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V Thermal Resistance (Typical, Note 3) JA (°C/W) V+ to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V 16 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . 90 V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V 18 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . 80 V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V 20 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . 77 Input Voltages 16 Ld Wide SOIC Package . . . . . . . . . . . . . . . . . . . 100 TIN, FORCEOFF, FORCEON, EN, SHDN. . . . . . . . . -0.3V to 6V 16 Ld Narrow SOIC Package. . . . . . . . . . . . . . . . . . 115 RIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V 18 Ld SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . 75 Output Voltages 28 Ld SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . 75 TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2V 16 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 135 ROUT, INVALID. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V 20 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 122 Short Circuit Duration 16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 145 TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous 20 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 140 ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table 28 Ld SSOP and TSSOP Packages . . . . . . . . . . . . 100 Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C Operating Conditions Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C Temperature Range (SOIC, SSOP, TSSOP - Lead Tips Only) ICL32XXCX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C *Pb-free PDIPs can be used for through hole wave solder processing ICL32XXIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1F; Unless Otherwise Specified. Typicals are at TA = 25°C TEMP PARAMETER TEST CONDITIONS (°C) MIN TYP MAX UNITS DC CHARACTERISTICS Supply Current, Automatic All RIN Open, FORCEON=GND, FORCEOFF=VCC 25 - 1.0 10 A Powerdown (ICL3221, ICL3223, ICL3243 Only) Supply Current, Powerdown FORCEOFF=SHDN=GND (Except ICL3232) 25 - 1.0 10 A Supply Current, All Outputs Unloaded, VCC = 3.15V, 25 - 0.3 1.0 mA Automatic Powerdown Disabled FORCEON=FORCEOFF= ICL3221-32 SHDN=VCC VCC = 3.0V, ICL3241-43 25 - 0.3 1.0 mA LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS Input Logic Threshold Low TIN, FORCEON, FORCEOFF, EN, SHDN Full - - 0.8 V Input Logic Threshold High TIN, FORCEON, FORCEOFF, EN, VCC = 3.3V Full 2.0 - - V SHDN VCC = 5.0V Full 2.4 - - V Input Leakage Current TIN, FORCEON, FORCEOFF, EN, SHDN Full - 0.01 1.0 A Output Leakage Current FORCEOFF=GND or EN=VCC Full - 0.05 10 A (Except ICL3232) Output Voltage Low IOUT = 1.6mA Full - - 0.4 V Output Voltage High IOUT = -1.0mA Full VCC -0.6 VCC -0.1 - V AUTOMATIC POWERDOWN (ICL3221, ICL3223, ICL3243 Only, FORCEON = GND, FORCEOFF = VCC) Receiver Input Thresholds to ICL32XX Powers Up (See Figure 6) Full -2.7 - 2.7 V Enable Transmitters Receiver Input Thresholds to ICL32XX Powers Down (See Figure 6) Full -0.3 - 0.3 V Disable Transmitters INVALID Output Voltage Low IOUT = 1.6mA Full - - 0.4 V INVALID Output Voltage High IOUT = -1.0mA Full VCC-0.6 - - V FN4805 Rev 22.00 Page 7 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Electrical Specifications Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1F; Unless Otherwise Specified. Typicals are at TA = 25°C (Continued) TEMP PARAMETER TEST CONDITIONS (°C) MIN TYP MAX UNITS Receiver Threshold to 25 - 100 - s Transmitters Enabled Delay (tWU) Receiver Positive or Negative 25 - 1 - s Threshold to INVALID High Delay (tINVH) Receiver Positive or Negative 25 - 30 - s Threshold to INVALID Low Delay (tINVL) RECEIVER INPUTS Input Voltage Range Full -25 - 25 V Input Threshold Low VCC = 3.3V 25 0.6 1.2 - V VCC = 5.0V 25 0.8 1.5 - V Input Threshold High VCC = 3.3V 25 - 1.5 2.4 V VCC = 5.0V 25 - 1.8 2.4 V Input Hysteresis 25 - 0.3 - V Input Resistance 25 3 5 7 k TRANSMITTER OUTPUTS Output Voltage Swing All Transmitter Outputs Loaded with 3k to Ground Full 5.0 5.4 - V Output Resistance VCC=V+=V-=0V, Transmitter Output=2V Full 300 10M -  Output Short-Circuit Current Full - 35 60 mA Output Leakage Current VOUT=12V, VCC=0V or 3V to 5.5V Full - - 25 A Automatic Powerdown or FORCEOFF=SHDN=GND MOUSE DRIVEABILITY (ICL324X Only) Transmitter Output Voltage T1IN=T2IN=GND, T3IN=VCC, T3OUT Loaded with 3kto Full 5 - - V (See Figure 9) GND, T1OUT and T2OUT Loaded with 2.5mA Each TIMING CHARACTERISTICS Maximum Data Rate RL=3kCL=1000pF, One Transmitter Switching Full 250 500 - kbps Receiver Propagation Delay Receiver Input to Receiver tPHL 25 - 0.3 - s Output, CL=150pF tPLH 25 - 0.3 - s Receiver Output Enable Time Normal Operation (Except ICL3232) 25 - 200 - ns Receiver Output Disable Time Normal Operation (Except ICL3232) 25 - 200 - ns Transmitter Skew tPHL - tPLH Full - 200 1000 ns Receiver Skew tPHL - tPLH Full - 100 500 ns Transition Region Slew Rate VCC=3.3V, CL = 200pF to 2500pF 25 4 8.0 30 V/s RMLea=s3ukredt oF r7okm 3V to -3V or -3V CL = 200pF to 1000pF 25 6 - 30 V/s to 3V ESD PERFORMANCE RS-232 Pins (TOUT, RIN) Human Body Model ICL3221 - ICL3243 25 - 15 - kV IEC61000-4-2 Contact Discharge ICL3221 - ICL3243 25 - 8 - kV IEC61000-4-2 Air Gap Discharge ICL3221 - ICL3232 25 - 8 - kV ICL3241 - ICL3243 25 - 6 - kV All Other Pins Human Body Model ICL3221 - ICL3243 25 - 2 - kV FN4805 Rev 22.00 Page 8 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Detailed Description The ICL3221/22/23/41 inverting receivers disable only when EN is driven high. ICL3243 receivers disable during forced ICL32XX interface ICs operate from a single +3V to +5.5V (manual) powerdown, but not during automatic powerdown supply, guarantee a 250kbps minimum data rate, require (See Table 2). only four small external 0.1F capacitors, feature low power consumption, and meet all ElA RS-232C and V.28 ICL324X monitor receivers remain active even during specifications. The circuit is divided into three sections: manual powerdown and forced receiver disable, making charge pump, transmitters and receivers. them extremely useful for Ring Indicator monitoring. Standard receivers driving powered down peripherals must Charge-Pump be disabled to prevent current flow through the peripheral’s Intersil’s new ICL32XX family utilizes regulated on-chip dual protection diodes (See Figures 2 and 3). This renders them charge pumps as voltage doublers, and voltage inverters to useless for wake up functions, but the corresponding generate 5.5V transmitter supplies from a VCC supply as monitor receiver can be dedicated to this task as shown in low as 3.0V. This allows these devices to maintain RS-232 Figure 3. compliant output levels over the 10% tolerance range of 3.3V powered systems. The efficient on-chip power supplies VCC require only four small, external 0.1F capacitors for the RXIN RXOUT voltage doubler and inverter functions at VCC=3.3V. See -25V  VRIN  +25V 5k GND  VROUT  VCC the Capacitor Selection section, and Table 3 for capacitor GND recommendations for other operating conditions. The charge pumps operate discontinuously (i.e., they turn off as soon as FIGURE 1. INVERTING RECEIVER CONNECTIONS the V+ and V- supplies are pumped up to the nominal values), resulting in significant power savings. Low Power Operation Transmitters These 3V devices require a nominal supply current of 0.3mA, even at VCC=5.5V, during normal operation (not in The transmitters are proprietary, low dropout, inverting powerdown mode). This is considerably less than the 5mA drivers that translate TTL/CMOS inputs to EIA/TIA-232 to 11mA current required by comparable 5V RS-232 devices, output levels. Coupled with the on-chip 5.5V supplies, allowing users to reduce system power simply by switching these transmitters deliver true RS-232 levels over a wide to this new family. range of single supply system voltages. Pin Compatible Replacements For 5V Devices Except for the ICL3232, all transmitter outputs disable and assume a high impedance state when the device enters the The ICL3221/22/32 are pin compatible with existing 5V powerdown mode (See Table 2). These outputs may be RS-232 transceivers - see the Features section on the front driven to 12V when disabled. page for details. All devices guarantee a 250kbps data rate for full load This pin compatibility coupled with the low Icc and wide conditions (3k and 1000pF), VCC  3.0V, with one operating supply range, make the ICL32XX potential lower power, higher performance drop-in replacements for existing transmitter operating at full speed. Under more typical conditions of VCC3.3V, RL=3k, and CL=250pF, one 5V applications. As long as the 5V RS-232 output swings are acceptable, and transmitter input pull-up resistors aren’t transmitter easily operates at 900kbps. required, the ICL32XX should work in most 5V applications. Transmitter inputs float if left unconnected, and may cause When replacing a device in an existing 5V application, it is ICC increases. Connect unused inputs to GND for the best performance. acceptable to terminate C3 to VCC as shown on the Typical Operating Circuit. Nevertheless, terminate C3 to GND if Receivers possible, as slightly better performance results from this All the ICL32XX devices contain standard inverting receivers configuration. that three-state (except for the ICL3232) via the EN or Powerdown Functionality (Except ICL3232) FORCEOFF control lines. Additionally, the two ICL324X products include noninverting (monitor) receivers (denoted The already low current requirement drops significantly by the ROUTB label) that are always active, regardless of the when the device enters powerdown mode. In powerdown, state of any control lines. All the receivers convert RS-232 supply current drops to 1A, because the on-chip charge signals to CMOS output levels and accept inputs up to 25V pump turns off (V+ collapses to VCC, V- collapses to GND), while presenting the required 3k to 7k input impedance and the transmitter outputs three-state. Inverting receiver (See Figure 1) even if the power is off (VCC = 0V). The outputs may or may not disable in powerdown; refer to receivers’ Schmitt trigger input stage uses hysteresis to Table2 for details. This micro-power mode makes these increase noise immunity and decrease errors due to slow devices ideal for battery powered and portable applications. input signal transitions. FN4805 Rev 22.00 Page 9 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Software Controlled (Manual) Powerdown The ICL3221, ICL3223, and ICL3243 utilize a two pin Most devices in the ICL32XX family provide pins that allow approach where the FORCEON and FORCEOFF inputs the user to force the IC into the low power, standby state. determine the IC’s mode. For always enabled operation, FORCEON and FORCEOFF are both strapped high. To On the ICL3222 and ICL3241, the powerdown control is via switch between active and powerdown modes, under logic a simple shutdown (SHDN) pin. Driving this pin high enables or software control, only the FORCEOFF input need be normal operation, while driving it low forces the IC into its driven. The FORCEON state isn’t critical, as FORCEOFF powerdown state. Connect SHDN to VCC if the powerdown dominates over FORCEON. Nevertheless, if strictly manual function isn’t needed. Note that all the receiver outputs control over powerdown is desired, the user must strap remain enabled during shutdown (See Table 2). For the FORCEON high to disable the automatic powerdown lowest power consumption during powerdown, the receivers circuitry. ICL3243 inverting (standard) receiver outputs also should also be disabled by driving the EN input high (See disable when the device is in manual powerdown, thereby next section, and Figures 2 and 3). eliminating the possible current path through a shutdown peripheral’s input protection diode (See Figures 2 and 3). TABLE 2. POWERDOWN AND ENABLE LOGIC TRUTH TABLE RS-232 SIGNAL PRESENT AT FORCEOFF (NOTE 4) RECEIVER OR SHDN FORCEON EN TRANSMITTER RECEIVER ROUTB INVALID INPUT? INPUT INPUT INPUT OUTPUTS OUTPUTS OUTPUTS OUTPUT MODE OF OPERATION ICL3222, ICL3241 N.A. L N.A. L High-Z Active Active N.A. Manual Powerdown N.A. L N.A. H High-Z High-Z Active N.A. Manual Powerdown w/Rcvr. Disabled N.A. H N.A. L Active Active Active N.A. Normal Operation N.A. H N.A. H Active High-Z Active N.A. Normal Operation w/Rcvr. Disabled ICL3221, ICL3223 No H H L Active Active N.A. L Normal Operation (Auto Powerdown Disabled) No H H H Active High-Z N.A. L Yes H L L Active Active N.A. H Normal Operation (Auto Powerdown Enabled) Yes H L H Active High-Z N.A. H No H L L High-Z Active N.A. L Powerdown Due to Auto Powerdown Logic No H L H High-Z High-Z N.A. L Yes L X L High-Z Active N.A. H Manual Powerdown Yes L X H High-Z High-Z N.A. H Manual Powerdown w/Rcvr. Disabled No L X L High-Z Active N.A. L Manual Powerdown No L X H High-Z High-Z N.A. L Manual Powerdown w/Rcvr. Disabled ICL3243 No H H N.A. Active Active Active L Normal Operation (Auto Powerdown Disabled) Yes H L N.A. Active Active Active H Normal Operation (Auto Powerdown Enabled) No H L N.A. High-Z Active Active L Powerdown Due to Auto Powerdown Logic Yes L X N.A. High-Z High-Z Active H Manual Powerdown No L X N.A. High-Z High-Z Active L Manual Powerdown NOTE: 4. Applies only to the ICL3241 and ICL3243. FN4805 Rev 22.00 Page 10 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 The INVALID output always indicates whether or not a valid FORCEOFF RS-232 signal is present at any of the receiver inputs (See PWR Table 2), giving the user an easy way to determine when the MGT FORCEON LOGIC interface block should power down. In the case of a disconnected interface cable where all the receiver inputs INVALID are floating (but pulled to GND by the internal receiver pull ICL3221/23/43 down resistors), the INVALID logic detects the invalid levels and drives the output low. The power management logic then uses this indicator to power down the interface block. Reconnecting the cable restores valid levels at the receiver I/O UART inputs, INVALID switches high, and the power management CPU logic wakes up the interface block. INVALID can also be used to indicate the DTR or RING INDICATOR signal, as long as the other receiver inputs are floating, or driven to GND (as in the case of a powered down driver). Connecting FORCEOFF and FORCEON together disables the FIGURE 4. CONNECTIONS FOR MANUAL POWERDOWN automatic powerdown feature, enabling them to function as WHEN NO VALID RECEIVER SIGNALS ARE a manual SHUTDOWN input (See Figure 4). PRESENT With any of the above control schemes, the time required to VCC exit powerdown, and resume transmission is only 100s. A VCC mouse, or other application, may need more time to wake up CURRENT from shutdown. If automatic powerdown is being utilized, the VCC FLOW RS-232 device will reenter powerdown if valid receiver levels aren’t reestablished within 30s of the ICL32XX powering VOUT = VCC up. Figure 5 illustrates a circuit that keeps the ICL32XX from Rx initiating automatic powerdown for 100ms after powering up. POWERED This gives the slow-to-wake peripheral circuit time to DOWN UART reestablish valid RS-232 output levels. Tx GND SHDN = GND RS-2O3L2D CHIP POWER MASTER POWERDOWN LINE MANAGEMENT UNIT 0.1F 1M FIGURE 2. POWER DRAIN THROUGH POWERED DOWN PERIPHERAL FORCEOFF FORCEON ICL3221/23/43 VCC FIGURE 5. CIRCUIT TO PREVENT AUTO POWERDOWN FOR TRANSITION 100ms AFTER FORCED POWERUP DETECTOR TO ICL324X WAKE-UP Automatic Powerdown (ICL3221/23/43 Only) LOGIC Even greater power savings is available by using the VCC devices which feature an automatic powerdown function. R2OUTB When no valid RS-232 voltages (See Figure 6) are sensed RX VOUT = HI-Z on any receiver input for 30s, the charge pump and PODWOEWRNED R2OUT R2IN t1raAns. mInivttaelrids preocweeivredro wlenv,e tlsh eorcecbuyr rwehdeuncienvge sr uthpep ldyr civuinrrge nt to UART TX T1IN peripheral’s outputs are shut off (powered down) or when the RS-232 interface cable is disconnected. The ICL32XX T1OUT powers back up whenever it detects a valid RS-232 voltage FORCEOFF = GND level on any receiver input. This automatic powerdown OR SHDN = GND, EN = VCC feature provides additional system power savings without FIGURE 3. DISABLED RECEIVERS PREVENT POWER DRAIN changes to the existing operating system. FN4805 Rev 22.00 Page 11 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 (standard) receiver outputs placing them in a high VALID RS-232 LEVEL - ICL32XX IS ACTIVE impedance state. This is useful to eliminate supply current, 2.7V due to a receiver output forward biasing the protection diode, INDETERMINATE - POWERDOWN MAY OR MAY NOT OCCUR when driving the input of a powered down (VCC=GND) peripheral (See Figure 2). The enable input has no effect on 0.3V transmitter nor monitor (ROUTB) outputs. INVALID LEVEL - POWERDOWN OCCURS AFTER 30ms -0.3V Capacitor Selection INDETERMINATE - POWERDOWN MAY OR The charge pumps require 0.1F capacitors for 3.3V MAY NOT OCCUR operation. For other supply voltages refer to Table 3 for -2.7V capacitor values. Do not use values smaller than those listed VALID RS-232 LEVEL - ICL32XX IS ACTIVE in Table 3. Increasing the capacitor values (by a factor of 2) reduces ripple on the transmitter outputs and slightly FIGURE 6. DEFINITION OF VALID RS-232 RECEIVER LEVELS reduces power consumption. C2, C3, and C4 can be increased without increasing C1’s value, however, do not Automatic powerdown operates when the FORCEON input increase C1 without also increasing C2, C3, and C4 to is low, and the FORCEOFF input is high. Tying FORCEON maintain the proper ratios (C1 to the other capacitors). high disables automatic powerdown, but manual powerdown is always available via the overriding FORCEOFF input. When using minimum required capacitor values, make sure Table 2 summarizes the automatic powerdown functionality. that capacitor values do not degrade excessively with temperature. If in doubt, use capacitors with a larger nominal Devices with the automatic powerdown feature include an value. The capacitor’s equivalent series resistance (ESR) INVALID output signal, which switches low to indicate that usually rises at low temperatures and it influences the invalid levels have persisted on all of the receiver inputs for amount of ripple on V+ and V-. more than 30s (See Figure 7). INVALID switches high 1s after detecting a valid RS-232 level on a receiver input. TABLE 3. REQUIRED CAPACITOR VALUES INVALID operates in all modes (forced or automatic VCC C1 C2, C3, C4 powerdown, or forced on), so it is also useful for systems (V) (F) (F) employing manual powerdown circuitry. When automatic 3.0 to 3.6 0.1 0.1 powerdown is utilized, INVALID=0 indicates that the ICL32XX is in powerdown mode. 4.5 to 5.5 0.047 0.33 3.0 to 5.5 0.1 0.47 RECEIVER INVALID INPUTS }REGION Power Supply Decoupling In most circumstances a 0.1F bypass capacitor is TRANSMITTER adequate. In applications that are particularly sensitive to OUTPUTS power supply noise, decouple VCC to ground with a INVALID VCC tINVL tINVH cCaopnanceitcotr t ohfe t hbeyp saasms ec avaplauceit oasr athse c clohsaer gaes- ppuomsspib claep taoc tihtoer ICC1.. OUTPUT 0 AUTOPWDN PWR UP Operation Down to 2.7V V+ ICL32XX transmitter outputs meet RS-562 levels (3.7V), at VCC full data rate, with VCC as low as 2.7V. RS-562 levels 0 typically ensure interoperability with RS-232 devices. V- Transmitter Outputs when Exiting Powerdown FIGURE 7. AUTOMATIC POWERDOWN AND INVALID TIMING DIAGRAMS Figure 8 shows the response of two transmitter outputs when exiting powerdown mode. As they activate, the two transmitter outputs properly go to opposite RS-232 levels, The time to recover from automatic powerdown mode is with no glitching, ringing, nor undesirable transients. Each typically 100s. transmitter is loaded with 3kin parallel with 2500pF. Note Receiver ENABLE Control (ICL3221/22/23/41 Only) that the transmitters enable only when the magnitude of the Several devices also feature an EN input to control the supplies exceed approximately 3V. receiver outputs. Driving EN high disables all the inverting FN4805 Rev 22.00 Page 12 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 for a single transmitter driving 1000pF and an RS-232 load at 250kbps. The static transmitters were also loaded with an 5V/DIV FORCEOFF RS-232 receiver. T1 VCC + 0.1F 2V/DIV + C1+ VCC V+ C1 +C3 C1- ICL32XX T2 + C2+ V- C2 +C4 VCC = +3.3V C2- C1 - C4 = 0.1F TIME (20s/DIV) TIN TOUT FIGURE 8. TRANSMITTER OUTPUTS WHEN EXITING POWERDOWN ROUT RIN 1000pF EN 5K Mouse Driveability SHDN OR The ICL324X have been specifically designed to power a VCC FORCEOFF serial mouse while operating from low voltage supplies. Figure 9 shows the transmitter output voltages under FIGURE 10. TRANSMITTER LOOPBACK TEST CIRCUIT increasing load current. The on-chip switching regulator ensures the transmitters will supply at least 5V during worst case conditions (15mA for paralleled V+ transmitters, 7.3mA 5V/DIV for single V- transmitter). The Automatic Powerdown feature does not work with a mouse, so FORCEOFF and T1IN FORCEON should be connected to VCC. 6 T1OUT V) 5 GE ( 4 VOUT+ A LT 3 T VO 2 VCC = 3.0V R1OUT U 1 OUTP 0 T1 VOUT+ VCC1 C- C= 4+ 3=. 30V.1F ER -1 T2 5s/DIV TT -2 ICL3241/43 FIGURE 11. LOOPBACK TEST AT 120kbps MI -3 ANS -4 VCC T3 VOUT - VOUT - R T -5 -6 5V/DIV. 0 1 2 3 4 5 6 7 8 9 10 LOAD CURRENT PER TRANSMITTER (mA) T1IN FIGURE 9. TRANSMITTER OUTPUT VOLTAGE vs LOAD CURRENT (PER TRANSMITTER, i.e., DOUBLE CURRENT AXIS FOR TOTAL VOUT+ CURRENT) T1OUT High Data Rates The ICL32XX maintain the RS-232 5V minimum transmitter output voltages even at high data rates. Figure 10 details a R1OUT transmitter loopback test circuit, and Figure 11 illustrates the loopback test result at 120kbps. For this test, all transmitters VCC = +3.3V C1 - C4 = 0.1F were simultaneously driving RS-232 loads in parallel with 2s/DIV. 1000pF, at 120kbps. Figure 12 shows the loopback results FIGURE 12. LOOPBACK TEST AT 250kbps FN4805 Rev 22.00 Page 13 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Interconnection with 3V and 5V Logic TABLE 4. LOGIC FAMILY COMPATIBILITY WITH VARIOUS SUPPLY VOLTAGES The ICL32XX directly interface with 5V CMOS and TTL logic families. Nevertheless, with the ICL32XX at 3.3V, and the SYSTEM VCC logic supply at 5V, AC, HC, and CD4000 outputs can drive POWER-SUPPLY SUPPLY VOLTAGE VOLTAGE ICL32XX inputs, but ICL32XX outputs do not reach the (V) (V) COMPATIBILITY minimum VIH for these logic families. See Table 4 for more information. 3.3 3.3 Compatible with all CMOS families. 5 5 Compatible with all TTL and CMOS logic families. 5 3.3 Compatible with ACT and HCT CMOS, and with TTL. ICL32XX outputs are incompatible with AC, HC, and CD4000 CMOS inputs. Typical Performance Curves VCC = 3.3V, TA = 25°C 6 25 E (V) VOUT+ G 4 A T 20 L VO 2 s) T 1 TRANSMITTER AT 250kbps V/ PU 1 OR 2 TRANSMITTERS AT 30kbps E ( UT 0 AT 15 O R R W -SLEW TTE -2 SLE +SLEW MI 10 NS -4 VOUT - A R T -6 5 0 1000 2000 3000 4000 5000 0 1000 2000 3000 4000 5000 LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF) FIGURE 13. TRANSMITTER OUTPUT VOLTAGE vs LOAD FIGURE 14. SLEW RATE vs LOAD CAPACITANCE CAPACITANCE 45 45 ICL3221 ICL3222 - ICL3232 40 40 250kbps A) 35 250kbps A) 35 m m T ( 30 T ( 30 N N E E R 25 R 25 120kbps R R U U C 20 120kbps C 20 Y Y L L PP 15 PP 15 20kbps U U S 10 20kbps S 10 5 5 0 0 0 1000 2000 3000 4000 5000 0 1000 2000 3000 4000 5000 LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF) FIGURE 15. SUPPLY CURRENT vs LOAD CAPACITANCE FIGURE 16. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA WHEN TRANSMITTING DATA FN4805 Rev 22.00 Page 14 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Typical Performance Curves VCC = 3.3V, TA = 25°C (Continued) 3.5 45 NO LOAD ICL324X 250kbps ALL OUTPUTS STATIC 40 3.0 ICL3221 - ICL3232 A) 35 mA) 2.5 NT (m 30 120kbps ENT ( 2.0 RE 25 RR R U CU 20 Y C 1.5 PPLY 15 20kbps UPPL 1.0 U S S 10 0.5 ICL324X 5 ICL324X 0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 1000 2000 3000 4000 5000 SUPPLY VOLTAGE (V) LOAD CAPACITANCE (pF) FIGURE 17. SUPPLY CURRENT vs LOAD CAPACITANCE FIGURE 18. SUPPLY CURRENT vs SUPPLY VOLTAGE WHEN TRANSMITTING DATA Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: ICL3221: 286 ICL3222: 338 ICL3223: 357 ICL3232: 296 ICL324X: 464 PROCESS: Si Gate CMOS FN4805 Rev 22.00 Page 15 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE September 1, 2015 FN4805.22 - Ordering Information Table on page2. - Added Revision History. - Added About Intersil Verbiage. - Updated POD M16.173 to latest revision changes are as follow: Convert to new POD format by moving dimensions from table onto drawing and adding land pattern. No dimension changes. - Updated POD M20.173 to most current version changes are as follow: Convert to new POD format by moving dimensions from table onto drawing and adding land pattern. No dimension changes. - Updated POD M28.173 to most current version changes are as follow: Convert to new POD format by moving dimensions from table onto drawing and adding land pattern. No dimension changes. -Updated POD M28.3 to most current version change is as follows: Added land pattern. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. FN4805 Rev 22.00 Page 16 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Dual-In-Line Plastic Packages (PDIP) E16.3 (JEDEC MS-001-BB ISSUE D) N 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX INCHES MILLIMETERS AREA 1 2 3 N/2 SYMBOL MIN MAX MIN MAX NOTES -B- A - 0.210 - 5.33 4 -A- D E A1 0.015 - 0.39 - 4 BASE A2 0.115 0.195 2.93 4.95 - PLANE A2 -C- A B 0.014 0.022 0.356 0.558 - SEATING PLANE L CL B1 0.045 0.070 1.15 1.77 8, 10 D1 D1 A1 eA C 0.008 0.014 0.204 0.355 - B1 e eC C D 0.735 0.775 18.66 19.68 5 B e D1 0.005 - 0.13 - 5 B 0.010 (0.25) M C A B S E 0.300 0.325 7.62 8.25 6 NOTES: E1 0.240 0.280 6.10 7.11 5 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. e 0.100 BSC 2.54 BSC - 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 7.62 BSC 6 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of eB - 0.430 - 10.92 7 Publication No. 95. L 0.115 0.150 2.93 3.81 4 4. Dimensions A, A1 and L are measured with the package seated in JE- DEC seating plane gauge GS-3. N 16 16 9 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Rev. 0 12/93 Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendic- ular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN4805 Rev 22.00 Page 17 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Dual-In-Line Plastic Packages (PDIP) N E18.3 (JEDEC MS-001-BC ISSUE D) E1 18 LEAD DUAL-IN-LINE PLASTIC PACKAGE INDEX AREA 1 2 3 N/2 INCHES MILLIMETERS -B- SYMBOL MIN MAX MIN MAX NOTES -A- A - 0.210 - 5.33 4 D E A1 0.015 - 0.39 - 4 BASE PLANE A2 -C- A A2 0.115 0.195 2.93 4.95 - SEATING PLANE L CL B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 D1 D1 A1 eA B1 e eC C C 0.008 0.014 0.204 0.355 - B D 0.845 0.880 21.47 22.35 5 e B 0.010 (0.25) M C A B S D1 0.005 - 0.13 - 5 NOTES: E 0.300 0.325 7.62 8.25 6 1. Controlling Dimensions: INCH. In case of conflict between English and E1 0.240 0.280 6.10 7.11 5 Metric dimensions, the inch dimensions control. e 0.100 BSC 2.54 BSC - 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of eA 0.300 BSC 7.62 BSC 6 Publication No. 95. eB - 0.430 - 10.92 7 4. Dimensions A, A1 and L are measured with the package seated in L 0.115 0.150 2.93 3.81 4 JEDEC seating plane gauge GS-3. N 18 18 9 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). Rev. 2 11/03 6. E and eA are measured with the leads constrained to be perpendic- ular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3 may have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN4805 Rev 22.00 Page 18 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Small Outline Plastic Packages (SOIC) N M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES MILLIMETERS E SYMBOL MIN MAX MIN MAX NOTES -B- A 0.0532 0.0688 1.35 1.75 - 1 2 3 A1 0.0040 0.0098 0.10 0.25 - L B 0.013 0.020 0.33 0.51 9 SEATING PLANE C 0.0075 0.0098 0.19 0.25 - -A- D A h x 45° D 0.3859 0.3937 9.80 10.00 3 E 0.1497 0.1574 3.80 4.00 4 -C- e 0.050 BSC 1.27 BSC -  e H 0.2284 0.2440 5.80 6.20 - A1 C h 0.0099 0.0196 0.25 0.50 5 B 0.10(0.004) L 0.016 0.050 0.40 1.27 6 0.25(0.010) M C A M B S N 16 16 7 NOTES:  0° 8° 0° 8° - 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Rev. 1 6/05 Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. FN4805 Rev 22.00 Page 19 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Package Outline Drawing M16.173 16 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 2, 5/10 A 1 3 5.00 ±0.10 16 9 SEE DETAIL "X" 6.40 PIN #1 4.40 ±0.10 I.D. MARK 2 3 0.20 C B A 1 8 0.65 B 0.09-0.20 TOP VIEW END VIEW H - 0.05 1.00 REF C 1.20 MAX 0.90 +0.15/-0.10 SEATING PLANE GAUGE 0.25 +0.05/-0.06 5 PLANE 0.25 0.10MCBA 0.10C 0.05 MIN 0°-8° 0.15 MAX 0.60 ±0.15 SIDE VIEW DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead (0.65 TYP) (0.35 TYP) is 0.07mm. 6. Dimension in ( ) are for reference only. TYPICAL RECOMMENDED LAND PATTERN 7. Conforms to JEDEC MO-153. FN4805 Rev 22.00 Page 20 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Small Outline Plastic Packages (SSOP) M16.209 (JEDEC MO-150-AC ISSUE B) N 16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES MILLIMETERS E GAUGE SYMBOL MIN MAX MIN MAX NOTES -B- PLANE A - 0.078 - 2.00 - 1 2 3 A1 0.002 - 0.05 - - A2 0.065 0.072 1.65 1.85 - L SEATING PLANE 0.25 B 0.009 0.014 0.22 0.38 9 0.010 -A- C 0.004 0.009 0.09 0.25 - D A D 0.233 0.255 5.90 6.50 3 -C- E 0.197 0.220 5.00 5.60 4  e 0.026 BSC 0.65 BSC - e A1 A2 C H 0.292 0.322 7.40 8.20 - B 0.10(0.004) L 0.022 0.037 0.55 0.95 6 0.25(0.010) M C A M B S N 16 16 7  0° 8° 0° 8° - NOTES: Rev. 3 6/05 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimen- sion at maximum material condition. 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. FN4805 Rev 22.00 Page 21 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Small Outline Plastic Packages (SOIC) M16.3 (JEDEC MS-013-AA ISSUE C) N 16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES MILLIMETERS E SYMBOL MIN MAX MIN MAX NOTES -B- A 0.0926 0.1043 2.35 2.65 - 1 2 3 A1 0.0040 0.0118 0.10 0.30 - L B 0.013 0.0200 0.33 0.51 9 SEATING PLANE C 0.0091 0.0125 0.23 0.32 - -A- D 0.3977 0.4133 10.10 10.50 3 D A h x 45° E 0.2914 0.2992 7.40 7.60 4 -C- e 0.050 BSC 1.27 BSC -  H 0.394 0.419 10.00 10.65 - e A1 C h 0.010 0.029 0.25 0.75 5 B 0.10(0.004) L 0.016 0.050 0.40 1.27 6 0.25(0.010) M C A M B S N 16 16 7 NOTES:  0° 8° 0° 8° - 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Rev. 1 6/05 Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. FN4805 Rev 22.00 Page 22 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Small Outline Plastic Packages (SOIC) M18.3 (JEDEC MS-013-AB ISSUE C) N 18 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES MILLIMETERS E SYMBOL MIN MAX MIN MAX NOTES -B- A 0.0926 0.1043 2.35 2.65 - 1 2 3 A1 0.0040 0.0118 0.10 0.30 - L B 0.013 0.0200 0.33 0.51 9 SEATING PLANE C 0.0091 0.0125 0.23 0.32 - -A- D 0.4469 0.4625 11.35 11.75 3 D A h x 45° E 0.2914 0.2992 7.40 7.60 4 -C- e 0.050 BSC 1.27 BSC -  H 0.394 0.419 10.00 10.65 - e A1 C h 0.010 0.029 0.25 0.75 5 B 0.10(0.004) L 0.016 0.050 0.40 1.27 6 0.25(0.010) M C A M B S N 18 18 7  0° 8° 0° 8° - NOTES: Rev. 1 6/05 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. FN4805 Rev 22.00 Page 23 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Package Outline Drawing M20.173 20 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 2, 5/10 A 1 3 6.50 ±0.10 20 10 SEE DETAIL "X" 6.40 PIN #1 I.D. MARK 4.40 ±0.10 2 3 0.20 C B A 1 9 0.65 B 0.09-0.20 TOP VIEW END VIEW 1.00 REF H - 0.05 C 0.90 +0.15/-0.10 1.20 MAX SEATING GAUGE PLANE PLANE 0.25 0.25 +0.05/-0.06 5 0.10C 0.10MCBA 0.05 MIN 0°-8° 0.15 MAX 0.60 ±0.15 SIDE VIEW DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead (0.65 TYP) (0.35 TYP) is 0.07mm. 6. Dimension in ( ) are for reference only. TYPICAL RECOMMENDED LAND PATTERN 7. Conforms to JEDEC MO-153. FN4805 Rev 22.00 Page 24 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Shrink Small Outline Plastic Packages (SSOP) M20.209 (JEDEC MO-150-AE ISSUE B) N 20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE IANRDEEAX H 0.25(0.010) M B M INCHES MILLIMETERS E GAUGE SYMBOL MIN MAX MIN MAX NOTES -B- PLANE A 0.068 0.078 1.73 1.99 A1 0.002 0.008’ 0.05 0.21 1 2 3 A2 0.066 0.070’ 1.68 1.78 L SEATING PLANE 0.25 B 0.010’ 0.015 0.25 0.38 9 0.010 -A- C 0.004 0.008 0.09 0.20’ D A D 0.278 0.289 7.07 7.33 3 -C- E 0.205 0.212 5.20’ 5.38 4  e 0.026 BSC 0.65 BSC e A2 A1 C H 0.301 0.311 7.65 7.90’ B 0.10(0.004) L 0.025 0.037 0.63 0.95 6 0.25(0.010) M C A M B S N 20 20 7  0 deg. 8 deg. 0 deg. 8 deg. NOTES: Rev. 3 11/02 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. In- terlead flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimension at maximum material condition. 10. Controlling dimension: MILLIMETER. Converted inch dimen- sions are not necessarily exact. FN4805 Rev 22.00 Page 25 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Package Outline Drawing M28.173 28 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 1, 5/10 A 1 3 9.70± 0.10 SEE DETAIL "X" 28 15 6.40 PIN #1 4.40 ± 0.10 I.D. MARK 2 3 0.20 C B A 1 14 +0.05 0.15 0.65 B -0.06 TOP VIEW END VIEW 1.00 REF H - 0.05 C 0.90+0.15 -0.10 1.20 MAX GAUGE PLANE 0.25 SEATING PLANE +0.05 0.25-0.06 5 0.05 MIN 0°-8° 0.10C 0.10MCBA 0.15 MAX 0.60 ±0.15 SIDE VIEW DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead (0.65 TYP) (0.35 TYP) is 0.07mm. 6. Dimension in ( ) are for reference only. TYPICAL RECOMMENDED LAND PATTERN 7. Conforms to JEDEC MO-153. FN4805 Rev 22.00 Page 26 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Shrink Small Outline Plastic Packages (SSOP) M28.209 (JEDEC MO-150-AH ISSUE B) N 28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES MILLIMETERS E GAUGE SYMBOL MIN MAX MIN MAX NOTES -B- PLANE A - 0.078 - 2.00 - 1 2 3 A1 0.002 - 0.05 - - A2 0.065 0.072 1.65 1.85 - L SEATING PLANE 0.25 B 0.009 0.014 0.22 0.38 9 0.010 -A- C 0.004 0.009 0.09 0.25 - D A D 0.390 0.413 9.90 10.50 3 -C- E 0.197 0.220 5.00 5.60 4  e 0.026 BSC 0.65 BSC - e A1 A2 C H 0.292 0.322 7.40 8.20 - B 0.10(0.004) L 0.022 0.037 0.55 0.95 6 0.25(0.010) M C A M B S N 28 28 7 NOTES:  0° 8° 0° 8° - 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 Rev. 2 6/05 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimension at maximum material condition. 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. FN4805 Rev 22.00 Page 27 of 28 September 1, 2015

ICL3221, ICL3222, ICL3223, ICL3232,ICL3241,ICL3243 Small Outline Plastic Packages (SOIC) M28.3 (JEDEC MS-013-AE ISSUE C) N 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES MILLIMETERS E SYMBOL MIN MAX MIN MAX NOTES -B- A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - 1 2 3 L B 0.013 0.0200 0.33 0.51 9 SEATING PLANE C 0.0091 0.0125 0.23 0.32 - -A- D 0.6969 0.7125 17.70 18.10 3 D A h x 45o E 0.2914 0.2992 7.40 7.60 4 -C- e 0.05 BSC 1.27 BSC - a H 0.394 0.419 10.00 10.65 - e A1 C h 0.01 0.029 0.25 0.75 5 B 0.10(0.004) L 0.016 0.050 0.40 1.27 6 0.25(0.010) M C A M B S N 28 28 7  0o 8o 0o 8o - Rev. 1, 1/13 NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. TYPICAL RECOMMENDED LAND PATTERN Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead (1.50mm) flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. (9.38mm) 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) (1.27mm TYP) (0.51mm TYP) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. © Copyright Intersil Americas LLC 1999-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN4805 Rev 22.00 Page 28 of 28 September 1, 2015

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: R enesas Electronics: ICL3221CAZ ICL3221CAZ-T ICL3221CVZ ICL3221CVZ-T ICL3221IAZ ICL3221IAZ-T ICL3232CBNZ ICL3232CBNZ-T ICL3232CVZ ICL3232CVZ-T ICL3232IBNZ ICL3232IBNZ-T ICL3222CVZ ICL3222CVZ-T ICL3223IAZ ICL3223IAZ-T ICL3223IVZ ICL3223IVZ-T ICL3232CPZ ICL3232IVZ ICL3232IVZ-T ICL3243CBZ ICL3243CBZ-T ICL3232IVZ-T7A