HCPL-260L/060L/263L/063L High Speed LVTTL Compatible 3.3 V Optocouplers Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features The HCPL-260L/060L/263L/063L are optically coupled • 3.3V/5V Dual Supply Voltages gates that combine a GaAsP light emitting diode and • Low power consumption an integrated high gain photo detector. An enable in- • 15 kV/µs minimum Common Mode Rejection (CMR) at put allows the detector to be strobed. The output of the detector IC is an open collector Schottky-clamped VCM = 1000 V transistor. The internal shield provides a guaranteed • High speed: 15 MBd typical common mode transient immunity specification of • LVTTL/LVCMOS compatible 15 kV/µs at 3.3V. • Low input current capability: 5 mA This unique design provides maximum AC and DC circuit • Guaranteed AC and DC performance over tempera- isolation while achieving LVTTL/LVCMOS compati-bili- ture: –40 °C to +85 °C ty. The optocoupler AC and DC operational parameters are guaranteed from –40 °C to +85 °C allowing trouble- • Available in 8-pin DIP, SOIC-8 free system performance. • Strobable output (single channel products only) These optocouplers are suitable for high speed logic • Safety approvals: UL, CSA, IEC/EN/DIN EN 60747-5-5 interfacing, input/output buffering, as line receivers in environments that conventional line receivers cannot Applications tolerate and are recommended for use in extremely high ground or induced noise environments. • Isolated line receiver • Computer-peripheral interfaces Functional Diagram HCPL-260L/060L HCPL-263L/063L • Microprocessor system interfaces NC 1 8 VCC ANODE 1 1 8 VCC • Digital isolation for A/D, D/A conversion ANODE 2 7 VE CATHODE 1 2 7 VO1 • Switching power supply • Instrument input/output isolation CATHODE 3 6 VO CATHODE 2 3 6 VO2 • Ground loop elimination NC 4 5 GND ANODE 2 4 5 GND SHIELD SHIELD • Pulse transformer replacement Truth Table Truth Table • Field buses (Positive Logic) (Positive Logic) LED Enable Output LED Output ON H L ON L OFF H H OFF H ON L H OFF L H ON NC L OFF NC H CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

Ordering Information HCPL-xxxx is UL Recognized with 3750 Vrms for 1 minute per UL1577 Option UL 5000 RoHS Non RoHS Surface Gull Tape Vrms/ 1 Min- IEC/EN/DIN Part number Compliant Compliant Package Mount Wing & Reel ute rating EN 60747-5-5 Quantity -000E No option 50 per tube -300E -300 X X 50 per tube -500E #500 X X X 1000 per reel -020E -020 300mil X 50 per tube HCPL-260L -320E -320 DIP-8 X X X 50 per tube -520E -520 X X X X 1000 per reel -060E #060 X 50 per tube -560E #560 X X X X 1000 per reel -000E No option 50 per tube -300E #300 X X 50 per tube -500E #500 X X X 1000 per reel -020E #020 300mil X 50 per tube HCPL-263L -320E -320 DIP-8 X X X 50 per tube -520E #520 X X X X 1000 per reel -060E -060 X 50 per tube -560E -560 X X X X 1000 per reel -000E No option X 100 per tube -500E #500 X X 1500 per reel HCPL-060L SO-8 -060E #060 X X 100 per tube -560E -560 X X X 1500 per reel -000E No option X 100 per tube -500E #500 X X 1500 per reel HCPL-063L SO-8 -060E -060 X X 100 per tube -560E -560 X X X 1500 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Combination of Option 020 and Option 060 is not available. Example 1: HCPL-260L-560E to order product of 300mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval in RoHS compliant. Example 2: HCPL-263L to order product of 300mil DIP package in tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use ‘-XXXE‘. 2

Schematic HCPL-260L/060L HCPL-263L/063L I 2+F ICC 8VCC ICC 8VCC 1 I IO 6 VO + F1 IO1 7 VO1 V F1 – V F – 2 GND 3 SHIELD 5 SHIELD IE 7 V 3 E I – O2 6 VO2 USE OF A 0.1 µF BYPASS CAPACITOR CONNECTED V BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 5). F2 + 4 IF2 GND SHIELD 5 Package Outline Drawings 8-Pin DIP Package 7.62 ± 0.25 (0.300 ± 0.010) 9.65 ± 0.25 6.35 ± 0.25 (0.380 ± 0.010) (0.250 ± 0.010) 8 7 6 5 DEVICE PART NUMBER AVAGO A NNNN Z TEST RATING CODE LEAD-FREE (cid:127) YYWW UL LOGO DATE CODE EEE P SPECIAL PROGRAM CODE LOT ID PIN 1 1 2 3 4 1.78 (0.070) MAX. 1.19 (0.047) MAX. + 0.076 5° TYP. 0.254 - 0.051 + 0.003) (0.010 - 0.002) 3.56 ± 0.13 4.70 (0.185) MAX. (0.140 ± 0.005) 0.51 (0.020) MIN. 2.92 (0.115) MIN. DIMENSIONS IN MILLIMETERS (INCHES). *MARKING CODE LETTER FOR OPTION NUMBERS 1.080 ± 0.320 0.65 (0.025) MAX. "V" = OPTION 060 (0.043 ± 0.013) OPTION NUMBERS 300 AND 500 NOT MARKED. 2.54 ± 0.25 (0.100 ± 0.010) NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. 3

8-Pin DIP Package with Gull Wing Surface Mount in Option 500 (HCPL-260L, HCPL-263L) LAND PATTERN RECOMMENDATION 9.65 ± 0.25 (0.380 ± 0.010) 1.016 (0.040) 8 7 6 5 6.350 ± 0.25 10.9 (0.430) (0.250 ± 0.010) 1 2 3 4 2.0 (0.080) 1.27 (0.050) 1.780 (0.070) 1.19 (0.047) MAX. 9.65 ± 0.25 MAX. (0.380 ± 0.010) 3.56 ± 0.13 7.62 ± 0.25 (0.140 ± 0.005) (0.300 ± 0.010) + 0.076 0.254 - 0.051 + 0.003) 1.080 ± 0.320 (0.010- 0.002) (0.043 ± 0.013) 2.54 (0.100) 0.635 ± 0.25 BSC (0.025 ± 0.010) 12° NOM. 0.635 ± 0.130 DIMENSIONS IN MILLIMETERS (INCHES). (0.025 ± 0.005) LEAD COPLANARITY = 0.10 mm (0.004 INCHES). NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. Small Outline SO-8 Package LAND PATTERN RECOMMENDATION 3.937 ± 0.127 (0.155 ± 0.005) 8 7 6 5 DEVICE PART TEST RATING CODE NNNN Z NUMBER LEAD-FREE (cid:127)YYWW DATE CODE 7.49 (0.295) EEE LOT ID PIN 1 5.994 ± 0.203 1 2 3 4 (0.236 ± 0.008) 1.9 (0.075) 0.406 ± 0.076 1.270 BSC (0.016 ± 0.003) (0.050) 0.64 (0.025) *5.080 ± 0.127 7° 0.432 45° X (0.200 ± 0.005) (0.017) 3.175 ± 0.127 (0.125 ± 0.005) 0 ~ 7° 0.228 ± 0.025 1.524 (0.009 ± 0.001) (0.060) 0.203 ± 0.102 (0.008 ± 0.004) *TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH) 0.305 5.207 ± 0.254 (0.205 ± 0.010) (0.012)MIN. DIMENSIONS IN MILLIMETERS (INCHES). Test Rating Code, Z Optional Identification Code LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX. L – Option x2x A – Avago OPTION NUMBER 500 NOT MARKED. V – Option x5x or x6x – UL Logo NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX. P – Special Program Code 4

Reflow Soldering Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. Regulatory Information The HCPL-260L/060L/263L/063L have been approved by the following organizations: UL Approval under UL 1577, Component Recognition Program, File E55361. CSA Approval under CSA Component Acceptance Notice #5, File CA 88324. IEC/EN/DIN EN 60747-5-5 Insulation and Safety Related Specifications 8-Pin DIP (300 Mil) SO-8 Parameter Symbol Value Value Units Conditions Minimum External Air L (101) 7.1 4.9 mm Measured from input terminals to output Gap (External Clearance) terminals, shortest distance through air. Minimum External Tracking L (102) 7.4 4.8 mm Measured from input terminals to output (External Creepage) terminals, shortest distance path along body. Minimum Internal Plastic 0.08 0.08 mm Through insulation distance, conductor Gap (Internal Clearance) to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. Tracking Resistance CTI 200 200 V DIN IEC 112/VDE 0303 Part 1 (Comparative Tracking Index) Isolation Group IIIa IIIa Material Group (DIN VDE 0110, 1/89, Table 1) 5

IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* Description Symbol PDIP Option 060 SO-8 Option 060 Unit Installation classification per DIN VDE 0110, Table 1 for rated mains voltage ≤ 150 Vrms I – IV I – IV for rated mains voltage ≤ 300 Vrms I – IV I – IV for rated mains voltage ≤ 600 Vrms I – III I – III Climatic Classification 40/85/21 40/85/21 Pollution Degree (DIN VDE 0110/39) 2 2 Maximum Working Insulation Voltage VIORM 630 567 Vpeak Input to Output Test Voltage, Method b* VPR 1181 1063 Vpeak VIORM x 1.875 = VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC Input to Output Test Voltage, Method a* VPR 1008 907 Vpeak VIORM x 1.6 = VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC Highest Allowable Overvoltage VIOTM 6000 6000 Vpeak (Transient Overvoltage tini = 60 sec) Safety-limiting values – maximum values allowed in the event of a failure. Case Temperature TS 175 150 °C Input Current IS, INPUT 230 150 mA Output Power PS, OUTPUT 600 600 mW Insulation Resistance at TS, VIO = 500 V RS ≥109 ≥109 W *Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section IEC/EN/DIN EN 60747-5-5, for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. Thermal Derating Curve Figures HCPL-060L/HCPL-063L HCPL-260L/HCPL-263L RENT – IS780000 PISS ( (mmAW)) RENT – IS780000 PISS ( (mmAW)) R600 R600 U U C C UT 500 UT 500 P P N N P, IS400 P, IS400 – 300 – 300 R R E E W200 W200 O O P P UT 100 UT 100 P P T T U 0 U 0 O 0 25 50 75 100 125 150 175 200 O 0 25 50 75 100 125 150 175 200 TS – CASE TEMPERATURE – °C TS – CASE TEMPERATURE – °C 6

Absolute Maximum Ratings (No Derating Required up to 85 °C) Parameter Symbol Package** Min. Max. Units Note Storage Temperature TS –55 125 °C Operating Temperature† TA –40 85 °C Average Forward Input Current IF Single 8-Pin DIP 20 mA 2 Single SO-8 Dual 8-Pin DIP 15 1, 3 Dual SO-8 Reverse Input Voltage VR 8-Pin DIP, SO-8 5 V 1 Input Power Dissipation PI 40 mW Supply Voltage (1 Minute Maximum) VCC 7 V Enable Input Voltage (Not to Exceed VE Single 8-Pin DIP VCC + 0.5 V VCC by more than 500 mV) Single SO-8 Enable Input Current IE 5 mA Output Collector Current IO 50 mA 1 Output Collector Voltage VO 7 V 1 Output Collector Power Dissipation PO Single 8-Pin DIP 85 mW Single SO-8 Dual 8-Pin DIP 60 1, 4 Dual SO-8 **Ratings apply to all devices except otherwise noted in the Package column. Recommended Operating Conditions Parameter Symbol Min. Max. Units Input Current, Low Level IFL* 0 250 µA Input Current, High Level[1] IFH** 5 15 mA Power Supply Voltage VCC 2.7 3.6 V 4.5 5.5 Low Level Enable Voltage VEL 0 0.8 V High Level Enable Voltage VEH 2.0 VCC V Operating Temperature TA –40 85 °C Fan Out (at RL = 1 kΩ)[1] N 5 TTL Loads Output Pull-up Resistor RL 330 4 k W *The off condition can also be guaranteed by ensuring that VFL ≤ 0.8 V. **The initial switching threshold is 5 mA or less. It is recommended that 6.3 mA to 10 mA be used for best performance and to permit at least a 20% LED degradation guardband. 7

Electrical Specifications Over Recommended Operating Conditions (TA = –40 °C to +85 °C , 2.7 V ≤ VCC ≤ 3.6 V), unless otherwise specified. All Typicals at VCC = 3.3 V, TA = 25 °C. All enable test conditions apply to single channel products only. See Note 5. Parameter Sym. Device Min. Typ. Max. Units Test Conditions Fig. Note High Level IOH* 4.5 50 µA VCC = 3.3 V, VE = 2.0 V, 1 1, 15 Output Current VO = 3.3 V, IF = 250 µA Input Threshold ITH 3.0 5.0 mA VCC = 3.3 V, VE = 2.0 V, 2 15 Current VO = 0.6 V, IOL (Sinking) = 13 mA Low Level VOL* 0.35 0.6 V VCC = 3.3 V, VE = 2.0 V, 3 15 Output Voltage IF = 5 mA, IOL (Sinking) = 13 mA High Level ICCH Single 4.7 7.0 mA VE = 0.5 V, IF = 0 mA Supply Current Dual 6.9 10.0 VCC = 3.3 V Low Level ICCL Single 7.0 10.0 mA VE = 0.5 V, IF = 10 mA Supply Current Dual 8.7 15.0 VCC = 3.3 V High Level IEH Single –0.5 –1.2 mA VCC = 3.3 V, VE = 2.0 V Enable Current Low Level IEL* Single –0.5 –1.2 mA VCC = 3.3 V, VE = 0.5 V Enable Current High Level VEH Single 2.0 V 15 Enable Voltage Low Level VEL Single 0.8 V Enable Voltage Input Forward VF 1.4 1.5 1.75* V TA = 25 °C, IF = 10 mA 5 1 Voltage Input Reverse BVR* 5 V IR = 10 µA 1 Breakdown Voltage Input Diode ∆VF/ –1.6 mV°C IF = 10 mA 1 Temperature ∆TA Coefficient Input CIN 60 pF f = 1 MHz, VF = 0 V 1 Capacitance *The JEDEC Registration specifies 0 °C to +70 °C. Avago specifies –40 °C to +85 °C. 8

Electrical Specifications (DC) Over recommended operating conditions (TA = -40 °C to +85 °C, 4.5 V ≤ VDD ≤ 5.5 V), unless otherwise specified. All typicals at VCC = 5 V, TA = 25 °C. Parameter Symbol Channel Min. Typ.* Max. Units Test Conditions Fig. Note High Level Output IOH 5.5 100 µA VCC = 5.5 V, 1 1,15 Current VO = 5.5 V, IFL = 250 µA Input Threshold ITH Single 2.0 5.0 mA VCC = 5.5 V, VO = 0.6 V, 2 15 Current Dual 2.5 IOL > 13 mA Low Level Output VOL 0.35 0.6 V VCC = 5.5 V, IF = 5 mA, 3 15 Voltage IOL(Sinking) = 13 mA High Level Supply ICCH Single 7.0 10.0 mA VE =0.5V, VCC = 5.5 V, Current IF = 0 mA 6.5 mA VE =VCC, VCC = 5.5 V, IF = 0 mA Dual 10.0 15.0 VCC = 5.5 V, IF = 0 mA Low Level Supply ICCL Single 9.0 13.0 mA VE =0.5 V, VCC = 5.5 V, Current IF = 10 mA 8.5 mA VE =VCC, VCC = 5.5 V, IF = 10 mA Dual 13.0 21.0 mA VCC = 5.5 V, IF = 10 mA High Level Enable IEH Single -0.7 -1.6 mA VCC = 5.5 V, VE = 2.0V Current Low Level Enable IEL Single -0.9 -1.6 mA VCC = 5.5 V, VE = 0.5V Current High Level Enable VEH Single 2.0 V 15 Voltage Low Level Enable VEL Single 0.8 V Voltage Input Forward VF 1.4 1.5 1.75 V TA = 25 °C, IF = 10 mA 5 Voltage 1.3 1.8 V IF =10 mA Input Reverse BVR 5 V IR = 10 µA 1 Breakdown Voltage Input Diode ΔVF/ΔTA -1.6 mV/°C IF = 10 mA 1 Temperature Coefficient Input Capacitance CIN 60 pF f = 1 MHz, VF = 0 V 1 9

Switching Specifications Over Recommended Operating Conditions (TA = –40 °C to +85 °C, 2.7 V ≤ VCC ≤ 3.6 V), IF = 7.5 mA, unless otherwise specified. All Typicals at TA = 25 °C, VCC = 3.3 V. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay tPLH 90 ns RL = 350 W 6, 7 1, 6, 15 Time to High Output CL = 15 pF Level Propagation Delay tPHL 75 ns RL = 350 W 1, 7, 15 Time to Low Output CL = 15 pF Level Pulse Width |tPHL – tPLH| 25 ns RL = 350 W 8 9, 15 Distortion CL = 15 pF Propagation Delay tPSK 40 ns RL = 350 W 8, 9, 15 Skew CL = 15 pF Output Rise Time tr 45 ns RL = 350 W 1, 15 (10-90%) CL = 15 pF Output Fall Time tf 20 ns RL = 350 W 1, 15 (90-10%) CL = 15 pF Propagation Delay tELH 45 ns RL = 350 W, 9 10 Time of Enable from CL = 15 pF, VEH to VEL VEL = 0 V, VEH = 3 V Propagation Delay tEHL 30 ns RL = 350 W, 9 11 Time of Enable from CL = 15 pF, VEL to VEH VEL = 0 V, VEH = 3 V 10

Switching Specifications (AC) Over recommended operating conditions TA = -40 °C to 85 °C, 4.5 V ≤ Vcc ≤ 5.5 V, IF = 7.5 mA, unless otherwise specified. All typicals at VCC = 5 V, TA = 25 °C. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time tPLH 20 48 75 ns TA = 25°C, RL = 350 W, 6,7 1,6,15 to High Output Level 100 CL = 15 pF Propagation Delay Time tPHL 25 50 75 ns TA = 25°C, RL = 350 W, 6, 7 1,7, 15 to Low Output Level 100 CL = 15 pF Pulse Width Distortion |tPHL - tPLH| 3.5 35 ns RL = 350 W, 8 9, 15 CL = 15 pF Propagation Delay Skew TPSK 40 ns RL = 350 W, 8,9, 15 CL = 15 pF Output Rise Time tr 24 ns RL = 350 W, 1,15 (10%-90%) CL = 15 pF Output Fall Time tf 10 ns RL = 350 W, 1, 15 (10%-90%) CL = 15 pF Propagation Delay tELH 30 ns RL = 350 W, CL = 15 pF, 9 10 Time of Enable from VEH to VEL VEL =0 V, VEH =3 V Propagation Delay tEHL 20 ns RL = 350W, CL = 15 pF, 9 11 Time of Enable from VEL to VEH VEL =0 V, VEH =3 V Parameter Symbol Device Min. Typ. Units Test Conditions Fig. Note Output High Level Common |CMH| HCPL-263L 15 25 kV/µs VCC = 3.3 V, IF = 0 mA, 10 12, Mode Transient Immunity HCPL-063L VO(MIN) = 2 V, RL = 350 W, 14, HCPL-260L TA = 25 °C, VCM = 1000 V 15 HCPL-060L and VCM = 10V Output Low Level Common |CML| HCPL-263L 15 25 kV/µs VCC = 3.3 V, IF = 7.5 mA, 10 13, Mode Transient Immunity HCPL-063L VO(MAX) = 0.8 V, RL = 350 W, 14, HCPL-260L TA = 25 °C, VCM = 1000 V 15 HCPL-060L and VCM = 10V Output High Level Common |CMH| HCPL-263L 10 15 kV/µs VCC = 5 V, IF = 0 mA, 10 12, Mode Transient Immunity HCPL-063L VO(MIN) = 2 V, RL = 350 W, 14, HCPL-260L TA = 25 °C, VCM = 1000 V 15 HCPL-060L Output Low Level Common |CML| HCPL-263L 10 15 kV/µs VCC = 5 V, IF = 7.5 mA, 10 13, Mode Transient Immunity HCPL-063L VO(MAX) = 0.8 V, RL = 350 14, HCPL-260L W, 15 HCPL-060L TA = 25 °C, VCM = 1000 V 11

Package Characteristics All Typicals at TA = 25 °C. Parameter Sym. Package Min. Typ. Max. Units Test Conditions Fig. Note Input-Output II-O* Single 8-Pin DIP 1 µA 45% RH, t = 5 s, 16, 17 Insulation Single SO-8 VI-O = 3 kV DC, TA = 25 °C Input-Output VISO 8-Pin DIP, SO-8 3750 Vrms RH ≤ 50%, t = 1 min, 16, 17 Momentary TA = 25 °C Withstand Voltage** Input-Output RI-O 8-Pin, SO-8 1012 W VI-O =500 Vdc 1, 16, 19 Resistance Input-Output CI-O 8-Pin DIP, SO-8 0.6 pF f = 1 MHz, TA = 25 °C 1, 16, 19 Capacitance Input-Input II-I Dual Channel 0.005 µA RH ≤ 45%, t = 5 s, 20 Insulation VI-I = 500 V Leakage Current Resistance RI-I Dual Channel 1011 W 20 (Input-Input) Capacitance CI-I Dual 8-Pin Dip 0.03 pG f = 1 MHz 20 (Input-Input) Dual SO-8 0.25 *The JEDEC Registration specifies 0 °C to +70 °C. Avago specifies –40 °C to +85 °C. **The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table (if applicable), your equip- ment level safety specification or Avago Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage." Notes: 1. Each channel. 2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 20 mA. 3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 15 mA. 4. Derate linearly above +80˚C free-air temperature at a rate of 2.7 mW/˚C for the SOIC-8 package. 5. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as illustrated in Figure 11. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm. 6. The tPLH propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the output pulse. 7. The tPHL propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the output pulse. 8. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature and specified test conditions. 9. See test circuit for measurement details. 10. The tELH enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the rising edge of the output pulse. 11. The tEHL enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the falling edge of the output pulse. 12. CMH is the maximum tolerable rate of rise on the common mode voltage to assure that the output will remain in a high logic state (i.e., Vo > 2.0 V). 13. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., Vo < 0.8 V). 14. For sinusoidal voltages, (|dVCM | / dt)max = πfCMVCM (p-p). 15. No external pull up is required for a high logic state on the enable input. If the VE pin is not used, tying VE to VCC will result in improved CMR performance. For single channel products only. See application information provided. 16. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together. 17. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 Vrms for one second (leakage detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/ EN/DIN EN 60747-5-5 Insulation Characteristics Table, if applicable. 18. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for one second (leakage detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/ EN/DIN EN 60747-5-5 Insulation Characteristics Table, if applicable. 19. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel products only. 20. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel products only. 12

Aµ15 A 15 RRENT – VVVCOE C == = 23 3..03.3 VV V* RENT – µ VVVCOE C == = 25 5..05.5 VV V* CU10 IF = 250 µA UR 10 IF = 250 µA UT * FOR SINGLE CHANNEL T C * FOR SINGLE CHANNEL P U T PRODUCTS ONLY P PRODUCTS ONLY U T O U VEL 5 EL O 5 E V GH L H LE I – HIOH0-60 -40 -20 0 20 40 60 80 100 I – HIGOH 0-60 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – °C TA – TEMPERATURE – °C Figure 1. Typical high level output current vs. temperature 8-PIN DIP, SO-8 8-PIN DIP, SO-8 I – INPUT THRESHOLD CURRENT – mATH112806402-60 VVCOC -= 4= 00 3.6.3 V V-20 RL =0 1 kΩ20RLR =L = 430 540 k ΩΩ60 80 100 I – INPUT THRESHOLD CURRENT – mATH3201456-60VVCOC = -=4 00 5.6.0 V V-20 RL0 = 1 kΩ20 RRL L= 4= 40 3 k5Ω0 Ω60 80 100 TA – TEMPERATURE – °C TA – TEMPERATURE – °C Figure 2. Typical output voltage vs. forward input current 8-PIN DIP, SO-8 8-PIN DIP, SO-8 W LEVEL OUTPUT VOLTAGE – V0000000.......5742368 VVIFCE = C= = 5 2 .3.00. 3m V V*A IO =* 1CP F3HRO AOmRND ASNUINCELTGSL EONLY W LEVEL OUTPUT VOLTAGE – V0000000.......8574236 VVIFCE = C= = 5 2 .5.00.I I5Om OV V= *A= 9 1.66 mmAA * CP FHROAORND SNUINCELTGSL EONIOLIO Y= = 1 62..48 mmAA V – LOOL0.01-60 -40 -20 0 20 40 60 80 100 V – LOOL0.0-160 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – °C TA – TEMPERATURE – °C Figure 3. Typical low level output voltage vs. temperature 13

70 70 W LEVEL OUTPUT CURRENT – mA 564000 VVVCEO CL= == 2 30.0..36 V VV* * CPI FFHR O=AOR ND5 SNU.I0NCE mLTGSLA EONLY W LEVEL OUTPUT CURRENT – mA 654000 VVVCEO CL= == 2 50.0..06 V VV* * CP FHROAORND SNUINCELTGSL EOIFNI =FL =Y 1 05 .–0 1m5A mA I – LOOL 20 I – LOOL20 -60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – °C TA – TEMPERATURE – °C Figure 4. Typical low level output current vs. temperature 8-PIN DIP, SO-8 1000 A 100 m I – F T + REN 10 V–F R CU 1.0 D AR TA = 25 °C W 0.1 R O F – 0.01 I F 0.001 1.1 1.2 1.3 1.4 1.5 1.6 V – FORWARD VOLTAGE – V F Figure 5. Typical input diode forward characteristic PULSE GEN. ZO = 50 Ω SINGLE CHANNEL 3.3 V or 5 V tf = tr = 5 ns DUAL CHANNEL 3.3 V or 5 V PZUO L=S E5 G0 EΩN. IF 1 VCC 8 IF 1 VCC 8 tf = tr = 5 ns 2 7 0B.Y1P AµSFS RL MONITOINRPINUGT 2 7 RL MOUOTNPIUTOT RVION G MONITOINRPINUGT 3 6 MOUOTNPIUTOT RVION G NODE 3 6 0B.Y1P µASFS NODE NODE RM 4 5 *CL NODE RM 4 5 CL* GND GND *C IS APPROXIMATELY 15 pF WHICH INCLUDES L PROBE AND STRAY WIRING CAPACITANCE. I = 7.50 mA F INPUT IF IF = 3.75 mA t t PHL PLH OUTPUT VO 1.5 V Figure 6. Test circuit for tPHL and tPLH 14

150 100 V = 5.0 V V = 3.3 V CC CC I = 7.5 mA I = 7.5 mA F DELAY – ns12900 F tPLH , RL = 350 Ω DELAY - ns6800 tPHL , RL = 3510 k ΩΩ tPLH , RL = 4 kΩ N N 4 kΩ O O ATI ATI AG 60 AG40 tPLH , RL = 1 kΩ P P O O t – PRP30 tPHL , RL = 350 Ω t - PRP20 tPLH , RL = 350 Ω 0 0 -60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – °C TA – TEMPERATURE – °C Figure 7. Typical propagation delay vs. temperature 50 40 V = 3.3 V – PULSE WIDTH DISTORTION – ns14320000 RL = 350 Ω IFC =C 7.5 mA D- PULSE WIDTH DISTORTION - ns3120000 RL R=L 3=5 40 kΩΩ VIFC =C = 7 .55. 0m VA PWD PW RL = 1 kΩ 0 -10 -60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – °C TA – TEMPERATURE – °C Figure 8. Typical pulse width distortion vs. temperature 15

PULSE GEN. ZO = 50 Ω tf = tr = 5 ns INPUT VE MONITORING NODE 3.3 V or 5 V 1 VCC 8 3.0 V INPUT 7.5 mA 0.1 µF VE 1.5 V IF 2 7 BYPASS RL tEHL tELH OUTPUT V 3 6 MONITORIONG OUTPUT *CL NODE VO 1.5 V GND 4 5 *C IS APPROXIMATELY 15 pF WHICH INCLUDES L PROBE AND STRAY WIRING CAPACITANCE. Figure 9. Test circuit for tEHL and tELH I F SINGLE CHANNEL DUAL CHANNEL I B F 1 VCC 8 3.3 V or 5 V A 1 VCC 8 3.3 V or 5 V B 0.1 µF RL OUTPUT VO A 2 7 BYPASS RL 2 7 MONITORING OUTPUT V VFF NODE VFF 3 6 MONITORIONG 3 6 0.1 µF BYPASS NODE GND GND 4 5 4 5 V V CM CM + – + – PULSE PULSE GENERATOR GENERATOR ZO = 50 Ω VCM (PEAK) ZO = 50 Ω V CM 0 V SWITCH AT A: I = 0 mA 5 V F C V MH O V (MIN.) O SWITCH AT B: I = 7.5 mA F V (MAX.) V O O 0.5 V C ML Figure 10. Test circuit for common mode transient immunity and typical waveforms GND BUS (BACK) V BUS (FRONT) CC NC ENABLE 0.1µF NC OUTPUT 10 mm MAX. SINGLE CHANNEL (SEE NOTE 5) DEVICE ILLUSTRATED. Figure 11. Recommended printed circuit board layout 16

SINGLE CHANNEL DEVICE 3.3 V or 5V 3.3 V or 5V V 8 CC1 V CC2 220 Ω RL I F 2 6 + D1* VF 0.1 µF BYPASS – 3 5 GND 1 GND 2 SHIELD VE 7 1 2 *DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT. DUAL CHANNEL DEVICE CHANNEL 1 SHOWN 3.3 V or 5V 3.3 V or 5 V V 8 CC1 V CC2 220 Ω RL I F 1 7 + D1* VF 0.1 µF BYPASS – 2 5 GND 1 GND 2 SHIELD 1 2 Figure 12. Recommended LVTTL interface circuit 17

Application Information Common-Mode Rejection for HCPL-260L Families: Figure 13 shows the recomm ended drive circuit for op- Also, common-mode transients can capacitively cou- timal common-mode rejection performance. Two main ple from the LED anode (or cathode) to the output-side points to note are: ground causing current to be shunted away from the LED (which can be bad if the LED is on) or conversely 1. The enable pin is tied to VCC rather than floating (this cause current to be injected into the LED (bad if the LED applies to single-channel parts only). is meant to be off). Figure 14 shows the parasitic capaci- 2. Two LED-current setting resistors are used instead of tances which exists between LED anode/cathode and one. This is to balance ILED variation during common- output ground (CLA and CLC). Also shown in Figure 14 on mode transients. the input side is an AC-equivalent circuit. If the enable pin is left floating, it is possible for common- For transients occurring when the LED is on, common- mode transients to couple to the enable pin, resulting in mode rejec tion (CMRL, since the output is in the “low” common-mode failure. This failure mechanism only oc- state) depends upon the amount of LED current drive curs when the LED is on and the output is in the Low (IF). For conditions where IF is close to the switching State. It is identified as occurring when the transient out- threshold (ITH), CMRL also depends on the extent which put voltage rises above 0.8 V. Therefore, the enable pin ILP and ILN balance each other. In other words, any condi- should be connected to either VCC or logic-level high for tion where common-mode transients cause a momen- best common-mode performance with the output low tary decrease in IF will cause common-mode failure for (CMRL). This failure mechanism is only present in single- transients which are fast enough. channel parts which have the enable function. HCPL-260L * V 1 8 V CC CC+ 0.01 µF 220 Ω 2 7 350 Ω 220 Ω 3 6 V O 74LS04 OR ANY TOTEM-POLE 4 5 GND SHIELD OUTPUT LOGIC GATE * GND1 GND2 * HIGHER CMR MAY BE OBTAINABLE BY CONNECTING PINS 1, 4 TO INPUT GROUND (GND1). Figure 13. Recommended drive circuit for High-CMR 1 8 V CC+ 1/2 RLED 0.01 µF 2 7 350 Ω I LP 1/2 RLED 3 ILN CLA 6 V O 15 pF C 4 LC 5 GND SHIELD + – V CM Figure 14. AC equivalent circuit 18

Likewise for common-mode transients which occur V CC when the LED is off (i.e. CMRH, since the output is “high”), if an imbalance between ILP and ILN results in a transient HCPL-260L IF equal to or greater than the switching threshold of the 420 Ω 1 optocoupler, the transient “signal” may cause the output (MAX) to spike below 2 V (which consti tutes a CMRH failure). 2 2N3906 By using the recommended circuit in Figure 13, good 74L504 (ANY PNP) LED (ANY CMR can be achieved. The balanced ILED-setting resistors TTL/CMOS 3 help equalize ILP and ILN to reduce the amount by which GATE) ILED is modulated from transient coupling through CLA 4 and CLC. CMR with Other Drive Circuits CMR performance with drive circuits other than that shown in Figure 13 may be enhanced by following these Figure 15. TTL interface circuit guidelines: 1. Use of drive circuits where current is shunted from the LED in the LED “off” state (as shown in Figures 15 and V CC HCPL-260L 16). This is beneficial for good CMRH. 1 R 2. Use of IFH > 3.5 mA. This is good for high CMRL. Figure 15 shows a circuit which can be used with any 2 totem-pole-output TTL/LSTTL/HCMOS logic gate. The 74HC00 (OR ANY LED buffer PNP transistor allows the circuit to be used with OPEN-COLLECTOR/ 3 logic devices which have low current-sinking capability. OPEN-DRAIN It also helps maintain the driving-gate power-supply cur- LOGIC GATE) rent at a constant level to minimize ground shifting for 4 other devices connected to the input-supply ground. When using an open-collector TTL or open-drain CMOS Figure 16. TTL open-collector/open-drain gate drive circuit logic gate, the circuit in Figure 16 may be used. When using a CMOS gate to drive the optocoupler, the circuit shown in Figure 17 may be used. The diode in parallel with the RLED speeds the turn-off of the optocoupler VCC LED. HCPL-260L 1N4148 1 2 74HC04 220 Ω (OR ANY LED TOTEM-POLE 3 OUTPUT LOGIC GATE) 4 Figure 17. CMOS gate drive circuit For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2014 Avago Technologies. All rights reserved. Obsoletes AV01-0581EN AV02-0616EN - July 11, 2014

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