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www.fairchildsemi.com FSDM0565RB TM Green Mode Fairchild Power Switch (FPS ) Features OUTPUT POWER TABLE • Internal Avalanche Rugged Sense FET • Advanced Burst-Mode operation consumes under 1 W at 230VAC ±15%(3) 85-265VAC 240VAC & 0.5W load PRODUCT Adapt- Open Adapt- Open • Precision Fixed Operating Frequency (66kHz) er(1) Frame(2) er(1) Frame(2) • Internal Start-up Circuit FSDM0565RB 60W 70W 50W 60W • Improved Pulse by Pulse Current Limiting FSDM0565RBI 60W 70W 50W 60W • Over Voltage Protection (OVP) • Over Load Protection (OLP) FSDM07652RB 70W 80W 60W 70W • Internal Thermal Shutdown Function (TSD) Table 1. Maximum Output Power • Auto-Restart Mode Notes: • Under Voltage Lock Out (UVLO) with hysteresis 1. Typical continuous power in a non-ventilated enclosed • Low Operating Current (2.5mA) adapter measured at 50°C ambient. • Built-in Soft Start 2. Maximum practical continuous power in an open frame design at 50°C ambient. Application 3. 230 VAC or 100/115 VAC with doubler. • SMPS for LCD monitor and STB • Adaptor Description Typical Circuit The FSDM0565RB is an integrated Pulse Width Modulator (PWM) and Sense FET specifically designed for high performance offline Switch Mode Power Supplies (SMPS) with minimal external components. This device is an AC IN DC integrated high voltage power switching regulator which OUT combine an avalanche rugged Sense FET with a current mode PWM control block. The PWM controller includes integrated fixed frequency oscillator, under voltage lockout, leading edge Vstr Drain blanking (LEB), optimized gate driver, internal soft start, PWM temperature compensated precise current sources for a loop compensation and self protection circuitry. Compared with Vfb Vcc Source discrete MOSFET and PWM controller solution, it can reduce total cost, component count, size and weight simultaneously increasing efficiency, productivity, and system reliability. This device is a basic platform well suited for cost effective Figure 1.Typical Flyback Application designs of flyback converters. FPSTM is a trademark of Fairchild Semiconductor Corporation. Rev.1.0.6 ©2006 Fairchild Semiconductor Corporation

FSDM0565RB Internal Block Diagram Vcc Vstr Drain 3 6 1 N.C 5 I start 0.5/0.7V + Internal Vref Bias 8V/12V Vcc good - Vcc Vref OSC Idelay IFB 2.5R PWM S Q FB 4 Gate R Q driver Soft start R LEB V SD Vcc 2 GND S Q Vovp Vcc good R Q V TSD CL Figure 2.Functional Block Diagram of FSDM0565RB 2

FSDM0565RB Pin Definitions Pin Number Pin Name Pin Function Description This pin is the high voltage power Sense FET drain. It is designed to drive the 1 Drain transformer directly. 2 GND This pin is the control ground and the Sense FET source. This pin is the positive supply voltage input. During start up, the power is sup- plied by an internal high voltage current source that is connected to the Vstr pin. 3 Vcc When Vcc reaches 12V, the internal high voltage current source is disabled and the power is supplied from the auxiliary transformer winding. This pin is internally connected to the inverting input of the PWM comparator. The collector of an opto-coupler is typically tied to this pin. For stable operation, 4 Vfb a capacitor should be placed between this pin and GND. If the voltage of this pin reaches 6.0V, the over load protection is activated resulting in shutdown of the FPSTM. 5 N.C - This pin is connected directly to the high voltage DC link. At startup, the internal high voltage current source supplies internal bias and charges the external ca- 6 Vstr pacitor that is connected to the Vcc pin. Once Vcc reaches 12V, the internal cur- rent source is disabled. Pin Configuration TO-220F-6L 6.Vstr 5.N.C. 4.Vfb 3.Vcc 2.GND 1.Drain I2-PAK-6L 6.Vstr 5.N.C. 4.Vfb 3.Vcc 2.GND 1.Drain Figure 3.Pin Configuration (Top View) 3

FSDM0565RB Absolute Maximum Ratings (Ta=25°C, unless otherwise specified) Parameter Symbol Value Unit Drain-source voltage VDSS 650 V Vstr Max Voltage VSTR 650 V Pulsed Drain current (Tc=25°C)(1) IDM 11 ADC Continuous Drain Current(Tc=25°C) 2.8 A ID Continuous Drain Current(Tc=100°C) 1.7 A Single pulsed avalanche energy (2) EAS 190 mJ Single pulsed avalanche current (3) IAS - A Supply voltage VCC 20 V Input voltage range VFB -0.3 to VCC V 45 (TO-220-6L) Total power dissipation(Tc=25°C) PD(Watt H/S) W 75 (I2-PAK-6L) Operating junction temperature Tj Internally limited °C Operating ambient temperature TA -25 to +85 °C Storage temperature range TSTG -55 to +150 °C ESD Capability, HBM Model (All pins - 2.0 kV excepts for Vstr and Vfb) (GND-Vstr/Vfb=1.5kV) ESD Capability, Machine Model (All pins - 300 V excepts for Vstr and Vfb) (GND-Vstr/Vfb=225V) Notes: 1. Repetitive rating: Pulse width limited by maximum junction temperature 2. L=14mH, starting Tj=25°C 3. L=13uH, starting Tj=25°C Thermal Impedance Parameter Symbol Package Value Unit TO-220F-6L 49.90 Junction-to-Ambient Thermal θJA(1) °C/W I2-PAK-6L 30 TO-220F-6L 2.78 Junction-to-Case Thermal θJC(2) °C/W I2-PAK-6L 1.67 Notes: 1. Free standing with no heat-sink under natural convection. 2. Infinite cooling condition - Refer to the SEMI G30-88. 4

FSDM0565RB Electrical Characteristics (Ta = 25°C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Sense FET SECTION Drain source breakdown voltage BVDSS VGS = 0V, ID = 250μA 650 - - V VDS = 650V, VGS = 0V - - 500 μA Zero gate voltage drain current IDSS VDS= 520V - - 500 μA VGS = 0V, TC = 125°C Static drain source on resistance (1) RDS(ON) VGS = 10V, ID = 2.5A - 1.76 2.2 Ω VGS = 0V, VDS = 25V, Output capacitance COSS - 78 - pF f = 1MHz Turn on delay time TD(ON) VDD= 325V, ID= 5A - 22 - (MOSFET switching Rise time TR time is essentially - 52 - ns independent of Turn off delay time TD(OFF) - 95 - operating temperature) Fall time TF - 50 - CONTROL SECTION Initial frequency FOSC VFB = 3V 60 66 72 kHz Voltage stability FSTABLE 13V ≤ Vcc ≤ 18V 0 1 3 % Temperature stability (2) ΔFOSC -25°C ≤ Ta ≤ 85°C 0 ±5 ±10 % Maximum duty cycle DMAX - 77 82 87 % Minimum duty cycle DMIN - - - 0 % Start threshold voltage VSTART VFB=GND 11 12 13 V Stop threshold voltage VSTOP VFB=GND 7 8 9 V Feedback source current IFB VFB=GND 0.7 0.9 1.1 mA Soft-start time TS Vfb=3 - 10 15 ms Leading Edge Blanking time TLEB - - 250 - ns BURST MODE SECTION VBURH Vcc=14V - 0.7 - V Burst Mode Voltages (2) VBURL Vcc=14V - 0.5 - V PROTECTION SECTION Peak current limit (4) IOVER VFB=5V, VCC=14V 2.0 2.25 2.5 A Over voltage protection VOVP - 18 19 20 V Thermal shutdown temperature (2) TSD 130 145 160 °C Shutdown feedback voltage VSD VFB ≥ 5.5V 5.5 6.0 6.5 V Shutdown delay current IDELAY VFB=5V 2.8 3.5 4.2 μA 5

FSDM0565RB TOTAL DEVICE SECTION IOP VFB=GND, VCC=14V Operating supply current (5) IOP(MIN) VFB=GND, VCC=10V - 2.5 5 mA IOP(MAX) VFB=GND, VCC=18V Notes: 1. Pulse test : Pulse width ≤ 300μS, duty ≤ 2% 2. These parameters, although guaranteed at the design, are not tested in mass production. 3. These parameters, although guaranteed, are tested in EDS(wafer test) process. 4. These parameters indicate the inductor current. 5. This parameter is the current flowing into the control IC. 6

FSDM0565RB Comparison Between FS6M07652RTC and FSDM0565RB Function FS6M07652RTC FSDM0565RB FSDM0565RB Advantages Soft-Start Adjustable soft-start Internal soft-start with • Gradually increasing current limit time using an typically 10ms (fixed) during soft-start further reduces peak external capacitor current and voltage component stresses • Eliminates external components used for soft-start in most applications • Reduces or eliminates output overshoot Burst Mode Operation • Built into controller • Built into controller • Improve light load efficiency • Output voltage • Output voltage fixed • Reduces no-load consumption drops to around half 7

FSDM0565RB Typical Performance Characteristics (These Characteristic Graphs are Normalized at Ta= 25°C) 1.2 1.2 1.0 1.0 e ng Current(Iop) 00..68 hold Voltagstart) 00..68 erati 0.4 hers(V 0.4 p T O 0.2 Start 0.2 0.0 0.0 -25 0 25 50 75 100 125 150 -25 0 25 50 75 100 125 150 Junction Temperature(℃) Junction Temperature(℃) Operating Current vs. Temp Start Threshold Voltage vs. Temp 1.2 1.2 1.0 1.0 e g y olta 0.8 enc 0.8 d Vp) equc) eshol(Vsto 0.6 ng Fr(Fos 0.6 hr 0.4 ati 0.4 p T per Sto 0.2 O 0.2 0.0 0.0 -25 0 25 50 75 100 125 150 -25 0 25 50 75 100 125 150 Junction Temperature(℃) Junction Temperature(℃) Stop Threshold Voltage vs. Temp Operating Freqency vs. Temp 1.2 1.2 1.0 1.0 e Cycl 0.8 ent 0.8 um Duty (Dmax) 0.6 urce Curr(Ifb) 0.6 axim 0.4 B So 0.4 M F 0.2 0.2 0.0 0.0 -25 0 25 50 75 100 125 150 -25 0 25 50 75 100 125 150 Junction Temperature(℃) Junction Temperature(℃) Maximum Duty vs. Temp Feedback Source Current vs. Temp 8

FSDM0565RB Typical Performance Characteristics (Continued) (These Characteristic Graphs are Normalized at Ta= 25°C) 1.2 1.2 1.0 1.0 e nt g e olta 0.8 Curr 0.8 wn FB V(Vsd) 0.6 n Delay (Idelay) 0.6 o 0.4 w 0.4 d o ut d Sh 0.2 hut 0.2 S 0.0 0.0 -25 0 25 50 75 100 125 150 -25 0 25 50 75 100 125 150 Junction Temperature(℃) Junction Temperature(℃) ShutDown Feedback Voltage vs. Temp ShutDown Delay Current vs. Temp 1.2 1.2 e on 1.0 oltag 1.0 ecti 0.8 e V 0.8 oltage Prot(Vovp) 00..46 Mode Enabl(Vfbe) 00..46 V Over 0.2 Burst 0.2 B 0.0 F 0.0 -25 0 25 50 75 100 125 150 -25 0 25 50 75 100 125 150 Junction Temperature(℃) Junction Temperature(℃) Over Voltage Protection vs. Temp Burst Mode Enable Voltage vs. Temp 1.2 1.2 ge n) olta 1.0 ctio 1.0 V e Mode Disable (Vfbd) 000...468 nt Limit(Self prot(Iover) 000...468 FB Burst 00..02 Peak Curre 00..02 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 Junction Temperature(℃) Junction Temperature(℃) Burst Mode Disable Voltage vs. Temp Current Limit vs. Temp 9

FSDM0565RB Typical Performance Characteristics (Continued) (These Characteristic Graphs are Normalized at Ta= 25°C) 1.2 1.0 ℃) e5 0.8 m2 art Tied to 0.6 oft Stmaliz 0.4 Sor N ( 0.2 0.0 -50 -25 0 25 50 75 100 125 Junction Temperature(℃) Soft Start Time vs. Temp 10

FSDM0565RB Functional Description 2.1 Pulse-by-pulse current limit: Because current mode 1. Startup : In previous generations of Fairchild Power control is employed, the peak current through the Sense FET Switches (FPSTM) the Vcc pin had an external start-up is limited by the inverting input of PWM comparator (Vfb*) resistor to the DC input voltage line. In this generation the as shown in Figure 5. Assuming that the 0.9mA current startup resistor is replaced by an internal high voltage current source flows only through the internal resistor (2.5R +R= 2.8 source. At startup, an internal high voltage current source kΩ), the cathode voltage of diode D2 is about 2.5V. Since D1 supplies the internal bias and charges the external capacitor is blocked when the feedback voltage (Vfb) exceeds 2.5V, (Cvcc) that is connected to the Vcc pin as illustrated in the maximum voltage of the cathode of D2 is clamped at this Figure 4. When Vcc reaches 12V, the FSDM0565RB begins voltage, thus clamping Vfb*. Therefore, the peak value of switching and the internal high voltage current source is the current through the Sense FET is limited. disabled. Then, the FSDM0565RB continues its normal switching operation and the power is supplied from the auxiliary transformer winding unless Vcc goes below the stop voltage of 8V. 2.2 Leading edge blanking (LEB) : At the instant the internal Sense FET is turned on, there usually exists a high current spike through the Sense FET, caused by primary-side capacitance and secondary-side rectifier reverse recovery. Excessive voltage across the Rsense resistor would lead to V incorrect feedback operation in the current mode PWM DC control. To counter this effect, the FSDM0565RB employs a C leading edge blanking (LEB) circuit. This circuit inhibits the Vcc PWM comparator for a short time (TLEB) after the Sense FET is turned on. Vcc Vstr 3 6 Vcc Vref I start Idelay IFB Vref Vo Vfb SenseFET 4 OSC 8V/12V Vcc good H11A817A D1 D2 CB 2.5R + Gate Internal Vfb* R driver Bias KA431 - OLP R Figure 4.Internal startup circuit VSD sense Figure 5.Pulse width modulation (PWM) circuit 3. Protection Circuit : The FSDM0565RB has several self 2. Feedback Control : FSDM0565RB employs current protective functions such as over load protection (OLP), over mode control, as shown in Figure 5. An opto-coupler (such voltage protection (OVP) and thermal shutdown (TSD). as the H11A817A) and shunt regulator (such as the KA431) Because these protection circuits are fully integrated into the are typically used to implement the feedback network. IC without external components, the reliability can be Comparing the feedback voltage with the voltage across the improved without increasing cost. Once the fault condition Rsense resistor plus an offset voltage makes it possible to occurs, switching is terminated and the Sense FET remains control the switching duty cycle. When the reference pin off. This causes Vcc to fall. When Vcc reaches the UVLO voltage of the KA431 exceeds the internal reference voltage stop voltage, 8V, the protection is reset and the internal high of 2.5V, the H11A817A LED current increases, thus pulling voltage current source charges the Vcc capacitor via the Vstr down the feedback voltage and reducing the duty cycle. This pin. When Vcc reaches the UVLO start voltage,12V, the event typically happens when the input voltage is increased FSDM0565RB resumes its normal operation. In this manner, or the output load is decreased. the auto-restart can alternately enable and disable the switching of the power Sense FET until the fault condition is eliminated (see Figure 6). 11

FSDM0565RB Fault V FB occurs Fault Vds Power removed Over load protection on 6.0V 2.5V Vcc T = Cfb*(6.0-2.5)/I 12 delay 12V T1 T2 t 8V Figure 7.Over load protection t 3.2 Over voltage Protection (OVP) : If the secondary side Normal Fault Normal feedback circuit were to malfunction or a solder defect operation situation operation caused an open in the feedback path, the current through the opto-coupler transistor becomes almost zero. Then, Vfb Figure 6.Auto restart operation climbs up in a similar manner to the over load situation, forcing the preset maximum current to be supplied to the SMPS until the over load protection is activated. Because 3.1 Over Load Protection (OLP) : Overload is defined as more energy than required is provided to the output, the the load current exceeding a pre-set level due to an output voltage may exceed the rated voltage before the over unexpected event. In this situation, the protection circuit load protection is activated, resulting in the breakdown of the should be activated in order to protect the SMPS. However, devices in the secondary side. In order to prevent this even when the SMPS is in the normal operation, the over situation, an over voltage protection (OVP) circuit is load protection circuit can be activated during the load employed. In general, Vcc is proportional to the output transition. In order to avoid this undesired operation, the over voltage and the FSDM0565RB uses Vcc instead of directly load protection circuit is designed to be activated after a monitoring the output voltage. If VCC exceeds 19V, an OVP specified time to determine whether it is a transient situation circuit is activated resulting in the termination of the or an overload situation. Because of the pulse-by-pulse switching operation. In order to avoid undesired activation of current limit capability, the maximum peak current through OVP during normal operation, Vcc should be designed to be the Sense FET is limited, and therefore the maximum input below 19V. power is restricted with a given input voltage. If the output consumes beyond this maximum power, the output voltage (Vo) decreases below the set voltage. This reduces the current through the opto-coupler LED, which also reduces 3.3 Thermal Shutdown (TSD) : The Sense FET and the the opto-coupler transistor current, thus increasing the control IC are built in one package. This makes it easy for feedback voltage (Vfb). If Vfb exceeds 2.5V, D1 is blocked the control IC to detect the heat generation from the Sense and the 3.5uA current source starts to charge CB slowly up to FET. When the temperature exceeds approximately 150°C, Vcc. In this condition, Vfb continues increasing until it the thermal shutdown is activated. reaches 6V, when the switching operation is terminated as shown in Figure 7. The delay time for shutdown is the time 4. Soft Start : The FSDM0565RB has an internal soft start required to charge CB from 2.5V to 6.0V with 3.5uA. In circuit that increases PWM comparator inverting input general, a 10 ~ 50 ms delay time is typical for most voltage together with the Sense FET current slowly after it applications. starts up. The typical soft start time is 10msec, The pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors is progressively increased with the intention of smoothly establishing the required output voltage. It also helps to prevent transformer saturation and reduce the stress on the secondary diode during startup. 12

FSDM0565RB 5. Burst operation : In order to minimize power dissipation in standby mode, the FSDM0565RB enters burst mode operation. As the load decreases, the feedback voltage decreases. As shown in Figure 8, the device automatically enters burst mode when the feedback voltage drops below VBURL(500mV). At this point switching stops and the output voltages start to drop at a rate dependent on standby current load. This causes the feedback voltage to rise. Once it passes VBURH(700mV) switching resumes. The feedback voltage then falls and the process repeats. Burst mode operation alternately enables and disables switching of the power Sense FET thereby reducing switching loss in Standby mode. Vo Voset V FB 0.7V 0.5V Ids Vds time Switching Switching T1 disabled T2 T3 disabled T4 Figure 8.Waveforms of burst operation 13

FSDM0565RB Typical application circuit Application Output power Input voltage Output voltage (Max current) Universal input 5V (2.0A) LCD Monitor 40W (85-265Vac) 12V (2.5A) Features • High efficiency (>81% at 85Vac input) • Low zero load power consumption (<300mW at 240Vac input) • Low standby mode power consumption (<800mW at 240Vac input and 0.3W load) • Low component count • Enhanced system reliability through various protection functions • Internal soft-start (10ms) Key Design Notes • Resistors R102 and R105 are employed to prevent start-up at low input voltage. After startup, there is no power loss in these resistors since the startup pin is internally disconnected after startup. • The delay time for over load protection is designed to be about 50ms with C106 of 47nF. If a faster triggering of OLP is required, C106 can be reduced to 10nF. • Zener diode ZD102 is used for a safety test such as UL. When the drain pin and feedback pin are shorted, the zener diode fails and remains short, which causes the fuse (F1) blown and prevents explosion of the opto-coupler (IC301). This zener diode also increases the immunity against line surge. 1. Schematic T1 D202 L201 EER3016 MBRF10100 12V, 2.5A 1 10 C201 C202 1000uF 1000uF C103 R301k0Ω2 5R26W1k0Ω3 2C.121kn0V4F D101 2 8 25V 25V 100uF UF 4007 400V 3 BD101 2 R105 2KBP06M3N257 40kΩ IC1 FSDM0565RB 1 3 6Vstr Drain1 227C25410Vn0A2FC Z1D01V02 C45710n0VF6 54VNfCbGND2VccZ2D321V01 C25210u0VF5TVDR10120G R51Ω04 4 76MBD1R0C21F00200110Vu034F5 L202 10C102000Vu4F 5V, 2A 5 C301 LF101 4.7nF 23mH R201 1kΩ R101 R204 560kΩ 5.6kΩ 1W 1R.22k0Ω2 1R22k0Ω3 C472n0F5 IC301 5RDT-19 2 72C521V00nA1FC F25FU01SVE H11A817A KICA240311 5R.62k0Ω5 2A 14

FSDM0565RB 2. Transformer Schematic Diagram EER3016 1 10 N/2 N p 12V 2 9 N/2 p 3 8 4 7 N 5V N 5 6 a 3.Winding Specification No Pin (s→f) Wire Turns Winding Method Na 4 → 5 0.2φ × 1 8 Center Winding Insulation: Polyester Tape t = 0.050mm, 2Layers Np/2 2 → 1 0.4φ × 1 18 Solenoid Winding Insulation: Polyester Tape t = 0.050mm, 2Layers N12V 10 → 8 0.3φ × 3 7 Center Winding Insulation: Polyester Tape t = 0.050mm, 2Layers N5V 7 → 6 0.3φ × 3 3 Center Winding Insulation: Polyester Tape t = 0.050mm, 2Layers Np/2 3 → 2 0.4φ × 1 18 Solenoid Winding Outer Insulation: Polyester Tape t = 0.050mm, 2Layers 4.Electrical Characteristics Pin Specification Remarks Inductance 1 - 3 520uH ± 10% 100kHz, 1V Leakage Inductance 1 - 3 10uH Max 2nd all short 5. Core & Bobbin Core : EER 3016 Bobbin : EER3016 Ae(mm2) : 96 15

FSDM0565RB 6.Demo Circuit Part List Part Value Note Part Value Note Fuse C301 4.7nF Polyester Film Cap. F101 2A/250V NTC Inductor RT101 5D-9 L201 5uH Wire 1.2mm Resistor L202 5uH Wire 1.2mm R101 560K 1W R102 30K 1/4W R103 56K 2W R104 5 1/4W Diode R105 40K 1/4W D101 UF4007 R201 1K 1/4W D102 TVR10G R202 1.2K 1/4W D201 MBRF1045 R203 12K 1/4W D202 MBRF10100 R204 5.6K 1/4W ZD101 Zener Diode 22V R205 5.6K 1/4W ZD102 Zener Diode 10V Bridge Diode BD101 2KBP06M 3N257 Bridge Diode Capacitor C101 220nF/275VAC Box Capacitor Line Filter C102 220nF/275VAC Box Capacitor LF101 23mH Wire 0.4mm C103 100uF/400V Electrolytic Capacitor IC C104 2.2nF/1kV Ceramic Capacitor IC101 FSDM0565RB FPSTM(5A,650V) C105 22uF/50V Electrolytic Capacitor IC201 KA431(TL431) Voltage reference C106 47nF/50V Ceramic Capacitor IC301 H11A817A Opto-coupler C201 1000uF/25V Electrolytic Capacitor C202 1000uF/25V Electrolytic Capacitor C203 1000uF/10V Electrolytic Capacitor C204 1000uF/10V Electrolytic Capacitor C205 47nF/50V Ceramic Capacitor 16

FSDM0565RB 7. Layout Figure 9.Layout Considerations for FSDM0565RB Figure 10.Layout Considerations for FSDM0565RB 17

FSDM0565RB Package Dimensions TO-220F-6L(Forming) 18

FSDM0565RB Package Dimensions (Continued) I2-PAK-6L(Forming) 19

FSDM0565RB Ordering Information Product Number Package Marking Code BVdss Rds(on)Max. FSDM0565RBWDTU TO-220F-6L(Forming) DM0565R 650V 2.2 Ω FSDM0565RBIWDTU I2-PAK-6L (Forming) DM0565R 650V 2.2 Ω WDTU : Forming Type DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be or (b) support or sustain life, and (c) whose failure to reasonably expected to cause the failure of the life support perform when properly used in accordance with device or system, or to affect its safety or effectiveness. instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com 1/9/06 0.0m 001 © 2006 Fairchild Semiconductor Corporation

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