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F D M F 6 April 2013 7 0 7 C - E x t FDMF6707C - Extra-Small, High-Performance, High- ra - S Frequency DrMOS Module m a l l H Benefits Description i g h  Ultra-Compact 6x6mm PQFN, 72% Space-Saving The XS™ DrMOS family is Fairchild’s next-generation, -P Compared to Conventional Discrete Solutions fully optimized, integrated MOSFET plus driver power e r  Fully Optimized System Efficiency stage solution for high-current, high-frequency, fo  Clean Switching Waveforms with Minimal Ringing synchronous buck DC-DC applications. The FDMF6707C rm integrates a driver IC, two power MOSFETs, and a  High-Current Handling bootstrap Schottky diode into a thermally enhanced, an ultra-compact 6x6 mm PQFN package. c Features e With an integrated approach, the complete switching , H  Over 93% Peak-Efficiency power stage is optimized for driver and MOSFET i g dynamic performance, system inductance, and power  High-Current Handling of 50 A h MOSFET R . XS™ DrMOS uses Fairchild's high- - DS(ON) F  High-Performance PQFN Copper-Clip Package performance PowerTrench® MOSFET technology, r e  3-State 5.0 V PWM Input Driver which dramatically reduces switch ringing, eliminating q the snubber circuit in most buck converter applications. u  Skip-Mode SMOD# (Low-Side Gate Turn Off) Input e n A new driver IC with reduced dead times and  Thermal Warning Flag for Over-Temperature propagation delays further enhances performance. A cy Condition thermal warning function indicates potential over- D  Driver Output Disable Function (DISB# Pin) temperature situations. FDMF6707C also incorporates rM  Internal Pull-Up and Pull-Down for SMOD# and features such as Skip Mode (SMOD) for improved light- O load efficiency, along with a three-state 5 V PWM input S DISB# Inputs, Respectively for compatibility with a wide range of PWM controllers. M  Fairchild PowerTrench® Technology MOSFETs for o Applications Clean Voltage Waveforms and Reduced Ringing d u  Fairchild SyncFET™ (Integrated Schottky Diode)  High-Performance Gaming Motherboards le Technology in the Low-Side MOSFET  Compact Blade Servers, V-Core and Non-V-Core  Integrated Bootstrap Schottky Diode DC-DC Converters  Adaptive Gate Drive Timing for Shoot-Through  Desktop Computers, V-Core and Non-V-Core Protection DC-DC Converters  Under-Voltage Lockout (UVLO)  Workstations  Optimized for Switching Frequencies up to 1MHz  High-Current DC-DC Point-of-Load (POL)  Low-Profile SMD Package Converters  Fairchild Green Packaging and RoHS Compliance  Networking and Telecom Microprocessor Voltage Regulators  Based on the Intel® 4.0 DrMOS Standard  Small Form-Factor Voltage Regulator Modules Ordering Information Part Number Current Rating Package Top Mark FDMF6707C 50 A 40-Lead, Clipbond PQFN DrMOS, 6.0mm x 6.0 mm Package FDMF6707C © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6707C • Rev. 1.0.2

F D Typical Application Circuit M F 6 7 0 7 C - E x t r a - S m a l l H i g h - P e r f o r m a n c e , H i g h - Figure 1. Typical Application Circuit F r e DrMOS Block Diagram q u e n VDRV BOOT VIN c y VCIN UVLO Q1 D HS Power r DBoot MOSFET M O S M DISB# GH GH o Logic Level Shift d u 10µA 30kΩ le V PHASE CIN RUP_PWM Dead-Time In put Control VSWH PWM 3-State Logic RDN_PWM VDRV GL GL Logic THWN# VCIN 30kΩ Q2 Temp. LS Power MOSFET Sense 10µA CGND SMOD# PGND Figure 2. DrMOS Block Diagram © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6707C • Rev. 1.0.2 2

F Pin Configuration D M F 6 7 0 7 C - E x t r a - S m a l l H i g h - P e r f o r m a n c e , H i g h - F Figure 3. Bottom View Figure 4. Top View r e q Pin Definitions u e n Pin # Name Description c y When SMOD#=HIGH, the low-side driver is the inverse of PWM input. When SMOD#=LOW, D r 1 SMOD# the low-side driver is disabled. This pin has a 10 µA internal pull-up current source. Do not add M a noise filter capacitor. O S 2 VCIN IC bias supply. Minimum 1 µF ceramic capacitor is recommended from this pin to CGND. M Power for gate driver. Minimum 1 µF ceramic capacitor is recommended, connected as close o 3 VDRV as possible from this pin to CGND. d u Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a le 4 BOOT bootstrap capacitor from this pin to PHASE. 5, 37, 41 CGND IC ground. Ground return for driver IC. 6 GH For manufacturing test only. This pin must float; must not be connected to any pin. 7 PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin. No connect. The pin is not electrically connected internally, but can be connected to VIN 8 NC for convenience. 9 - 14, 42 VIN Power input. Output stage supply voltage. 15, 29 - Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point VSWH 35, 43 for the adaptive shoot-through protection. 16 – 28 PGND Power ground. Output stage ground. Source pin of the low-side MOSFET. 36 GL For manufacturing test only. This pin must float; must not be connected to any pin. Thermal warning flag, open collector output. When temperature exceeds the trip limit, the 38 THWN# output is pulled LOW. THWN# does not disable the module. Output disable. When LOW, this pin disables the power MOSFET switching (GH and GL are 39 DISB# held LOW). This pin has a 10µA internal pull-down current source. Do not add a noise filter capacitor. 40 PWM PWM signal input. This pin accepts a three-state 5V PWM signal from the controller. © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6707C • Rev. 1.0.2 3

F D Absolute Maximum Ratings M F Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be 6 7 operable above the recommended operating conditions and stressing the parts to these levels is not recommended. 0 In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. 7 C The absolute maximum ratings are stress ratings only. - E Symbol Parameter Min. Max. Unit x t r VCIN Supply Voltage Referenced to CGND -0.3 6.0 V a - V Drive Voltage Referenced to CGND -0.3 6.0 V S DRV m VDISB# Output Disable Referenced to CGND -0.3 6.0 V a l VPWM PWM Signal Input Referenced to CGND -0.3 6.0 V l H VSMOD# Skip Mode Input Referenced to CGND -0.3 6.0 V ig h VGL Low Gate Manufacturing Test Pin Referenced to CGND -0.3 6.0 V -P V Thermal Warning Flag Referenced to CGND -0.3 6.0 V e THWN# r f V Power Input Referenced to PGND, CGND -0.3 25.0 V o IN r Referenced to VSWH, PHASE -0.3 6.0 V m VBOOT Bootstrap Supply a Referenced to CGND -0.3 25.0 V n c Referenced to VSWH, PHASE -0.3 6.0 V e VGH High Gate Manufacturing Test Pin Referenced to CGND -0.3 25.0 V , H i g V PHASE Referenced to CGND -0.3 25.0 V PHS h - Referenced to PGND, CGND (DC Only) -0.3 25.0 V F VSWH Switch Node Input Referenced to PGND, <20 ns -8.0 25.0 V re q V Bootstrap Supply Referenced to VDRV 22 V u BOOT e I THWN# Sink Current -0.1 7.0 mA n THWN# c f =300 kHz, V =12 V, V =1 V 50 y I Output Current(1) SW IN O A D O(AV) fSW=1 MHz, VIN=12 V, VO=1 V 45 rM θJPCB Junction-to-PCB Thermal Resistance 3.5 °C/W O S T Ambient Temperature Range -40 +125 °C A M T Maximum Junction Temperature +150 °C J o d T Storage Temperature Range -55 +150 °C STG u l Human Body Model, JESD22-A114 2000 e ESD Electrostatic Discharge Protection V Charged Device Model, JESD22-C101 1000 Note: 1. I is rated using Fairchild’s DrMOS evaluation board, T = 25°C, natural convection cooling. This rating is limited O(AV) A by the peak DrMOS temperature, T = 150°C, and varies depending on operating conditions and PCB layout. This J rating can be changed with different application settings. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Typ. Max. Unit V Control Circuit Supply Voltage 4.5 5.0 5.5 V CIN V Gate Drive Circuit Supply Voltage 4.5 5.0 5.5 V DRV V Output Stage Supply Voltage 3.0 12.0 15.0(2) V IN Note: 2. Operating at high VIN can create excessive AC overshoots on the VSWH-to-GND and BOOT-to-GND nodes during MOSFET switching transients. For reliable DrMOS operation, VSWH-to-GND and BOOT-to-GND must remain at or below the Absolute Maximum Ratings shown in the table above. Refer to the “Application Information” and “PCB Layout Guidelines” sections of this datasheet for additional information. © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6707C • Rev. 1.0.2 4

F D Electrical Characteristics M F Typical values are V = 12 V, V = 5 V, V = 5 V, and T = +25°C unless otherwise noted. 6 IN CIN DRV A 7 0 Symbol Parameter Condition Min. Typ. Max. Unit 7 C Basic Operation - E I Quiescent Current I =I +I , PWM=LOW or HIGH or Float 2 mA x Q Q VCIN VDRV t r UVLO UVLO Threshold VCIN Rising 2.9 3.1 3.3 V a - S UVLO UVLO Hysteresis 0.4 V _Hyst m PWM Input (V = V = 5 V ±10%) a CIN DRV l l RUP_PWM Pull-Up Impedance 10 kΩ H i R Pull-Down Impedance 10 kΩ g DN_PWM h VIH_PWM PWM High Level Voltage 3.04 3.55 4.05 V -P e VTRI_HI 3-State Upper Threshold 2.95 3.45 3.94 V rf o VTRI_LO 3-State Lower Threshold 0.98 1.25 1.52 V r m V PWM Low Level Voltage 0.84 1.15 1.42 V IL_PWM a n tD_HOLD-OFF 3-State Shut-off Time 160 200 ns c e VHiZ_PWM 3-State Open Voltage 2.2 2.5 2.8 V , H PWM Input (VCIN = VDRV = 5 V ±5%) ig R Pull-Up Impedance 10 kΩ h UP_PWM - F RDN_PWM Pull-Down Impedance 10 kΩ re V PWM High Level Voltage 3.22 3.55 3.87 V q IH_PWM u V 3-State Upper Threshold 3.13 3.45 3.77 V e TRI_HI n c V 3-State Lower Threshold 1.04 1.25 1.46 V TRI_LO y V PWM Low Level Voltage 0.90 1.15 1.36 V D IL_PWM r M t 3-State Shut-Off Time 160 200 ns D_HOLD-OFF O VHiZ_PWM 3-State Open Voltage 2.3 2.5 2.7 V S DISB# Input M o V High-Level Input Voltage 2 V d IH_DISB u VIL_DISB Low-Level Input Voltage 0.8 V le I Pull-Down Current 10 µA PLD PWM=GND, Delay Between DISB# from t Propagation Delay 25 ns PD_DISBL HIGH to LOW to GL from HIGH to LOW PWM=GND, Delay Between DISB# from t Propagation Delay 25 ns PD_DISBH LOW to HIGH to GL from LOW to HIGH SMOD# Input V High-Level Input Voltage 2 V IH_SMOD V Low-Level Input Voltage 0.8 V IL_SMOD I Pull-Up Current 10 µA PLU PWM=GND, Delay Between SMOD# from t Propagation Delay 10 ns PD_SLGLL HIGH to LOW to GL from HIGH to LOW PWM=GND, Delay Between SMOD# from t Propagation Delay 10 ns PD_SHGLH LOW to HIGH to GL from LOW to HIGH Continued on the following page… © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6707C • Rev. 1.0.2 5

F D Electrical Characteristics (Continued) M F Typical values are V = 12 V, V = 5 V, V = 5 V, and T = +25°C unless otherwise noted. 6 IN CIN DRV A 7 0 Symbol Parameter Condition Min. Typ. Max. Unit 7 C Thermal Warning Flag - E T Activation Temperature 150 °C x ACT t r T Reset Temperature 135 °C a RST - S RTHWN Pull-Down Resistance IPLD=5 mA 30 Ω m 250 ns Timeout Circuit a l l SW=0V, Delay Between GH from HIGH to H tD_TIMEOUT Timeout Delay LOW and GL from LOW to HIGH 250 ns ig h High-Side Driver - P e R Output Impedance, Sourcing Source Current=100 mA 1 Ω SOURCE_GH r f o R Output Impedance, Sinking Sink Current=100 mA 0.8 Ω SINK_GH r m t Rise Time GH=10% to 90%, C =1.1 nF 6 ns R_GH LOAD a n t Fall Time GH=90% to 10%, C =1.1 nF 5 ns F_GH LOAD c e GL going LOW to GH going HIGH, , t LS to HS Deadband Time 10 ns D_DEADON 1 V GL to 10 % GH H i g t PWM LOW Propagation PWM going LOW to GH going LOW, 16 30 ns h PD_PLGHL Delay V to 90% GH - IL_PWM F r PWM HIGH Propagation PWM going HIGH to GH going HIGH, e tPD_PHGHH Delay (SMOD# Held LOW) V to 10% GH (SMOD#=LOW) 30 ns q IH_PWM u e Exiting 3-State Propagation PWM (from 3-State) going HIGH to GH t 30 ns n PD_TSGHH Delay going HIGH, V to 10% GH c IH_PWM y Low-Side Driver D r RSOURCE_GL Output Impedance, Sourcing Source Current=100 mA 1 Ω M O R Output Impedance, Sinking Sink Current=100 mA 0.5 Ω SINK_GL S tR_GL Rise Time GL=10% to 90%, CLOAD=5.9 nF 20 ns M o t Fall Time GL=90% to 10%, C =5.9 nF 13 ns F_GL LOAD d u SW going LOW to GL going HIGH, tD_DEADOFF HS to LS Deadband Time 2.2 V SW to 10% GL 12 ns le PWM-HIGH Propagation PWM going HIGH to GL going LOW, t 9 25 ns PD_PHGLL Delay V to 90% GL IH_PWM Exiting 3-State Propagation PWM (from 3-State) going LOW to GL t 20 ns PD_TSGLH Delay going HIGH, V to 10% GL IL_PWM Boot Diode V Forward-Voltage Drop I =10 mA 0.35 V F F V Breakdown Voltage I =1 mA 22 V R R © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6707C • Rev. 1.0.2 6

F D Timing Diagram M F 6 7 0 7 C V IH_PWM - E x VIL_PWM tr a PWM - S m a l l GL 90% H i g 1.0V 10% h - P e r 90% fo r GH m to a VSWH 10% 1.2V t n D_TIMEOUT c (250ns Timeout) e , H i g h - F VSWH 2.2V re q u e n t t c PD PHGLL PD PLGHL y D r t D_DEADON tD_DEADOFF MO S M Figure 5. PWM Timing Diagram o d u l e © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6707C • Rev. 1.0.2 7

F Typical Performance Characteristics D M F Test Conditions: V =12 V, V =1.0 V, V =5 V, V =5 V, L =320 nH, T =25°C, and natural convection cooling; IN OUT CIN DRV OUT A 6 unless otherwise specified. 7 0 7 55 11 C 50 10 300kHz - E A) 45 9 500kHz x (OUT 40 fSW= 1MHz W) 8 800kHz tra nt, I 35 ss ( 7 1MHz -S utput curre 223050 fSW= 300kHz e Power Lo 456 mall H e O 15 dul 3 ig Modul 150 VΘIJNPC=B 1=2 V3,. 5V°OCU/TW= 1.0V Mo 12 h-Pe r 0 0 f o 0 25 50 75 100 125 150 0 5 10 15 20 25 30 35 40 45 r PCB Temperature (°C) Module Output Current, I (A) m OUT a n Figure 6. Safe Operating Area Figure 7. Module Power Loss vs. Output Current c e , 1.5 1.3 H IOUT= 30A IOUT= 30A, fSW= 300kHz ig s h ss 1.4 os - o L F wer L 1.3 ower 1.2 req ule Po 1.2 dule P 1.1 uen od Mo c alized M 1.1 malized 1.0 y DrM orm 1 Nor O N S 0.9 0.9 M 200 300 400 500 600 700 800 900 1000 4 6 8 10 12 14 16 o Module Switching Frequency, fSW(kHz) Module Input Voltage, VIN(V) du l e Figure 8. Power Loss vs. Switching Frequency Figure 9. Power Loss vs. Input Voltage 1.10 2.2 I = 30A, f = 300kHz I = 30A, f = 300kHz OUT SW OUT SW s 2.0 s o s L s Power 1.05 wer Lo11..68 e Po d Modul1.00 Module 11..24 ze d ali0.95 ze1.0 Norm ormali0.8 N 0.90 0.6 4.50 4.75 5.00 5.25 5.50 0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4 Driver Supply Voltage, V and V (V) Output Voltage, V (V) DRV CIN OUT Figure 10. Power Loss vs. Driver Supply Voltage Figure 11. Power Loss vs. Output Voltage © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6707C • Rev. 1.0.2 8

F Typical Performance Characteristics (Continued) D M F Test Conditions: V =12 V, V =1.0 V, V =5 V, V =5 V, L =320 nH, T =25°C, and natural convection cooling; IN OUT CIN DRV OUT A 6 unless otherwise specified. 7 0 7 1.06 50 C 1.05 IOUT= 30A, fSW= 300kHz A) 45 IOUT= 0A - E ss (m x Module Power Lo 1111....00001234 Current, I+ IVDRV VCIN 23345050 tra-Small H zed 1.00 pply 20 ig ali Su 15 h Norm 00..9989 Driver 105 -Perf 225 275 325 375 425 200 300 400 500 600 700 800 900 1000 o r Output Inductance, LOUT(nH) Module Switching Frequency, fSW(kHz) m a n Figure 12. Power Loss vs. Output Inductance Figure 13. Driver Supply Current vs. Frequency c e , 17 1.10 H , I+ Iy Current(mA)VDRV VCIN 111456 IOUT= 0A, fSW= 300kHz Driver Supply Current 11111.....0000002468 31M00HkzHz igh-Frequency ver Suppl 13 malized 00..9968 DrMO Dri or S N 12 0.94 M 4.50 4.75 5.00 5.25 5.50 0 5 10 15 20 25 30 35 40 45 o Driver Supply Voltage, VDRVand VCIN(V) Module Output Current, IOUT(A) d u l e Figure 14. Driver Supply Current vs. Driver Figure 15. Driver Supply Current vs. Output Current Supply Voltage 4.0 4.0 ge (V) 33..05 TA= 25°C VIH_PWM VTRI_HI ge ( V)33..05 VCIN= 5V VTRI_HI VIH_PWM a a olt VHIZ_PWM olt V 2.5 V2.5 d d ol ol sh 2.0 sh2.0 hre VTRI_LO hre VTRI_LO M T 1.5 M T1.5 PW 1.0 VIL_PWM PW1.0 V IL_PWM 0.5 0.5 4.50 4.75 5.00 5.25 5.50 -50 -25 0 25 50 75 100 125 150 Driver Supply Voltage, V & V (V) DRV CIN Driver IC Junction Temperature, T (°C) J Figure 16. PWM Thresholds vs. Driver Supply Voltage Figure 17. PWM Thresholds vs. Temperature © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6707C • Rev. 1.0.2 9

F Typical Performance Characteristics (Continued) D M F Test Conditions: V =12 V, V =1.0 V, V =5 V, V =5 V, L =320 nH, T =25°C, and natural convection cooling; IN OUT CIN DRV OUT A 6 unless otherwise specified. 7 0 7 2.2 2.0 C TA= 25°C VCIN= 5V - old Voltage (V) 12..80 VIH_SMOD old Voltage (V)111...789 VIH_SMOD Extra-Sm hresh 1.6 hresh1.6 VIL_SMOD all T T H D# VIL_SMOD OD 1.5 ig O 1.4 M h SM S1.4 -P e 1.2 1.3 r f 4.50 4.75 5.00 5.25 5.50 -50 -25 0 25 50 75 100 125 150 o Driver Supply Voltage, VCIN(V) Driver IC Junction Temperature (oC) rm a Figure 18. SMOD# Thresholds vs. Driver Figure 19. SMOD# Thresholds vs. Temperature n Supply Voltage c e , -9.0 2.00 H ent, I(uA)PLU-1-90..50 VCIN= 5V oltage (V)11..8900 VCIN = 5V VIH_DISB igh-Freq # Pull-up Curr--1110..05 B Threshold V11..6700 VIL_DISB uency Dr D S M MO-11.5 DI1.50 O S S -12.0 1.40 M -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 o Driver IC Junction Temperature, T (oC) Driver IC Junction Temperature, T (°C) d J J u l Figure 20. SMOD# Pull-Up Current vs. Temperature Figure 21. Disable Thresholds vs. Driver e Supply Voltage 2.1 12.0 V) 2.0 TA= 25oC µA) 11.5 VCIN= 5V Voltage ( 11..89 VIH_DISB ent , I (PLD 1101..50 hreshold 11..67 VIL_DISB Down Curr 109..05 B# T 1.5 Pull- 9.0 S # DI 1.4 B S 8.5 DI 1.3 8.0 4.50 4.75 5.00 5.25 5.50 -50 -25 0 25 50 75 100 125 150 Driver Supply Voltage, V (V) CIN Driver IC Junction Temperature ( oC) Figure 22. Disable Thresholds vs. Temperature Figure 23. Disable Pull-Down Current vs. Temperature © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6707C • Rev. 1.0.2 10

F D M Functional Description F 6 The FDMF6707C is a driver-plus-FET module optimized Three-State PWM Input 7 for the synchronous buck converter topology. A single 0 The FDMF6707C incorporates a three-state 5 V PWM 7 PWM input signal is all that is required to properly drive C input gate drive design. The three-state gate drive has the high-side and the low-side MOSFETs. Each part is both logic HIGH level and LOW level, along with a - capable of driving speeds up to 1 MHz. E three-state shutdown window. When the PWM input x VCIN and Disable (DISB#) signal enters and remains within the three -state window tr a for a defined hold-off time (t ), both GL and GH The VCIN pin is monitored by an under-voltage lockout are pulled LOW. This featurDe_ HeOnLDa-bOlFeFs the gate drive to -S (UVLO) circuit. When V rises above ~3.1 V, the driver m CIN shut down both high-and low-side MOSFETs to support is enabled. When V falls below ~2.7 V, the driver is a CIN features such as phase shedding, a common feature on l disabled (GH, GL=0). The driver can also be disabled by multi-phase voltage regulators. l H pulling the DISB# pin LOW (DISB# < V ), which IL_DISB i g holds both GL and GH LOW regardless of the PWM Exiting Three-State Condition h input state. The driver can be enabled by raising the - When exiting a valid three-state condition, the P DISB# pin voltage HIGH (DISB# > VIH_DISB). FDMF6707C design follows the PWM input command. If e r Table 1. UVLO and Disable Logic the PWM input goes from three-state to LOW, the low- fo side MOSFET is turned on. If the PWM input goes from r m UVLO DISB# Driver State three-state to HIGH, the high-side MOSFET is turned a on, as illustrated in Figure 25. The FDMF6707C design n 0 X Disabled (GH, GL=0) allows for short propagation delays when exiting the c e 1 0 Disabled (GH, GL=0) three-state window (see Electrical Characteristics). , H 1 1 Enabled (See Table 2) Low-Side Driver ig h 1 Open Disabled (GH, GL=0) The low-side driver (GL) is designed to drive a ground- - F referenced low R N-channel MOSFET. The bias Note: DS(ON) r for GL is internally connected between VDRV and e 3. DISB# internal pull-down current source is 10 µA. q CGND. When the driver is enabled, the driver's output is u Thermal Warning Flag (THWN#) 180° out of phase with the PWM input. When the driver e n The FDMF6707C provides a thermal warning flag is disabled (DISB#=0 V), GL is held LOW. c y (THWN#) to advise of over-temperature conditions. The High-Side Driver D thermal warning flag uses an open-drain output that r The high-side driver is designed to drive a floating M pulls to CGND when the activation temperature (150°C) N-channel MOSFET. The bias voltage for the high-side O is reached. The THWN# output returns to high- driver is developed by a bootstrap supply circuit S impedance state once the temperature falls to the reset consisting of the internal Schottky diode and external M temperature (135°C). The THWN# output requires a bootstrap capacitor (C ). During startup, V is o pull-up resistor, which can be connected to VCIN. BOOT SWH d held at PGND, allowing C to charge to V THWN# does NOT disable the DrMOS module. BOOT DRV u through the internal diode. When the PWM input goes le HIGH, GH begins to charge the gate of the high-side 150°C 135°C Reset MOSFET (Q1). During this transition, the charge is Activation Temperature removed from C and delivered to the gate of Q1. HIGH Temperature BOOT As Q1 turns on, V rises to V , forcing the BOOT SWH IN THWN# pin to V + V , which provides sufficient V IN BOOT GS Logic Normal Thermal enhancement for Q1. To complete the switching cycle, State Operation Warning Q1 is turned off by pulling GH to VSWH. CBOOT is then recharged to V when V falls to PGND. GH DRV SWH LOW output is in-phase with the PWM input. The high-side gate is held LOW when the driver is disabled or the T PWM signal is held within the three-state window for J_driver IC longer than the three-state hold-off time, tD_HOLD-OFF. Figure 24. THWN Operation © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6707C • Rev. 1.0.2 11

F D Adaptive Gate Drive Circuit M F The driver IC design ensures minimum MOSFET dead To prevent overlap during the HIGH-to-LOW transition 6 7 time, while eliminating potential shoot-through (cross- (Q1 off to Q2 on), the adaptive circuitry monitors the 0 conduction) currents. It senses the state of the MOSFETs voltage at the VSWH pin. When the PWM signal goes 7 C and adjusts the gate drive adaptively to prevent LOW, Q1 turns off after a propagation delay (t ). PD_PLGHL - simultaneous conduction. Figure 25 provides the timing Once the VSWH pin falls below ~2.2 V, Q2 turns on E waveforms. To prevent overlap during the LOW-to-HIGH after adaptive delay, tD_DEADOFF. Additionally, VGS(Q1) is x switching transition (Q2 off to Q1 on), the adaptive monitored. When VGS(Q1) is discharged below ~1.2 V, a tr a circuitry monitors the voltage at the GL pin. When the secondary adaptive delay is initiated that results in Q2 - S PWM signal goes HIGH, Q2 turns off after a propagation being driven on after t , regardless of VSWH D_TIMEOUT m delay (t ). Once the GL pin is discharged below state. This function ensures C is recharged each PD_PHGLL BOOT a ~1 V, Q1 turns on after adaptive delay, tD_DEADON. switching cycle in the event that the VSWH voltage does ll not fall below the 2.2 V adaptive threshold. Secondary H delay tD_TIMEOUT is longer than tD_DEADOFF. ig h - P e r f o r VIH_PWM VIH_PWM VTRI_HI VIH_PWM VVITHRIP_WHIM man VIL_PWM VTRI_LO ce tR_GH tF_GH VIL_PWM , PWM H i g less th a n tD_HOLD-OFF 90 % h GH tD_HOLD-OFF - to 10% F VSWH r e q VIN ue n CCM DCM DCM c 2.2V VOUT y D VSWH r M O GL S 90% 90% M 1.0V 10% 10% o d t PD_PHGLL t PD_PLGHL tR_GL t F_GL tPD_TSGHH tD_HOLD-OFF tPD_TSGHH tlDe_sHsO tLhD a- OnF F t D_HOLD-OFF tPD_TSGLH ule t D_DEADON t D_DEADOFF En ter Exit Enter Exit E nter Exit 3-State 3-State 3-State 3 State 3-State 3-State Notes: tPD_xxx = propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal. Example (tPD_PHGLL – PWM going HIGH to LS VGS (GL) going LOW) tD_xxx = delay from IC generated signal to IC generated signal. Example (tD_DEADON – LS VGS (GL) LOW to HS VGS (GH) HIGH) PWM Exiting 3-state tPD_PHGLL = PWM rise to LS VGS fall, VIH_PWM to 90% LS VGS tPD_TSGHH = PWM 3-state to HIGH to HS VGS rise, VIH_PWM to 10% HS VGS tPD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGS tPD_TSGLH = PWM 3-state to LOW to LS VGS rise, VIL_PWM to 10% LS VGS tPD_PHGHH = PWM rise to HS VGS rise, VIH_PWM to 10% HS VGS (SMOD# held LOW) SMOD# Dead Times tPD_SLGLL = SMOD# fall to LS VGS fall, VIL_SMOD to 90% LS VGS tD_DEADON = LS VGS fall to HS VGS rise, LS-comp trip value (~1.0V GL) to 10% HS VGS tPD_SHGLH = SMOD# rise to LS VGS rise, VIH_SMOD to 10% LS VGS tD_DEADOFF = VSWH fall to LS VGS rise, SW-comp trip value (~2.2V VSWH) to 10% LS VGS Figure 25. PWM and 3-StateTiming Diagram © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6707C • Rev. 1.0.2 12

F D M Skip Mode (SMOD) F 6 The SMOD function allows higher converter efficiency Table 2. SMOD Logic 7 0 under light-load conditions. During SMOD, the low-side 7 FET gate signal is disabled (held LOW), preventing DISB# PWM SMOD# GH GL C discharging of the output capacitors as the filter inductor 0 X X 0 0 - current attempts reverse current flow – also known as E 1 3-State X 0 0 x Diode Emulation Mode. t r 1 0 0 0 0 a When the SMOD# pin is pulled HIGH, the synchronous - S buck converter works in Synchronous Mode. This mode 1 1 0 1 0 m allows for gating on the low-side FET. When the 1 0 1 0 1 a SMOD# pin is pulled LOW, the low-side FET is gated ll off. If the SMOD# pin is connected to the PWM 1 1 1 1 0 H controller, the controller can actively enable or disable Note: ig SMOD when the controller detects light-load condition 4. The SMOD feature is intended to have low h- from output current sensing. This pin is active LOW. propagation delay between the SMOD signal and P e See Figure 26 for timing delays. the low-side FET VGS response time to control rf diode emulation on a cycle-by-cycle basis. o r m a n c e SMOD# , VIH_SMOD H VIL_SMOD ig h VIH_PWM VIH_PWM -F r VIL_PWM eq PWM u e 90% n GH c to 10% 10% y VSWH D r M O DCM S 2.2V CCM CCM VOUT M VSWH o d u GL 90% le 1.0V 10% 10% tPD_PHGLL tPD_PLGHL tPD_SLGLL tPD_PHGHH tPD_SHGLH tD_DEADON tD_DEADOFF Delay from SMOD# going Delay from SMOD# going LOW to LS VGSLOW HIGH to LS VGS HIGH HS turn-on with SMOD# LOW Figure 26. SMOD Timing Diagram © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6707C • Rev. 1.0.2 13

F D Application Information M F 6 Supply Capacitor Selection VCIN Filter 7 0 7 For the supply inputs (VDRV and VCIN), a local ceramic The VDRV pin provides power to the gate drive of the C bypass capacitor is required to reduce noise and to high-side and low-side power MOSFETs. In most cases, - supply peak transient currents during gate drive VDRV can be connected directly to VCIN, which supplies E switching action. It is recommended to use a minimum power to the logic circuitry of the gate driver. For x t capacitor value of 1 µF X7R or X5R. Keep this capacitor additional noise immunity, an RC filter can be inserted r a close to the VCIN and VDRV pins and connect it to the between VDRV and VCIN. Recommended values would - S GND plane with vias. be 10 Ω (RVCIN) placed between VDRV and VCIN and m 1 µF (CVCIN) from VCIN to CGND (see Figure 27). a Bootstrap Circuit l l The bootstrap circuit uses a charge storage capacitor Power Loss and Efficiency H i (C ), as shown in Figure 27. A bootstrap capacitance Measurement and Calculation g BOOT h of 100 nF X7R or X5R capacitor is typically adequate. A Refer to Figure 28 for power loss testing method. Power - series bootstrap resistor may be needed for specific loss calculations are: P e applications to improve switching noise immunity. The r P =(V x I ) + (V x I ) (W) (1) f boot resistor may be required when operating near the IN IN IN 5V 5V o maximum rated VIN and is effective at controlling the PSW=VSW x IOUT (W) (2) rm high-side MOSFET turn-on slew rate and VSHW POUT=VOUT x IOUT (W) (3) a overshoot. Typical RBOOT values from 0.5 Ω to 2.0 Ω are PLOSS_MODULE=PIN - PSW (W) (4) nc effective in reducing VSWH overshoot. PLOSS_BOARD=PIN - POUT (W) (5) e, EFFMODULE=100 x PSW/PIN (%) (6) H i EFFBOARD=100 x POUT/PIN (%) (7) gh - F r e q u e n c y D r M O S M o d u l e Figure 27. Block Diagram With V Filter CIN Figure 28. Power Loss Measurement © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6707C • Rev. 1.0.2 14

F PCB Layout Guidelines D M F Figure 29 provides an example of a proper layout for the boot capacitor (C ) and DrMOS BOOT pin. The BOOT 6 FDMF6707C and critical components. All of the high- BOOT-to-VSWH loop size, including R and 7 BOOT 0 current paths, such as V , V , V , and GND C , should be as small as possible. The boot IN SWH OUT BOOT 7 copper, should be short and wide for low inductance resistor may be required when operating near the C and resistance. This technique achieves a more stable maximum rated VIN. The boot resistor is effective at - and evenly distributed current flow, along with enhanced controlling the high-side MOSFET turn-on slew rate E x heat radiation and system performance. and VSHW overshoot. RBOOT can improve noise t r operating margin in synchronous buck designs that a The following guidelines are recommendations for the may have noise issues due to ground bounce or high -S PCB designer: positive and negative VSWH ringing. However, m inserting a boot resistance lowers the DrMOS a 1. Input ceramic bypass capacitors must be placed l efficiency. Efficiency versus noise trade-offs must be l close to the VIN and PGND pins. This helps reduce H considered. R values from 0.5 Ω to 2.0 Ω are the high-current power loop inductance and the input BOOT ig typically effective in reducing VSWH overshoot. current ripple induced by the power MOSFET h - switching operation. The VIN and PGND pins handle large current P e transients with frequency components greater than 2. The VSWH copper trace serves two purposes. In 100 MHz. If possible, these pins should be rfo addition to being the high-frequency current path connected directly to the VIN and board GND r from the DrMOS package to the output inductor, it m planes. The use of thermal relief traces in series with also serves as a heat sink for the low-side MOSFET a these pins is discouraged since this adds n in the DrMOS package. The trace should be short c inductance to the power path. Added inductance in and wide enough to present a low-impedance path e series with the VIN or PGND pin degrades system , for the high-frequency, high-current flow between the H noise immunity by increasing positive and negative DrMOS and inductor to minimize losses and VSWH ringing. ig temperature rise. Note that the VSWH node is a h - high-voltage and high-frequency switching node with 8. CGND pad and PGND pins should be connected to F high noise potential. Care should be taken to the GND plane copper with multiple vias for stable re minimize coupling to adjacent traces. Since this grounding. Poor grounding can create a noise q u copper trace also acts as a heat sink for the lower transient offset voltage level between CGND and e FET, balance using the largest area possible to PGND. This could lead to faulty operation of the gate n c improve DrMOS cooling while maintaining driver and MOSFETs. y acceptable noise emission. D 9. Ringing at the BOOT pin is most effectively r 3. An output inductor should be located close to the controlled by close placement of the boot capacitor. M FDMF6707C to minimize the power loss due to the Do not add an additional BOOT to PGND capacitor: O VSWH copper trace. Care should also be taken so this may lead to excess current flow through the S the inductor dissipation does not heat the DrMOS. BOOT diode. M o 4. PowerTrench® MOSFETs are used in the output 10. The SMOD# and DISB# pins have weak internal d u stage. The power MOSFETs are effective at pull-up and pull-down current sources, respectively. l e minimizing ringing due to fast switching. In most These pins should not have any noise filter cases, no VSWH snubber is required. If a snubber is capacitors. Do not to float these pins unless used, it should be placed close to the VSWH and absolutely necessary. PGND pins. The resistor and capacitor need to be of 11. Use multiple vias on each copper area to proper size for the power dissipation. interconnect top, inner, and bottom layers to help 5. VCIN, VDRV, and BOOT capacitors should be distribute current flow and heat conduction. Vias placed as close as possible to the VCIN to CGND, should be relatively large and of reasonably low VDRV to CGND, and BOOT to PHASE pins to inductance. Critical high-frequency components, ensure clean and stable power. Routing width and such as R , C , the RC snubber, and bypass BOOT BOOT length should be considered. capacitors should be located as close to the respective DrMOS module pins as possible on the 6. Include a trace from PHASE to VSWH to improve top layer of the PCB. If this is not feasible, they noise margin. Keep the trace as short as possible. should be connected from the backside through a 7. The layout should include a placeholder to insert a network of low-inductance vias. small-value series boot resistor (R ) between the BOOT © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6707C • Rev. 1.0.2 15

F D M F 6 7 0 7 C - E x t r a - S m a l l H i g h - Top View Bottom View P e r Figure 29. PCB Layout Example f o r m a n c e , H i g h - F r e q u e n c y D r M O S M o d u l e © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6707C • Rev. 1.0.2 16

F D Physical Dimensions M F 6 7 0 7 B PIN#1 C 0.10 C INDICATOR - 6.00 2X A 5.80 Ex t 4.50 ra 30 21 - S 31 m 20 a 6.00 2.50 0.40 ll H 0.65 i g 0.25 h 1.60 - 0.10 C 11 P 40 e 2X r 1 10 f TOP VIEW SEE 0.60 0.35 o r DETAIL 'A' 0.50 TYP 0.15 m 2.10 a 2.10 n c LAND PATTERN e FRONT VIEW 0.10 C A B RECOMMENDATION , H 4.40±0.10 0.05 C i g (2.20) 0.30 h 0.40 21 300.20(40X) - F 31 r e 0.50 20 PIN #1 INDICATOR q (0.70) 2.40±0.10 0.20 MAY APPEAR AS u e OPTIONAL n c y 1.50±0.10 00..5300 (40X) D 40 11 rM 0.40 10 1 2.00±0.10 2.00±0.10 O (0.20) 0.50 S (0.20) NOTES: UNLESS OTHERWISE SPECIFIED M BOTTOM VIEW o A) DOES NOT FULLY CONFORM TO JEDEC d REGISTRATION MO-220, DATED u 1.10 MAY/2005. le 0.90 B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS 0.10 C OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 0.08 C 0.30 0.05 E) DRAWING FILE NAME: PQFN40AREV3 0.20 0.00 C SEATING DETAIL 'A' PLANE SCALE: 2:1 Figure 30. 40-Lead, Clipbond PQFN DrMOS, 6.0x6.0 mm Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6707C • Rev. 1.0.2 17

F D M F 6 7 0 7 C - E x t r a - S m a l l H i g h - P e r f o r m a n c e , H i g h - F r e q u e n c y D r M O S M o d u l e © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6707C • Rev. 1.0.2 18

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