ESDALC6V1W5 Quad TRANSIL™ array for data protection Main applications Where transient overvoltage protection in ESD sensitive equipment is required, such as : SOT323-5L ■ Computers ■ Printers ■ Communication systems Order codes ■ Cellular phones and accessories Part Number Marking ■ Wireline and wireless telephone sets ESDALC6V1W5 C61 ■ Set top boxes ESDALC6V1W5 Functional diagram Features ■ 4 Unidirectional Transil functions ■ Breakdown voltage: VBR = 6.1 V minimum I/01 I/04 ■ Low leakage current: < 1 µA ■ Low capacitance: 7.5 pF at 3 V GND ■ Very small PCB area < 4.2 mm2 typically I/02 I/03 Description The ESDALCxxxWx are monolithic suppressors designed to protect components connected to data and transmission lines against ESD. Complies with the following standards These devices clamp the voltage just above the IEC61000-4-2 logic level supply for positive transients, and to a Level 4 15 kV (air discharge) diode drop below ground for negative transients. 8 kV(contact discharge) MIL STD 883E - Method 3015-7 Class 3 Benefits 25 kV HBM (Human Body Model) ■ High ESD protection level: up to 25 kV ■ High integration TM: TRANSIL is a trademark of STMicroelectronics Rev 5 January 2006 1/7 www.st.com 7

1 Characteristics ESDALC6V1W5 1 Characteristics Table 1. Absolute Ratings (T = 25°C) amb Symbol Parameter Value Unit PPP Peak pulse power (8/20 µs) 25 W Tj Junction temperature 150 °C Tstg Storage temperature range -55 to +150 °C TL Maximum lead temperature for soldering during 10s 260 °C Top Operating temperature range(1) -40 to +150 °C 1. The values of the operating parameters versus temperature are given through curves and αT parameter. 1.1 Electrical Characteristics (Tamb = 25°C) Symbol Parameter VRM Stand-off voltage I VBR Breakdown voltage IF VCL Clamping voltage IRM Leakage current V F IPP Peak pulse current VCLVBR VRM V I IR Reverse leakage current RM IF Forward current αT Voltage temperature coefficient VF Forward voltage drop Slope:1/Rd I PP C Capacitance Rd Dynamic resistance VBR@ IR IRM @ VRM Rd αT C typ. Part Numbers min. max. max. typ.(1) max.(2) 3V bias V V mA µA V Ω 10-4/°C pF ESDALC6V1W5 6.1 7.2 1 1 3 1.1 6 7.5 1. Square pulse l = 15 A, t = 2.5 µs pp p 2. V = aT* (T - 25 °C) * V (25 °C) BR amb BR 2/7

ESDALC6V1W5 1 Characteristics Figure 1. Peak power dissipation versus Figure 2. Peak pulse power versus initial junction temperature exponential pulse duration (T initial = 25°C) j Ppp[Tjinitial] / Ppp[Tjinitial = 25°C] Ppp(W) 1.1 100 1.0 Tjinitial = 25°C 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 Tj(°C) tp(µs) 0.0 10 0 25 50 75 100 125 150 175 1 10 100 Figure 3. Clamping voltage versus peak pulse Figure 4. Capacitance versus reverse applied current (T initial = 25°C, rectangular voltage (typical values) j waveform, t = 2.5 µs) p Ipp(A) C(pF) 100.0 14 13 F=1MHz 12 VosTc=j=3205m°CVRMS 11 10 10.0 9 8 7 6 5 1.0 4 3 2 0.1 Vcl(V) Tjitnpit=ia2l. 5=µ2s5°C 01 VR(V) 0 10 20 30 40 50 60 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Figure 5. Relative variation of leakage current Figure 6. Peak forward voltage drop versus versus junction temperature peak forward current (typical (typical values) values) IR[Tj] / IR[Tj=25°C] IFM(A) 1.E+00 100 1.E-01 10 1.E-02 Tj(°C) VFM(V) 1 1.E-03 25 50 75 100 125 150 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 3/7

2 Ordering information scheme ESDALC6V1W5 Figure 7. ESD response to IEC61000-4-2 (air discharge 15 kV, positive surge) 2 Ordering information scheme ESDA LC 6V1 W5 ESD Array Low capacitance BreakdownVoltage 6V1 = 6.1Volts min Package W5 = SOT323-5L 4/7

ESDALC6V1W5 3 Package mechanical data 3 Package mechanical data 3.1 SOT323-5L package DIMENSIONS A REF. Millimeters Inches E Min. Max. Min. Max. A 0.8 1.1 0.031 0.043 e A1 0 0.1 0 0.004 b D e A2 0.8 1 0.031 0.039 b 0.15 0.3 0.006 0.012 A1 c 0.1 0.18 0.004 0.007 A2 D 1.8 2.2 0.071 0.086 Q1 E 1.15 1.35 0.045 0.053 c e 0.65 Typ. 0.025 Typ. HE HE 1.8 2.4 0.071 0.094 Q1 0.1 0.4 0.004 0.016 Figure 8. Footprint dimensions 0.3 1.0 2.9 1.0 0.35 Dimensions in mm In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 5/7

4 Ordering information ESDALC6V1W5 4 Ordering information Part Number Marking Package Weight Base qty Delivery mode ESDALC6V1W5 C61 SOT323-5L 5.4 mg 3000 Tape & reel 5 Revision history Date Revision Changes Jun-2002 4A Previous issue Reformatted to current template. Figure 5: Range of T extended to 150 °C. 10-Jan-2006 5 j Figure 6: Peak forward voltage drop versus peak forward current (typical values) added. 6/7

ESDALC6V1W5 5 Revision history Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 7/7