DS1050 5-Bit, Programmable, Pulse- Width Modulator: 1kHz, 5kHz, 10kHz, and 25kHz www.maxim-ic.com FEATURES PIN ASSIGNMENT (cid:1) Single 5-bit, programmable, pulse-width modulator (PWM) (cid:1) Adjustable Duty Cycle: 0% to 100% SCL 1 8 V CC (cid:1) 2.7V to 5.5V Operation (cid:1) Standard Frequency Values: SDA 2 7 A1 1kHz, 5kHz, 10kHz, and 25kHz A0 3 6 A2 (cid:1) 2-Wire Addressable Interface (cid:1) Packages: 8-Pin (150-mil) SOIC and 8-Pin GND 4 5 PWM(cid:1) (118-mil) (cid:1)SOP 8-Pin 150-mil SOIC (cid:1) Operating Temperature: -40oC to +85oC 8-Pin 118-mil (cid:1)SOP ORDERING INFORMATION PIN DESCRIPTION DS1050Z-001 1kHz 8-Pin 150-mil SOIC V - 2.7V to 5.5V Power Supply CC DS1050Z-005 5kHz 8-Pin 150-mil SOIC PWM - PWM Ouput O DS1050Z-010 10kHz 8-Pin 150-mil SOIC A0, A1, A2 - Device Address DS1050Z-025 25kHz 8-Pin 150 mil SOIC SDA - Serial Data I/O SCL - Serial Clock Input DS1050U-001 1kHz 8-Pin 118-mil (cid:1)SOP GND - Ground DS1050U-005 5kHz 8-Pin 118-mil (cid:1)SOP DS1050U-010 10kHz 8-Pin 118-mil (cid:1)SOP DS1050U-025 25kHz 8-Pin 118-mil µSOP DESCRIPTION The DS1050 is a programmable, 5-bit, pulse-width modulator featuring a 2-wire addressable controlled interface. The DS1050 operates from power supplies ranging from 2.7V up to 5.5V. The PWM output provides a signal that swings from 0V to V . The DS1050 requires a typical operating current of 50(cid:1)A CC and a programmable shutdown supply current of 1(cid:1)A. Four standard PWM output frequencies are offered and include 1kHz, 5kHz, 10kHz, and 25kHz. The 2-wire addressable interface allows operation of multiple devices on a single 2-wire bus and provides compatibility with other Dallas Semiconductor 2-wire devices such as real-time clocks (RTCs), digital thermometers, and digital potentiometers. The device is ideal for low-cost LCD contrast and/or brightness control, power supply voltage adjustment, and battery charging or current adjustment. The DS1050 is offered in standard integrated circuit packaging including the 8-pin (150-mil) SOIC and space-saving 8-pin (118-mil) (cid:1)SOP. 1 of 17 072701

DS1050 OPERATION Interface protocol is simplified to an 8-bit control byte and 8-bit data byte. Information can be read or written to the DS1050 including a commanded shutdown operation. Power-Up Configuration The DS1050 powers-up to half-scale (10000B) providing 50% duty-cycle. In this mode, the DS1050 can be used as a standalone oscillator of the frequency specified. Once powered, the PWM output can be changed via the 2-wire addressable serial port. Pin Description V – Power supply terminal. The DS1050 will support operation from power supply voltages ranging cc from +2.7 volts to +5.5 volts. GND – Ground terminal. PWM – Pulse-width modulated output. This output is a square-wave having amplitudes from 0 volts to O V . The duty cycle of this output is governed by a 5-bit control register. Output duty cycles range from CC 0% to 96.88%. An additional command sequence will provide a 100% duty cycle or “full-on.” SCL – Serial clock input. SDA – Serial bi-directional data I/O. A0, A1, A2 – Device address (chip selects). 2-Wire Addressable Serial Port Control The 2-wire serial port interface supports a bi-directional data transmission protocol with device addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a “master.” The devices that are controlled by the master are “slaves.” The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1050 operates as a slave on the 2-wire bus. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The following I/O terminals control the 2-wire serial port: SDA, SCL, A0, A1, and A2. A 2-wire serial port overview and timing diagrams for the 2-wire serial port can be found in Figures 2 and 5, respectively. Timing information for the 2-wire serial port is provided in the “AC Electrical Characteristics” table for 2-wire serial communications. 2 of 17

DS1050 The following bus protocol has been defined (see Figure 2). (cid:1) Data transfer may be initiated only when the bus is not busy. (cid:1) During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is high will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain HIGH. Start data transfer: A change in the state of the data line from HIGH to LOW while the clock is HIGH, defines a START condition. Stop data transfer: A change in the state of the data line from LOW to HIGH while the clock line is HIGH defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Figure 2 details how data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/W bit, two types of data transfer are possible. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Within the bus specifications, a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. The DS1050 works in both modes. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. 1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the command/control byte. Next follows a number of data bytes. The slave returns an “acknowledge” bit after each received byte. 2. Data transfer from a slave transmitter to a master receiver. The first byte (the command/control byte) is transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a “not acknowledge” is returned. 3 of 17

DS1050 The master device generates all serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus will not be released. The DS1050 may operate in the following two modes: 1. Slave receiver mode: Serial data and clock are received through SDA and SCL, respectively. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave (device) address and direction bit. 2. Slave transmitter mode: The first byte is received and handled as in the slave receiver mode. However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1050 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. SLAVE ADDRESS A command/control byte is the first byte received following the START condition from the master device. The command/control byte consists of a four-bit control code. For the DS1050, this is set as 0101 binary for read/write operations. The next three bits of the command/control byte are the device select bits or slave address (A2, A1, A0). They are used by the master device to select which of eight possible devices is to be accessed. When reading or writing the DS1050, the device select bits must match the device select pins (A2, A1, A0). The last bit of the command/control byte (R/W) defines the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected. The command control byte is presented in Figure 3. Following the START condition, the DS1050 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving the 0101 control code, the appropriate device address bits, and the read/write bit, the slave device outputs an “acknowledge” signal on the SDA line. COMMAND AND PROTOCOL The command and protocol structure of the DS1050 allows the user to read or write the PWM configuration register or place the device in a low-current state (shut-down mode) and recall the device from a low-current state. Additionally, the 2-wire command/protocol structure of the DS1050 will support eight different devices that can be uniquely controlled. Figure 4a, b, c, d, & e show the five different command and protocol bytes for the DS1050. These include the following command operations: 1) Set PWM duty cycle, 2) Set PWM duty cycle 100%, 3) Set shutdown mode, 4) Set recall mode, 5) Read PWM configuration register. The command operation “Set PWM Duty Cycle” is used to configure the output duty cycle of the device. The DS1050 has a 5-bit resolution and is capable of setting the duty cycle output from 0% up to 96.88% in steps of 3.125%. A binary value of (00000B) sets the duty cycle output at 0% while a binary value of (11111B) sets the duty cycle output at 96.88%. The command operation “Set PWM Duty Cycle 100%” is used to configure the output duty cycle of the device to a “full-on.” This command is provided in addition to the Set PWM Duty Cycle command for flexibility and convenience in total duty cycle coverage. It allows the user to provide a total duty cycle range from 0% to 100%. 4 of 17

DS1050 The command operation “Set Shutdown Mode” is used to provide a low-current (inactive state) state for the DS1050. When in a low-current state the DS1050 will draw currents less than or equal to 1(cid:1)A. The PWM output will be high impedance. O The command operation “Set Recall Mode” is used to recall the DS1050 from a low-current state. The value of the PWM output is recalled to that prior to initiating a “Set shutdown mode” command. O The “Read PWM Duty Cycle” command is used to read the current setting of the PWM configuration register. Information returned by this command includes PWM output value as well as whether the device is in a shutdown configuration. PWM data values and control/command values are always transmitted most significant bit (MSB) first. During communications, the receiving unit always generates the “acknowledge.” READING THE DS1050 As shown in Figure 4e, the DS1050 provides one read command operation. This operation allows the user to read the current setting of the PWM configuration register. Specifically, the R/W bit of the command/control byte is set equal to a 1 for a read operation. Communication to read the DS1050 begins with a START condition which is issued by the master device. The command/control byte from the master device will follow the START condition. Once the command/control byte has been received by the DS1050, the part will respond with an ACKNOWLEDGE. The read/write bit of the command/control byte, as stated, should be set equal to 1 for reading the DS1050. When the master has received the ACKNOWLEDGE from the DS1050, the master can then begin to receive the PWM configuration register data. As mentioned this data will be transmitted MSB first. Once the eight bits of the PWM configuration register have been transmitted, the master will need to issue an ACKNOWLEDGE, unless it is the only byte to be read, in which case the master issues a NOT ACKNOWLEDGE. If desired the master may stop the communication transfer at this point by issuing the STOP condition. Final communication transfer is terminated by issuing the STOP command. Again, the flow of the read operation is presented in Figure 4e. WRITING THE DS1050 A data flow diagram for writing the DS1050 is shown in Figures 4a, b, c, and d. The DS1050 has three write commands that are used to change the PWM configuration register or the shutdown and recall mode of the device. All the write operations begin with a START condition. Following the START condition, the master device will issue the command/control byte. The read/write bit of the command/control byte will be set to “0” for writing the DS1050. Once the command/control byte has been issued and the master receives the acknowledgment from the DS1050, PWM configuration data is transmitted to the DS1050 by the master device. A data byte for the DS1050 will contain PWM configuration data and shutdown/recall command data. The five least significant bits of data specify the PWM configuration value while the three most significant bits specify the whether the device is to be shutdown or recalled. When the DS1050 has received the data byte, it will respond with an ACKNOWLEDGE. At this point, the new PWM configuration register value and shutdown/recall command value will be updated in the DS1050. The master device, after the receipt of the ACKNOWLEDGE, can continue to transmit additional data bytes 5 of 17

DS1050 or if the transaction is complete respond with the STOP condition. The 2-wire serial timing diagram is presented in Figure 5. 6 of 17

DS1050 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground -0.3V to +6.0V Operating Temperature -40oC to +85oC Storage Temperature -55oC to +125oC Soldering Temperature See J-STD-020A specification *This is a stress rating only and functional operation of the device at these or any other conditions above those conditions indicated in the operation section of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (-40(cid:1)C to +85(cid:1)C; V = 2.7V to 5.5V) CC PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Supply voltage V +2.7 +5.5 V 1 CC DC ELECTRICAL CHARACTERISTICS (-40(cid:1)C to +85(cid:1)C; V = 2.7V to 5.5V) CC PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS NOTES Active Supply I 50 85 (cid:1)A 2 CC Current Input Leakage I +1 (cid:1)A LI Input Logic 1 V 0.7 V V +0.3 V 3, 4 IH CC CC Input Logic 0 V GND-0.3 0.3 V V 3, 4 IL CC Input Current Each 0.4(cid:2)V (cid:2)0.9 -10 10 (cid:1)A I/O I/O Pin V CC Standby Current I 0.1 1 (cid:1)A 5 STBY LOW Level Ouput V 3mA Sink 0.0 0.4 V OL1 Voltage (SDA) Current V 6mA Sink 0.0 0.6 V OL2 Current I/O Capacitance C 10 pF I/O PWM Output I V - 0.4 2 mA OH CC Currents I 0.4 3 mA OL 7 of 17

DS1050 AC ELECTRICAL CHARACTERISTICS (-40(cid:1)C to +85(cid:1)C; V = 2.7V to 5.5V) CC PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS NOTES SCL Clock f Fast Mode 0 400 kHz 6 SCL Frequency Standard Mode 0 100 Bus Free Time t Fast Mode 1.3 (cid:1)s 6 BUF Between STOP and Standard Mode 4.7 START Condition Hold Time t Fast Mode 0.6 (cid:1)s 7, 6 HD:STA (Repeated) START Standard Mode 4.0 Condition Low Period of SCL t Fast Mode 1.3 (cid:1)s 6 LOW Clock Standard Mode 4.7 High Period of SCL t Fast Mode 0.6 (cid:1)s 6 HIGH Clock Standard Mode 4.0 Data Hold Time t Fast Mode 0 0.9 (cid:1)s 6, 8, 9 HD:DAT Standard Mode 0 Data Set-Up Time t Fast Mode 100 ns 6 SU:DAT Standard Mode 250 Rise Time of Both t Fast Mode 20+0.1C 300 ns 10 R B SDA and SCL Standard Mode 1000 Signals Fall Time of Both t Fast Mode 20+0.1C 300 ns 10 F B SDA and SCL Standard Mode 300 Signals Set-Up Time for t Fast Mode 0.6 (cid:1)s SU:STO STOP Condition Standard Mode 4.0 Capacitive Load for CB Fast Mode 400 pF 10 Each Bus Line Standard Mode PWM Output tPWM(cid:1) Fast Mode 2 periods 11 Change Standard Mode AC ELECTRICAL CHARACTERISTICS (-40(cid:1)C to +85(cid:1)C; V = 2.7V to 5.5V) CC PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS NOTES Output Frequency -20 +20 % 12 Tolerance Output Impedance 200 (cid:3) Absolute Linearity -0.5 +0.5 LSB 14 Relative Linearity -0.25 +0.25 LSB 15 Resolution 5 Bits 13 Frequency ±200 ppm/ºC Temperature Coefficient Frequency Voltage 1.5 % per Coefficient V 8 of 17

DS1050 NOTES: 1. All voltages are referenced to ground. 2. I specified with outputs open. CC 3. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if V is switched off. CC 4. Address Inputs, A0, A1, and A2, should be tied to either V or GND depending on the desired CC address selections. 5. I specified for V between 3.0V and 5.0V, control port logic pins are driven to the appropriate STBY CC logic levels. 6. A fast mode device can be used in a standard mode system, but the requirement t > 250ns must then be met. This will automatically be the case if the device does not stretch SU:DAT the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t + t = 1000 + 250=1250ns before the SCL RMAX SU:DAT line is released. 7. After this period, the first clock pulse is generated. 8. The maximum t has only to be met if the device does not stretch the LOW period (t ) of the SU:DAT LOW SCL signal. 9. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. IH MIN 10. C – total capacitance of one bus line in picofarads, timing referenced to (0.9)(V ) and (0.1)(V ). B CC CC 11. A PWM output duty cycle change will occur with 2 periods of the output frequency when a change is initiated. 12. The absolute frequency output of the PWM can be expected to fall within a (cid:4)20% range from the nominal specified value of the device. 13. The DS1050 is a 5-bit PWM. The output duty cycles of the device range from 0% to 100% in step sizes of 3.125%. The “Set PWM Duty Cycle 100%” allows the PWM output to be set to full-on. 14. Absolute Linearity is used to compare measured duty cycle against expected duty cycle as determined by the DAC setting. The DS1050 is specified to provide an absolute linearity of (cid:4)0.5 LSB. 15. Relative Linearity is used to determine the change in duty cycle between adjacent or successive duty cycle settings. The DS1050 is specified to provide a relative linearity specification of (cid:4)0.25 LSB. 9 of 17

DS1050 BLOCK DIAGRAM Figure 1 vcc OSCILLATOR DRIVER PWM(cid:2) CONTROL LOGIC SCL SDA SHUTDOWN A0 Serial Port CONTROL A1 CIRCUITRY A2 GND 2-WIRE ADDRESSABLE SERIAL PORT OVERVIEW Figure 2 SDA msb slave address r/w direction bit acknowledgement acknowledgement signal from receiver signal from receiver SCL 1 2 6 7 8 9 1 2 3-7 8 9 Start ACK ACK Stop Condition Condition repeated if more bytes or repeated are transferred Start Condition COMMAND/CONTROL BYTE Figure 3 msb lsb 0 1 0 1 A2 A1 A0 r/w Device Device Read/Write Identifier Address Bit 10 of 17

DS1050 DS1050 COMMANDS AND PROTOCOL Figure 4 CONTROL PWM BYTE DATABYTE MSB LSB MSB LSB SET PWM DUTY CYCLE STS A S AA S 0 1 0 1 A2 A1 A0 0 C 0 0 0 PWM Data T (a) RT TA K OP R T R/W=0 CONTROL PWM BYTE DATABYTE MSB LSB MSB LSB S T A S A 0 1 0 1 A2 A1 A0 0 C 0 0 1 Don't Care T R O (b) T K P R/W=0 CONTROL PWM BYTE DATABYTE MSB LSB MSB LSB SET SHUT-DOWN MODE S S T S 0 1 0 1 A2 A1 A0 0 A 1 1 0 Don't Care T (c) A T C O R A K P T R T R/W=0 CONTROL PWM BYTE DATABYTE MSB LSB MSB LSB RECALL MODE S T A S (d) ART 0 1 0 1 A2 A1 A0 0 CK 1 0 0 Don't Care TOP R/W=0 CONTROL PWM BYTE DATABYTE MSB LSB MSB LSB READ PWM DUTY CYCLE S S T A (e) A 0 1 0 1 A2 A1 A0 1 C 0 0 0 PWM-DATA TO R K P T R/W=1 11 of 17

DS1050 2-WIRE SERIAL DIAGRAMS Figure 5 SDA t t BUF tF t SP t HD:STA R t LOW SCL t tHD:STA HIGH t tSU:STO SU:STA t t HD:STA SU:DAT STOP START REPEATED START 12 of 17

DS1050 TYPICAL OPERATING CHARACTERISTICS DS1050 (V = 5.0V; T = +25ºC, unless otherwise specified) CC DS1050 SUPPLY CURRENT vs. FREQUENCY 55 50 A) 45 (cid:1) ( T 40 N E R R 35 U C Y 30 L P P 25 U S 20 DS1050 Supply Current vs Freq, 3.3V 15 DS1050 Supply Current vs Freq, 5V 10 0 5 10 15 20 25 30 FREQUENCY (kHz) DS1050 DUTY CYCLE vs. POSITION 100 90 80 ) % 70 ( E L 60 C Y C 50 Y T U 40 D 30 20 DS1050 Duty Cycle vs Position, 10 3.3V and 5V 0 0 5 10 15 20 25 30 POSITION SETTING (DECIMAL) 13 of 17

DS1050 TYPICAL OPERATING CHARACTERISTICS DS1050-001 (V = 5.0V, T = +25ºC, unless otherwise specified) CC DS1050-001 FREQUENCY vs. TEMPERATURE 1.030 1.025 1.020 1.015 1.010 1.005 1.000 0.995 DS1050-001 Freq vs Temp, 3.3V 0.990 DS1050-001 Freq vs Temp, 5V 0.985 -40 -20 0 20 40 60 80 TEMPERATURE (C) DS1050-001 SUPPLY CURRENT vs. TEMPERATURE 40 35 ) A (cid:1) ( T 30 N E R R U 25 C Y L P P 20 U S 15 DS1050-001 Supply Current vs Temp, 3.3V DS1050-001SupplyCurrentvsTemp 5V 10 -40 -20 0 20 40 60 80 TEMPERATURE (C) 14 of 17

DS1050 TYPICAL OPERATING CHARACTERISTICS DS1050-005 (V = 5.0V, T = +25ºC, unless otherwise specified) CC DS1050-005 FREQUENCY vs. TEMPERATURE 5.2 5.15 5.1 5.05 5 DS1050-005 Freq vs Temp, 3.3V DS1050-005 Freq vs Temp, 5V 4.95 -40 -20 0 20 40 60 80 TEMPERATURE (C) DS1050-005 SUPPLY CURRENT vs. TEMPERATURE 45 40 ) A 35 (cid:1) ( T N E 30 R R U C 25 Y L P P 20 U S DS1050-005 Supply Current vs Temp, 3.3V 15 DS1050-005 Supply Current vs Temp, 5V 10 -40 -20 0 20 40 60 80 TEMPERATURE (C) 15 of 17

DS1050 TYPICAL OPERATING CHARACTERISTICS DS1050-010 (V = 3V, T = +25ºC, unless otherwise specified) CC DS1050-010 FREQUENCY vs. TEMPERATURE 10.7 10.65 10.6 10.55 10.5 10.45 10.4 DS1050-010 Freq vs Temp, 3.3V 10.35 DS1050-010 Freq vs Temp, 5V 10.3 -40 -20 0 20 40 60 80 TEMPERATURE (C) DS1050-010 SUPPLY CURRENT vs. TEMPERATURE 50 45 40 ) A (cid:1) ( T 35 N E R R 30 U C Y 25 L P P U 20 S 15 DS1050-010 Supply Current vs Temp, 3.3V DS1050-010 Supply Current vs Temp, 5V 10 -40 -20 0 20 40 60 80 TEMPERATURE (C) 16 of 17

DS1050 TYPICAL OPERATING CHARACTERISTICS DS1050-025 (V = 5.0V; T = +25ºC, unless otherwise specified) CC DS1050-025 FREQUENCY vs. TEMPERATURE 26.8 26.6 26.4 26.2 26 25.8 25.6 25.4 DS1050-025 Freq vs Temp, 3.3V DS1050-025 Freq vs Temp, 5V 25.2 -40 -20 0 20 40 60 80 TEMPERATURE (C) DS1050-025 SUPPLY CURRENT vs. TEMPERATURE 55 50 45 ) A (cid:1) 40 ( T N E 35 R R U 30 C Y L 25 P P U S 20 DS1050-025 Supply Current vs Temp, 3.3V DS1050-025 Supply Current vs Temp, 5V 15 10 -40 -20 0 20 40 60 80 TEMPERATURE (C) 17 of 17

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M axim Integrated: DS1050U-001+ DS1050U-005+T DS1050U-010+ DS1050U-010+T DS1050U-025+ DS1050U-025+T DS1050Z- 001 DS1050Z-001+T&R DS1050Z-005+ DS1050Z-005+T&R DS1050Z-010+ DS1050Z-010+T&R DS1050Z-025+ DS1050Z-025+T&R DS1050Z-005/C05+T DS1050Z-005 DS1050U-001+T DS1050U-005+ DS1050Z-001+