CY7C1565KV18 ® 72-Mbit QDR II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 72-QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations ■Separate independent read and write data ports With Read Cycle Latency of 2.5 cycles ❐Supports concurrent transactions CY7C1565KV18: 2M × 36 ■550-MHz clock for high bandwidth Functional Description ■Four-word burst for reducing address bus frequency The CY7C1565KV18 is1.8-V synchronous pipelined SRAM, ■Double data rate (DDR) Interfaces on both read and write ports equipped with QDR II+ architecture. Similar to QDR II (data transferred at 1100 MHz) at 550 MHz architecture, QDR II+ architecture consists of two separate ports: ■Available in 2.5-clock cycle latency the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations ■Two input clocks (K and K) for precise DDR timing and the write port has dedicated data inputs to support write ❐SRAM uses rising edges only operations. QDR II+ architecture has separate data inputs and ■Echo clocks (CQ and CQ) simplify data capture in high speed data outputs to completely eliminate the need to “turnaround” the systems data bus that exists with common I/O devices. Each port is ■Data valid pin (QVLD) to indicate valid data on the output accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the ■Single multiplexed address input bus latches address inputs input (K) clock. Accesses to the QDR II+ read and write ports are for read and write ports completely independent of one another. To maximize data ■Separate port selects for depth expansion throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with four 36-bit ■Synchronous internally self-timed writes words (CY7C1565KV18) that burst sequentially into or out of the ■Quad data rate (QDR®) II+ operates with 2.5-cycle read latency device. Because data is transferred into and out of the device on when DOFF is asserted HIGH every rising edge of both input clocks (K and K), memory ■Operates similar to QDR I device with one cycle read latency bandwidth is maximized while simplifying system design by when DOFF is asserted LOW eliminating bus “turnarounds”. ■Available in × 36 configurations Depth expansion is accomplished with port selects, which enables each port to operate independently. ■Full data coherency, providing most current data All synchronous inputs pass through input registers controlled by ■Core VDD = 1.8 V± 0.1 V; I/O VDDQ = 1.4 V to VDD [1] the K or K input clocks. All data outputs pass through output ❐Supports both 1.5 V and 1.8 V I/O supply registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. ■High-speed transceiver logic (HSTL) inputs and variable drive HSTL output buffers For a complete list of related documentation, click here. ■Available in 165-ball fine pitch ball grid array (FBGA) package (13 × 15 × 1.4 mm) ■Offered in both Pb-free and non Pb-free packages ■JTAG 1149.1 compatible test access port ■Phase-locked loop (PLL) for accurate data placement Selection Guide Description 550 MHz 500 MHz 450 MHz 400 MHz Unit Maximum operating frequency 550 500 450 400 MHz Maximum operating current × 36 1310 1210 1100 1000 mA Note 1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4 V to VDD. CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 001-15878 Rev. *S Revised November 30, 2017

CY7C1565KV18 Logic Block Diagram – CY7C1565KV18 36 D [35:0] Write Write Write Write 19 Reg Reg Reg Reg Address A(18:0) 19 Address Register A(18:0) Register ode 51 51 51 51 ode c 2 2 2 2 c e K K K K e d. D × 3 × 3 × 3 × 3 d. D KK CGLeKn. Write Ad 6 Array 6 Array 6 Array 6 Array Read Ad CLoongtircol RPS DOFF Read Data Reg. CQ 144 VREF 72 Reg. Reg. 36 CQ Control WPS 36 Logic BWS[3:0] 72 Reg. 36 36 Q[35:0] 36 QVLD Document Number: 001-15878 Rev. *S Page 2 of 30

CY7C1565KV18 Contents Pin Configuration .............................................................4 Boundary Scan Order ....................................................18 Pin Definitions ..................................................................5 Power-Up Sequence in QDR II+ SRAM .........................19 Functional Overview ........................................................6 Power-Up Sequence .................................................19 Read Operations .........................................................6 PLL Constraints .........................................................19 Write Operations .........................................................6 Maximum Ratings ...........................................................20 Byte Write Operations .................................................6 Operating Range .............................................................20 Concurrent Transactions .............................................7 Neutron Soft Error Immunity .........................................20 Depth Expansion .........................................................7 Electrical Characteristics ...............................................20 Programmable Impedance ..........................................7 DC Electrical Characteristics .....................................20 Echo Clocks ................................................................7 AC Electrical Characteristics .....................................21 Valid Data Indicator (QVLD) ........................................7 Capacitance ....................................................................21 PLL ..............................................................................7 Thermal Resistance ........................................................21 Application Example ........................................................8 AC Test Loads and Waveforms .....................................22 Truth Table ........................................................................9 Switching Characteristics ..............................................23 Write Cycle Descriptions ...............................................10 Switching Waveforms ....................................................24 IEEE 1149.1 Serial Boundary Scan (JTAG) ..................11 Read/Write/Deselect Sequence ................................24 Disabling the JTAG Feature ......................................11 Ordering Information ......................................................25 Test Access Port .......................................................11 Ordering Code Definitions .........................................25 Performing a TAP Reset ...........................................11 Package Diagram ............................................................26 TAP Registers ...........................................................11 Acronyms ........................................................................27 TAP Instruction Set ...................................................11 Document Conventions .................................................27 TAP Controller State Diagram .......................................13 Units of Measure .......................................................27 TAP Controller Block Diagram ......................................14 Document History Page .................................................28 TAP Electrical Characteristics ......................................14 Sales, Solutions, and Legal Information ......................30 TAP AC Switching Characteristics ...............................15 Worldwide Sales and Design Support .......................30 TAP Timing and Test Conditions ..................................16 Products ....................................................................30 Identification Register Definitions ................................17 PSoC® Solutions ......................................................30 Scan Register Sizes .......................................................17 Cypress Developer Community .................................30 Instruction Codes ...........................................................17 Technical Support .....................................................30 Document Number: 001-15878 Rev. *S Page 3 of 30

CY7C1565KV18 Pin Configuration The pin configurations for CY7C1565KV18 follows. [2] Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout CY7C1565KV18 (2M × 36) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/288M A WPS BWS K BWS RPS A NC/144M CQ 2 1 B Q27 Q18 D18 A BWS K BWS A D17 Q17 Q8 3 0 C D27 Q28 D19 V A NC A V D16 Q7 D8 SS SS D D28 D20 Q19 V V V V V Q16 D15 D7 SS SS SS SS SS E Q29 D29 Q20 V V V V V Q15 D6 Q6 DDQ SS SS SS DDQ F Q30 Q21 D21 V V V V V D14 Q14 Q5 DDQ DD SS DD DDQ G D30 D22 Q22 V V V V V Q13 D13 D5 DDQ DD SS DD DDQ H DOFF V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J D31 Q31 D23 V V V V V D12 Q4 D4 DDQ DD SS DD DDQ K Q32 D32 Q23 V V V V V Q12 D3 Q3 DDQ DD SS DD DDQ L Q33 Q24 D24 V V V V V D11 Q11 Q2 DDQ SS SS SS DDQ M D33 Q34 D25 V V V V V D10 Q1 D2 SS SS SS SS SS N D34 D26 Q25 V A A A V Q10 D9 D1 SS SS P Q35 D35 Q26 A A QVLD A A Q9 D0 Q0 R TDO TCK A A A NC A A A TMS TDI Note 2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level. Document Number: 001-15878 Rev. *S Page 4 of 30

CY7C1565KV18 Pin Definitions Pin Name I/O Pin Description D[x:0] Input- Data input signals. Sampled on the rising edge of K and K clocks when valid write operations are active. Synchronous CY7C1565KV18  D [35:0] WPS Input- Write port select  Active LOW. Sampled on the rising edge of the K clock. When asserted active, a Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D . [x:0] BWS0, Input- Byte write select (BWS) 0, 1, 2, and 3  Active LOW. Sampled on the rising edge of the K and K clocks BWS1, Synchronous when write operations are active. Used to select which byte is written into the device during the current BWS2, portion of the write operations. Bytes not written remain unaltered. BWS3 CY7C1565KV18  BWS0 controls D[8:0], BWS1 controls D[17:9], BWS controls D and BWS controls D 2 [26:18] 3 [35:27]. All the byte write selects are sampled on the same edge as the data. Deselecting a BWS ignores the corresponding byte of data and it is not written into the device. A Input- Address inputs. Sampled on the rising edge of the K clock during active read and write operations. These Synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as 2M × 36 (4 arrays each of 512K × 36) for CY7C1565KV18. Therefore, 19 address inputs for CY7C1565KV18. These inputs are ignored when the appropriate port is deselected. Q Outputs- Data output signals. These pins drive out the requested data when the read operation is active. Valid [x:0] Synchronous data is driven out on the rising edge of the K and K clocks during read operations. On deselecting the read port, Q are automatically tri-stated. [x:0] CY7C1565KV18  Q [35:0] RPS Input- Read port select  Active LOW. Sampled on the rising edge of positive input clock (K). When active, a Synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the K clock. Each read access consists of a burst of four sequential transfers. QVLD Valid output Valid output indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ. indicator K Input Clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q . All accesses are initiated on the rising edge of K. [x:0] K Input Clock Negative input clock input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q . [x:0] CQ Echo Clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock (K) of the QDR II+. The timings for the echo clocks are shown in the Switching Characteristics on page 23. CQ Echo Clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock (K) of the QDR II+.The timings for the echo clocks are shown in the Switching Characteristics on page 23. ZQ Input Output impedance matching input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q output impedance are set to 0.2 × RQ, where RQ is a resistor [x:0] connected between ZQ and ground. Alternatively, this pin can be connected directly to V , which DDQ enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. DOFF Input PLL turn-off  Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timings in the PLL turned off operation differs from those listed in this datasheet. For normal operation, this pin can be connected to a pull-up through a 10 K or less pull-up resistor. The device behaves in QDR I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167MHz with QDR I timing. TDO Output Test data out (TDO) pin for JTAG TCK Input Test clock (TCK) pin for JTAG TDI Input Test data in (TDI) pin for JTAG TMS Input Test mode select (TMS) pin for JTAG NC N/A Not Connected to the die. Can be tied to any voltage level. Document Number: 001-15878 Rev. *S Page 5 of 30

CY7C1565KV18 Pin Definitions (continued) Pin Name I/O Pin Description NC/144M N/A Not Connected to the die. Can be tied to any voltage level. NC/288M N/A Not Connected to the die. Can be tied to any voltage level. V Input- Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC REF Reference measurement points. V Power Supply Power supply inputs to the core of the device DD V Ground Ground for the device SS V Power Supply Power supply inputs for the outputs of the device DDQ Functional Overview accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device ignores the second The CY7C1565KV18 is synchronous pipelined Burst SRAM read request. Read accesses can be initiated on every other K equipped with a read port and a write port. The read port is clock rise. Doing so pipelines the data flow such that data is dedicated to read operations and the write port is dedicated to transferred out of the device on every rising edge of the input write operations. Data flows into the SRAM through the write port clocks (K and K). and flows out through the read port. These devices multiplex the When the read port is deselected, the CY7C1565KV18 first address inputs to minimize the number of address pins required. completes the pending read transactions. Synchronous internal By having separate read and write ports, the QDR II+ completely circuitry automatically tri-states the outputs following the next eliminates the need to “turnaround” the data bus and avoids any rising edge of the negative input clock (K). This enables for a possible data contention, thereby simplifying system design. seamless transition between devices without the insertion of wait Each access consists of four 36-bit data transfers in the case of states in a depth expanded memory. CY7C1565KV18, in two clock cycles. Write Operations These devices operate with a read latency of two and half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or Write operations are initiated by asserting WPS active at the connected to VSS then device behaves in QDR I mode with a rising edge of the positive input clock (K). On the following K read latency of one clock cycle. clock rise the data presented to D is latched and stored into [35:0] Accesses for both ports are initiated on the positive input clock the lower 36-bit write data register, provided BWS[3:0] are both (K). All synchronous input and output timing are referenced from asserted active. On the subsequent rising edge of the negative the rising edge of the input clocks (K and K). input clock (K) the information presented to D[35:0] is also stored into the write data register, provided BWS are both asserted All synchronous data inputs (D ) pass through input registers [3:0] [x:0] active. This process continues for one more cycle until four 36-bit controlled by the input clocks (K and K). All synchronous data words (a total of 144 bits) of data are stored in the SRAM. The outputs (Q ) outputs pass through output registers controlled [x:0] 144 bits of data are then written into the memory array at the by the rising edge of the input clocks (K and K) as well. specified location. Therefore, write accesses to the device can All synchronous control (RPS, WPS, BWS ) inputs pass not be initiated on two consecutive K clock rises. The internal [x:0] through input registers controlled by the rising edge of the input logic of the device ignores the second write request. Write clocks (K and K). accesses can be initiated on every other rising edge of the positive input clock (K). Doing so pipelines the data flow such CY7C1565KV18 is described in the following sections. that 36 bits of data can be transferred into the device on every Read Operations rising edge of the input clocks (K and K). The CY7C1565KV18 is organized internally as four arrays of When deselected, the write port ignores all inputs after the 512K × 36. Accesses are completed in a burst of four sequential pending write operations have been completed. 36-bit data words. Read operations are initiated by asserting Byte Write Operations RPSactive at the rising edge of the positive input clock (K). The address presented to the address inputs is stored in the read Byte write operations are supported by the CY7C1565KV18. A address register. Following the next two K clock rise, the corre- write operation is initiated as described in the Write Operations sponding lowest order 36-bit word of data is driven onto the section. The bytes that are written are determined by BWS , 0 Q using K as the output timing reference. On the subse- BWS , BWS , and BWS which are sampled with each set of [35:0] 1 2 3 quent rising edge of K, the next 36-bit data word is driven onto 36-bit data words. Asserting the appropriate Byte Write Select the Q . This process continues until all four 36-bit data words input during the data portion of a write latches the data being [35:0] have been driven out onto Q . The requested data is valid presented and writes it into the device. Deasserting the Byte [35:0] 0.45 ns from the rising edge of the input clock (K or K). To Write Select input during the data portion of a write enables the maintain the internal logic, each read access must be allowed to data stored in the device for that byte to remain unaltered. This complete. Each read access consists of four 36-bit data words feature can be used to simplify read, modify, or write operations and takes two clock cycles to complete. Therefore, read to a byte write operation. Document Number: 001-15878 Rev. *S Page 6 of 30

CY7C1565KV18 Concurrent Transactions of ±15% is between 175  and 350 , with VDDQ=1.5 V. The output impedance is adjusted every 1024 cycles upon power-up The read and write ports on the CY7C1565KV18 operates to account for drifts in supply voltage and temperature. completely independently of one another. As each port latches the address inputs on different clock edges, the user can read or Echo Clocks write to any location, regardless of the transaction on the other port. If the ports access the same location when a read follows a Echo clocks are provided on the QDR II+ to simplify data capture write in successive clock cycles, the SRAM delivers the most on high-speed systems. Two echo clocks are generated by the recent information associated with the specified address QDR II+. CQ is referenced with respect to K and CQ is refer- location. This includes forwarding data from a write cycle that enced with respect to K. These are free running clocks and are was initiated on the previous K clock rise. synchronized to the input clock of the QDR II+. The timing for the echo clocks is shown in Switching Characteristics on page 23. Read access and write access must be scheduled such that one transaction is initiated on any clock cycle. If both ports are Valid Data Indicator (QVLD) selected on the same K clock rise, the arbitration depends on the previous state of the SRAM. If both ports are deselected, the QVLD is provided on the QDR II+ to simplify data capture on high read port takes priority. If a read was initiated on the previous speed systems. The QVLD is generated by the QDR II+ device cycle, the write port takes priority (as read operations cannot be along with data output. This signal is also edge-aligned with the initiated on consecutive cycles). If a write was initiated on the echo clock and follows the timing of any data pin. This signal is previous cycle, the read port takes priority (as write operations asserted half a cycle before valid data arrives. can not be initiated on consecutive cycles). Therefore, asserting PLL both port selects active from a deselected state results in alter- nating read or write operations being initiated, with the first These chips use a PLL that is designed to function between access being a read. 120MHz and the specified maximum clock frequency. During power-up, when the DOFF is tied HIGH, the PLL is locked after Depth Expansion 20 s of stable clock. The PLL can also be reset by slowing or The CY7C1565KV18 has a port select input for each port. This stopping the input clocks K and K for a minimum of 30ns. enables for easy depth expansion. Both port selects are sampled However, it is not necessary to reset the PLL to lock to the on the rising edge of the positive input clock only (K). Each port desired frequency. The PLL automatically locks 20 s after a select input can deselect the specified port. Deselecting a port stable clock is presented. The PLL may be disabled by applying does not affect the other port. All pending transactions (read and ground to the DOFF pin. When the PLL is turned off, the device write) are completed before the device is deselected. behaves in QDR I mode (with one cycle latency and a longer access time). For information, refer to the application note, PLL Programmable Impedance Considerations in QDRII/DDRII/QDRII+/DDRII+. An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V to allow the SRAM to adjust its output SS driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM, the allowable range of RQ to guarantee impedance matching with a tolerance Document Number: 001-15878 Rev. *S Page 7 of 30

CY7C1565KV18 Application Example Figure2 shows two QDR II+ used in an application. Figure 2. Application Example (Width Expansion) ZQ ZQ SRAM#1 SRAM#2 CQ/CQ CQ/CQ RQ RQ D[x:0] D[x:0] Q[x:0] Q[x:0] A RPS WPS BWS K K A RPS WPS BWS K K DATA IN[2x:0] DATA OUT [2x:0] ADDRESS RPS WPS BWS CLKIN1/CLKIN1 CLKIN2/CLKIN2 SOURCE K SOURCE K FPGA / ASIC Document Number: 001-15878 Rev. *S Page 8 of 30

CY7C1565KV18 Truth Table The truth table for CY7C1565KV18 follows. [3, 4, 5, 6, 7, 8] Operation K RPS WPS DQ DQ DQ DQ Write cycle: L–H H [9] L [10] D(A) at K(t + 1) D(A + 1) at K(t + 1) D(A + 2) at K(t + 2) D(A + 3) at K(t + 2) Load address on the rising edge of K; input write data on two consecutive K and K rising edges. Read cycle: L–H L [10] × Q(A) at K(t + 2) Q(A + 1) at K(t + 3) Q(A + 2) at K(t + 3) Q(A + 3) at K(t + 4) (2.5 cycle Latency) Load address on the rising edge of K; wait two and half cycles; read data on two consecutive K and K rising edges. NOP: No operation L–H H H D = X D = X D = X D = X Q = High Z Q = High Z Q = High Z Q = High Z Standby: Clock stopped Stopped X X Previous state Previous state Previous state Previous State Notes 3. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge. 4. Device powers up deselected with the outputs in a tri-state condition. 5. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst. 6. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle. 7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well. 8. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 9. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation. 10.This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the second read or write request. Document Number: 001-15878 Rev. *S Page 9 of 30

CY7C1565KV18 Write Cycle Descriptions The write cycle description table for CY7C1565KV18 follows. [11, 12] BWS BWS BWS BWS K K Comments 0 1 2 3 L L L L L–H – During the data portion of a write sequence, all four bytes (D ) are written into [35:0] the device. L L L L – L–H During the data portion of a write sequence, all four bytes (D ) are written into [35:0] the device. L H H H L–H – During the data portion of a write sequence, only the lower byte (D ) is written [8:0] into the device. D remains unaltered. [35:9] L H H H – L–H During the data portion of a write sequence, only the lower byte (D ) is written [8:0] into the device. D remains unaltered. [35:9] H L H H L–H – During the data portion of a write sequence, only the byte (D ) is written into [17:9] the device. D and D remains unaltered. [8:0] [35:18] H L H H – L–H During the data portion of a write sequence, only the byte (D ) is written into [17:9] the device. D and D remains unaltered. [8:0] [35:18] H H L H L–H – During the data portion of a write sequence, only the byte (D ) is written into [26:18] the device. D and D remains unaltered. [17:0] [35:27] H H L H – L–H During the data portion of a write sequence, only the byte (D ) is written into [26:18] the device. D and D remains unaltered. [17:0] [35:27] H H H L L–H – During the data portion of a write sequence, only the byte (D ) is written into [35:27] the device. D remains unaltered. [26:0] H H H L – L–H During the data portion of a write sequence, only the byte (D ) is written into [35:27] the device. D remains unaltered. [26:0] H H H H L–H – No data is written into the device during this portion of a write operation. H H H H – L–H No data is written into the device during this portion of a write operation. Notes 11.X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge. 12.Is based on a write cycle that was initiated in accordance with Write Cycle Descriptions. BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-15878 Rev. *S Page 10 of 30

CY7C1565KV18 IEEE 1149.1 Serial Boundary Scan (JTAG) Instruction Register Three-bit instructions can be serially loaded into the instruction These SRAMs incorporate a serial boundary scan Test Access register. This register is loaded when it is placed between the TDI Port (TAP) in the FBGA package. This part is fully compliant with and TDO pins, as shown in TAP Controller Block Diagram on IEEE Standard #1149.1-2001. The TAP operates using JEDEC page 14. Upon power-up, the instruction register is loaded with standard 1.8 V I/O logic levels. the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state, as described Disabling the JTAG Feature in the previous section. It is possible to operate the SRAM without using the JTAG When the TAP controller is in the Capture-IR state, the two least feature. To disable the TAP controller, TCK must be tied LOW significant bits are loaded with a binary “01” pattern to allow for (V ) to prevent clocking of the device. TDI and TMS are SS fault isolation of the board level serial test path. internally pulled up and may be unconnected. They may alternatively be connected to VDD through a pull-up resistor. TDO Bypass Register must be left unconnected. Upon power-up, the device comes up To save time when serially shifting data through registers, it is in a reset state, which does not interfere with the operation of the sometimes advantageous to skip certain chips. The bypass device. register is a single-bit register that can be placed between TDI Test Access Port and TDO pins. This enables shifting of data through the SRAM with minimal delay. The bypass register is set LOW (V ) when SS Test Clock the BYPASS instruction is executed. The test clock is used only with the TAP controller. All inputs are Boundary Scan Register captured on the rising edge of TCK. All outputs are driven from The boundary scan register is connected to all of the input and the falling edge of TCK. output pins on the SRAM. Several No Connect (NC) pins are also Test Mode Select (TMS) included in the scan register to reserve pins for higher density devices. The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left The boundary scan register is loaded with the contents of the unconnected if the TAP is not used. The pin is pulled up inter- RAM input and output ring when the TAP controller is in the nally, resulting in a logic HIGH level. Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The Test Data-In (TDI) EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the input and output ring. The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The The section Boundary Scan Order on page 18 shows the order register between TDI and TDO is chosen by the instruction that in which the bits are connected. Each bit corresponds to one of is loaded into the TAP instruction register. For information on the bumps on the SRAM package. The MSB of the register is loading the instruction register, see TAP Controller State connected to TDI, and the LSB is connected to TDO. Diagram on page 13. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is Identification (ID) Register connected to the most significant bit (MSB) on any register. The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is Test Data-Out (TDO) loaded in the instruction register. The IDCODE is hardwired into The TDO output pin is used to serially clock data out from the the SRAM and can be shifted out when the TAP controller is in registers. The output is active, depending upon the current state the Shift-DR state. The ID register has a vendor code and other of the TAP state machine (see Instruction Codes on page 17). information described in Identification Register Definitions on The output changes on the falling edge of TCK. TDO is page 17. connected to the least significant bit (LSB) of any register. TAP Instruction Set Performing a TAP Reset Eight different instructions are possible with the three-bit A Reset is performed by forcing TMS HIGH (VDD) for five rising instruction register. All combinations are listed in Instruction edges of TCK. This Reset does not affect the operation of the Codes on page 17. Three of these instructions are listed as SRAM and can be performed while the SRAM is operating. At RESERVED and must not be used. The other five instructions power-up, the TAP is reset internally to ensure that TDO comes are described in this section in detail. up in a High Z state. Instructions are loaded into the TAP controller during the Shift-IR TAP Registers state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the Registers are connected between the TDI and TDO pins to scan instruction register through the TDI and TDO pins. To execute the data in and out of the SRAM test circuitry. Only one register the instruction after it is shifted in, the TAP controller must be can be selected at a time through the instruction registers. Data moved into the Update-IR state. is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 001-15878 Rev. *S Page 11 of 30

CY7C1565KV18 IDCODE PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection The IDCODE instruction loads a vendor-specific, 32-bit code into of another boundary scan test operation. the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the The shifting of data for the SAMPLE and PRELOAD phases can device when the TAP controller enters the Shift-DR state. The occur concurrently when required, that is, while the data IDCODE instruction is loaded into the instruction register at captured is shifted out, the preloaded data can be shifted in. power-up or whenever the TAP controller is supplied a Test-Logic-Reset state. BYPASS When the BYPASS instruction is loaded in the instruction register SAMPLE Z and the TAP is placed in a Shift-DR state, the bypass register is The SAMPLE Z instruction connects the boundary scan register placed between the TDI and TDO pins. The advantage of the between the TDI and TDO pins when the TAP controller is in a BYPASS instruction is that it shortens the boundary scan path Shift-DR state. The SAMPLE Z command puts the output bus when multiple devices are connected together on a board. into a High Z state until the next command is supplied during the Update IR state. EXTEST The EXTEST instruction drives the preloaded data out through SAMPLE/PRELOAD the system output pins. This instruction also connects the SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When boundary scan register for serial access between the TDI and the SAMPLE/PRELOAD instructions are loaded into the TDO in the Shift-DR controller state. instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the input and output pins is captured EXTEST OUTPUT BUS TRI-STATE in the boundary scan register. IEEE Standard 1149.1 mandates that the TAP controller be able The TAP controller clock can only operate at a frequency up to to put the output bus into a tri-state mode. 20 MHz, while the SRAM clock operates more than an order of The boundary scan register has a special bit located at bit #108. magnitude faster. Because there is a large difference in the clock When this scan cell, called the “extest output bus tri-state,” is frequencies, it is possible that during the Capture-DR state, an latched into the preload register during the Update-DR state in input or output undergoes a transition. The TAP may then try to the TAP controller, it directly controls the state of the output capture a signal while in transition (metastable state). This does (Q-bus) pins, when the EXTEST is entered as the current not harm the device, but there is no guarantee as to the value instruction. When HIGH, it enables the output buffers to drive the that is captured. Repeatable results may not be possible. output bus. When LOW, this bit places the output bus into a To guarantee that the boundary scan register captures the HighZ condition. correct value of a signal, the SRAM signal must be stabilized This bit can be set by entering the SAMPLE/PRELOAD or long enough to meet the TAP controller's capture setup plus hold EXTEST command, and then shifting the desired bit into that cell, times (tCS and tCH). The SRAM clock input might not be captured during the Shift-DR state. During Update-DR, the value loaded correctly if there is no way in a design to stop (or slow) the clock into that shift-register cell latches into the preload register. When during a SAMPLE/PRELOAD instruction. If this is an issue, it is the EXTEST instruction is entered, this bit directly controls the still possible to capture all other signals and simply ignore the output Q-bus pins. Note that this bit is preset HIGH to enable the value of the CK and CK captured in the boundary scan register. output when the device is powered up, and also when the TAP After the data is captured, it is possible to shift out the data by controller is in the Test-Logic-Reset state. putting the TAP into the Shift-DR state. This places the boundary Reserved scan register between the TDI and TDO pins. These instructions are not implemented but are reserved for future use. Do not use these instructions. Document Number: 001-15878 Rev. *S Page 12 of 30

CY7C1565KV18 TAP Controller State Diagram The state diagram for the TAP controller follows. [13] TEST-LOGIC 1 RESET 0 1 TEST-LOGIC/ 1 SELECT 1 SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 0 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 PAUSE-DR 0 PAUSE-IR 0 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR UPDATE-IR 1 1 0 0 Note 13.The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-15878 Rev. *S Page 13 of 30

CY7C1565KV18 TAP Controller Block Diagram 0 Bypass Register 2 1 0 TDI Selection Instruction Register Selection TDO Circuitry Circuitry 31 30 29 . . 2 1 0 Identification Register 108 . . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range Parameter [14, 15, 16] Description Test Conditions Min Max Unit V Output HIGH voltage I =2.0 mA 1.4 – V OH1 OH V Output HIGH voltage I =100 A 1.6 – V OH2 OH V Output LOW voltage I = 2.0 mA – 0.4 V OL1 OL V Output LOW voltage I = 100 A – 0.2 V OL2 OL V Input HIGH voltage 0.65 × V V + 0.3 V IH DD DD V Input LOW voltage –0.3 0.35 × V V IL DD I Input and output load current GND  V  V –5 5 A X I DD Notes 14.These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics on page 20. 15.Overshoot: VIH(AC) < VDDQ + 0.35V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tCYC/2). 16.All Voltage referenced to Ground. Document Number: 001-15878 Rev. *S Page 14 of 30

CY7C1565KV18 TAP AC Switching Characteristics Over the Operating Range Parameter [17, 18] Description Min Max Unit t TCK clock cycle time 50 – ns TCYC t TCK clock frequency – 20 MHz TF t TCK clock HIGH 20 – ns TH t TCK clock LOW 20 – ns TL Setup Times t TMS setup to TCK clock rise 5 – ns TMSS t TDI setup to TCK clock rise 5 – ns TDIS t Capture setup to TCK rise 5 – ns CS Hold Times t TMS hold after TCK clock rise 5 – ns TMSH t TDI hold after clock rise 5 – ns TDIH t Capture hold after clock rise 5 – ns CH Output Times t TCK clock LOW to TDO valid – 10 ns TDOV t TCK clock LOW to TDO invalid 0 – ns TDOX Notes 17.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 18.Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns. Document Number: 001-15878 Rev. *S Page 15 of 30

CY7C1565KV18 TAP Timing and Test Conditions Figure3 shows the TAP timing and test conditions. [19] Figure 3. TAP Timing and Test Conditions 0.9 V ALL INPUT PULSES 1.8 V 50 0.9 V TDO 0 V Z0= 50 CL= 20 pF (a) GND tTH tTL Test Clock TCK t TCYC t TMSH t TMSS Test Mode Select TMS t TDIS t TDIH Test Data In TDI Test Data Out TDO tTDOV tTDOX Note 19.Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns. Document Number: 001-15878 Rev. *S Page 16 of 30

CY7C1565KV18 Identification Register Definitions Value Instruction Field Description CY7C1565KV18 Revision number (31:29) 000 Version number. Cypress device ID (28:12) 11010010001100100 Defines the type of SRAM. Cypress JEDEC ID (11:1) 00000110100 Allows unique identification of SRAM vendor. ID register presence (0) 1 Indicates the presence of an ID register. Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary scan 109 Instruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the input and output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the input and output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-15878 Rev. *S Page 17 of 30

CY7C1565KV18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F 60 5C 88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43 11C 71 1D 99 2N 16 9N 44 9B 72 2C 100 2P 17 11L 45 10B 73 3E 101 1P 18 11M 46 11A 74 2D 102 3R 19 9L 47 10A 75 2E 103 4R 20 10L 48 9A 76 1E 104 4P 21 11K 49 8B 77 2F 105 5P 22 10K 50 7C 78 3F 106 5N 23 9J 51 6C 79 1G 107 5R 24 9K 52 8A 80 1F 108 Internal 25 10J 53 7A 81 3G 26 11J 54 7B 82 2G 27 11H 55 6B 83 1H Document Number: 001-15878 Rev. *S Page 18 of 30

CY7C1565KV18 Power-Up Sequence in QDR II+ SRAM PLL Constraints ■PLL uses K clock as its synchronizing input. The input must QDR II+ SRAMs must be powered up and initialized in a have low phase jitter, which is specified as t . predefined manner to prevent undefined operations. KC Var ■The PLL functions at frequencies down to 120 MHz. Power-Up Sequence ■If the input clock is unstable and the PLL is enabled, then the ■Apply power and drive DOFF either HIGH or LOW (All other PLL may lock onto an incorrect frequency, causing unstable inputs can be HIGH or LOW). SRAM behavior. To avoid this, provide 20 s of stable clock to ❐Apply VDD before VDDQ. relock to the desired clock frequency. ❐Apply V before V or at the same time as V . DDQ REF REF ❐Drive DOFF HIGH. ■Provide stable DOFF (HIGH), power and clock (K, K) for 20 s to lock the PLL. Figure 4. Power-Up Waveforms ~~ K K ~~ Unstable Clock > 20μs Stable clock Start Normal Operation Clock Start (Clock Starts after V D D / V D D Q Stable) VDD/VDDQ VDD/ VDDQ Stable (< +/- 0.1V DC per 50ns ) Fix HIGH (or tie to V ) DDQ DOFF Document Number: 001-15878 Rev. *S Page 19 of 30

CY7C1565KV18 Maximum Ratings Operating Range Exceeding maximum ratings may shorten the useful life of the Range Ambient V [21] V [21] device. User guidelines are not tested. Temperature (TA) DD DDQ Storage temperature ................................–65 °C to +150 °C Commercial 0 °C to +70 °C 1.8 ± 0.1 V 1.4 V to V Ambient temperature Industrial –40 °C to +85 °C DD with power applied ...................................–55 °C to +125 °C Supply voltage on V relative to GND .......–0.5 V to +2.9 V DD Neutron Soft Error Immunity Supply voltage on V relative to GND ......–0.5 V to +V DDQ DD DC applied to outputs in High Z ........–0.5 V to VDDQ + 0.3 V Parameter Description ConTdeistito ns Typ Max* Unit DC input voltage [20] ...........................–0.5 V to V + 0.3 V DD LSBU Logical 25 °C 197 216 FIT/ Current into outputs (LOW) ........................................20 mA single-bit Mb upsets Static discharge voltage (MIL-STD-883, M. 3015) ....................................... > 2,001V LMBU Logical 25 °C 0 0.01 FIT/ multi-bit Mb Latch up current .................................................... > 200 mA upsets SEL Single-event 85 °C 0 0.1 FIT/ latch up Dev * No LMBU or SEL events occurred during testing; this column represents a statistical 2, 95% confidence limit calculation. For more details refer to Application Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates” Electrical Characteristics Over the Operating Range DC Electrical Characteristics Over the Operating Range Parameter [22] Description Test Conditions Min Typ Max Unit V Power supply voltage 1.7 1.8 1.9 V DD V I/O supply voltage 1.4 1.5 V V DDQ DD V Output HIGH voltage Note 23 V /2 – 0.12 – V /2 + 0.12 V OH DDQ DDQ V Output LOW voltage Note 24 V /2 – 0.12 – V /2 + 0.12 V OL DDQ DDQ V Output HIGH voltage I =0.1 mA, nominal impedance V – 0.2 – V V OH(LOW) OH DDQ DDQ V Output LOW voltage I = 0.1 mA, nominal impedance V – 0.2 V OL(LOW) OL SS V Input HIGH voltage V + 0.1 – V + 0.15 V IH REF DDQ V Input LOW voltage –0.15 – V – 0.1 V IL REF I Input leakage current GND  V  V 2 – 2 A X I DDQ I Output leakage current GND  V  V output disabled 2 – 2 A OZ I DDQ, V Input reference voltage [25] Typical Value = 0.75V 0.68 0.75 0.95 V REF IDD [26] VDD operating supply VDD = Max, 550 MHz (× 36) – – 1310 mA I = 0 mA, OUT 500 MHz (× 36) – – 1210 mA f = f = 1/t MAX CYC 450 MHz (× 36) – – 1100 mA 400 MHz (× 36) – – 1000 mA Notes 20.Overshoot: VIH(AC) < VDDQ + 0.35 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tCYC/2). 21.Power-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 22.All Voltage referenced to Ground. 23.Output are impedance controlled. IOH = (VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms. 24.Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms. 25.VREF (min) = 0.68V or 0.46VDDQ, whichever is larger, VREF (max) = 0.95V or 0.54VDDQ, whichever is smaller. 26.The operation current is calculated with 50% read cycle and 50% write cycle. Document Number: 001-15878 Rev. *S Page 20 of 30

CY7C1565KV18 Electrical Characteristics (continued) Over the Operating Range DC Electrical Characteristics (continued) Over the Operating Range Parameter [22] Description Test Conditions Min Typ Max Unit I Automatic power-down Max V , 550 MHz (× 36) – – 380 mA SB1 DD current Both Ports Deselected, 500 MHz (× 36) – – 360 mA V  V or V  V IN IH IN IL f = f = 1/t , 450 MHz (× 36) – – 340 mA MAX CYC Inputs Static 400 MHz (× 36) – – 320 mA AC Electrical Characteristics Over the Operating Range Parameter [27] Description Test Conditions Min Typ Max Unit V Input HIGH voltage V + 0.2 – V + 0.24 V IH REF DDQ V Input LOW voltage –0.24 – V – 0.2 V IL REF Capacitance Parameter [28] Description Test Conditions Max Unit C Input capacitance T = 25 C, f = 1 MHz, V = 1.8 V, V = 1.5 V 4 pF IN A DD DDQ C Output capacitance 4 pF O Thermal Resistance Parameter [28] Description Test Conditions 165-ball FBGA Unit Package  (0 m/s) Thermal resistance Socketed on a 170 × 220 × 2.35 mm, eight-layer printed 14.43 °C/W JA (junction to ambient) circuit board  (1 m/s) 13.40 °C/W JA  (3 m/s) 12.66 °C/W JA  Thermal resistance 11.38 °C/W JB (junction to board)  Thermal resistance 3.30 °C/W JC (junction to case) Notes 27.Overshoot: VIH(AC) < VDDQ + 0.35 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tCYC/2). 28.Tested initially and after any design or process change that may affect these parameters. Document Number: 001-15878 Rev. *S Page 21 of 30

CY7C1565KV18 AC Test Loads and Waveforms Figure 5. AC Test Loads and Waveforms V = 0.75 V REF V 0.75 V REF OUTPUT VREF 0.75V R = 50  [29] ALL INPUT PULSES Device Z0= 50  R = 50  OUTPUT 1.25V L Under Device 0.75 V Test Under 5pF 0.25 V VREF = 0.75 V Test ZQ Slew Rate = 2 V/ns ZQ RQ = RQ = 250  250  (a) INCLUDING JIG AND (b) SCOPE Note 29.Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75V, RQ = 250 , VDDQ = 1.5 V, input pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure5. Document Number: 001-15878 Rev. *S Page 22 of 30

CY7C1565KV18 Switching Characteristics Over the Operating Range [29, 30] Cypress Consortium 550 MHz 500 MHz 450 MHz 400 MHz Description Unit Parameter Parameter Min Max Min Max Min Max Min Max t V (typical) to the first access [31] 1 – 1 – 1 – 1 – ms POWER DD t t K clock cycle time 1.81 8.4 2.0 8.4 2.2 8.4 2.5 8.4 ns CYC KHKH tKH tKHKL Input clock (K/K) HIGH 0.4 – 0.4 – 0.4 – 0.4 – ns tKL tKLKH Input clock (K/K) LOW 0.4 – 0.4 – 0.4 – 0.4 – ns tKHKH tKHKH K clock rise to K clock rise (rising edge to rising 0.77 – 0.85 – 0.94 – 1.06 – ns edge) Setup Times t t Address setup to K clock rise 0.23 – 0.25 – 0.275 – 0.4 – ns SA AVKH tSC tIVKH Control setup to K clock rise (RPS, WPS) 0.23 – 0.25 – 0.275 – 0.4 – ns t t Double data rate control setup to clock (K/K) rise 0.18 – 0.20 – 0.22 – 0.28 – ns SCDDR IVKH (BWS , BWS ,BWS , BWS ) 0 1 2 3 tSD tDVKH D[X:0] setup to clock (K/K) rise 0.18 – 0.20 – 0.22 – 0.28 – ns Hold Times tHA tKHAX Address hold after K clock rise 0.23 – 0.25 – 0.275 – 0.4 – ns t t Control hold after K clock rise (RPS, WPS) 0.23 – 0.25 – 0.275 – 0.4 – ns HC KHIX t t Double data rate control hold after clock (K/K) 0.18 – 0.20 – 0.28 – 0.28 – ns HCDDR KHIX rise (BWS , BWS , BWS , BWS ) 0 1 2 3 tHD tKHDX D[X:0] hold after clock (K/K) rise 0.18 – 0.20 – 0.28 – 0.28 – ns Output Times tCO tCHQV K/K clock rise to data valid – 0.45 – 0.45 – 0.45 – 0.45 ns tDOH tCHQX Data output hold after output K/K clock rise –0.45 – –0.45 – –0.45 – –0.45 – ns (active to active) tCCQO tCHCQV K/K clock rise to echo clock valid – 0.45 – 0.45 – 0.45 – 0.45 ns tCQOH tCHCQX Echo clock hold after K/K clock rise –0.45 – –0.45 – –0.45 – –0.45 – ns t t Echo clock high to data valid 0.15 0.15 0.15 0.20 ns CQD CQHQV t t Echo clock high to data invalid –0.15 – –0.15 – –0.15 – –0.20 – ns CQDOH CQHQX t t Output clock (CQ/CQ) HIGH [32] 0.655 – 0.75 – 0.85 – 1.0 – ns CQH CQHCQL t t CQ clock rise to CQ clock rise 0.655 – 0.75 – 0.85 – 1.0 – ns CQHCQH CQHCQH [32] (rising edge to rising edge) tCHZ tCHQZ Clock (K/K) rise to high Z (active to High Z) [33, 34] – 0.45 – 0.45 – 0.45 – 0.45 ns tCLZ tCHQX1 Clock (K/K) rise to Low Z [33, 34] –0.45 – –0.45 – –0.45 – –0.45 – ns t t Echo clock high to QVLD Valid [35] –0.15 0.15 –0.15 0.15 –0.15 0.15 –0.20 0.20 ns QVLD CQHQVLD PLL Timing t t Clock phase jitter – 0.15 – 0.15 – 0.15 – 0.20 ns KC Var KC Var t t PLL lock time (K) 20 – 20 – 20 – 20 – s KC lock KC lock t t K static to PLL reset [36] 30 30 30 30 ns KC Reset KC Reset Notes 30.When a part with a maximum frequency above 400 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range. 31.This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD minimum initially before a read or write operation can be initiated. 32.These parameters are extrapolated from the input timing parameters (tCYC/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by design and are not tested in production. 33.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 22. Transition is measured ± 100 mV from steady-state voltage. 34.At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO. 35.tQVLD spec is applicable for both rising and falling edges of QVLD signal. 36.Hold to >VIH or <VIL. Document Number: 001-15878 Rev. *S Page 23 of 30

CY7C1565KV18 Switching Waveforms Read/Write/Deselect Sequence Figure 6. Waveform for 2.5 Cycle Read Latency [37, 38, 39] NOP READ WRITE READ WRITE NOP 1 2 3 4 5 6 7 8 K tKH tKL tCYC tKHKH K RPS tSC tHC tSC tHC WPS A A0 A1 A2 A3 t t tSA tHA HD HD tSD tSD D D10 D11 D12 D13 D30 D31 D32 D33 t QVLD t QVLD QVLD t DOH tCLZ tCO tCQD tCQDOH tCHZ Q Q00 Q01 Q02 Q03 Q20 Q21 Q22 Q23 (Read Latency = 2.5 Cycles) t t CCQO CQOH CQ t CCQO tCQH tCQHCQH tCQOH CQ DON’T CARE UNDEFINED Notes 37.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1. 38.Outputs are disabled (High Z) one clock cycle after a NOP. 39.In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, and Q23 = D13. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document Number: 001-15878 Rev. *S Page 24 of 30

CY7C1565KV18 Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed Package Operating Ordering Code Part and Package Type (MHz) Diagram Range 550 CY7C1565KV18-550BZXC 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free Commercial 500 CY7C1565KV18-500BZXC 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free Commercial CY7C1565KV18-500BZXI 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free Industrial 450 CY7C1565KV18-450BZXC 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free Commercial CY7C1565KV18-450BZI 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Industrial 400 CY7C1565KV18-400BZXC 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free Commercial CY7C1565KV18-400BZI 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Industrial CY7C1565KV18-400BZXI 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free Ordering Code Definitions CY 7 C 1565 K V18 - XXX BZ X X Temperature Range: X = C or I C = Commercial; I = Industrial Pb-free Package Type: BZ = 165-ball FBGA Frequency Range: XXX = 550 MHz or 500 MHz or 450 MHz or 400 MHz V18 = 1.8 V Die Revision Part Identifier Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-15878 Rev. *S Page 25 of 30

CY7C1565KV18 Package Diagram Figure 7. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180 51-85180 *G Document Number: 001-15878 Rev. *S Page 26 of 30

CY7C1565KV18 Acronyms Document Conventions Acronym Description Units of Measure DDR Double Data Rate Symbol Unit of Measure FBGA Fine-Pitch Ball Grid Array °C degree Celsius HSTL High-Speed Transceiver Logic MHz megahertz JEDEC Joint Electron Device Engineering Council µA microampere JTAG Joint Test Action Group µs microsecond ODT On-Die Termination mA milliampere PLL Phase-Locked Loop mm millimeter QDR Quad Data Rate ms millisecond TAP Test Access Port ns nanosecond TCK Test Clock  ohm TDI Test Data In % percent TDO Test Data Out pF picofarad TMS Test Mode Select V volt W watt Document Number: 001-15878 Rev. *S Page 27 of 30

CY7C1565KV18 Document History Page Document Title: CY7C1565KV18, 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Document Number: 001-15878 Orig. of Submission Revision ECN Description of Change Change Date ** 1120252 VKN 06/01/07 New data sheet. *A 1246904 VKN / AESA See ECN Added 550 MHz and 500 MHz speed bins related information in all instances across the document. Removed 375 MHz, 333 MHz, and 300 MHz speed bins related information in all instances across the document. Updated Pin Configuration: Added Note 2 and referred the same note in description below heading. *B 1739283 VKN / AESA See ECN Changed status from Advance Information to Preliminary. *C 2065806 VKN / AESA See ECN Updated Electrical Characteristics: Added Note 26 and referred the same note in I parameter. DD Updated Switching Characteristics: Updated Note 32 (Corrected typo). Changed minimum value of PLL Lock Time (K) from 2048 cycles to 20 s. *D 2612383 VKN / AESA 11/25/08 Updated Identification Register Definitions: Changed Revision Number (31:29) from 001 to 000. Updated Power-Up Sequence in QDR II+ SRAM: Updated description. Updated Figure4. Updated Thermal Resistance: Included values. Updated Package Diagram: Removed spec 51-85195 *A. Added spec 51-85180 *A. Updated to new template. *E 2683451 VKN / PYRS 04/03/09 Updated Ordering Information: No change in part numbers. Added disclaimer on top of the Ordering Information table. Post to external web. *F 2746858 VKN 07/31/09 Changed status from Preliminary to Final. Added Neutron Soft Error Immunity. Updated Switching Characteristics: Updated maximum value of t , t , t parameters to 0.45 ns for CO CCQO CHZ 550MHz, 500 MHz and 450 MHz speed bins. Updated minimum value of t , t , t parameters to –0.45 ns for DOH CQOH CLZ 550MHz, 500 MHz and 450 MHz bins Updated Ordering Information: Updated part numbers. Modified the disclaimer on top of the Ordering Information table. *G 2870201 NJY 02/01/10 Added Contents. Updated to new template. *H 2894069 NJY 03/17/10 Updated Ordering Information: Updated part numbers. *I 2931775 VKN 05/13/10 Updated Document Title. Removed CY7C1563KV18 parts related information in all instances across the document. Updated Capacitance: Changed Input Capacitance (C ) from 2 pF to 4 pF, and Output Capacitance IN (C ) from 3 pF to 4 pF, O Updated Ordering Information: Updated part numbers. Document Number: 001-15878 Rev. *S Page 28 of 30

CY7C1565KV18 Document History Page (continued) Document Title: CY7C1565KV18, 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Document Number: 001-15878 Orig. of Submission Revision ECN Description of Change Change Date *J 2981269 NJY 07/15/10 Added Pin Configuration and Pin Definitions sections that were missing in the previous revision. *K 3055013 NJY 10/12/10 Updated Ordering Information: Updated part numbers. *L 3216622 NJY 04/05/2011 Updated to new template. *M 3506265 PRIT 02/14/2012 Removed CY7C1561KV18 and CY7C1576KV18 parts related information in all instances across the document. Updated Ordering Information. Updated Package Diagram. *N 3862706 PRIT 01/09/2013 Updated Package Diagram: spec 51-85180 – Changed revision from *E to *F. *O 4371936 PRIT 05/06/2014 Updated Application Example: Updated Figure2. Updated Thermal Resistance: Updated values of  parameter. JA Included  parameter and its details. JB Updated to new template. *P 4567085 PRIT 11/11/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Updated Ordering Information: Updated part numbers. *Q 4675860 PRIT 03/04/2015 Updated Ordering Information: Updated part numbers. Completing Sunset Review. *R 5097330 PRIT 01/21/2016 Updated Ordering Information: Updated part numbers. Updated Package Diagram: spec 51-85180 – Changed revision from *F to *G. Updated to new template. Completing Sunset Review. *S 5980585 AESATMP9 11/30/2017 Updated logo and copyright. Document Number: 001-15878 Rev. *S Page 29 of 30

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