® CY62126EV30 MoBL 1-Mbit (64 K × 16) Static RAM 1-Mbit (64 K × 16) Static RAM Features Functional Description ■High speed: 45 ns The CY62126EV30 is a high performance CMOS static RAM organized as 64K words by 16 bits. This device features ■Temperature ranges advanced circuit design to provide ultra low active current. This ❐Industrial: –40 °C to +85 °C is ideal for providing More Battery Life(MoBL®) in portable ❐Automotive-A: –40 °C to +85 °C applications such as cellular telephones. The device also has an ❐Automotive-E: –40 °C to +125 °C automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the ■Wide voltage range: 2.2 V to 3.6 V device in standby mode reduces power consumption by more ■Pin compatible with CY62126DV30 than 99 percent when deselected (CE HIGH). The input and output pins (I/O through I/O ) are placed in a high impedance 0 15 ■Ultra low standby power state when the device is deselected (CE HIGH), the outputs are ❐Typical standby current: 1 A disabled (OE HIGH), both Byte High Enable and Byte Low ❐Maximum standby current: 4 A Enable are disabled (BHE, BLE HIGH) or during a write operation (CE LOW and WE LOW). ■Ultra low active power ❐Typical active current: 1.3 mA at f = 1 MHz To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data ■Easy memory expansion with CE and OE features from I/O pins (I/O through I/O ) is written into the location 0 7 specified on the address pins (A through A ). If Byte High ■Automatic power down when deselected 0 15 Enable (BHE) is LOW, then data from I/O pins (I/O through 8 ■Complementary metal oxide semiconductor (CMOS) for I/O ) is written into the location specified on the address pins 15 optimum speed and power (A through A ). 0 15 ■Offered in Pb-free 48-ball very fine-pitch ball grid array To read from the device, take Chip Enable (CE) and Output (VFBGA) and 44-pin thin small outline package (TSOP) II Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If packages Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O to I/O . If 0 7 Byte High Enable (BHE) is LOW, then data from memory appears on I/O to I/O . See the Truth Table on page 11 for a 8 15 complete description of read and write modes. For a complete list of related documentation, click here. Logic Block Diagram DATA IN DRIVERS A 10 A 9 A R 8 E S A7 D P A O 64K x 16 M 6 C A AA5 DE RAM Array SE I/O0–I/O7 4 W N AA3 RO SE I/O8–I/O15 2 A 1 A 0 COLUMN DECODER BHE WE A11A12 A13 A14A15 OCEE BLE CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 38-05486 Rev. *P Revised November 24, 2017

® CY62126EV30 MoBL Contents Pin Configuration .............................................................3 Ordering Information ......................................................12 Product Portfolio ..............................................................3 Ordering Code Definitions .........................................12 Maximum Ratings .............................................................4 Package Diagrams ..........................................................13 Operating Range ...............................................................4 Acronyms ........................................................................15 Electrical Characteristics .................................................4 Document Conventions .................................................15 Capacitance ......................................................................5 Units of Measure .......................................................15 Thermal Resistance ..........................................................5 Document History Page .................................................16 AC Test Loads and Waveforms .......................................5 Sales, Solutions, and Legal Information ......................18 Data Retention Characteristics .......................................6 Worldwide Sales and Design Support .......................18 Data Retention Waveform ................................................6 Products ....................................................................18 Switching Characteristics ................................................7 PSoC® Solutions ......................................................18 Switching Waveforms ......................................................8 Cypress Developer Community .................................18 Truth Table ......................................................................11 Technical Support .....................................................18 Document Number: 38-05486 Rev. *P Page 2 of 18

® CY62126EV30 MoBL Pin Configuration Figure 1. 48-ball VFBGA pinout (Top View) Figure 2. 44-pin TSOP II pinout (Top View) [1] 1 2 3 4 5 6 A4 1 44 A5 A3 2 43 A6 BLE OE A0 A1 A2 NC A A2 3 42 A7 A1 4 41 OE I/O8 BHE A3 A4 CE I/O0 B CAE0 56 4309 BBLHEE I/O0 7 38 I/O15 I/O9 I/O10 A5 A6 I/O1 I/O2 C I/O1 8 37 I/O14 I/O2 9 36 I/O13 VSS I/O11 NC A7 I/O3 Vcc D VI/COC3 1110 3354 VI/OSS12 VCC I/O12 NC NC I/O4 Vss E VI/SOS4 1123 3323 IV/OCC11 I/O5 14 31 I/O10 I/O14 I/O13 A14 A15 I/O5 I/O6 F II//OO76 1165 2390 II//OO89 WE 17 28 NC I/O15 NC A12 A13 WE I/O7 G A15 18 27 A8 A14 19 26 A9 NC A8 A9 A10 A11 NC H AA1123 2201 2254 AA1110 NC 22 23 NC Product Portfolio Power Dissipation Product Range VCC Range (V) Speed Operating, ICC (mA) Standby, ISB2 (ns) f = 1 MHz f = f (A) max Min Typ[2] Max Typ[2] Max Typ[2] Max Typ[2] Max CY62126EV30LL Industrial 2.2 3.0 3.6 45 1.3 2 11 16 1 4 CY62126EV30LL Automotive-A 2.2 3.0 3.6 45 1.3 2 11 16 1 4 CY62126EV30LL Automotive-E 2.2 3.0 3.6 55 1.3 4 11 35 1 30 Notes 1. NC pins are not connected on the die. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. Document Number: 38-05486 Rev. *P Page 3 of 18

® CY62126EV30 MoBL Maximum Ratings DC input voltage [3, 4] 0.3 V to 3.6 V (V + 0.3 V) CCmax Output current into outputs (LOW) .............................20 mA Exceeding maximum ratings may shorten the battery life of the Static discharge voltage device. These user guidelines are not tested. (MIL-STD-883, Method 3015) ................................ > 2001 V Storage temperature ................................–65 °C to +150 °C Latch up current .................................................... > 200 mA Ambient temperature with power applied ...................................–55 °C to +125 °C Operating Range Supply voltage to ground potential [3, 4] .....–0.3 V to 3.6 V (VCCmax + 0.3 V) Device Range Ambient V [5] Temperature CC DC voltage applied to outputs in High Z state [3, 4].............–0.3 V to 3.6 V (VCCmax + 0.3 V) CY62126EV30LL Industrial / –40 °C to +85 °C 2.2 V to Automotive-A 3.6 V Automotive-E –40 °C to +125 °C Electrical Characteristics Over the Operating Range 45 ns (Industrial / 55 ns (Automotive-E) Parameter Description Test Conditions Automotive-A) Unit Min Typ[6] Max Min Typ[6] Max V Output high voltage I = –0.1 mA 2.0 – – 2.0 – – V OH OH I = –1.0 mA, V > 2.70 V 2.4 – – 2.4 – – V OH CC V Output low voltage I = 0.1 mA – – 0.4 – 0.4 V OL OL I = 2.1 mA, V > 2.70 V – – 0.4 – – 0.4 V OL CC V Input high voltage V = 2.2 V to 2.7 V 1.8 – V + 0.3 1.8 – V + 0.3 V IH CC CC CC V = 2.7 V to 3.6 V 2.2 – V + 0.3 2.2 – V + 0.3 V CC CC CC V Input low voltage V = 2.2 V to 2.7 V –0.3 – 0.6 –0.3 – 0.6 V IL CC V = 2.7 V to 3.6 V –0.3 – 0.8 –0.3 – 0.8 V CC I Input leakage current GND < V < V –1 – +1 –4 – +4 A IX I CC I Output leakage current GND < V < V , Output –1 – +1 –4 – +4 A OZ O CC Disabled I V operating supply f = f = 1/t V = V – 11 16 – 11 35 mA CC CC max RC CC CCmax current I = 0 mA f = 1 MHz OUT – 1.3 2.0 – 1.3 4.0 CMOS levels I [7] Automatic CE power CE > V 0.2 V, – 1 4 – 1 35 A SB1 CC down current —CMOS V > V – 0.2 V, V < 0.2 V, IN CC IN inputs f = f (Address and Data Only), max f = 0 (OE, BHE, BLE and WE), V = 3.60 V CC I [7] Automatic CE power CE > V – 0.2 V, – 1 4 – 1 30 A SB2 CC down current —CMOS V > V – 0.2 V or V < 0.2 V, IN CC IN inputs f = 0, V = 3.60 V CC Notes 3. VIL(min) = –2.0 V for pulse durations less than 20 ns. 4. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 5. Full device AC operation assumes a 100 s ramp time from 0 to Vcc(min) and 200 s wait time after Vcc stabilization. 6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 7. Chip enable (CE) needs to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. Document Number: 38-05486 Rev. *P Page 4 of 18

® CY62126EV30 MoBL Capacitance Parameter [8] Description Test Conditions Max Unit C Input capacitance T = 25 °C, f = 1 MHz, V = V 10 pF IN A CC CC(typ) C Output capacitance 10 pF OUT Thermal Resistance Parameter [8] Description Test Conditions 48-ball VFBGA 44-pin TSOP II Unit Package Package  Thermal resistance Still Air, soldered on a 4.25 × 1.125 inch, 58.85 28.2 °C/W JA (junction to ambient) two-layer printed circuit board  Thermal resistance 17.01 3.4 °C/W JC (junction to case) AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms R1 V ALL INPUT PULSES CC OUTPUT VCC 90% 90% 10% 10% R2 GND 30 pF Rise Time = 1 V/ns Fall Time = 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT R TH OUTPUT V TH Parameters 2.2 V–2.7 V 2.7 V–3.6 V Unit R1 16600 1103  R2 15400 1554  R 8000 645  TH V 1.2 1.75 V TH Note 8. Tested initially and after any design or process changes that may affect these parameters. Document Number: 38-05486 Rev. *P Page 5 of 18

® CY62126EV30 MoBL Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ [9] Max Unit V V for data retention 1.5 – – V DR CC I [10] Data retention current V = V , Industrial / A CCDR CC DR – – 3 Automotive-A CE > V – 0.2 V, CC A VIN > VCC – 0.2 V or Automotive-E – – 30 V < 0.2 V IN t [11] Chip deselect to data retention 0 – – ns CDR time t [12] Operation recovery time CY62126EV30LL-45 45 – – ns R CY62126EV30LL-55 55 – – Data Retention Waveform Figure 4. Data Retention Waveform DATA RETENTION MODE V V VCC CC(min) VDR> 1.5 V CC(min) tCDR tR CE Notes 9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 10.Chip enable (CE) needs to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. 11.Tested initially and after any design or process changes that may affect these parameters. 12.Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s. Document Number: 38-05486 Rev. *P Page 6 of 18

® CY62126EV30 MoBL Switching Characteristics Over the Operating Range 45 ns (Industrial / 55 ns (Automotive-E) Parameter [13, 14] Description Automotive-A) Unit Min Max Min Max Read Cycle t Read cycle time 45 – 55 – ns RC t Address to data valid – 45 – 55 ns AA t Data hold from address change 10 – 10 – ns OHA t CE LOW to data valid – 45 – 55 ns ACE t OE LOW to data valid – 22 – 25 ns DOE t OE LOW to Low Z [15] 5 – 5 – ns LZOE t OE HIGH to High Z [15, 16] – 18 – 20 ns HZOE t CE LOW to Low Z [15] 10 – 10 – ns LZCE t CE HIGH to High Z [15, 16] – 18 – 20 ns HZCE t CE LOW to power up 0 – 0 – ns PU t CE HIGH to power down – 45 – 55 ns PD t BHE / BLE LOW to data valid – 22 – 25 ns DBE t BHE / BLE LOW to Low Z [15] 5 – 5 – ns LZBE t BHE / BLE HIGH to High Z [15, 16] – 18 – 20 ns HZBE Write Cycle [17, 18] t Write cycle time 45 – 55 – ns WC t CE LOW to write end 35 – 40 – ns SCE t Address setup to write end 35 – 40 – ns AW t Address hold from write end 0 – 0 – ns HA t Address setup to write start 0 – 0 – ns SA t WE pulse width 35 – 40 – ns PWE t BHE / BLE pulse width 35 – 40 – ns BW t Data setup to write end 25 – 25 – ns SD t Data hold from write end 0 – 0 – ns HD t WE LOW to High Z [15, 16] – 18 – 20 ns HZWE tLZWE WE HIGH to Low Z [15] 10 – 10 – ns Notes 13.Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance. 14.AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 15.At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 16.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 17.The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must refer to the edge of signal that terminates write. 18.The minimum write cycle pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to sum of tSD and tHZWE. Document Number: 38-05486 Rev. *P Page 7 of 18

® CY62126EV30 MoBL Switching Waveforms Figure 5. Read Cycle No. 1 (Address transition controlled) [19, 20] t RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 6. Read Cycle No. 2 (OE controlled) [20, 21] ADDRESS t RC CE tPD tACE tHZCE OE t t HZOE DOE tLZOE BHE/BLE tHZBE t DBE t LZBE HIGH HIGHI MPEDANCE IMPEDANCE DATA OUT DATA VALID tLZCE tPU I CC VCC 50% 50% SUPPLY ISB CURRENT Notes 19.The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL. 20.WE is high for read cycle. 21.Address valid before or similar to CE and BHE, BLE transition LOW. Document Number: 38-05486 Rev. *P Page 8 of 18

® CY62126EV30 MoBL Switching Waveforms (continued) Figure 7. Write Cycle No. 1 (WE controlled) [22, 23, 24] tWC ADDRESS t SCE CE tAW tHA tSA tPWE WE BHE/BLE tBW OE tSD tHD DATA I/O NOTE 25 DATAIN tHZOE Figure 8. Write Cycle No. 2 (CE controlled) [22, 23, 24] tWC ADDRESS tSCE CE t SA tAW tHA t WE PWE BHE/BLE tBW OE tSD tHD DATAI/O NOTE 25 DATAIN tHZOE Notes 22.The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must refer to the edge of signal that terminates write. 23.Data I/O is high impedance if OE = VIH. 24.If CE goes high simultaneously with WE = VIH, the output remains in a high impedance state. 25.During this period, the I/Os are in output state. Do not apply input signals. Document Number: 38-05486 Rev. *P Page 9 of 18

® CY62126EV30 MoBL Switching Waveforms (continued) Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW [26, 27] tWC ADDRESS tSCE CE BHE/BLE tBW tAW tHA tSA tPWE WE tHD tSD DATA I/O NOTE 28 DATA IN tHZWE tLZWE Figure 10. Write Cycle No. 4 (BHE/BLE controlled, OE LOW) [26] tWC ADDRESS CE tSCE tAW tHA t BW BHE/BLE tSA t WE PWE tHZWE tSD tHD DATA I/O NOTE 28 DATAIN tLZWE Notes 26.If CE goes high simultaneously with WE = VIH, the output remains in a high impedance state. 27.The minimum write cycle pulse width should be equal to sum of tSD and tHZWE. 28.During this period, the I/Os are in output state. Do not apply input signals. Document Number: 38-05486 Rev. *P Page 10 of 18

® CY62126EV30 MoBL Truth Table CE[29] WE OE BHE BLE Inputs/Outputs Mode Power H X X X X High Z Deselect/power down Standby (I ) SB L X X H H High Z Output disabled Active (I ) CC L H L L L Data out (I/O –I/O ) Read Active (I ) 0 15 CC L H L H L Data out (I/O –I/O ); Read Active (I ) 0 7 CC I/O –I/O in High Z 8 15 L H L L H Data out (I/O –I/O ); Read Active (I ) 8 15 CC I/O –I/O in High Z 0 7 L H H L L High Z Output disabled Active (I ) CC L H H H L High Z Output disabled Active (I ) CC L H H L H High Z Output disabled Active (I ) CC L L X L L Data in (I/O –I/O ) Write Active (I ) 0 15 CC L L X H L Data in (I/O –I/O ); Write Active (I ) 0 7 CC I/O –I/O in High Z 8 15 L L X L H Data in (I/O –I/O ); Write Active (I ) 8 15 CC I/O –I/O in High Z 0 7 Note 29.Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted. Document Number: 38-05486 Rev. *P Page 11 of 18

® CY62126EV30 MoBL Ordering Information Speed Package Operating Package Type (ns) Ordering Code Diagram Range 45 CY62126EV30LL-45BVXI 51-85150 48-ball VFBGA (Pb-free) Industrial CY62126EV30LL-45ZSXI 51-85087 44-pin TSOP II (Pb-free) Industrial CY62126EV30LL-45ZSXA 51-85087 44-pin TSOP II (Pb-free) Automotive-A 55 CY62126EV30LL-55BVXE 51-85150 48-ball VFBGA (Pb-free) Automotive-E CY62126EV30LL-55ZSXE 51-85087 44-pin TSOP II (Pb-free) Automotive-E Contact your local Cypress sales representative for availability of other parts. Ordering Code Definitions CY 621 2 6 E V30 LL - XX XX X X Temperature Range: X = I or A or E I = Industrial; A = Automotive-A; E = Automotive-E Pb-free Package Type: XX = BV or ZS BV = 48-ball VFBGA ZS = 44-pin TSOP II Speed Grade: XX = 45 ns or 55 ns LL = Low Power Voltage: V30 = 3 V Typical Process Technology: E = 90 nm Bus Width: 6 = × 16 Density: 2 = 1-Mbit Family Code: 621= MoBL SRAM family Company ID: CY = Cypress Document Number: 38-05486 Rev. *P Page 12 of 18

® CY62126EV30 MoBL Package Diagrams Figure 11. 48-ball VFBGA (6 × 8 × 1.0 mm) Package Outline, 51-85150 51-85150 *H Document Number: 38-05486 Rev. *P Page 13 of 18

® CY62126EV30 MoBL Package Diagrams (continued) Figure 12. 44-pin TSOP II Package Outline, 51-85087 51-85087 *E Document Number: 38-05486 Rev. *P Page 14 of 18

® CY62126EV30 MoBL Acronyms Document Conventions Units of Measure Acronym Description CE Chip Enable Symbol Unit of Measure CMOS Complementary Metal Oxide Semiconductor °C degree Celsius I/O Input/Output MHz megahertz OE Output Enable µA microampere µs microsecond RAM Random Access Memory mA milliampere SRAM Static Random Access Memory mm millimeter TSOP Thin Small Outline Package ns nanosecond VFBGA Very Fine-Pitch Ball Grid Array  ohm WE Write Enable % percent pF picofarad V volt W watt Document Number: 38-05486 Rev. *P Page 15 of 18

® CY62126EV30 MoBL Document History Page Document Title: CY62126EV30 MoBL®, 1-Mbit (64 K × 16) Static RAM Document Number: 38-05486 Submission Orig. of Rev. ECN No. Description of Change Date Change ** 202760 See ECN AJU New data sheet. *A 300835 See ECN SYT Converted from Advance Information to Preliminary Specified Typical standby power in the Features Section Changed E3 ball from DNU to NC in the Pin Configuration for the FBGA Package and removed the footnote associated with it on page #2 Changed t from 6 ns to 10 ns for both 35- and 45-ns speed bins, OHA respectively Changed t , t from 15 to 18 ns for 35-ns speed bin DOE SD Changed t , t , t from 12 and 15 ns to 15 and 18 ns for the 35ns HZOE HZBE HZWE and 45ns speed bins, respectively Changed t from 12 and 15 ns to 18 and 22 ns for the 35- and 45-ns speed HZCE bins, respectively Changed t ,t from 25 and 40 ns to 30 and 35 ns for the 35- and 45-ns SCE BW speed bins, respectively Changed t from 25 to 30 ns and 40 to 35 ns for 35 and 45-ns speed bins AW respectively Changed t from 35 and 45 ns to 18 and 22 ns for the 35 and 45 ns speed DBE bins respectively Removed footnote that read “BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE” on page # 4 Removed footnote that read “If both BHE and BLE are toggled together, then t LZBE is 10 ns” on page # 5 Added Pb-free package information *B 461631 See ECN NXR Converted from Preliminary to Final Removed 35 ns Speed Bin Removed “L” version of CY62126EV30 Changed I from 8 mA to 11 mA and I from 12 mA to 16 mA for CC (Typ) CC (max) f = f max Changed I from 1.5 mA to 2.0 mA for f = 1 MHz, I ,I from CC (max) SB1 SB2 (max) 1A to 4 A, I ,I from 0.5 A to 1 A, I from 1.5 A to SB1 SB2 (Typ) CCDR (max) 3A, AC Test load Capacitance value from 50 pF to 30 pF, t from 3 to LZOE 5ns, t from 6 to 10 ns, t from 22 to 18 ns, t from 6 to 5 ns, t LZCE HZCE LZBE PWE from 30 to 35 ns, t from 22 to 25 ns, t from 6 to 10 ns, and updated the SD LZWE Ordering Information table. *C 925501 See ECN VKN Added footnote #7 related to I andI SB2 CCDR Added footnote #11 related AC timing parameters *D 1045260 See ECN VKN Added Automotive information Updated Ordering Information table *E 2631771 01/07/09 NXR / PYRS Changed CE condition from X to L in Truth table for Output Disable mode Updated template *F 2944332 06/04/2010 VKN Added Contents Removed byte enable from footnote #2 in Electrical Characteristics Added footnote related to chip enable in Truth Table Updated Package Diagrams Updated links in Sales, Solutions, and Legal Information *G 2996166 07/29/2010 AJU Added CY62126EV30LL-45ZSXA part in Ordering Information. Added Ordering Code Definitions. Modified table footnote format. *H 3113864 12/17/2010 PRAS Updated Figure 1 and Package Diagram, and fixed Typo in Figure 3. Document Number: 38-05486 Rev. *P Page 16 of 18

® CY62126EV30 MoBL Document History Page (continued) Document Title: CY62126EV30 MoBL®, 1-Mbit (64 K × 16) Static RAM Document Number: 38-05486 Submission Orig. of Rev. ECN No. Description of Change Date Change *I 3270487 05/31/2011 RAME Updated Functional Description (Removed “For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.”). Updated Electrical Characteristics. Updated Data Retention Characteristics. Added Acronyms and Units of Measure. Updated to new template. *J 4205722 11/29/2013 MEMJ Updated Features: Added Automotive-A range information. Updated Product Portfolio: Added Automotive-A range information. Updated Operating Range: Segregated Automotive-A and Automotive-E ranges. Updated Electrical Characteristics: Added Automotive-A with Industrial for 45 ns speed bin. Renamed Automotive as Automotive-E for 55 ns speed bin. Updated Data Retention Characteristics: Segregated Automotive-A and Automotive-E in conditions for I CCDR parameter. Updated Switching Characteristics: Added Automotive-A with Industrial for 45 ns speed bin. Renamed Automotive as Automotive-E for 55 ns speed bin. Updated Package Diagrams: spec 51-85150 – Changed revision from *F to *H. spec 51-85087 – Changed revision from *C to *E. Updated to new template. *K 4211675 12/12/2013 MEMJ No technical updates. Removed the border lines in Package Diagram specs. *L 4410948 06/17/2014 VINI Updated Switching Characteristics: Added Note 18 and referred the same note in “Write Cycle”. Updated Switching Waveforms: Added Note 27 and referred the same note in Figure9. Completing Sunset Review. *M 4576475 11/21/2014 VINI Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. *N 4612072 01/05/2015 VINI Updated Maximum Ratings: Referred Notes 3, 4 in “Supply voltage to ground potential”. *O 4797476 06/15/2015 VINI Updated to new template. Completing Sunset Review. *P 5975641 11/24/2017 AESATMP9 Updated logo and Copyright. Document Number: 38-05486 Rev. *P Page 17 of 18

® CY62126EV30 MoBL Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC® Solutions ARM® Cortex® Microcontrollers cypress.com/arm PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Automotive cypress.com/automotive Cypress Developer Community Clocks & Buffers cypress.com/clocks Forums | WICED IOT Forums | Projects | Video | Blogs | Interface cypress.com/interface Training | Components Internet of Things cypress.com/iot Technical Support Memory cypress.com/memory cypress.com/support Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless Connectivity cypress.com/wireless © Cypress Semiconductor Corporation, 2004-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 38-05486 Rev. *P Revised November 24, 2017 Page 18 of 18

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