CD54HC4060, CD74HC4060, CD54HCT4060, CD74HCT4060 Data sheet acquired from Harris Semiconductor SCHS207G High-Speed CMOS Logic February 1998 - Revised October 2003 14-Stage Binary Counter with Oscillator Features thenegativetransitionofφI(andφO).Allinputsandoutputs are buffered. Schmitt trigger action on the input-pulse-line • Onboard Oscillator permits unlimited rise and fall times. [ /Title • Common Reset Inordertoachieveasymmetricalwaveformintheoscillator (CD74 sectiontheHCT4060inputpulseswitchpointsarethesame • Negative-Edge Clocking as in the HC4060; only the MR input in the HCT4060 has HC406 • Fanout (Over Temperature Range) TTL switching levels. 0, - Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads CD74 Ordering Information - Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads HCT40 • Wide Operating Temperature Range . . .-55oC to 125oC TEMP. RANGE 60) PART NUMBER (oC) PACKAGE • Balanced Propagation Delay and Transition Times /Sub- ject • Significant Power Reduction Compared to LSTTL CD54HC4060F3A -55 to 125 16 Ld CERDIP Logic ICs (High CD54HCT4060F3A -55 to 125 16 Ld CERDIP Speed • HC Types CD74HC4060E -55 to 125 16 Ld PDIP CMOS - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC CD74HC4060M -55 to 125 16 Ld SOIC at VCC = 5V CD74HC4060MT -55 to 125 16 Ld SOIC • HCT Types CD74HC4060M96 -55 to 125 16 Ld SOIC - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, CD74HC4060PW -55 to 125 16 Ld TSSOP VIL= 0.8V (Max), VIH = 2V (Min) CD74HC4060PWR -55 to 125 16 Ld TSSOP - CMOS Input Compatibility, Il≤1µA at VOL, VOH CD74HC4060PWT -55 to 125 16 Ld TSSOP Description CD74HCT4060E -55 to 125 16 Ld PDIP The ’HC4060 and ’HCT4060 each consist of an oscillator CD74HCT4060M -55 to 125 16 Ld SOIC section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal CD74HCT4060MT -55 to 125 16 Ld SOIC oscillator circuits. A Master Reset input is provided which CD74HCT4060M96 -55 to 125 16 Ld SOIC resets the counter to the all-0’s state and disables the oscillator.AhighlevelontheMRlineaccomplishesthereset NOTE: Whenordering,usetheentirepartnumber.Thesuffixes96 function. All counter stages are master-slave flip-flops. The andRdenotetapeandreel.ThesuffixTdenotesasmall-quantity stateofthecounterisadvancedonestepinbinaryorderon reel of 250. Pinout CD54HC4060, CD54HCT4060 (CERDIP) CD74HC4060 (PDIP, SOIC, TSSOP) CD74HCT4060 (PDIP, SOIC) TOP VIEW Q12 1 16 VCC Q13 2 15 Q10 Q14 3 14 Q8 Q6 4 13 Q9 Q5 5 12 MR Q7 6 11 φI Q4 7 10 φO GND 8 9 φO CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright ©2003, Texas Instruments Incorporated 1

CD54/74HC4060, CD54/74HCT4060 Functional Diagram 7 Q4 5 Q5 12 4 MR Q6 6 Q7 14-STAGE 14 RIPPLE Q8 11 COUNTER 13 φI AND Q9 OSCILLATOR 15 Q10 1 Q12 2 Q13 3 Q14 9 φ O GND = 8 φO 10 VCC = 16 9 øO ø1 Q1 ø4 Q4 ø5 Q13 ø14Q14 10 øO 11 FF1 FF4 FF5 - FF13 FF14 ø1 ø1 Q1 ø4 Q4 ø5 Q13 ø14Q14 R R R R 12 MR 7 2 3 Q4 5, 4, 6, 14, 13, 15, 1 Q13 Q14 Q5 - Q10, Q12 FIGURE 1. LOGIC BLOCK DIAGRAM TRUTH TABLE øI MR OUTPUT STATE ↑ L No Change ↓ L Advance to Next State X H All Outputs are Low 2

CD54/74HC4060, CD54/74HCT4060 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 1) θJA (oC/W) DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 DC Output Diode Current, IOK PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . 108 For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC DC Drain Current, per Output, IO Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyratingandoperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS 25oC -40oC TO 85oC -55oCTO125oC VCC PARAMETER SYMBOL VI(V) IO(mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V Voltage 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V Voltage 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V High Level Output VOH VIHorVIL -0.02 2 1.9 - - 1.9 - 1.9 - V Voltage Q Outputs -0.02 4.5 4.4 - - 4.4 - 4.4 - V CMOS Loads -0.02 6 5.9 - - 5.9 - 5.9 - V High Level Output - - - - - - - - - V Voltage Q Outputs -4 4.5 3.98 - - 3.84 - 3.7 - V TTL Loads -5.2 6 5.48 - - 5.34 - 5.2 - V Low Level Output VOL VIHorVIL 0.02 2 - - 0.1 - 0.1 - 0.1 V Voltage Q Outputs 0.02 4.5 - - 0.1 - 0.1 - 0.1 V CMOS Loads 0.02 6 - - 0.1 - 0.1 - 0.1 V Low Level Output - - - - - - - - - V Voltage Q Outputs 4 4.5 - - 0.26 - 0.33 - 0.4 V TTL Loads 5.2 6 - - 0.26 - 0.33 - 0.4 V High-Level Output VOH VCC or -0.02 2 1.9 - - 1.9 - 1.9 - V VoltageφO Output GND -0.02 4.5 4.4 - - 4.4 - 4.4 - V (Pin 10) CMOS Loads -0.02 6 5.9 - - 5.9 - 5.9 - V 3

CD54/74HC4060, CD54/74HCT4060 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oCTO125oC VCC PARAMETER SYMBOL VI(V) IO(mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS High-Level Output VOH VCC or -2.6 4.5 3.98 - - 3.84 - 3.7 - V VoltageφO Output GND -3.3 6 5.48 - - 5.34 - 5.2 - V (Pin 10) TTL Loads (Note 2) Low-Level Output VOL VCC or 0.02 2 - - 0.1 - 0.1 - 0.1 V VoltageφO Output GND 0.02 4.5 - - 0.1 - 0.1 - 0.1 V (Pin 10) CMOS Loads 0.02 6 - - 0.1 - 0.1 - 0.1 V Low-Level Output VOL VCC or 2.6 4.5 - - 0.26 - 0.33 - 0.4 V VoltageφO Output GND 3.3 6 - - 0.26 - 0.33 - 0.4 V (Pin 10) TTL Loads High-Level Output VOH VILorVIH -3.2 4.5 3.98 - - 3.84 - 3.7 - V VoltageφO Output -4.2 6 5.48 - - 5.34 - 5.2 - V (Pin 9) TTL Loads Low-Level Output VOL VILorVIH -2.6 4.5 - - 0.26 - 0.33 - 0.4 V VoltageφO Output -3.3 6 - - 0.26 - 0.33 - 0.4 V (Pin 9) TTL Loads Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA Current GND HCT TYPES High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V Voltage 5.5 Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V Voltage 5.5 High Level Output VOH VIHorVIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V Voltage Q Outputs (Note 3) CMOS Loads High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V Voltage Q Outputs TTL Loads Low Level Output VOL VIHorVIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V Voltage Q Outputs (Note 3) CMOS Loads Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V Voltage Q Outputs TTL Loads High-Level Output VOH VCC or -0.02 4.5 4.4 - - 4.4 - 4.4 - V VoltageφO Output GND (Pin 10) CMOS Loads High-Level Output VOH VCC or -2.6 4.5 3.98 - - 3.84 - 3.7 - V VoltageφO Output GND (Pin 10) TTL Loads (Note 2) Low-Level Output VOL VCC or 0.02 4.5 - - 0.1 - 0.1 - 0.1 V VoltageφO Output GND (Pin 10) CMOS Loads 4

CD54/74HC4060, CD54/74HCT4060 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oCTO125oC VCC PARAMETER SYMBOL VI(V) IO(mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS Low-Level Output VOL VCC or 2.6 4.5 - - 0.26 - 0.33 - 0.4 V VoltageφO Output GND (Pin 10) TTL Loads High-Level Output VOH VILorVIH -3.2 4.5 3.98 - - 3.84 - 3.7 - V VoltageφO Output (Pin 9) TTL Loads Low-Level Output VOL VIHorVIL 3.2 4.5 - 0.26 - 0.33 - 0.4 V VoltageφO Output (Note 3) (Pin 9) TTL Loads Input Leakage II Any - 5.5 - ±0.1 - ±1 - ±1 µA Current Voltage Between VCCand GND Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA Current GND Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA Device Current Per (Note 4) - 2.1 5.5 Input Pin: 1 Unit Load NOTES: 2. Limits not valid when pin 12 (instead of pin 11) is used as control input. 3. For pin 11 VIH = 3.15V, VIL = 0.9V. 4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS MR 0.35 NOTE: Unit Load is∆ICClimit specified in DC Electrical Specifica- tions Table, e.g. 360µA max at 25oC. Prerequisite for Switching Specifications 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VCC(V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS HC TYPES Maximum Input Pulse fmax 2 6 - - 5 - - 4 - - MHz Frequency 4.5 30 - - 25 - - 20 - - MHz 6 35 - - 29 - - 23 - - MHz Input Pulse Width tW 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 6 14 - - 17 - - 20 - - ns Reset Removal Time tREM 2 100 - - 125 - - 150 - - ns 4.5 20 - - 25 - - 30 - - ns 6 17 - - 21 - - 26 - - ns 5

CD54/74HC4060, CD54/74HCT4060 Prerequisite for Switching Specifications (Continued) 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VCC(V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Reset Pulse Width tW 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 6 14 - - 17 - - 20 - - ns HCT TYPES Maximum Input, fmax 4.5 30 - - 25 - - 20 - - MHz Pulse Frequency Input Pulse Width tW 4.5 16 - - 20 - - 24 - - ns Reset Removal Time tREM 4.5 26 - - 33 - - 39 - - ns Reset Pulse Width tW 4.5 25 - - 31 - - 38 - - ns Switching Specifications Input tr, tf= 6ns -40oC TO -55oC TO 25oC 85oC 125oC TEST PARAMETER SYMBOL CONDITIONS VCC(V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Propagation Delay tPLH, tPHL CL = 50pF 2 - - 300 - 375 - 450 ns φI to Q4 4.5 - - 60 - 75 - 90 ns CL = 15pF 5 - 25 - - - - - ns CL = 50pF 6 - - 51 - 64 - 78 ns Qn to Qn+1 tPLH, tPHL CL = 50pF 2 - - 80 - 100 - 120 ns 4.5 - - 16 - 20 - 24 ns CL = 15pF 5 - 6 - - - - - ns CL = 50pF 6 - - 14 - 17 - 20 ns MR to Qn tPHL CL = 50pF 2 - - 175 - 220 - 265 ns 4.5 - - 35 - 44 - 53 ns CL = 15pF 5 - 14 - - - - - ns CL = 50pF 6 - - 30 - 37 - 45 ns Output Transition Time tTHL, tTLH CL = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns Input Capacitance CI (TBD) Propagation Dissipation CPD - - - 40 - - - - - pF Capacitance (Notes 5, 6) HCT TYPES Propagation Delay tPLH, tPHL CL = 50pF 2 - - - - - - - -ns φI to Q4 4.5 - - 66 - 83 - 100 ns CL = 15pF 5 - 25 - - - - - -ns CL = 50pF 6 - - - - - - - -ns 6

CD54/74HC4060, CD54/74HCT4060 Switching Specifications Input tr, tf= 6ns (Continued) -40oC TO -55oC TO 25oC 85oC 125oC TEST PARAMETER SYMBOL CONDITIONS VCC(V) MIN TYP MAX MIN MAX MIN MAX UNITS Qn to Qn+1 tPLH, tPHL CL = 50pF 2 - - - - - - - ns 4.5 - - 16 - 20 - 24 ns CL = 15pF 5 - 6 - - - - - ns CL = 50pF 6 - - - - - - - ns MR to Qn tPHL CL = 50pF 2 - - - - - - - ns 4.5 - - 44 - 55 - 66 ns CL = 15pF 5 - 17 - - - - - ns CL = 50pF 6 - - - - - - - ns Output Transition Time tTHL, tTLH CL = 50pF 2 - - - - - - - ns 4.5 - - 15 - 19 - 22 ns 6 - - - - - - - ns Input Capacitance CI (TBD) Propagation Dissipation CPD - - - 40 - - - - - pF Capacitance (Notes 5, 6) NOTES: 5. CPD is used to determine the dynamic power consumption, per package. 6. PD = CPD VCC2 fi∑(CL VCC2 fi/M) where M = 21, 22, 23, ...214, fi =input frequency, CL = output load capacitance. TYPICAL LIMIT VALUES FOR RX AND CX TYPICAL PARAMETER CONTDEISTTIONS VOLTAGE MLAIXMIMITUSM 102 TRAX == 215KoΩC RX Minimum CX > 1000pF 2 1KΩ 10 1100K0KΩΩ CX > 10pF 4.5 1 11M0MΩΩ CX > 10pF 6 RX Maximum CX > 10pF 2 20MΩ µF) 10-1 CX > 10pF 4.5 C (X10-2 CX > 10pF 6 CX Minimum RX > 10KΩ 2 10pF 10-3 RX > 10KΩ 4.5 10-4 RX > 10KΩ 6 RX = 1KΩ 2 1000pF 10-5 RX = 1KΩ 4.5 10pF 10-1 100 10 102 103 104 105 106 OSCILLATOR FREQUENCY (Hz) RX = 1KΩ 6 10pF Maximum CX = 1000pF, 2 0.5MHz Astable Oscillator RX = 1KΩ (Note 7) NOTE: OSC Frequency≈ 1/2.2 RXCX Frequency CX = 100pF, 4.5 3MHz For 1MΩ > RX > 1KΩ, CX > 10pF, f < 1MHz RX = 1KΩ (Note 7) FIGURE 2. FREQUENCY OF ON-BOARD OSCILLATOR AS A CX = 100pF, 6 3MHz FUNCTION OF CX AND RX RX = 1KΩ (Note 7) NOTE: 7. Atveryhighfrequenciesf=1/2.2RXCXnolongergivesan accurate approximation. 7

CD54/74HC4060, CD54/74HCT4060 Typical Performance Curves I trCL tfCL tWL+ tWH=fCIL trCL= 6ns tfCL= 6ns tWL+ tWH=fCL VCC 3V 90% 2.7V CLOCK 50% 50% 50% CLOCK 1.3V 1.3V 1.3V 10% 10% GND 0.3V 0.3V GND tWL tWH tWL tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordancewithdevicetruthtable.ForfMAX,inputdutycycle=50%. accordancewithdevicetruthtable.ForfMAX,inputdutycycle=50%. FIGURE3. HCCLOCKPULSERISEANDFALLTIMESAND FIGURE4. HCTCLOCKPULSERISEANDFALLTIMESAND PULSE WIDTH PULSE WIDTH tr = 6ns tf = 6ns tr = 6ns tf = 6ns 90% VCC 2.7V 3V INPUT 50% INPUT 1.3V 10% GND 0.3V GND tTHL tTLH tTHL tTLH 90% 90% 50% 1.3V INVERTING INVERTING 10% 10% OUTPUT OUTPUT tPHL tPLH tPHL tPLH FIGURE5. HCANDHCTTRANSITIONTIMESANDPROPAGA- FIGURE6. HCTTRANSITIONTIMESANDPROPAGATION TION DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC 8

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-8768001EA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8768001EA CD54HC4060F3A 5962-8977101EA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8977101EA CD54HCT4060F3A CD54HC4060F3A ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8768001EA CD54HC4060F3A CD54HCT4060F3A ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8977101EA CD54HCT4060F3A CD74HC4060E ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HC4060E & no Sb/Br) CD74HC4060M ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC4060M & no Sb/Br) CD74HC4060M96 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC4060M & no Sb/Br) CD74HC4060M96G4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC4060M & no Sb/Br) CD74HC4060MG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC4060M & no Sb/Br) CD74HC4060MT ACTIVE SOIC D 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC4060M & no Sb/Br) CD74HC4060PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4060 & no Sb/Br) CD74HC4060PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4060 & no Sb/Br) CD74HC4060PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4060 & no Sb/Br) CD74HC4060PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4060 & no Sb/Br) CD74HC4060PWT ACTIVE TSSOP PW 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4060 & no Sb/Br) CD74HCT4060E ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4060E & no Sb/Br) CD74HCT4060EE4 ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4060E & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CD74HCT4060M ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4060M & no Sb/Br) CD74HCT4060M96 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4060M & no Sb/Br) CD74HCT4060M96G4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4060M & no Sb/Br) CD74HCT4060MT ACTIVE SOIC D 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4060M & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HC4060, CD54HCT4060, CD74HC4060, CD74HCT4060 : •Catalog: CD74HC4060, CD74HCT4060 •Military: CD54HC4060, CD54HCT4060 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74HC4060M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC4060PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HC4060PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HCT4060M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74HC4060M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC4060PWR TSSOP PW 16 2000 367.0 367.0 35.0 CD74HC4060PWT TSSOP PW 16 250 367.0 367.0 35.0 CD74HCT4060M96 SOIC D 16 2500 333.2 345.9 28.6 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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