CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 Data sheet acquired from Harris Semiconductor High-Speed CMOS Logic SCHS168D Quad-Bus Transceiver with Three-State Outputs November 1997 - Revised October 2003 Features Description • Typical Propagation Delay (A to B, B to A) of 7ns at The ’HC243 and ’HCT243 silicon-gate CMOS three-state VCC = 5V, CL = 15pF, TA = 25oC bidirectional noninverting buffers are intended for two-way [ /Title • Three-State Outputs asynchronous communication between data buses. They (CD74 • Buffered Inputs havehigh-drive-currentoutputsthatenablehigh-speedoper- ation when driving large bus capacitances. These circuits HCT24 • Fanout (Over Temperature Range) possess the low power dissipation of CMOS circuits and 2, - Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads havespeedscomparabletolow-powerSchottkyTTLcircuits. CD74 - Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads They can drive 15 LSTTL loads. HC243 • Wide Operating Temperature Range . . .-55oC to 125oC The states of the output-enable (OEB, OEA) inputs , • Balanced Propagation Delay and Transition Times determineboththedirectionofflow(AtoB,BtoA),andthe three-state mode. CD74 • Significant Power Reduction Compared to LSTTL Logic ICs HCT24 Ordering Information • HC Types 3) - 2V to 6V Operation /Sub- TEMP. RANGE - High Noise Immunity: NIL = 30%, NIH = 30% of VCC PART NUMBER (oC) PACKAGE ject at VCC = 5V (High • HCT Types CD54HC243F3A -55 to 125 14 Ld CERDIP Speed - 4.5V to 5.5V Operation CD54HCT243F3A -55 to 125 14 Ld CERDIP CMOS - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) CD74HC243E -55 to 125 14 Ld PDIP Logic - CMOS Input Compatibility, Il≤1µA at VOL, VOH Quad- CD74HC243M -55 to 125 14 Ld SOIC CD74HC243MT -55 to 125 14 Ld SOIC Pinout CD74HC243M96 -55 to 125 14 Ld SOIC CD54HC243, CD54HCT243 CD74HCT243E -55 to 125 14 Ld PDIP (CERDIP) CD74HC243, CD74HCT243 CD74HCT243M -55 to 125 14 Ld SOIC (PDIP, SOIC) TOP VIEW NOTE: When ordering, use the entire part number. The suffix 96 denotestapeandreel.ThesuffixTdenotesasmall-quantityreelof OEB 1 14 VCC 250. NC 2 13 OEA A0 3 12 NC A1 4 11 B0 A2 5 10 B1 A3 6 9 B2 GND 7 8 B3 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1

CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 Functional Diagram ‘HC243, ‘HCT243 3 11 A0 B0 4 10 A1 B1 5 9 A2 B2 6 8 A3 B3 1 OEB DIRECTION 13 OEA SELECT LOGIC TRUTH TABLE HC, HCT243 SERIES CONTROL INPUTS DATA PORT STATUS OEB OEA An Bn H H O I L H Z Z H L Z Z L L I O H= High Voltage Level L= Low Voltage Level I= Input O= Output (Same Level as Input) Z=High Impedance TopreventexcesscurrentsintheHighZmodesallI/Oterminalsshouldbeterminatedwith10kΩ to 1MΩ resistors. 2

CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 1) θJA (oC/W) DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 DC Output Diode Current, IOK Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC DC Drain Current, per Output, IO Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA (SOIC - Lead Tips Only) DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±70mA Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyratingandoperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V Voltage 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V Voltage 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V High Level Output VOH VIH or -0.02 2 1.9 - - 1.9 - 1.9 - V Voltage VIL CMOS Loads -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V High Level Output -6 4.5 3.98 - - 3.84 - 3.7 - V Voltage TTL Loads -7.8 6 5.48 - - 5.34 - 5.2 - V Low Level Output VOL VIH or 0.02 2 - - 0.1 - 0.1 - 0.1 V Voltage VIL CMOS Loads 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V Low Level Output 6 4.5 - - 0.26 - 0.33 - 0.4 V Voltage TTL Loads 7.8 6 - - 0.26 - 0.33 - 0.4 V 3

CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA Current GND Three-State Leakage IOZ VIL or - 6 - - ±0.5 - ±0.5 - ±10 µA Current VIH HCT TYPES High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V Voltage 5.5 Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V Voltage 5.5 High Level Output VOH VIH or -0.02 4.5 4.4 - - 4.4 - 4.4 - V Voltage VIL CMOS Loads High Level Output -6 4.5 3.98 - - 3.84 - 3.7 - V Voltage TTL Loads Low Level Output VOL VIH or 0.02 4.5 - - 0.1 - 0.1 - 0.1 V Voltage VIL CMOS Loads Low Level Output 6 4.5 - - 0.26 - 0.33 - 0.4 V Voltage TTL Loads Input Leakage II VCC to - 5.5 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA Current GND Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA Device Current Per (Note 2) -2.1 5.5 Input Pin: 1 Unit Load Three-State Leakage IOZ VIL or - 5.5 - - ±0.5 - ±5.0 - ±10 µA Current VIH NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS An, Bn 1.1 OEA,OEB 0.6 NOTE: Unit Load is∆ICClimit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. 4

CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 Switching Specifications Input tr, tf = 6ns 25oC -40oC TO 85oC -55oCTO125oC TEST PARAMETER SYMBOL CONDITIONS VCC (V) TYP MAX MAX MAX UNITS HC TYPES Propagation Delay Data tPLH, tPHL CL= 50pF 2 - 90 115 135 ns to Outputs 4.5 - 18 23 27 ns CL= 15pF 5 7 - - - ns CL = 50pF 6 - 15 20 23 ns Output High-Z, to High Level tPZL,tPZH CL= 50pF 2 - 150 190 225 ns to Low Level CL = 50pF 4.5 - 30 38 45 ns CL = 15pF 5 12 - - - ns CL = 50pF 6 - 26 33 38 ns Output High Level, tPHZ,tPLZ CL= 50pF 2 - 150 190 225 ns Output Low Level to High-Z CL = 50pF 4.5 - 30 38 45 ns CL = 15pF 5 12 - - - ns CL = 50pF 6 - 26 33 38 ns Output Transition Times tTLH, tTHL CL= 50pF 2 - 60 75 90 ns 4.5 - 12 15 18 ns 6 - 10 13 15 ns Input Capacitance CI - - - 10 10 10 pF Three-State Output CO - - - 20 20 20 pF Capacitance Power Dissipation CPD - 5 80 - - - pF Capacitance (Notes 3, 4) HCT TYPES Propagation Delay Data to tPLH, tPHL CL= 50pF 4.5 - 22 28 33 ns Outputs CL= 15pF 5 9 - - - ns Output High-Z to High Level tPZH, tPZL CL= 50pF 4.5 - 34 43 51 ns to Low Level CL= 15pF 5 14 - - - ns Output High Level, tPHZ, tPLZ CL= 50pF 4.5 - 35 44 53 ns Output Low Level to High-Z CL= 15pF 5 14 - - - ns Output Transition Times tTLH, tTHL CL= 50pF 4.5 - 12 15 18 ns Input Capacitance CI - - - 10 10 10 pF Three-State Output CO - - - 20 20 20 pF Capacitance Power Dissipation CPD - 5 91 - - - pF Capacitance (Notes 3, 4) NOTES: 3. CPD is used to determine the dynamic power consumption, per channel. 4. PD = VCC2 fi(CPD + CL) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. 5

CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 Test Circuits and Waveforms tr = 6ns tf = 6ns tr = 6ns tf = 6ns 90% VCC 2.7V 3V INPUT 50% INPUT 1.3V 10% GND 0.3V GND tTHL tTLH tTHL tTLH 90% 90% 50% 1.3V INVERTING INVERTING 10% 10% OUTPUT OUTPUT tPHL tPLH tPHL tPLH FIGURE1. HCANDHCTTRANSITIONTIMESANDPROPAGA- FIGURE2. HCTTRANSITIONTIMESANDPROPAGATION TION DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC 6ns 6ns tr 6ns tf 6ns OUTPUT 90% VCC OUTPUT 2.7 3V DISABLE 50% DISABLE 1.3 10% 0.3 GND GND tPLZ tPZL tPLZ tPZL OUTPUT LOW OUTPUT LOW TO OFF 50% TO OFF 1.3V 10% 10% tPHZ 90% tPZH tPHZ 90% tPZH OUTPUT HIGH OUTPUT HIGH 50% TO OFF TO OFF 1.3V OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS ENABLED DISABLED ENABLED ENABLED DISABLED ENABLED FIGURE3. HCTHREE-STATEPROPAGATIONDELAY FIGURE4. HCTTHREE-STATEPROPAGATIONDELAY WAVEFORM WAVEFORM OTHER OUTPUT INPUTS IC WITH RL = 1kΩ TIED HIGH THREE- VCC FOR tPLZ AND tPZL OR LOW STATE CL GND FOR tPHZ AND tPZH OUTPUT 50pF OUTPUT DISABLE NOTE: OpendrainwaveformstPLZandtPZLarethesameasthoseforthree-stateshownontheleft.ThetestcircuitisOutputRL=1kΩto VCC, CL = 50pF. FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 6

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 8409001CA ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 8409001CA CD54HC243F3A CD54HC243F ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54HC243F CD54HC243F3A ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 8409001CA CD54HC243F3A CD74HC243E ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HC243E & no Sb/Br) CD74HC243EE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HC243E & no Sb/Br) CD74HC243M ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC243M & no Sb/Br) CD74HC243M96 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC243M & no Sb/Br) CD74HC243MT ACTIVE SOIC D 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC243M & no Sb/Br) CD74HCT243E ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HCT243E & no Sb/Br) CD74HCT243EE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HCT243E & no Sb/Br) CD74HCT243M ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT243M & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HC243, CD74HC243 : •Catalog: CD74HC243 •Military: CD54HC243 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74HC243M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HC243MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74HC243M96 SOIC D 14 2500 367.0 367.0 38.0 CD74HC243MT SOIC D 14 250 210.0 185.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID A 4X .005 MIN (OPTIONAL) [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 14X .045-.065 [0.36-0.66] [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 7 8 B .245-.283 .2 MAX TYP .13 MIN TYP [6.22-7.19] [5.08] [3.3] SEATING PLANE C .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 14X .008-.014 TYP [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com

EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL B SEE DETAIL A 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 7 8 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX (.063) [0.05] [1.6] METAL ALL AROUND ( .063) SOLDER MASK [1.6] OPENING METAL .002 MAX SOLDER MASK (R.002 ) TYP [0.05] OPENING [0.05] ALL AROUND DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com

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