CD54ACT112, CD74ACT112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS323 – JANUARY 2003 (cid:0) Inputs Are TTL-Voltage Compatible CD54ACT112...F PACKAGE (cid:0) CD74ACT112...M PACKAGE Speed of Bipolar F, AS, and S, With (TOP VIEW) Significantly Reduced Power Consumption (cid:0) Balanced Propagation Delays 1CLK 1 16 VCC (cid:0) ±24-mA Output Drive Current 1K 2 15 1CLR – Fanout to 15 F Devices 1J 3 14 2CLR (cid:0) 1PRE 4 13 2CLK SCR-Latchup-Resistant CMOS Process and 1Q 5 12 2K Circuit Design (cid:0) 1Q 6 11 2J Exceeds 2-kV ESD Protection Per 2Q 7 10 2PRE MIL-STD-883, Method 3015 GND 8 9 2Q description/ordering information The ’ACT112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING Tube CD74ACT112M SSOOIICC – MM AACCTT111122MM –55°C to 125°C Tape and reel CD74ACT112M96 CDIP – F Tube CD54ACT112F3A CD54ACT112F3A †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each flip-flop) INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H L X X X L H L L X X X H‡ H‡ H H ↓ L L Q0 Q0 H H ↓ H L H L H H ↓ L H L H H H ↓ H H Toggle H H H X X Q0 Q0 ‡Output states are unpredictable if PRE and CLR go high simultaneously after both being low at the same time. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright  2003, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production testing of all parameters. processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

CD54ACT112, CD74ACT112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS323 – JANUARY 2003 logic diagram (positive logic) Q Q PRE CLR K J CLK absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V CC Input clamp current, IIK (VI < 0 V or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 V or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, I (V > 0 V or V < V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA O O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA CC Package thermal impedance, θ (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W JA Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) –55°C to –40°C to TA = 25°C 125°C 85°C UNIT MIN MAX MIN MAX MIN MAX VCC Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 V VIH High-level input voltage 2 2 2 V VIL Low-level input voltage 0.8 0.8 0.8 V VI Input voltage 0 VCC 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC 0 VCC V IOH High-level output current –24 –24 –24 mA IOL Low-level output current 24 24 24 mA ∆t/∆v Input transition rise or fall rate 10 10 10 ns/V NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD54ACT112, CD74ACT112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS323 – JANUARY 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) –55°C to –40°C to PARAMETER TEST CONDITIONS VCCCC TA = 25°C 125°C 85°C UNIT MIN MAX MIN MAX MIN MAX IOH = –50 µA 4.5 V 4.4 4.4 4.4 IOH = –24 mA 4.5 V 3.94 3.7 3.8 VVOOHH VVII == VVIIHH oorr VVIILL IOH = –50 mA† 5.5 V 3.85 VV IOH = –75 mA† 5.5 V 3.85 IOL = 50 µA 4.5 V 0.1 0.1 0.1 IOL = 24 mA 4.5 V 0.36 0.5 0.44 VVOOLL VVII == VVIIHH oorr VVIILL IOL = 50 mA† 5.5 V 1.65 VV IOL = 75 mA† 5.5 V 1.65 II VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA ICC VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA 4.5 V to (cid:0)ICC VI = VCC –2.1 V 5.5 V 2.4 3 2.8 mA Ci 10 10 10 pF †Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C. ACT INPUT LOAD TABLE INPUT UNIT LOAD J or CLK 1 K 0.53 CLR or PRE 0.58 Unit Load is ∆ICC limit specified in electrical characteristics table (e.g., 2.4 mA at 25°C). timing requirements over recommended operating conditions (unless otherwise noted) –55°C to –40°C to 125°C 85°C UNIT MIN MAX MIN MAX fclock Clock frequency 100 114 MHz CLK high or low 5 4.4 ttw PPuullssee dduurraattiioonn nnss CLR or PRE low 5.5 4.8 tsu Setup time, before CLK↓ J or K 4 3.5 ns th Hold time, after CLK↓ J or K 1 1 ns trec Recovery time, before CLK↓ CLR↑or PRE↑ 2.5 2.2 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

CD54ACT112, CD74ACT112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS323 – JANUARY 2003 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) –55°C to –40°C to PARAMETER FROM TO 125°C 85°C UNIT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN MAX MIN MAX fmax 100 114 MHz CLK 2.6 10.3 2.7 9.4 ttPPLLHH QQ or QQ nnss CLR or PRE 3.1 12.2 3.2 11.1 CLK 2.6 10.3 2.7 9.4 ttPPHHLL QQ oorr QQ nnss CLR or PRE 3.1 12.2 3.2 11.1 operating characteristics, V = 5 V, T = 25°C CC A PARAMETER TYP UNIT Cpd Power dissipation capacitance 56 pF 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD54ACT112, CD74ACT112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS323 – JANUARY 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC TEST S1 S1 From Output R1 = 500 Ω Open tPLH/tPHL Open Under Test GND tPLZ/tPZL 2 × VCC CL = 50 pF tPHZ/tPZH GND (see Note A) R2 = 500 Ω tw 3 V Input 1.5 V 1.5 V LOAD CIRCUIT 0 V VOLTAGE WAVEFORMS PULSE DURATION 3 V 3 V Reference 1.5 V CLR Input Input 1.5 V 0 V 0 V tsu th trec 3 V 3 V IDnpautat 1.5 V 90% 90% 1.5 V CLK 1.5 V 10% 10% 0 V 0 V tr tf VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS RECOVERY TIME SETUP AND HOLD AND INPUT RISE AND FALL TIMES 3 V Input 1.5 V 1.5 V Output 3 V 1.5 V 1.5 V 0 V Control 0 V tPLH tPHL In-Phase VOH Output tPZL tPLZ Output 50% 90% 90% 50% VCC Waveform 1 ≈VCC 10% 10% VOL S1 at 2 × VCC 20% VCC 20% VCC tr tf (see Note B) VOL tPHL tPLH VOH tPZH tPHZ Out-ofO-Puhtapsuet 90% 501%0% VCC 105%0% 90% VOL WaveOfourtmpu 2t 80% VCC 80% VCCVOH S1 at GND tf tr ≈0 V (see Note B) VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLH and tPHL are the same as tpd. G. tPZL and tPZH are the same as ten. H. tPLZ and tPHZ are the same as tdis. I. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CD54ACT112F3A ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54ACT112F3A CD74ACT112M ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 ACT112M & no Sb/Br) CD74ACT112M96 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 ACT112M & no Sb/Br) CD74ACT112MG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 ACT112M & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54ACT112, CD74ACT112 : •Catalog: CD74ACT112 •Military: CD54ACT112 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74ACT112M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74ACT112M96 SOIC D 16 2500 333.2 345.9 28.6 PackMaterials-Page2

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