a DSP Microcomputer ADSP-2191M PERFORMANCE FEATURES Multifunction Instructions 6.25ns Instruction Cycle Time, for up to 160MIPS Pipelined Architecture Supports Efficient Code Sustained Performance Execution ADSP-218x Family Code Compatible with the Same Architectural Enhancements for Compiled C and C++ Easy to Use Algebraic Syntax CodeEfficiency Single-Cycle Instruction Execution Architectural Enhancements beyond ADSP-218x Family Single-Cycle Context Switch between Two Sets of Com- are Supported with Instruction Set Extensions for putation and Memory Instructions Added Registers, and Peripherals Instruction Cache Allows Dual Operand Fetches in Every Flexible Power Management with User-Selectable Instruction Cycle Power-Down and Idle Modes FUNCTIONAL BLOCK DIAGRAM INTERNALMEMORY FOUR INDEPENDENTBLOCKS 0K ADDSSPPC-2O1R9Ex 64C(cid:1)AC24H-BEIT ADADRDAEDDSRADSEDRSDESRSESS2S42B4I1TB6IT1B6ITBIT DATDAATDAATDAATA LBCO L1BOCK2LBCKOL3BOCK EMTUJETLSAATGT&ION 6 DAG1 DAG2 PROGRAM 4(cid:1)4(cid:1)16 4(cid:1)4(cid:1)16 SEQUENCER EXTERNALPORT 24 PMADDRESSBUS 22 I/OADDRESS 18 DMADDRESSBUS 24 ADDRBUS MUX 24 DMAADDRESS DMA 24 DMADATA CONNECT PMDATABUS 24 PX DATABUS 16 MUX DMDATABUS 16 16 I/ODATA DATA REGISTER I/OPROCESSOR FILE INPUT 24 REGISTERS HOSTPORT I/OREGISTERS RESULT (MEMORY-MAPPED) 18 REGISTERS SERIALPORTS MULT 16(cid:1)16-BIT SBHAIRFRTEERL ALU CSOTNATTRUOSL DMA (3) BUFFERS CONTROLLER 6 SPIPORTS (2) 2 UARTPORT (1) 3 PROGRAMMABLE SYSTEMINTERRUPTCONTROLLER TIMERS(3) FLAGS(16) REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise Tel:781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Fax:781/326-8703 © Analog Devices, Inc., 2002

ADSP-2191M INTEGRATION FEATURES TABLE OF CONTENTS 160K Bytes On-Chip RAM Configured as 32K Words 24-Bit GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . .3 Memory RAM and 32K Words 16-Bit Memory RAM DSP Core Architecture . . . . . . . . . . . . . . . . . . . . . . . .3 Dual-Purpose 24-Bit Memory for Both Instruction and DSP Peripherals Architecture . . . . . . . . . . . . . . . . . . .4 Data Storage Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . .5 Independent ALU, Multiplier/Accumulator, and Barrel Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Shifter Computational Units with Dual 40-Bit DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Accumulators Host Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Unified Memory Space Allows Flexible Address Genera- DSP Serial Ports (SPORTs) . . . . . . . . . . . . . . . . . . . .8 tion, Using Two Independent DAG Units Serial Peripheral Interface (SPI) Ports . . . . . . . . . . . . .9 Powerful Program Sequencer Provides Zero-Overhead UART Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Looping and Conditional Instruction Execution Programmable Flag (PFx) Pins . . . . . . . . . . . . . . . . . .9 Enhanced Interrupt Controller Enables Programming of Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . .10 Interrupt Priorities and Nesting Modes Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 SYSTEM INTERFACE FEATURES Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Host Port with DMA Capability for Glueless 8- or 16-Bit Booting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Host Interface Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . .12 16-Bit External Memory Interface for up to 16M Words of Addressable Memory Space Instruction Set Description . . . . . . . . . . . . . . . . . . . .13 Three Full-Duplex Multichannel Serial Ports, with Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . .13 Support for H.100 and up to 128 TDM Channels with Additional Information . . . . . . . . . . . . . . . . . . . . . . .15 A-Law and (cid:2)-Law Companding Optimized for Telecom- PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . .15 munications Systems SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Two SPI-Compatible Ports with DMA Support ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . .19 UART Port with DMA Support ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . .19 16 General-Purpose I/O Pins with Integrated Interrupt Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Support TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . .20 Three Programmable Interval Timers with PWM Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . .40 Generation, PWM Capture/Pulsewidth Measurement, Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .40 and External Event Counter Capabilities Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Up to 11 DMA Channels Can Be Active at Any Given Time Environmental Conditions . . . . . . . . . . . . . . . . . . . .41 for High I/O Throughput 144-Lead LQFP Pinout . . . . . . . . . . . . . . . . . . . . . .43 On-Chip Boot ROM for Automatic Booting from External 144-Lead Mini-BGA Pinout . . . . . . . . . . . . . . . . . . .45 8- or 16-Bit Host Device, SPI ROM, or UART with OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . .47 Autobaud Detection ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . .48 Programmable PLL Supports 1(cid:1) to 32(cid:1) Input Frequency Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Multiplication and Can Be Altered during Runtime IEEE JTAG Standard 1149.1 Test Access Port Supports On-Chip Emulation and System Debugging 2.5V Internal Operation and 3.3V I/O 144-Lead LQFP and 144-Ball Mini-BGA Packages –2– REV. A

ADSP-2191M GENERAL DESCRIPTION uses an algebraic syntax for ease of coding and readability. A The ADSP-2191M DSP is a single-chip microcomputer comprehensive set of development tools supports program optimized for digital signal processing (DSP) and other high development. speed numeric processing applications. The functional block diagram onPage1 shows the architecture The ADSP-2191M combines the ADSP-219x family base of the ADSP-219x core. It contains three independent compu- architecture (three computational units, two data address gener- tational units: the ALU, the multiplier/accumulator (MAC), and ators, and a program sequencer) with three serial ports, two the shifter. The computational units process 16-bit data from the SPI-compatible ports, one UART port, a DMA controller, three register file and have provisions to support multiprecision com- programmable timers, general-purpose Programmable Flag putations. The ALU performs a standard set of arithmetic and pins, extensive interrupt capabilities, and on-chip program and logic operations; division primitives are also supported. The data memory spaces. MAC performs single-cycle multiply, multiply/add, and multi- ply/subtract operations. The MAC has two 40-bit accumulators, The ADSP-2191M architecture is code-compatible with DSPs which help with overflow. The shifter performs logical and arith- of the ADSP-218x family. Although the architectures are metic shifts, normalization, denormalization, and derive compatible, the ADSP-2191M architecture has a number of exponent operations. The shifter can be used to efficiently enhancements over the ADSP-218x architecture. The enhance- implement numeric format control, including multiword and ments to computational units, data address generators, and block floating-point representations. program sequencer make the ADSP-2191M more flexible and even easier to program. Register-usage rules influence placement of input and results within the computational units. For most operations, the com- Indirect addressing options provide addressing flexibility— putational units’ data registers act as a data register file, premodify with no update, pre- and post-modify by an immediate permitting any input or result register to provide input to any unit 8-bit, two’s-complement value and base address registers for for a computation. For feedback operations, the computational easier implementation of circular buffering. units let the output (result) of any unit be input to any unit on The ADSP-2191M integrates 64K words of on-chip memory the next cycle. For conditional or multifunction instructions, configured as 32K words (24-bit) of program RAM, and there are restrictions on which data registers may provide inputs 32Kwords (16-bit) of data RAM. Power-down circuitry is also or receive results from each computational unit. For more infor- provided to reduce power consumption. The ADSP-2191M is mation, see the ADSP-219x DSP Instruction Set Reference. available in 144-lead LQFP and 144-ball mini-BGA packages. A powerful program sequencer controls the flow of instruction Fabricated in a high speed, low power, CMOS process, the execution. The sequencer supports conditional jumps, subrou- ADSP-2191M operates with a 6.25ns instruction cycle time tine calls, and low interrupt overhead. With internal loop (160MIPS). All instructions, except single-word instructions, counters and loop stacks, the ADSP-2191M executes looped execute in one processor. code with zero overhead; no explicit jump instructions are The ADSP-2191M’s flexible architecture and comprehensive required to maintain loops. instruction set support multiple operations in parallel. For Two data address generators (DAGs) provide addresses for example, in one processor cycle, the ADSP-2191M can: simultaneous dual operand fetches (from data memory and • Generate an address for the next instruction fetch program memory). Each DAG maintains and updates four • Fetch the next instruction 16-bit address pointers. Whenever the pointer is used to access data (indirect addressing), it is pre- or post-modified by the value • Perform one or two data moves of one of four possible modify registers. A length value and base • Update one or two data address pointers address may be associated with each pointer to implement • Perform a computational operation automatic modulo addressing for circular buffers. Page registers in the DAGs allow circular addressing within 64K-word bound- These operations take place while the processor continuesto: aries of each of the 256 memory pages, but these buffers may not • Receive and transmit data through two serial ports cross page boundaries. Secondary registers duplicate all the • Receive and/or transmit data from a Host primary registers in the DAGs; switching between primary and • Receive or transmit data through the UART secondary registers provides a fast context switch. • Receive or transmit data over two SPI ports Efficient data transfer in the core is achieved with the use of internal buses: • Access external memory through the external memory interface • Program Memory Address (PMA) Bus • Decrement the timers • Program Memory Data (PMD) Bus • Data Memory Address (DMA) Bus DSP Core Architecture The ADSP-2191M instruction set provides flexible data moves • Data Memory Data (DMD) Bus and multifunction (one or two data moves with a computation) • DMA Address Bus instructions. Every single-word instruction can be executed in a • DMA Data Bus single processor cycle. The ADSP-2191M assembly language REV. A –3–

ADSP-2191M The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded off-chip, and the ADSP-2191M EXTERNAL two data buses (PMD and DMD) share a single external data CLOCK CLKIN CLKOUT (MOPETMIOONRAYL) bus. Boot memory space and I/O memory space also share the OR CRYSTAL XTAL ADDR21–0 ADDR21–0 external buses. DATA15–8 DATA15–8 TIMER Program memory can store both instructions and data, permit- OUTOR TMR2–0 DATA7–0 DATA7–0 ting the ADSP-2191M to fetch two operands in a single cycle, CAPTURE MS3–0 CS one from program memory and one from data memory. The CLOCK MSEL6–0/PF6–0 RD OE MULTIPLY DSP’s dual memory buses also let the ADSP-219x core fetch an AND DF/PF7 WR WE operand from data memory and the next instruction from RANGE BYPASS ACK ACK BOOT BMODE1–0 pDrSogPr aPme rmipehmeorrayl sin A ar scinhgitlee cctyucrlee. AMNODDOEP OPMODE TLCONRO RESSADD TDAA (MOPBETOMIOOONTRAYL) The functional block diagram onPage1 shows the DSP’s SPORT0 ADDR21–0 on-chip peripherals, which include the external memory inter- TCLK0 DATA15–8 face, Host port, serial ports, SPI-compatible ports, UART port, TFS0 DATA7–0 JTAG test and emulation port, timers, flags, and interrupt con- SERIAL DT0 BMS CS DEVICE troller. These on-chip peripherals can connect to off-chip devices (OPTIONAL) RCLK0 OE RFS0 WE as shown in Figure1. DR0 ACK The ADSP-2191M has a 16-bit Host port with DMA capability SPORT1 BR that lets external Hosts access on-chip memory. This 24-pin TCLK1 BG EXTERNAL I/OMEMORY parallel port consists of a 16-pin multiplexed data/address bus TFS1 BGH (OPTIONAL) and provides a lowservice overhead data move capability. Con- SERIAL DT1 ADDR17–0 DEVICE figurable for 8 or 16 bits, this port provides a glueless interface (OPTIONAL) RCLK1 DATA15–8 to a wide variety of 8- and 16-bit microcontrollers. Two RFS1 DATA7–0 chip-selects provide Hosts access to the DSP’s entire memory DR1 IOMS CS map. The DSP is bootable through this port. SPORT2 OE TCLK2/SCK0 WE The ADSP-2191M also has an external memory interface that is TFS2/MOSI0 SPI0 ACK shared by the DSP’s core, the DMA controller, and DMA SERIAL DT2/MISO0 capable peripherals, which include the UART, SPORT0, DEVICE HOST (OPTIONAL) RCLK2/SCK1 PROCESSOR SPORT1, SPORT2, SPI0, SPI1, and the Host port. The external RFS2/MOSI1 SPI1 (OPTIONAL) port consists of a 16-bit data bus, a 22-bit address bus, and DR2/MISO1 HAD15–0 ADDR15–0/ DATA15–0 control signals. The data bus is configurable to provide an 8- or HA16 ADDR16 16-bit interface to external memory. Support for word packing UART HCMS CS0 lets the DSP access 16- or 24-bit words from external memory UART RXD HCIOMS CS1 DEVICE regardless of the external data bus width. When configured for (OPTIONAL) TXD HRD RD an 8-bit interface, the unused eight lines provide eight program- HWR WR mable, bidirectional general-purpose Programmable Flag lines, RESET HACK ACK six of which can be mapped to software condition signals. 6 HALE ALE JTAG HACK_P The memory DMA controller lets the ADSP-2191M move data and instructions from between memory spaces: internal-to-exter- Figure 1. System Diagram nal, internal-to-internal, and external-to-external. On-chip peripherals can also use this controller for DMA transfers. of operation. Each serial port can transmit or receive an internal The ADSP-2191M can respond to up to seventeen interrupts at or external, programmable serial clock and frame syncs. Each any given time: three internal (stack, emulator kernel, and serial port supports 128-channel Time Division Multiplexing. power-down), two external (emulator and reset), and twelve user- The ADSP-2191M provides up to sixteen general-purpose I/O defined (peripherals) interrupts. The programmer assigns a pins, which are programmable as either inputs or outputs. Eight peripheral to one of the 12 user-defined interrupts. The priority of these pins are dedicated-general purpose Programmable Flag of each peripheral for interrupt service is determined by these pins. The other eight of them are multifunctional pins, acting as assignments. general-purpose I/O pins when the DSP connects to an 8-bit There are three serial ports on the ADSP-2191M that provide a external data bus and acting as the upper eight data pins when complete synchronous, full-duplex serial interface. This interface the DSP connects to a 16-bit external data bus. These Program- includes optional companding in hardware as well as a wide mable Flag pins can implement edge- or level-sensitive variety of framed or frameless data transmit and receive modes interrupts, some of which can be used to base the execution of conditional instructions. –4– REV. A

ADSP-2191M Three programmable interval timers generate periodic inter- pulsewidth register. A single status register supports all three rupts. Each timer can be independently set to operate in one of timers. A bit in each timer’s configuration register enables or three modes: disables the corresponding timer independently of the others. • Pulse Waveform Generation mode Memory Architecture • Pulsewidth Count/Capture mode The ADSP-2191M DSP provides 64K words of on-chip SRAM • External Event Watchdog mode memory. This memory is divided into four 16K blocks located on memory Page0 in the DSP’s memory map. In addition to the Each timer has one bidirectional pin and four registers that internal and external memory space, the ADSP-2191M can implement its mode of operation: A 7-bit configuration register, address two additional and separate off-chip memory spaces: I/O a 32-bit count register, a 32-bit period register, and a 32-bit space and boot space. 64KWORD LOGICAL LOWERPAGEBOUNDARIES MEMORYSELECTS(MS) MEMORY ADDRESS ARECONFIGURABLEFOR FORPORTIONSOFTHE PAGES BANKSOFEXTERNALMEMORY. MEMORYMAPAPPEAR 0xFFFFFF BOUNDARIESSHOWNARE WITHTHESELECTED RESERVED BANKSIZESATRESET. MEMORY. INTERNAL PAGE255 0xFF0400 MEMORY 0xFF03FF BOOTROM,24-BIT 0xFF0000 PAGES192–254 BANK3 (MS3) 0xC00000 PAGES128–191 BANK2 (MS2) EXMTEEMRONRAYL 0x800000 BOO1T6M-BEIMTORY I/O1M6E-BMIOTRY (16-BIT) (BMS) BANK1 LOGICAL 1KWORD PAGES64–127 (MS1) 64KWORD ADDRESS PAGES8–255 0x400000 0xFEFFFF 1KWORD LOGICAL PAGES0–7 ADDRESS PAGES1–63 BANK0 PAGES1–254 (MS0) 0xFF3FF 0x010000 0x010000 EXTERNAL BLOCK3,16-BIT 0x00C000 (IOMS) INTERNAL BLOCK2,16-BIT 0x008000 0x08000 MEMORY PAGE0 BLOCK1,24-BIT 0x004000 INTERNAL 0x073FF 0x00000 BLOCK0,24-BIT 0x000000 8-BIT 10-BIT Figure 2. Memory Map As shown in Figure2, the DSP’s two internal memory blocks different mechanisms to generate a 24-bit address for each bus. populate all of Page0. The entire DSP memory map consists of The DSP has three functions that support access to the full 256 pages (Pages 0−255), and each page is 64K words long. memory map. External memory space consists of four memory banks (banks • The DAGs generate 24-bit addresses for data fetches from 0–3) and supports a wide variety of SRAM memory devices. Each the entire DSP memory address range. Because DAG bank is selectable using the memory select pins (MS3–0) and has index (address) registers are 16 bits wide and hold the configurable page boundaries, waitstates, and waitstate modes. lower 16bits of the address, each of the DAGs has its own The 1K word of on-chip boot-ROM populates the top of 8-bit page register (DMPGx) to hold the most significant Page255 while the remaining 254 pages are addressable off-chip. eight address bits. Before a DAG generates an address, I/O memory pages differ from external memory pages in that I/O the program must set the DAG’s DMPGx register to the pages are 1K word long, and the external I/O pages have their appropriate memory page. own select pin (IOMS). Pages 0–7 of I/O memory space reside • The Program Sequencer generates the addresses for on-chip and contain the configuration registers for the peripher- instruction fetches. For relative addressing instructions, als. Both the core and DMA-capable peripherals can access the the program sequencer bases addresses for relative jumps, DSP’s entire memory map. calls, and loops on the 24-bit Program Counter (PC). In Internal (On-Chip) Memory direct addressing instructions (two-word instructions), The ADSP-2191M’s unified program and data memory space consists of 16M locations that are accessible through two 24-bit address buses, the PMA and DMA buses. The DSP uses slightly REV. A –5–

ADSP-2191M the instruction provides an immediate 24-bit address 8-bit I/O page (IOPG) register and a 10-bit immediate value value. The PC allows linear addressing of the full 24-bit supplied in the instruction. Both the ADSP-219x core and a Host address range. (through the Host Port Interface) can access I/O memory space. • For indirect jumps and calls that use a 16-bit DAG Boot Memory Space address register for part of the branch address, the Boot memory space consists of one off-chip bank with 63 pages. Program Sequencer relies on an 8-bit Indirect Jump page The BMS memory bank pin selects boot memory space. Both (IJPG) register to supply the most significant eight the ADSP-219x core and DMA-capable peripherals can access address bits. Before a cross page jump or call, the program the DSP’s off-chip boot memory space. After reset, the DSP must set the program sequencer’s IJPG register to the always starts executing instructions from the on-chip boot ROM. appropriate memory page. Depending on the boot configuration, the boot ROM code can The ADSP-2191M has 1K word of on-chip ROM that holds start booting the DSP from boot memory. For more information, boot routines. If peripheral booting is selected, the DSP starts see “Booting Modes” on Page11. executing instructions from the on-chip boot ROM, which starts the boot process from the selected peripheral. For more informa- Interrupts The interrupt controller lets the DSP respond to 17 interrupts tion, see “Booting Modes” on Page11. The on-chip boot ROM with minimum overhead. The controller implements an interrupt is located on Page255 in the DSP’s memory space map. priority scheme as shown in Table1. Applications can use the External (Off-Chip) Memory unassigned slots for software and peripheral interrupts. Each of the ADSP-2191M’s off-chip memory spaces has a Table2 shows the ID and priority at reset of each of the periph- separate control register, so applications can configure unique eral interrupts. To assign the peripheral interrupts a different access parameters for each space. The access parameters include priority, applications write the new priority to their correspond- read and write wait counts, waitstate completion mode, I/O clock ing control bits (determined by their ID) in the Interrupt Priority divide ratio, write hold time extension, strobe polarity, and data Control register. The peripheral interrupt’s position in the bus width. The core clock and peripheral clock ratios influence IMASK and IRPTL register and its vector address depend on its the external memory access strobe widths. For more information, priority level, as shown in Table1. Because the IMASK and see “Clock Signals” on Page11. The off-chip memory IRPTL registers are limited to 16 bits, any peripheral interrupts spacesare: assigned a priority level of 11 are aliased to the lowest priority bit • External memory space (MS3–0 pins) position (15) in these registers and share vector address • I/O memory space (IOMS pin) 0x0001E0. • Boot memory space (BMS pin) Table 1. Interrupt Priorities/Addresses All of these off-chip memory spaces are accessible through the IMASK/ Vector External Port, which can be configured for data widths of Interrupt IRPTL Address1 8 or 16 bits. Emulator (NMI)— NA NA External Memory Space Highest Priority External memory space consists of four memory banks. These Reset (NMI) 0 0x00 0000 banks can contain a configurable number of 64K word pages. At Power-Down (NMI) 1 0x00 0020 reset, the page boundaries for external memory have Bank0 Loop and PC Stack 2 0x00 0040 containing Pages1−63, Bank1 containing Pages64−127, Bank2 Emulation Kernel 3 0x00 0060 containing Pages128−191, and Bank3 that contains Pages User Assigned Interrupt 4 0x00 0080 192−254. The MS3–0 memory bank pins select Banks 3–0, User Assigned Interrupt 5 0x00 00A0 respectively. The external memory interface is byte-addressable User Assigned Interrupt 6 0x00 00C0 and decodes the 8 MSBs of the DSP program address to select User Assigned Interrupt 7 0x00 00E0 one of the four banks. Both the ADSP-219x core and DMA-capa- User Assigned Interrupt 8 0x00 0100 ble peripherals can access the DSP’s external memory space. User Assigned Interrupt 9 0x00 0120 I/O Memory Space User Assigned Interrupt 10 0x00 0140 The ADSP-2191M supports an additional external memory User Assigned Interrupt 11 0x00 0160 called I/O memory space. This space is designed to support User Assigned Interrupt 12 0x00 0180 simple connections to peripherals (such as data converters and User Assigned Interrupt 13 0x00 01A0 external registers) or to bus interface ASIC data registers. I/O User Assigned Interrupt 14 0x00 01C0 space supports a total of 256K locations. The first 8K addresses User Assigned Interrupt— 15 0x00 01E0 are reserved for on-chip peripherals. The upper 248K addresses Lowest Priority are available for external peripheral devices. The DSP’s instruc- 1These interrupt vectors start at address 0x10000 when the DSP is in tion set provides instructions for accessing I/O space. These “no-boot,” run from external memory mode. instructions use an 18-bit address that is assembled from an –6– REV. A

ADSP-2191M Table 2. Peripheral Interrupts and Priority at Reset The following instructions globally enable or disable interrupt servicing, regardless of the state of IMASK. Reset ENA INT; Interrupt ID Priority DIS INT; Slave DMA/Host Port Interface 0 0 At reset, interrupt servicing is disabled. SPORT0 Receive 1 1 SPORT0 Transmit 2 2 For quick servicing of interrupts, a secondary set of DAG and SPORT1 Receive 3 3 computational registers exist. Switching between the primary SPORT1 Transmit 4 4 and secondary registers lets programs quickly service interrupts, SPORT2 Receive/SPI0 5 5 while preserving the DSP’s state. SPORT2 Transmit/SPI1 6 6 DMA Controller UART Receive 7 7 The ADSP-2191M has a DMA controller that supports UART Transmit 8 8 automated data transfers with minimal overhead for the DSP Timer 0 9 9 core. Cycle stealing DMA transfers can occur between the Timer 1 10 10 ADSP-2191M’s internal memory and any of its DMA-capable Timer 2 11 11 peripherals. Additionally, DMA transfers can be accomplished Programmable Flag A (any PFx) 12 11 between any of the DMA-capable peripherals and external Programmable Flag B (any PFx) 13 11 devices connected to the external memory interface. DMA-capa- Memory DMA port 14 11 ble peripherals include the Host port, SPORTs, SPI ports, and UART. Each individual DMA-capable peripheral has a dedicated Interrupt routines can either be nested with higher priority inter- DMA channel. To describe each DMA sequence, the DMA con- rupts taking precedence or processed sequentially. Interrupts can troller uses a set of parameters—called a DMA descriptor. When be masked or unmasked with the IMASK register. Individual successive DMA sequences are needed, these DMA descriptors interrupt requests are logically ANDed with the bits in IMASK; can be linked or chained together, so the completion of one DMA the highest priority unmasked interrupt is then selected. The sequence auto-initiates and starts the next sequence. DMA emulation, power-down, and reset interrupts are nonmaskable sequences do not contend for bus access with the DSP core; with the IMASK register, but software can use the DIS INT instead DMAs “steal” cycles to access memory. instruction to mask the power-down interrupt. All DMA transfers use the DMA bus shown in the functional The Interrupt Control (ICNTL) register controls interrupt block diagram onPage1. Because all of the peripherals use the nesting and enables or disables interrupts globally. same bus, arbitration for DMA bus access is needed. The arbi- The general-purpose Programmable Flag (PFx) pins can be con- tration for DMA bus access appears in Table4. figured as outputs, can implement software interrupts, and (as inputs) can implement hardware interrupts. Programmable Flag Table 4. I/O Bus Arbitration Priority pin interrupts can be configured for level-sensitive, single DMA Bus Master Arbitration Priority edge-sensitive, or dual edge-sensitiveoperation. SPORT0 Receive DMA 0—Highest Table 3. Interrupt Control (ICNTL) Register Bits SPORT1 Receive DMA 1 SPORT2 Receive DMA 2 Bit Description SPORT0 Transmit DMA 3 0–3 Reserved SPORT1 Transmit DMA 4 4 Interrupt Nesting Enable SPORT2 Transmit DMA 5 5 Global Interrupt Enable SPI0 Receive/Transmit DMA 6 6 Reserved SPI1 Receive/Transmit DMA 7 7 MAC-Biased Rounding Enable UART Receive DMA 8 8–9 Reserved UART Transmit DMA 9 10 PC Stack Interrupt Enable Host Port DMA 10 11 Loop Stack Interrupt Enable Memory DMA 11—Lowest 12–15 Reserved Host Port The IRPTL register is used to force and clear interrupts. On- The ADSP-2191M’s Host port functions as a slave on the chip stacks preserve the processor status and are automatically external bus of an external Host. The Host port interface lets a maintained during interrupt handling. To support interrupt, Host read from or write to the DSP’s memory space, boot space, loop, and subroutine nesting, the PC stack is 33levels deep, the or internal I/O space. Examples of Hosts include external micro- loop stack is eight levels deep, and the status stack is 16levels controllers, microprocessors, orASICs. deep. To prevent stack overflow, the PC stack can generate a The Host port is a multiplexed address and data bus that provides stack-level interrupt if the PC stack falls below three locations full both an 8-bit and a 16-bit data path and operates using an asyn- or rises above 28 locationsfull. chronous transmission protocol. Through this port, an off-chip REV. A –7–

ADSP-2191M Host can directly access the DSP’s entire memory space map, The functional modes selected by HPCR [7:6] are as follows boot memory space, and internal I/O space. To access the DSP’s (assuming active high signal): internal memory space, a Host steals one cycle per access from • ACK Mode—Acknowledge is active on strobes; HACK the DSP. A Host access to the DSP’s external memory uses the goes high from the leading edge of the strobe to indicate external port interface and does not stall (or steal cycles from) when the access can complete. After the Host samples the the DSP’s core. Because a Host can access internal I/O memory HACK active, it can complete the access by removing the space, a Host can control any of the DSP’s I/O mapped strobe.The Host port then removes theHACK. peripherals. • Ready Mode—Ready active on strobes, goes low to insert The Host port is most efficient when using the DSP as a slave waitstate during the access.If the Host port cannot and uses DMA to automate the incrementing of addresses for complete the access, it deasserts the HACK/READY line. these accesses. In this case, an address does not have to be trans- In this case, the Host has to extend the access by keeping ferred from the Host for every datatransfer. the strobe asserted. When the Host samples the HACK asserted, it can then proceed and complete the access by Host Port Acknowledge (HACK) Modes deasserting the strobe. The Host port supports a number of modes (or protocols) for generating a HACK output for the host. The host selects ACK While in Address Cycle Control (ACC) mode and the ACK or or Ready modes using the HACK_P and HACK pins. The Host Ready acknowledge modes, the HACK is returned active for any port also supports two modes for address control: Address Latch address cycle. Enable (ALE) and Address Cycle Control (ACC) modes. The Host Port Chip Selects DSP auto-detects ALE versus ACC mode from the HALE and There are two chip-select signals associated with the Host port: HWR inputs. HCMS and HCIOMS. The Host Chip Memory Select (HCMS) The Host port HACK signal polarity is selected (only at reset) as lets the Host select the DSP and directly access the DSP’s inter- active high or active low, depending on the value driven on the nal/external memory space or boot memory space. The Host HACK_P pin.The HACK polarity is stored into the Host port Chip I/O Memory Select (HCIOMS) lets the Host select the configuration register as a read only bit. DSP and directly access the DSP’s internal I/O memory space. The DSP uses HACK to indicate to the Host when to complete Before starting a direct access, the Host configures Host port an access. For a read transaction, a Host can proceed and interface registers, specifying the width of external data bus complete an access when valid data is present in the read buffer (8- or 16-bit) and the target address page (in the IJPG register). and the Host port is not busy doing a write. For a write transac- The DSP generates the needed memory select signals during the tions, a Host can complete an access when the write buffer is not access, based on the target address. The Host port interface full and the Host port is not busy doing a write. combines the data from one, two, or three consecutive Host Two mode bits in the Host Port configuration register HPCR accesses (up to one 24-bit value) into a single DMA bus access [7:6] define the functionality of the HACK line. HPCR6 is ini- to prefetch Host direct reads or to post direct writes. During tialized at reset based on the values driven on HACK and assembly of larger words, the Host port interface asserts ACK for HACK_P pins (shown in Table5); HPCR7 is always cleared (0) each byte access that does not start a read or complete a write. at reset. HPCR [7:6] can be modified after reset by a write access Otherwise, the Host port interface asserts ACK when it has to the Host port configurationregister. completed the memory access successfully. Table 5. Host Port Acknowledge Mode Selection DSP Serial Ports (SPORTs) The ADSP-2191M incorporates three complete synchronous Values Driven At HPCR [7:6] serial ports (SPORT0, SPORT1, and SPORT2) for serial and Reset Initial Values multiprocessor communications. The SPORTs support the Acknowledge following features: HACK_P HACK Bit 7 Bit 6 Mode 0 0 0 1 Ready Mode • Bidirectional operation—each SPORT has independent 0 1 0 0 ACK Mode transmit and receive pins. 1 0 0 0 ACK Mode • Double-buffered transmit and receive ports—each port 1 1 0 1 Ready Mode has a data register for transferring data words to and from memory and shift registers for shifting data in and out of the data registers. • Clocking—each transmit and receive port can either use an external serial clock (40 MHz) or generate its own, in frequencies ranging from 19Hz to 40MHz. • Word length—each SPORT supports serial data words from 3 to 16 bits in length transferred in Big Endian (MSB) or Little Endian (LSB) format. –8– REV. A

ADSP-2191M • Framing—each transmit and receive port can run with or During transfers, the SPI ports simultaneously transmit and without frame sync signals for each data word. Frame sync receive by serially shifting data in and out on their two serial data signals can be generated internally or externally, active lines. The serial clock line synchronizes the shifting and sampling high or low, and with either of two pulsewidths and early of data on the two serial data lines. or late frame sync. UART Port • Companding in hardware—each SPORT can perform The UART port provides a simplified UART interface to another A-law or µ-law companding according to ITU recommen- peripheral or Host. It performs full duplex, asynchronous dation G.711. Companding can be selected on the transfers of serial data. Options for the UART include support transmit and/or receive channel of the SPORT without for 5–8 data bits; 1 or 2 stop bits; and none, even, or odd parity. additional latencies. The UART port supports two modes ofoperation: • DMA operations with single-cycle overhead—each • Programmed I/O SPORT can automatically receive and transmit multiple buffers of memory data, one data word each DSP cycle. The DSP’s core sends or receives data by writing or Either the DSP’s core or a Host processor can link or chain reading I/O-mapped THR or RBR registers, respectively. sequences of DMA transfers between a SPORT and The data is double-buffered on both transmit and receive. memory. The chained DMA can be dynamically allocated • DMA (direct memory access) and updated through the DMA descriptors (DMA The DMA controller transfers both transmit and receive transfer parameters) that set up the chain. data. This reduces the number and frequency of inter- • Interrupts—each transmit and receive port generates an rupts required to transfer data to and from memory. The interrupt upon completing the transfer of a data word or UART has two dedicated DMA channels. These DMA after transferring an entire data buffer or buffers through channels have lower priority than most DMA channels DMA. because of their relatively low servicerates. • Multichannel capability—each SPORT supports the The UART’s baud rate (see following equation for UART clock H.100 standard. rate calculation), serial data format, error code generation and status, and interrupts are programmable: Serial Peripheral Interface (SPI) Ports The DSP has two SPI-compatible ports that enable the DSP to • Supported bit rates range from 9.5 bits to 5Mbits per communicate with multiple SPI-compatible devices. These ports second (80MHz peripheral clock). are multiplexed with SPORT2, so either SPORT2 or the SPI • Supported data formats are 7- to 12-bit frames. ports are active, depending on the state of the OPMODE pin • Transmit and receive status can be configured to generate during hardware reset. maskable interrupts to the DSP’s core. The SPI interface uses three pins for transferring data: two data The timers can be used to provide a hardware-assisted autobaud pins (Master Output-Slave Input, MOSIx, and Master detection mechanism for the UART interface. Input-Slave Output, MISOx) and a clock pin (Serial Clock, SCKx). Two SPI chip select input pins (SPISSx) let other SPI devices select the DSP, and fourteen SPI chip select output pins UART Clock Rate = H------C----L-----K--- 16×D (SPIxSEL7–1) let the DSP select other SPI devices. The SPI select pins are reconfigured Programmable Flag pins. Using Where D is the programmable divisor = 1 to 65536. these pins, the SPI ports provide a full duplex, synchronous serial interface, which supports both master and slave modes and mul- Programmable Flag (PFx) Pins timaster environments. The ADSP-2191M has 16 bidirectional, general-purpose I/O, Each SPI port’s baud rate and clock phase/polarities are program- Programmable Flag (PF15–0) pins. The PF7–0 pins are mable (see equation below for SPI clock rate calculation), and dedicated to general-purpose I/O. The PF15–8 pins serve either each has an integrated DMA controller, configurable to support as general-purpose I/O pins (if the DSP is connected to an 8-bit both transmit and receive data streams. The SPI’s DMA control- external data bus) or serve as DATA15–8 lines (if the DSP is ler can only service unidirectional accesses at any given time. connected to a 16-bit external data bus). The Programmable Flag pins have special functions for clock multiplier selection and for SPI port operation. For more information, see Serial Peripheral HCLK SPI Clock Rate = -------------------------------------- 2×SPIBAUD REV. A –9–

ADSP-2191M Interface (SPI) Ports on Page9 and Clock Signals on Page11. To enter Idle mode, the DSP can execute the IDLE instruction Ten memory-mapped registers control operation of the Program- anywhere in code. To exit Idle mode, the DSP responds to an mable Flag pins: interrupt and (after two cycles of latency) resumes executing • Flag Direction register instructions with the instruction after the IDLE. Specifies the direction of each individual PFx pin as input Power-Down Core Mode or output. When the ADSP-2191M is in Power-Down Core mode, the DSP • Flag Control and Status registers core clock is off, but the DSP retains the contents of the pipeline and keeps the PLL running. The peripheral bus keeps running, Specify the value to drive on each individual PFx output letting the peripherals receive data. pin. As input, software can predicate instruction To enter Power-Down Core mode, the DSP executes an IDLE execution on the value of individual PFx input pins instruction after performing the following tasks: captured in this register. One register sets bits, and one register clears bits. • Enter a power-down interrupt service routine • Flag Interrupt Mask registers • Check for pending interrupts and I/O serviceroutines Enable and disable each individual PFx pin to function • Clear (= 0) the PDWN bit in the PLLCTL register as an interrupt to the DSP’s core. One register sets bits to • Clear (= 0) the STOPALL bit in the PLLCTLregister enable interrupt function, and one register clears bits to • Set (= 1) the STOPCK bit in the PLLCTL register disable interrupt function. Input PFx pins function as hardware interrupts, and output PFx pins function as To exit Power-Down Core mode, the DSP responds to an software interrupts—latching in the IMASK and IRPTL interrupt and (after two cycles of latency) resumes executing registers. instructions with the instruction after the IDLE. • Flag Interrupt Polarity register Power-Down Core/Peripherals Mode Specifies the polarity (active high or low) for interrupt When the ADSP-2191M is in Power-Down Core/Peripherals sensitivity on each individual PFx pin. mode, the DSP core clock and peripheral bus clock are off, but • Flag Sensitivity registers the DSP keeps the PLL running. The DSP does not retain the contents of the instruction pipeline.The peripheral bus is Specify whether individual PFx pins are level- or stopped, so the peripherals cannot receive data. edge-sensitive and specify—if edge-sensitive—whether To enter Power-Down Core/Peripherals mode, the DSP executes just the rising edge or both the rising and falling edges of an IDLE instruction after performing the followingtasks: the signal are significant. One register selects the type of sensitivity, and one register selects which edges are signif- • Enter a power-down interrupt service routine icant for edge-sensitivity. • Check for pending interrupts and I/O serviceroutines Low Power Operation • Clear (= 0) the PDWN bit in the PLLCTL register The ADSP-2191M has four low power options that significantly • Set (= 1) the STOPALL bit in the PLLCTLregister reduce the power dissipation when the device operates under To exit Power-Down Core/Peripherals mode, the DSP responds standby conditions. To enter any of these modes, the DSP to a wake-up event and (after five to six cycles of latency) resumes executes an IDLE instruction. The ADSP-2191M uses configu- executing instructions with the instruction after the IDLE. ration of the PDWN, STOPCK, and STOPALL bits in the PLLCTL register to select between the low power modes as the Power-Down All Mode DSP executes the IDLE. Depending on the mode, an IDLE shuts When the ADSP-2191M is in Power-Down All mode, the DSP off clocks to different parts of the DSP in the different modes. core clock, the peripheral clock, and the PLL are all stopped. The The low power modes are: DSP does not retain the contents of the instruction pipeline. The • Idle peripheral bus is stopped, so the peripherals cannot receive data. • Power-Down Core To enter Power-Down All mode, the DSP executes an IDLE instruction after performing the following tasks: • Power-Down Core/Peripherals • Power-Down All • Enter a power-down interrupt service routine • Check for pending interrupts and I/O serviceroutines Idle Mode • Set (= 1) the PDWN bit in the PLLCTL register When the ADSP-2191M is in Idle mode, the DSP core stops executing instructions, retains the contents of the instruction To exit Power-Down Core/Peripherals mode, the DSP responds pipeline, and waits for an interrupt. The core clock and peripheral to an interrupt and (after 500 cycles to restabilize the PLL) clock continue running. resumes executing instructions with the instruction after the IDLE. –10– REV. A

ADSP-2191M Clock Signals The ADSP-2191M can be clocked by a crystal oscillator or a 1M(cid:3) buffered, shaped clock derived from an external clock oscillator. If a crystal oscillator is used, the crystal should be connected 25MHz across the CLKIN and XTAL pins, with two capacitors and a CLKIN XTAL CLKOUT 1MΩ shunt resistor connected as shown in Figure3. Capacitor MSEL0(PF0) values are dependent on crystal type and should be specified by VDD ADSP-2196M the crystal manufacturer. A parallel-resonant, fundamental fre- quency, microprocessor-grade crystal should be used for this MSEL1(PF1) VDD configuration. MSEL2(PF2) If a buffered, shaped clock is used, this external clock connects to the DSP’s CLKIN pin. CLKIN input cannot be halted, RUNTIME changed, or operated below the specified frequency during PF PINI/O MSEL3(PF3) normal operation. When an external clock is used, the XTAL input must be left unconnected. MSEL4(PF4) The DSP provides a user-programmable 1(cid:1) to 32(cid:1) multiplica- tion of the input clock, including some fractional values, to MSEL5(PF5) support 128 external to internal (DSP core) clock ratios. The THEPULL-UP/PULL-DOWN MSEL6–0, BYPASS, and DF pins decide the PLL multiplication MSEL6(PF6) RESISTORSONTHEMSEL, DF,ANDBYPASSPINS factor at reset. At runtime, the multiplication factor can be con- SELECTTHECORECLOCK trolled in software. The combination of pullup and pull-down DF(PF7) RATIO. resistors in Figure3 sets up a core clock ratio of6:1, which HERE,THESELECTION(6:1) AND25MHzINPUTCLOCK produces a 150MHz core clock from the 25MHz input. For BYPASS PRODUCEA150MHzCORE other clock multiplier settings, see the ADSP-219x/ADSP-2191 CLOCK. DSP Hardware Reference. RESET RESET SOURCE The peripheral clock is supplied to the CLKOUT pin. All on-chip peripherals for the ADSP-2191M operate at the rate Figure 3. External Crystal Connections set by the peripheral clock. The peripheral clock is either equal to the core clock rate or one-half the DSP core clock rate. This The master reset sets all internal stack pointers to the empty stack selection is controlled by the IOSEL bit in the PLLCTL register. condition, masks all interrupts, and resets all registers to their The maximum core clock is160MHz and the maximum periph- default values (where applicable). When RESET is released, if eral clock is80MHz—the combination of the input clock and there is no pending bus request and the chip is configured for core/peripheral clock ratios may not exceed these limits. booting, the boot-loading sequence is performed. Program control jumps to the location of the on-chip boot ROM Reset (0xFF0000). The RESET signal initiates a master reset of the ADSP-2191M. The RESET signal must be asserted during the powerup Power Supplies sequence to assure proper initialization. RESET during initial The ADSP-2191M has separate power supply connections for powerup must be held long enough to allow the internal clock to the internal (VDDINT) and external (VDDEXT) power supplies. The stabilize. internal supply must meet the 2.5V requirement. The external supply must be connected to a 3.3V supply. All external supply The powerup sequence is defined as the total time required for pins must be connected to the same supply. the crystal oscillator circuit to stabilize after a valid V is applied DD to the processor, and for the internal phase-locked loop (PLL) to Power-Up Sequence lock onto the specific crystal frequency. A minimum of 100µs Power up together the two supplies V and V . If they DDEXT DDINT ensures that the PLL has locked, but does not include the crystal cannot be powered up together, power up the internal (core) oscillator start-up time. During this powerup sequence the supply first (powering up the core supply first reduces the risk of RESET signal should be held low. On any subsequent resets, the latchup events. RESET signal must meet the minimum pulsewidth specifica- tion,t . Booting Modes WRST The ADSP-2191M has five mechanisms (listed in Table6) for The RESET input contains some hysteresis. If using an RC automatically loading internal program memory afterreset. Two circuit to generate your RESET signal, the circuit should use an no-boot modes are also supported. external Schmidt trigger. REV. A –11–

ADSP-2191M Table 6. Select Boot Mode (OPMODE, BMODE1, and • Execute from memory external 8 bits (No Boot)— BMODE0) Execution starts from Page1 of external memory space, packing either 8- or 16-bit external data into 24-bit DE E1 E0 internal data. The External Port Interface is config- O D D ured for the default clock multiplier (128) and read M O O P M M waitstates (7). O B B Function • Boot from UART—Using an autobaud handshake sequence, a boot-stream-formatted program is down- 0 0 0 Execute from external memory 16bits loaded by the Host. The Host agent selects a baud rate (NoBoot) within the UART’s clocking capabilities. After a hardware 0 0 1 Boot from EPROM reset, the DSP’s UART expects a 0xAA character (eight 0 1 0 Boot from Host bits data, one start bit, one stop bit, no parity bit) on the 0 1 1 Reserved RXD pin to determine the bit rate; and then replies with 1 0 0 Execute from external memory 8bits an OK string. Once the host receives this OK it downloads (No Boot) the boot stream without further handshake.The UART 1 0 1 Boot from UART boot routine is located in internal ROM memory space 1 1 0 Boot from SPI, up to 4Kbits and uses the top 16 locations of Page0 program memory 1 1 1 Boot from SPI, >4Kbits up to and the top 272 locations of Page0 data memory. 512Kbits • Boot from SPI, up to 4K bits—The SPI0 port uses the SPI0SEL1 (reconfigured PF2) output pin to select a The OPMODE, BMODE1, and BMODE0 pins, sampled single serial EEPROM device, submits a read command during hardware reset, and three bits in the Reset Configuration at address 0x00, and begins clocking consecutive data into Register implement these modes: internal or external memory. Use only SPI-compatible • Execute from memory external 16 bits—The memory EEPROMs of ≤4K bit (12-bit address range). The SPI0 boot routine located in boot ROM memory space boot routine located in internal ROM memory space executes a boot-stream-formatted program located at executes a boot-stream-formatted program, using the top address 0x010000 of boot memory space, packing 16-bit 16 locations of Page0 program memory and the top 272 external data into 24-bit internal data. The External Port locations of Page0 data memory. The SPI boot configu- Interface is configured for the default clock multiplier ration is SPIBAUD0=60 (decimal), CPHA=1, (128) and read waitstates (7). CPOL=1, 8-bit data, and MSB first. • Boot from EPROM—The EPROM boot routine located • Boot from SPI, from >4K bits to 512K bits—The SPI0 in boot ROM memory space fetches a boot-stream-for- port uses the SPI0SEL1 (re-configured PF2) output pin matted program located at physical address 0x00 0000 of to select a single serial EEPROM device, submits a read boot memory space, packing 8- or 16-bit external data command at address 0x00, and begins clocking consecu- into 24-bit internal data. The External Port Interface is tive data into internal or external memory. Use only configured for the default clock multiplier (32) and read SPI-compatible EEPROMs of ≥4K bit (16-bit address waitstates (7). range). The SPI0 boot routine, located in internal ROM • Boot from Host—The (8- or 16-bit) Host downloads a memory space, executes a boot-stream-formatted boot-stream-formatted program to internal or external program, using the top 16 locations of Page0 program memory. The Host’s boot routine is located in internal memory and the top 272 locations of Page0 data memory. ROM memory space and uses the top 16 locations of As indicated in Table6, the OPMODE pin has a dual role, acting Page0 program memory and the top 272 locations of as a boot mode select during reset and determining SPORT or Page0 data memory. SPI operation at runtime. If the OPMODE pin at reset is the The internal boot ROM sets semaphore A (an IO register opposite of what is needed in an application during runtime, the within the Host port) and then polls until the semaphore application needs to set the OPMODE bit appropriately during is reset. Once detected, the internal boot ROM will remap runtime prior to using the corresponding peripheral. the interrupt vector table to Page0 internal memory and jump to address 0x00 0000 internal memory. From the Bus Request and Bus Grant point of view of the host interface, an external host has The ADSP-2191M can relinquish control of the data and ad- full control of the DSP’s memory map. The Host has the dress buses to an external device. When the external device freedom to directly write internal memory, external requires access to the bus, it asserts the bus request (BR) signal. memory, and internal I/O memory space. The DSP core The (BR) signal is arbitrated with core and peripheral requests. execution is held off until the Host clears the semaphore External Bus requests have the lowest priority. If no other internal register. This strategy allows the maximum flexibility for request is pending, the external bus request will be granted. the Host to boot in the program and data code, by leaving it up to theprogrammer. –12– REV. A

ADSP-2191M Because of synchronizer and arbitration delays, bus grants will Development Tools be provided with a minimum of three peripheral clock delays. The ADSP-2191M is supported with a complete set of software ADSP-2191M DSPs will respond to the bus grant by: and hardware development tools, including Analog Devices • Three-stating the data and address buses and the MS3–0, emulators and VisualDSP++® development environment. The same emulator hardware that supports other ADSP-219x DSPs, BMS, IOMS, RD, and WR output drivers. also fully emulates the ADSP-2191M. • Asserting the bus grant (BG) signal. The VisualDSP++ project management environment lets pro- The ADSP-2191M will halt program execution if the bus is grammers develop and debug an application. This environment granted to an external device and an instruction fetch or data includes an easy-to-use assembler that is based on an algebraic read/write request is made to external general-purpose or periph- syntax; an archiver (librarian/library builder), a linker, a loader, eral memory spaces. If an instruction requires two external a cycle-accurate instruction-level simulator, a C/C++ compiler, memory read accesses, bus requests will not be granted between and a C/C++ run-time library that includes DSP and mathemat- the two accesses. If an instruction requires an external memory ical functions. Two key points for these tools are: read and an external memory write access, the bus may be • Compiled ADSP-219x C/C++ code efficiency—the granted between the two accesses. The external memory compiler has been developed for efficient translation of interface can be configured so that the core will have exclusive C/C++ code to ADSP-219x assembly. The DSP has use of the interface. DMA and Bus Requests will be granted. architectural features that improve the efficiency of When the external device releases BR, the DSP releases BG and compiledC/C++code. continues program execution from the point at which it stopped. • ADSP-218x family code compatibility—The assembler The bus request feature operates at all times, even while the DSP has legacy features to ease the conversion of existing is booting and RESET is active. ADSP-218x applications to the ADSP-219x. The ADSP-2191M asserts the BGH pin when it is ready to start Debugging both C/C++ and assembly programs with the Visu- another external port access, but is held off because the bus was alDSP++ debugger, programmers can: previously granted. This mechanism can be extended to define more complex arbitration protocols for implementing more • View mixed C/C++ and assembly code (interleaved elaborate multimaster systems. source and object information) • Insert break points Instruction Set Description The ADSP-2191M assembly language instruction set has an • Set conditional breakpoints on registers, memory, and algebraic syntax that was designed for ease of coding and read- stacks ability. The assembly language, which takes full advantage of the • Trace instruction execution processor’s unique architecture, offers the following benefits: • Perform linear or statistical profiling of program • ADSP-219x assembly language syntax is a superset of and execution source-code-compatible (except for two data registers • Fill, dump, and graphically plot the contents of memory and DAG base address registers) with ADSP-218x family • Source level debugging syntax. It may be necessary to restructure ADSP-218x programs to accommodate the ADSP-2191M’s unified • Create custom debugger windows memory space and to conform to its interrupt vector map. The VisualDSP++ IDE lets programmers define and manage • The algebraic syntax eliminates the need to remember DSP software development. Its dialog boxes and property pages cryptic assembler mnemonics. For example, a typical let programmers configure and manage all of the ADSP-219x arithmetic add instruction, such as AR=AX0+AY0, development tools, including the syntax highlighting in the Visu- resembles a simple equation. alDSP++ editor. This capability permits: • Every instruction, but two, assembles into a single, 24-bit • Control how the development tools process inputs and word that can execute in a single instruction cycle. The generate outputs. exceptions are two dual word instructions. One writes 16- • Maintain a one-to-one correspondence with the tool’s or 24-bit immediate data to memory, and the other is an command line switches. absolute jump/call with the 24-bit address specified in the Analog Devices DSP emulators use the IEEE 1149.1 JTAG test instruction. access port of the ADSP-2191M processor to monitor and • Multifunction instructions allow parallel execution of an control the target board processor during emulation. The arithmetic, MAC, or shift instruction with up to two emulator provides full-speed emulation, allowing inspection and fetches or one write to processor memory space during a modification of memory, registers, and processor stacks. Nonin- single instruction cycle. trusive in-circuit emulation is assured by the use of the processor’s • Program flow instructions support a wider variety of con- JTAG interface—the emulator does not affect target system ditional and unconditional jumps/calls and a larger set of loading or timing. conditions on which to base execution of conditional instructions. REV. A –13–

ADSP-2191M In addition to the software and hardware development tools As can be seen in Figure4, there are two sets of signals on the available from Analog Devices, third parties provide a wide range header. There are the standard JTAG signals TMS, TCK, TDI, of tools supporting the ADSP-219x processor family. Hardware TDO, TRST, and EMU used for emulation purposes (via an tools include ADSP-219x PC plug-in cards. Third party software emulator). There are also secondary JTAG signals BTMS, tools include DSP libraries, real-time operating systems, and BTCK, BTDI, and BTRST that are optionally used for block diagram design tools. board-level (boundary scan) testing. When the emulator is not connected to this header, place jumpers Designing an Emulator-Compatible DSP Board across BTMS, BTCK, BTRST, and BTDI as shown in Figure5. (Target) The White Mountain DSP (Product Line of Analog Devices, This holds the JTAG signals in the correct state to allow the DSP Inc.) family of emulators are tools that every DSP developer to run free. Remove all the jumpers when connecting the needs to test and debug hardware and software systems. Analog emulator to the JTAG header. Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG DSP. The emulator uses the TAP to access the internal features of the DSP, allowing the developer to load 1 2 GND EMU code, set breakpoints, observe variables, observe memory, and examine registers. The DSP must be halted to send data and 3 4 commands, but once an operation has been completed by the KEY(NOPIN) GND emulator, the DSP system is set running at full speed with no 5 6 BTMS TMS impact on system timing. To use these emulators, the target’s design must include the 7 8 BTCK TCK interface between an Analog Devices JTAG DSP and the emulation header on a custom DSP target board. 9 10 BTRST TRST Target Board Header 11 12 The emulator interface to an Analog Devices JTAG DSP is a BTDI TDI 14-pin header, as shown in Figure4. The customer must supply 13 14 this header on the target board in order to communicate with the GND TDO emulator. The interface consists of a standard dual row 0.025" square post header, set on 0.1"(cid:1)0.1" spacing, with a minimum TOPVIEW post length of 0.235". Pin 3 is the key position used to prevent Figure 5. JTAG Target Board Connector with No Local the pod from being inserted backwards. This pin must be clipped Boundary Scan on the target board. Also, the clearance (length, width, and height) around the header JTAG Emulator Pod Connector must be considered. Leave a clearance of at least 0.15" and 0.10" Figure6 details the dimensions of the JTAG pod connector at the around the length and width of the header, and reserve a height 14-pin target end. Figure7 displays the keep-out area for a target clearance to attach and detach the pod connector. board header. The keep-out area allows the pod connector to properly seat onto the target board header. This board area should contain no components (chips, resistors, capacitors, etc.). The dimensions are referenced to the center of the 0.25" square 1 2 GND EMU post pin. 3 4 KEY(NOPIN) GND 5 6 BTMS TMS 7 8 BTCK TCK 9 10 BTRST TRST 0.64" 11 12 BTDI TDI 13 14 GND TDO 0.88" TOPVIEW 0.24" Figure 4. JTAG Target Board Connector for JTAG Equipped Analog Devices DSP (Jumpers in Place) Figure 6. JTAG Pod Connector Dimensions –14– REV. A

ADSP-2191M Additional Information This data sheet provides a general overview of the ADSP-2191M architecture and functionality. For detailed information on the 0.10" core architecture of the ADSP-219x family, refer to the ADSP-219x/ADSP-2191 DSP Hardware Reference. For details on the instruction set, refer to the ADSP-219x Instruction Set 0.15" Reference. Figure 7. JTAG Pod Connector Keep-Out Area PIN FUNCTION DESCRIPTIONS ADSP-2191M pin definitions are listed in Table7. All Design-for-Emulation Circuit Information ADSP-2191M inputs are asynchronous and can be asserted For details on target board design issues including: single asynchronously to CLKIN (or to TCK for TRST). processor connections, multiprocessor scan chains, signal buff- ering, signal termination, and emulator pod logic, see the EE-68: Tie or pull unused inputs to VDDEXT or GND, except for Analog Devices JTAG Emulation Technical Reference on the Analog ADDR21–0, DATA15–0, PF7-0, and inputs that have internal Devices website (www.analog.com)—use site search on pull-up or pull-down resistors (TRST, BMODE0, BMODE1, “EE-68.” This document is updated regularly to keep pace with OPMODE, BYPASS, TCK, TMS, TDI, and RESET)—these improvements to emulator support. pins can be left floating. These pins have a logic-level hold circuit that prevents input from floating internally. The following symbols appear in the Type column of Table7: G = Ground, I=Input, O = Output, P=Power Supply, and T = Three-State. Table 7. Pin Function Descriptions Pin Type Function A21–0 O/T External Port Address Bus D7–0 I/O/T External Port Data Bus, least significant 8 bits D15 I/O/T Data 15 (if 16-bit external bus)/Programmable Flags 15 (if 8-bit external bus)/SPI1 Slave /PF15 I/O Select output 7 (if 8-bit external bus, when SPI1 enabled) /SPI1SEL7 I D14 I/O/T Data 14 (if 16-bit external bus)/Programmable Flags 14 (if 8-bit external bus)/SPI0 Slave /PF14 I/O Select output 7 (if 8-bit external bus, when SPI0 enabled) /SPI0SEL7 I D13 I/O/T Data 13 (if 16-bit external bus)/Programmable Flags 13 (if 8-bit external bus)/SPI1 Slave /PF12 I/O Select output 6 (if 8-bit external bus, when SPI1 enabled) /SPI1SEL6 I D12 I/O/T Data 12 (if 16-bit external bus)/Programmable Flags 12 (if 8-bit external bus)/SPI0 Slave /PF12 I/O Select output 6 (if 8-bit external bus, when SPI0 enabled) /SPI0SEL6 I D11 I/O/T Data 11 (if 16-bit external bus)/Programmable Flags 11 (if 8-bit external bus)/SPI1 Slave /PF11 I/O Select output 5 (if 8-bit external bus, when SPI1 enabled) /SPI1SEL5 I D10 I/O/T Data 10 (if 16-bit external bus)/Programmable Flags 10 (if 8-bit external bus)/SPI0 Slave /PF10 I/O Select output 5 (if 8-bit external bus, when SPI0 enabled) /SPI0SEL5 I D9 I/O/T Data 9 (if 16-bit external bus)/Programmable Flags 9 (if 8-bit external bus)/SPI1 Slave Select /PF9 I/O output 4 (if 8-bit external bus, when SPI1 enabled) /SPI1SEL4 I D8 I/O/T Data 8 (if 16-bit external bus)/Programmable Flags 8 (if 8-bit external bus)/SPI0 Slave Select /PF8 I/O output 4 (if 8-bit external bus, when SPI0 enabled) /SPI0SEL4 I PF7 I/O/T Programmable Flags 7/SPI1 Slave Select output 3 (when SPI0 enabled)/Divisor Frequency /SPI1SEL3 I (divisor select for PLL input during boot) /DF I PF6 I/O/T Programmable Flags 6/SPI0 Slave Select output 3 (when SPI0 enabled)/Multiplier Select 6 /SPI0SEL3 I (during boot) /MSEL6 I REV. A –15–

ADSP-2191M Table 7. Pin Function Descriptions (continued) Pin Type Function PF5 I/O/T Programmable Flags 5/SPI1 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 5 /SPI1SEL2 I (during boot) /MSEL5 I PF4 I/O/T Programmable Flags 4/SPI0 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 4 /SPI0SEL2 I (during boot) /MSEL4 I PF3 I/O/T Programmable Flags 3/SPI1 Slave Select output 1 (when SPI0 enabled)/Multiplier Select 3 /SPI1SEL1 I (during boot) /MSEL3 I PF2 I/O/T Programmable Flags 2/SPI0 Slave Select output 1 (when SPI0 enabled)/Multiplier Select 2 /SPI0SEL1 I (during boot) /MSEL2 I PF1 I/O/T Programmable Flags 1/SPI1 Slave Select input (when SPI1 enabled)/Multiplier Select 1 /SPISS1 I (during boot) /MSEL1 I PF0 I/O/T Programmable Flags 0/SPI0 Slave Select input (when SPI0 enabled)/Multiplier Select 0 /SPISS0 I (during boot) /MSEL0 I RD O/T External Port Read Strobe WR O/T External Port Write Strobe ACK I External Port Access Ready Acknowledge BMS O/T External Port Boot Space Select IOMS O/T External Port IO Space Select MS3–0 O/T External Port Memory Space Selects BR I External Port Bus Request BG O External Port Bus Grant BGH O External Port Bus Grant Hang HAD15–0 I/O/T Host Port Multiplexed Address and Data Bus HA16 I Host Port MSB of Address Bus HACK_P I Host Port ACK Polarity HRD I Host Port Read Strobe HWR I Host Port Write Strobe HACK O Host Port Access Ready Acknowledge HALE I Host Port Address Latch Strobe or Address Cycle Control HCMS I Host Port Internal Memory–Internal I/O Memory–Boot Memory Select HCIOMS I Host Port Internal I/O Memory Select CLKIN I Clock Input/Oscillator Input XTAL O Oscillator Output BMODE1–0 I Boot Mode 1–0. The BMODE1 and BMODE0 pins have 85kΩ internal pull-up resistors. OPMODE I Operating Mode. The OPMODE pin has a 85kΩ internal pull-up resistor. CLKOUT O Clock Output BYPASS I Phase-Lock-Loop (PLL) Bypass Mode. The BYPASS pin has a 85kΩ internal pull-up resistor. RCLK1–0 I/O/T SPORT1–0 Receive Clock RCLK2/SCK1 I/O/T SPORT2 Receive Clock/SPI1 Serial Clock RFS1–0 I/O/T SPORT1–0 Receive Frame Sync RFS2/MOSI1 I/O/T SPORT2 Receive Frame Sync/SPI1 Master-Output, Slave-Input Data TCLK1–0 I/O/T SPORT1–0 Transmit Clock TCLK2/SCK0 I/O/T SPORT2 Transmit Clock/SPI0 Serial Clock TFS1–0 I/O/T SPORT1–0 Transmit Frame Sync TFS2/MOSI0 I/O/T SPORT2 Transmit Frame Sync/SPI0 Master-Output, Slave-Input Data DR1–0 I/T SPORT1–0 Serial Data Receive DR2/MISO1 I/O/T SPORT2 Serial Data Receive/SPI1 Master-Input, Slave-Output Data DT1–0 O/T SPORT1–0 Serial Data Transmit DT2/MISO0 I/O/T SPORT2 Serial Data Transmit/SPI0 Master-Input, Slave-Output Data –16– REV. A

ADSP-2191M Table 7. Pin Function Descriptions (continued) Pin Type Function TMR2–0 I/O/T Timer Output or Capture RXD I UART Serial Receive Data TXD O UART Serial Transmit Data RESET I Processor Reset. Resets the ADSP-2191M to a known state and begins execution at the program memory location specified by the hardware reset vector address. The RESET input must be asserted (low) at powerup. The RESET pin has an 85kΩ internal pull-up resistor. TCK I Test Clock (JTAG). Provides a clock for JTAG boundary scan. The TCK pin has an 85kΩ internal pull-up resistor. TMS I Test Mode Select (JTAG). Used to control the test state machine. The TMS pin has an 85kΩ internal pull-up resistor. TDI I Test Data Input (JTAG). Provides serial data for the boundary scan logic. The TDI pin has a 85kΩ internal pull-up resistor. TDO O Test Data Output (JTAG). Serial scan output of the boundary scan path. TRST I Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after powerup or held low for proper operation of the ADSP-2191M. The TRST pin has a 65kΩ internal pull-down resistor. EMU O Emulation Status (JTAG). Must be connected to the ADSP-2191M emulator target board connector only. V P Core Power Supply. Nominally 2.5V dc and supplies the DSP’s core processor. (four pins) DDINT V P I/O Power Supply. Nominally 3.3V dc. (nine pins) DDEXT GND G Power Supply Return. (twelve pins) NC Do Not Connect. Reserved pins that must be left open and unconnected. REV. A –17–

ADSP-2191M SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS K Grade (Commercial) B Grade (Industrial) Parameter Test Conditions Min Max Min Max Unit V Internal (Core) Supply 2.37 2.63 2.37 2.63 V DDINT Voltage V External (I/O) Supply 2.97 3.6 2.97 3.6 V DDEXT Voltage V High Level Input Voltage @ V = max, 2.0 V +0.3 2.0 V +0.3 V IH DDINT DDEXT DDEXT V = max DDEXT V Low Level Input Voltage @ V = min, –0.3 +0.8 –0.3 +0.8 V IL DDINT V = min DDEXT T Ambient Operating 0 70 –40 +85 ºC AMB Temperature Specifications subject to change without notice. ELECTRICAL CHARACTERISTICS K and B Grades Parameter Test Conditions Min Typ Max Unit V High Level Output Voltage1 @ V = min, 2.4 V OH DDEXT I = –0.5 mA OH V Low Level Output Voltage1 @ V = min, 0.4 V OL DDEXT I = 2.0 mA OL I High Level Input Current2, 3 @ V = max, 10 µA IH DDEXT V = V max IN DD I Low Level Input Current3, 4 @ V = max, 10 µA IL DDEXT V = 0 V IN I High Level Input Current5 @ V = max, 30 100 µA IHP DDEXT V = V max IN DD I Low Level Input Current4 @ V = max, 20 70 µA ILP DDEXT V = 0 V IN I Three-State Leakage Current5 @ V = max, 10 µA OZH DDEXT V = V max IN DD I Three-State Leakage Current6 @ V = max, 10 µA OZL DDEXT V = 0 V IN C Input Capacitance6,7 f = 1 MHz, 8 pF IN IN T = 25°C, CASE V = 2.5V IN Specifications subject to change without notice. 1Applies to output and bidirectional pins: DATA15–0, ADDR21–0, HAD15–0, MS3–0, IOMS, RD, WR, CLKOUT, HACK, PF7–0, TMR2–0, BGH, BG, DT0, DT1, DT2/MISO0, TCLK0, TCLK1, TCLK2/SCK0, RCLK0, RCLK1, RCLK2/SCK1, TFS0, TFS1, TFS2/MOSI0, RFS0, RFS1, RFS2/MOSI1, BMS, TDO, TXD, EMU, DR2/MISO1. 2Applies to input pins: ACK, BR, HCMS, HCIOMS, HA16, HALE, HRD, HWR, CLKIN, DR0, DR1, RXD, HACK_P. 3Applies to input pins with internal pull-ups: BMODE0, BMODE1, OPMODE, BYPASS, TCK, TMS, TDI, RESET. 4Applies to input pin with internal pull-down: TRST. 5Applies to three-statable pins: DATA15–0, ADDR21–0, MS3–0, RD, WR, PF7–0, BMS, IOMS, TFSx, RFSx, TDO, EMU, TCLKx, RCLKx, DTx, HAD15–0, TMR2–0. 6Applies to all signal pins. 7Guaranteed, but not tested. –18– REV. A

ADSP-2191M ABSOLUTE MAXIMUM RATINGS V Internal (Core) Supply Voltage1. . . –0.3 V to +3.0 V DDINT V External (I/O) Supply Voltage. . . . –0.3 V to +4.6 V DDEXT V –V Input Voltage. . . . . . . . . . –0.5 V to V +0.5 V IL IH DDEXT V –V Output Voltage Swing. . . –0.5 V to V +0.5 V OL OH DDEXT T Storage Temperature Range. . . . . .–65ºC to +150ºC STORE T Lead Temperature of ST-144 (5 seconds) . . . .185ºC LEAD 1Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD SENSITIVITY CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2191M features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid perfor- mance degradation or loss of functionality. Power Dissipation Using the operation-versus-current information in Table8, designers can estimate the ADSP-2191M’s internal power supply (V ) DDINT input current for a specific application, according to the formula for I calculation beneath Table8. For calculation of external DDINT supply current and total supply current, see Power Dissipation on Page40. Table 8. Operation Types Versus Input Current K-Grade B-Grade I (mA) CCLK = 160 MHz I (mA)1 CCLK = 140 MHz DDINT DDINT Core Peripheral Core Peripheral Activity Typ1 Max2 Typ1 Max2 Typ1 Max2 Typ1 Max2 Power Down3 100 µA 600 µA 0 50 µA 100 µA 500 µA 0 50 µA Idle 14 1 2 5 8 1 2 4 7 Idle 25 1 2 60 70 1 2 55 62 Typical6 184 210 60 70 165 185 55 62 Peak7 215 240 60 70 195 210 55 62 1Test conditions: V = 2.50 V; HCLK (peripheral clock) frequency = CCLK/2 (core clock/2) frequency; T = 25ºC. DDINT AMB 2Test conditions: V = 2.65 V; HCLK (peripheral clock) frequency = CCLK/2 (core clock/2) frequency; T = 25ºC. DDINT AMB 3PLL, Core, peripheral clocks, and CLKIN are disabled. 4PLL is enabled and Core and peripheral clocks are disabled. 5Core CLK is disabled and peripheral clock is enabled. 6All instructions execute from internal memory. 50% of the instructions are repeat MACs with dual operand addressing, with changing data fetched using a linear address sequence. 50% of the instructions are type 3 instructions. 7All instructions execute from internal memory. 100% of the instructions are MACs with dual operand addressing, with changing data fetched using a linear address sequence. I = (%Typical×I )+(%Idle×I )+(%Power Down×I ) DDINT DDINT-TYPICAL DDINT-IDLE DDINT-PWRDWN REV. A –19–

ADSP-2191M TIMING SPECIFICATIONS This section contains timing information for the DSP’s external Timing requirements apply to signals that are controlled by signals. Use the exact information given. Do not attempt to derive circuitry external to the processor, such as the data input for a parameters from the addition or subtraction of other information. read operation.Timing requirements guarantee that the While addition or subtraction would yield meaningful results for processor operates correctly with other devices. an individual device, the values given in this data sheet reflect Clock In and Clock Out Cycle Timing statistical variations and worst cases. Consequently, parameters Table9 and Figure8 describe clock and reset operations. Com- cannot be added meaningfully to derive longer times. binations of CLKIN and clock multipliers must not select Switching characteristics specify how the processor changes its core/peripheral clocks in excess of 160/80 MHz for commercial signals. No control is possible over this timing; circuitry external grade and 140/70 MHz for industrial grade, when the peripheral to the processor must be designed for compatibility with these clock rate is one-half the core clock rate. If the peripheral clock signal characteristics. Switching characteristics indicate what the rate is equal to the core clock rate, the maximum peripheral clock processor will do in a given circumstance. Switching character- rate is 80 MHz for both commercial and industrial grade parts. istics can also be used to ensure that any timing requirement of The peripheral clock is supplied to the CLKOUT pins. a device connected to the processor (such as memory) is satisfied. When changing from bypass mode to PLL mode, allow 512 HCLK cycles for the PLL to stabilize. Table 9. Clock In and Clock Out Cycle Timing Parameter Min Max Unit Switching Characteristics t CLKOUT Delay from CLKIN 0 5.8 ns CKOD t CLKOUT Period1 12.5 ns CKO Timing Requirements t CLKIN Period2, 3 10 200 ns CK t CLKIN Low Pulse 4.5 ns CKL t CLKIN High Pulse 4.5 ns CKH t RESET Asserted Pulsewidth Low 200t ns WRST CLKOUT t MSELx/BYPASS Stable Before RESET Deasserted Setup 40 µs MSS t MSELx/BYPASS Stable After RESET Deasserted Hold 1000 ns MSH t MSELx/BYPASS Stable After RESET Asserted 200 ns MSD t Flag Output Disable Time After RESET Asserted 10 ns PFD 1CLKOUT jitter can be as great as 8 ns when CLKOUT frequency is less than 20 MHz. For frequencies greater than 20 MHz, jitter is less than 1 ns. 2In clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN = CCLK), t = t . CK CCLK 3In bypass mode, t = t . CK CCLK t CK CLKIN tCKL tCDD t WRST RESET t MSD t t t PFD MSS MSH MSEL6–0 BYPASS DF t t CKOD CKO CLKOUT Figure 8. Clock In and Clock Out Cycle Timing –20– REV. A

ADSP-2191M Programmable Flags Cycle Timing Table10 and Figure9 describe Programmable Flag operations. Table 10. Programmable Flags Cycle Timing Parameter Min Max Unit Switching Characteristics t Flag Output Delay with Respect to CLKOUT 7 ns DFO t Flag Output Hold After CLKOUT High 6 ns HFO Timing Requirement t Flag Input Hold is Asynchronous 3 ns HFI CLKOUT tDFO tHFO PF (OUTPUT) FLAGOUTPUT t HFI PF (INPUT) FLAGINPUT Figure 9. Programmable Flags Cycle Timing Timer PWM_OUT Cycle Timing Table11 and Figure10 describe timer expired operations. The input signal is asynchronous in “width capture mode” and has an absolute maximum input frequency of 40MHz. Table 11. Timer PWM_OUT Cycle Timing Parameter Min Max Unit Switching Characteristic t Timer Pulsewidth Output1 12.5 (232–1) cycles ns HTO 1The minimum time for t is one cycle, and the maximum time for t equals (232–1) cycles. HTO HTO HCLK t HTO PWM_OUT Figure 10. Timer PWM_OUT Cycle Timing REV. A –21–

ADSP-2191M External Port Write Cycle Timing edge of EMI clock. ACK low causes the DSP to wait, and the Table12 and Figure11 describe external port write operations. DSP requires two EMI clock cycles after ACK goes high to finish the access. For more information, see the External Port chapter The external port lets systems extend read/write accesses in three in the ADSP-219x/ADSP-2191 DSP Hardware Reference. ways: waitstates, ACK input, and combined waitstates and ACK. To add waits with ACK, the DSP must see ACK low at the rising Table 12. External Port Write Cycle Timing Parameter1, 2 Min Max Unit Switching Characteristics t Chip Select Asserted to WR Asserted Delay 0.5t –4 ns CSWS HCLK t Address Valid to WR Setup and Delay 0.5t –3 ns AWS HCLK t WR Deasserted to Chip Select Deasserted 0.5t –4 ns WSCS HCLK t WR Deasserted to Address Invalid 0.5t –3 ns WSA HCLK t WR Strobe Pulsewidth t –2+W3 ns WW HCLK t WR to Data Enable Access Delay 0 ns CDA t WR to Data Disable Access Delay 0.5t –3 0.5t +4 ns CDD HCLK HCLK t Data Valid to WR Deasserted Setup t +1+W3 t +7+W3 ns DSW HCLK HCLK t WR Deasserted to Data Invalid Hold Time; E_WHC4 3.4 ns DHW t WR Deasserted to Data Invalid Hold Time; E_WHC4 t +3.4 ns DHW HCLK t WR Deasserted to WR, RD Asserted t WWR HCLK Timing Requirements t ACK Strobe Pulsewidth 12.5 ns AKW t ACK Delay from WR Low 0 ns DWSAK 1t is the peripheral clock period. HCLK 2These are timing parameters that are based on worst-case operating conditions. 3W = (number of waitstates specified in wait register) (cid:1) t HCLK. 4Write hold cycle–memory select control registers (MS (cid:1) CTL). tCSWS tWSCS MS3–0 IOMS BMS A21–0 tAWS tWW tWSA WR tDWSAK tAKW tWWR ACK tCDD tCDA tDSW tDHW D15–0 RD Figure 11. External Port Write Cycle Timing –22– REV. A

ADSP-2191M External Port Read Cycle Timing Table13 and Figure12 describe external port read operations. For additional information on the ACK signal, see the discussion onPage22. Table 13. External Port Read Cycle Timing Parameter1, 2 Min Max Unit Switching Characteristics t Chip Select Asserted to RD Asserted Delay 0.5t –3 ns CSRS HCLK t Address Valid to RD Setup and Delay 0.5t –3 ns ARS HCLK t RD Deasserted to Chip Select Deasserted Setup 0.5t –2 ns RSCS HCLK t RD Strobe Pulsewidth t –2+W3 ns RW HCLK t RD Deasserted to Address Invalid Setup 0.5t –2 ns RSA HCLK t RD Deasserted to WR, RD Asserted t RWR HCLK Timing Requirements t ACK Strobe Pulsewidth t ns AKW HCLK t RD Asserted to Data Access Setup t –4+W3 ns RDA HCLK t Address Valid to Data Access Setup t +W3 ns ADA HCLK t Chip Select Asserted to Data Access Setup t +W3 ns SDA HCLK t Data Valid to RD Deasserted Setup 7 ns SD t RD Deasserted to Data Invalid Hold 0 ns HRD t ACK Delay from RD Low 0 ns DRSAK 1t is the peripheral clock period. HCLK 2These are timing parameters that are based on worst-case operating conditions. 3W = (number of waitstates specified in wait register) (cid:1) t . HCLK t t RSCS MS3--0 CSRS IOMS BMS A21–0 t tRW tRSA ARS RD t DRSAK t RWR t AKW ACK tCDA tSD tHRD D15–0 t RDA t ADA t SDA WR Figure 12. External Port Read Cycle Timing REV. A –23–

ADSP-2191M External Port Bus Request and Grant Cycle Timing Table14 and Figure13 describe external port bus request and bus grant operations. Table 14. External Port Bus Request and Grant Cycle Timing Parameter1, 2 Min Max Unit Switching Characteristics t CLKOUT High to xMS, Address, and RD/WR Disable 0.5t +1 ns SD HCLK t CLKOUT Low to xMS, Address, and RD/WR Enable 0 4 ns SE t CLKOUT High to BG Asserted Setup 0 4 ns DBG t CLKOUT High to BG Deasserted Hold Time 0 4 ns EBG t CLKOUT High to BGH Asserted Setup 0 4 ns DBH t CLKOUT High to BGH Deasserted Hold Time 0 4 ns EBH Timing Requirements t BR Asserted to CLKOUT High Setup 4.6 ns BS t CLKOUT High to BR Deasserted Hold Time 0 ns BH 1t is the peripheral clock period. HCLK 2These are timing parameters that are based on worst-case operating conditions. CLKOUT t t BS BH BR tSD tSE MS3--0 IOMS BMS tSD tSE A21–0 tSD tSE WR RD tDBG tEBG BG t t DBH EBH BGH Figure 13. External Port Bus Request and Grant Cycle Timing –24– REV. A

ADSP-2191M Host Port ALE Mode Write Cycle Timing Table15 and Figure14 describe Host port write operations in Address Latch Enable (ALE) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description onPage8. Table 15. Host Port ALE Mode Write Cycle Timing Parameter Min Max Unit Switching Characteristics t HWR Asserted to HACK Asserted (Setup, ACK Mode) First 10 5t +t 1 ns WHKS1 HCLK NH Byte t HWR Asserted to HACK Asserted (Setup, ACK Mode)2 10 ns WHKS2 t HWR Deasserted to HACK Deasserted (Hold, ACK Mode) 10 ns WHKH t HWR Asserted to HACK Asserted (Setup, Ready Mode) 10 ns WHS t HWR Asserted to HACK Deasserted (Hold, Ready Mode) 0 5t +t 1 ns WHH HCLK NH First Byte Timing Requirements t HCMS or HCIOMS Asserted to HALE Asserted 0 ns CSAL t HALE Asserted Pulsewidth 4 ns ALPW t HALE Deasserted to HCMS or HCIOMS Deasserted 1 ns ALCSW t HWR Deasserted to HCMS or HCIOMS Deasserted 0 ns WCSW t HALE Deasserted to HWR Asserted 1 ns ALW t HWR Deasserted (After Last Byte) to HCMS or 0 ns WCS HCIOMS Deasserted (Ready for Next Write) t HACK Asserted to HWR Deasserted (Hold, ACK Mode) 1.5 ns HKWD t Address Valid to HALE Deasserted (Setup) 2 ns AALS t HALE Deasserted to Address Invalid (Hold) 4 ns ALAH t Data Valid to HWR Deasserted (Setup) 4 ns DWS t HWR Deasserted to Data Invalid (Hold) 1 ns WDH 1t are peripheral bus latencies (n(cid:1)t ); these are internal DSP latencies related to the number of peripheral DMAs attempting to access DSP memory NH HCLK at the same time. 2Measurement is for the second, third, or fourth byte of a host write transaction. The quantity of bytes to complete a host write transaction is dependent on the data bus size (8 or 16 bits) and the data type (16 or 24 bits). REV. A –25–

ADSP-2191M HCMS HIOMS t t ALCSW tCSAL ALPW tWCSW HALE tALW tWCS HWR t HKWD tWHKS tWHKH HACK (ACK HACKEACHBYTE MODE) t WHH t WHS HACK (READY HACKFIRSTBYTE MODE) t ALAH t DWS tAALS tWDH HAD15–0 ADDRESS DATA DATA ADDRESS HA16 VALID VALID VALID VALID START FIRST LAST START FIRSTWORD BYTE BYTE NEXTWORD Figure 14. Host Port ALE Mode Write Cycle Timing –26– REV. A

ADSP-2191M Host Port ACC Mode Write Cycle Timing Table16 and Figure15 describe Host port write operations in Address Cycle Control (ACC) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description onPage8. Table 16. Host Port ACC Mode Write Cycle Timing Parameter Min Max Unit Switching Characteristics t HWR Asserted to HACK Asserted (ACK Mode) First Byte 10 5t +t 1 ns WHKS1 HCLK NH t HWR Asserted to HACK Asserted (Setup, ACK Mode)2 12 ns WHKS2 t HWR Deasserted to HACK Deasserted (Hold, ACK Mode) 10 ns WHKH t HWR Asserted to HACK Asserted (Setup, Ready Mode) 10 ns WHS t HWR Asserted to HACK Deasserted (Hold, Ready Mode) 0 5t +t 1 ns WHH HCLK NH First Byte t HWR Asserted to HACK Asserted (Setup) During Address 10 ns WSHKS Latch t HWR Deasserted to HACK Deasserted (Hold) During 10 ns WHHKH Address Latch Timing Requirements t HWR Asserted to HALE Deasserted (Delay) 1.5 ns WAL t HCMS or HCIOMS Asserted to HALE Asserted (Delay) 0 ns CSAL t HALE Deasserted to Optional HCMS or HCIOMS 1 ns ALCS Deasserted t HWR Deasserted to HCMS or HCIOMS Deasserted 0 ns WCSW t HALE Asserted to HWR Asserted 0.5 ns ALW t HCMS or HCIOMS Asserted to HWR Asserted 0 ns CSW t HWR Deasserted (After Last Byte) to HCMS or 0 ns WCS HCIOMS Deasserted (Ready for Next Write) t HALE Deasserted to HWR Asserted 1 ns ALEW t HACK Asserted to HWR Deasserted (Hold, ACK Mode) 1.5 ns HKWD t Address Valid to HWR Asserted (Setup) 3 ns ADW t HWR Deasserted to Address Invalid (Hold) 3 ns WAD t Data Valid to HWR Deasserted (Setup) 2 ns DWS t HWR Deasserted to Data Invalid (Hold) 2 ns WDH t HACK Asserted to HWR Deasserted (Hold) During Address 2 ns HKWAL Latch2 1t are peripheral bus latencies (n(cid:1)t ); these are internal DSP latencies related to the number of peripheral DMAs attempting to access DSP memory NH HCLK at the same time. 2 Measurement is for the second, third, or fourth byte of a host write transaction. The quantity of bytes to complete a host write transaction is dependent on the data bus size (8 or 16 bits) and the data type (16 or 24 bits). REV. A –27–

ADSP-2191M HCMS HIOMS t ALCS tCSAL t tWCSW WAL HALE t CSW tALW tALEW tWCS HWR tHKWAL tHKWD t HACK tWSHKS tWHKS WHKH (ACK HACKEACHBYTE MODE) tWHHKH t tWHH WHS HACK (READY HACKFIRSTBYTE MODE) t WAD t t t ADW DWS WDH HAD15–0 ADDRESS DATA DATA ADDRESS HA16 VALID VALID VALID VALID START FIRST LAST START FIRSTWORD BYTE BYTE NEXTWORD Figure 15. Host Port ACC Mode Write Cycle Timing –28– REV. A

ADSP-2191M Host Port ALE Mode Read Cycle Timing Table17 and Figure16 describe Host port read operations in Address Latch Enable (ALE) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description onPage8. Table 17. Host Port ALE Mode Read Cycle Timing Parameter Min Max Unit Switching Characteristics t HRD Asserted to HACK Asserted (ACK Mode) First Byte 12t 15t +t 1 ns RHKS1 HCLK HCLK NH t HRD Asserted to HACK Asserted (Setup, ACK Mode)2 12 ns RHKS2 t HRD Deasserted to HACK Deasserted (Hold, ACK Mode) 10 ns RHKH t HRD Asserted to HACK Asserted (Setup, Ready Mode) 10 ns RHS t HRD Asserted to HACK Deasserted (Hold, Ready Mode) 12t 15t +t 1 ns RHH HCLK HCLK NH First Byte t HRD Deasserted to Data Invalid (Hold) 1 ns RDH t HRD Deasserted to Data Disable 10 ns RDD Timing Requirements t HCMS or HCIOMS Asserted to HALE Asserted (Delay) 0 ns CSAL t HALE Deasserted to Optional HCMS or HCIOMS 1 ns ALCS Deasserted t HRD Deasserted to HCMS or HCIOMS Deasserted 0 ns RCSW t HALE Deasserted to HRD Asserted 5 ns ALR t HRD Deasserted (After Last Byte) to HCMS or 0 ns RCS HCIOMS Deasserted (Ready for Next Read) t HALE Asserted Pulsewidth 4 ns ALPW t HACK Asserted to HRD Deasserted (Hold, ACK Mode) 1.5 ns HKRD t Address Valid to HALE Deasserted (Setup) 2 ns AALS t HALE Deasserted to Address Invalid (Hold) 4 ns ALAH 1t are peripheral bus latencies (n(cid:1)t ); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at NH HCLK the same time. 2Measurement is for the second, third, or fourth byte of a host read transaction. The quantity of bytes to complete a host read transaction is dependent on the data bus size (8 or 16 bits) and the data type (16 or 24 bits). REV. A –29–

ADSP-2191M HCMS HIOMS tCSAL tALCS tRCSW HALE t ALPW tALR tRCS HRD t tHKRD t RHKS RHKH HACK (ACK HACKFOREACHBYTE MODE) t RHH t RHS HACK (READY HACKFIRSTBYTE MODE) t ALAH tAALS tRDH tRDD HAD15–0 ADDRESS DATA DATA ADDRESS HA16 VALID VALID VALID VALID START FIRST LAST START FIRSTWORD BYTE BYTE NEXTWORD Figure 16. Host Port ALE Mode Read Cycle Timing –30– REV. A

ADSP-2191M Host Port ACC Mode Read Cycle Timing Table18 and Figure17 describe Host port read operations in Address Cycle Control (ACC) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description onPage8. Table 18. Host Port ACC Mode Read Cycle Timing Parameter Min Max Unit Switching Characteristics t HRD Asserted to HACK Asserted (ACK Mode) First Byte 12t 15t +t 1 ns RHKS1 HCLK HCLK NH t HRD Asserted to HACK Asserted (Setup, ACK Mode)2 10 ns RHKS2 t HRD Deasserted to HACK Deasserted (Hold, ACK Mode) 10 ns RHKH t HRD Asserted to HACK Asserted (Setup, Ready Mode) 10 ns RHS t HRD Asserted to HACK Deasserted (Hold, Ready Mode) 12t 15t +t 1 ns RHH HCLK HCLK NH First Byte t HRD Deasserted to Data Invalid (Hold) 1 ns RDH t HWR Asserted to HACK Asserted (Setup) During Address 10 ns WSHKS Latch t HWR Deasserted to HACK Deasserted (Hold) During 10 ns WHHKH Address Latch t HRD Deasserted to Data Disable 10 ns RDD Timing Requirements t HCMS or HCIOMS Asserted to HALE Asserted (Delay) 0 ns CSAL t HALE Deasserted to Optional HCMS or HCIOMS 1 ns ALCS Deasserted t HRD Deasserted to HCMS or HCIOMS Deasserted 0 ns RCSW t HALE Asserted to HWR Asserted 0.5 ns ALW t HALE Deasserted to HWR Asserted 1 ns ALER t HCMS or HCIOMS Asserted to HRD Asserted 0 ns CSR t HRD Deasserted (After Last Byte) to HCMS or 0 ns RCS HCIOMS Deasserted (Ready for Next Read) t HWR Deasserted to HALE Deasserted (Delay) 2.5 ns WAL t HACK Asserted to HRD Deasserted (Hold, ACK Mode) 1.5 ns HKRD t Address Valid to HWR Deasserted (Setup) 2 ns ADW t HWR Deasserted to Address Invalid (Hold) 1 ns WAD t HACK Asserted to HWR Deasserted (Hold) During Address 2 ns HKWAL Latch2 1t are peripheral bus latencies (n(cid:1)t ); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at NH HCLK the same time. 2Measurement is for the second, third, or fourth byte of a host read transaction. The quantity of bytes to complete a host read transaction is dependent on the data bus size (8 or 16 bits) and the data type (16 or 24 bits). REV. A –31–

ADSP-2191M HCMS HIOMS t tCSAL ALCS tRCSW HALE tWAL tt t RCS ALW HWR t CSR t ALER HRD t HKWAL t HKRD t tRHKS tRHKH WSHKS HACK (ACK HACKEACHBYTE MODE) tWHHKH tRHH tRHS HACK (READY HACKFIRSTBYTE MODE) tADW tWAD tRDH tRDD HAD15–0 ADDRESS DATA DATA ADDRESS HA16 VALID VALID VALID VALID START FIRST LAST START FIRSTWORD BYTE BYTE NEXTWORD Figure 17. Host Port ACC Mode Read Cycle Timing –32– REV. A

ADSP-2191M Serial Ports Table19 and Figure18 describe SPORT transmit and receive operations, while Figure19 and Figure20 describe SPORT Frame Sync operations. Table 19. Serial Ports1, 2 Parameter Min Max Unit External Clock Timing Requirements t TFS/RFS Setup Before TCLK/RCLK3 4 ns SFSE t TFS/RFS Hold After TCLK/RCLK3 4 ns HFSE t Receive Data Setup Before RCLK3 1.5 ns SDRE t Receive Data Hold After RCLK3 4 ns HDRE t TCLK/RCLK Width 0.5t –1 ns SCLKW HCLK t TCLK/RCLK Period 2t ns SCLK HCLK Internal Clock Timing Requirements t TFS Setup Before TCLK4; RFS Setup Before RCLK3 4 ns SFSI t TFS/RFS Hold After TCLK/RCLK3 3 ns HFSI t Receive Data Setup Before RCLK3 2 ns SDRI t Receive Data Hold After RCLK3 5 ns HDRI External or Internal Clock Switching Characteristics t TFS/RFS Delay After TCLK/RCLK (Internally 14 ns DFSE Generated FS)4 t TFS/RFS Hold After TCLK/RCLK (Internally 3 ns HOFSE Generated FS)4 External Clock Switching Characteristics t Transmit Data Delay After TCLK4 13.4 ns DDTE t Transmit Data Hold After TCLK4 4 ns HDTE Internal Clock Switching Characteristics t Transmit Data Delay After TCLK4 13.4 ns DDTI t Transmit Data Hold After TCLK4 4 ns HDTI t TCLK/RCLK Width 0.5t –3.5 0.5t +2.5 ns SCLKIW HCLK HCLK Enable and Three-State5 Switching Characteristics t Data Enable from External TCLK4 0 12.1 ns DTENE t Data Disable from External TCLK4 13 ns DDTTE t Data Enable from Internal TCLK4 0 13 ns DTENI t Data Disable from External TCLK4 12 ns DDTTI External Late Frame Sync Switching Characteristics t Data Delay from Late External TFS with MCE=1, MFD=06, 7 10.5 ns DDTLFSE t Data Enable from Late FS or MCE=1, MFD=06, 7 3.5 ns DTENLFSE 1To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup-and-hold, 2) data delay and data setup-and-hold, and 3) SCLK width. 2Word selected timing for I2S mode is the same as TFS/RFS timing (normal framing only). 3Referenced to sample edge. 4Referenced to drive edge. 5Only applies to SPORT0/1. 6MCE=1, TFS enable, and TFS valid follow t and t . DDTENFS DDTLFSE 7If external RFSD/TFS setup to RCLK/TCLK>0.5t , t and t apply; otherwise t and t apply. LSCK DDTLSCK DTENLSCK DDTLFSE DTENLFS REV. A –33–

ADSP-2191M DATARECEIVE-INTERNALCLOCK DATARECEIVE-EXTERNALCLOCK DRIVE SAMPLE DRIVE SAMPLE EDGE EDGE EDGE EDGE t t SCLKIW SCLKW RCLK RCLK tDFSE tDFSE tHOFSE tSFSI tHFSI tHOFSE tSFSE tHFSE RFS RFS tSDRI tHDRI tSDRE tHDRE DR DR NOTE:EITHERTHERISINGEDGEORFALLINGEDGEOFRCLKORTCLKCANBEUSEDASTHEACTIVESAMPLINGEDGE. DATATRANSMIT-INTERNALCLOCK DATATRANSMIT-EXTERNALCLOCK DRIVE SAMPLE DRIVE SAMPLE EDGE EDGE EDGE EDGE t t SCLKIW SCLKW TCLK TCLK tDFSE tDFSE tHOFSE tSFSI tHFSI tHOFSE tSFSE tHFSE TFS TFS tHDTItDDTI tHDTEtDDTE DT DT NOTE:EITHERTHERISINGEDGEORFALLINGEDGEOFRCLKORTCLKCANBEUSEDASTHEACTIVESAMPLINGEDGE. DRIVE DRIVE EDGE EDGE TCLK(EXT) TCLK/RCLK TFS(“LATE,”EXT.) tDDTEN tDDTTE DT DRIVE DRIVE EDGE EDGE TCLK(INT) TCLK/RCLK TFS(“LATE,”INT.) t DDTIN t DDTTI DT Figure 18. Serial Ports –34– REV. A

ADSP-2191M EXTERNALRFSWITHMCE=1,MFD=0 DRIVE SAMPLE DRIVE RCLK t t HOSFSE/I SFSE/I RFS tDTENLFSE tDDTE/I t HDTE/I DT 1STBIT 2NDBIT t DDTLFSE LATEEXTERNALTFS DRIVE SAMPLE DRIVE TCLK tHOSFSE/I t SFSE/I TFS tDTENLFSE tDDTE/I t HDTE/I DT 1STBIT 2NDBIT t DDTLFSE Figure 19. Serial Ports—External Late Frame Sync (Frame Sync Setup > 0.5t ) SCLK EXTERNALRFSWITHMCE=1,MFD=0 DRIVE SAMPLE DRIVE RCLK tSFSE/I tHOFSE/I RFS tDTENLFSE t tDDTE/I HDTE/I DT 1STBIT 2NDBIT t DDTLFSE LATEEXTERNALTFS DRIVE SAMPLE DRIVE TCLK tSFSE/I tHOFSE/I TFS tDTENLFSE tDDTE/I t HDTE/I DT 1STBIT 2NDBIT t DDTLFSE Figure 20. Serial Ports—External Late Frame Sync (Frame Sync Setup < 0.5t ) HCLK REV. A –35–

ADSP-2191M Serial Peripheral Interface (SPI) Port—Master Timing Table20 and Figure21 describe SPI port master operations. Table 20. Serial Peripheral Interface (SPI) Port—Master Timing Parameter Min Max Unit Switching Characteristics t SPIxSEL Low to First SCLK edge (x=0 or 1) 2t –3 ns SDSCIM HCLK t Serial Clock High Period 2t –3 ns SPICHM HCLK t Serial Clock Low Period 2t –3 ns SPICLM HCLK t Serial Clock Period 4t –1 ns SPICLK HCLK t Last SCLK Edge to SPIxSEL High (x=0 or 1) 2t –3 ns HDSM HCLK t Sequential Transfer Delay 2t –2 ns SPITDM HCLK t SCLK Edge to Data Output Valid (Data Out Delay) 0 6 ns DDSPID t SCLK Edge to Data Output Invalid (Data Out Hold) 0 5 ns HDSPID Timing Requirements t Data Input Valid to SCLK Edge (Data Input Setup) 8 ns SSPID t SCLK Sampling Edge to Data Input Invalid (Data In Hold) 1 ns HSPID t SPICHM SPIxSEL (OUTPUT) (x=0or1) tSDSCIM tSPICLM tSPICLK tHDSM tSPITDM SCLK (CPOL=0) (OUTPUT) t t SPICLM SPICHM SCLK (CPOL=1) (OUTPUT) t t DDSPID HDSPID MOSI MSB LSB (OUTPUT) CPHA=1 tSSPID tHSPID tSSPID tHSPID MISO MSB LSB (INPUT) VALID VALID t t DDSPID HDSPID MOSI MSB LSB (OUTPUT) CPHA=0 t t SSPID HSPID MISO MSB LSB (INPUT) VALID VALID Figure 21. Serial Peripheral Interface (SPI) Port—Master Timing –36– REV. A

ADSP-2191M Serial Peripheral Interface (SPI) Port—Slave Timing Table21 and Figure22 describe SPI port slave operations. Table 21. Serial Peripheral Interface (SPI) Port—Slave Timing Parameter Min Max Unit Switching Characteristics t SPISS Assertion to Data Out Active 0 8 ns DSOE t SPISS Deassertion to Data High Impedance 0 10 ns DSDHI t SCLK Edge to Data Out Valid (Data Out Delay) 0 10 ns DDSPID t SCLK Edge to Data Out Invalid (Data Out Hold) 0 10 ns HDSPID Timing Requirements t Serial Clock High Period 2t ns SPICHS HCLK t Serial Clock Low Period 2t ns SPICLS HCLK t Serial Clock Period 4t ns SPICLK HCLK t Last SPICLK Edge to SPISS Not Asserted 2t ns HDS HCLK t Sequential Transfer Delay 2t +4 ns SPITDS HCLK t SPISS Assertion to First SPICLK Edge 2t ns SDSCI HCLK t Data Input Valid to SCLK Edge (Data Input Setup) 1.6 ns SSPID t SCLK Sampling Edge to Data Input Invalid (Data In Hold) 2.4 ns HSPID SPISS (INPUT) t t t t t SPICHS SPICLS SPICLK HDS SPITDS SCLK (CPOL=0) (INPUT) tSPICLS tSPICHS t SDSCI SCLK (CPOL=1) (INPUT) t t t t t DSOE DDSPID HDSPID DDSPID DSDHI MISO MSB LSB (OUTPUT) CPHA=1 t t t t SSPID HSPID SSPID HSPID MOSI MSB LSB (INPUT) VALID VALID t t t DSOE DDSPID DSDHI MISO MSB LSB (OUTPUT) CPHA=0 t t SSPID HSPID MOSI MSB LSB (INPUT) VALID VALID Figure 22. Serial Peripheral Interface (SPI) Port—Slave Timing REV. A –37–

ADSP-2191M Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing Figure23 describes UART port receive and transmit operations. The maximum baud rate is HCLK/16. As shown in Figure23 there is some latency between the generation internal UART interrupts and the external data operations. These latencies are negligible at the data transmission rates for the UART. HCLK (SAMPLE CLOCK) RXD DATA(5–8) STOP RECEIVE INTERNAL UARTRECEIVE UARTRECEIVEBITSETBYDATASTOP; INTERRUPT CLEAREDBYFIFOREAD START TXD DATA(5–8) STOP(1–2) ASDATA TRANSMIT WRITTENTO BUFFER INTERNAL UARTTRANSMITBITSETBYPROGRAM; UARTTRANSMIT CLEAREDBYWRITETOTRANSMIT INTERRUPT Figure 23. UART Port—Receive and Transmit Timing –38– REV. A

ADSP-2191M JTAG Test And Emulation Port Timing Table22 and Figure24 describe JTAG port operations. Table 22. JTAG Port Timing Parameter Min Max Unit Switching Characteristics t TDO Delay from TCK Low 8 ns DTDO t System Outputs Delay After TCK Low1 0 22 ns DSYS Timing Requirements t TCK Period 20 ns TCK t TDI, TMS Setup Before TCK High 4 ns STAP t TDI, TMS Hold After TCK High 4 ns HTAP t System Inputs Setup Before TCK Low2 4 ns SSYS t System Inputs Hold After TCK Low2 5 ns HSYS t TRST Pulsewidth3 4t ns TRSTW TCK 1System Outputs = DATA15–0, ADDR21–0, MS3–0, RD, WR, ACK, CLKOUT, BG, PF7–0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS. 2System Inputs = DATA15–0, ADDR21–0, RD, WR, ACK, BR, BG, PF7–0, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, CLKIN, RESET. 350MHz max. t TCK TCK t t STAP HTAP TMS TDI t DTDO TDO t t SSYS HSYS SYSTEM INPUTS t DSYS SYSTEM OUTPUTS Figure 24. JTAG Port Timing REV. A –39–

ADSP-2191M Output Drive Currents The external component of total power dissipation is caused by Figure25 shows typical I-V characteristics for the output drivers the switching of output pins. Its magnitude depends on: of the ADSP-2191M. The curves represent the current drive • Number of output pins that switch during each cycle (O) capability of the output drivers as a function of output voltage. • The maximum frequency at which they can switch (f) • Their load capacitance (C) 60 VDDEXT=3.65V@–40°C • Their voltage swing (VDD) 40 VDDEXT=3.3V@+25°C and is calculated by the formula below. Am VOH – 20 T EN OUTPUTCURRENT P = O×C×V 2×f R 0 EXT DD R CU VDDEXT=3.0V@+85°C )TEX –20 VOL VDDEXT=3.0V@+85°C The load capacitance includes the processor’s package capaci- D VD –40 tance (C ). The switching frequency includes driving the load (E VDDEXT=3.3V@+25°C IN C high and then back low. Address and data pins can drive high and R –60 OU VDDEXT=3.65V@–40°C low at a maximum rate of 1/(2t ). The write strobe can switch S CK –80 every cycle at a frequency of 1/t . Select pins switch at 1/(2t ), INPUTCURRENT CK CK but selects can switch on each cycle. For example, estimate P –100 EXT 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 with the following assumptions: SOURCE(VDDEXT)VOLTAGE–V • A system with one bank of external data memory—asyn- Figure 25. Typical Drive Currents chronous RAM (16-bit) • One 64K(cid:1)16 RAM chip is used with a load of 10 pF Power Dissipation • Maximum peripheral speed CCLK = 80 MHz, HCLK = Total power dissipation has two components, one due to internal 80 MHz circuitry and one due to the switching of external output drivers. Internal power dissipation is dependent on the instruction • External data memory writes occur every other cycle, a execution sequence and the data operands involved. rate of 1/(4t ), with 50% of the pins switching HCLK • The bus cycle time is 80MHz (t = 12.5ns) HCLK The P equation is calculated for each class of pins that can EXT drive as shown in Table23. Table 23. P Calculation Example EXT Pin Type # of Pins % Switching (cid:1) C (cid:1) f (cid:1) VDD2 = P EXT Address 15 50 10pF (cid:1)20MHz (cid:1)10.9V = 0.01635W MSx 1 0 10pF (cid:1)20MHz (cid:1)10.9V = 0.0W WR 1 — 10pF (cid:1)40MHz (cid:1)10.9V = 0.00436W Data 16 50 10pF (cid:1)20MHz (cid:1)10.9V = 0.01744W CLKOUT 1 — 10pF (cid:1)80MHz (cid:1)10.9V = 0.00872W P =0.04687W EXT A typical power consumption can now be calculated for these Note that the conditions causing a worst-case P are different EXT conditions by adding a typical internal power dissipation with the from those causing a worst-case P . Maximum P cannot INT INT following formula. occur while 100% of the output pins are switching from all ones to all zeros. Note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. P = P +P TOTAL EXT INT Test Conditions Where: The DSP is tested for output enable, disable, and hold time. • P is from Table23 EXT Output Disable Time • P is I (cid:1) 2.5 V, using the calculation I listed INT DDINT DDINT Output pins are considered to be disabled when they stop driving, in Power Dissipation on Page19. go into a high impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by –V is dependent on the capacitive load, C and the L load current, I . This decay time can be approximated by the L equation below. –40– REV. A

ADSP-2191M output has reached a specified high or low trip point, as shown C ∆V in the Output Enable/Disable diagram (Figure26). If multiple tDECAY = -----L-I--------- pins (such as the data bus) are enabled, the measurement value L is that of the first pin to start driving. The output disable time t is the difference between t DIS MEASURED Example System Hold Time Calculation and t as shown in Figure26. The time t is the DECAY MEASURED To determine the data output hold time in a particular system, interval from when the reference signal switches to when the first calculate t using the equation at Output Disable Time output voltage decays –V from the measured output high or DECAY on Page40. Choose –V to be the difference between the output low voltage. The t is calculated with test loads C DECAY L ADSP-2191M’s output voltage and the input threshold for the and I , and with –V equal to 0.5V. L device requiring the hold time. A typical –V will be 0.4V. C is L the total bus capacitance (per data line), and I is the total leakage L or three-state current (per data line). The hold time will be t DECAY REFERENCE plus the minimum disable time (i.e., tDATRWH for the SIGNAL write cycle). t Capacitive Loading MEASURED t t ENA Output delays and holds are based on standard capacitive loads: DIS VOH(MEASURED) 50pF on all pins (see Figure30). The delay and hold specifica- VOH(MEASURED)–(cid:4)V 2.0V tions given should be derated by a factor of 1.5ns/50pF for loads VOL(MEASURED) VOL(MEASURED)+(cid:4)V 1.0V other than the nominal value of 50pF. Figure28 and Figure29 tDECAY show how output rise time varies with capacitance. These figures also show graphically how output delays and holds vary with load OUTPUTSTOPS OUTPUTSTARTS capacitance. (Note that this graph or derating does not apply to DRIVING DRIVING output disable delays; see Output Disable Time on Page40.) The HIGHIMPEDANCESTATE. TESTCONDITIONSCAUSETHISVOLTAGE graphs in these figures may not be linear outside the ranges TOBEAPPROXIMATELY1.5V shown. Figure 26. Output Enable/Disable 40 )% IOL 90 – %30 0 (1 RISETIME s n – TO S OUTPUT 1.5V EM20 PIN IT 50pF L L A F D FALLTIME AN10 IOH SE IR 0 Figure 27. Equivalent Device Loading for AC 0 50 100 150 200 250 Measurements (Includes All Fixtures) LOADCAPACITANCE–pF Figure 29. Typical Output Rise Time (10%-90%, V = Minimum at Maximum Ambient Operating DDEXT INPUT Temperature) vs. Load Capacitance OR 1.5V 1.5V OUTPUT Environmental Conditions The thermal characteristics in which the DSP is operating Figure 28. Voltage Reference Levels for AC influence performance. Measurements (Except Output Enable/Disable) Thermal Characteristics Output Enable Time The ADSP-2191M comes in a 144-lead LQFP or 144-lead Ball Output pins are considered to be enabled when they have made Grid Array (mini-BGA) package. The ADSP-2191M is specified a transition from a high impedance state to when they start for an ambient temperature (T ) as calculated using the driving. The output enable time t is the interval from when a AMB ENA formula below. reference signal reaches a high or low voltage level to when the REV. A –41–

ADSP-2191M 30 T =T –PD×θ AMB CASE CA Where: s L–nD20 • TAMB = Ambient temperature (measured near top surface O of package) H R O • PD = Power dissipation in W (this value depends upon Y10 LA the specific application; a method for calculating PD is E D shown under Power Dissipation). T U TUP 0 • θCA = Value from Table24. O • For the LQFP package: θ = 0.96°C/W JC For the mini-BGA package: θ = 8.4°C/W JC –10 0 50 100 150 200 250 Table 24. θ Values LOADCAPACITANCE–pF CA Figure 30. Typical Output Delay or Hold vs. Load Airflow 0 100 200 400 600 Capacitance (at Maximum Case Temperature) (Linear Ft./Min.) Airflow 0 0.5 1 2 3 To ensure that the TAMB data sheet specification is not exceeded, (Meters/Second) a heatsink and/or an air flow source may be used. A heatsink LQFP: 44.3 41.4 38.5 35.3 32.1 should be attached to the ground plane (as close as possible to θ (°C/W) CA the thermal pathways) with a thermal adhesive. Mini-BGA: 26 24 22 20.9 19.8 θ (°C/W) CA –42– REV. A

ADSP-2191M 144-Lead LQFP Pinout Table25 lists the LQFP pinout by signal name. Table26 lists the LQFP pinout by pin. Table 25. 144-Lead LQFP Pins (Alphabetically by Signal) Pin Pin Pin Pin Pin Signal No. Signal No. Signal No. Signal No. Signal No. A0 84 BYPASS 72 GND 33 HCMS 27 TCLK1 65 A1 85 CLKIN 132 GND 54 HCIOMS 28 TCLK2 47 A2 86 CLKOUT 130 GND 55 HRD 31 TDI 75 A3 87 D0 123 GND 77 HWR 32 TDO 74 A4 88 D1 124 GND 80 IOMS 114 TFS0 59 A5 89 D2 125 GND 94 MS0 115 TFS1 66 A6 91 D3 126 GND 105 MS1 116 TFS2 48 A7 92 D4 128 GND 129 MS2 117 TMR0 43 A8 93 D5 135 GND 134 MS3 119 TMR1 44 A9 95 D6 136 HA16 23 OPMODE 83 TMR2 45 A10 96 D7 137 HACK 26 PF0 34 TMS 76 A11 97 D8 138 HACK_P 24 PF1 35 TRST 79 A12 98 D9 139 HAD0 3 PF2 36 TXD 53 A13 99 D10 140 HAD1 4 PF3 37 V 13 DDEXT A14 101 D11 141 HAD2 6 PF4 38 V 25 DDEXT A15 102 D12 142 HAD3 7 PF5 39 V 40 DDEXT A16 103 D13 144 HAD4 8 PF6 41 V 63 DDEXT A17 104 D14 1 HAD5 9 PF7 42 V 90 DDEXT A18 106 D15 2 HAD6 10 RCLK0 61 V 100 DDEXT A19 107 DR0 60 HAD7 11 RCLK1 68 V 118 DDEXT A20 108 DR1 67 HAD8 12 RCLK2 50 V 131 DDEXT A21 109 DR2 49 HAD9 14 RD 122 V 143 DDEXT ACK 120 DT0 56 HAD10 15 RESET 73 V 19 DDINT BG 111 DT1 64 HAD11 17 RFS0 62 V 58 DDINT BGH 110 DT2 46 HAD12 18 RFS1 69 V 82 DDINT BMODE0 70 EMU 81 HAD13 20 RFS2 51 V 127 DDINT BMODE1 71 GND 5 HAD14 21 RXD 52 WR 121 BMS 113 GND 16 HAD15 22 TCK 78 XTAL 133 BR 112 GND 29 HALE 30 TCLK0 57 REV. A –43–

ADSP-2191M Table 26. 144-Lead LQFP Pins (Numerically by Pin Number) Pin Pin Pin Pin Pin No. Signal No. Signal No. Signal No. Signal No. Signal 1 D14 30 HALE 59 TFS0 88 A4 117 MS2 2 D15 31 HRD 60 DR0 89 A5 118 V DDEXT 3 HAD0 32 HWR 61 RCLK0 90 V 119 MS3 DDEXT 4 HAD1 33 GND 62 RFS0 91 A6 120 ACK 5 GND 34 PF0 63 V 92 A7 121 WR DDEXT 6 HAD2 35 PF1 64 DT1 93 A8 122 RD 7 HAD3 36 PF2 65 TCLK1 94 GND 123 D0 8 HAD4 37 PF3 66 TFS1 95 A9 124 D1 9 HAD5 38 PF4 67 DR1 96 A10 125 D2 10 HAD6 39 PF5 68 RCLK1 97 A11 126 D3 11 HAD7 40 V 69 RFS1 98 A12 127 V DDEXT DDINT 12 HAD8 41 PF6 70 BMODE0 99 A13 128 D4 13 V 42 PF7 71 BMODE1 100 V 129 GND DDEXT DDEXT 14 HAD9 43 TMR0 72 BYPASS 101 A14 130 CLKOUT 15 HAD10 44 TMR1 73 RESET 102 A15 131 V DDEXT 16 GND 45 TMR2 74 TDO 103 A16 132 CLKIN 17 HAD11 46 DT2 75 TDI 104 A17 133 XTAL 18 HAD12 47 TCLK2 76 TMS 105 GND 134 GND 19 V 48 TFS2 77 GND 106 A18 135 D5 DDINT 20 HAD13 49 DR2 78 TCK 107 A19 136 D6 21 HAD14 50 RCLK2 79 TRST 108 A20 137 D7 22 HAD15 51 RFS2 80 GND 109 A21 138 D8 23 HA16 52 RXD 81 EMU 110 BGH 139 D9 24 HACK_P 53 TXD 82 V 111 BG 140 D10 DDINT 25 V 54 GND 83 OPMODE 112 BR 141 D11 DDEXT 26 HACK 55 GND 84 A0 113 BMS 142 D12 27 HCMS 56 DT0 85 A1 114 IOMS 143 V DDEXT 28 HCIOMS 57 TCLK0 86 A2 115 MS0 144 D13 29 GND 58 V 87 A3 116 MS1 DDINT –44– REV. A

ADSP-2191M 144-Lead Mini-BGA Pinout Table27 lists the mini-BGA pinout by signal name. Table28 lists the mini-BGA pinout by ball number. Table 27. 144-Lead Mini-BGA Pins (Alphabetically by Signal) Ball Ball Ball Ball Ball Signal No. Signal No. Signal No. Signal No. Signal No. A0 J11 BYPASS M11 GND F7 HALE J1 TCLK0 J6 A1 H9 CLKIN A5 GND F8 HCIOMS J3 TCLK1 M9 A2 H10 CLKOUT C6 GND F9 HCMS H1 TCLK2 K5 A3 G12 D0 D7 GND G4 HRD J2 TDI K12 A4 H11 D1 A7 GND G5 HWR K2 TDO L11 A5 G10 D2 C7 GND G6 IOMS E8 TFS0 M8 A6 F12 D3 A6 GND H5 MS0 D9 TFS1 J8 A7 G11 D4 B7 GND L6 MS1 A9 TFS2 M5 A8 F10 D5 A4 GND M1 MS2 C9 TMR0 K4 A9 F11 D6 C5 GND M12 MS3 D8 TMR1 L4 A10 E12 D7 B5 HACK H3 OPMODE H12 TMR2 J4 A11 E11 D8 D5 HACK_P G1 PF0 K1 TMS K10 A12 E10 D9 A3 HAD0 C1 PF1 L1 TRST J12 A13 E9 D10 C4 HAD1 B3 PF2 M2 TXD M7 A14 D11 D11 B4 HAD2 C2 PF3 L2 V E5 DDEXT A15 D10 D12 C3 HAD3 D1 PF4 M3 V E6 DDEXT A16 D12 D13 A2 HAD4 D4 PF5 L3 V F5 DDEXT A17 C11 D14 B1 HAD5 D3 PF6 K3 V F6 DDEXT A18 C12 D15 B2 HAD6 D2 PF7 M4 V G7 DDEXT A19 B12 DR0 L7 HAD7 E1 RCLK0 K7 V G8 DDEXT A20 B11 DR1 K9 HAD8 E4 RCLK1 J9 V H7 DDEXT A21 A11 DR2 L5 HAD9 E2 RCLK2 J5 V H8 DDEXT ACK A8 DT0 H6 HAD10 F1 RD B8 V D6 DDINT BG C10 DT1 L8 HAD11 E3 RESET L12 V F4 DDINT BGH B10 DT2 H4 HAD12 F2 RFS0 K8 V G9 DDINT BMODE0 L10 EMU J10 HAD13 G2 RFS1 M10 V J7 DDINT BMODE1 L9 GND A1 HAD14 F3 RFS2 M6 WR C8 BMS A10 GND A12 HAD15 G3 RXD K6 XTAL B6 BR B9 GND E7 HA16 H2 TCK K11 REV. A –45–

ADSP-2191M Table 28. 144-Lead Mini-BGA Pins (Numerically by Ball Number) Ball Ball Ball Ball Ball No. Signal No. Signal No. Signal No. Signal No. Signal A1 GND C6 CLKOUT E11 A11 H4 DT2 K9 DR1 A2 D13 C7 D2 E12 A10 H5 GND K10 TMS A3 D9 C8 WR F1 HAD10 H6 DT0 K11 TCK A4 D5 C9 MS2 F2 HAD12 H7 V K12 TDI DDEXT A5 CLKIN C10 BG F3 HAD14 H8 V L1 PF1 DDEXT A6 D3 C11 A17 F4 V H9 A1 L2 PF3 DDINT A7 D1 C12 A18 F5 V H10 A2 L3 PF5 DDEXT A8 ACK D1 HAD3 F6 V H11 A4 L4 TMR1 DDEXT A9 MS1 D2 HAD6 F7 GND H12 OPMODE L5 DR2 A10 BMS D3 HAD5 F8 GND J1 HALE L6 GND A11 A21 D4 HAD4 F9 GND J2 HRD L7 DR0 A12 GND D5 D8 F10 A8 J3 HCIOMS L8 DT1 B1 D14 D6 V F11 A9 J4 TMR2 L9 BMODE1 DDINT B2 D15 D7 D0 F12 A6 J5 RCLK2 L10 BMODE0 B3 HAD1 D8 MS3 G1 HACK_P J6 TCLK0 L11 TDO B4 D11 D9 MS0 G2 HAD13 J7 V L12 RESET DDINT B5 D7 D10 A15 G3 HAD15 J8 TFS1 M1 GND B6 XTAL D11 A14 G4 GND J9 RCLK1 M2 PF2 B7 D4 D12 A16 G5 GND J10 EMU M3 PF4 B8 RD E1 HAD7 G6 GND J11 A0 M4 PF7 B9 BR E2 HAD9 G7 V J12 TRST M5 TFS2 DDEXT B10 BGH E3 HAD11 G8 V K1 PF0 M6 RFS2 DDEXT B11 A20 E4 HAD8 G9 V K2 HWR M7 TXD DDINT B12 A19 E5 V G10 A5 K3 PF6 M8 TFS0 DDEXT C1 HAD0 E6 V G11 A7 K4 TMR0 M9 TCLK1 DDEXT C2 HAD2 E7 GND G12 A3 K5 TCLK2 M10 RFS1 C3 D12 E8 IOMS H1 HCMS K6 RXD M11 BYPASS C4 D10 E9 A13 H2 HA16 K7 RCLK0 M12 GND C5 D6 E10 A12 H3 HACK K8 RFS0 –46– REV. A

ADSP-2191M OUTLINE DIMENSIONS 144-Lead Metric Thin Plastic Quad Flatpack [LQFP] (ST-144) 22.00BSCSQ 20.00BSCSQ 144 109 1 108 PIN1INDICATOR 0.27 0.50 0.22TYP BSC 0.17 TYP (LEAD PITCH) SEATING PLANE 0.08MAX(LEAD COPLANARITY) 0.15 0.05 0.75 1.45 0.60 1.40 0.45 1.35 36 73 1.60MAX 37 72 DETAILA DETAILA TOPVIEW(PINSDOWN) NOTES: 1.DIMENSIONSAREINMILLIMETERSANDCOMPLYWITHJEDECSTANDARDMS-026-BFB. 2.ACTUALPOSITIONOFEACHLEADISWITHIN0.08OFITS IDEALPOSITION,WHENMEASUREDINTHELATERALDIRECTION. 3.CENTERDIMENSIONSARENOMINAL. 144-Ball Mini-BGA [PBGA] (CA-144-2) 10.00BSCSQ 121110 9 8 7 6 5 4 3 21 A PINA1INDICATOR B 8.80 C D BSC E SQ F 0.80 G H BSC J (BALL K PITCH) L M TOPVIEW BOTTOMVIEW 1.70 DETAILA MAX 0.85 MIN 0.25 MIN NOTES: 0.55 SEATING 1.DIMENSIONSAREINMILLIMETERSANDCOMPLY 0.50 PLANE WITHJEDECSTANDARDMO-205-AC. 0.45 0.10MAX(BALL 2.ACTUALPOSITIONOFTHEBALLGRIDIS (BALL COPLANARITY) WITHIN0.15OFITSIDEALPOSITION,RELATIVETO DIAMETER) THEPACKAGEEDGES. 3.ACTUALPOSITIONOFEACHBALLISWITHIN0.08OF DETAILA ITSIDEALPOSITION,RELATIVETOTHEBALLGRID. 4.CENTERDIMENSIONSARENOMINAL. REV. A –47–

ADSP-2191M ORDERING GUIDE Instruction Package Part Number1, 2 Ambient Temperature Range Rate (MHz) Description Operating Voltage ADSP-2191MKST-160 0ºC to 70ºC 160 144-Lead LQFP 2.5 Int./3.3 Ext.V ADSP-2191MBST-140 –40ºC to +85ºC 140 144-Lead LQFP 2.5 Int./3.3 Ext.V ADSP-2191MKCA-160 0ºC to 70ºC 160 144-Ball Mini-BGA 2.5 Int./3.3 Ext.V ADSP-2191MBCA-140 –40ºC to +85ºC 140 144-Ball Mini-BGA 2.5 Int./3.3 Ext.V 1ST = Plastic Thin Quad Flatpack (LQFP). 2CA = Mini Ball Grid Array (PBGA) A) 2( 0 Revision History –7/ 0 – 6 3 9 2 0 Location Page C 7/02—Changed from Rev. 0 to Rev. A Changes to formatting only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Global A. S. U. N D I E T N RI P –48– REV. A

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADSP-2191MBCA-140 ADSP-2191MBCAZ-140 ADSP-2191MBSTZ-140 ADSP-2191MKCA-160 ADSP- 2191MKCAZ-160 ADSP-2191MKSTZ-160