ADS8317 ADS8317 ADS8317 www.ti.com.................................................................................................................................................... SBAS356D–JUNE2007–REVISEDOCTOBER2009 16-Bit, High-Speed, 2.7V to 5.5V microPower Sampling ANALOG-TO-DIGITAL CONVERTER CheckforSamples:ADS8317 FEATURES DESCRIPTION 1 • 16BitsNoMissingCodes(Full-SupplyRange, The ADS8317 is a 16-bit, sampling, analog-to-digital 23 HighorLowGrade) (A/D) converter specified for a supply voltage range • VeryLowNoise:5LSB from 2.7V to 5.5V. It requires very little power, even PP when operating at the full data rate. At lower data • ExcellentLinearity: rates, the high speed of the device enables it to ±0.8LSBtyp, ±1.5LSBmaxINL spend most of its time in the power-down mode. For +0.7LSBtyp,+1.25LSBmaxDNL example, the average power dissipation is less than ±1mVmaxOffset 0.2mWata10kHzdatarate. ±16LSBtypGainError The ADS8317 offers excellent linearity and very low • microPower: noise and distortion. It also features a synchronous 10mWat5V,250kHz serial (SPI/SSI-compatible) interface and a differential 4mWat2.7V,200kHz input. The reference voltage can be set to any level 2mWat2.7V,100kHz withintherangeof0.1VtoV /2. DD 0.2mWat2.7V,10kHz Low power and small size make the ADS8317 ideal • Packages:MSOP-8,SON-8 for portable and battery-operated systems. It is also • Pin-CompatiblewiththeADS8321 an excellent fit for remote data-acquisition modules, simultaneous multichannel systems, and isolated • Serial(SPI™/SSI)Interface data acquisition. The ADS8317 is available in MSOP-8 and SON-8 packages. The SON package APPLICATIONS sizeisthesameasa3x3QFNpackage. • Battery-OperatedSystems • RemoteDataAcquisition • IsolatedDataAcquisition • SimultaneousSampling,Multichannel Systems • IndustrialControls • Robotics • VibrationAnalysis SAR REF ADS8317 D OUT +IN CDAC Serial - IN Interface DCLOCK S/HAmp Comparator CS/SHDN 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. SPIisatrademarkofMotorola,Inc. 2 Allothertrademarksarethepropertyoftheirrespectiveowners. 3 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2007–2009,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

ADS8317 SBAS356D–JUNE2007–REVISEDOCTOBER2009.................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. ORDERINGINFORMATION(1) MAXIMUM NO INTEGRAL MISSING LINEARITY CODES SPECIFIED TRANSPORT ERROR ERROR PACKAGE- PACKAGE TEMPERATURE PACKAGE ORDERING MEDIA, PRODUCT (LSB)(2) (LSB) LEAD DESIGNATOR RANGE MARKING NUMBER QUANTITY ADS8317IDGKT TapeandReel,250 ADS8317I ±2 16 MSOP-8 DGK –40°Cto+85°C D17 ADS8317IDGKR TapeandReel,2500 ADS8317IBDGKT TapeandReel,250 ADS8317IB ±1.5 16 MSOP-8 DGK –40°Cto+85°C D17 ADS8317IBDGKR TapeandReel,2500 ADS8317IDRBT TapeandReel,250 ADS8317I ±2 16 SON-8 DRB –40°Cto+85°C D17 ADS8317IDRBR TapeandReel,2500 ADS8317IBDRBT TapeandReel,250 ADS8317IB ±1.5 16 SON-8 DRB –40°Cto+85°C D17 ADS8317IBDRBR TapeandReel,2500 (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumlocatedattheendofthisdatasheet,orsee theTIwebsiteatwww.ti.com. (2) MaximumIntegralLinearityErrorspecifiesa5Vpowersupplyand2.5Vreferencevoltage. ABSOLUTE MAXIMUM RATINGS(1) Overoperatingfree-airtemperaturerange(unlessotherwisenoted). ADS8317 UNIT Supplyvoltage,V toGND –0.3to+7 V DD Analoginputvoltage(2) –0.3toV +0.3 V DD Referenceinputvoltage(2) –0.3toV +0.3 V DD Digitalinputvoltage(2) –0.3toV +0.3 V DD Inputcurrenttoanypinexceptsupply –20to+20 mA Powerdissipation SeeDissipationRatingsTable Operatingvirtualjunctiontemperaturerange,T –40to+150 °C J Operatingfree-airtemperaturerange,T –40to+85 °C A Storagetemperaturerange,T –65to+150 °C STG (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximumratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Allvoltagevaluesarewithrespecttogroundterminal. DISSIPATION RATINGS DERATING FACTORABOVE T ≤+25°C T =+70°C T =+85°C A A A PACKAGE R R T =+25°C POWERRATING POWERRATING POWERRATING θJC θJA A DGK +39.1°C/W +206.3°C/W 4.847mW/°C 606mW 388mW 315mW DRB +5°C/W +45.8°C/W 3.7mW/°C 370mW 204mW 148mW 2 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8317

ADS8317 www.ti.com.................................................................................................................................................... SBAS356D–JUNE2007–REVISEDOCTOBER2009 RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT Low-voltagelevels 2.7 3.6 V Supplyvoltage,GNDtoV DD 5Vlogiclevels 4.5 5.0 5.5 V Referenceinputvoltage 1 V /2 V DD –INtoGND –0.2 V +0.2 V DD Analoginputvoltage +INtoGND –0.2 V +0.2 V DD +IN–(–IN) –V +V V REF REF Operatingjunctiontemperature,T –40 +125 °C J ELECTRICAL CHARACTERISTICS: V = +5V DD At–40°Cto+85°C,V =+2.5V,–IN=+2.5V,f =250kHz,andf =24×f ,unlessotherwisenoted. REF SAMPLE CLK SAMPLE ADS8317I ADS8317IB PARAMETER TESTCONDITIONS MIN TYP MAX MIN TYP MAX UNIT ANALOGINPUT Full-scalerange FSR +IN–(–IN) –VREF VREF –VREF VREF V Absoluteinputrange +IN –0.1 VDD+0.1 –0.1 VDD+0.1 V Hold 5 5 GΩ Inputresistance RON Sampling 50 100 50 100 Ω Inputcapacitance Duringsampling 24 24 pF Inputleakagecurrent ±50 ±50 nA Differentialinputcapacitance +INto–IN,duringsampling 20 20 pF Full-powerbandwidth FSBW fSsinewave,SINAD=60dB 500 500 kHz DCACCURACY Resolution 16 16 Bits Nomissingcodes NMC 16 16 16 16 Bits Integrallinearityerror INL –2 ±1.5 +2 –1.5 ±0.8 +1.5 LSB Differentiallinearityerror DNL –1 ±1 +2 –1 +0.7,–0.5 +1.25 LSB Offseterror VOS –2 ±0.75 +2 –1 ±0.5 +1 mV Offseterrordrift TCVOS ±3 ±3 μV/°C Positive –32 ±16 +32 –32 ±16 +32 LSB Gainerror GERR Negative –32 ±16 +32 –32 ±16 +32 LSB Gainerrordrift TCGERR ±0.1 ±0.1 ppm/°C Bipolarzeroerror –2 ±0.75 +2 –1 ±0.5 +1 mV Bipolarzeroerrordrift ±3 ±3 μV/°C Noise 50 50 μVRMS Power-supplyrejection PSRR 4.75V≤VDD≤5.25V 1 1 LSB SAMPLINGDYNAMICS Conversiontime (16DCLOCKs) tCONV 24kHz≤fCLK≤6.0MHz 2.667 666.7 2.667 666.7 μs Acquisitiontime (4.5DCLOCKs) tAQ fCLK=6.0MHz 0.75 0.75 μs Throughputrate 250 250 kSPS (22DCLOCKs) Clockfrequency 0.024 6.0 0.024 6.0 MHz Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):ADS8317

ADS8317 SBAS356D–JUNE2007–REVISEDOCTOBER2009.................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: V = +5V (continued) DD At–40°Cto+85°C,V =+2.5V,–IN=+2.5V,f =250kHz,andf =24×f ,unlessotherwisenoted. REF SAMPLE CLK SAMPLE ADS8317I ADS8317IB PARAMETER TESTCONDITIONS MIN TYP MAX MIN TYP MAX UNIT ACACCURACY 5VPPsinewaveat2kHz –102 –106 dB Totalharmonicdistortion THD 5VPPsinewaveat10kHz –100 –104 dB 5VPPsinewaveat2kHz 106 110 dB Spurious-freedynamicrange SFDR 5VPPsinewaveat10kHz 104 109 dB 5VPPsinewaveat2kHz 89.6 90 dB Signal-to-noiseratio SNR 5VPPsinewaveat10kHz 89.6 90 dB 5VPPsinewaveat2kHz 89.5 89.9 dB Signal-to-noise+distortion SINAD 5VPPsinewaveat10kHz 89.4 89.8 dB 5VPPsinewaveat2kHz 14.57 14.65 Bits Effectivenumberofbits ENOB 5VPPsinewaveat10kHz 14.56 14.63 Bits VOLTAGEREFERENCEINPUT Referencevoltage 0.5 VDD/2 0.5 VDD/2 V CS=GND,fSAMPLE=0Hz 5 5 GΩ Referenceinputresistance CS=VDD 5 5 GΩ Referenceinputcapacitance 24 24 pF fS=250kHz 35 52 35 52 μA fS=200kHz 25 38 25 38 μA Referenceinputcurrent fS=100kHz 10 15 10 15 μA fS=10kHz 1 2 1 2 μA CS=VDD 0.1 0.1 μA DIGITALINPUTS(1) Logicfamily CMOS CMOS High-levelinputvoltage VIH 0.7×VDD VDD+0.3 0.7×VDD VDD+0.3 V Low-levelinputvoltage VIL –0.3 0.3×VDD –0.3 0.3×VDD V Inputcurrent IIN VI=VDDorGND –50 +50 –50 +50 nA Inputcapacitance CI 5 5 pF DIGITALOUTPUTS(1) Logicfamily CMOS CMOS High-leveloutputvoltage VOH VDD=4.5V,IOH=–100μA 4.44 4.44 V Low-leveloutputvoltage VOL VDD=4.5V,IOL=100μA 0.5 0.5 V High-impedancestateoutput current IOZ CS=VDD,VI=VDDorGND –50 +50 –50 +50 nA Outputcapacitance CO 5 5 pF Loadcapacitance CL 30 30 pF Dataformat Binarytwoscomplement Binarytwoscomplement (1) Appliesfor5.0Vnominalsupply:V (min)=4.5VandV (max)=5.5V. DD DD 4 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8317

ADS8317 www.ti.com.................................................................................................................................................... SBAS356D–JUNE2007–REVISEDOCTOBER2009 ELECTRICAL CHARACTERISTICS: V = +2.7V DD At–40°Cto+85°C,V =+1.25V,–IN=1.25V,f =200kHz,andf =24×f ,unlessotherwisenoted. REF SAMPLE CLK SAMPLE ADS8317I ADS8317IB PARAMETER TESTCONDITIONS MIN TYP MAX MIN TYP MAX UNIT ANALOGINPUT Full-scalerange FSR +IN–(–IN) –VREF VREF –VREF VREF V Absoluteinputrange +IN –0.1 VDD+0.1 –0.1 VDD+0.1 V Hold 5 5 GΩ Inputresistance RON Sampling 100 150 100 150 Ω Inputcapacitance Duringsampling 24 24 pF Inputleakagecurrent ±50 ±50 nA Differentialinputcapacitance +INto–IN,duringsampling 20 20 pF Full-powerbandwidth FSBW fSsinewave,SINAD=60dB 1000 1000 kHz DCACCURACY Resolution 16 16 Bits Nomissingcodes NMC 16 16 16 16 Bits Integrallinearityerror INL –3 ±2 +3 –2 ±1.5 +2 LSB Differentiallinearityerror DNL –1 +1.5,–1 +2.5 –1 ±1 +2 LSB Offseterror VOS –2 ±1 +2 –1 ±0.5 +1 mV Offseterrordrift TCVOS ±0.4 ±0.4 μV/°C Positive –32 ±16 +32 –32 ±16 +32 LSB Gainerror GERR Negative –32 ±16 +32 –32 ±16 +32 LSB Gainerrordrift TCGERR ±0.15 ±0.15 ppm/°C Bipolarzeroerror –2 ±0.8 +2 –1 ±0.4 +1 mV Bipolarzeroerrordrift ±0.2 ±0.2 μV/°C Noise 50 50 μVRMS Power-supplyrejection PSRR 2.7V≤VDD≤3.6V 1 1 LSB SAMPLINGDYNAMICS Conversiontime(16DCLOCKs) tCONV 24kHz≤fCLK≤4.8MHz 3.333 666.7 3.333 666.7 μs Acquisitiontime(4.5DCLOCKs) tAQ fCLK=4.8MHz 0.9375 0.9375 μs Throughputrate(22DCLOCKs) 200 200 kSPS Clockfrequency 0.024 4.8 0.024 4.8 MHz ACACCURACY 2.5VPPsinewaveat2kHz –104 –107 dB Totalharmonicdistortion THD 2.5VPPsinewaveat10kHz –101 –106 dB 2.5VPPsinewaveat2kHz 106 108 dB Spurious-freedynamicrange SFDR 2.5VPPsinewaveat10kHz 104 107 dB 2.5VPPsinewaveat2kHz 84.8 85 dB Signal-to-noiseratio SNR 2.5VPPsinewaveat10kHz 84.8 85 dB 2.5VPPsinewaveat2kHz 84.7 84.9 dB Signal-to-noise+distortion SINAD 2.5VPPsinewaveat10kHz 84.7 84.8 dB 2.5VPPsinewaveat2kHz 13.77 13.8 Bits Effectivenumberofbits ENOB 2.5VPPsinewaveat10kHz 13.77 13.79 Bits VOLTAGEREFERENCEINPUT Referencevoltage 1 VDD/2 1 VDD/2 V CS=GND,fSAMPLE=0Hz 5 5 kΩ Referenceinputresistance CS=VDD 5 5 GΩ Referenceinputcapacitance 20 20 pF fS=200kHz 9 14 9 14 μA fS=100kHz 3 5 3 5 μA Referenceinputcurrent fS=10kHz 0.5 1 0.5 1 μA CS=VDD 0.1 0.1 μA Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):ADS8317

ADS8317 SBAS356D–JUNE2007–REVISEDOCTOBER2009.................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: V = +2.7V (continued) DD At–40°Cto+85°C,V =+1.25V,–IN=1.25V,f =200kHz,andf =24×f ,unlessotherwisenoted. REF SAMPLE CLK SAMPLE ADS8317I ADS8317IB PARAMETER TESTCONDITIONS MIN TYP MAX MIN TYP MAX UNIT DIGITALINPUTS(1) Logicfamily LVCMOS LVCMOS High-levelinputvoltage VIH VDD=3.6V 2 VDD+0.3 2 VDD+0.3 V Low-levelinputvoltage VIL VDD=2.7V –0.3 0.8 –0.3 0.3×VDD V Inputcurrent IIN VI=VDDorGND –50 +50 –50 +50 nA Inputcapacitance CI 5 5 pF DIGITALOUTPUTS(1) Logicfamily LVCMOS LVCMOS High-leveloutputvoltage VOH VDD=2.7V,IOH=–100μA VDD–0.2 VDD–0.2 V Low-leveloutputvoltage VOL VDD=2.7V,IOL=100μA 0.2 0.2 V High-impedancestateoutput current IOZ CS=VDD,VI=VDDorGND –50 +50 –50 +50 nA Outputcapacitance CO 5 5 pF Loadcapacitance CL 30 30 pF Dataformat Binarytwoscomplement Binarytwoscomplement (1) Appliesfor5.0Vnominalsupply:V (min)=2.7VandV (max)=3.6V. DD DD ELECTRICAL CHARACTERISTICS: GENERAL At–40°Cto+85°C,–IN=GND,andf =24×f ,unlessotherwisenoted. DCLOCK SAMPLE ADS8317I ADS8317IB PARAMETER TESTCONDITIONS MIN TYP MAX MIN TYP MAX UNIT ANALOGINPUT Low-voltagelevels 2.7 3.6 2.7 3.6 V Powersupply VDD 5Vlogiclevels 4.5 5.5 4.5 5.5 V VDD=2.7V,fS=10kHz, 0.065 0.085 0.065 0.085 mA fDCLOCK=4.8MHz VDD=2.7V,fS=100kHz, 0.7 1.0 0.7 1.0 mA fDCLOCK=4.8MHz Operatingsupplycurrent IDD VfDDCDLO=CK2.=7V4,.8fSM=Hz200kHz, 1.4 2.0 1.4 2.0 mA VDD=5V,fS=200kHz, 1.5 2.5 1.5 2.5 mA fDCLOCK=6MHz VDD=5V,fS=250kHz, 2.0 3.0 2.0 3.0 mA fDCLOCK=6MHz VDD=2.7V 0.1 0.1 μA Power-downsupplycurrent IDD VDD=5V 0.2 0.2 μA VDD=2.7V,fS=10kHz, 0.18 0.23 0.18 0.23 mW fDCLOCK=4.8MHz VDD=2.7V,fS=100kHz, 1.9 2.7 1.9 2.7 mW fDCLOCK=4.8MHz Powerdissipation VDD=2.7V,fS=200kHz, 3.8 5.4 3.8 5.4 mW fDCLOCK=4.8MHz VDD=5V,fS=200kHz, 7.5 12.5 7.5 12.5 mW fDCLOCK=6MHz VDD=5V,fS=250kHz, 10 15 10 15 mW fDCLOCK=6MHz VDD=2.7V,CS=VDD 0.3 0.3 μW Powerdissipationinpower-down VDD=5V,CS=VDD 0.6 0.6 μW 6 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8317

ADS8317 www.ti.com.................................................................................................................................................... SBAS356D–JUNE2007–REVISEDOCTOBER2009 PIN CONFIGURATION DGKPACKAGE MSOP-8 (TOPVIEW) REF 1 8 V DD +IN 2 7 DCLOCK ADS8317 -IN 3 6 D OUT GND 4 5 CS/SHDN DRBPACKAGE SON-8 (TOPVIEW) REF 1 8 V DD +IN 2 7 DCLOCK ADS8317 -IN 3 6 D OUT GND 4 (Thermal Pad) 5 CS/SHDN (1) The DRB package thermal pad must be soldered to the printed circuit board for proper thermal and mechanical performance. TERMINALFUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION REF 1 Analoginput Referenceinput +IN 2 Analoginput Noninvertinganaloginput –IN 3 Analoginput Invertinganaloginput GND 4 Power-supplyconnection Ground CS/SHDN 5 Digitalinput Chipselectwhenlow;Shutdownmodewhenhigh. D 6 Digitaloutput Serialoutputdataword OUT DCLOCK 7 Digitalinput Dataclocksynchronizestheserialdatatransferanddeterminesconversionspeed. V 8 Power-supplyconnection Powersupply DD Equivalent Input Circuits (V = 5.0V) DD V V V DD DD DD R C R ON (SAMPLE) ON 50W 24pF 50W 24pF ANALOG IN REF I/O GND GND GND Diode Turn-On Voltage: 0.35V Equivalent Reference Input Circuit Equivalent Digital Input/Output Circuit Equivalent Analog Input Circuit Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):ADS8317

ADS8317 SBAS356D–JUNE2007–REVISEDOCTOBER2009.................................................................................................................................................... www.ti.com TIMING INFORMATION t CYC CS/SHDN Power Down Sample Conversion t SUCS DCLOCK t CSD Use positive clock edge for data transfer DOUT Hi-Z 0 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0(1) Hi-Z (MSB) (LSB) t t SMPL CONV NOTE: (1) A minimum of 22 clock cycles are required for 16-bit conversion; 24 clock cycles are shown. IfCSremains low at the end of conversion, a new data stream is shifted out with LSB-first data followed by zeroes indefinitely. t CYC CS/SHDN tSUCS Power Down DCLOCK t CSD DOUT Hi-Z 0 B15 B14 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B0 B11B12 B13 B14 B1(52) Hi-Z (MSB) (LSB) (MSB) t t SMPL CONV NOTE: (2) After completing the data transfer, if further clocks are applied withCSlow, the A/D converter will output zeroes indefinitely. 1.4V 3kW 90% D OUT DOUT Test Point 10% t t 100pF r f C LOAD Voltage Waveforms for D Rise and Fall Times, t, t OUT r f Load Circuit for t , t, and t dDO r f Test Point DCLOCK V DD 3kW tdisWaveform 2, ten tdDO DOUT D 100pF tdisWaveform 1 OUT C LOAD t hDO Load Circuit for t and t dis en Voltage Waveforms for D Delay Times, t OUT dDO 90% CS/SHDN CS/SHDN DOUT 90% DCLOCK 1 4 5 Waveform 1(3) t dis DOUT 10% DOUT B15 Waveform 2(4) t en Voltage Waveforms for t dis Voltage Waveforms for t en NOTES:(3) Waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control. (4) Waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control. Figure1. TimingDiagrams 8 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8317

ADS8317 www.ti.com.................................................................................................................................................... SBAS356D–JUNE2007–REVISEDOCTOBER2009 TIMING INFORMATION (continued) TimingCharacteristics SYMBOL DESCRIPTION MIN TYP MAX UNIT t Analoginputsampletime 4.5 5.0 DCLOCKs SMPL t Conversiontime 16 DCLOCKs CONV t Completecycletime 22 DCLOCKs CYC t CSfallingtoDCLOCKlow 0 ns CSD t CSfallingtoDCLOCKrising 20 ns SUCS t DCLOCKfallingtocurrentD notvalid 5 15 ns HDO OUT t CSrisingtoD 3-state 70 100 ns DIS OUT t DCLOCKfallingtoD enabled 20 50 ns EN OUT t D falltime 5 25 ns F OUT t D risetime 7 25 ns R OUT Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):ADS8317

ADS8317 SBAS356D–JUNE2007–REVISEDOCTOBER2009.................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: V = +5V DD AtT =25°C,V =2.5V,f =250kHz,f =24×f ,unlessotherwisenoted. A REF SAMPLE CLK SAMPLE INTEGRALLINEARITYERRORvsCODE DIFFERENTIALLINEARITYERRORvsCODE 3 3 2 2 1 1 B) B) S S E (L 0 E (L 0 IL DL -1 -1 -2 -2 -3 -3 8000h C000h 0000h 4000h 7FFFh 8000h C000h 0000h 4000h 7FFFh Output Code Output Code Figure2. Figure3. SUPPLYCURRENTvsTEMPERATURE CHANGEINOFFSETvsTEMPERATURE 1.750 3.0 2.5 1.745 2.0 A) 1.740 SB) 1.5 m L ent ( 1.735 °5C ( 1.0 urr 1.730 +2 0.5 C m Supply 11..772250 elta fro -0.05 D -1.0 1.715 -1.5 1.710 -2.0 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) Figure4. Figure5. CHANGEINBIPOLARZEROERRORvsTEMPERATURE CHANGEINGAINvsTEMPERATURE 3.0 0.50 2.5 2.0 0.25 B) B) S 1.5 S L L C ( 1.0 C ( 0 °5 °5 +2 0.5 +2 om 0 om -0.25 elta fr -0.5 elta fr D -1.0 D -0.50 -1.5 -2.0 -0.75 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) Figure6. Figure7. 10 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8317

ADS8317 www.ti.com.................................................................................................................................................... SBAS356D–JUNE2007–REVISEDOCTOBER2009 TYPICAL CHARACTERISTICS: V = +5V (continued) DD AtT =25°C,V =2.5V,f =250kHz,f =24×f ,unlessotherwisenoted. A REF SAMPLE CLK SAMPLE POWER-DOWNCURRENTvsTEMPERATURE SUPPLYCURRENTvsSAMPLINGRATE 38 10 37 36 n Current (nA) 3333354321 urrent (mA) 0.11 wer-Dow 322098 Supply C 0.01 Po 27 26 25 24 0.001 -50 -25 0 25 50 75 100 1 10 100 250 Temperature (°C) Sampling Rate (kHz) Figure8. Figure9. FREQUENCYSPECTRUM REFERENCECURRENTvsSAMPLINGRATE (8192pointFFT,f =1.9836kHz,–0.2dB) IN 100 0 -20 10 -40 A) murrent ( 1 ude (dB) --6800 pply C Amplit -100 u S 0.1 -120 -140 0.01 -160 1 10 100 250 0 25 50 75 100 125 Sampling Rate (kHz) Frequency (kHz) Figure10. Figure11. FREQUENCYSPECTRUM SIGNAL-TO-NOISERATIOAND (8192PointFFT,f =9.9792kHz,–0.2dB) SIGNAL-TO-NOISE+DISTORTIONvsINPUTFREQUENCY IN 0 95 -20 SNR -40 B) 90 e (dB) -60 NAD (d SINAD ud -80 SI 85 mplit -100 and A R -120 SN 80 -140 -160 75 0 25 50 75 100 125 1 10 100 200 Frequency (kHz) Frequency (kHz) Figure12. Figure13. Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):ADS8317

ADS8317 SBAS356D–JUNE2007–REVISEDOCTOBER2009.................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: V = +5V (continued) DD AtT =25°C,V =2.5V,f =250kHz,f =24×f ,unlessotherwisenoted. A REF SAMPLE CLK SAMPLE SPURIOUS-FREEDYNAMICRANGEAND TOTALHARMONICDISTORTIONvsINPUTFREQUENCY EFFECTIVENUMBEROFBITSvsINPUTFREQUENCY 120 -120 15.0 115 -115 SFDR 110 -110 14.5 105 -105 SFDR (dB) 109980505 THD(1) ----199805050 THD (dB) ENOB (Bits) 1143..05 13.0 80 -80 75 -75 12.5 70 -70 NOTE: (1) First nine harmonics of the input frequency. 65 -65 12.0 1 10 100 200 1 10 100 200 Frequency (kHz) Frequency (kHz) Figure14. Figure15. CHANGEINSIGNAL-TO-NOISE+DISTORTION CHANGEINSIGNAL-TO-NOISE+DISTORTION vsTEMPERATURE vsINPUTLEVEL 0.7 100 0.6 f = 1.98364kHz,-0.2dB fIN= 1.98364kHz IN 90 0.5 B) 0.4 80 S °+25C (L 000...321 D (dB) 7600 m 0 NA 50 a fro -0.1 SI 40 elt -0.2 D 30 -0.3 -0.4 20 -0.5 10 -50 -25 0 25 50 75 100 -80 -70 -60 -50 -40 -30 -20 -10 0 Temperature (°C) Input Level (dB) Figure16. Figure17. PEAK-TO-PEAKNOISEFORADCINPUT OUTPUTCODEHISTOGRAMFORADCINPUT vsREFERENCEVOLTAGE (8192Conversions) 100 V = 5V DD 4835 B) S L e ( s oi N k 10 a e P o- 1673 1608 k-t a e P 34 42 1 0.1 1 2 2.5 FFFE FFFF 0000 0001 0002 Reference Voltage (V) Code (Hex) Figure18. Figure19. 12 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8317

ADS8317 www.ti.com.................................................................................................................................................... SBAS356D–JUNE2007–REVISEDOCTOBER2009 TYPICAL CHARACTERISTICS: V = +2.7V DD AtT =25°C,V =1.25V,f =200kHz,f =24×f ,unlessotherwisenoted. A REF SAMPLE CLK SAMPLE INTEGRALLINEARITYERRORvsCODE DIFFERENTIALLINEARITYERRORvsCODE 3 3 2 2 1 1 ILE (LSB) 0 DLE (LSB) 0 -1 -1 -2 -2 -3 -3 8000h C000h 0000h 4000h 7FFFh 8000h C000h 0000h 4000h 7FFFh Output Code Output Code Figure20. Figure21. SUPPLYCURRENTvsTEMPERATURE CHANGEINOFFSETvsTEMPERATURE 1.310 1.00 1.305 0.75 1.300 A) 1.295 SB) 0.50 m L ent ( 1.290 °5C ( 0.25 urr 1.285 +2 0 C m Supply 11..228705 elta fro --00..2550 1.270 D -0.75 1.265 1.260 -1.00 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) Figure22. Figure23. CHANGEINBIPOLARZEROERROR vsTEMPERATURE CHANGEINGAINvsTEMPERATURE 0.50 0.50 0.25 B) 0.25 B) S S L L 0 C ( C ( °5 °5 +2 0 +2 -0.25 m m o o a fr a fr -0.50 elt -0.25 elt D D -0.75 -0.50 -1.00 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) Figure24. Figure25. Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):ADS8317

ADS8317 SBAS356D–JUNE2007–REVISEDOCTOBER2009.................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: V = +2.7V (continued) DD AtT =25°C,V =1.25V,f =200kHz,f =24×f ,unlessotherwisenoted. A REF SAMPLE CLK SAMPLE POWER-DOWNCURRENTvsTEMPERATURE SUPPLYCURRENTvsSAMPLINGRATE 25 10 24 A) 23 1 nt (n 22 mA) urre 21 ent ( 0.1 wn C 20 Curr o y 0.01 er-D 19 uppl w S Po 18 0.001 17 16 0.0001 -50 -25 0 25 50 75 100 1 10 100 200 Temperature (°C) Sampling Rate (kHz) Figure26. Figure27. FREQUENCYSPECTRUM REFERENCECURRENTvsSAMPLINGRATE (8192PointFFT,fN=1.9775kHz,–0.2dB) I 100 0 -20 A) 10 -40 m Current ( 1 ude (dB) --6800 nce mplit -100 ere A ef 0.1 -120 R -140 0.01 -160 1 10 100 200 0 10 20 30 40 50 60 70 80 90 100 Sampling Rate (kHz) Frequency (kHz) Figure28. Figure29. FREQUENCYSPECTRUM SIGNAL-TO-NOISERATIOAND (8192PointFFT,f =9.9854kHz,–0.2dB) SIGNAL-TO-NOISE+DISTORTIONvsINPUTFREQUENCY IN 0 86 -20 85 -40 B) 84 dB) -60 D (d 83 SNR e ( NA ud -80 SI 82 mplit -100 and 81 A R SINAD -120 SN 80 -140 79 -160 78 0 10 20 30 40 50 60 70 80 90 100 1 10 100 200 Frequency (kHz) Frequency (kHz) Figure30. Figure31. 14 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8317

ADS8317 www.ti.com.................................................................................................................................................... SBAS356D–JUNE2007–REVISEDOCTOBER2009 TYPICAL CHARACTERISTICS: V = +2.7V (continued) DD AtT =25°C,V =1.25V,f =200kHz,f =24×f ,unlessotherwisenoted. A REF SAMPLE CLK SAMPLE SPURIOUS-FREEDYNAMICRANGEAND TOTALHARMONICDISTORTIONvsINPUTFREQUENCY EFFECTIVENUMBEROFBITSvsINPUTFREQUENCY 110 -110 15.0 SFDR 105 -105 14.5 100 -100 14.0 SFDR (dB) 95 THD(1) -95 THD (dB) NOB (Bits) 13.5 90 -90 E 13.0 85 -85 12.5 NOTE: (1) First nine harmonics of the input frequency. 80 -80 12.0 1 10 100 200 1 10 100 200 Frequency (kHz) Frequency (kHz) Figure32. Figure33. CHANGEINSIGNAL-TO-NOISE+DISTORTIONvs TEMPERATURE SIGNAL-TO-NOISE+DISTORTIONvsINPUTLEVEL 0.6 100 0.5 fIN= 1.97754kHz,-0.2dB 90 fIN= 1.97754kHz 0.4 80 B) 0.3 S 70 °+25C (L 00..210 D (dB) 6500 elta from ---000...123 SINA 4300 D -0.4 20 -0.5 10 -0.6 0 -50 -25 0 25 50 75 100 -80 -70 -60 -50 -40 -30 -20 -10 0 Temperature (°C) Input Level (dB) Figure34. Figure35. OUTPUTCODEHISTOGRAMFORADCINPUT (8192Conversions) 3920 1596 1504 581 497 2 41 50 1 FFFCFFFDFFFE FFFF 0000 0001 0002 0003 0004 Code (Hex) Figure36. Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):ADS8317

ADS8317 SBAS356D–JUNE2007–REVISEDOCTOBER2009.................................................................................................................................................... www.ti.com THEORY OF OPERATION The digital data that are provided on the D pin are The ADS8317 is a classic Successive Approximation OUT for the conversion currently in progress—there is no Register (SAR) analog-to-digital (A/D) converter. The pipeline delay. It is possible to continue to clock the architecture is based on capacitive redistribution that ADS8317 after the conversion is complete and to inherently includes a sample-and-hold function. The obtain the serial data least significant bit first. See the converter is fabricated on a 0.6μ CMOS process. The DigitalTimingsectionformoreinformation. architecture and fabrication process allow the ADS8317 to acquire and convert an analog signal at ANALOG INPUT up to 250,000 conversions per second while consuminglessthan10mWfromV . Theanaloginputisbipolarandfullydifferential.There DD are two general methods of driving the analog input Differential linearity for the ADS8317 is of the ADS8317: single-ended or differential, as factory-adjusted via a package-level trim procedure. shown in Figure 37. When the input is single-ended, Thestateofthetrimelementsisstoredinnon-volatile the –IN input is held at a fixed voltage. The +IN input memory and is continuously updated after each swings around the same voltage and the acquisition cycle, just prior to the start of the peak-to-peak amplitude is 2 × V . The value of successive approximation operation. This process REF V determines the range over which the common ensures that one complete conversion cycle always REF voltage may vary, as shown in Figure 38 and returns the part to its factory-adjusted state in the Figure39. eventofapowerinterruption. The ADS8317 requires an external reference, an Single-Ended Input external clock, and a single power source (V ). The DD external reference can be any voltage between 0.1V and V /2. The value of the reference voltage directly 2´V DD REF ADS8317 sets the range of the analog input. The reference Peak-to-Peak input current depends on the conversion rate of the Common ADS8317. Voltage The external clock can vary between 24kHz (1kHz throughput) and 6.0MHz (250kHz throughput). The Differential Input duty cycle of the clock is not significant, as long as the minimum high and low times are at least 200ns V (V = 4.75V or greater). The minimum clock REF DD Peak-to-Peak frequency is set by the leakage on the internal ADS8317 capacitorstotheADS8317. Common V REF Voltage Peak-to-Peak The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input on these pins is sampled on the Figure37. MethodsofDrivingthe internal capacitor array. While a conversion is in ADS8317—Single-EndedorDifferential progress, both inputs are disconnected from any internalfunction. The digital result of the conversion is clocked out by the DCLOCK input and is provided serially (most significantbitfirst)ontheD pin. OUT 16 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8317

ADS8317 www.ti.com.................................................................................................................................................... SBAS356D–JUNE2007–REVISEDOCTOBER2009 5 5 V = 5V V = 5V DD DD V) 4 3.8 V) 4 3.8 e ( e ( ng 3 2.8 ng 3 2.75 a a R R e e oltag 2 Single-Ended Input 2.2 oltag 2 Differential Input V V on 1 on 1 mm 0.2 mm 0.95 o o C 0 C 0 -0.3 -0.3 -1 -1 00 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5 V (V) V (V) REF REF Figure38. Single-Ended5VInput, Figure40. Differential5VInput, CommonVoltageRangevsV CommonVoltageRangevsV REF REF 3.0 3.0 V = 2.7V V = 2.7V DD DD 2.5 2.5 V) V) e ( 2.0 e ( 2.0 g g n 1.5 1.5 n 1.5 1.5 Ra 1.5 Ra 1.5 e e ag 1.0 Single-Ended Input ag 1.0 Volt 1.05 Volt Differential Input on 0.5 0.2 on 0.5 0.5 m m m 0 m 0 o o C -0.5 -0.2 C -0.5 -0.3 0.5 -1.0 -1.0 0.10 0.35 0.60 0.85 1.10 1.35 00 0.25 0.50 0.75 1.00 1.25 V (V) V (V) REF REF Figure39. Single-Ended2.7VInput, Figure41. Differential2.7VInput, CommonVoltageRangevsV CommonVoltageRangevsV REF REF When the input is differential, the amplitude of the In each case, care should be taken to ensure that the input is the difference between the +IN and –IN input, output impedance of the sources driving the +IN and or +IN – (–IN). A voltage or signal is common to both –IN inputs are matched. If this matching is not of these inputs. The peak-to-peak amplitude of each observed, the two inputs could have different settling input is V about this common voltage. However, times. This difference may result in offset error, gain REF since the inputs are 180° out-of-phase, the error, and linearity error that change with both peak-to-peak amplitude of the difference voltage is 2 temperature and input voltage. If the impedance × V . The value of V also determines the range cannot be matched, the errors can be lessened by REF REF of the voltage that may be common to both inputs, as givingtheADS8317additionalacquisitiontime. showninFigure41andFigure40. Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):ADS8317

ADS8317 SBAS356D–JUNE2007–REVISEDOCTOBER2009.................................................................................................................................................... www.ti.com The input current on the analog inputs depends on a REFERENCE INPUT number of factors: sample rate, input voltage, and The external reference sets the analog input range. source impedance. Essentially, the current into the The ADS8317 operates with a reference in the range ADS8317 charges the internal capacitor array during of 0.1V to V /2. There are several important the sample period. After this capacitance has been DD implicationstothisspecification. fully charged, there is no further input current. The source of the analog input voltage must be able to As the reference voltage is reduced, the analog charge the input capacitance (24pF) to 16-bit settling voltage weight of each digital output code is reduced. level within 4.5 clock cycles. When the converter This reduction is often referred to as the least goes into the hold mode, or while it is in the significant bit (LSB) size and is equal to the reference power-down mode, the input impedance is greater voltage divided by 65,536. This relationship means than1GΩ. that any offset or gain error inherent in the A/D converter appears to increase (in terms of LSB size) Care must be taken regarding the absolute analog as the reference voltage is reduced. For a reference input voltage. The +IN input should always remain voltage of 2.5V, the value of the LSB is 76.3μV, and within the range of GND – 300mV to V + 300mW. DD forareferencevoltageof1.25V,theLSBis38.15μV. The –IN input should always remain within the range of GND – 300mV to 4V. Outside of these ranges, the The noise inherent in the converter also appears to converter linearity may not meet specifications. To increase with a lower LSB size. With a 2.5V obtain maximum performance from the ADS8317, an reference, the internal noise of the converter typically input circuit such as that shown in Figure 42 is contributes only 5LSB peak-to-peak of potential error recommended. to the output code. When the external reference is 1.25V, the potential error contribution from the internal noise is almost two times larger (9LSB). The Single-Ended errors arising from the internal noise are Gaussian in nature and can be reduced by averaging consecutive 10W +IN 50W 24pF conversionresults. OPA365 1000pF For more information regarding noise, consult ADS8317 Figure 18, Peak-to-Peak Noise for a DC Input vs -IN 50W 24pF ReferenceVoltage.NotethattheEffectiveNumberOf Bits (ENOB) figure is calculated based on the + V converter signal-to-(noise + distortion) ratio with a CM 2kHz, 0dB input signal. SINAD is related to ENOB as follows: SINAD=6.02×ENOB+1.76 Differential With lower reference voltages, extra care should be taken to provide a clean layout including adequate 10W +IN 50W 24pF bypassing, a clean power supply, a low-noise OPA365 reference, and a low-noise input signal. Due to the 1000pF lower LSB size, the converter is also more sensitive 1nF ADS8317 to external sources of error, such as nearby digital signalsandelectromagneticinterference. 10W -IN 50W 24pF OPA365 1000pF Figure42. Single-EndedandDifferentialMethods ofInterfacingtheADS8317 18 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8317

ADS8317 www.ti.com.................................................................................................................................................... SBAS356D–JUNE2007–REVISEDOCTOBER2009 The equivalent input circuit for the reference voltage Noise is presented in Figure 43. At the same time, an The transition noise of the ADS8317 itself is equivalent capacitor of 24pF is switched. To obtain extremely low, as shown in Figure 19 and Figure 36; optimum performance from the ADS8317, special it is much lower than competing A/D converters. care must be taken in designing the interface circuit These histograms were generated by applying a to the reference input pin. To ensure a stable low-noise DC input and initiating 8192 conversions. reference voltage, a 47μF tantalum capacitor with low The digital output of the A/D converter varies in ESR should be connected as close as possible to the output code because of the internal noise of the input pin. If a high output impedance reference ADS8317. This variance is true for all 16-bit, source is used, an additional operational amplifier SAR-type A/D converters. Using a histogram to plot with a current-limiting resistor must be placed in front the output codes, the distribution should appear ofthecapacitors. bell-shaped with the peak of the bell curve representing the nominal code for the input value. The ±1σ, ±2σ, and ±3σ distributions represent 68.3%, ADS8317 95.5%, and 99.7%, respectively, of all codes. The V 50W 24pF transition noise can be calculated by dividing the REF OPA350 number of codes measured by 6, which yields the 47mF ±3σ distribution, or 99.7%, of all codes. Statistically, up to three codes could fall outside the distribution when executing 1000 conversions. The ADS8317, with five output codes for the ±3σ distribution, yields Figure43. InputReferenceCircuitandInterface less than ±0.8LSB of transition noise. Remember that to achieve this low-noise performance, the peak-to-peak noise of the input signal and reference WhentheADS8317isinpower-downmode,theinput mustbelessthan50μV. resistance of the reference pin has a value of 5GΩ. Because the input capacitors must be recharged Averaging before the next conversion starts, an operational amplifier with good dynamic characteristics, such as The noise of the A/D converter can be compensated the OPA350, should be used to buffer the reference by averaging the digital codes. By averaging input. conversion results, transition noise is reduced by a factor of 1/√n , where n is the number of averages. For example, averaging four conversion results reduces the transition noise from ±0.8LSB to ±0.4LSB. Averaging should only be used for input signalswithfrequenciesnearDC. For AC signals, a digital filter can be used to low-pass filter and decimate the output codes. This configuration works in a similar manner to averaging; for every decimation by 2, the signal-to-noise ratio improvesby3dB. Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):ADS8317

ADS8317 SBAS356D–JUNE2007–REVISEDOCTOBER2009.................................................................................................................................................... www.ti.com DIGITAL INTERFACE After the fifth falling DCLOCK edge, D is enabled OUT and outputs a low value for one clock period. For the SignalLevels next 16 DCLOCK periods, D outputs the OUT conversion result, most significant bit first. After the The ADS8317 has a wide range of power-supply least significant bit (B0) has been output, subsequent voltage. The A/D converter, as well as the digital clocksrepeattheoutputdata,butinaleastsignificant interface circuit, is designed to accept and operate bitfirstformat. from 2.7V up to 5.5V. This voltage range accommodates different logic levels. When the After the most significant bit (B15) has been ADS8317 power-supply voltage is in the range of repeated, D will 3-state. Subsequent clocks have OUT 4.5V to 5.5V (5V logic level), the ADS8317 can be no effect on the converter. A new conversion is connected directly to another 5V, CMOS-integrated initiated only when CS has been taken high and circuit.WhentheADS8317power-supplyvoltageisin returnedlow. the range of 2.7V to 3.6V (3V logic level), the ADS8317 can be connected directly to another 3.3V DataFormat LVCMOSintegratedcircuit. The output data from the ADS8317 are in binary twos complement format, as shown in Table 1 and SerialInterface Figure 44. The table and figure represent the ideal The ADS8317 communicates with microprocessors output code for the given input voltage and do not and other digital systems via a synchronous 3-wire includetheeffectsofoffset,gainerror,ornoise. serial interface, as illustrated in the Timing Information section and Timing Characteristics . The Table1.IdealInputVoltagesandOutputCodes DCLOCK signal synchronizes the data transfer, with each bit being transmitted on the falling edge of DESCRIPTION ANALOGVALUE DIGITALOUTPUT DCLOCK. Most receiving systems capture the Full-scalerange 2×VREF BINARYTWOSCOMPLEMENT bitstream on the rising edge of DCLOCK. However, if Leastsignificant 2×VREF/65536 Binary Hex the minimum hold time for D is acceptable, the bit(LSB) Code Code OUT system can use the falling edge of DCLOCK to +Fullscale +VREF–1LSB 0111111111111111 7FFF captureeachbit. Midscale 0V 0000000000000000 0000 A falling CS signal initiates the conversion and data Midscale–1LSB 0V–1LSB 1111111111111111 FFFF transfer. The first 4.5 to 5.0 clock periods of the –Fullscale –VREF 1000000000000000 8000 conversion cycle are used to sample the input signal. 20 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8317

ADS8317 www.ti.com.................................................................................................................................................... SBAS356D–JUNE2007–REVISEDOCTOBER2009 BinaryTwos Complement 0111 1111 1111 1111 65535 0111 1111 1111 1110 65534 0111 1111 1111 1101 65533 e d Co 0000 0000 0000 0001 32769 Output 0000 0000 0000 0000 32768 Step gital 1111 1111 1111 1111 32767 Di 1000 0000 0000 0010 2 1000 0000 0000 0001 1 1000 0000 0000 0000 0 V =-2.5V -38.15mV +38.15mV V = V = 2.5V -FS +FS REF -2.49996V 0V V+FS-1LSB = 2.499992V -2.49992V 2.499985V Bipolar Analog Input Voltage = V(+IN)-V(-IN) -2.49985V 1LSB = 76.29mV 16-BIT VCM= 2.5V Twos Complement Output Bipolar Analog Input VREF= 2.5V -Full-Scale Code V =8000h V =-V -FS CODE REF Midscale Code V = 0000h V = 0V MS CODE +Full-Scale Code V = 7FFFh V = V -1LSB +FS CODE REF Figure44. IdealConversionCharacteristics(Conditions:V =2.5V,V =2.5V) CM REF Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):ADS8317

ADS8317 SBAS356D–JUNE2007–REVISEDOCTOBER2009.................................................................................................................................................... www.ti.com POWER DISSIPATION ShortCycling The architecture of the converter, the semiconductor Another way to save power is to use the CS signal to fabrication process, and a careful design allow the short-cycle the conversion. The ADS8317 places the ADS8317 to convert at up to a 250kHz rate while latest data bit on the D line as it is generated; OUT requiring very little power. However, for the absolute therefore, the converter can easily be short-cycled. lowest power dissipation, there are several things to This term means that the conversion can be keepinmind. terminated at any time. For example, if only 14 bits of theconversionresultareneeded,thentheconversion The power dissipation of the ADS8317 scales directly can be terminated (by pulling CS high) after the 14th with conversion rate. Therefore, the first step to bithasbeenclockedout. achieving the lowest power dissipation is to find the lowest conversion rate that satisfies the system This technique can also be used to lower the power requirements. dissipation (or to increase the conversion rate) in those applications where an analog signal is being In addition, the ADS8317 goes into Power-Down monitored until some condition becomes true. For mode under two conditions: when the conversion is example, if the signal is outside a predetermined complete and whenever CS is high (see the Timing range, the full 16-bit conversion result may not be Characteristics section). Ideally, each conversion needed. If so, the conversion can be terminated after should occur as quickly as possible, preferably at a the first n bits, where n might be as low as 3 or 4. 6.0MHz clock rate. This way, the converter spends This technique results in lower power dissipation in the longest possible time in power-down mode. This both the converter and the rest of the system is very important because the converter not only uses becausetheyspendmoretimeinpower-downmode. power on each DCLOCK transition (as is typical for digital CMOS components), but also uses some POWER-ON RESET current for the analog circuitry, such as the comparator. The analog section dissipates power The ADS8317 bias circuit is self-starting. There may continuouslyuntilpower-downmodeisentered. be a static current (approximately 1.5mA with V = DD 5V) after power-on, unless the circuit is powered Figure 9 and Figure 27 illustrate the current down. It is recommended to run a single test consumptionoftheADS8317versussamplerate.For conversion (configured the same as any regular these graphs, the converter is clocked at maximum conversion) after the power supply reaches at least speed regardless of the sample rate. CS is held high 2.4V to ensure the device is put into power-down duringtheremainingsampleperiod. mode. There is an important distinction between the power-down mode that is entered after a conversion is complete and the full power-down mode that is enabled when CS is high. CS low only shuts down the analog section. The digital section completely shuts down only when CS is high. Thus, if CS is left low at the end of a conversion, and the converter is continually clocked, the power consumption is not as lowaswhenCSishigh. 22 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8317

ADS8317 www.ti.com.................................................................................................................................................... SBAS356D–JUNE2007–REVISEDOCTOBER2009 LAYOUT The reference should be similarly bypassed with a 47μF capacitor. Again, a series resistor and large For optimum performance, care should be taken with capacitor can be used to low-pass filter the reference the physical layout of the ADS8317 circuitry. This voltage. If the reference voltage originates from an op caution is particularly true if the reference voltage is amp, make sure that the op amp can drive the low and/or the conversion rate is high. At a 250kHz bypass capacitor without oscillation (the series conversion rate, the ADS8317 makes a bit decision resistor can help in this case). Keep in mind that every 167ns. That is, for each subsequent bit while the ADS8317 draws very little current from the decision, the digital output must be updated with the reference on average, there are still instantaneous results of the last bit decision, the capacitor array current demands placed on the external input and appropriately switched and charged, and the input to referencecircuitry. the comparator settled to a 16-bit level, all within one clockcycle. Texas Instruments' OPA365 op amp provides optimum performance for buffering the signal inputs; The basic SAR architecture is sensitive to spikes on the OPA350 can be used to effectively buffer the the power supply, reference, and ground connections referenceinput. that occur just prior to latching the comparator output. Thus, during any single conversion for an n-bit SAR Also, keep in mind that the ADS8317 offers no converter, there are n windows in which large inherent rejection of noise or voltage variation in external transient voltages can easily affect the regards to the reference input. This characteristic is conversion result. Such spikes might originate from of particular concern when the reference input is tied switching power supplies, digital logic, and to the power supply. Any noise and ripple from the high-power devices, to name a few potential sources. supply appears directly in the digital results. While This particular source of error can be very difficult to high-frequency noise can be filtered out, as described track down if the glitch is almost synchronous to the in the previous paragraph, voltage variation resulting converter DCLOCK signal because the phase from the line frequency (50Hz or 60Hz) can be difference between the glitch and DCLOCK changes difficulttoremove. with time and temperature, causing sporadic The GND pin on the ADS8317 should be placed on a misoperation. clean ground point. In many cases, this point is the With these considerations in mind, power to the analog ground. Avoid connecting the GND pin too ADS8317 should be clean and well-bypassed. A close to the grounding point for a microprocessor, 0.1μF ceramic bypass capacitor should be placed as microcontroller, or digital signal processor. If needed, close as possible to the ADS8317 package. In run a ground trace directly from the converter to the addition, a 1μF to 10μF capacitor and a 5Ω or 10Ω power-supply connection point. The ideal layout series resistor may be used to low-pass filter a noisy includes an analog ground plane for the converter supply. andassociatedanalogcircuitry. Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):ADS8317

ADS8317 SBAS356D–JUNE2007–REVISEDOCTOBER2009.................................................................................................................................................... www.ti.com APPLICATION CIRCUITS on the supply, as well as any high-frequency noise Figure 45 shows an example of a basic data from the supply itself. The exact values should be acquisition system. The ADS8317 input range is picked such that the filter provides adequate rejection connected to 2.5V or 4.096V. The 5Ω resistor and of noise. Operational amplifiers and voltage reference 1μF to 10μF capacitor filters the microcontroller noise areconnectedtotheanalogpowersupply,AV . DD DV DD 2.7V to 3.6V + 0.1mF 10mF AV DD 5W 2.7V to 5V REF3225 10W OPA350 REF V DD IN OUT 47mF 0.1mF + 10mF 2.2mF 0.47mF GND ADS8317 DSP 10W TMS320C6xx OPA365 +IN or V + (0V to 2.5V) TMS320C5xx CM 1000pF CS or TMS320C2xx 1nF D OUT DCLOCK 10W OPA365 -IN GND GND V CM 1000pF Figure45. ExampleofaBasicDataAcquisitionSystem 24 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):ADS8317

ADS8317 www.ti.com.................................................................................................................................................... SBAS356D–JUNE2007–REVISEDOCTOBER2009 REVISION HISTORY NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionC(June2008)toRevisionD .................................................................................................... Page • ChangedSON-8(DRB)packageavailability ........................................................................................................................ 1 • Deletedleadtemperaturespecification ................................................................................................................................ 2 • AddedmissingmusymboltoHigh-leveloutputvoltagetestcondition................................................................................. 4 • AddedmissingmusymboltoLow-leveloutputvoltagetestcondition ................................................................................. 4 • ChangedX-axisunitfrommAtoμAinFigure10 ............................................................................................................... 11 • ChangedFigure38 ............................................................................................................................................................. 17 • ChangedFigure39 ............................................................................................................................................................. 17 • ChangedFigure40title(typo) ............................................................................................................................................ 17 • AddedmissingmusymboltothevalueoftheLSB,76.3V ................................................................................................ 18 ChangesfromRevisionB(May2008)toRevisionC ...................................................................................................... Page • Changed2ndtimingdiagramfromthetopinFigure1 ......................................................................................................... 8 Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):ADS8317

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ADS8317IBDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAU | Level-2-260C-1 YEAR -40 to 85 D17 & no Sb/Br) CU NIPDAUAG ADS8317IBDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS CU NIPDAU | Level-2-260C-1 YEAR -40 to 85 D17 & no Sb/Br) CU NIPDAUAG ADS8317IBDRBR ACTIVE SON DRB 8 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D17 & no Sb/Br) ADS8317IBDRBT ACTIVE SON DRB 8 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D17 & no Sb/Br) ADS8317IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAU | Level-2-260C-1 YEAR -40 to 85 D17 & no Sb/Br) CU NIPDAUAG ADS8317IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS CU NIPDAU | Level-2-260C-1 YEAR -40 to 85 D17 & no Sb/Br) CU NIPDAUAG ADS8317IDRBR ACTIVE SON DRB 8 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D17 & no Sb/Br) ADS8317IDRBT ACTIVE SON DRB 8 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D17 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ADS8317IBDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8317IBDGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8317IBDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 ADS8317IBDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 ADS8317IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8317IDGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8317IDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 ADS8317IDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ADS8317IBDGKR VSSOP DGK 8 2500 350.0 350.0 43.0 ADS8317IBDGKT VSSOP DGK 8 250 210.0 185.0 35.0 ADS8317IBDRBR SON DRB 8 3000 350.0 350.0 43.0 ADS8317IBDRBT SON DRB 8 250 210.0 185.0 35.0 ADS8317IDGKR VSSOP DGK 8 2500 350.0 350.0 43.0 ADS8317IDGKT VSSOP DGK 8 250 210.0 185.0 35.0 ADS8317IDRBR SON DRB 8 3000 350.0 350.0 43.0 ADS8317IDRBT SON DRB 8 250 210.0 185.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE DRB0008B VSON - 1 mm max height SCALE 4.000 PLASTIC SMALL OUTLINE - NO LEAD 3.1 B A 2.9 PIN 1 INDEX AREA 3.1 2.9 C 1 MAX SEATING PLANE 0.05 0.08 C 0.00 EXPOSED 1.65 0.05 (0.2) TYP THERMAL PAD 4 5 2X 1.95 2.4 0.05 8 1 6X 0.65 0.35 8X 0.25 PIN 1 ID 0.5 0.1 C A B (OPTIONAL) 8X 0.3 0.05 C 4218876/A 12/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT DRB0008B VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD (1.65) 8X (0.6) SYMM 1 8 8X (0.3) (2.4) (0.95) 6X (0.65) 4 5 (R0.05) TYP (0.575) ( 0.2) VIA (2.8) TYP LAND PATTERN EXAMPLE SCALE:20X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4218876/A 12/2017 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN DRB0008B VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD SYMM 8X (0.6) METAL TYP 1 8X (0.3) 8 (0.63) SYMM 6X (0.65) (1.06) 5 4 (R0.05) TYP (1.47) (2.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 81% PRINTED SOLDER COVERAGE BY AREA SCALE:25X 4218876/A 12/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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