1.2 A, Low V , Low Dropout IN Linear Regulator Data Sheet ADP1754/ADP1755 FEATURES TYPICAL APPLICATION CIRCUITS Maximum output current: 1.2 A VIN = 1.8V VOUT = 1.5V Input voltage range: 1.6 V to 3.6 V 4.7µF 4.7µF Low shutdown current: <2 µA 16 15 14 13 Very low dropout voltage: 105 mV at 1.2 A load VIN VIN VOUTVOUT Initial accuracy: ±1% 1VIN VOUT12 Accuracy over line, load, and temperature: ±2% 100kΩ 2VIN ADP1754 VOUT11 7 fixed output voltage options with soft start TOP VIEW 0.75 V to 2.5 V (ADP1754) 3VIN (Not to Scale) VOUT10 Adjustable output voltage option with soft start PG 4EN SENSE 9 0.75 V to 3.3 V (ADP1755) PG GND SS NC High PSRR 5 6 7 8 65 dB at 1 kHz 6554 ddBB aatt 1100 0k HkHz z 10nF 07722-001 Figure 1. ADP1754 with Fixed Output Voltage, 1.5 V 23 μV rms at 0.75 V output Stable with small 4.7 µF ceramic output capacitor VIN = 1.8V VOUT = 0.5V(1 + R1/R2) Excellent load and line transient response 4.7µF 4.7µF Current-limit and thermal overload protection 16 15 14 13 VIN VIN VOUTVOUT Power-good indicator 1VIN VOUT12 Logic-controlled enable Reverse current protection 100kΩ 2VIN ADP1755 VOUT11 TOP VIEW APPLICATIONS 3VIN (Not to Scale) VOUT10 R1 PG Server computers 4EN ADJ 9 Memory components PG GND SS NC R2 5 6 7 8 Telecommunications equipment DNeStPw/FoPrGk Aeq/muiipcrmopenrot cessor supplies 10nF 07722-002 Figure 2. ADP1755 with Adjustable Output Voltage, 0.75 V to 3.3 V Instrumentation equipment/data acquisition systems GENERAL DESCRIPTION The ADP1754/ADP1755 are low dropout (LDO) CMOS linear voltages that range from 0.75 V to 3.3 V via an external divider. regulators that operate from 1.6 V to 3.6 V and provide up to The ADP1754/ADP1755 allow an external soft start capacitor 1.2 A of output current. These low V /V LDOs are ideal for to be connected to program the startup. A digital power-good IN OUT regulation of nanometer FPGA geometries operating from 2.5 V output allows power system monitors to check the health of the down to 1.8 V I/O rails, and for powering core voltages down to output voltage. 0.75 V. Using an advanced proprietary architecture, the ADP1754/ The ADP1754/ADP1755 are available in a 16-lead, 4 mm × 4 mm ADP1755 provide high power supply rejection ratio (PSRR) and LFCSP, making them not only very compact solutions, but also low noise, and achieve excellent line and load transient response providing excellent thermal performance for applications that with only a small 4.7 µF ceramic output capacitor. require up to 1.2 A of output current in a small, low profile The ADP1754 is available in seven fixed output voltage options. footprint. The ADP1755 is the adjustable version, which allows output Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2008–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADP1754/ADP1755 Data Sheet TABLE OF CONTENTS Soft Start Function (ADP1754/ADP1755) ............................. 11 Features .............................................................................................. 1 Applications ....................................................................................... 1 Adjustable Output Voltage (ADP1755) ................................... 12 Typical Application Circuits ............................................................ 1 Enable Feature ............................................................................ 12 Power-Good Feature .................................................................. 12 General Description ......................................................................... 1 Reverse Current Protection Feature ........................................ 13 Revision History ............................................................................... 2 Applications Information .............................................................. 14 Specifications ..................................................................................... 3 Capacitor Selection .................................................................... 14 Input and Output Capacitor, Recommended Specifications .. 4 Absolute Maximum Ratings ............................................................ 5 Undervoltage Lockout ............................................................... 15 Thermal Data ................................................................................ 5 Current-Limit and Thermal Overload Protection ................. 15 Thermal Resistance ...................................................................... 5 Thermal Considerations ............................................................ 15 PCB Layout Considerations ...................................................... 18 ESD Caution .................................................................................. 5 Outline Dimensions ....................................................................... 19 Pin Configurations and Function Descriptions ........................... 6 Ordering Guide .......................................................................... 19 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 11 REVISION HISTORY 4/14—Rev. F to Rev. G 4/09—Rev. 0 to Rev. A Changes to Figure 1 and Figure 2 ................................................... 1 Changes to Adjustable Output Voltage Accuracy (ADP1755) Change to Table 4 ............................................................................. 5 Parameter, Table 1 ............................................................................. 3 Changes to Figure 3 and Figure 4 ................................................... 6 Changes to Table 3 ............................................................................. 5 Updated Outline Dimensions ....................................................... 19 10/08—Revision 0: Initial Version Changes to Ordering Guide .......................................................... 19 8/13—Rev. E to Rev. F Changes to Ordering Guide .......................................................... 19 6/13—Rev. D to Rev. E Changed Adjustable Output Voltage Option with Soft Start (ADP1755) from 0.75 V to 3.0 V to 0.75 V to 3.3 V (Throughout) .................................................................................... 1 Updated Outline Dimensions ....................................................... 19 12/12—Rev. C to Rev. D Added Junction Temperature of 150°C, Table 3 ........................... 5 9/12—Rev. B to Rev. C Changes to Absolute Maximum Ratings, Table 3......................... 5 Changes to Ordering Guide .......................................................... 19 2/10—Rev. A to Rev. B Changes to Table 4 ............................................................................ 5 Changes to Ordering Guide .......................................................... 19 Rev. G | Page 2 of 20

Data Sheet ADP1754/ADP1755 SPECIFICATIONS V = (V + 0.4 V) or 1.6 V (whichever is greater), I = 10 mA, C = C = 4.7 µF, T = 25°C, unless otherwise noted. IN OUT OUT IN OUT A Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT VOLTAGE RANGE V T = −40°C to +125°C 1.6 3.6 V IN J OPERATING SUPPLY CURRENT1 I I = 500 μA 90 µA GND OUT I = 100 mA 400 µA OUT I = 100 mA, T = −40°C to +125°C 800 µA OUT J I = 1.2 A 1.1 mA OUT I = 1.2 A, T = −40°C to +125°C 1.4 mA OUT J SHUTDOWN CURRENT I EN = GND, V = 1.6 V 2 6 µA GND-SD IN EN = GND, V = 1.6 V, T = −40°C to +85°C 30 µA IN J EN = GND, V = 3.6 V, T = −40°C to +85°C 100 µA IN J OUTPUT VOLTAGE ACCURACY Fixed Output Voltage Accuracy V I = 10 mA −1 +1 % OUT OUT (ADP1754) I = 10 mA to 1.2 A −1.5 +1.5 % OUT 10 mA < I < 1.2 A, T = −40°C to +125°C −2 +2 % OUT J Adjustable Output Voltage Accuracy V I = 10 mA 0.495 0.5 0.505 V ADJ OUT (ADP1755)2 I = 10 mA to 1.2 A 0.495 0.505 V OUT 10 mA < I < 1.2 A, T = −40°C to +125°C 0.490 0.510 V OUT J LINE REGULATION ∆V /∆V V = (V + 0.4 V) to 3.6 V, T = −40°C to +125°C −0.3 +0.3 %/V OUT IN IN OUT J LOAD REGULATION3 ∆V /∆I I = 10 mA to 1.2 A, T = −40°C to +125°C 0.6 %/A OUT OUT OUT J DROPOUT VOLTAGE4 V I = 100 mA, V ≥ 1.8 V 10 mV DROPOUT OUT OUT I = 100 mA, V ≥ 1.8 V, T = −40°C to +125°C 16 mV OUT OUT J I = 1.2 A, V ≥ 1.8 V 105 mV OUT OUT I = 1.2 A, V ≥ 1.8 V, T = −40°C to +125°C 200 mV OUT OUT J START-UP TIME5 t C = 0 nF, I = 10 mA 200 µs START-UP SS OUT C = 10 nF, I = 10 mA 5.2 ms SS OUT CURRENT-LIMIT THRESHOLD6 I 1.5 2 5 A LIMIT THERMAL SHUTDOWN Thermal Shutdown Threshold TSSD TJ rising 150 °C Thermal Shutdown Hysteresis TSSD-HYS 15 °C PG OUTPUT LOGIC LEVEL PG Output Logic High PG 1.6 V ≤ V ≤ 3.6 V, I < 1 µA 1.0 V HIGH IN OH PG Output Logic Low PG 1.6 V ≤ V ≤ 3.6 V, I < 2 mA 0.4 V LOW IN OL PG Output Delay from EN Transition 1.6 V ≤ V ≤ 3.6 V, C = 10 nF 5.5 ms IN SS Low to High PG OUTPUT THRESHOLD Output Voltage Falling PG 1.6 V ≤ V ≤ 3.6 V −10 % FALL IN Output Voltage Rising PG 1.6 V ≤ V ≤ 3.6 V −6.5 % RISE IN EN INPUT EN Input Logic High V 1.6 V ≤ V ≤ 3.6 V 1.2 V IH IN EN Input Logic Low V 1.6 V ≤ V ≤ 3.6 V 0.4 V IL IN EN Input Leakage Current V EN = VIN or GND 0.1 1 µA I-LEAKAGE UNDERVOLTAGE LOCKOUT UVLO Input Voltage Rising UVLO T = −40°C to +125°C 1.58 V RISE J Input Voltage Falling UVLO T = −40°C to +125°C 1.25 V FALL J Hysteresis UVLO T = 25°C 100 mV HYS J SOFT START CURRENT I 1.6 V ≤ V ≤ 3.6 V 0.6 0.9 1.2 µA SS IN ADJ INPUT BIAS CURRENT (ADP1755) ADJ 1.6 V ≤ V ≤ 3.6 V, T = −40°C to +125°C 10 150 nA I-BIAS IN J SENSE INPUT BIAS CURRENT SNS 1.6 V ≤ V ≤ 3.6 V 10 µA I-BIAS IN Rev. G | Page 3 of 20

ADP1754/ADP1755 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit OUTPUT NOISE OUT 10 Hz to 100 kHz, V = 0.75 V 23 µV rms NOISE OUT 10 Hz to 100 kHz, V = 2.5 V 65 µV rms OUT POWER SUPPLY REJECTION RATIO PSRR V = V + 1 V, I = 10 mA IN OUT OUT 1 kHz, V = 0.75 V 65 dB OUT 1 kHz, V = 2.5 V 56 dB OUT 10 kHz, V = 0.75 V 65 dB OUT 10 kHz, V = 2.5 V 56 dB OUT 100 kHz, V = 0.75 V 54 dB OUT 100 kHz, V = 2.5 V 51 dB OUT 1 Minimum output load current is 500 μA. 2 Accuracy when VOUT is connected directly to ADJ. When VOUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances of resistors used. 3 Based on an end-point calculation using 10 mA and 1.2 A loads. See Figure 6 for typical load regulation performance. 4 Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages above 1.6 V. 5 Start-up time is defined as the time between the rising edge of EN to VOUT being at 95% of its nominal value. 6 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V. INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit MINIMUM INPUT AND OUTPUT CAPACITANCE1 C T = −40°C to +125°C 3.3 µF MIN A CAPACITOR ESR R T = −40°C to +125°C 0.001 0.1 Ω ESR A 1 The minimum input and output capacitance should be greater than 3.3 µF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with this LDO. Rev. G | Page 4 of 20

Data Sheet ADP1754/ADP1755 ABSOLUTE MAXIMUM RATINGS Junction-to-ambient thermal resistance (θ ) of the package is Table 3. JA based on modeling and calculation using a 4-layer board. The Parameter Rating junction-to-ambient thermal resistance is highly dependent VIN to GND −0.3 V to +4.0 V on the application and board layout. In applications where high VOUT to GND −0.3 V to VIN maximum power dissipation exists, close attention to thermal EN to GND −0.3 V to VIN board design is required. The value of θ may vary, depending SS to GND −0.3 V to VIN JA on PCB material, layout, and environmental conditions. The PG to GND −0.3 V to +4.0 V specified values of θ are based on a 4-layer, 4 in × 3 in circuit SENSE/ADJ to GND −0.3 V to VIN JA board. Refer to JEDEC JESD51-7 for detailed information about Storage Temperature Range −65°C to +150°C board construction. For more information, see the AN-772 Junction Temperature Range −40°C to +125°C Application Note, A Design and Manufacturing Guide for the Junction Temperature 150°C Lead Frame Chip Scale Package (LFCSP). Soldering Conditions JEDEC J-STD-020 Ψ is the junction-to-board thermal characterization parameter JB Stresses above those listed under Absolute Maximum Ratings with units of °C/W. Ψ of the package is based on modeling and JB may cause permanent damage to the device. This is a stress calculation using a 4-layer board. The JESD51-12 document, rating only; functional operation of the device at these or any Guidelines for Reporting and Using Electronic Package Thermal other conditions above those indicated in the operational Information, states that thermal characterization parameters are section of this specification is not implied. Exposure to absolute not the same as thermal resistances. Ψ measures the component JB maximum rating conditions for extended periods may affect power flowing through multiple thermal paths rather than through device reliability. a single path as in thermal resistance, θ . Therefore, Ψ thermal JB JB THERMAL DATA paths include convection from the top of the package as well as Absolute maximum ratings apply individually only, not in radiation from the package, factors that make ΨJB more useful in combination. The ADP1754/ADP1755 may be damaged if the real-world applications. Maximum junction temperature (TJ) junction temperature limits are exceeded. Monitoring ambient is calculated from the board temperature (TB) and the power temperature does not guarantee that TJ is within the specified dissipation (PD) using the following formula: temperature limits. In applications with high power dissipation T = T + (P × Ψ ) J B D JB and poor thermal resistance, the maximum ambient temperature Refer to the JEDEC JESD51-8 and JESD51-12 documents for more may need to be derated. In applications with moderate power detailed information about Ψ . JB dissipation and low PCB thermal resistance, the maximum THERMAL RESISTANCE ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. θ and Ψ are specified for the worst-case conditions, that is, a JA JB The junction temperature (T) of the device is dependent on the device soldered in a circuit board for surface-mount packages. J ambient temperature (T ), the power dissipation of the device A Table 4. Thermal Resistance (P ), and the junction-to-ambient thermal resistance of the D Package Type θ Ψ Unit package (θ ). T is calculated using the following formula: JA JB JA J 16-Lead LFCSP with Exposed Pad (CP-16-23) 42 25.5 °C/W T = T + (P × θ ) J A D JA ESD CAUTION Rev. G | Page 5 of 20

ADP1754/ADP1755 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS T T T T VIN VIN VOU VOU VIN VIN VOU VOU 61 51 41 31 61 51 41 31 VIN1 12VOUT VIN1 12VOUT VIN 2 ADP1754 11VOUT VIN 2 ADP1755 11VOUT VIN 3 (NToOt Pto V SIEcWale) 10VOUT VIN 3 (NToOt Pto V SIEcWale) 10VOUT EN 4 9 SENSE EN 4 9 ADJ 5 6 7 8 5 6 7 8 G D S C G D S C P N S N P N S N G G NOTES 1.NC = NO CONNECT. NOTES 2.THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES 1.NC = NO CONNECT. TIBNHESE ICDROEMN ATNLHE EPC EPTREAFDCO KTRAOMG TAEHN. EICT GE I SRA ORNUEDNC ISDO MEPLLMEAECNNTEDR EOICDNA TTLHHLAEYT BC TOOHANERN EDEX.CPTOESDE TDO P GANDD 07722-003 2.TIBTNHHESE EICDR EOEMXN ATPNLHOE ESPC EEPTDREA FDCPO KATRADOMG OTAEHNN. E ICTT GHE I SERA ORBNUEODNC TISDOT OMEPMLLMEA EOCNNFTED RT EOIHCDNEA T TLLHHFLAECYT SBC TPOOH EANENRN EHDEXA.CPNTOCESEDES TDO P GANDD 07722-004 Figure 3. ADP1754 Pin Configuration Figure 4. ADP1755 Pin Configuration Table 5. Pin Function Descriptions ADP1754 ADP1755 Pin No. Pin No. Mnemonic Description 1, 2, 3, 15, 1, 2, 3, 15, VIN Regulator Input Supply. Bypass VIN to GND with a 4.7 µF or greater capacitor. Note that all five 16 16 VIN pins must be connected to the source. 4 4 EN Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the regulator. For automatic startup, connect EN to VIN. 5 5 PG Power Good. This open-drain output requires an external pull-up resistor to VIN. If the part is in shutdown mode, current-limit mode, thermal shutdown, or if it falls below 90% of the nominal output voltage, PG immediately transitions low. 6 6 GND Ground. 7 7 SS Soft Start. A capacitor connected to this pin determines the soft start time. 8 8 NC Not Connected. No internal connection. 9 N/A SENSE Sense. This pin measures the actual output voltage at the load and feeds it to the error amplifier. Connect SENSE as close as possible to the load to minimize the effect of IR drop between the regulator output and the load. N/A 9 ADJ Adjust. A resistor divider from VOUT to ADJ sets the output voltage. 10, 11, 12, 10, 11, 12, VOUT Regulated Output Voltage. Bypass VOUT to GND with a 4.7 µF or greater capacitor. Note that all 13, 14 13, 14 five VOUT pins must be connected to the load. 17 (EPAD) 17 (EPAD) Exposed The exposed pad on the bottom of the LFCSP package enhances thermal performance and is paddle electrically connected to GND inside the package. It is recommended that the exposed pad be (EPAD) connected to the ground plane on the board. Rev. G | Page 6 of 20

Data Sheet ADP1754/ADP1755 TYPICAL PERFORMANCE CHARACTERISTICS V = 1.9 V, V = 1.5 V, I = 10 mA, C = 4.7 µF, C = 4.7 µF, T = 25°C, unless otherwise noted. IN OUT OUT IN OUT A 1.520 1200 LOAD = 10mA LOAD = 1.2A 1.515 LOAD = 100mA LOAD = 400mA 1000 LOAD = 800mA LOAD = 800mA AGE (V) 11..551005 LOAD = 1.2A ENT (µA) 800 LOAD = 400mA T R OL 1.500 UR 600 V C UTPUT 1.495 OUND 400 LOAD = 100mA O R 1.490 G LOAD = 10mA 200 1.485 1.480 0 –40 JU–N5CTION TEM25PERATURE8 (5°C) 125 07722-005 –40 JU–N5CTION TEM25PERATURE8 (5°C) 125 07722-008 Figure 5. Output Voltage vs. Junction Temperature Figure 8. Ground Current vs. Junction Temperature 1.520 1200 1.515 1000 GE (V) 11..550150 NT (µA) 800 A E T R OL 1.500 UR 600 V C UTPUT 1.495 OUND 400 O R 1.490 G 200 1.485 1.480 0 10 10L0OAD CURRENT (mA1)k 10k 07722-006 10 10L0OAD CURRENT (mA1)k 10k 07722-009 Figure 6. Output Voltage vs. Load Current Figure 9. Ground Current vs. Load Current 1.520 1200 LOAD = 10mA 1.515 LOAD = 100mA LOAD = 400mA 1000 LOAD = 1.2A LOAD = 800mA GE (V) 11..551005 LOAD = 1.2A NT (µA) 800 LOAD = 800mA A E OLT 1.500 URR 600 LOAD = 400mA V C UTPUT 1.495 OUND 400 LOAD = 100mA O R 1.490 G 200 LOAD = 10mA 1.485 1.480 0 1.8 2.0 2.2 2.4INPUT2 .V6OLT2A.8GE (V3).0 3.2 3.4 3.6 07722-007 1.8 2.0 2.2 2.4INPUT2 .V6OLT2A.8GE (V3).0 3.2 3.4 3.6 07722-010 Figure 7. Output Voltage vs. Input Voltage Figure 10. Ground Current vs. Input Voltage Rev. G | Page 7 of 20

ADP1754/ADP1755 Data Sheet 100 4500 1.9V LOAD = 10mA 90 2.0V 4000 LOAD = 100mA 2.4V LOAD = 400mA NT (µA) 7800 233...606VVV T (µA) 33500000 LLOOAADD == 810.20AmA E 60 N RR RE 2500 CU 50 UR UTDOWN 4300 ROUND C 21050000 H G S 20 1000 10 500 0 0 –40 –15 TE1M0PERATURE3 5(°C) 60 85 07722-011 2.3 2.4 INP2U.5T VOLTAG2E.6 (V) 2.7 2.8 07722-014 Figure 11. Shutdown Current vs. Temperature at Various Input Voltages Figure 14. Ground Current vs. Input Voltage (in Dropout), VOUT = 2.5 V 0.14 T ILOAD 0.12 V) 0.10 E ( 1 G A 1mA TO 1.2A LOAD STEP, 2.5A/µs, 500mA/DIV T 0.08 L O V UT 0.06 VOUT O 2 P O R 0.04 D 1.6V 50mV/DIV 0.02 2.5V VIN = 3.6V VOUT = 1.5V 01 10 LOAD CU1R0R0ENT (mA) 1k 10k 07722-012 CH1 500mA ΩBW CH2 50mV BW MT 1 010µ.s40%A CH1 380mA 07722-015 Figure 12. Dropout Voltage vs. Load Current, VOUT = 1.6 V, 2.5 V Figure 15. Load Transient Response, CIN = 4.7 μF, COUT = 4.7 μF 2.60 T 2.55 ILOAD 1mA TO 1.2A LOAD STEP, 2.5A/µs, 500mA/DIV 2.50 V) GE ( 2.45 1 A T L O 2.40 V PUT 2.35 2 VOUT T U O 2.30 LOAD = 10mA LOAD = 100mA 20mV/DIV LOAD = 400mA 2.25 LOAD = 800mA VIN = 3.6V LOAD = 1.2A VOUT = 1.5V 2.202.3 2.4 INP2U.5T VOLTAG2E.6 (V) 2.7 2.8 07722-013 CH1 500mA ΩBWCH2 20mV BWMT 1 01µ0.s20%A CH1 340mA 07722-016 Figure 13. Output Voltage vs. Input Voltage (in Dropout), VOUT = 2.5 V Figure 16. Load Transient Response, CIN = 22 μF, COUT = 22 μF Rev. G | Page 8 of 20

Data Sheet ADP1754/ADP1755 0 T VIN 1.2A –10 800mA 400mA –20 100mA 10mA 3V TO 3.5V INPUT VOLTAGE STEP, 2V/µs –30 B) –40 d R ( –50 VOUT SR 2 P –60 5mV/DIV –70 –80 VOUT = 1.5V –90 CIN = COUT = 4.7µF 1 CH1 500mVBW CH2 5mV BW MT 1 09µ.6s0% A CH4 800mV 07722-017 –10010 100 1kFREQU1E0NkCY (Hz1)00k 1M 10M 07722-020 Figure 17. Line Transient Response, Load Current = 1200 mA Figure 20. Power Supply Rejection Ratio vs. Frequency, VOUT = 0.75 V, VIN = 1.75 V 70 0 1.2A 2.5V –10 800mA 60 400mA –20 100mA 50 –30 10mA s) E (µV rm 40 1.5V RR (dB) ––5400 OIS 30 PS –60 N 20 0.75V –70 –80 10 –90 0 –100 0.0001 0.001 LO0.A0D1 CURREN0T.1 (A) 1 10 07722-018 10 100 1kFREQU1E0NkCY (Hz1)00k 1M 10M 07722-121 Figure 18. Noise vs. Load Current and Output Voltage Figure 21. Power Supply Rejection Ratio vs. Frequency, VOUT = 1.5 V, VIN = 2.5 V 10 0 1.2A –10 800mA Hz) 400mA V/ –20 100mA TY (µ 1 –30 10mA NSI B) –40 AL DE 1.5V RR (d –50 R S T 2.5V P –60 C SPE 0.1 –70 E OIS 0.75V –80 N –90 0.01 –100 10 100 FREQUE1NkCY (Hz) 10k 100k 07081-019 10 100 1kFREQU1E0NkCY (Hz1)00k 1M 10M 07722-122 Figure 19. Noise Spectral Density vs. Output Voltage, ILOAD = 10 mA Figure 22. Power Supply Rejection Ratio vs. Frequency, VOUT = 2.5 V, VIN = 3.5 V Rev. G | Page 9 of 20

ADP1754/ADP1755 Data Sheet 0 1.5V/1200mA 1.5V/10mA –10 2.5V/1200mA 2.5V/10mA 0.75V/1200mA 0.75V/10mA –20 –30 B) d –40 R ( R S –50 P –60 –70 –80 –90 10 100 1kFREQU1E0NkCY (Hz1)00k 1M 10M 07722-123 Figure 23. Power Supply Rejection Ratio vs. Frequency and Output Voltage Rev. G | Page 10 of 20

Data Sheet ADP1754/ADP1755 THEORY OF OPERATION The ADP1754 is available in seven fixed output voltage options The ADP1754/ADP1755 are low dropout linear regulators that between 0.75 V and 2.5 V. The ADP1754 allows for connection use an advanced, proprietary architecture to provide high power of an external soft start capacitor that controls the output supply rejection ratio (PSRR) and excellent line and load transient voltage ramp during startup. The ADP1755 is the adjustable response with only a small 4.7 µF ceramic output capacitor. Both version with an output voltage that can be set to a value devices operate from a 1.6 V to 3.6 V input rail and provide up between 0.75 V and 3.3 V by an external voltage divider. Both to 1.2 A of output current. Supply current in shutdown mode is devices are controlled by an enable pin (EN). typically 2 µA. SOFT START FUNCTION (ADP1754/ADP1755) REVERSE POLARITY ADP1754 PROTECTION For applications that require a controlled startup, the ADP1754/ ADP1755 provide a programmable soft start function. The VIN VOUT programmable soft start is useful for reducing inrush current UVLO upon startup and for providing voltage sequencing. To implement soft start, connect a small ceramic capacitor from SS to GND. GND SHORT-CIRCUIT Upon startup, a 0.9 µA current source charges this capacitor. AND THERMAL PROTECTION SENSE The ADP1754/ADP1755 start-up output voltage is limited by R1 the voltage at SS, providing a smooth ramp-up to the nominal PG 0.5V output voltage. The soft start time is calculated as follows: REF R2 PG tSS = VREF × (CSS/ISS) (1) DETECT 0.9µA where: SS EN SHUTDOWN 07722-021 tVSSR EiFs itsh teh seo 0ft. 5s tVar rt epfeerreiondc.e voltage. Figure 24. ADP1754 Internal Block Diagram CSS is the soft start capacitance from SS to GND. I is the current sourced from SS (0.9 µA). SS REVERSE POLARITY ADP1755 PROTECTION When the ADP1754/ADP1755 is disabled (using the EN pin), the soft start capacitor is discharged to GND through an internal 100 Ω VIN VOUT resistor. UVLO 2.50 2.25 GND SHORT-CIRCUIT EN AND THERMAL 2.00 PROTECTION 1.75 PG 0R.E5VF ADJ GE (V) 1.50 1nF A 1.25 PG LT 4.7nF DETECT O 1.00 0.9µA V 10nF SS 0.75 EN SHUTDOWN 07722-022 0.50 Figure 25. ADP1755 Internal Block Diagram 0.25 0 eInrrteorrn aamllyp,l itfhieer A, aD fPee1d7b5a4c/kA DvoPlt1a7g5e5 d civoindseisr,t aonf da are PfeMreOnSce p, aasns 0 2 4TIME (ms)6 8 10 07722-023 transistor. Output current is delivered via the PMOS pass Figure 26. VOUT Ramp-Up with External Soft Start Capacitor transistor, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to pass and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to pass and decreasing the output voltage. Rev. G | Page 11 of 20

ADP1754/ADP1755 Data Sheet As shown in Figure 28, the EN pin has hysteresis built in. This T EN hysteresis prevents on/off oscillations that can occur due to noise on the EN pin as it passes through the threshold points. 1 The EN pin active/inactive thresholds are derived from the VIN voltage. Therefore, these thresholds vary with changing input voltage. Figure 29 shows typical EN active/inactive thresholds when the input voltage varies from 1.6 V to 3.6 V. VOUT 1.1 1.0 2 500mV/DIV VCOINU =T =C O1U.5TV = 4.7µF CH1 2.0V BW CH2 500mV BW MT 4 09µ.8s% A CH1 920mV 07722-024 HOLD (V) 0.9 EN ACTIVE Figure 27. VOUT Ramp-Up with Internal Soft Start ES 0.8 R H EN INACTIVE ADJUSTABLE OUTPUT VOLTAGE (ADP1755) T EN 0.7 The output voltage of the ADP1755 can be set over a 0.75 V to 3.3 V range. The output voltage is set by connecting a resistive 0.6 voltage divider from VOUT to ADJ. The output voltage is calcu- lated using the following equation: 0.5 VOUT = 0.5 V × (1 + R1/R2) (2) 1.6 1.8 2.0 2.2INP2U.4T VO2.L6TAG2E.8 (V)3.0 3.2 3.4 3.6 07722-026 Figure 29. Typical EN Pin Thresholds vs. Input Voltage where: R1 is the resistor from VOUT to ADJ. POWER-GOOD FEATURE R2 is the resistor from ADJ to GND. The ADP1754/ADP1755 provide a power-good pin, PG, to The maximum bias current into ADJ is 150 nA. Therefore, to indicate the status of the output. This open-drain output achieve less than 0.5% error due to the bias current, use values requires an external pull-up resistor to V If the part is in IN. less than 60 kΩ for R2. shutdown mode, current-limit mode, thermal shutdown, or if it falls below 90% of the nominal output voltage, PG imme- ENABLE FEATURE diately transitions low. During soft start, the rising threshold of The ADP1754/ADP1755 use the EN pin to enable and disable the power-good signal is 93.5% of the nominal output voltage. the VOUT pins under normal operating conditions. As shown The open-drain output is held low when the ADP1754/ADP1755 in Figure 28, when a rising voltage on EN crosses the active have sufficient input voltage to turn on the internal PG transistor. threshold, VOUT turns on. When a falling voltage on EN crosses An optional soft start delay can be detected. The PG transistor the inactive threshold, VOUT turns off. is terminated via a pull-up resistor to V or V . OUT IN T Power-good accuracy is 93.5% of the nominal regulator output EN voltage when this voltage is rising, with a 90% trip point when this voltage is falling. Regulator input voltage brownouts or glitches trigger a power VOUT no-good if VOUT falls below 90%. A normal power-down triggers a power no-good when V OUT drops below 90%. 21 VOUT = 1.5V 500mV/DIV CIN = COUT = 4.7µF CH1 500mV BW CH2 500mV BW MT 2 .209m.6s% A CH1 1.05V 07722-025 Figure 28. Typical EN Pin Operation Rev. G | Page 12 of 20

Data Sheet ADP1754/ADP1755 REVERSE CURRENT PROTECTION FEATURE T VIN 1V/DIV The ADP1754/ADP1755 have additional circuitry to protect against reverse current flow from VOUT to VIN. For a typical LDO with a PMOS pass device, there is an intrinsic body diode 1 VOUT between VIN and VOUT. When VIN is greater than VOUT, this 500mV/DIV diode is reverse-biased. If V is greater than V , the intrinsic OUT IN diode becomes forward-biased and conducts current from VOUT to VIN, potentially causing destructive power dissipation. The PG 1V/DIV reverse current protection circuitry detects when V is greater OUT than V and reverses the direction of the intrinsic diode connec- IN 22 VOUT = 1.5V tion, reverse-biasing the diode. The gate of the PMOS pass CIN = COUT = 4.7µF device is also connected to VOUT, keeping the device off. CCHH13 11..00VV BBWW CH2 500mV BW MT 4 05.00.µ40s%A CH3 900mV 07722-027 Figure 32 shows a plot of the reverse current vs. the VOUT to VIN Figure 30. Typical PG Behavior vs. VOUT, VIN Rising (VOUT = 1.5 V) differential. 4000 T 3500 VIN 1V/DIV A) 3000 µ NT ( 2500 E R 1 R VOUT CU 2000 500mV/DIV E S R 1500 E V E R 1000 PG 500 1V/DIV 22 VOUT = 1.5V 0 CCHHC13IN 11 =..00 CVVOUBBTWW = 4.7CµHF2 500mV BW MT 4 05.00.µ40s%A CH3 900mV 07722-028 0 0.3 0.6Fig0u.9re 312.2. ReV1v.O5eUrTs 1–e. 8VCIuNr 2(r.Ve1)nt2 v.4s. V2O.U7T −3 V.0IN 3.3 3.6 07722-132 Figure 31. Typical PG Behavior vs. VOUT, VIN Falling (VOUT = 1.5 V) Rev. G | Page 13 of 20

ADP1754/ADP1755 Data Sheet APPLICATIONS INFORMATION Input Bypass Capacitor CAPACITOR SELECTION Output Capacitor Connecting a 4.7 μF capacitor from the VIN pin to GND reduces the circuit sensitivity to printed circuit board (PCB) The ADP1754/ADP1755 are designed for operation with small, layout, especially when long input traces or high source space-saving ceramic capacitors, but they can function with most impedance are encountered. If output capacitance greater than commonly used capacitors as long as care is taken with the 4.7 μF is required, it is recommended that the input capacitor be effective series resistance (ESR) value. The ESR of the output increased to match it. capacitor affects the stability of the LDO control loop. A mini- Input and Output Capacitor Properties mum of 3.3 μF capacitance with an ESR of 500 mΩ or less is recommended to ensure the stability of the ADP1754/ADP1755. Any good quality ceramic capacitors can be used with the Transient response to changes in load current is also affected by ADP1754, as long as they meet the minimum capacitance and output capacitance. Using a larger value of output capacitance maximum ESR requirements. Ceramic capacitors are manufac- improves the transient response of the ADP1754/ADP1755 to tured with a variety of dielectrics, each with different behavior large changes in load current. Figure 33 and Figure 34 show the over temperature and applied voltage. Capacitors must have a transient responses for output capacitance values of 4.7 μF and dielectric adequate to ensure the minimum capacitance over the 22 μF, respectively. necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recom- T mended. Y5V and Z5U dielectrics are not recommended, due ILOAD to their poor temperature and dc bias characteristics. Figure 35 shows the capacitance vs. voltage bias characteristics 1mA TO 1.2A LOAD STEP, 2.5A/µs, 500mA/DIV 1 of an 0805 case, 4.7 μF, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or with 2 VOUT a higher voltage rating exhibits better stability. The temperature 50mV/DIV variation of the X5R dielectric is about ±15% over the −40°C to +85°C temperature range and is not a function of package size or voltage rating. VIN = 3.6V, VOUT = 1.5V CIN = COUT = 4.7µF 5 CH1 500mABW CH2 50mV BW MT 1 µ11s.2% A CH1 380mA 07722-133 MURATA P/N GRM219R61A475KE34 Figure 33. Output Transient Response, COUT = 4.7 μF 4 T F) µ ILOAD E ( 3 C N A T CI 1mA TO 1.2A LOAD STEP, 2.5A/µs, 500mA/DIV A 2 1 AP C 1 2 VOUT 20mV/DIV 0 0 2 VO4LTAGE BIAS6 (V) 8 10 07722-031 VIN = 3.6V, VOUT = 1.5V Figure 35. Capacitance vs. Voltage Bias Characteristics CIN = COUT = 22µF CH1 500mABW CH2 20mV BW MT 1 µ11s.0% A CH1 340mA 07722-134 Eacqcuoautniotnin 3g cfoarn cbaep uacsietdo rt ov adreiatetiromni noev etrh ete wmopresrt-actuasree , ccaopmacpiotannecnet, Figure 34. Output Transient Response, COUT = 22 μF tolerance, and voltage. C = C × (1 − TEMPCO) × (1 − TOL) (3) EFF OUT where: C is the effective capacitance at the operating voltage. EFF TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. Rev. G | Page 14 of 20

Data Sheet ADP1754/ADP1755 In this example, the worst-case temperature coefficient THERMAL CONSIDERATIONS (TEMPCO) over −40°C to +85°C is assumed to be 15% for an To guarantee reliable operation, the junction temperature of the X5R dielectric. The tolerance of the capacitor (TOL) is assumed ADP1754/ADP1755 must not exceed 125°C. To ensure that the to be 10%, and C = 4.46 μF at 1.8 V, as shown in Figure 35. OUT junction temperature stays below this maximum value, the user Substituting these values in Equation 3 yields needs to be aware of the parameters that contribute to junction temperature changes. These parameters include ambient temp- C = 4.46 μF × (1 − 0.15) × (1 − 0.1) = 3.41 μF EFF erature, power dissipation in the power device, and thermal Therefore, the capacitor chosen in this example meets the resistance between the junction and ambient air (θ ). The θ JA JA minimum capacitance requirement of the LDO over temper- value is dependent on the package assembly compounds used ature and tolerance at the chosen output voltage. and the amount of copper to which the GND pin and the exposed To guarantee the performance of the ADP1754/ADP1755, it is pad (EPAD) of the package are soldered on the PCB. Table 6 shows imperative that the effects of dc bias, temperature, and toler- typical θ values for the 16-lead LFCSP for various PCB copper JA ances on the behavior of the capacitors be evaluated for each sizes. Table 7 shows typical Ψ values for the 16-lead LFCSP. JB application. Table 6. Typical θ Values JA UNDERVOLTAGE LOCKOUT Copper Size (mm2) θ (°C/W), LFCSP JA The ADP1754/ADP1755 have an internal undervoltage lockout 01 130 circuit that disables all inputs and the output when the input 100 80 voltage is less than approximately 1.58 V. This ensures that the 500 69 ADP1754/ADP1755 inputs and the output behave in a predicta- 1000 54 ble manner during power-up. 6400 42 CURRENT-LIMIT AND THERMAL OVERLOAD 1 Device soldered to minimum size pin traces. PROTECTION Table 7. Typical Ψ Values JB The ADP1754/ADP1755 are protected against damage due to Copper Size (mm2) Ψ (°C/W) at 1 W JB excessive power dissipation by current-limit and thermal 100 32.7 overload protection circuits. The ADP1754/ADP1755 are 500 31.5 designed to reach current limit when the output load reaches 1000 25.5 2 A (typical). When the output load exceeds 2 A, the output voltage is reduced to maintain a constant current limit. The junction temperature of the ADP1754/ADP1755 can be Thermal overload protection is included, which limits the calculated from the following equation: junction temperature to a maximum of 150°C (typical). Under T = T + (P × θ ) (4) J A D JA extreme conditions (that is, high ambient temperature and where: power dissipation) when the junction temperature begins to T is the ambient temperature. rise above 150°C, the output is turned off, reducing the output A P is the power dissipation in the die, given by current to zero. When the junction temperature drops below D 135°C (typical), the output is turned on again and the output P = [(V − V ) × I ] + (V × I ) (5) D IN OUT LOAD IN GND current is restored to its nominal value. where: Consider the case where a hard short from VOUT to ground V and V are the input and output voltages, respectively. IN OUT occurs. At first, the ADP1754/ADP1755 reach current limit so I is the load current. LOAD that only 2 A is conducted into the short. If self-heating of the I is the ground current. GND junction becomes great enough to cause its temperature to Power dissipation due to ground current is quite small and can rise above 150°C, thermal shutdown activates, turning off the be ignored. Therefore, the junction temperature equation can output and reducing the output current to zero. As the junction be simplified as follows: temperature cools and drops below 135°C, the output turns on T = T + {[(V − V ) × I ] × θ } (6) and conducts 2 A into the short, again causing the junction J A IN OUT LOAD JA temperature to rise above 150°C. This thermal oscillation between As shown in Equation 6, for a given ambient temperature, input- 135°C and 150°C causes a current oscillation between 2A and to-output voltage differential, and continuous load current, a 0 A that continues as long as the short remains at the output. minimum copper size requirement exists for the PCB to ensure that the junction temperature does not rise above 125°C. Current-limit and thermal overload protections are intended to protect the device against accidental overload conditions. For Figure 36 through Figure 41 show junction temperature reliable operation, device power dissipation should be externally calculations for different ambient temperatures, load currents, limited so that junction temperatures do not exceed 125°C. V to V differentials, and areas of PCB copper. IN OUT Rev. G | Page 15 of 20

ADP1754/ADP1755 Data Sheet 140 140 MAX JUNCTION MAX JUNCTION TEMPERATURE TEMPERATURE 120 120 E, T (°C)J100 LOAD = 1.2A LOAD = 800mA E, T (°C)J100 LOAD = 1.2A LOAD = 800mA UR UR LOAD = 400mA ERAT 80 LOAD = 400mA ERAT 80 LOAD = 200mA P P M M E 60 E 60 T LOAD = 200mA T ON ON LOAD = 10mA TI 40 LOAD = 100mA TI 40 LOAD = 100mA C C N N U U J 20 LOAD = 10mA J 20 00.25 0.75 1.V2I5N – VOUT (1V.7)5 2.25 2.75 07722-032 00.25 0.75 1.V2I5N – VOUT (1V.7)5 2.25 2.75 07722-035 Figure 36. 6400 mm2 of PCB Copper, TA = 25°C, LFCSP Figure 39. 6400 mm2 of PCB Copper, TA = 50°C, LFCSP 140 140 MAX JUNCTION LOAD = 1.2A MAX JUNCTION TEMPERATURE TEMPERATURE 120 120 E, T (°C)J100 LOAD = 1.2A LOAD = 400mA E, T (°C)J100 LOAD = 800mA LOAD = 400mA R LOAD = 800mA R U U AT 80 AT 80 R R LOAD = 200mA E E P LOAD = 200mA P EM 60 EM 60 LOAD = 100mA T T ON LOAD = 100mA ON LOAD = 10mA TI 40 TI 40 NC LOAD = 10mA NC U U J 20 J 20 00.25 0.75 1.V2I5N – VOUT (1V.7)5 2.25 2.75 07722-033 00.25 0.75 1.V2I5N – VOUT (1V.7)5 2.25 2.75 07722-036 Figure 37. 500 mm2 of PCB Copper, TA = 25°C, LFCSP Figure 40. 500 mm2 of PCB Copper, TA = 50°C, LFCSP 140 140 MTEAMXP JEURNACTTUIORNE LOAD = 1.2A MTEAMXP JEURNACTTUIORNE 120 120 RE, T (°C)J100 LOAD =LOAD = 1.2A RE, T (°C)J100 L80O0AmDA = LOAD = 400mALOAD = 200mA U 800mA LOAD = 400mA U AT 80 AT 80 R R PE LOAD = 200mA PE LOAD = 100mA M M E 60 E 60 T T ON LOAD = 100mA ON LOAD = 10mA TI 40 TI 40 C C N N U U J 20 LOAD = 10mA J 20 00.25 0.75 1.V2I5N – VOUT (1V.7)5 2.25 2.75 07722-034 00.25 0.75 1.V2I5N – VOUT (1V.7)5 2.25 2.75 07722-037 Figure 38. 0 mm2 of PCB Copper, TA = 25°C, LFCSP Figure 41. 0 mm2 of PCB Copper, TA = 50°C, LFCSP In cases where the board temperature is known, the thermal characterization parameter, Ψ , can be used to estimate the JB junction temperature rise. Maximum junction temperature (T) J is calculated from the board temperature (T ) and power B dissipation (P ) using the following formula: D T = T + (P × Ψ ) (7) J B D JB Rev. G | Page 16 of 20

Data Sheet ADP1754/ADP1755 Figure 42 through Figure 45 show junction temperature calcula- 140 MAX JUNCTION TEMPERATURE tions for different board temperatures, load currents, V to IN 120 V differentials, and areas of PCB copper. C) OUT 140 MTEAMXP JEURNACTTUIORNE RE, T (°J100 LOAD = 1.2A U LOAD = 800mA C)120 RAT 80 RATURE, T (°J10800 LOAD = 1.2LAOAD = 800mA CTION TEMPE 6400 LOADL =O 4A0D0 m= A200mA E N EMP 60 LOAD = 400mA JU 20 LOAD = 10mA ON T LOAD = 200mA LOAD = 100mA JUNCTI 4200 LOAD = 10mA 00.25 0.75 1.V2I5N – VOUT (1V.7)5 2.25 2.75 07722-040 LOAD = 100mA Figure 44. 1000 mm2 of PCB Copper, TB = 25°C, LFCSP 00.25 0.75 1.V2I5N – VOUT (1V.7)5 2.25 2.75 07722-038 114200 MTEAMXP JEURNACTTUIORNE 140 Figure 42. 500M mAmX J2 UoNf CPTCIBO NCopper, TB = 25°C, LFCSP E, T (°C)J100 LOAD = 1.2A LOAD = 800mA TEMPERATURE R U C)120 LOAD = 1.2A LOAD = 800mA RAT 80 LOAD = 400mA ERATURE, T (°J10800 LLOOAADD == 240000mmAA NCTION TEMPE 6400 LOAD = 100mA LLOOAADD = = 2 1000mmAA P U EM 60 J 20 T ON LOAD = 10mA JUNCTI 4200 LOAD = 100mA 00.25 0.75 1.V2I5N – VOUT (1V.7)5 2.25 2.75 07722-041 Figure 45. 1000 mm2 of PCB Copper, TB = 50°C, LFCSP 00.25 0.75 1.V2I5N – VOUT (1V.7)5 2.25 2.75 07722-039 Figure 43. 500 mm2 of PCB Copper, TB = 50°C, LFCSP Rev. G | Page 17 of 20

ADP1754/ADP1755 Data Sheet PCB LAYOUT CONSIDERATIONS Heat dissipation from the package can be improved by increas- ing the amount of copper attached to the pins of the ADP1754/ ADP1755. However, as shown in Table 6, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. Here are a few general tips when designing PCBs: • Place the input capacitor as close as possible to the VIN and GND pins. • Place the output capacitor as close as possible to the VOUT and GND pins. • Place the soft start capacitor as close as possible to the SS pin. • Connect the load as close as possible to the VOUT and SENSE pins (ADP1754) or to the VOUT and ADJ pins (ADP1755). Use of 0603 or 0805 size capacitors and resistors achieves the 07722-045 smallest possible footprint solution on boards where area is Figure 47. Typical Board Layout—Top Side limited. 07722-046 07722-044 Figure 48. Typical Board Layout—Bottom Side Figure 46. Evaluation Board Rev. G | Page 18 of 20

Data Sheet ADP1754/ADP1755 OUTLINE DIMENSIONS 4.10 0.35 4.00 SQ 0.30 PIN 1 3.90 0.25 INDICATOR PIN 1 0.65 13 16 INDICATOR BSC 12 1 EXPOSED 2.25 PAD 2.10 SQ 1.95 9 4 0.70 8 5 0.25 MIN TOP VIEW 0.60 BOTTOM VIEW 0.50 0.80 FOR PROPER CONNECTION OF 0.75 THE EXPOSED PAD, REFER TO 0.05 MAX THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF COMPLIANTTOJEDEC STANDARDS MO-220-WGGC. 111908-A Figure 49. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-16-23) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Output Voltage (V) Package Description Package Option ADP1754ACPZ-0.75R7 −40°C to +125°C 0.75 16-Lead LFCSP_WQ CP-16-23 ADP1754ACPZ-1.0-R7 −40°C to +125°C 1.0 16-Lead LFCSP_WQ CP-16-23 ADP1754ACPZ-1.1-R7 −40°C to +125°C 1.1 16-Lead LFCSP_WQ CP-16-23 ADP1754ACPZ-1.2-R7 −40°C to +125°C 1.2 16-Lead LFCSP_WQ CP-16-23 ADP1754ACPZ-1.3-R7 −40°C to +125°C 1.3 16-Lead LFCSP_WQ CP-16-23 ADP1754ACPZ-1.5-R7 −40°C to +125°C 1.5 16-Lead LFCSP_WQ CP-16-23 ADP1754ACPZ-1.8-R7 −40°C to +125°C 1.8 16-Lead LFCSP_WQ CP-16-23 ADP1754ACPZ-2.5-R7 −40°C to +125°C 2.5 16-Lead LFCSP_WQ CP-16-23 ADP1755ACPZ-R7 −40°C to +125°C Adjustable from 0.75 to 3.3 16-Lead LFCSP_WQ CP-16-23 ADP1754-1.5-EVALZ 1.5 Evaluation Board ADP1755-EVALZ Adjustable Evaluation Board 1 Z = RoHS Compliant Part. Rev. G | Page 19 of 20

ADP1754/ADP1755 Data Sheet NOTES ©2008–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07722-0-4/14(G) Rev. G | Page 20 of 20

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADP1754ACPZ-1.5-R7 ADP1754ACPZ-0.75R7 ADP1755ACPZ-R7 ADP1754ACPZ-1.0-R7 ADP1754ACPZ-1.1-R7 ADP1754ACPZ-1.2-R7 ADP1754-1.5-EVALZ ADP1755-EVALZ ADP1754ACPZ-2.5-R7 ADP1754ACPZ-1.8-R7