Wide Supply Range, Rail-to-Rail Output Instrumentation Amplifier Data Sheet AD8226 FEATURES PIN CONFIGURATION Gain set with 1 external resistor AD8226 Gain range: 1 to 1000 –IN 1 8 +VS Input voltage goes below ground RG 2 7 VOUT Inputs protected beyond supplies RG 3 6 REF Very wide power supply range +IN 4 5 –VS SDiunagll esu spupplpielys:: 2±.12. 3V5 t Vo 3to6 ±V1 8 V (NToOt Pto V SIEcaWle) 07036-001 Figure 1. Bandwidth (G = 1): 1.5 MHz CMRR (G = 1): 90 dB minimum for BR models Input noise: 22 nV/√Hz Table 1. Instrumentation Amplifiers by Category1 Typical supply current: 350 μA Specified temperature: −40°C to +125°C General Zero Military Low High Speed Purpose Drift Grade Power PGA 8-lead SOIC and MSOP packages AD8220 AD8231 AD620 AD627 AD8250 APPLICATIONS AD8221 AD8290 AD621 AD623 AD8251 Industrial process controls AD8222 AD8293 AD524 AD8223 AD8253 Bridge amplifiers AD8224 AD8553 AD526 AD8226 Medical instrumentation AD8228 AD8556 AD624 AD8227 Portable data acquisition AD8295 AD8557 AD8235/ Multichannel systems AD8236 1 Visit www.analog.com for the latest instrumentation amplifiers. GENERAL DESCRIPTION The AD8226 is a low cost, wide supply range instrumentation AD8226 can handle voltages beyond the rails. For example, amplifier that requires only one external resistor to set any gain with a ±5 V supply, the part is guaranteed to withstand ±35 V between 1 and 1000. at the input with no damage. Minimum as well as maximum input bias currents are specified to facilitate open wire detection. The AD8226 is designed to work with a variety of signal voltages. A wide input range and rail-to-rail output allow the The AD8226 is perfect for multichannel, space-constrained signal to make full use of the supply rails. Because the input industrial applications. Unlike other low cost, low power range also includes the ability to go below the negative supply, instrumentation amplifiers, the AD8226 is designed with small signals near ground can be amplified without requiring dual a minimum gain of 1 and can easily handle ±10 V signals. supplies. The AD8226 operates on supplies ranging from ±1.35 V With its MSOP package and 125°C temperature rating, the to ±18 V for dual supplies and 2.2 V to 36 V for single supply. AD8226 thrives in tightly packed, zero airflow designs. The robust AD8226 inputs are designed to connect to real- The AD8226 is available in 8-lead MSOP and SOIC packages, world sensors. In addition to its wide operating range, the and is fully specified for −40°C to +125°C operation. For a device with a similar package and performance as the AD8226 but with gain settable from 5 to 1000, consider using the AD8227. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2009–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD8226 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Gain Selection ............................................................................. 19 Applications ....................................................................................... 1 Reference Terminal .................................................................... 20 Pin Configuration ............................................................................. 1 Input Voltage Range ................................................................... 20 General Description ......................................................................... 1 Layout .......................................................................................... 20 Revision History ............................................................................... 2 Input Bias Current Return Path ............................................... 21 Specifications ..................................................................................... 3 Input Protection ......................................................................... 22 Absolute Maximum Ratings ............................................................ 7 Radio Frequency Interference (RFI) ........................................ 22 Thermal Resistance ...................................................................... 7 Applications Information .............................................................. 23 ESD Caution .................................................................................. 7 Differential Drive ....................................................................... 23 Pin Configuration and Function Descriptions ............................. 8 Precision Strain Gage ................................................................. 24 Typical Performance Characteristics ............................................. 9 Driving an ADC ......................................................................... 24 Theory of Operation ...................................................................... 19 Outline Dimensions ....................................................................... 25 Architecture ................................................................................. 19 Ordering Guide .......................................................................... 25 REVISION HISTORY 9/12—Rev. B to Rev. C 7/09—Rev. 0 to Rev. A Changes to CMRR, Voltage Offset, Input Offset Current, and Added BRZ and BRM Models .......................................... Universal Gain Error Parameters, Table 2....................................................... 3 Changes to Features Section ............................................................ 1 Changes to CMRR, Voltage Offset, and Input Offset Current Changes to Table 1 ............................................................................. 1 Parameters, Table 2 ........................................................................... 5 Changes to General Description Section ....................................... 1 Changes to Gain vs. Temperature Parameter, Output Parameter, 3/11—Rev. A to Rev. B and Operating Range Parameter, Table 2 ........................................... 4 Added AD8235/AD8236 to Table 1 ............................................... 1 Changes to Common-Mode Rejection Ratio (CMRR) Parameter Changes to Endnote 1, Table 2 ........................................................ 4 and to Input Offset, V , Average Temperature Coefficient OSO Change Endnote 2 Placement in Total Noise Equation, Table 3 ...... 5 Parameter, Table 3 ......................................................................... 5 Added G > 1 BRZ, BRMZ Max Parameter .................................... 6 Changes to Gain vs. Temperature Parameter, Table 3 .................. 6 Changes to Endnote 1, Table 3 ........................................................ 6 Changes to Gain Selection Section .............................................. 19 Changes to Figure 18 ...................................................................... 11 Changes to Reference Terminal Section and Input Voltage Changes to Figure 37 ...................................................................... 14 Range Section.............................................................................. 20 Changes to Figure 42 ...................................................................... 15 Changes to Ordering Guide .......................................................... 25 Updated Outline Dimensions ....................................................... 25 1/09—Revision 0: Initial Version Rev. C | Page 2 of 28

Data Sheet AD8226 SPECIFICATIONS +V = +15 V, −V = −15 V, V = 0 V, T = 25°C, G = 1, R = 10 kΩ, specifications referred to input, unless otherwise noted. S S REF A L Table 2. ARZ, ARMZ BRZ, BRMZ Parameter Conditions Min Typ Max Min Typ Max Unit COMMON-MODE REJECTION RATIO (CMRR) V = −10 V to +10 V CM CMRR, DC to 60 Hz G = 1 86 90 dB G = 10 106 106 dB G = 100 120 120 dB G = 1000 120 120 dB CMRR at 5 kHz G = 1 80 80 dB G = 10 90 90 dB G = 100 90 90 dB G = 1000 100 100 dB NOISE Total noise: e = √(e 2 + (e /G)2) N NI NO Voltage Noise 1 kHz Input Voltage Noise, e 22 24 22 24 nV/√Hz NI Output Voltage Noise, e 120 125 120 125 nV/√Hz NO RTI f = 0.1 Hz to 10 Hz G = 1 2 2 µV p-p G = 10 0.5 0.5 µV p-p G = 100 to 1000 0.4 0.4 µV p-p Current Noise f = 1 kHz 100 100 fA/√Hz f = 0.1 Hz to 10 Hz 3 3 pA p-p VOLTAGE OFFSET Total offset voltage: V = V + (V /G) OS OSI OSO Input Offset, V V = ±5 V to ±15 V 100 50 µV OSI S Average Temperature Coefficient T = −40°C to +125°C 0.5 2 0.5 1 µV/°C A Output Offset, V V = ±5 V to ±15 V 600 400 µV OSO S Average Temperature Coefficient T = −40°C to +125°C 2 10 1 5 µV/°C A Offset RTI vs. Supply (PSR) V = ±5 V to ±15 V S G = 1 100 100 dB G = 10 115 115 dB G = 100 120 120 dB G = 1000 120 120 dB INPUT CURRENT Input Bias Current1 T = +25°C 5 20 27 5 20 27 nA A T = +125°C 5 15 25 5 15 25 nA A T = −40°C 5 30 35 5 30 35 nA A Average Temperature Coefficient T = −40°C to +125°C 70 70 pA/°C A Input Offset Current T = +25°C 1 0.5 nA A T = +125°C 1.5 0.5 nA A T = −40°C 2 0.5 nA A Average Temperature Coefficient T = −40°C to +125°C 5 5 pA/°C A REFERENCE INPUT R 100 100 kΩ IN I 7 7 µA IN Voltage Range −V +V −V +V V S S S S Reference Gain to Output 1 1 V/V Reference Gain Error 0.01 0.01 % DYNAMIC RESPONSE Small-Signal −3 dB Bandwidth G = 1 1500 1500 kHz G = 10 160 160 kHz G = 100 20 20 kHz G = 1000 2 2 kHz Rev. C | Page 3 of 28

AD8226 Data Sheet ARZ, ARMZ BRZ, BRMZ Parameter Conditions Min Typ Max Min Typ Max Unit Settling Time 0.01% 10 V step G = 1 25 25 µs G = 10 15 15 µs G = 100 40 40 µs G = 1000 350 350 µs Slew Rate G = 1 0.4 0.4 V/µs G = 5 to 100 0.6 0.6 V/µs GAIN G = 1 + (49.4 kΩ/R ) G Gain Range 1 1000 1 1000 V/V Gain Error V ±10 V OUT G = 1 0.015 0.01 % G = 5 to 1000 0.15 0.1 % Gain Nonlinearity V = −10 V to +10 V OUT G = 1 to 10 R ≥ 2 kΩ 10 10 ppm L G = 100 R ≥ 2 kΩ 75 75 ppm L G = 1000 R ≥ 2 kΩ 750 750 ppm L Gain vs. Temperature2 G = 1 T = −40°C to +85°C 5 1 ppm/°C A T = 85°C to 125°C 5 2 ppm/°C A G > 1 T = −40°C to +125°C −100 −100 ppm/°C A INPUT V = ±1.35 V to +36 V S Input Impedance Differential 0.8||2 0.8||2 GΩ||pF Common Mode 0.4||2 0.4||2 GΩ||pF Input Operating Voltage Range3 T = +25°C −V − 0.1 +V − 0.8 −V − 0.1 +V − 0.8 V A S S S S T = +125°C −V − 0.05 +V − 0.6 −V − 0.05 +V − 0.6 V A S S S S T = −40°C −V − 0.15 +V − 0.9 −V − 0.15 +V − 0.9 V A S S S S Input Overvoltage Range T = −40°C to +125°C +V − 40 −V + 40 +V − 40 −V + 40 V A S S S S OUTPUT Output Swing R = 2 kΩ to Ground L T = +25°C −V + 0.4 +V − 0.7 −V + 0.4 +V − 0.7 V A S S S S T = +125°C −V + 0.4 +V – 1.0 −V + 0.4 +V – 1.0 V A S S S S T = −40°C −V + 1.2 +V – 1.1 −V + 1.2 +V – 1.1 V A S S S S R = 10 kΩ to Ground L T = +25°C −V + 0.2 +V − 0.2 −V + 0.2 +V − 0.2 V A S S S S T = +125°C −V + 0.3 +V − 0.3 −V + 0.3 +V − 0.3 V A S S S S T = −40°C −V + 0.2 +V − 0.2 −V + 0.2 +V − 0.2 V A S S S S R = 100 kΩ to Ground L T = −40°C to +125°C −V + 0.1 +V − 0.1 −V + 0.1 +V − 0.1 V A S S S S Short-Circuit Current 13 13 mA POWER SUPPLY Operating Range Dual-supply operation ±1.35 ±18 ±1.35 ±18 V Quiescent Current T = +25°C 350 425 350 425 µA A T = −40°C 250 325 250 325 µA A T = +85°C 450 525 450 525 µA A T = +125°C 525 600 525 600 µA A TEMPERATURE RANGE −40 +125 −40 +125 °C 1 The input stage uses pnp transistors; therefore, input bias current always flows out of the part. 2 The values specified for G > 1 do not include the effects of the external gain-setting resistor, R. G 3 Input voltage range of the AD8226 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage. See the Input Voltage Range section for more information. Rev. C | Page 4 of 28

Data Sheet AD8226 +V = 2.7 V, −V = 0 V, V = 0 V, T = 25°C, G = 1, R = 10 kΩ, specifications referred to input, unless otherwise noted. S S REF A L Table 3. ARZ, ARMZ BRZ, BRMZ Parameter Conditions Min Typ Max Min Typ Max Unit COMMON-MODE REJECTION RATIO (CMRR) V = 0 V to 1.7 V CM CMRR, DC to 60 Hz G = 1 86 90 dB G = 10 106 106 dB G = 100 120 120 dB G = 1000 120 120 dB CMRR at 5 kHz G = 1 80 80 dB G = 10 90 90 dB G = 100 90 90 dB G = 1000 100 100 dB NOISE Total noise: e = √(e 2 + (e /G)2) N NI NO Voltage Noise 1 kHz Input Voltage Noise, e 22 24 22 24 nV/√Hz NI Output Voltage Noise, e 120 125 120 125 nV/√Hz NO RTI f = 0.1 Hz to 10 Hz G = 1 2.0 2.0 µV p-p G = 10 0.5 0.5 µV p-p G = 100 to 1000 0.4 0.4 µV p-p Current Noise f = 1 kHz 100 100 fA/√Hz f = 0.1 Hz to 10 Hz 3 3 pA p-p VOLTAGE OFFSET Total offset voltage: V = V + (V /G) OS OSI OSO Input Offset, V 100 50 µV OSI Average Temperature Coefficient T = −40°C to +125°C 0.5 2 0.5 1 µV/°C A Output Offset, V 600 400 µV OSO Average Temperature Coefficient T = −40°C to +125°C 2 10 1 5 µV/°C A Offset RTI vs. Supply (PSR) V = 0 V to 1.7 V S G = 1 100 100 dB G = 10 115 115 dB G = 100 120 120 dB G = 1000 120 120 dB INPUT CURRENT Input Bias Current1 T = +25°C 5 20 27 5 20 27 nA A T = +125°C 5 15 25 5 15 25 nA A T = −40°C 5 30 35 5 30 35 nA A Average Temperature Coefficient T = −40°C to +125°C 70 70 pA/°C A Input Offset Current T = +25°C 1 0.5 nA A T = +125°C 1.5 0.5 nA A T = −40°C 1 0.1 nA A Average Temperature Coefficient T =−40°C to +125°C 5 5 pA/°C A REFERENCE INPUT R 100 100 kΩ IN I 7 7 µA IN Voltage Range −V +V −V +V V S S S S Reference Gain to Output 1 1 V/V Reference Gain Error 0.01 0.01 % DYNAMIC RESPONSE Small-Signal −3 dB Bandwidth G = 1 1500 1500 kHz G = 10 160 160 kHz G = 100 20 20 kHz G = 1000 2 2 kHz Rev. C | Page 5 of 28

AD8226 Data Sheet ARZ, ARMZ BRZ, BRMZ Parameter Conditions Min Typ Max Min Typ Max Unit Settling Time 0.01% 2 V step G = 1 6 6 µs G = 10 6 6 µs G = 100 35 35 µs G = 1000 350 350 µs Slew Rate G = 1 0.4 0.4 V/µs G = 5 to 100 0.6 0.6 V/µs GAIN G = 1 + (49.4 kΩ/R ) G Gain Range 1 1000 1 1000 V/V Gain Error G = 1 V = 0.8 V to 1.8 V 0.04 0.01% % OUT G = 5 to 1000 V = 0.2 V to 2.5 V 0.3 0.1% % OUT Gain vs. Temperature2 G = 1 T = −40°C to +85°C 5 1 ppm/°C A T = +85°C to +125°C 5 2 ppm/°C A G > 1 T = −40°C to +125°C −100 −100 ppm/°C A INPUT −V = 0 V, +V = 2.7 V to 36 V S S Input Impedance Differential 0.8||2 0.8||2 GΩ||pF Common Mode 0.4||2 0.4||2 GΩ||pF Input Operating Voltage Range3 T = +25°C −0.1 +V − 0.7 −0.1 +V − 0.7 V A S S T = −40°C −0.15 +V − 0.9 −0.15 +V − 0.9 V A S S T = +125°C −0.05 +V − 0.6 −0.05 +V − 0.6 V A S S Input Overvoltage Range T = −40°C to +125°C +V − 40 −V + 40 +V − 40 −V + 40 A S S S S OUTPUT Output Swing R = 10 kΩ to 1.35 V, 0.1 +V − 0.1 0.1 +V − 0.1 V L S S T = −40°C to +125°C A Short-Circuit Current 13 13 mA POWER SUPPLY Operating Range Single-supply operation 2.2 36 2.2 36 V Quiescent Current T = +25°C, −V = 0 V, +V = 2.7 V 325 400 325 400 µA A S S T = −40°C, −V = 0 V, +V = 2.7 V 250 325 250 325 µA A S S T = +85°C, −V = 0 V, +V = 2.7 V 425 500 425 500 µA A S S T = +125°C, −V = 0 V, +V = 2.7 V 475 550 475 550 µA A S S TEMPERATURE RANGE −40 +125 −40 +125 °C 1 Input stage uses pnp transistors; therefore, input bias current always flows out of the part. 2 The values specified for G > 1 do not include the effects of the external gain-setting resistor, R. G 3 Input voltage range of the AD8226 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage. See the Input Voltage Range section for more information. Rev. C | Page 6 of 28

Data Sheet AD8226 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. θ is specified for a device in free air. Parameter Rating JA Supply Voltage ±18 V Table 5. Thermal Resistance Output Short-Circuit Current Indefinite Package θ Unit JA Maximum Voltage at −IN or +IN −V + 40 V S 8-Lead MSOP, 4-Layer JEDEC Board 135 °C/W Minimum Voltage at −IN or +IN +V − 40 V S 8-Lead SOIC, 4-Layer JEDEC Board 121 °C/W REF Voltage ±V S Storage Temperature Range −65°C to +150°C ESD CAUTION Specified Temperature Range −40°C to +125°C Maximum Junction Temperature 140°C ESD Human Body Model 1.5 kV Charge Device Model 1.5 kV Machine Model 100 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. C | Page 7 of 28

AD8226 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD8226 –IN 1 8 +VS RG 2 7 VOUT RG 3 6 REF +IN 4 5 –VS (NToOt Pto V SIEcaWle) 07036-002 Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 −IN Negative Input. 2, 3 R Gain-Setting Pins. Place a gain resistor between these two pins. G 4 +IN Positive Input. 5 −V Negative Supply. S 6 REF Reference. This pin must be driven by low impedance. 7 V Output. OUT 8 +V Positive Supply. S Rev. C | Page 8 of 28

Data Sheet AD8226 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, V = ±15 V, R = 10 kΩ, unless otherwise noted. S L N: 2203 MEAN: 0.041 160 MEAN: 35.7649 250 SD: 0.224 SD: 229.378 140 200 120 S100 S150 T T HI HI 80 100 60 40 50 20 0 –900 –600 –3V0O0SO @ 0±15V (µV3)00 600 900 07036-031 0–1.2 –0.9 –0.6 –0.V3OSI D0RIFT (0µ.V3) 0.6 0.9 1.2 07036-034 Figure 3. Typical Distribution of Output Offset Voltage Figure 6. Typical Distribution of Input Offset Voltage Drift, G = 100 240 MEAN: –0.57 180 MEAN: 21.5589 SD: 1.5762 SD: 0.624 210 150 180 120 150 S S HIT120 HIT 90 90 60 60 30 30 0 –9 –6 –3VOSO DR0IFT (µV)3 6 9 07036-032 0 18 POSITIV2E0 IBIAS CURR2E2NT @ ±15V 2(n4A) 26 07036-035 Figure 4. Typical Distribution of Output Offset Voltage Drift Figure 7. Typical Distribution of Input Bias Current 350 MEAN: –3.67283 MEAN: 0.003 SD: 51.1 300 SD: 0.075 300 250 250 200 S200 S T T HI HI150 150 100 100 50 50 0 –400 –V2O0S0I @ RG PIN0S @ ±15V (µ20V0) 400 07036-033 0 –0.9 –0.6 –0.V3OSI @ 0±15V (n0A.)3 0.6 0.9 07036-036 Figure 5. Typical Distribution of Input Offset Voltage Figure 8. Typical Distribution of Input Offset Current Rev. C | Page 9 of 28

AD8226 Data Sheet 2.5 2.5 2.0 +0.02V, +2.0V +1.35V, +1.9V VREF = +1.35V 2.0 +0.02V, +2.0V +1.35V, +1.9V VREF = +1.35V V) V) GE ( 1.5 GE ( A A 1.5 LT +0.02V, +1.3V +2.68V, +1.2V LT DE VO 1.0 VREF = 0V +2.4V, +0.8V DE VO 1.0 +0.02V, +1.3V VREF = 0V +2.67V, +1.3V O O M 0.5 M +2.4V, +0.8V N- +0.02V, +0.3V +2.68V, +0.3V N- MO MO 0.5 +0.02V, +0.4V +2.67V, +0.4V M 0 M O O C C 0 ––10..05 +0.02V, –0.4V +1.35V, –0.4V 07036-037 –0.5 +0.02V, –0.3V +1.35, –0.3V 07036-040 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 9. Input Common-Mode Voltage vs. Output Voltage, Figure 12. Input Common-Mode Voltage vs. Output Voltage, Single Supply, V = +2.7 V, G = 1 Single Supply, V = +2.7 V, G = 100 S S 5 5 +0.02V, +4.3V +2.5V, +4.3V VREF = +1.35V +0.02V, +4.3V +2.5V, +4.2V VREF = +2.5V 4 4 V) V) E ( E ( G G TA 3 +0.02V, +3.0V +4.98V, +3.0V TA 3 +0.02V, +3.0V +4.96V, +3.0V L L O O V V ODE 2 VREF = 0V +4.7V, +1.9V ODE 2 VREF = 0V +4.7V, +1.9V M M N- N- MO 1 +0.02V, +0.8V +4.98V, +0.8V MO 1 +0.02V, +0.7V +4.96V, +0.7V M M O O C C 0 0 –1 +0.02V, –0.4V +2.5V, –0.4V 07036-038 –1 +0.02V, –0.3V +2.5V, –0.3.V 07036-041 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 10. Input Common-Mode Voltage vs. Output Voltage, Figure 13. Input Common-Mode Voltage vs. Output Voltage, Single Supply, V = +5 V, G = 1 Single Supply, V = +5 V, G = 100 S S 6 6 0V, +4.3V 0V, +4.2V 4 4 V) V) E ( E ( G G A 2 A 2 LT –4.97V, +1.8V +4.96V, +1.8V LT –4.96V, +1.7V +4.96V, +1.7V O O V V DE 0 DE 0 O O M M N- N- MO–2 MO–2 M –4.97V, –3.0V +4.96V, –0.3V M –4.96V, –3.1V +4.96V, –3.1V O O C C –4 –4 –6 0V, –5.4V 07036-039 –6 0V, –5.3V 07036-042 –6 –4 –2 0 2 4 6 –6 –4 –2 0 2 4 6 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 11. Input Common-Mode Voltage vs. Output Voltage, Figure 14. Input Common-Mode Voltage vs. Output Voltage, Dual Supplies, V = ±5 V, G = 1 Dual Supplies, V = ±5 V, G = 100 S S Rev. C | Page 10 of 28

Data Sheet AD8226 20 20 15 0V, +14.3V VS = ±15V 15 0V, +14.2V VS = ±15V V) V) GE ( 10 +14.96V, +6.8V 0V, +11.3V +14.94V, +6.8V GE ( 10 –14.95V, +6.7V 0V, +11.2V +14.95V, +6.7V A A OLT 5 –11.95V, +5.3V +11.95V, +5.3V OLT 5 –11.95V, +5.2V +11.95V, +5.2V V V ODE 0 VS = ±12V ODE 0 VS = ±12V M M ON- –5 –11.95V, –6.4V +11.95V, –6.4V ON- –5 –11.95V, –6.5V +11.95V, –6.5V M M M M O –10 –14.96V, –7.9V 0V, –12.4V +14.94V, –7.9V O –10 –14.95V, –8.0V 0V, –12.3V +14.95V, –8.0V C C ––2105 0V, –15.4V 07036-043 ––2105 0V, –15.4V 07036-046 –20 –15 –10 –5 0 5 10 15 20 –20 –15 –10 –5 0 5 10 15 20 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 15. Input Common-Mode Voltage vs. Output Voltage, Figure 18. Input Common-Mode Voltage vs. Output Voltage, Dual Supplies, VS = ±15 V, G = 1 Dual Supplies, VS = ±15 V, G = 100 2.25 0.6 2.75 0.6 2.00 VGS = = 1 2.7V 0.5 2.50 VGS = = 1 20.07V 0.5 1.75 –VIN = 0V 0.4 2.25 –VIN = 0V VOUT 0.4 OUTPUT VOLTAGE (V)1110....52070505 VIIONUT 0000–––...000321...123 INPUT CURRENT (mA) OUTPUT VOLTAGE (V)211110......075207050505 IIN 0000–––...000321...123 INPUT CURRENT (mA) 0.50 –0.4 0.50 –0.4 0.25 –0.5 0.25 –0.5 0–40–35–30–25–20–15IN–1P0U–T5 VO0LTA5GE1 (0V)15 20 25 30 35 40–0.6 07036-044 0–40–35–30–25–20–15IN–1P0U–T5 VO0LTA5GE1 (0V)15 20 25 30 35 40–0.6 07036-047 Figure 16. Input Overvoltage Performance, G = 1, VS = 2.7 V Figure 19. Input Overvoltage Performance, G = 100, VS = 2.7 V 16 0.5 16 0.6 1142 VGS = = 1 ±15V 0.4 1142 VGS = = 1 ±0105V 0.5 10 –VIN = 0V 0.3 10 –VIN = 0V 0.4 8 VOUT 8 VOUT 0.3 OUTPUT VOLTAGE (V) ––––24686420 IIN 000––..0021..12 INPUT CURRENT (mA) OUTPUT VOLTAGE (V) ––––24686420 IIN 000–––..00021...123 INPUT CURRENT (mA) –10 –0.3 –10 –0.4 –12 –12 –14 –0.4 –14 –0.5 –16–40–35–30–25–20–15IN–1P0U–T5 VO0LTA5GE1 (0V)15 20 25 30 35 40–0.5 07036-045 –16–40–35–30–25–20–15IN–1P0U–T5 VO0LTA5GE1 (0V)15 20 25 30 35 40–0.6 07036-048 Figure 17. Input Overvoltage Performance, G = 1, VS = ±15 V Figure 20. Input Overvoltage Performance, G = 100, VS = ±15 V Rev. C | Page 11 of 28

AD8226 Data Sheet 30 160 29 28 140 –0.15V GAIN = 1000 27 A) 120 GAIN = 100 ENT (n 2265 R (dB)100 GGAAIINN == 110 R 24 R R S AS CU 2232 TIVE P 80 PUT BI 2210 +4.22V NEGA 60 N 40 I 19 18 20 17 1–60.5 0 0.5 C1O.0MMO1N.5-MOD2.E0 VO2L.T5AGE3 .(0V) 3.5 4.0 4.5 07036-049 00.1 1 10 FR1E0Q0UENCY1 k(Hz) 10k 100k 1M 07036-014 Figure 21. Input Bias Current vs. Common-Mode Voltage, V = +5 V Figure 24. Negative PSRR vs. Frequency S 50 70 45 –15.13V 60 GAIN = 1000 VS = ±15V 40 50 T (nA) 35 40 GAIN = 100 N 30 CURRE 25 N (dB) 3200 GAIN = 10 S 20 AI NPUT BIA 1150 +14.18V G 100 GAIN = 1 I 5 –10 0 –20 –5–16 –12 –8COMM–O4N-MOD0E VOLT4AGE (V)8 12 16 07036-050 –30100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M 07036-015 Figure 22. Input Bias Current vs. Common-Mode Voltage, V = ±15 V Figure 25. Gain vs. Frequency, V = ±15 V S S 160 70 GAIN = 1000 VS = 2.7V 140 GAIN = 1000 60 GAIN = 100 50 120 GAIN = 10 GAIN = 100 dB) GAIN = 1 40 RR (100 B) 30 VE PS 80 AIN (d 20 GAIN = 10 TI G 10 SI 60 O GAIN = 1 P 0 40 –10 20 –20 00.1 1 10 FR1E0Q0UENCY1 k(Hz) 10k 100k 1M 07036-013 –30100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M 07036-016 Figure 23. Positive PSRR vs. Frequency, RTI Figure 26. Gain vs. Frequency, 2.7 V Single Supply Rev. C | Page 12 of 28

Data Sheet AD8226 160 35 150 GAIN = 1000 –IN BIAS CURRENT VS = ±15V 140 GAIN = 100 30 +OIFNF BSIEATS CCUURRRREENNTT VREF = 0V 125 B)112000 GGAAIINN == 110 BANDLIWMIIDTTEHD RENT (nA)25 100 RRENT (pA) d R U CMRR ( 8600 BIAS CU20 75 FFSET C UT 15 50 T O P U 40 N P I N I 10 25 20 00.1 1 10FREQU1E0N0CY (Hz)1k 10k 100k 07036-017 5–45 –30 –15 0 15TEM3P0ERA45TUR6E0 (°C7)5 90 105 120 1350 07036-012 Figure 27. CMRR vs. Frequency, RTI Figure 30. Input Bias Current and Input Offset Current vs. Temperature 120 20 GAIN = 1000 GAIN = 100 10 BANDWIDTH 100 LIMITED GAIN = 1 0 –0.6 80 GAIN = 10 V)–10 ppm/°C V/ dB) R (µ–20 R ( 60 RO –0.3ppm/°C MR ER–30 C 40 GAIN –40 –0.4ppm/°C –50 20 –60 NORMALIZED AT 25°C 00.1 1 10FREQU1E0N0CY (Hz)1k 10k 100k 07036-018 –70–60 –40 –20 0 TEM20PERA40TURE6 0(°C) 80 100 120 140 07036-051 Figure 28. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance Figure 31. Gain Error vs. Temperature, G = 1 3.0 20 V) 2.5 µ E ( 2.0 10 G TA 1.5 –0.35ppm/°C L VO 1.0 0 PUT OFFSET –00..550 CMRR (µV/V)–10 0.2ppm/°C N IN–1.0 –20 E I–1.5 G AN–2.0 –30 H REPRESENTATIVE DATA C–2.5 NORMALIZED AT 25°C –3.00 10 20 30 W4A0RM-5U0P T6IM0E (S70econ8d0s)90 100 110 120 07036-011 –40–50 –30 –10 10TEMP3E0RATU5R0E (°C7)0 90 110 130 07036-052 Figure 29. Change in Input Offset Voltage vs. Warm-Up Time Figure 32. CMRR vs. Temperature, G = 1 Rev. C | Page 13 of 28

AD8226 Data Sheet +VS 15 –40°C +25°C +85°C +105°C +125°C –0.2 NPUT VOLTAGE (V)ED TO SUPPLY VOLTAGES––––000V...468S UT VOLTAGE SWING (V) 1–0550 –++++4281105502°°°55CCC°°CC IR–0.2 P R T E U F–0.4 O RE –10 –0.6 –0.82 4 6 SUP8PLY VO1L0TAGE1 (2±VS) 14 16 18 07036-053 –15100 L1OkAD RESISTANCE (1Ω0)k 100k 07036-056 Figure 33. Input Voltage Limit vs. Supply Voltage Figure 36. Output Voltage Swing vs. Load Resistance +VS +VS –0.1 –0.2 S S –40°C VOLTAGE SWING (V)TO SUPPLY VOLTAGE+–––0000....2344 –++++4281105502°°°55CCC°°CC VOLTAGE SWING (V)TO SUPPLY VOLTAGE+–––0000....4688 ++++28115502°°55CC°°CC T D T D UE UE PR+0.3 PR+0.6 TR TR UE UE OEF+0.2 OEF+0.4 R R +0.1 +0.2 –VS2 4 6 SUP8PLY VO1L0TAGE1 (2±VS) 14 16 18 07036-054 –VS10µ 1O00UµTPUT CURRENT (1Am) 10m 07036-057 Figure 34. Output Voltage Swing vs. Supply Voltage, R = 10 kΩ Figure 37. Output Voltage Swing vs. Output Current, G = 1 L +VS 8 G = 1 –0.2 6 S–0.4 UTPUT VOLTAGE SWING (V)ERRED TO SUPPLY VOLTAGE+++––––0110101.......8026082 –++++4281105502°°°55CCC°°CC NONLINEARITY (2ppm/DIV)––24420 OF+0.6 E R+0.4 –6 +0.2 –VS2 4 6 SUP8PLY VO1L0TAGE1 (2±VS) 14 16 18 07036-055 –8–10 –8 –6 –4OUT–P2UT VO0LTAG2E (V)4 6 8 10 07036-019 Figure 35. Output Voltage Swing vs. Supply Voltage, R = 2 kΩ Figure 38. Gain Nonlinearity, G = 1, R ≥ 2 kΩ L L Rev. C | Page 14 of 28

Data Sheet AD8226 8 1k G = 10 6 V) 4 DI m/ 2pp 2 Hz) GAIN = 1 RITY ( 0 E (nV/100 A S LINE–2 NOI GAIN = 100 N NO–4 GAIN = 10 GAIN = 1000 –6 BANDWIDTH LIMITED –8–10 –8 –6 –4OUT–P2UT VO0LTAG2E (V)4 6 8 10 07036-020 101 10 F1R0E0QUENCY (1Hkz) 10k 100k 07036-023 Figure 39. Gain Nonlinearity, G = 10, RL ≥ 2 kΩ Figure 42. Voltage Noise Spectral Density vs. Frequency 80 G = 100 60 GAIN = 1000, 200nV/DIV DIV) 40 m/ pp 20 0 2 TY ( 0 GAIN = 1, 1µV/DIV RI A NE–20 LI N NO–40 ––6800–10 –8 –6 –4OUT–P2UT VO0LTAG2E (V)4 6 8 10 07036-021 1s/DIV 07036-024 Figure 40. Gain Nonlinearity, G = 100, RL ≥ 2 kΩ Figure 43. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1, G = 1000 800 1k G = 1000 600 DIV) 400 m/ 00pp 200 Hz) RITY (1 0 SE (fA/100 NEA–200 NOI LI N O–400 N –600 –800–10 –8 –6 –4OUT–P2UT VO0LTAG2E (V)4 6 8 10 07036-022 101 10 FREQUE10N0CY (Hz) 1k 10k 07036-058 Figure 41. Gain Nonlinearity, G = 1000, RL ≥ 2 kΩ Figure 44. Current Noise Spectral Density vs. Frequency Rev. C | Page 15 of 28

AD8226 Data Sheet 5V/DIV 15.46μs TO 0.01% 17.68µs TO 0.001% 0.002%/DIV 1.5pA/DIV 1s/DIV 07036-025 40µs/DIV 07036-061 Figure 45. 0.1 Hz to 10 Hz Current Noise Figure 48. Large-Signal Pulse Response and Settling Time, G = 10, 10 V Step, V = ±15 V S 30 27 VS= ±15V 24 p) p- 21 V 5V/DIV GE ( 18 A 39.64μs TO 0.01% LT 15 58.04µs TO 0.001% O V T 12 U P UT 9 0.002%/DIV O 6 03 VS= +5V 07036-059 100µs/DIV 07036-062 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 46. Large-Signal Frequency Response Figure 49. Large-Signal Pulse Response and Settling Time, G = 100, 10 V Step, V = ±15 V S 5V/DIV 5V/DIV 25.38μs TO 0.01% 349.6μs TO 0.01% 26.02µs TO 0.001% 529.6µs TO 0.001% 0.002%/DIV 0.002%/DIV 40µs/DIV 07036-060 400µs/DIV 07036-063 Figure 47. Large-Signal Pulse Response and Settling Time, Figure 50. Large-Signal Pulse Response and Settling Time, G = 1, 10 V Step, V = ±15 V G = 1000, 10 V Step, V = ±15 V S S Rev. C | Page 16 of 28

Data Sheet AD8226 20mV/DIV 4µs/DIV 07036-026 20mV/DIV 20µs/DIV 07036-028 Figure 51. Small-Signal Response, G = 1, R = 10 kΩ, C = 100 pF Figure 53. Small-Signal Response, G = 100, R = 10 kΩ, C = 100 pF L L L L 20mV/DIV 4µs/DIV 07036-027 20mV/DIV 100µs/DIV 07036-029 Figure 52. Small-Signal Response, G = 10, R = 10 kΩ, C = 100 pF Figure 54. Small-Signal Response, G = 1000, R = 10 kΩ, C = 100 pF L L L L Rev. C | Page 17 of 28

AD8226 Data Sheet 340 330 A) µ T ( N320 NO LOAD E R R RL = 47pF CU RL = 100pF PLY 310 P U RL = 147pF S 300 20mV/DIV 4µs/DIV 07036-030 2900 2 4 SU6PPLY8 VOLTA10GE (±V12S) 14 16 18 07036-066 Figure 55. Small-Signal Response with Various Capacitive Loads, Figure 57. Supply Current vs. Supply Voltage G = 1, R = ∞ L 60 50 µs) 40 E ( M TI G 30 N TLI SETTLEDTO 0.001% T E 20 S SETTLEDTO 0.01% 10 0 07036-064 2 4 6 8 10 12 14 16 18 20 STEP SIZE (V) Figure 56. Settling Time vs. Step Size, V = ±15 V Dual Supplies S Rev. C | Page 18 of 28

Data Sheet AD8226 THEORY OF OPERATION +VS +VS NODE 3 RG NODE 4 R3 50kΩ 24.7kRΩ1 –VS –VS R242.7kΩ R4 +VS 50kΩ NODE 2 A3 VOUT NODE 1 R5 +VS 50kΩ R6 –VS ESDAND ESDAND 50kΩ +IN OVERVOLTAGE Q1 Q2 OVERVOLTAGE –IN REF A1 A2 PROTECTION PROTECTION –VS RB VBIAS RB GAIN STAGE –VS AMDPILFIFFEIERRE NSCTAEGE 07036-003 Figure 58. Simplified Schematic ARCHITECTURE GAIN SELECTION The AD8226 is based on the classic 3-op-amp topology. This Placing a resistor across the R terminals sets the gain of the G topology has two stages: a preamplifier to provide differential AD8226, which can be calculated by referring to Table 7 or by amplification, followed by a difference amplifier to remove the using the following gain equation: common-mode voltage. Figure 58 shows a simplified schematic 49.4kΩ of the AD8226. R  G G1 The first stage works as follows: in order to maintain a constant voltage across the bias resistor RB, A1 must keep Node 3 a con- Table 7. Gains Achieved Using 1% Resistors stant diode drop above the positive input voltage. Similarly, A2 1% Standard Table Value of R (Ω) Calculated Gain G keeps Node 4 at a constant diode drop above the negative input 49.9 k 1.990 voltage. Therefore, a replica of the differential input voltage is 12.4 k 4.984 placed across the gain-setting resistor, RG. The current that 5.49 k 9.998 flows across this resistance must also flow through the R1 2.61 k 19.93 and R2 resistors, creating a gained differential signal between 1.00 k 50.40 the A2 and A1 outputs. Note that, in addition to a gained 499 100.0 differential signal, the original common-mode signal, shifted 249 199.4 a diode drop up, is also still present. 100 495.0 The second stage is a difference amplifier, composed of A3 and 49.9 991.0 four 50 kΩ resistors. The purpose of this stage is to remove the common-mode signal from the amplified differential signal. The AD8226 defaults to G = 1 when no gain resistor is used. The transfer function of the AD8226 is The tolerance and gain drift of the RG resistor should be added to the AD8226 specifications to determine the total gain accu- V = G(V − V ) + V OUT IN+ IN− REF racy of the system. When the gain resistor is not used, gain where: error and gain drift are minimal. 49.4kΩ G1 If a gain of 5 is required and minimal gain drift is important, R G consider using the AD8227. The AD8227 has a default gain of 5 that is set with internal resistors. Because all resistors are internal, the gain drift is extremely low (<5 ppm/°C maximum). Rev. C | Page 19 of 28

AD8226 Data Sheet REFERENCE TERMINAL (V )(G) V − DIFF >−V +V (1) The output voltage of the AD8226 is developed with respect to CM 2 S −LIMIT the potential on the reference terminal. This is useful when the (V )(G) output signal needs to be offset to a precise midsupply level. For VCM + DIF2F <+VS −V+LIMIT (2) example, a voltage source can be tied to the REF pin to level- shift the output so that the AD8226 can drive a single-supply (V )(G) DIFF +V +V ADC. The REF pin is protected with ESD diodes and should 2 CM REF <+V −V (3) not exceed either +V or −V by more than 0.3 V. 2 S REF_LIMIT S S For the best performance, source impedance to the REF Table 8. Input Voltage Range Constants for Various terminal should be kept below 2 Ω. As shown in Figure 58, Temperatures the reference terminal, REF, is at one end of a 50 kΩ resistor. Temperature V V V −LIMIT +LIMIT REF_LIMIT Additional impedance at the REF terminal adds to this 50 kΩ −40°C −0.55 V 0.8 V 1.3 V resistor and results in amplification of the signal connected to +25°C −0.35 V 0.7 V 1.15 V the positive input. The amplification from the additional R REF +85°C −0.15 V 0.65 V 1.05 V can be computed by 2(50 kΩ + R )/(100 kΩ + R ). REF REF +125°C −0.05 V 0.6 V 0.9 V Only the positive signal path is amplified; the negative path is unaffected. This uneven amplification degrades CMRR. Performance Across Temperature INCORRECT CORRECT The common-mode input range shifts upward with temper- ature. At cold temperatures, the part requires extra headroom from the positive supply, and operation near the negative supply AD8226 AD8226 has more margin. Conversely, hot temperatures require less REF REF V headroom from the positive supply, but are the worst-case V conditions for input voltages near the negative supply. + Recommendation for Best Performance OP1177 – 07036-004 Ase ctytipoinc.a Hl poawrte vfuenr,c ftoior nbse sutp p teor ftohrem baonucned, dareiseisg ndiensgcr wibiethd ain f etwhi s Figure 59. Driving the Reference Pin hundred millivolts extra margin is recommended. As signals approach the boundary, internal transistors begin to saturate, INPUT VOLTAGE RANGE which can affect frequency and linearity performance. Figure 9 through Figure 15 and Figure 18 show the allowable If the application requirements exceed the boundaries, one common-mode input voltage ranges for various output voltages solution is to apply less gain with the AD8226, and then apply and supply voltages. The 3-op-amp architecture of the AD8226 additional gain later in the signal chain. Another option is to applies gain in the first stage before removing common-mode use the pin-compatible AD8227. voltage with the difference amplifier stage. Internal nodes between the first and second stages (Node 1 and Node 2 in Figure 58) LAYOUT experience a combination of a gained signal, a common-mode To ensure optimum performance of the AD8226 at the PCB signal, and a diode drop. This combined signal can be limited level, care must be taken in the design of the board layout. by the voltage supplies even when the individual input and The AD8226 pins are arranged in a logical manner to aid in output signals are not limited. this task. For most applications, Figure 9 through Figure 15 and Figure 18 provide sufficient information to achieve a good design. For –IN 1 8 +VS applications where a more detailed understanding is needed, RG 2 7 VOUT Equation 1 to Equation 3 can be used to understand how the RG 3 6 REF vtghoaeiltn ac go(eGn s()Vt,a cDnoItFmsF), ,mV anodn -rem,f eVordene cien p,v aounltt davg oVel t(aVgReE F()V i,nC aMter)er, a dschitf.of Tewrhneen ivntia aTlul aiebnsl pefou 8rt. +IN 4 (NTAoOtD Pto8 V 2SIEc2Wa6le) 5 –VS 07036-005 −LIMIT +LIMIT REF_LIMIT Figure 60. Pinout Diagram These three formulas, along with the input and output range specifications in Table 2 and Table 3, set the operating boundaries of the part. Rev. C | Page 20 of 28

Data Sheet AD8226 Common-Mode Rejection Ratio Over Frequency INPUT BIAS CURRENT RETURN PATH Poor layout can cause some of the common-mode signals to be The input bias current of the AD8226 must have a return path converted to differential signals before reaching the in-amp. to ground. When the source, such as a thermocouple, cannot Such conversions occur when one input path has a frequency provide a return current path, one should be created, as shown response that is different from the other. To keep CMRR across in Figure 62. frequency high, the input source impedance and capacitance of INCORRECT CORRECT each path should be closely matched. Additional source resistance +VS +VS in the input path (for example, for input protection) should be placed close to the in-amp inputs, which minimizes their interaction with parasitic capacitance from the PCB traces. AD8226 AD8226 Parasitic capacitance at the gain-setting pins can also affect REF REF CMRR over frequency. If the board design has a component at the gain-setting pins (for example, a switch or jumper), the part should be chosen so that the parasitic capacitance is as –VS –VS small as possible. TRANSFORMER TRANSFORMER Power Supplies +VS +VS A stable dc voltage should be used to power the instrumentation amplifier. Note that noise on the supply pins can adversely affect performance. For more information, see the PSRR performance AD8226 AD8226 curves in Figure 23 and Figure 24. REF REF A 0.1 μF capacitor should be placed as close as possible to each 10MΩ supply pin. As shown in Figure 61, a 10 μF tantalum capacitor can be used farther away from the part. In most cases, it can be –VS –VS shared by other precision integrated circuits. THERMOCOUPLE THERMOCOUPLE +VS +VS +VS C C 0.1µF 10µF +IN AD8226 fHIGH-PASS =2π1RC R AD8226 C C REF REF VOUT AD8226 R LOAD –IN REF CAPACITIVE–LVYS COUPLED CAPACITIVELY COUP–LVESD 07036-007 Figure 62. Creating an IBIAS Path 0.1µF 10µF –VS 07036-006 Figure 61. Supply Decoupling, REF, and Output Referred to Local Ground References The output voltage of the AD8226 is developed with respect to the potential on the reference terminal. Care should be taken to tie REF to the appropriate local ground. Rev. C | Page 21 of 28

AD8226 Data Sheet INPUT PROTECTION +VS The AD8226 has very robust inputs and typically does not 0.1µF 10µF need additional input protection. Input voltages can be up to CC 40 V from the opposite supply rail. For example, with a +5 V 1nF positive supply and a −8 V negative supply, the part can safely R +IN 4.02kΩ winistthrsutmanedn tvaotlitoang easm frpolimfie −rs3,5 t hVe tpoa 3r2t cVa.n U hnalnikdel es olamrgee o dthifeferr en- C10DnF RG AD8226 VOUT R REF tial input voltages even when the part is in high gain. Figure 16, 4.02kΩ –IN Figure 17, Figure 19, and Figure 20 show the behavior of the CC 1nF part under overvoltage conditions. 0.1µF 10µF Tsuhpep rlieesst. oAfl lt hteer mAiDn8al2s2 o6f ttehrem AiDna8l2s2 s6h aoruel dpr boete kcteepdt awgiatihnisnt EthSeD . –VS 07036-008 Figure 63. RFI Suppression For applications where the AD8226 encounters voltages beyond the allowed limits, external current-limiting resistors and low- C affects the difference signal and C affects the common-mode D C leakage diode clamps such as the BAV199L, the FJH1100s, or signal. Values of R and C should be chosen to minimize RFI. C the SP720 should be used. Mismatch between the R × C at the positive input and the R × C C C RADIO FREQUENCY INTERFERENCE (RFI) at the negative input degrades the CMRR of the AD8226. By using a value of C that is one magnitude larger than C , the effect of D C RF rectification is often a problem when amplifiers are used in the mismatch is reduced and performance is improved. applications having strong RF signals. The disturbance can appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass RC network placed at the input of the instru- mentation amplifier, as shown in Figure 63. The filter limits the input signal bandwidth according to the following relationship: 1 FilterFrequency  DIFF 2πR(2C C ) D C 1 FilterFrequency  CM 2πRC C where C  10 C . D C Rev. C | Page 22 of 28

Data Sheet AD8226 APPLICATIONS INFORMATION DIFFERENTIAL DRIVE Tips for Best Differential Output Performance For best ac performance, an op amp with at least a 2 MHz gain +IN bandwidth and a 1 V/µs slew rate is recommended. Good choices AD8226 +OUT for op amps are the AD8641, AD8515, and AD820. –IN Keep trace lengths from the resistors to the inverting terminal REF R VBIAS of the op amp as short as possible. Excessive capacitance at this node can cause the circuit to be unstable. If capacitance cannot – + R OP AMP be avoided, use lower value resistors. For best linearity and ac performance, a minimum positive supply voltage (+V) is required. Table 9 shows the minimum S –OUT RREECCOOMMMMEENNDDEEDD ORPVAALMUPESS::A 5Dk8Ω5 1to5 ,2A0DkΩ86.41,AD820. 07036-009 sVuCpMp_MlyA Xv oinltdaigcea treesq uthiree md afoxri moputmim cuomm mpeornfo-rmmoadnec ev.o Ilnta tghei se xmpoecdtee,d Figure 64. Differential Output Using an Op Amp at the input of the AD8226. Figure 64 shows how to configure the AD8226 for differ- Table 9. Minimum Positive Supply Voltage ential output. Temperature Equation The differential output is set by the following equation: Less than −10°C +V > (V + V )/2 + 1.4 V S CM_MAX BIAS −10°C to 25°C +V > (V + V )/2 + 1.25 V V = V − V = Gain × (V − V ) S CM_MAX BIAS DIFF_OUT OUT+ OUT− IN+ IN− More than 25°C +V > (V + V )/2 + 1.1 V S CM_MAX BIAS The common-mode output is set by the following equation: V = (V − V )/2= V CM_OUT OUT+ OUT− BIAS The advantage of this circuit is that the dc differential accuracy depends on the AD8226, not on the op amp or the resistors. In addition, this circuit takes advantage of the precise control that the AD8226 has of its output voltage relative to the reference voltage. Although the dc performance and resistor matching of the op amp affect the dc common-mode output accuracy, such errors are likely to be rejected by the next device in the signal chain and therefore typically have little effect on overall system accuracy. Rev. C | Page 23 of 28

AD8226 Data Sheet PRECISION STRAIN GAGE Option 1 shows the minimum configuration required to drive a charge-sampling ADC. The capacitor provides charge to the The low offset and high CMRR over frequency of the AD8226 ADC sampling capacitor while the resistor shields the AD8226 make it an excellent candidate for performing bridge measure- from the capacitance. To keep the AD8226 stable, the RC time ments. The bridge can be connected directly to the inputs of the constant of the resistor and capacitor needs to stay above 5 µs. amplifier (see Figure 65). This circuit is mainly useful for lower frequency signals. 5V Option 2 shows a circuit for driving higher speed signals. It uses a 10µF 0.1µF precision op amp (AD8616) with relatively high bandwidth and 350Ω 350Ω output drive. This amplifier can drive a resistor and capacitor with +IN + a much higher time constant and is therefore suited for higher 350Ω 350Ω RG AD8226 frequency applications. –IN – 2.5V 07036-010 Orupnt ioofnf a3 liasr ugese vfoullt faogre aspupplpiclya tbiount sd wrihvee rae stihneg Ale-Dsu82p2p6ly n AeeDdCs .t o In normal operation, the AD8226 output stays within the ADC Figure 65. Precision Strain Gage range, and the AD8616 simply buffers it. However, in a fault DRIVING AN ADC condition, the output of the AD8226 may go outside the supply Figure 66 shows several methods for driving an ADC. The range of both the AD8616 and the ADC. This is not an issue in ADuC7026 microcontroller was chosen for this example because it the circuit, however, because the 10 kΩ resistor between the two contains ADCs with an unbuffered, charge-sampling architecture amplifiers limits the current into the AD8616 to a safe level. that is typical of most modern ADCs. This type of architecture typically requires an RC buffer stage between the ADC and amplifier to work correctly. OPTION 1: DRIVING LOW FREQUENCY SIGNALS 3.3V 3.3V 100Ω AVDD AD8226 ADC0 REF 100nF ADuC7026 OPTION 2: DRIVING HIGH FREQUENCY SIGNALS 3.3V 3.3V AD8226 REF 10Ω AD8616 ADC1 10nF OPTION 3: PROTECTINGADC FROM LARGE VOLTAGES +15V 3.3V 10kΩ AD8226 REF 10Ω AD8616 ADC2 10nF AGND –15V 07036-065 Figure 66. Driving an ADC Rev. C | Page 24 of 28

Data Sheet AD8226 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN1 IDENTIFIER 0.65BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.80 0.15 0.40 6° 0.23 0.55 CO0P.0L50A.1N0ARICTOYMPLIANT0.T25OJEDECSTA0°NDARDS0M.0O9-187-AA 0.40 10-07-2009-B Figure 67. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 5.00(0.1968) 4.80(0.1890) 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 1.27(0.0500) 0.50(0.0196) BSC 1.75(0.0688) 0.25(0.0099) 45° 0.25(0.0098) 1.35(0.0532) 8° 0.10(0.0040) 0° COPLANARITY 0.51(0.0201) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 10..2470((00..00510507)) PLANE 0.17(0.0067) COMPLIANTTOJEDECSTANDARDSMS-012-AA C(RINOEFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIOARRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 012407-A Figure 68. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model1 Temperature Range Package Description Package Option Branding AD8226ARMZ −40°C to +125°C 8-Lead MSOP RM-8 Y18 AD8226ARMZ-RL −40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y18 AD8226ARMZ-R7 −40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y18 AD8226ARZ −40°C to +125°C 8-Lead SOIC_N R-8 AD8226ARZ-RL −40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD8226ARZ-R7 −40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD8226BRMZ −40°C to +125°C 8-Lead MSOP RM-8 Y19 AD8226BRMZ-RL −40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y19 AD8226BRMZ-R7 −40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y19 AD8226BRZ −40°C to +125°C 8-Lead SOIC_N R-8 AD8226BRZ-RL −40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD8226BRZ-R7 −40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8 1 Z = RoHS Compliant Part. Rev. C | Page 25 of 28

AD8226 Data Sheet NOTES Rev. C | Page 26 of 28

Data Sheet AD8226 NOTES Rev. C | Page 27 of 28

AD8226 Data Sheet NOTES ©2009–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07036-0-9/12(C) Rev. C | Page 28 of 28

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD8226ARMZ AD8226ARMZ-R7 AD8226ARZ AD8226ARZ-R7 AD8226ARMZ-RL AD8226ARZ-RL AD8226BRMZ AD8226BRMZ-R7 AD8226BRMZ-RL AD8226BRZ AD8226BRZ-R7 AD8226BRZ-RL