1.6 V, Micropower 12-/10-/8-Bit ADCs AD7466/AD7467/AD7468 FEATURES FUNCTIONAL BLOCK DIAGRAM Specified for VDD of 1.6 V to 3.6 V VDD Low power: 0.62 mW typical at 100 kSPS with 3 V supplies 12-/10-/8-BIT 0.48 mW typical at 50 kSPS with 3.6 V supplies VIN T/H APSPURCOCXEISMSAITVIEON 0.12 mW typical at 100 kSPS with 1.6 V supplies ADC Fast throughput rate: 200 kSPS Wide input bandwidth: 71 dB SNR at 30 kHz input frequency SCLK Flexible power/serial clock speed management CONTROL SDATA LOGIC No pipeline delays CS High speed serial interface: AD7466/AD7467/AD7468 AuStoPmI/QaStiPcI p™o/MwIeCrR-dOoWwInR E™/DSP compatible GND 02643-001 Power-down mode: 8 nA typical Figure 1. 6-lead SOT-23 package 8-lead MSOP package APPLICATIONS Battery-powered systems Medical instruments Remote data acquisition Isolated data acquisition GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7466/AD7467/AD74681 are 12-/10-/8-bit, high speed, 1. Specified for supply voltages of 1.6 V to 3.6 V. low power, successive approximation analog-to-digital 2. 12-, 10-, and 8-bit ADCs in SOT-23 and MSOP packages. converters (ADCs), respectively. The parts operate from a single 3. High throughput rate with low power consumption. 1.6 V to 3.6 V power supply and feature throughput rates up to Power consumption in normal mode of operation at 200 kSPS with low power dissipation. The parts contain a low 100 kSPS and 3 V is 0.9 mW maximum. noise, wide bandwidth track-and-hold amplifier, which can handle input frequencies in excess of 3 MHz. 4. Flexible power/serial clock speed management. The conversion rate is determined by the serial clock, The conversion process and data acquisition are controlled allowing the conversion time to be reduced through using CS and the serial clock, allowing the devices to interface increases in the serial clock speed. Automatic power-down with microprocessors or DSPs. The input signal is sampled on after conversion allows the average power consumption to the falling edge of CS, and the conversion is also initiated at this be reduced when in power-down. Current consumption is point. There are no pipeline delays associated with the part. 0.1 μA maximum and 8 nA typically when in power-down. The reference for the part is taken internally from V . This DD 5. Reference derived from the power supply. allows the widest dynamic input range to the ADC. Thus, the analog input range for the part is 0 V to V . The conversion 6. No pipeline delay. DD rate is determined by the SCLK. 7. The part features a standard successive approximation ADC with accurate control of conversions via a CS input. 1 Protected by U.S. Patent No. 6,681,332. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2003–2007 Analog Devices, Inc. All rights reserved.

AD7466/AD7467/AD7468 TABLE OF CONTENTS Features..............................................................................................1 Power Requirement Curves......................................................13 Applications.......................................................................................1 Terminology....................................................................................16 Functional Block Diagram..............................................................1 Theory of Operation......................................................................17 General Description.........................................................................1 Circuit Information....................................................................17 Product Highlights...........................................................................1 Converter Operation..................................................................17 Revision History...............................................................................2 ADC Transfer Function.............................................................17 Specifications.....................................................................................3 Typical Connection Diagram...................................................17 AD7466..........................................................................................3 Analog Input...............................................................................18 AD7467..........................................................................................5 Digital Inputs..............................................................................18 AD7468..........................................................................................7 Normal Mode..............................................................................19 Timing Specifications..................................................................9 Power Consumption..................................................................20 Timing Examples........................................................................10 Serial Interface................................................................................22 Absolute Maximum Ratings..........................................................11 Microprocessor Interfacing.......................................................23 ESD Caution................................................................................11 Application Hints...........................................................................25 Pin Configurations and Function Descriptions.........................12 Grounding and Layout..............................................................25 Typical Performance Characteristics...........................................13 Evaluating the Performance of the AD7466 and AD7467....25 Dynamic Performance Curves.................................................13 Outline Dimensions.......................................................................26 DC Accuracy Curves.................................................................13 Ordering Guide..........................................................................27 REVISION HISTORY 5/07—Rev. B to Rev. C Deleted Figure 3..............................................................................10 Updated Outline Dimensions.......................................................26 Changes to Ordering Guide..........................................................27 4/05—Rev. A to Rev. B Moved Terminology Section.........................................................16 Changes to Ordering Guide..........................................................27 11/04—Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to General Description....................................................1 Added Patent Number.....................................................................1 Updated Outline Dimensions.......................................................26 Changes to Ordering Guide..........................................................27 5/03—Revision 0: Initial Version Rev. C | Page 2 of 28

AD7466/AD7467/AD7468 SPECIFICATIONS AD7466 V = 1.6 V to 3.6 V, f = 3.4 MHz, f = 100 kSPS, unless otherwise noted. T = T to T , unless otherwise noted. DD SCLK SAMPLE A MIN MAX The temperature range for the B version is −40°C to +85°C. Table 1. Parameter B Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 30 kHz sine wave IN Signal-to-Noise and Distortion (SINAD) 69 dB min 1.8 V ≤ V ≤ 2 V; see the Terminology section DD 70 dB min 2.5 V ≤ V ≤ 3.6 V DD 70 dB typ V = 1.6 V DD Signal-to-Noise Ratio (SNR) 70 dB min 1.8 V ≤ V ≤ 2 V; see the Terminology section DD 71 dB typ 1.8 V ≤ V ≤ 2 V DD 71 dB min 2.5 V ≤ V ≤ 3.6 V DD 70.5 dB typ V = 1.6 V DD Total Harmonic Distortion (THD) −83 dB typ See the Terminology section Peak Harmonic or Spurious Noise (SFDR) −85 dB typ See the Terminology section Intermodulation Distortion (IMD) fa = 29.1 kHz, fb = 29.9 kHz; see the Terminology section Second-Order Terms −84 dB typ Third-Order Terms −86 dB typ Aperture Delay 10 ns typ Aperture Jitter 40 ps typ Full Power Bandwidth 3.2 MHz typ @ 3 dB, 2.5 V ≤ V ≤ 3.6 V DD 1.9 MHz typ @ 3 dB, 1.6 V ≤ V ≤ 2.2 V DD 750 kHz typ @ 0.1 dB, 2.5 V ≤ V ≤ 3.6 V DD 450 kHz typ @ 0.1 dB, 1.6 V ≤ V ≤ 2.2 V DD DC ACCURACY Maximum specifications apply as typical figures when V = 1.6 V DD Resolution 12 Bits Integral Nonlinearity ±1.5 LSB max See the Terminology section Differential Nonlinearity −0.9/+1.5 LSB max Guaranteed no missed codes to 12 bits; see the Terminology section Offset Error ±1 LSB max See the Terminology section Gain Error ±1 LSB max See the Terminology section Total Unadjusted Error (TUE) ±2 LSB max See the Terminology section ANALOG INPUT Input Voltage Ranges 0 to V V DD DC Leakage Current ±1 μA max Input Capacitance 20 pF typ LOGIC INPUTS Input High Voltage, V 0.7 × V V min 1.6 V ≤ V < 2.7 V INH DD DD 2 V min 2.7 V ≤ V ≤ 3.6 V DD Input Low Voltage, V 0.2 × V V max 1.6 V ≤ V < 1.8 V INL DD DD 0.3 × V V max 1.8 V ≤ V < 2.7 V DD DD 0.8 V max 2.7 V ≤ V ≤ 3.6 V DD Input Current, I , SCLK Pin ±1 μA max Typically 20 nA, V = 0 V or V IN IN DD Input Current, I , CS Pin ±1 μA typ IN Input Capacitance, C 10 pF max Sample tested at 25°C to ensure compliance IN Rev. C | Page 3 of 28

AD7466/AD7467/AD7468 Parameter B Version Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, V V − 0.2 V min I = 200 μA, V = 1.6 V to 3.6 V OH DD SOURCE DD Output Low Voltage, V 0.2 V max I = 200 μA OL SINK Floating-State Leakage Current ±1 μA max Floating-State Output Capacitance 10 pF max Output Coding Straight (natural) binary CONVERSION RATE Conversion Time 4.70 μs max 16 SCLK cycles with SCLK at 3.4 MHz Throughput Rate 200 kSPS max See the Serial Interface section POWER REQUIREMENTS V 1.6/3.6 V min/max DD I Digital inputs = 0 V or V DD DD Normal Mode (Operational) 300 μA max V = 3 V, f = 100 kSPS DD SAMPLE 110 μA typ V = 3 V, f = 50 kSPS DD SAMPLE 20 μA typ V = 3 V, f = 10 kSPS DD SAMPLE 240 μA max V = 2.5 V, f = 100 kSPS DD SAMPLE 80 μA typ V = 2.5 V, f = 50 kSPS DD SAMPLE 16 μA typ V = 2.5 V, f = 10 kSPS DD SAMPLE 165 μA max V = 1.8 V, f = 100 kSPS DD SAMPLE 50 μA typ V = 1.8 V, f = 50 kSPS DD SAMPLE 10 μA typ V = 1.8 V, f = 10 kSPS DD SAMPLE Power-Down Mode 0.1 μA max SCLK on or off, typically 8 nA Power Dissipation See the Power Consumption section Normal Mode (Operational) 0.9 mW max V = 3 V, f = 100 kSPS DD SAMPLE 0.6 mW max V = 2.5 V, f = 100 kSPS DD SAMPLE 0.3 mW max V = 1.8 V, f = 100 kSPS DD SAMPLE Power-Down Mode 0.3 μW max V = 3 V DD Rev. C | Page 4 of 28

AD7466/AD7467/AD7468 AD7467 V = 1.6 V to 3.6 V, f = 3.4 MHz, f = 100 kSPS, unless otherwise noted. T = T to T , unless otherwise noted. DD SCLK SAMPLE A MIN MAX The temperature range for the B version is −40°C to +85°C. Table 2. Parameter B Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE Maximum/minimum specifications apply as typical figures when V = 1.6 V, f = 30 kHz sine wave DD IN Signal-to-Noise and Distortion (SINAD) 61 dB min See the Terminology section Total Harmonic Distortion (THD) −72 dB max See the Terminology section Peak Harmonic or Spurious Noise (SFDR) −74 dB max See the Terminology section Intermodulation Distortion (IMD) fa = 29.1 kHz, fb = 29.9 kHz; see the Terminology section Second-Order Terms −83 dB typ Third-Order Terms −83 dB typ Aperture Delay 10 ns typ Aperture Jitter 40 ps typ Full Power Bandwidth 3.2 MHz typ @ 3 dB, 2.5 V ≤ V ≤ 3.6 V DD 1.9 MHz typ @ 3 dB, 1.6 V ≤ V ≤ 2.2 V DD 750 kHz typ @ 0.1 dB, 2.5 V ≤ V ≤ 3.6 V DD 450 kHz typ @ 0.1 dB, 1.6 V ≤ V ≤ 2.2 V DD DC ACCURACY Maximum specifications apply as typical figures when V = 1.6 V DD Resolution 10 Bits Integral Nonlinearity ±0.5 LSB max See the Terminology section Differential Nonlinearity ±0.5 LSB max Guaranteed no missed codes to 10 bits; see the Terminology section Offset Error ±0.2 LSB max See the Terminology section Gain Error ±0.2 LSB max See the Terminology section Total Unadjusted Error (TUE) ±1 LSB max See the Terminology section ANALOG INPUT Input Voltage Ranges 0 to V V DD DC Leakage Current ±1 μA max Input Capacitance 20 pF typ LOGIC INPUTS Input High Voltage, V 0.7 × V V min 1.6 V ≤ V < 2.7 V INH DD DD 2 V min 2.7 V ≤ V ≤ 3.6 V DD Input Low Voltage, V 0.2 × V V max 1.6 V ≤ V < 1.8 V INL DD DD 0.3 × V V max 1.8 V ≤V < 2.7 V DD DD 0.8 V max 2.7 V ≤ V ≤ 3.6 V DD Input Current, I , SCLK Pin ±1 μA max Typically 20 nA, V = 0 V or V IN IN DD Input Current, I , CS Pin ±1 μA typ IN Input Capacitance, C 10 pF max Sample tested at 25°C to ensure compliance IN LOGIC OUTPUTS Output High Voltage, V V − 0.2 V min I = 200 μA, V = 1.6 V to 3.6 V OH DD SOURCE DD Output Low Voltage, V 0.2 V max I = 200 μA OL SINK Floating-State Leakage Current ±1 μA max Floating-State Output Capacitance 10 pF max Sample tested at 25°C to ensure compliance Output Coding Straight (natural) binary CONVERSION RATE Conversion Time 3.52 μs max 12 SCLK cycles with SCLK at 3.4 MHz Throughput Rate 275 kSPS max See the Serial Interface section Rev. C | Page 5 of 28

AD7466/AD7467/AD7468 Parameter B Version Unit Test Conditions/Comments POWER REQUIREMENTS V 1.6/3.6 V min/max DD I Digital inputs = 0 V or V DD DD Normal Mode (Operational) 210 μA max V = 3 V, f = 100 kSPS DD SAMPLE 170 μA max V = 2.5 V, f = 100 kSPS DD SAMPLE 140 μA max V = 1.8 V, f = 100 kSPS DD SAMPLE Power-Down Mode 0.1 μA max SCLK on or off, typically 8 nA Power Dissipation See the Power Consumption section Normal Mode (Operational) 0.63 mW max V = 3 V, f = 100 kSPS DD SAMPLE 0.42 mW max V = 2.5 V, f = 100 kSPS DD SAMPLE 0.25 mW max V = 1.8 V, f = 100 kSPS DD SAMPLE Power-Down Mode 0.3 μW max V = 3 V DD Rev. C | Page 6 of 28

AD7466/AD7467/AD7468 AD7468 V = 1.6 V to 3.6 V, f = 3.4 MHz, f = 100 kSPS, unless otherwise noted. T = T to T , unless otherwise noted. DD SCLK SAMPLE A MIN MAX The temperature range for the B version is −40°C to +85°C. Table 3. Parameter B Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE Maximum/minimum specifications apply as typical figures when V = 1.6 V, f = 30 kHz sine wave DD IN Signal-to-Noise and Distortion (SINAD) 49 dB min See the Terminology section Total Harmonic Distortion (THD) −66 dB max See the Terminology section Peak Harmonic or Spurious Noise −66 dB max See the Terminology section (SFDR) Intermodulation Distortion (IMD) fa = 29.1 kHz, fb = 29.9 kHz; see the Terminology section Second-Order Terms −77 dB typ Third-Order Terms −77 dB typ Aperture Delay 10 ns typ Aperture Jitter 40 ps typ Full Power Bandwidth 3.2 MHz typ @ 3 dB, 2.5 V ≤ V ≤ 3.6 V DD 1.9 MHz typ @ 3 dB, 1.6 V ≤ V ≤ 2.2 V DD 750 kHz typ @ 0.1 dB, 2.5 V ≤ V ≤ 3.6 V DD 450 kHz typ @ 0.1 dB, 1.6 V ≤ V ≤ 2.2 V DD DC ACCURACY Maximum specifications apply as typical figures when V = 1.6 V DD Resolution 8 Bits Integral Nonlinearity ±0.2 LSB max See the Terminology section Differential Nonlinearity ±0.2 LSB max Guaranteed no missed codes to 8 bits; see the Terminology section Offset Error ±0.1 LSB max See the Terminology section Gain Error ±0.1 LSB max See the Terminology section Total Unadjusted Error (TUE) ±0.3 LSB max See the Terminology section ANALOG INPUT Input Voltage Ranges 0 to V V DD DC Leakage Current ±1 μA max Input Capacitance 20 pF typ LOGIC INPUTS Input High Voltage, V 0.7 × V V min 1.6 V ≤ V < 2.7 V INH DD DD 2 V min 2.7 V ≤ V ≤ 3.6 V DD Input Low Voltage, V 0.2 × V V max 1.6 V ≤ V < 1.8 V INL DD DD 0.3 × V V max 1.8 V ≤ V < 2.7 V DD DD 0.8 V max 2.7 V ≤ V ≤ 3.6 V DD Input Current, I , SCLK Pin ±1 μA max Typically 20 nA, V = 0 V or V IN IN DD Input Current, I , CS Pin ±1 μA typ IN Input Capacitance, C 10 pF max Sample tested at 25°C to ensure compliance IN LOGIC OUTPUTS Output High Voltage, V V − 0.2 V min I = 200 μA; V = 1.6 V to 3.6 V OH DD SOURCE DD Output Low Voltage, V 0.2 V max I = 200 μA OL SINK Floating-State Leakage Current ±1 μA max Floating-State Output Capacitance 10 pF max Sample tested at 25°C to ensure compliance Output Coding Straight (natural) binary CONVERSION RATE Conversion Time 2.94 μs max 10 SCLK cycles with SCLK at 3.4 MHz Throughput Rate 320 kSPS max See the Serial Interface section Rev. C | Page 7 of 28

AD7466/AD7467/AD7468 Parameter B Version Unit Test Conditions/Comments POWER REQUIREMENTS V 1.6/3.6 V min/max DD I Digital inputs = 0 V or V DD DD Normal Mode (Operational) 190 μA max V = 3 V, f = 100 kSPS DD SAMPLE 155 μA max V = 2.5 V, f = 100 kSPS DD SAMPLE 120 μA max V = 1.8 V, f = 100 kSPS DD SAMPLE Power-Down Mode 0.1 μA max SCLK on or off, typically 8 nA Power Dissipation See the Power Consumption section Normal Mode (Operational) 0.57 mW max V = 3 V, f = 100 kSPS DD SAMPLE 0.4 mW max V = 2.5 V, f = 100 kSPS DD SAMPLE 0.2 mW max V = 1.8 V, f = 100 kSPS DD SAMPLE Power-Down Mode 0.3 μW max V = 3 V DD Rev. C | Page 8 of 28

AD7466/AD7467/AD7468 TIMING SPECIFICATIONS For all devices, V = 1.6 V to 3.6 V; T = T to T , unless otherwise noted. Sample tested at 25°C to ensure compliance. All input DD A MIN MAX signals are specified with tr = tf = 5 ns (10% to 90% of V ) and timed from a voltage level of 1.4 V. DD Table 4. Parameter Limit at T , T Unit Description MIN MAX f 3.4 MHz max Mark/space ratio for the SCLK input is 40/60 to 60/40. SCLK 10 kHz min 1.6 V ≤ V ≤ 3 V; minimum f at which specifications are guaranteed. DD SCLK 20 kHz min V = 3.3 V; minimum f at which specifications are guaranteed. DD SCLK 150 kHz min V = 3.6 V; minimum f at which specifications are guaranteed. DD SCLK t 16 × t AD7466. CONVERT SCLK 12 × t AD7467. SCLK 10 × t AD7468. SCLK Acquisition Time Acquisition time/power-up time from power-down. See the Terminology section. The acquisition time is the time required for the part to acquire a full-scale step input value within ±1 LSB or a 30 kHz ac input value within ±0.5 LSB. 780 ns max V = 1.6 V. DD 640 ns max 1.8 V ≤ V ≤ 3.6 V. DD t 10 ns min Minimum quiet time required between bus relinquish and the start of the next QUIET conversion. t 10 ns min Minimum CS pulse width. 1 t 55 ns min CS to SCLK setup time. If V = 1.6 V and f = 3.4 MHz, t has to be 192 ns 2 DD SCLK 2 minimum in order to meet the maximum figure for the acquisition time. t 55 ns max Delay from CS until SDATA is three-state disabled. Measured with the load circuit 3 in Figure 2 and defined as the time required for the output to cross the V or V IH IL voltage. t 140 ns max Data access time after SCLK falling edge. Measured with the load circuit in Figure 2 4 and defined as the time required for the output to cross the V or V voltage. IH IL t 0.4 t ns min SCLK low pulse width. 5 SCLK t 0.4 t ns min SCLK high pulse width. 6 SCLK t 10 ns min SCLK to data valid hold time. Measured with the load circuit in Figure 2 and 7 defined as the time required for the output to cross the V or V voltage. IH IL t 60 ns max SCLK falling edge to SDATA three-state. t is derived from the measured time taken 8 8 by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t, quoted in the timing 8 characteristics, is the true bus relinquish time of the part, and is independent of the bus loading. 7 ns min SCLK falling edge to SDATA three-state. 200μA IOL TO OUTPUT 1.4V PIN CL 50pF 200μA IOH 02643-002 Figure 2. Load Circuit for Digital Output Timing Specifications Rev. C | Page 9 of 28

AD7466/AD7467/AD7468 TIMING EXAMPLES Timing Example 2 Figure 3 shows some of the timing parameters from Table 4 in The AD7466 can also operate with slower clock frequencies. the Timing Specifications section. As shown in Figure 3, assuming VDD = 1.8 V, fSCLK = 2 MHz, and a throughput of 50 kSPS gives a cycle time of t + t + Timing Example 1 CONVERT 8 t = 20 μs. With t = t + 15(1/f ) = 55 ns + 7.5 μs = QUIET CONVERT 2 SCLK As shown in Figure 3, f = 3.4 MHz and a throughput of SCLK 7.55 μs, and t = 60 ns maximum, this leaves t to be 12.39 8 QUIET 100 kSPS gives a cycle time of t + t + t = 10 μs. CONVERT 8 QUIET μs, which satisfies the requirement of 10 ns for t . The part is QUIET Assuming V = 1.8 V, t = t + 15(1/f ) = 55 ns + DD CONVERT 2 SCLK fully powered up and the signal is fully acquired at Point A, 4.41 μs = 4.46 μs, and t = 60 ns maximum, then t = 5.48 μs, 8 QUIET which means the acquisition/power-up time is t + 2(1/f ) = 2 SCLK which satisfies the requirement of 10 ns for t . The part is QUIET 55 ns + 1 μs = 1.05 μs, satisfying the maximum requirement of fully powered up and the signal is fully acquired at Point A. 640 ns for the power-up time. In this example and with other This means that the acquisition/power-up time is t + 2(1/f ) 2 SCLK slower clock values, the part is fully powered up and the signal = 55 ns + 588 ns = 643 ns, satisfying the maximum requirement already acquired before the third SCLK falling edge; however, of 640 ns for the power-up time. the track-and-hold does not go into hold mode until that point. In this example, the part can be powered up and the signal can be fully acquired at approximately Point B in Figure 3. CS t CONVERT t2 B A SCLK 1 2 3 4 5 13 14 15 16 t 8 t QUIET ACQUISITION TIME AUTOMATIC TRACK-AND-HOLD POWER-DOWN IN TRACK TRACK-AND-HOLD IN HOLD 1/THROUGHPUT POINT A: THE PART IF FULLY POWERED UP WITH VIN FULLY ACQUIRED. 02643-004 Figure 3. AD7466 Serial Interface Timing Diagram Example Rev. C | Page 10 of 28

AD7466/AD7467/AD7468 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Transient currents of up to A Stresses above those listed under Absolute Maximum Ratings 100 mA do not cause SCR latch-up. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Table 5. other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute V to GND −0.3 V to +7 V DD maximum rating conditions for extended periods may affect Analog Input Voltage to GND −0.3 V to V + 0.3 V DD device reliability. Digital Input Voltage to GND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to V + 0.3 V DD Input Current to any Pin Except Supplies ±10 mA ESD CAUTION Operating Temperature Range Commercial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C SOT-23 Package θ Thermal Impedance 229.6°C/W JA θ Thermal Impedance 91.99°C/W JC MSOP Package θ Thermal Impedance 205.9°C/W JA θ Thermal Impedance 43.74°C/W JC Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C ESD 3.5 kV Rev. C | Page 11 of 28

AD7466/AD7467/AD7468 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD 1 AD7466/ 6 CS CS 1 AD7466/ 8 VDD GND 2 AD7467/ 5 SDATA SDATA 2 AD7467/ 7 GND AD7468 AD7468 VIN 3 (NToOt Pto V SIEcaWle) 4 SCLK 02643-005 SCNLCK 34NC(N =To ONt POto V CSIOEcWaNlNe)EC65TVNICN 02643-006 Figure 4. SOT-23 Pin Configuration Figure 5. MSOP Pin Configuration Table 6. Pin Function Descriptions Pin No. SOT-23 MSOP Mnemonic Description 6 1 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the devices and frames the serial data transfer. 1 8 V Power Supply Input. The V range for the devices is from 1.6 V to 3.6 V. DD DD 2 7 GND Analog Ground. Ground reference point for all circuitry on the devices. All analog input signals should be referred to this GND voltage. 3 6 V Analog Input. Single-ended analog input channel. The input range is 0 V to V . IN DD 5 2 SDATA Data Out. Logic output. The conversion result from the AD7466/AD7467/AD7468 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7466 consists of four leading zeros followed by the 12 bits of conversion data, provided MSB first. The data stream from the AD7467 consists of four leading zeros followed by the 10 bits of conversion data, provided MSB first. The data stream from the AD7468 consists of four leading zeros followed by the 8 bits of conversion data, provided MSB first. 4 3 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the parts. This clock input is also used as the clock source for the conversion process of the parts. 4, 5 NC No Connect. Rev. C | Page 12 of 28

AD7466/AD7467/AD7468 TYPICAL PERFORMANCE CHARACTERISTICS DYNAMIC PERFORMANCE CURVES SCLK frequency of 3.4 MHz, and sampling at a rate of 100 kSPS for the AD7466 (see the Analog Input section). Figure 6, Figure 7, and Figure 8 show typical FFT plots for the AD7466, AD7467, and AD7468, respectively, at a 100 kSPS DC ACCURACY CURVES sample rate and a 30 kHz input tone. Figure 13 and Figure 14 show typical INL and DNL perform- Figure 9 shows the signal-to-noise and distortion ratio ance for the AD7466. performance vs. input frequency for various supply voltages POWER REQUIREMENT CURVES while sampling at 100 kSPS with an SCLK frequency of 3.4 MHz Figure 15 shows the supply current vs. supply voltage for the for the AD7466. AD7466 at −40°C, +25°C, and +85°C, with SCLK frequency of Figure 10 shows the signal-to-noise ratio (SNR) performance 3.4 MHz and a sampling rate of 100 kSPS. vs. input frequency for various supply voltages while sampling Figure 16 shows the maximum current vs. supply voltage for the at 100 kSPS with an SCLK frequency of 3.4 MHz for the AD7466 with different SCLK frequencies. AD7466. Figure 17 shows the shutdown current vs. supply voltage. Figure 11 shows the total harmonic distortion (THD) vs. analog input signal frequency for various supply voltages while sam- Figure 18 shows the power consumption vs. throughput rate for pling at 100 kSPS with an SCLK frequency of 3.4 MHz for the AD7466 with an SCLK of 3.4 MHz and different supply the AD7466. voltages. See the Power Consumption section for more details. Figure 12 shows the THD vs. analog input frequency for different source impedances with a supply voltage of 2.7 V, an 25 15 8192 POINT FFT 8192 POINT FFT VDD = 1.8V VDD = 1.8V 5 ffSINA =M P3L0Ek H= z100kSPS –5 ffSINA =M P3L0Ek H= z100kSPS SINAD = 70.82dB SINAD = 61.51dB –15 THD =–84.18dB THD =–80.61dB SFDR =–85.48dB –25 SFDR =–82.10dB B) –35 B) R (d R (d –45 N N S –55 S –65 –75 –85 –95 –115 02643-007 –105 02643-008 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (kHz) FREQUENCY (kHz) Figure 6. AD7466 Dynamic Performance at 100 kSPS Figure 7. AD7467 Dynamic Performance at 100 kSPS Rev. C | Page 13 of 28

AD7466/AD7467/AD7468 5 –65 8192 POINT FFT TEMP = 25°C –5 VDD = 1.8V –67 fSAMPLE = 100kSPS –15 fIN = 30kHz –69 SINAD = 49.83dB –25 THD =–79.37dB –71 SFDR =–70.46dB SNR (dB) –––435555 THD (dB) –––777753 VDD =V 2D.2DV = 1.8V VDD = 1.6V VDD = 3V –65 –79 –75 –81 ––8955 02643-009 ––8835 VDD = 3.6V VDD = 2.7V 02643-012 0 5 10 15 20 25 30 35 40 45 50 10 100 FREQUENCY (kHz) INPUT FREQUENCY (kHz) Figure 8. AD7468 Dynamic Performance at 100 kSPS Figure 11. AD7466 THD vs. Analog Input Frequency at 100 kSPS for Various Supply Voltages –65 –76 TEMP = 25°C TEMP = 25°C VDD = 2.7V –66 –77 –67 –78 –68 –79 SINAD (dB) ––7609 VDD = 1.8V VDD = 1.6V VDD = 2.2V THD (dB) ––8810 RIN = 10Ω RIN = 1kΩ –71 –82 RIN = 510Ω RIN = 100Ω ––7723 VDD = 3.6V VDD = 3V VDD = 2.7V 02643-010 ––8834 RIN = 0Ω 02643-013 10 100 10 100 INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) Figure 9. AD7466 SINAD vs. Analog Input Frequency Figure 12. AD7466 THD vs. Analog Input Frequency at 100 kSPS for Various Supply Voltages for Various Source Impedances –68.0 1.0 TEMP = 25°C VDD = 1.8V –68.5 0.8 TEMP = 25°C fIN = 50Hz –69.0 0.6 fSAMPLE = 100kSPS –69.5 0.4 B) dB)–70.0 VDD = 1.8V VDD = 1.6V R (LS 0.2 SNR (––7710..05 VDD = 2.2V L ERRO –0.20 N –71.5 I –0.4 –72.0 –0.6 ––7723..50 VDD = 3.6V VDD = 3V VDD = 2.7V 02643-011 ––01..80 02643-014 10 100 0 512 1024 1536 2048 2560 3072 3584 4096 INPUT FREQUENCY (kHz) CODE Figure 10. AD7466 SNR vs. Analog Input Frequency Figure 13. AD7466 INL Performance at 100 kSPS for Various Supply Voltages Rev. C | Page 14 of 28

AD7466/AD7467/AD7468 1.0 2.5 VDD = 1.8V 0.8 TEMP = 25°C fIN = 50Hz 0.6 fSAMPLE = 100kSPS A) 2.0 TEMP = +85°C n R (LSB) 00..42 RRENT ( 1.5 O U R C R 0 N L E OW 1.0 DN –0.2 TD U TEMP = +25°C –0.4 SH TEMP =–40°C 0.5 ––00..68 02643-015 0 02643-018 0 512 1024 1536 2048 2560 3072 3584 4096 1.5 2.0 2.5 3.0 3.5 4.0 CODE SUPPLY VOLTAGE (V) Figure 14. AD7466 DNL Performance Figure 17. Shutdown Current vs. Supply Voltage 290 1.4 fSAMPLE = 100kSPS TEMP =–40°C TEMP = 25°C 265 1.2 240 VDD = 3.0V A) TEMP = +25°C 1.0 Y CURRENT (μ 112691505 OWER (mW) 00..68 VDD = 2.7V PL P SUP 140 TEMP = +85°C 0.4 VDD = 2.2V 115 0.2 VDD = 1.8V 6950 02643-016 0 02643-019 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 0 50 100 150 200 250 SUPPLY VOLTAGE (V) THROUGHPUT (kSPS) Figure 15. AD7466 Supply Current vs. Supply Voltage, SCLK 3.4 MHz Figure 18. AD7466 Power Consumption vs. Throughput Rate, SCLK 3.4 MHz 560 TEMP = 25°C 500 fSCLK = 3.4MHz,fSAMPLE = 200kSPS A) 440 fSCLK = 2.4MHz,fSAMPLE = 140kSPS μ NT ( 380 E R R U 320 C M MU 260 XI A M 200 fSCLK = 1.2MHz,fSAMPLE = 50kSPS 14800 02643-017 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 SUPPLY VOLTAGE (V) Figure 16. AD7466 Maximum Current vs. Supply Voltage for Different SCLK Frequencies Rev. C | Page 15 of 28

AD7466/AD7467/AD7468 TERMINOLOGY Integral Nonlinearity (INL) Signal-to-Noise and Distortion Ratio (SINAD) The maximum deviation from a straight line passing through The measured ratio of signal-to-noise and distortion at the the endpoints of the ADC transfer function. For the AD7466/ output of the ADC. The signal is the rms value of the sine wave, AD7467/AD7468, the endpoints of the transfer function are and noise is the rms sum of all nonfundamental signals up to zero scale, a point 1 LSB below the first code transition, and full half the sampling frequency (f/2), including harmonics, but S scale, a point 1 LSB above the last code transition. excluding dc. Differential Nonlinearity (DNL) Total Unadjusted Error (TUE) The difference between the measured and the ideal 1 LSB A comprehensive specification that includes gain error, linearity change between any two adjacent codes in the ADC. error, and offset error. Offset Error Total Harmonic Distortion (THD) The deviation of the first code transition (00 . . . 000) to The ratio of the rms sum of harmonics to the fundamental. For (00 . . . 001) from the ideal (that is, AGND + 1 LSB). the AD7466/AD7467/AD7468, it is defined as Gain Error V2+V2+V2+V2+V2 The deviation of the last code transition (111 . . . 110) to THD(dB)=20log 2 3 4 5 6 V (111…111) from the ideal (that is, VREF − 1 LSB) after the offset 1 error has been adjusted out. where V is the rms amplitude of the fundamental, and V, V, 1 2 3 V, V, and V are the rms amplitudes of the second through Track-and-Hold Acquisition Time 4 5 6 sixth harmonics. The time required for the part to acquire a full-scale step input value within ±1 LSB, or a 30 kHz ac input value within Peak Harmonic or Spurious Noise (SFDR) ±0.5 LSB. The AD7466/AD7467/AD7468 enter track mode on The ratio of the rms value of the next-largest component in the the CS falling edge, and return to hold mode on the third SCLK ADC output spectrum (up to f/2 and excluding dc) to the rms S falling edge. The parts remain in hold mode until the following value of the fundamental. Typically, the value of this specifica- CS falling edge. See Figure 3 and the Serial Interface section for tion is determined by the largest harmonic in the spectrum, but more details. for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Signal-to-Noise Ratio (SNR) The measured ratio of signal to noise at the output of the ADC. Intermodulation Distortion (IMD) The signal is the rms value of the sine wave input. Noise is the With inputs consisting of sine waves at two frequencies, fa rms quantization error within the Nyquist bandwidth (f/2). and fb, any active device with nonlinearities creates distortion S The rms value of the sine wave is half of its peak-to-peak value products at sum and difference frequencies of mfa ± nfb, where divided by √2, and the rms value for the quantization noise is m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms q/√12. The ratio depends on the number of quantization levels are those for which neither m nor n are equal to zero. For in the digitization process; the more levels, the smaller the example, the second-order terms include (fa + fb) and (fa − fb), quantization noise. while the third-order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa − 2fb). For an ideal N-bit converter, the SNR is defined as The AD7466/AD7467/AD7468 are tested using the CCIF SNR = 6.02 N + 1.76 db standard where two input frequencies are used. In this case, Thus, for a 12-bit converter, it is 74 dB; for a 10-bit converter, it the second-order terms are usually distanced in frequency from is 62 dB; and for an 8-bit converter, it is 50 dB. the original sine waves, while the third-order terms are usually However, in practice, various error sources in the ADCs cause at a frequency close to the input frequencies. As a result, the the measured SNR to be less than the theoretical value. These second- and third-order terms are specified separately. The errors occur due to integral and differential nonlinearities, calculation of the intermodulation distortion is as per the internal ac noise sources, and so on. THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals, expressed in dB. Rev. C | Page 16 of 28

AD7466/AD7467/AD7468 THEORY OF OPERATION CIRCUIT INFORMATION CHARGE REDISTRIBUTION The AD7466/AD7467/AD7468 are fast, micropower, 12-bit, DAC SAMPLING 10-bit, and 8-bit ADCs, respectively. The parts can be operated CAPACITOR A from a 1.6 V to 3.6 V supply. When operated from any supply VIN SW1 CONTROL voltage within this range, the AD7466/AD7467/AD7468 are B CONVERSION SW2 LOGIC PHASE c3a.4p aMblHe zo cf ltohcrko.u ghput rates of 200 kSPS when provided with a AGND VDD/2 COMPARATOR 02643-021 The AD7466/AD7467/AD7468 provide the user with an on- Figure 20. ADC Conversion Phase chip track-and-hold, an ADC, and a serial interface housed in a ADC TRANSFER FUNCTION tiny 6-lead SOT-23 or an 8-lead MSOP package, which offer the The output coding of the AD7466/AD7467/AD7468 is straight user considerable space-saving advantages over alternative binary. The designed code transitions occur at successive solutions. The serial clock input accesses data from the part, but integer LSB values; that is, 1 LSB, 2 LSB, and so on. The LSB size also provides the clock source for the successive approximation for the devices is as follows: ADC. The analog input range is 0 V to V . An external refer- DD ence is not required for the ADC, and there is no on-chip VDD/4096 for the AD7466 reference. The reference for the AD7466/AD7467/AD7468 is V /1024 for the AD7467 DD derived from the power supply, thus giving the widest possible V /256 for the AD7468 dynamic input range. DD The ideal transfer characteristics for the devices are shown in The AD7466/AD7467/AD7468 also feature an automatic Figure 21. power-down mode to allow power savings between conversions. The power-down feature is implemented across the standard serial interface, as described in the Normal Mode section. 111...111 111...110 CONVERTER OPERATION E D The AD7466/AD7467/AD7468 are successive approximation CO111...000 C analog-to-digital converters based around a charge redistribu- D011...111 A 1LSB = VDD/4096 (AD7466) tion DAC. Figure 19 and Figure 20 show simplified schematics 1LSB = VDD/1024 (AD7467) of the ADC. Figure 19 shows the ADCs during the acquisition 000...010 1LSB = VDD/256 (AD7468) phase. SW2 is closed and SW1 is in Position A, the comparator 000...001 000...000 iasc hquelidre isn t ha eb sailgannacle do nc oVnINd.i tion, and the sampling capacitor 0V 1LSB ANALO+GVD INDP–U 1TLSB 02643-022 Figure 21. AD7466/AD7467/AD7468 Transfer Characteristics CHARGE REDISTRIBUTION DAC TYPICAL CONNECTION DIAGRAM SAMPLING A CAPACITOR Figure 22 shows a typical connection diagram for the devices. VIN SW1 COLNOTGRICOL VREF is taken internally from VDD and, therefore, VDD should B ACQPUHIASSITEION SW2 be well decoupled. This provides an analog input range of AGND VDD/2 COMPARATOR 02643-020 0 V to VDD. 2.5V 5V Figure 19. ADC Acquisition Phase 240μA 0.1μF TA1NμFT REF192 10μF 0.1μF SUPPLY When the ADC starts a conversion, as shown in Figure 20, SW2 opens and SW1 moves to Position B, causing the com- 680nF parator to become unbalanced. The control logic and the VDD charge redistribution DAC are used to add and subtract fixed 0VTIONPVUDDT VIN SCLK amounts of charge from the sampling capacitor to bring the AD7466 SDATA μC/μP comparator back into a balanced condition. When the com- GND CS ploagriact ogre nise rreatbeasl athnec eAdD, tChe o cuotnpvuet rcsoiodne .i Fs icgoumrep 2le1t es.h Tohwes ctohne tAroDl C INTSEERRFIAALCE 02643-023 transfer function. Figure 22. REF192 as Power Supply to AD7466 Rev. C | Page 17 of 28

AD7466/AD7467/AD7468 The conversion result consists of four leading zeros followed by VDD the MSB of the 12-bit, 10-bit, or 8-bit result from the AD7466, D1 C2 AD7467, or AD7468, respectively. See the Serial Interface R1 20pF section. Alternatively, because the supply current required by VIN C1 D2 CONVERSION PHASE—SWITCH OPEN the AD7466/AD7467/AD7468 is so low, a precision reference 4pF TRACK PHASE—SWITCH CLOSED cTahne bReE uFs1e9dx a sse trhiees sduepvpiclye ss oaurer cper etoc itshioen d meviiccreosp. ower, low drop- Figure 23. Equivalent Analog Input Circuit 02643-024 out voltage references. For the AD7466/AD7467/AD7468 For ac applications, removing high frequency components voltage range operation, the REF193, REF192, and REF191 can from the analog input signal by using a band-pass filter on be used to supply the required voltage to the ADC, delivering the relevant analog input pin is recommended. In applications 3 V, 2.5 V, and 2.048 V, respectively (see Figure 22). This con- where harmonic distortion and signal-to-noise ratio are critical, figuration is especially useful if the power supply is quite noisy the analog input should be driven from a low impedance or if the system supply voltages are at a value other than 3 V or source. Large source impedances significantly affect the ac 2.5 V (for example, 5 V). The REF19x outputs a steady voltage performance of the ADC. This might necessitate the use of an to the AD7466/AD7467/AD7468. If the low dropout REF192 is input buffer amplifier. The choice of the op amp is a function of used when the AD7466 is converting at a rate of 100 kSPS, the the particular application. REF192 needs to supply a maximum of 240 μA to the AD7466. The load regulation of the REF192 is typically 10 ppm/mA Table 8 provides typical performance data for various op amps (REF192, V = 5 V), which results in an error of 2.4 ppm (6 μV) used as the input buffer under constant setup conditions. S for the 240 μA drawn from it. This corresponds to a 0.0098 LSB Table 8. AD7466 Performance for Input Buffers error for the AD7466 with V = 2.5 V from the REF192. For DD Op Amp in the AD7466 SNR Performance (dB) applications where power consumption is important, the Input Buffer 30 kHz Input, V = 1.8 V DD automatic power-down mode of the ADC and the sleep mode AD8510 70.75 of the REF19x reference should be used to improve power AD8610 71.45 performance. See the Normal Mode section. AD797 71.42 Table 7 provides some typical performance data with various When no amplifier is used to drive the analog input, the source references used as a V source under the same setup DD impedance should be limited to low values. The maximum conditions. The ADR318, for instance, is a 1.8 V band gap source impedance depends on the amount of total harmonic voltage reference. Its tiny footprint, low power consumption, distortion (THD) that can be tolerated. The THD increases as and additional shutdown capability make the ADR318 ideal for the source impedance increases and performance degrades. battery-powered applications. Figure 12 shows a graph of THD vs. analog input signal Table 7. AD7466 Performance for Voltage Reference IC frequency for different source impedances when using a supply voltage of 2.7 V and sampling at a rate of 100 kSPS. Reference Tied to V AD7466 SNR Performance (dB) DD ADR318 @ 1.8 V 70.73 DIGITAL INPUTS ADR370 @ 2.048 V 70.72 The digital inputs applied to the AD7466/AD7467/AD7468 ADR421 @ 2.5 V 71.13 are not limited by the maximum ratings that limit the analog ADR423 @ 3 V 71.44 inputs. Instead, the digital inputs applied can go to 7 V and are ANALOG INPUT not restricted by the VDD + 0.3 V limit as on the analog input. For example, if the AD7466/AD7467/AD7468 are operated with An equivalent circuit of the AD7466/AD7467/AD7468 analog a V of 3 V, 5 V logic levels could be used on the digital inputs. DD input structure is shown in Figure 23. The two diodes, D1 and However, the data output on SDATA still has 3 V logic levels D2, provide ESD protection for the analog inputs. Care must be when V = 3 V. Another advantage of SCLK and CS not being taken to ensure that the analog input signal never exceeds the DD restricted by the V + 0.3 V limit is that power supply supply rails by more than 300 mV. This causes these diodes to DD sequencing issues are avoided. If CS or SCLK is applied before become forward-biased and to start conducting current into the V , there is no risk of latch-up as there would be on the analog substrate. Capacitor C1 in Figure 23 is typically about 4 pF and DD inputs if a signal greater than 0.3 V is applied prior to V . can primarily be attributed to pin capacitance. Resistor R1 is a DD lumped component made up of the on resistance of a switch. This resistor is typically about 200 Ω. Capacitor C2 is the ADC sampling capacitor with a typical capacitance of 20 pF. Rev. C | Page 18 of 28

AD7466/AD7467/AD7468 NORMAL MODE The AD7468 automatically enters power-down mode on the 12th SCLK falling edge. The AD7466/AD7467/AD7468 automatically enter power- down at the end of each conversion. This mode of operation is The AD7466 also enters power-down mode if CS is brought designed to provide flexible power management options and to high any time before the 16th SCLK falling edge. The conver- optimize the power dissipation/throughput rate ratio for low sion that was initiated by the CS falling edge terminates and power application requirements. Figure 24 shows the general SDATA goes back into three-state. This also applies for the operation of the AD7466/AD7467/AD7468. On the CS falling AD7467 and AD7468; if CS is brought high before the conver- edge, the part begins to power up and the track-and-hold, sion is complete (the 14th SCLK falling edge for the AD7467, which was in hold while the part was in power-down, goes into and the 12th SCLK falling edge for the AD7468), the part enters track mode. The conversion is also initiated at this point. On power-down, the conversion terminates, and SDATA goes back the third SCLK falling edge after the CS falling edge, the track- into three-state. and-hold returns to hold mode. Although CS can idle high or low between conversions, For the AD7466, 16 serial clock cycles are required to complete bringing CS high once the conversion is complete is recom- the conversion and access the complete conversion result. The mended to save power. AD7466 automatically enters power-down mode on the 16th When supplies are first applied to the devices, a dummy conver- SCLK falling edge. sion should be performed to ensure that the parts are in power- For the AD7467, 14 serial clock cycles are required to complete down mode, the track-and-hold is in hold mode, and SDATA is the conversion and access the complete conversion result. The in three-state. AD7467 automatically enters power-down mode on the 14th Once a data transfer is complete (SDATA has returned to three- SCLK falling edge. state), another conversion can be initiated after the quiet time, For the AD7468, 12 serial clock cycles are required to complete t , has elapsed, by bringing CS low again. QUIET the conversion and access the complete conversion result. AD7468 ENTERS POWER-DOWN AD7467 ENTERS POWER-DOWN THE PART BEGINS THE PART IS POWERED UP TO POWER UP AND VIN FULLY ACQUIRED AD7466 ENTERS POWER-DOWN CS 1 2 3 12 14 16 SCLK SDATA VALID DATA 02643-025 Figure 24. Normal Mode Operation Rev. C | Page 19 of 28

AD7466/AD7467/AD7468 POWER CONSUMPTION This reduced power consumption can be seen in Figure 25, which shows the supply current vs. SCLK frequency for various The AD7466/AD7467/AD7468 automatically enter power- supply voltages at a throughput rate of 100 kSPS. For a fixed down mode at the end of each conversion or if CS is brought throughput rate, the supply current (average current) drops as high before the conversion is finished. the SCLK frequency increases because the part is in power- When the AD7466/AD7467/AD7468 are in power-down mode, down mode most of the time. It can also be seen that, for a all the analog circuitry is powered down and the current con- lower supply voltage, the supply current drops accordingly. sumption is typically 8 nA. 390 To achieve the lowest power dissipation, there are some fSAMPLE = 100kSPS 360 TEMP = 25°C considerations the user should keep in mind. 330 VDD = 3.6V The conversion time is determined by the serial clock A) 300 frequency; the faster the SCLK frequency, the shorter the T (μ 270 conversion time. This implies that as the frequency increases, REN 240 VDD = 3.0V R the part dissipates power for a shorter period of time when the U C 210 conversion is taking place, and it remains in power-down mode PLY 180 VDD = 2.7V for a longer percentage of the cycle time or throughput rate. UP VDD = 2.2V S 150 VDD = 1.8V Figure 26 shows two AD7466s running with two different 120 SthCeL hKig fhreeqr uSeCnLcKie sf,r eSqCuLeKn cAy. aFnodr SthCeL sKam B,e wthitrho uSgChLpKu tA r ahtaev, itnhge 9600 VDD = 1.6V 02643-026 AD7466 using SCLK A has a shorter conversion time than the 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 SCLK FREQUENCY (MHz) AD7466 using SCLK B, and it remains in power-down mode Figure 25. Supply Current vs. SCLK Frequency longer. The current consumption in power-down mode is very for a Fixed Throughput Rate and Different Supply Voltages low; thus, the average power consumption is greatly reduced. 1/THROUGHPUT CONVERSION TIME B CONVERSION TIME A CS 1 16 SCLK A SCLK B 1 16 02643-027 Figure 26. Conversion Time Comparison for Different SCLK Frequencies and a Fixed Throughput Rate 1/THROUGHPUT B 1/THROUGHPUT A POWER DOWN TIME A CONVERSION TIME A CS A POWER DOWN TIME B CONVERSION TIME B CS B 1 16 SCLK 02643-028 Figure 27. Conversion Time vs. Power-Down Time for a Fixed SCLK Frequency and Different Throughput Rates Rev. C | Page 20 of 28

AD7466/AD7467/AD7468 Figure 18 shows power consumption vs. throughput rate for a The average power consumption includes the power dissipated 3.4 MHz SCLK frequency. In this case, the conversion time is when the part is converting and the power dissipated when the the same for all cases because the SCLK frequency is a fixed part is in power-down mode. The average power dissipated parameter. Low throughput rates lead to lower current con- during conversion is calculated as the percentage of the cycle sumptions, with a higher percentage of the time in power-down time spent when converting, multiplied by the maximum mode. Figure 27 shows two AD7466s running with the same current during conversion. The average power dissipated in SCLK frequency, but at different throughput rates. The A power-down mode is calculated as the percentage of cycle time throughput rate is higher than the B throughput rate. The spent in power-down mode, multiplied by the current figure for slower the throughput rate, the longer the period of time the power-down mode. In order to obtain the value for the average part is in power-down mode, and the average power consump- power, these terms must be multiplied by the voltage. tion drops accordingly. Considering the maximum current for each SCLK frequency Figure 28 shows the power vs. throughput rate for different for V = 1.8 V, DD supply voltages and SCLK frequencies. For this plot, all the Power Consumption A = ((4.7/20) × 186 μA + (15.3/20) × elements regarding power consumption that were explained 100 nA) × 1.8 V = (43.71 + 0.076) μA × 1.8 V = 78.8 μW previously (the influence of the SCLK frequency, the influence = 0.07 mW of the throughput rate, and the influence of the supply voltage) Power Consumption B = ((13/20) × 108 μA + (7/20) × are taken into consideration. 100 nA) × 1.8 V = (70.2 + 0.035) μA × 1.8 V = 126.42 μW 1.4 = 0.126 mW TEMP = 25°C 1.2 It can be concluded that for a fixed throughput rate, the average VDD = 3.0V, SCLK = 2.4MHz power consumption drops as the SCLK frequency increases. 1.0 Power Consumption Example 2 W) m 0.8 This example shows that, for a fixed SCLK frequency, as the ER ( VDD = 3.0V, SCLK = 3.4MHz throughput rate decreases, the average power consumption W 0.6 PO VDD = 1.8V, SCLK = 2.4MHz drops. From Figure 27, for SCLK = 3.4 MHz, Throughput A = 0.4 100 kSPS (which gives a cycle time of 10 μs), and Throughput B = 50 kSPS (which gives a cycle time of 20 μs), the following 0.02 VDD = 1.8V, SCLK = 3.4MHz 02643-029 valueCs ocnavne brsei oonb tTaiimneed A: = 16 × (1/SCLK) = 4.7 μs 0 50 100 150 200 250 (47% of the cycle time for a throughput of 100 kSPS) THROUGHPUT (kSPS) Figure 28. Power vs. Throughput Rate Power-Down Time A = (1/Throughput A) − Conversion for Different SCLK and Supply Voltages Time A = 10 μs − 4.7 μs = 5.3 μs (53% of the cycle time) The following examples show calculations for the information Conversion Time B = 16 × (1/SCLK) = 4.7 μs in this section. (23.5% of the cycle time for a throughput of 50 kSPS) Power Consumption Example 1 Power-Down Time B = (1/Throughput B) − Conversion This example shows that, for a fixed throughput rate, as the Time B = 20 μs − 4.7 μs = 15.3 μs (76.5% of the cycle time) SCLK frequency increases, the average power consumption The average power consumption is calculated as explained in drops. From Figure 26, for SCLK A = 3.4 MHz, SCLK B = Power Consumption Example 1, considering the maximum 1.2 MHz, and a throughput rate of 50 kSPS, which gives a cycle current for a 3.4 MHz SCLK frequency for V = 1.8 V. time of 20 μs, the following values can be obtained: DD Power Consumption A = ((4.7/10) × 186 μA + (5.3/10) × Conversion Time A = 16 × (1/SCLK A) = 4.7 μs 100 nA) × 1.8 V= (87.42 + 0.053) μA × 1.8 V = 157.4 μW = (23.5% of the cycle time) 0.157 mW Power-Down Time A = (1/Throughput) − Conversion Power Consumption B = ((4.7/20) × 186 μA + (15.3/20) × Time A = 20 μs − 4.7 μs = 15.3 μs (76.5% of the cycle time) 100 nA) × 1.8 V = (43.7 + 0.076) μA × 1.8 V = 78.79 μW = Conversion Time B = 16 × (1/SCLK B) = 13 μs 0.078 mW (65% of the cycle time) It can be concluded that for a fixed SCLK frequency, the average Power-Down Time B = (1/Throughput) − Conversion power consumption drops as the throughput rate decreases. Time B = 20 μs − 13 μs = 7 μs (35% of the cycle time) Rev. C | Page 21 of 28

AD7466/AD7467/AD7468 SERIAL INTERFACE Figure 29, Figure 30, and Figure 31 show the timing diagrams down. If the rising edge of CS occurs before 12 SCLKs elapse, for serial interfacing to the AD7466/AD7467/AD7468. The the conversion terminates, the SDATA line goes back into three- serial clock provides the conversion clock and controls the state, and the AD7468 enters power-down; otherwise SDATA transfer of information from the ADC during a conversion. returns to three-state on the 12th SCLK falling edge, as shown The part begins to power up on the CS falling edge. The falling in Figure 31. Twelve serial clock cycles are required to perform the conversion process and to access data from the AD7468. edge of CS puts the track-and-hold into track mode and takes the bus out of three-state. The conversion is also initiated at this CS going low provides the first leading zero to be read in by the point. On the third SCLK falling edge after the CS falling edge, microcontroller or DSP. The remaining data is then clocked out the part should be powered up fully at Point B, as shown in by subsequent SCLK falling edges, beginning with the second Figure 29, and the track-and-hold returns to hold. leading zero; thus, the first clock falling edge on the serial clock has the first leading zero provided and also clocks out the For the AD7466, the SDATA line goes back into three-state and second leading zero. For the AD7466, the final bit in the data the part enters power-down on the 16th SCLK falling edge. If transfer is valid on the 16th SCLK falling edge, having been the rising edge of CS occurs before 16 SCLKs elapse, the clocked out on the previous (15th) SCLK falling edge. conversion terminates, the SDATA line goes back into three- state, and the part enters power-down; otherwise SDATA In applications with a slow SCLK, it is possible to read in data returns to three-state on the 16th SCLK falling edge, as shown on each SCLK rising edge. In such a case, the first falling edge in Figure 29. Sixteen serial clock cycles are required to perform of SCLK after the CS falling edge clocks out the second leading the conversion process and to access data from the AD7466. zero and can be read in the following rising edge. If the first SCLK edge after the CS falling edge is a falling edge, the first For the AD7467, the 14th SCLK falling edge causes the SDATA leading zero that was clocked out when CS went low is missed, line to go back into three-state, and the part enters power-down. If the rising edge of CS occurs before 14 SCLKs elapse, the con- unless it is not read on the first SCLK falling edge. The 15th falling edge of SCLK clocks out the last bit, and it can be read in version terminates, the SDATA line goes back into three-state, the following rising SCLK edge. and the AD7467 enters power-down; otherwise SDATA returns to three-state on the 14th SCLK falling edge, as shown in Figure 30. If the first SCLK edge after the CS falling edge is a rising edge, CS Fourteen serial clock cycles are required to perform the clocks out the first leading zero, and it can be read on the SCLK conversion process and to access data from the AD7467. rising edge. The next SCLK falling edge clocks out the second leading zero, and it can be read on the following rising edge. For the AD7468, the 12th SCLK falling edge causes the SDATA line to go back into three-state, and the part enters power- t 1 CS t CONVERT t2 B t6 SCLK 1 2 3 4 5 13 14 15 16 t5 t8 t3 t4 t7 tQUIET SDATTHAREE-STATE 0 04 LEADING0 ZEROS 0 DB11 DB1102 BITS OF DATADB2 DB1 DB0 THREE-STATE 02643-030 Figure 29. AD7466 Serial Interface Timing Diagram t 1 CS t CONVERT t2 B t6 SCLK 1 2 3 4 5 13 14 t3 t4 t7 t5 t8 tQUIET SDATATHREE-STATE 0 0 4 LEADIN0G ZEROS 0 DB9 D1B08 BITS OF DATA DB0 THREE-STATE 02643-031 Figure 30. AD7467 Serial Interface Timing Diagram Rev. C | Page 22 of 28

AD7466/AD7467/AD7468 t 1 CS t CONVERT t2 B t6 SCLK 1 2 3 4 11 12 t3 t4 t5 t7 t8 tQUIET SDATATHREE-STATE 0 04 LEADING0 ZEROS 0 DB7 8 BITS OF DATADB0 THREE-STATE 02643-032 Figure 31. AD7468 Serial Interface Timing Diagram MICROPROCESSOR INTERFACING Figure 32 shows the connection diagram. For signal processing applications, it is imperative that the frame synchronization The serial interface on the AD7466/AD7467/AD7468 allows signal from the TMS320C541 provide equidistant sampling. the parts to be connected directly to many different micro- processors. This section explains how to interface the AD7466/ AD7466/ TMS320C5411 AD7467/AD7468 with some of the more common microcontroller AD7467/ AD74681 and DSP serial interface protocols. SCLK CLKX AD7466/AD7467/AD7468 to TMS320C541 Interface CLKR The serial interface on the TMS320C541 uses a continuous SDATA DR serial clock and frame synchronization signals to synchronize CS FSX the data transfer operations with peripheral devices like the FSR fAaDci7n4g6 b6e/tAwDee7n4 6th7/eA TDM7S436280. CTh54e 1C aSn idn pthuet AalDlo7w4sx exa dsye vinicteesr,- 1ADDITIONAL PINS OMITTED FOR CLARITY. 02643-033 Figure 32. Interfacing to the TMS320C541 without requiring any glue logic. The serial port of the TMS320C541 is set up to operate in burst mode (FSM = 1 AD7466/AD7467/AD7468 to ADSP-218x Interface in the serial port control register, SPC) with internal CLKX The ADSP-218x family of DSPs is interfaced directly to the (MCM = 1 in the SPC register) and internal frame signal AD7466/AD7467/AD7468 without any glue logic. The SPORT (TXM = 1 in the SPC register), so both pins are configured as control register must be set up as described in Table 9. outputs. For the AD7466, the word length should be set to 16 bits (FO = 0 in the SPC register). The standard synchronous Table 9. SPORT Control Register Setup serial port interface in this DSP allows only frames with a word Setting Description length of 16 bits or 8 bits. Therefore, for the AD7467 and TFSW = RFSW = 1 Alternate framing AD7468 where 14 and 12 bits are required, the FO bit also INVRFS = INVTFS = 1 Active low frame signal would be set up to 16 bits. In these cases, the user should keep DTYPE = 00 Right-justify data in mind that the last 2 bits and 4 bits for the AD7467 and ISCLK = 1 Internal serial clock AD7468, respectively, are invalid data as the SDATA line goes TFSR = RFSR = 1 Frame every word back into three-state on the 14th and 12th SCLK falling edge. IRFS = 0 Sets up RFS as an input ITFS = 1 Sets up TFS as an output To summarize, the values in the SPC register are FO = 0, SLEN = 1111 16 bits for the AD7466 FSM = 1, MCM = 1, and TXM = 1. SLEN = 1101 14 bits for the AD7467 SLEN = 1011 12 bits for the AD7468 Rev. C | Page 23 of 28

AD7466/AD7467/AD7468 The connection diagram in Figure 33 shows how the ADSP-218x AD7466/AD7467/AD7468 to DSP563xx Interface has the TFS and RFS of the SPORT tied together, with TFS set The connection diagram in Figure 34 shows how the AD7466/ as an output and RFS set as an input. The DSP operates in AD7467/AD7468 can be connected to the synchronous serial alternate framing mode, and the SPORT control register is set interface (SSI) of the DSP563xx family of DSPs from Motorola. up as described. The frame synchronization signal generated on The SSI is operated in synchronous mode and normal mode the TFS is tied to CS, and as with all signal processing applica- (SYN = 1 and MOD = 0 in Control Register B, CRB) with an tions, equidistant sampling is necessary. However, in this example, internally generated word frame sync for both Tx and Rx the timer interrupt is used to control the sampling rate of the (Bit FSL1 = 0 and Bit FSL0 = 0 in the CRB register). Set the ADC and, under certain conditions, equidistant sampling might word length in Control Register A (CRA) to 16 by setting Bits not be achieved. WL2 = 0, WL1 = 1, and WL0 = 0 for the AD7466. The word The timer registers, for example, are loaded with a value that length for the AD7468 can be set to 12 bits (WL2 = 0, WL1 = 0, provides an interrupt at the required sample interval. When an and WL0 = 1). This DSP does not offer the option for a 14-bit interrupt is received, a value is transmitted with TFS/DT (ADC word length, so the AD7467 word length is set up to 16 bits like control word). The TFS is used to control the RFS and, there- the AD7466 word length. In this case, the user should keep in fore, the reading of data. The frequency of the serial clock is set mind that the last two bits are invalid data because the SDATA in the SCLKDIV register. When the instruction to transmit with goes back into three-state on the 14th SCLK falling edge. TFS is given (that is, AX0 = TX0), the state of the SCLK is The frame sync polarity bit (FSP) in the CRB register can be set checked. The DSP waits until the SCLK goes high, low, and high to 1, which means the frame goes low and a conversion starts. again before transmission starts. If the timer and SCLK values Likewise, by means of Bits SCD2, SCKD, and SHFD in the CRB are chosen such that the instruction to transmit occurs on or register, it is established that Pin SC2 (the frame sync signal) near the rising edge of SCLK, the data can be transmitted, or it and Pin SCK in the serial port are configured as outputs, and can wait until the next clock edge. the most significant bit (MSB) is shifted first. To summarize, For example, the ADSP-2181 has a master clock frequency of MOD = 0 16 MHz. If the SCLKDIV register is loaded with the value 3, an SYN = 1 SCLK of 2 MHz is obtained, and eight master clock periods WL2, WL1, WL0 depend on the word length elapse for every SCLK period. If the timer registers are loaded FSL1 = 0, FSL0 = 0 with the value 803, 100.5 SCLKs occur between interrupts and, FSP = 1, negative frame sync subsequently, between transmit instructions. This situation SCD2 = 1 results in nonequidistant sampling as the transmit instruction is SCKD = 1 occurring on an SCLK edge. If the number of SCLKs between SHFD = 0 interrupts is a whole integer figure of N, equidistant sampling is For signal processing applications, it is imperative that the implemented by the DSP. frame synchronization signal from the DSP563xx provides AD7466/ ADSP-218x1 equidistant sampling. AD7467/ AD74681 AD7466/ DSP563xx1 SCLK SCLK AD7467/ AD74681 SDATA DR SCLK SCK CS RFS TFS SDATA SRD 1ADDITIONAFLig PuINreS 3O3M. IInTTteErDfa FcOinRg C tLoA tRhIeT YA.DSP-218x 02643-034 1ADDITIONAL PINS OCMSITTED FOR CLARISTCY2. 02643-035 Figure 34. Interfacing to the DSP563xx Rev. C | Page 24 of 28

AD7466/AD7467/AD7468 APPLICATION HINTS GROUNDING AND LAYOUT component side of the board is dedicated to ground planes, while signals are placed on the solder side. The printed circuit board that houses the AD7466/AD7467/ AD7468 should be designed such that the analog and digital Good decoupling is also very important. All analog supplies sections are separated and confined to certain areas. This facili- should be decoupled with 10 μF tantalum in parallel with 0.1 μF tates the use of ground planes that can be separated easily. A capacitors to AGND. All digital supplies should have a 0.1 μF minimum etch technique is generally best for ground planes ceramic disc capacitor to DGND. To achieve the best perform- because it gives the best shielding. Digital and analog ground ance from these decoupling components, the user should keep planes should be joined at only one place. If the devices are in a the distance between the decoupling capacitor and the VDD and system where multiple devices require an AGND to DGND GND pins to a minimum, with short track lengths connecting connection, the connection should still be made at one point the respective pins. only, a star ground point, which should be established as close EVALUATING THE PERFORMANCE as possible to the AD7466/AD7467/AD7468. OF THE AD7466 AND AD7467 Avoid running digital lines under the device because these The evaluation board package includes a fully assembled and couple noise onto the die. The analog ground plane should be tested evaluation board, documentation, and software for allowed to run under the AD7466/AD7467/AD7468 to avoid controlling the board from the PC via an evaluation board noise coupling. The power supply lines to the devices should controller. To evaluate the ac and dc performance of the use as large a trace as possible to provide low impedance paths AD7466 and AD7467, the evaluation board controller can be and to reduce the effects of glitches on the power-supply line. used in conjunction with the AD7466/AD7467CB evaluation Fast switching signals, like clocks, should be shielded with board and other Analog Devices evaluation boards ending in digital ground to avoid radiating noise to other sections of the the CB designator. board, and clock signals should never be run near the analog The software allows the user to perform ac tests (fast Fourier inputs. Avoid crossover of digital and analog signals. Traces on transform) and dc tests (histogram of codes) on the AD7466 opposite sides of the board should run at right angles to each and AD7467. See the data sheet in the evaluation board package other to reduce the effects of feedthrough on the board. A for more information. microstrip technique is the best choice, but is not always possible with a double-sided board. With this technique, the Rev. C | Page 25 of 28

AD7466/AD7467/AD7468 OUTLINE DIMENSIONS 2.90 BSC 6 5 4 1.60 BSC 2.80 BSC 1 2 3 PIN 1 INDICATOR 0.95 BSC 1.90 1.30 BSC 1.15 0.90 1.45 MAX 0.22 0.08 10° 0.60 0.15 MAX 00..5300 SEATING 4° 0.45 PLANE 0° 0.30 COMPLIANT TO JEDEC STANDARDS MO-178-AB Figure 35. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN 1 0.65 BSC 0.95 0.85 1.10 MAX 0.75 0.80 0.15 0.38 0.23 8° 0.60 0.00 0.22 0.08 0° 0.40 COPLANARITY SEATING 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 36. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. C | Page 26 of 28

AD7466/AD7467/AD7468 ORDERING GUIDE Model Temperature Range Linearity Error (LSB)1 Package Description Package Option Branding AD7466BRT-REEL7 −40°C to +85°C ±1.5 max 6-Lead SOT-23 RJ-6 CLB AD7466BRT-R2 −40°C to +85°C ±1.5 max 6-Lead SOT-23 RJ-6 CLB AD7466BRTZ-REEL2 −40°C to +85°C ±1.5 max 6-Lead SOT-23 RJ-6 C2T AD7466BRTZ-REEL72 −40°C to +85°C ±1.5 max 6-Lead SOT-23 RJ-6 C2T AD7466BRTZ-R22 −40°C to +85°C ±1.5 max 6-Lead SOT-23 RJ-6 C2T AD7466BRM −40°C to +85°C ±1.5 max 8-Lead MSOP RM-8 CLB AD7466BRM-REEL −40°C to +85°C ±1.5 max 8-Lead MSOP RM-8 CLB AD7466BRM-REEL7 −40°C to +85°C ±1.5 max 8-Lead MSOP RM-8 CLB AD7466BRMZ2 −40°C to +85°C ±1.5 max 8-Lead MSOP RM-8 CLB# AD7466BRMZ-REEL2 −40°C to +85°C ±1.5 max 8-Lead MSOP RM-8 CLB# AD7466BRMZ-REEL72 −40°C to +85°C ±1.5 max 8-Lead MSOP RM-8 CLB# AD7467BRT-REEL −40°C to +85°C ±0.5 max 6-Lead SOT-23 RJ-6 CMB AD7467BRT-REEL7 −40°C to +85°C ±0.5 max 6-Lead SOT-23 RJ-6 CMB AD7467BRT-R2 −40°C to +85°C ±0.5 max 6-Lead SOT-23 RJ-6 CMB AD7467BRTZ-REEL2 −40°C to +85°C ±0.5 max 6-Lead SOT-23 RJ-6 CMB# AD7467BRTZ-REEL72 −40°C to +85°C ±0.5 max 6-Lead SOT-23 RJ-6 CMB# AD7467BRTZ-R22 −40°C to +85°C ±0.5 max 6-Lead SOT-23 RJ-6 CMB# AD7467BRM −40°C to +85°C ±0.5 max 8-Lead MSOP RM-8 CMB AD7467BRM-REEL −40°C to +85°C ±0.5 max 8-Lead MSOP RM-8 CMB AD7467BRM-REEL7 −40°C to +85°C ±0.5 max 8-Lead MSOP RM-8 CMB AD7467BRMZ2 −40°C to +85°C ±0.5 max 8-Lead MSOP RM-8 CMU AD7468BRT-REEL −40°C to +85°C ±0.2 max 6-Lead SOT-23 RJ-6 CNB AD7468BRT-REEL7 −40°C to +85°C ±0.2 max 6-Lead SOT-23 RJ-6 CNB AD7468BRT-R2 −40°C to +85°C ±0.2 max 6-Lead SOT-23 RJ-6 CNB AD7468BRTZ-REEL2 −40°C to +85°C ±0.2 max 6-Lead SOT-23 RJ-6 CNU# AD7468BRTZ-REEL72 −40°C to +85°C ±0.2 max 6-Lead SOT-23 RJ-6 CNU# AD7468BRM −40°C to +85°C ±0.2 max 8-Lead MSOP RM-8 CNB AD7468BRM-REEL −40°C to +85°C ±0.2 max 8-Lead MSOP RM-8 CNB AD7468BRM-REEL7 −40°C to +85°C ±0.2 max 8-Lead MSOP RM-8 CNB AD7468BRMZ2 −40°C to +85°C ±0.2 max 8-Lead MSOP RM-8 CNU# AD7468BRMZ-REEL2 −40°C to +85°C ±0.2 max 8-Lead MSOP RM-8 CNU# AD7468BRMZ-REEL72 −40°C to +85°C ±0.2 max 8-Lead MSOP RM-8 CNU# EVAL-AD7466CB3 Evaluation Board EVAL-AD7467CB3 Evaluation Board EVAL-CONTROL BRD24 Control Board 1 Linearity error refers to integral nonlinearity. 2 Z = RoHS Compliant Part, # denotes lead-free product may be top or bottom marked. 3 This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes. 4 This board is a complete unit that allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. For a complete evaluation kit, order a particular ADC evaluation board (such as EVAL-AD7466CB), the EVAL-CONTROL BRD2, and a 12 V ac transformer. See relevant evaluation board data sheets for more information. Rev. C | Page 27 of 28

AD7466/AD7467/AD7468 NOTES ©2003–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02643-0-5/07(C) Rev. C | Page 28 of 28

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD7467BRMZ AD7466BRMZ-REEL7 AD7466BRMZ AD7468BRMZ AD7466BRTZ-REEL7 AD7468BRMZ-REEL7 AD7468BRTZ-REEL7 AD7468BRM AD7467BRTZ-REEL7 AD7466BRTZ-R2