AD6650 Diversity IF-to-Baseband GSM/EDGE Narrow-Band Receiver AD6650 FEATURES Smart antenna systems 116 dB dynamic range Software radios Digital VGA In-building wireless telephony I/Q demodulators PRODUCT DESCRIPTION Active low-pass filters Dual wideband ADC The AD6650 is a diversity intermediate frequency-to-baseband Programmable decimation and channel filters (IF-to-baseband) receiver for GSM/EDGE. This narrow-band VCO and phase-locked loop circuitry receiver consists of an integrated DVGA, IF-to-baseband I/Q Serial data output ports demodulators, low-pass filtering, and a dual wideband ADC. Intermediate frequencies of 70 MHz to 260 MHz The chip can accommodate IF input from 70 MHz to 260 MHz. 10 dB noise figure The receiver architecture is designed such that only one external +43 dBm input IP2 at 70 MHz IF surface acoustic wave (SAW) filter for main and one for diversity −9.5 dBm input IP3 at 70 MHz IF are required in the entire receive signal path to meet GSM/EDGE 3.3 V I/O and CMOS core blocking requirements. Microprocessor interface Digital decimation and filtering circuitry provided on-chip JTAG boundary scan remove unwanted signals and noise outside the channel of APPLICATIONS interest. Programmable RAM coefficient filters allow antialiasing, matched filtering, and static equalization functions to be combined PHS or GSM/EDGE single carrier, diversity receivers in a single cost-effective filter. The output of the channel filters Microcell and picocell systems is provided to the user via serial output I/Q data streams. Wireless local loop FUNCTIONAL BLOCK DIAGRAM TWEAK GAIN AD6650 GSM/ DAC AGC LP EDGE IF RECEIVER RELIN FILTER CTRL I LPF AAIINN VGA MUX 1A2-DBCIT CODACRCSE ORC4DTICHER OR7IIDTRHER P(RRFCOIRFG). FDICNCE BIST LPF Q SCLK CPOUT 0 SDFS LF PVLCLO/ /4 90 REF SPEORRIATL SDO0 VLDO SDO1 DR Q LPF BBIINN VGA MUX 1A2-DBCIT CODACRCSE ORC4DTICHER OR7IIDTRHER P(RRFCOIRFG). FDICNCE BIST LPF I AGC LP RELIN FILTER DAC CTRL TWEAK GAIN JTAG DIVCILDKER MICRO 03683-001 TRST TCLK TDI TDO TMS SYNC CLK CLK AVDD AGND DVDD DGND RESET CS R/W DS DE [2:0] A[2:0] D[7:0] DTACK MO Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2006–2007 Analog Devices, Inc. All rights reserved.

AD6650 TABLE OF CONTENTS Features..............................................................................................1 LO Synthesis................................................................................22 Applications.......................................................................................1 LDO..............................................................................................23 Product Description.........................................................................1 AGC Loop/Relinearization.......................................................23 Functional Block Diagram..............................................................1 Serial Output Data Port.............................................................24 Revision History...............................................................................2 Application Information................................................................26 Specifications.....................................................................................3 Required Settings and Start-up Sequence for DC Correction Explanation of Test Levels...........................................................3 .......................................................................................................26 AC Specifications..........................................................................3 Clocking the AD6650................................................................26 Digital Specifications...................................................................4 Driving the Analog Inputs........................................................27 Electrical Characteristics.............................................................5 External Reference.....................................................................27 General Timing Characteristics.................................................5 Power Supplies............................................................................27 Microprocessor Port Timing Characteristics...........................6 Digital Outputs...........................................................................28 Timing Diagrams..........................................................................7 Grounding...................................................................................28 Absolute Maximum Ratings..........................................................10 Layout Information....................................................................28 Thermal Characteristics............................................................10 Chip Synchronization................................................................29 ESD Caution................................................................................10 Microport Control..........................................................................30 Pin Configuration and Function Descriptions...........................11 External Memory Map..............................................................30 Typical Performance Characteristics...........................................13 Access Control Register (ACR)................................................30 Terminology....................................................................................14 Channel Address Register (CAR)............................................30 Equivalent Circuits.........................................................................15 Special Function Registers........................................................30 Theory of Operation......................................................................16 Data Address Registers..............................................................31 Analog Front End.......................................................................16 Write Sequencing.......................................................................31 Digital Back End.........................................................................16 Read Sequencing........................................................................31 DC Correction............................................................................16 Read/Write Chaining.................................................................31 Fourth-Order Cascaded Integrator Comb Filter (CIC4)......17 Programming Modes.................................................................31 Infinite Impulse Response (IIR) Filter.....................................18 JTAG Boundary Scan.................................................................32 RAM Coefficient Filter..............................................................18 Register Map...................................................................................33 Composite Filter.........................................................................19 Register Details...........................................................................39 Fine DC Correction...................................................................20 Outline Dimensions.......................................................................44 Peak Detector DC Correction Ranging...................................20 Ordering Guide..........................................................................44 User-Configurable Built-In Self-Test (BIST)..........................21 REVISION HISTORY 1/07—Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to Specifications................................................................3 Changes to Figure 18......................................................................13 Changes to Power Supplies Section..............................................27 Changes to Ordering Guide..........................................................44 3/06—Revision 0: Initial Version Rev. A | Page 2 of 44

AD6650 SPECIFICATIONS EXPLANATION OF TEST LEVELS I. 100% production tested. II. 100% production tested at 25°C; sample tested at specified temperatures. III. Sample tested only. IV. Parameter guaranteed by design and analysis. V. Parameter is typical value only. VI. 100% production tested at 25°C; sample tested at temperature extreme. VII. 100% production tested at +85°C. C = 40 pF on all outputs, unless otherwise specified. All timing specifications valid over VDD range of 3.0 V to 3.45 V and VDDIO LOAD range of 3.0 V to 3.45 V. AC SPECIFICATIONS AVDD and DVDD = 3.3 V, CLK = 52 MSPS (driven differentially), 50% duty cycle, unless otherwise noted. All minimum ac specifications are guaranteed from −25°C to +85°C. AC minimum specifications degrade slightly from −25°C to −40°C. Table 1. Parameter Temp Test Level Min Typ Max Unit OVERALL FUNCTION Frequency Range Full V 70 260 MHz GAIN CONTROL Gain Step Size 25°C V 0.094 dB Gain Step Accuracy 25°C V ±0.047 dB AGC Range 25°C V 36 dB BASEBAND FILTERS Bandwidth Full IV 3.36 3.5 3.64 MHz Alias Rejection at 25.9 MHz 25°C V 77 dB LO PHASE NOISE At 10 kHz Offset 25°C V −79 dBc/Hz At 20 kHz Offset 25°C V −87 dBc/Hz At 50 kHz Offset 25°C V −103 dBc/Hz At 100 kHz Offset 25°C V −112 dBc/Hz At 200 kHz Offset 25°C V −119 dBc/Hz At 400 kHz Offset 25°C V −125 dBc/Hz At 600 kHz Offset 25°C V −130 dBc/Hz At 800 kHz Offset 25°C V −133 dBc/Hz At 1600 kHz Offset 25°C V −138 dBc/Hz At 3000 kHz Offset 25°C V −143 dBc/Hz GAIN ERROR 25°C V −0.7 dB PSRR (AVDD with 20 mV RMS Ripple)1 At 5 kHz 25°C V −13.4 dBc At 10 kHz 25°C V −17 dBc At 50 kHz 25°C V −34 dBc At 100 kHz 25°C V −39.8 dBc At 150 kHz 25°C V −45.7 dBc f = 70 MHz Coarse DC Correction V −70 dB Noise Figure2 V 10 dB Input IP22 Full IV 24 43 dBm Input IP32 Full IV −15 −9.5 dBm Image Rejection Full IV −49 −33 dBc Full-Scale Input Power V 4 dBm Input Impedance V 189.6 − j33.6 Ω Rev. A | Page 3 of 44

AD6650 Parameter Temp Test Level Min Typ Max Unit f = 150 MHz Coarse DC Correction V −70 dB Noise Figure2 V 10 dB Input IP22 Full IV 24 37 dBm Input IP32 Full IV −15 −11.5 dBm Image Rejection Full IV −46.5 −33 dBc Full-Scale Input Power V 4 dBm Input Impedance V 169.3 − j59.2 Ω f = 200 MHz Coarse DC Correction V −70 dB Noise Figure2 V 10 dB Input IP22 Full IV 24 35 dBm Input IP32 Full IV −16 −12 dBm Image Rejection Full IV −46.5 −33 dBc Full-Scale Input Power V 4 dBm Input Impedance V 159.3 − j66.9 Ω f = 250 MHz Coarse DC Correction V −70 dB Noise Figure2 V 10 dB Input IP22 Full VII 24 33 dBm Input IP32 Full VII −16 −13 dBm Image Rejection Full VII −45 −33 dBc Full-Scale Input Power V 4 dBm Input Impedance V 137.1 − j72.7 Ω 1 See Figure 40 and Figure 41 for additional PSRR specifications. 2 This measurement applies for maximum gain (36 dB). DIGITAL SPECIFICATIONS AVDD and DVDD = 3.3 V, CLK = 52 MSPS, unless otherwise noted. Table 2. Parameter Temp Test Level Min Typ Max Unit DVDD Full IV 3.0 3.3 3.45 V AVDD Full IV 3.0 3.3 3.45 V T 1 IV −25 +25 +85 °C AMBIENT 1 The AD6650 is guaranteed fully functional from −40°C to +85°C. All ac minimum specifications are guaranteed from −25°C to +85°C, but degrade slightly from −25°C to −40°C. Rev. A | Page 4 of 44

AD6650 ELECTRICAL CHARACTERISTICS Table 3. Parameter (Conditions) Temp Test Level Min Typ Max Unit LOGIC INPUTS Logic Compatibility Full IV 3.3 V CMOS Digital Logic Logic 1 Voltage Full IV 2.0 VDD V Logic 0 Voltage Full IV 0 0.8 V Logic 1 Current 25°C V 60 μA Logic 0 Current 25°C V 7 μA Input Capacitance 25°C V 5 pF CLOCK INPUTS Differential Input Voltage1 25°C V 0.4 3.6 V p-p Common-Mode Input Voltage 25°C V DVDD/2 V Differential Input Resistance 25°C V 7.5 kΩ Differential Input Capacitance 25°C V 5 pF LOGIC OUTPUTS Logic Compatibility Full 3.3 V CMOS/TTL Logic 1 Voltage (I = 0.25 mA) Full IV 2.4 VDD − 0.2 V OH Logic 0 Voltage (I = 0.25 mA) Full IV 0.2 0.8 V OL IDD SUPPLY CURRENT CLK = 52 MHz (GSM Example) I Full VII 155 mA DVDD I Full VII 360 mA AVDD POWER DISSIPATION CLK = 52 MHz (GSM/EDGE Example) Full VII 1.7 2.1 W 1 All ac specifications are tested by driving CLK and CLK differentially. GENERAL TIMING CHARACTERISTICS Table 4. Parameter (Conditions) Symbol Temp Test Level Min Typ Max Unit CLK TIMING REQUIREMENTS CLK Period1 t Full I 9.6 19.2 ns CLK CLK Width Low t Full IV 0.5 × t ns CLKL CLK CLK Width High t Full IV 0.5 × t ns CLKH CLK RESET TIMING REQUIREMENTS RESET Width Low t Full IV 30 ns SSF PIN_SYNC TIMING REQUIREMENTS SYNC to ↑ CLK Setup Time tSS Full IV −3 ns SYNC to ↑ CLK Hold Time tHS Full IV 6 ns SERIAL PORT TIMING REQUIREMENTS: SWITCHING CHARACTERISTICS2 ↑ CLK to ↑ SCLK Delay (Divide-by-1) tDSCLK1 Full IV 3.2 12.5 ns ↑ CLK to ↑ SCLK Delay (For Any Other Divisor) tDSCLKH Full IV 4.4 16 ns ↑ CLK to ↓ SCLK Delay (Divide-by-2 or Even Number) tDSCLKL Full IV 4.7 16 ns ↓ CLK to ↓ SCLK Delay (Divide-by-3 or Odd Number) tDSCLKLL Full IV 4 14 ns ↑ SCLK to SDFS Delay tDSDFS Full IV 1 2.6 ns ↑ SCLK to SDO0 Delay tDSDO0 Full IV 0.5 3.5 ns ↑ SCLK to SDO1 Delay tDSDO1 Full IV 0.5 3.5 ns ↑ SCLK to DR Delay tDSDR Full IV 1 3.5 ns 1 Minimum specification is based on a 104 MSPS clock rate (an internal divide-by-2 must be used with a 104 MSPS clock rate); maximum specification is based on a 52 MSPS clock rate. This device is optimized to operate at a clock rate of 52 MSPS or 104 MSPS. 2 The timing parameters for SCLK, SDFS, SDO0, SDO1, and DR apply to both Channel 0 and Channel 1. Rev. A | Page 5 of 44

AD6650 MICROPROCESSOR PORT TIMING CHARACTERISTICS All timing specifications valid over VDD range of 3.0 V to 3.45 V and VDDIO range of 3.0 V to 3.45 V. Table 5. Microprocessor Port, Mode INM (MODE = 0); Asynchronous Operation Parameter Symbol Temp Test Level Min Typ Max Unit WRITE TIMING WR (R/W) to RDY (DTACK) Hold Time1 t Full IV 0.0 ns HWR Address/Data to WR (R/W) Setup Time1 t Full IV 0.0 ns SAM Address/Data to RDY (DTACK) Hold Time1 t Full IV 0.0 ns HAM WR (R/W) to RDY (DTACK) Delay t 2 Full IV 9.0 15.0 ns DRDY WR (R/W) to RDY (DTACK) High Delay1 t Full IV 4 × t 13 × t ns ACC CLK CLK READ TIMING Address to RD (DS) Setup Time1 t Full IV 0.0 ns SAM Address to Data Hold Time1 t Full IV 0.0 ns HAM Data Three-state Delay1 t Full V 12 ns ZD RDY (DTACK) to Data Delay1 t Full IV 0.0 ns DD RD (DS) to RDY (DTACK) Delay t 2 Full IV 9.0 15.0 ns DRDY RD (DS) to RDY (DTACK) High Delay1 t Full IV 4 × t 13 × t ns ACC CLK CLK 1 Timing is guaranteed by design. 2 Specification pertains to control signals R/W, WR, DS, RD, and CS such that the minimum specification is valid after the last control signal has reached a valid logic level. Table 6. Microprocessor Port, Mode MNM (MODE = 1) Parameter Symbol Temp Test Level Min Typ Max Unit WRITE TIMING DS (RD) to DTACK (RDY) Hold Time t Full IV 15.0 ns HDS R/W (WR) to DTACK (RDY) Hold Time t Full IV 15.0 ns HRW Address/Data to R/W (WR) Setup Time1 t Full IV 0.0 ns SAM Address/Data to R/W (WR) Hold Time1 t Full IV 0.0 ns HAM DS (RD) to DTACK (RDY) Delay2 t Full V 16 ns DDTACK R/W (WR) to DTACK (RDY) Low Delay1 t Full IV 4 × t 13 × t ns ACC CLK CLK READ TIMING DS (RD) to DTACK (RDY) Hold Time t Full IV 15.0 ns HDS Address to DS (RD) Setup Time1 t Full IV 0.0 ns SAM Address to Data Hold Time1 t Full IV 0.0 ns HAM Data Three-State Delay t Full V 13 ns ZD DTACK (RDY) to Data Delay1 t Full IV 0.0 ns DD DS (RD) to DTACK (RDY) Delay2 t Full V 16 ns DDTACK DS (RD) to DTACK (RDY) Low Delay1 t Full IV 4 × t 13 × t ns ACC CLK CLK 1 Timing is guaranteed by design. 2 DTACK is an open-drain device and must be pulled up with a 1 kΩ resistor. Rev. A | Page 6 of 44

AD6650 TIMING DIAGRAMS RESET tSSF 03683-002 Figure 2. RESET Timing Requirements CLK t DSCLKH SCLK 03683-003 Figure 3. SCLK Switching Characteristics (Divide-by-1) CLK t t DSCLKH DSCLKL SCLK 03683-004 Figure 4. SCLK Switching Characteristics (Divide-by-2 or Even Integer) CLK t t DSCLKH DSCLKLL SCLK 03683-005 Figure 5. SCLK Switching Characteristics (Divide-by-3 or Odd Integer) SCLK t DSDR DR 03683-006 Figure 6. SCLK, DR Switching Characteristics SCLK t DSDFS SDFS 03683-007 Figure 7. SCLK, SDFS Switching Characteristics SCLK t t DSD0/DSD1 SDO0/SDO1 03683-008 Figure 8. SCLK, SDO0/SDO1 Switching Characteristics Rev. A | Page 7 of 44

AD6650 CLK t t SS HS SYNC 03683-009 Figure 9. SYNC Timing Inputs RD (DS) tHWR WR (R/W) CS tSAM tHAM A[2:0] VALIDADDRESS tSAM tHAM D[7:0] VALID DATA tDRDY RDY (DTACK) tACC NOTES 12..FttAARCCOCCM ARCFEACQLEULSIRISNE GTSI MEADE MG DAEEX OPIMEFUN WMDRS O TOFON N RTINIHSEEIN CAGLD KED DPRGEEERS ISOOAFD CSRC.DEYS.SED.ACCESS TIME IS MEASURED 03683-010 Figure 10. INM Microport Write Timing Requirements RD (DS) WR (R/W) CS tSAM A[2:0] VALIDADDRESS tZD tDD tHAM tZD D[7:0] VALID DATA tDRDY RDY (DTACK) tACC NOTES 21..FttAARCCOCCM ARCEFACQLEULSIRISNE GTSI MEADE MG DAEEX OPIMEFUN RMDDS OT OOFN 1R 3TI SHCIELNKGA D PEDEDRRGEIOES DOSSFA. RCDCYE.SSED.ACCESS TIME IS MEASURED 03683-011 Figure 11. INM Microport Read Timing Requirements Rev. A | Page 8 of 44

AD6650 tHDS DS (RD) tHRW R/W (WR) CS tSAM tHAM A[2:0] VALIDADDRESS tSAM tHAM D[7:0] VALID DATA tDDTACK DTACK (RDY) tACC NOTES 12..FttAARCCOCCM ARCFEACQLEULSIRISNE GTSI MEADE MG DAEEX OPIMEFUN DMDSS OT OOFN NF TIANHLEEL CIANLDGKD EPRDEEGRSISEO AODCSFC .DETSASCEKD..ACCESS TIME IS MEASURED 03683-012 Figure 12. MNM Microport Write Timing Requirements tHDS DS (RD) R/W (WR) CS tSAM A[2:0] VALIDADDRESS tZD tDD tHAM tZD D[7:0] VALID DATA tDDTACK DTACK (RDY) tACC NOTES 21..FttAARCCOCCM ARCEFACQLEULSIRISNE GTSI MEADE MG DAEEX OPIMEFUN DMDSS OT OOFN 1T 3TH HCEELFKAA DLPLDEIRRNEIGOS DESSDA.GCEC OESFS DETDA.CAKC.CESS TIME IS MEASURED 03683-013 Figure 13. MNM Microport Read Timing Requirements Rev. A | Page 9 of 44

AD6650 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 7. Parameter Rating 121-lead chip scale package ball grid array: Supply Voltage −0.3 V to +3.6 V θ = 22.8°C/W, no airflow, measurements made in the JA Input Voltage −0.3 V to +3.6 V horizontal position on a 4-layer board. Output Voltage Swing −0.3 V to VDDIO + 0.3 V θ = 20.2°C/W, 200 LFPM airflow, measurements made in the JA Load Capacitance 200 pF horizontal position on a 4-layer board. Junction Temperature Under Bias 125°C θ = 20.7°C/W, no airflow, soldered on an 8-layer board with JA Storage Temperature Range −65°C to +150°C two layers dedicated as ground planes. Lead Temperature (5 sec) 280°C Stresses above those listed under Absolute Maximum Ratings ESD CAUTION may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 10 of 44

AD6650 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A1 CORNER INDEXAREA 1 2 3 4 5 6 7 8 91011 A B C D E F G H J K L AD6650 (NToOt Pto V SIEcWale) 03683-042 Figure 14. Pin Configuration Table 8. Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 A DGND TDI TMS TRST RESET DNC AVDD CLK CLK AGND AGND A B SDFS SCLK TDO TCLK SYNC DNC AVDD AVDD AGND AGND BIN B C SDO1 SDO0 DVDD DVDD DVDD DVDD AVDD AVDD AGND AGND BIN C D D7 DR DVDD DGND DGND DGND AVDD AVDD AGND AGND AGND D E D5 D6 DVDD DGND DGND DGND AVDD AVDD AGND AGND LF E F D3 D4 DVDD DGND DGND DGND AVDD AVDD AGND DNC VLDO F G D1 D2 DVDD DGND DGND DGND AVDD AVDD AGND AGND CPOUT G H DS (RD) D0 DVDD DGND DGND DGND AVDD AVDD AGND AGND AGND H J R/W (WR) DTACK (RDY) DVDD DVDD DVDD DVDD AVDD AVDD AGND AGND AIN J K A2 A1 CS MODE1 CHIP_ID1 DNC AVDD REFGND REFT AGND AIN K L DGND A0 MODE2 MODE0 CHIP_ID0 DNC AVDD VREF REFB AGND AGND L 1 2 3 4 5 6 7 8 9 10 11 Table 9. Pin Function Descriptions Mnemonic Type Description No. of Pins POWER SUPPLY DVDD Power 3.3 V Digital Supply. 13 AVDD Power 3.3 V Analog Supply. 19 DGND Ground Digital Ground. 17 AGND Ground Analog Ground. 22 DIGITAL INPUTS RESET Input Active Low Reset Pin. 1 SYNC Input Synchronizes Digital Filters. 1 CHIP_ID[1:0] Input Chip ID. 2 SERIAL DATA PORT SCLK Bidirectional Serial Clock. 1 SDFS Bidirectional Serial Data Frame Sync. 1 SDO[1:0] Output Serial Data Outputs. Three-stated when inactive. 2 DR Output Output Data Ready Indicator. 1 MICROPORTCONTROL D[7:0] Bidirectional Microport Data. 8 A[2:0] Input Microport Address Bits. 3 CS Input Chip Select. 1 DS (RD) Input Active Low Data Strobe (Active Low Read). 1 Rev. A | Page 11 of 44

AD6650 Mnemonic Type Description No. of Pins DTACK (RDY) Output Active Low Data Acknowledge (Microport Status Bit). Open-drain output, requires 1 external pull-up resistor of 1 kΩ. R/W (WR) Input Read Write (Active Low Write). 1 MODE [2:0] Input Selects Control Port Mode. 3 JTAG TRST Input Test Reset Pin. 1 TCLK Input Test Clock Input. 1 TMS Input Test Mode Select Input. 1 TDO Output Test Data Output. Three-stated when JTAG is in reset. 1 TDI Input Test Data input. 1 ANALOG INPUTS AIN Input Main Analog Input. 1 AIN Input Complement of AIN. Differential analog input. 1 BIN Input Diversity Analog Input. 1 BIN Input Complement of BIN. Differential analog input. 1 PLL INPUTS CPOUT Output Charge-Pump Output. 1 LF Input Loop Filter. 1 VLDO Output Compensation for Internal Low Dropout Regulator. Bypass to ground with a 220 1 nF chip capacitor. REFT Output Internal ADC Voltage Reference. Bypass to ground with capacitors. See Figure 39 1 for recommended connection. REFB Output Internal ADC Voltage Reference. Bypass to ground with capacitors. See Figure 39 1 for recommended connection. VREF Output Internal ADC Voltage Reference. Bypass to ground with capacitors. See Figure 39 1 for recommended connection. REFGND Ground ADC Ground Reference. See Figure 39 for recommended connection. 1 CLOCK INPUTS CLK Input Encode Input. Conversion initiated on rising edge. 1 CLK Input Complement of Encode. 1 DNC Do Not Connect. 5 Rev. A | Page 12 of 44

AD6650 TYPICAL PERFORMANCE CHARACTERISTICS –44 44 –45 42 –25°C +25°C –46 +25°C 40 m) Bc) –47 +85°C P2 (dB 38 –25°C +85°C AGE (d –48 II 36 M I –49 34 3320 03683-016 ––5501 03683-018 70 90 110 130 150 170 190 210 230 250 70 90 110 130 150 170 190 210 230 250 IF FREQUENCY (MHz) IF FREQUENCY (MHz) Figure 15. Input IP2 vs. Frequency Figure 17. Image vs. Frequency –6 0.2 –7 0 –25°C –8 –0.2 –9 B) d –0.4 m) R ( B –10 O IIP3 (d –11 –25°C +25°C AIN ERR ––00..68 +25°C –12 G –1.0 –13 +85°C +85°C ––1145 03683-017 ––11..24 03683-019 70 90 110 130 150 170 190 210 230 250 70 90 110 130 150 170 190 210 230 250 IF FREQUENCY (MHz) IF FREQUENCY (MHz) Figure 16. Input IP3 vs. Frequency Figure 18. Gain Error vs. Frequency Rev. A | Page 13 of 44

AD6650 TERMINOLOGY Analog Bandwidth Image The analog input frequency at which the spectral power of the The AD6650 incorporates a quadrature demodulator that mixes fundamental frequency (as determined by the FFT analysis) is the IF frequency to a baseband frequency. The phase and amplitude reduced by 3 dB. imbalance of this quadrature demodulator is observed in a complex FFT as an image of the fundamental frequency. The term image Noise Figure (NF) arises from the mirror-like symmetry of signal and image The degradation in SNR performance (in dB) of an IF input frequencies about the beating-oscillator frequency (in this signal after it passes through a component or system. case, this is dc). The AD6650 noise figure is determined by the equation Differential Analog Input Resistance, Differential Analog NF=⎜⎛10log⎜⎛V2rms Zin ⎟⎞−SNR ⎟⎞−10log⎜⎛ kTB ⎟⎞ (1) Input Capacitance, and Differential Analog Input Impedance ⎜⎝ ⎜⎝ 0.001 ⎟⎠ FS⎟⎠ ⎝0.001⎠ The real and complex impedances measured at each analog input port. The resistance is measured statically, and the where: capacitance and differential input impedances are measured k is the Boltzmann constant = 1.38 × 10−23. with a network analyzer. T is the temperature in kelvin. Differential Analog Input Voltage Range B is the channel bandwidth in hertz (200 kHz typical). The peak-to-peak differential voltage that must be applied to V2rms is the full-scale input voltage. the converter to generate a full-scale response. Peak differential Zin is the input impedance. voltage is computed by observing the voltage on a single pin SNRFS is the computed signal-to-noise ratio referred to full scale and subtracting the voltage from the other pin, which is 180° with a small input signal and the AD6650 in maximum gain. out of phase. The peak-to-peak differential voltage is computed Input Second-Order Intercept (IIP2) by rotating the phases of the inputs 180° and taking the peak A figure of merit used to determine a component’s or system’s measurement again. Then the difference is computed between susceptibility to intermodulation distortion (IMD) from its both peak measurements. second-order nonlinearities. Two unmodulated carriers at a Full-Scale Input Power specified frequency relationship (f1 and f2) are injected into a Expressed in dBm. It is computed using the following equation: nonlinear system exhibiting second-order nonlinearities ⎛V2 ⎞ producing IMD components at f1 − f2 and f2 − f1. IIP2 ⎜ Fullscalerms ⎟ graphically represents the extrapolated intersection of the Power =10log⎜⎜ ZInput ⎟⎟ (2) carrier’s input power with the second-order IMD component Fullscale 0.001 ⎜ ⎟ when plotted in decibels. ⎜ ⎟ ⎝ ⎠ Input Third-Order Intercept (IIP3) where Z is the input impedance. Input A figure of merit used to determine a component’s or system’s susceptibility to intermodulation distortion (IMD) from its Noise third-order nonlinearities. Two unmodulated carriers at a The noise, including both thermal and quantization noise, for specified frequency relationship (f1 and f2) are injected into a any range within the ADC is computed as nonlinear system exhibiting third-order nonlinearities producing IMD components at (2 × f1) – f2 and (2 × f2) – f1. V = Z×0.001×10⎜⎜⎝⎛FSdBm−SNRd1B0c−SignaldBFS⎟⎟⎠⎞ (3) noise IIP3 graphically represents the extrapolated intersection of the carrier’s input power with the third-order IMD component where: when plotted in decibels. Z is the input impedance. FS is the full scale of the device for the frequency in question. dBm SNR is the value for the particular input level. dBc Signal is the signal level within the ADC reported in decibels dBFS below full scale. Rev. A | Page 14 of 44

AD6650 EQUIVALENT CIRCUITS 1nH AIN/BIN 25Ω 75Ω CLAMP 1pF 2pF 1.3V 75Ω 25Ω 1nH AIN/BIN 03683-014 Figure 19. Analog Input AVDD 20kΩ 20kΩ 5kΩ 2.5kΩ CLK 5pF 5kΩ 2.5kΩ CLK 20kΩ 20kΩ 03683-015 Figure 20. Clock Input Rev. A | Page 15 of 44

AD6650 THEORY OF OPERATION ANALOG FRONT END that the total AD6650 response is unchanged. The 19-bit output of the AGC block is then decimated and filtered using the CIC4 filter, The AD6650 is a mixed-signal front-end (MxFE®) component the IIR filter, and the programmable RAM coefficient filter (RCF). intended for direct IF sampling radios requiring high dynamic Either 16-bit or 24-bit data is output through the serial port. range. It is optimized for the demanding performance require- With the 36 dB VGA gain, 12-bit ADC performance, and ments of GSM and EDGE. approximately 21 dB of processing gain, the AD6650 is capable The AD6650 has five signal processing stages: a digital VGA, of delivering approximately 116 dB of dynamic range or 19 bits I/Q demodulators, seventh-order low-pass filters, dual ADCs, of performance. For this reason, it is recommended that the and digital filtering. Programming and control are accom- 24-bit serial output be used so that dynamic range is not lost. plished via a microprocessor interface. A block diagram of the digital signal path is shown in Figure 21. DVGA A gain-ranging digital VGA is used to extend the dynamic AGC LP range of the ADC and minimize signal clipping at the ADC DGITEHNE.R RCETLRILN FILTER input. The VGA has a maximum gain of 36 dB with a nominal sthteep A sDize6 6o5f 00 .a0n9d4 hdaBs. aT nhoe maminpalli fiinepru ste rimvepse adsa tnhcee i onfp 2u0t 0s tΩag aen tod a CODACRCSE ORC4DTICHER OR7IIDTRHER P(RRFCOIRFG). FDICNCE BIST SPORT 03683-020 4 dBm maximum input. Figure 21. Channel Digital Signal Path I/Q Demodulators DC CORRECTION Frequency translation is accomplished with I/Q demodulators. The dc offset in the analog path of the AD6650 comes from Real data entering this stage is separated into in-phase (I) and three sources: the analog baseband filters, the ADCs, and the quadrature (Q) components. This stage translates the input LO leakage of the mixers. The dc offsets of the analog filters and signal from an intermediate frequency (IF) of 70 MHz to the ADCs dominate that of the LO leakage. The dc offsets on 260 MHz to a baseband frequency. the I and Q data for both Channel A and Channel B are Low-Pass Filters different because they use different analog paths. Each path is corrected independently. In each I/Q signal path is a seventh-order low-pass active filter with 3.5 MHz bandwidth and automatic resistance-capacitance The typical uncorrected dc offset is between −32 dB and −35 dB calibration to ±4%. This filter typically offers greater than 70 dB relative to full scale (dBFS) of the ADC. When the AGC range is of alias rejection at 25.9 MHz. considered along with this offset, the dc is effectively slid down by the gain setting so that it is approximately −68 dBFS to −71 dBFS Dual ADCs or smaller when the AD6650 is in maximum gain. The AD6650 has two ADCs. Each is implemented with an 0 AD9238 core preceded by dual track-and-holds that multiplex –10 –20 in the I and Q signals at 26 MSPS each. The full-scale input –30 power into the ADC is 4 dBm. –40 –50 DIGITAL BACK END –60 DC OFFSET –70 The 12-bit ADC data goes through the coarse dc correction –80 block, which performs a one-time calibration of the dc offsets in (dB) –1–0900 the I and Q paths. The output of this block drives the automatic –110 –120 gain control (AGC) loop block, which adjusts the digitally –130 controlled VGA in the analog path. The AGC adjusts the amplitude –140 –150 oprf etvheen itns cthoem AinDgC s ifgrnomal oclfi pinptienrge. sTt htoe gaa pinro ogfr tahme mVGabAle i sl esvueblt raancdte d –––111678000 03683-021 in the relinearization block so that externally the AD6650 appears 6 1 6 1 6 1 4 9 4 9 4 2 0 7 5 2 0 2 4 7 9 2 1 1 0 0 0 0 0 0 0 0 1 to have constant gain. For example, if the VGA must increase the –0. –0. –0. –0. –0. –0. 0. 0. 0. 0. 0. FREQUENCY (MHz) gain from 20 dB to 30 dB due to a decrease in the signal power, Figure 22. Uncorrected DC Offset the relinearization word changes from a −20 dB to a −30 dB gain so Rev. A | Page 16 of 44

AD6650 Coarse DC Correction given by Equation 6 and Equation 7. The gain and pass-band droop of the CIC4 can be calculated using these equations. If the The coarse dc correction block is a simple integrate-and-dump gain and/or droop of the CIC4 filter are not acceptable, they can that integrates the data for 16,384 cycles at the ADC clock rate be compensated for in the programmable RCF filter stage. (typically 26 MSPS) and then updates an estimate of the dc. This estimate is then subtracted from the signal path. The signal is ⎛ 1 1−Z−MCIC4 ⎞4 clipped after the subtraction to avoid numerical wrap around CIC4(Z)=⎜ × ⎟ × CIC_Gain (6) ⎜M 1−Z−1 ⎟ with large signals. ⎝ CIC4 ⎠ The −32 dBFS to −35 dBFS uncorrected offset is sufficient to 4 ⎛ ⎛ f ×M ⎞⎞ demodulate large signals, but it does not leave any margin if ⎜ sin⎜π× CIC4 ⎟⎟ 30 dB of signal-to-dc is desired. It is essential to consider the dc CIC4(f)=⎜⎜ 1 × ⎜⎝ fADC ⎟⎠⎟⎟ × CIC_Gain (7) offset of the signal at the point where the AGC of the AD6650 ⎜M ⎛ f ⎞ ⎟ begins to range. This is important because once the signal or a ⎜⎝ CIC4 sin⎜⎜⎝π× fADC ⎟⎟⎠ ⎟⎠ blocker is in the range of the AGC loop, the dc signal that appears The output rate of this stage is given by Equation 8. at the output of the AD6650 is modulated by the change in gain of the loop. If the gain decreases, the signal at the output remains f f ≤ ADC (8) at the same power level due to the digital relinearization, but the SAMP4 M CIC4 dc signal at the output is gained up by the relinearization process. CIC4 Rejection For this reason, the coarse dc correction is used to provide addi- tional correction before relinearizing the data to provide additional Table 10 shows the amount of bandwidth as a percentage of the margin. This block gains another 5 dB to 8 dB (sometimes up to input sample rate (ADC sample rate) that can be protected with 25 dB) of dc rejection that provides additional margin. various decimation rates and alias rejection specifications. The The coarse dc correction is provided for two reasons: maximum input rate into the CIC4 is 26 MHz. Table 10 shows the half-bandwidth characteristics of the CIC4. • To provide additional margin on the carrier-to-dc term for large input signals. Table 10. SSB CIC4 Alias Rejection Table • To provide more range for the fine dc correction upper dB threshold by decreasing the total input power to the block Rate −50 −60 −70 −80 −90 −100 8 2.494 1.921 1.473 1.128 0.860 0.651 for small input signals. (This is described in more detail in 9 2.224 1.713 1.315 1.007 0.768 0.581 the Fine DC Correction section.) 10 2.006 1.546 1.187 0.909 0.693 0.525 FOURTH-ORDER CASCADED INTEGRATOR COMB 11 1.827 1.408 1.081 0.828 0.632 0.478 FILTER (CIC4) 12 1.676 1.292 0.992 0.760 0.580 0.439 13 1.549 1.194 0.917 0.703 0.536 0.406 The CIC4 processing stage implements a fixed-coefficient 14 1.439 1.110 0.852 0.653 0.499 0.378 decimating filter. It reduces the sample rate of the signal and 15 1.344 1.037 0.796 0.610 0.466 0.353 allows subsequent filtering stages to be implemented more 16 1.261 0.972 0.747 0.572 0.437 0.331 efficiently. The input of the CIC4 is driven by the 19-bit relinearized 17 1.187 0.916 0.703 0.539 0.411 0.312 data at a maximum input rate of 26 MHz (52 MHz clock rate). 18 1.122 0.865 0.665 0.509 0.389 0.295 The CIC4 decimation ratio, M , can be programmed from 19 1.063 0.820 0.630 0.483 0.369 0.279 CIC4 20 1.010 0.779 0.599 0.459 0.350 0.265 8 to 32 (all integer values). The CIC4 scale factor, S , is a CIC4 21 0.962 0.742 0.570 0.437 0.334 0.253 programmable unsigned integer between 0 and 8. It serves to 22 0.919 0.709 0.544 0.417 0.319 0.241 control the attenuation of the data into the CIC4 stage in 6 dB 23 0.879 0.678 0.521 0.399 0.305 0.231 increments such that the CIC4 does not overflow. Because this 24 0.842 0.650 0.499 0.383 0.292 0.221 scale factor is in 6 dB steps, the CIC4 filter has a gain between 25 0.809 0.624 0.479 0.367 0.281 0.212 0 dB and −6.02 dB when properly scaled. For the best dynamic 26 0.778 0.600 0.461 0.353 0.270 0.204 range, SCIC4 should be set to the smallest value possible (lowest 27 0.749 0.578 0.444 0.340 0.260 0.197 attenuation) without creating an overflow condition. 28 0.722 0.557 0.428 0.328 0.251 0.190 ( ( )) 29 0.697 0.538 0.413 0.317 0.242 0.183 S =Ceil 4×log M −12 (4) CIC4 2 CIC4 30 0.674 0.520 0.400 0.306 0.234 0.177 M 4 31 0.653 0.503 0.387 0.297 0.226 0.171 CIC_Gain= CIC4 (5) 32 0.632 0.488 0.375 0.287 0.219 0.166 2SCIC4+12 Table 10 enables the calculation of an upper bound on the The value of 12 that is subtracted in Equation 4 comes from the decimation ratio (M ), given the desired filter characteristics CIC4 amount of scaling needed to compensate for the minimum and input sample rate. decimation of 8. The frequency response of the CIC4 filter is Rev. A | Page 17 of 44

AD6650 INFINITE IMPULSE RESPONSE (IIR) FILTER the band of interest is essentially perfect. From −100 kHz to +100 kHz, the phase distortion is ~0.056° rms. This phase The IIR filter of the AD6650 is a seventh-order low-pass filter response is several orders of magnitude below the analog LO with an infinite impulse response. This filter cannot be bypassed and analog filter phase distortions. and always performs a decimation of 2. As can be seen from the Z-transform, the IIR filter has a gain of −6.02 dB to accommodate 0.001 signal peaking within the structure. It is designed to be free of limit cycles and is unconditionally stable. The IIR filter is 6 × 10–4 s) described by the Z-transform and coefficients shown in the e e gr following equation: e D IIR(z)=(n0×z7+n2×(zd57+×nz37×+zd35+×nz15×+zd+3n×1z×3+z6d+1×n3z×)×z42+n2× z2+n0) ESPONSE (–22 ×× 1100––44 IIR PHASE RESPONSE R (9) E S A where: H P–6 × 10–4 nn01 == 00..024768292671 –0.001 03683-023 n = 0.76021 –100 –50 0 50 100 2 CHANNEL BW (kHz) n = 1.208472 3 Figure 24. IIR Phase Response d = 0 0 RAM COEFFICIENT FILTER d = 0.12895 1 d2 = 0 The final signal processing stage is a sum-of-products decimating d3 = 0.254698 filter with programmable coefficients (see Figure 25). The I-RAM d4 = 0 and Q-RAM data memories store the most recent complex d5 = 1.026276 samples from the IIR filter with 23-bit resolution. The number d6 = 0 of samples stored in these memories is equal to the coefficient d7 = 1 length (Ntaps), up to 48 taps. The coefficient memory, CMEM, stores up to 48 coefficients with 20-bit resolution. On every Figure 23 shows the magnitude response of the IIR filter in a CLK (up to 52 MHz) cycle, one tap for I and one tap for Q are typical GSM/EDGE case where the ADCs are sampling at calculated using the same coefficients. The RCF output consists 26 MHz and the CIC filter is decimating by 12 to generate a of 16-bit or 24-bit data. 2.16 MHz (8× symbol rate) input rate to the IIR. 0 I IN 48× 23 28 I-RAM –10 –20 –30 48× 20 CSOCAARLSEE 25 24 C-RAM –40 IIR RESPONSE (dB) ––5600 Q IN Q48-R×A 2M3 28 WRONRDD 03683-024 –70 Figure 25. Block Diagram of the RCF –80 RCF Decimation Register –90 Each RCF channel can decimate the data rate by a factor of 1 to –100 ––112100 03683-022 8st.o Trhede dinec Aimddatrieosns r0exg1is8t eirn i st hae 3 f-obritm re ogfi sMterR.C TF −h e1 R. TChFe d iencpimuta rtiaotne is 200 000 800 600 400 200 0 200 400 600 800 000 200 to the RCF is fSAMPIIR. 1 1 – – – – 1 1 – – FREQUENCY (MHz) RCF Decimation Phase Register Figure 23. IIR Frequency Response The AD6650 uses the value stored in this register to preload the Figure 24 shows the phase response of the IIR filter over the RCF counter. Therefore, instead of starting from 0, the counter range of ±100 kHz after a time delay during which ~13.449 input is loaded with this value, thus creating a time offset in the samples of the filter have been removed. The input rate is the output data. This data is stored in Address 0x19 as a 3-bit same 2.16 MHz from the above GSM/EDGE configuration. number. Time delays can be achieved in even units of the RCF Examining the plot shows that the IIR filter is not exactly phase input rate, which is typically ¼ of the symbol time for GSM. linear. (Linear phase would be flat after the time delay has been removed). It can be seen, however, that the phase response over Rev. A | Page 18 of 44

AD6650 RCF Filter Length The output rate of this filter (f ) is determined by the output SAMPR rate of the IIR stage and M . The maximum number of taps this filter can calculate, N , is RCF taps given by Equation 10. The value Ntaps − 1 is written to the f f = SAMPIIR (11) channel register within the AD6650 at Address 0x1B. SAMPR M RCF ⎛ f ×M ⎞ N ≤min⎜ CLK RCF ,48⎟ (10) where: taps ⎜⎝ fSAMPIIR ⎟⎠ f is the input rate to the RCF. SAMPIIR where: MRCF is the RCF filter decimation rate. f is the external frequency oscillator. RCF Output Scale Factor and Control Register CLK MRCF is the RCF filter decimation rate. Address 0x1C is used to configure the scale factor for the RCF fSAMPIIR is the input rate to the RCF. filter. This 2-bit register is used to scale the output data in 6 dB increments. The possible output scales range from 0 dB to −18 dB. The RCF coefficients are located in Address 0x40 to Address 0x6F, and are interpreted as 20-bit twos complement numbers. When The AD6650 RCF uses a recirculating multiply accumulator writing the coefficient RAM, the lower addresses are multiplied (MAC) to compute the filter. This accumulator has three bits of by relatively older data from the IIR, and the higher coefficient growth, allowing the output of the accumulator to be up to eight addresses are multiplied by relatively newer data from the IIR. times as large as the input signal. To achieve the best filter The coefficients need not be symmetric, and the coefficient performance, the coefficients should be as large as possible length, Ntaps, can be even or odd. If the coefficients are without overflowing the accumulator. The gain of a filter is symmetric, both sides of the impulse response must be written merely the sum of the coefficients; therefore, for normal steady into the coefficient RAM. state signals, the sum of the coefficients must be less than 8. If The RCF stores the data from the IIR into a 46 × 48 RAM. A the sum of the coefficients is 8 or slightly less, very rare RAM of 23 × 48 is assigned to I data, and a RAM of 23 × 48 is transient events can overflow the accumulator. To prevent this, assigned to Q data. the sum of the absolute values of the coefficients should be less than 8. It is then impossible for the RCF filter to overflow. When the RCF is triggered to calculate a filter output, it starts The RCF filter has a 4-position mux at the output of the by multiplying the oldest value in the data RAM by the first accumulator. This mux chooses which 24 bits are propagated to coefficient, which is pointed to by the RCF coefficient offset the output and adjusts the rounding appropriately. This can be register (Address 0x1A). This value is accumulated with the viewed as a gain block that can be varied in 6 dB steps and is products of newer data-words multiplied by the subsequent controlled by the 2-bit RCF scale register. locations in the coefficient RAM until the coefficient address RCFOFF + Ntaps − 1 is reached. The resulting gain of the RCF (RCFgain) is then represented by the following equation: Table 11. Three-Tap Filter 1 Coefficient Address Impulse Response Data RCFgain=∑Coef × (12) 0 h(0) N(0) oldest 23−RCFScale 1 h(1) N(1) where RCFScale is the value in the RCF scale register. 2 = (N − 1) h(2) N(2) newest taps COMPOSITE FILTER The total gain of the digital filters can be calculated with The RCF coefficient offset register can be used for two purposes. Equation 13 and must be less than or equal to 1 (0 dB). The main purpose is to allow multiple filters to be loaded into Typically, the RCF coefficient gain is scaled to compensate for memory and selected simply by changing the offset. The other the gain of the CIC and IIR, and the RCF scale factor is set to 3. is to contribute to the symbol timing adjustment. If the desired filter length is padded with 0s on the ends, the starting point Gain= MCIC44 ×1× ⎜⎛∑Coef × 1 ⎟⎞ (13) can be adjusted to form slight delays in the time the filter is 2SCIC4+12 2 ⎝ 23−RCFScale ⎠ computed with reference to the high speed clock. This allows where: for vernier adjustment of the symbol timing. Coarse adjustments Gain is the gain of the digital filters. can be made with the RCF decimation phase. M is the CIC4 decimation ratio. CIC4 S is the CIC4 scale factor. CIC4 RCFScale is the value in the RCF scale register. The individual responses of the CIC4 and IIR filters, along with the composite response of all the filters, are shown in Figure 26. Rev. A | Page 19 of 44

AD6650 0 ⎛ f ⎞ –10 PG=10×log⎜⎜ BW ⎟⎟ (14) –20 ⎝ fHPF ⎠ –30 where: CIC4 RESPONSE –40 AD6650 DIGITAL f is the channel filter bandwidth. COMPOSITE BW –50 RESPONSE f is the HPF bandwidth. dB) –60 HPF ( IIR FILTER In the case of GSM, a simple HPF is not well suited to this –70 RESPONSE problem because the signal power can vary 50 dB or more from –80 time slot to time slot and has a total dynamic range of 91 dB or –90 more. A large time slot would excite the impulse response of the –100 ––112100 03683-025 HtimPFe, sploots sisib plyre rseesnutl.t iTnog pinro av ipdeea ak mococruer oripntgim laatle rd cw choernr eac stimonal, l –1.98 –1.46 –0.94 –0.43 017 0.61 1.13 1.65 2.17 the AD6650 adaptively adjusts the bandwidth of the HPF based FREQUENCY (MHz) Figure 26. Composite Digital Response with 8× Rate on the signal power. As the signal level decreases, the HPF bandwidth increases. Conversely, as the signal level increases, FINE DC CORRECTION the HPF bandwidth decreases. The fine dc correction block in the AD6650 lies between the The AD6650 implements this high-pass filter in the form of an RCF and serial output port. While the coarse dc correction accumulator that integrates a number of samples of the output block at the front of the channel is included to provide a one- of the RCF and produces an estimate after the samples are time correction at startup or at rare intervals when commanded accumulated. The estimated dc is then removed from the signal by the user, the fine dc correction block is intended to run path by a simple subtraction. The subtraction is clamped to continuously and track any changes in the dc offsets of the avoid overflow problems. The HPF bandwidth is varied by analog front end. To achieve this efficiently under varying changing the integration time (equivalent to a SYNC 1 filter signal conditions, this dc estimation process is adaptive. decimation of the integrator). The integration time is varied based Adaptive DC Correction Filter on the output of a peak detector circuit according to the process In typical applications where dc offsets are to be corrected, a described in the Peak Detector DC Correction Ranging section. high-pass filter (HPF) is used to remove the dc and some small PEAK DETECTOR DC CORRECTION RANGING percentage of the input signal power. This approach is The peak detector of the AD6650 always looks at the maximum straightforward and works well when the input signal has a signal power present in the I or Q data path. The I and Q paths relatively constant power or when the bandwidth of the HPF is are treated totally independently in the dc correction circuitry extremely small (in the μHz or nHz range) and the dc content because the analog paths are not guaranteed to match. The first does not vary. In general, the more the input signal power can sample that arrives is rectified and preloaded into the peak vary, the narrower the bandwidth of the high-pass filter must be detector. A control counter is set to the minimum period to avoid low frequency transients in the filter that are larger control register setting. On every input sample, the peak than the smallest expected signals. A fundamental trade-off detector determines if the new sample is larger than the exists because if the high-pass filter has a very low bandwidth, it currently held sample, and if so, the peak detector is updated. can only track very slow changes (over hours, days, or weeks) in The contents of the peak detector are then examined. If they are the dc offsets of the device. On the other hand, if it has a higher below the lower threshold, the control counter counts down and bandwidth, it may not be able to estimate the dc properly in the when it reaches 0, it updates the dc estimate, resets the dc presence of a large baseband signal. accumulator, and reloads the peak detector with the newest Given the assumption that the signal of interest is uniformly input sample magnitude. If the peak detector value is above the distributed across frequency, the processing gain equation can upper threshold of the dc correction, the estimate currently be used to provide a starting point for system optimization. being calculated is discarded. When the signal drops below the Enough processing gain must be guaranteed for the dc estimate upper threshold, the calculation of a new dc estimate begins. to be valid for a minimum signal case. This is typically 20 dB to The current estimate is held, so the last known dc content 30 dB but depends on the baseband signal processing of a continues to be removed. particular system. For GSM/EDGE, which is distributed over The AI, AQ, BI, and BQ paths of the AD6650 are each treated ~100 kHz single sideband (SSB), this implies that the HPF independently in the dc correction circuitry because the analog bandwidth must be between 100 Hz to 1 kHz SSB. For every paths are not guaranteed to match, and separate dc estimates 6 dB that the signal power increases, 6 dB more processing gain need to be kept for each. Separate peak detectors, dc estimate is required; therefore, the HPF bandwidth needs to decrease by accumulators, dc estimate subtractors, and control counters are a factor of 4 or more. implemented for each of these paths. (14) Rev. A | Page 20 of 44

AD6650 Peak Detector I_P=2Min_Period+Ceil⎜⎛Desired_Signal_Power−Lower_Threshold ⎟⎞×2 The peak detector always stores the input sample with the ⎜ 6.02 ⎟ ⎝ ⎠ largest magnitude. The absolute value of every input sample is (16) compared to what is currently in the peak detector’s holding where Min_Period, Upper_Threshold, and Lower_Threshold are register. The only exception is when the control counter reaches register-programmable values. 0; at this point, the dc offset estimate is updated and the peak To calculate the time required for the fine dc correction to detector is set to the current input magnitude. The output of converge, use the following equation: each of the peak detectors is then encoded into a digital word that represents the signal power in 6 dB steps relative to full I_P×T Fine_DC_Converge= SYM (17) scale (FS). 60 DC Accumulator where: The dc accumulator accumulates the 24-bit samples input from T is the output symbol rate of the AD6650. SYM the RCF filter until the control counter reaches 0. At this time, Fine_DC_Converge is expressed in minutes, and for a GSM the dc estimate in the holding register is updated, and the application with 1× oversampling, it is 3.69 × 10−6. accumulator is directly loaded with the new input sample to USER-CONFIGURABLE BUILT-IN SELF-TEST (BIST) begin work on the next estimate. Control Counter The AD6650 includes a BIST to assess digital functionality. This feature verifies the integrity of the main digital signal paths of This counter controls the update of the dc correction block the AD6650. Each BIST register is independent, meaning that based on the peak detector value and the input control registers. each channel can be tested independently at the same time. The following three conditions are possible: The BIST is a thorough test of the selected AD6650 digital • If the digital word from the peak detector indicates that the signal path. With this test mode, it is possible to use the internal desired signal is below the lower threshold, the counter pseudorandom generator to produce known test data. A merely cycles through at the minimum period. signature register follows the fine dc correction block. This • If the digital word from the peak detector indicates that the register can be read back and compared to a known good desired signal is above the upper threshold, the control signature. If the known good signature matches the register counter is held at the minimum period value and does value, the channel is fully operational. not count down; therefore, no update is made. When the If an error is detected, each internal block can be bypassed and signal returns below the upper threshold, this counter another test can be run to debug the fault. The I and Q paths are resumes counting. tested independently. Use the following steps to perform this test: • If the digital word from the peak detector indicates that the desired signal is between the lower threshold and the upper 1. Reset the AD6650. threshold, the fine dc correction circuit is in its normal mode 2. Program the desired AD6650 channel parameters for the of operation. In this mode, the control counter starts with the desired application (these parameters include decimation minimum period but is reloaded with 4× minimum period rates, scalars, and RCF coefficients). Also, ensure that the every time the peak detector output words increment by start holdoff counter is set to a nonzero value. 6 dB. This errs on the side of caution and ensures that the 3. Set Register 0xA, Bit 1, to 1 (PN_EN). dc correction integrates long enough to obtain a valid 4. Set Register 0x21, Bit 8, to 0 (fine DCC to BIST). estimate. If smaller integrations are preferred, the minimum 5. Start the A and/or B channels with a microprocessor write period can be decreased or the lower threshold can be raised. (Soft_SYNC) or a pulse on the SYNC pin (Pin_SYNC). 6. Wait at least 300 μs. The integration period is given by Equation 15 and Equation 16. 7. Read the four BIST registers and compare the values to a The factor of 2 in the exponent shows that as peak signal power known good device. This ensures that the AD6650 is increases, the integration time is increased by a factor of 4. This programmed correctly and that each channel is decreases the bandwidth of the estimation filter, thus providing functioning correctly. the additional processing gain in the dc estimation term. When the desired signal power equals the upper threshold, I_P=2Min_Period+Ceil⎜⎛Upper_Threshold−Lower_Threshold ⎟⎞×2 ⎜ 6.02 ⎟ ⎝ ⎠ (15) When the desired signal power is less than the upper threshold, Rev. A | Page 21 of 44

AD6650 LO SYNTHESIS therefore, the PFD reference frequency should be set for optimal placement of spurs. The AD6650 has a fully integrated quadrature LO synthesizer consisting of a voltage-controlled oscillator (VCO) and a phase- Prescaler and Feedback Dividers locked loop (PLL). Together these blocks generate quadrature The dual modulus prescaler, P/(P + 1), and the A and B IF LO signals for the demodulators. feedback dividers (5 bits and 13 bits, respectively) combine to Figure 27 shows a block diagram of the LO synthesis block. provide a wide ranging N-divider in the PLL feedback loop. The Besides the usual PLL and VCO, there is also a programmable feedback division is N = 8B + A. Including the final quadrature half-rate divider (Div-X and a fixed divide-by-4 quadrature divider (divide-by-4), the LO frequency is given by divider that produces the final I and Q LO signals). ( ) f × B×8+A f = CLK (18) VCO LO 4R The VCO generates an on-chip RF signal in the range of where: 2.2 GHz to 2.8 GHz. The only external component required is a f is the local oscillator frequency. bypass capacitor for the low dropout (LDO) voltage regulator LO f is the external frequency oscillator. used to power the VCO tank core. The VCO uses overlapping CLK B is the 13-bit divider (3 to 8191). bands to achieve the wide tuning range while maintaining A is the 5-bit swallow divider (0 to 31). excellent phase noise and spurious performance. During band R is the input reference divider (1 to 16,384). selection, which takes 5 PFD cycles, the VCO V is disconnected TUNE from the output of the loop filter and connected to an internal The f /4R term combines the effects of the reference divider CLK reference voltage. After band select, normal PLL action and the final quadrature divider, and determines the frequency resumes. The nominal value of K is 65 MHz/V, where K is the spacing for the LO synthesizer. For a typical GSM application, V V VCO sensitivity. f = 52 MHz and R = 65 result in a 200 kHz PFD update rate, CLK which sets the frequency spacing at a desired 200 kHz. However, Immediately following the VCO is a programmable half-rate this also places LO spurs at offsets of 200 kHz multiples, which divider that has settings of divide-by-2, -2.5, -3, -3.5, and so on, might degrade the interferer/blocker performance. up to divide-by-8. This function divides the VCO frequency down to four times the LO frequency and effectively extends CAL the tuning range of the VCO. The VCO and the half-rate da ifvriedqeure cnacny brea nthgeo uogf h2t8 o0f M asH az s tion g1l0e 4lo0 wMerH fzr.e quency VCO with fCLK 1R4--DBIIVT fREF PFD UDPN CHPUAMRGPE LEOXOTPE FRINLATELR VCO DIV-X DIV-4 QIOOUUTT Autocalibration selects both the VCO operating band and the oscillator amplitude to ensure peak operating performance across the entire frequency range. The half-rate divide setting is N-COUNTER also selected as part of the VCO calibration. Autocalibration is 1B3--DBIIVT PRESCALER performed whenever PLL Register 3 (the test mode latch) is P/(P + 1) A-DIV 5-BIT written; therefore, all other PLL registers should be set first, and Register 3 should be written to last. This is true whenever 03683-027 programming any portion of the LO synthesizer because the Figure 27. PLL Circuit VCO may need to recalibrate itself, depending on the changes PFD and Charge Pump made to the registers. The phase-frequency detector (PFD) takes inputs from the PLL R-divider and N-divider and produces an output proportional The integer-N type PLL consists of a programmable reference to the phase and frequency difference between them. The PFD divider (R-divider), a prescaler and feedback divider (N-divider), includes a programmable delay element that controls the width a phase-frequency detector (PFD), and a charge pump. The of the antibacklash pulse. This pulse ensures that there is no output of the charge pump drives an external loop filter, which dead zone in the PFD transfer function and minimizes in turn drives the input of the VCO. reference spurs. R-Divider Loop Filter The 14-bit R-divider divides down the input clock frequency to The final element in the LO synthesizer is the external loop produce the reference frequency for the phase-frequency filter, which is generally a first-order or second-order RC low- detector. Although division ratios from 1 to 16,383 are allowed, pass filter. A filter like the one shown in Figure 28 is recommended the maximum update rate for the PFD is 1 MHz. The selected to provide a good balance of stability, spurs, and phase noise. update rate of the PFD and the subsequent charge pump This partiular filter is optimized for an update rate of 1 MHz. determines the spurious performance of the LO synthesizer; Rev. A | Page 22 of 44

AD6650 Slow Loop LF 867Ω The slow loop is the main loop and is associated with a loop CP gain parameter. This parameter controls the rate of change of 200Ω the gain and should always be less than 1. To determine the AD6650 56000pF 3900pF 1.0µF loop gain, Equation 19 should be used. VLDO 03683-028 AGCLoopGain=⎜⎝⎛KM2a5n6tissa ⎟⎠⎞×2−KExponent (19) Figure 28. Loop Filter Circuit where: VP CHARGE K is the loop gain mantissa. Values can range from 0 to 63. PUMP Mantissa UP K is the loop gain exponent. Values can range from 0 to 7. HI D1 Q1 Exponent U1 As the loop gain value increases, the speed of the response of R-DIVIDER CLR1 the AGC loop increases; as the loop gain value decreases, so BLE does the speed of the response of the AGC loop. The slow loop GRAMMADELAY U3 CP aletvteeml, pretfse tror emd ation atasi nth teh ree sqiugensatle den lteevreiln. gT thhies lAevDeCl i sa ts pa egciivfeiend in O R dBFS and can be between 0 dBFS and −24 dBFS (in 0.094 dB P ADP2 steps) of the converter resolution. The default value is −6.02 dBFS. ADP1 The slow loop has a peak detection function, the period of CLR2 DOWN HI D2 Q2 which can be set by the user. This period should be set to ¼ of U2 the symbol period, or greater, to prevent the AGC loop from N-DIVIDER CPGND gaining off the envelope of the EDGE signal. This detection period works because the peak detector’s operation is based on dB (max(|I|, |Q|)); therefore, all of the I/Q samples are reflected R-DIVIDER back into one quadrant of the I/Q plane. At a 26 MHz sampling N-DIVIDER frequency, one symbol period is 96 clock cycles. Therefore, to obtain a peak detector period that is ¼ of the symbol period, CP OUTPUT 03683-029 the peak detector period should be set to a minimum of 24 Figure 29. PFD Simplified Schematic and Timing (Locked) samples. The following equation can also be used: LDO SPBPeakSamples≥1 ×(f /f ) (20) 4 SAMP SYM The AD6650 includes an on-chip 2.6 V low dropout (LDO) where: voltage regulator that supplies the VCO and other sections of f = 270.833 kHz (GSM symbol rate). the PLL. A 0.22 μF bypass capacitor is required on the VLDO SYM f = 26 MHz. output to ensure stability. This LDO employs the same technology SAMP used in the anyCAP® line of regulators from Analog Devices, Inc., Fast Attack (FA) Loop making it insensitive to the type of capacitor used. Driving an The FA loop utilizes an analog threshold detector that prevents external load from the VLDO output is not supported. overdrive of the analog signal path. In a situation that could AGC LOOP/RELINEARIZATION potentially overdrive the ADC, the FA loop takes over from the slow loop and decreases the gain to the VGA in the front end. The AGC consists of three gain control loops: a slow loop, a fast The step size used for the FA loop is programmable between attack (FA) loop, and a fast decay (FD) loop. 0 dB and 1.504 dB in 0.094 dB steps. The FA loop also has a counter that is programmable between 1 and 16. When ADC R E initialized to count + 1, the FA loop decreases the gain for T THRUEPSPHEORLD POWER DETECTORDECIMATION FILTERSLINEARIZTION FORMAT cFTsioahgunsent aF tlD D +fea ll1col saco yblpoe (cilFsok Dw ac ) yfa aLc stloeth oslr oepwos hhpeo tnlhd at hdt euin rtcihnrregea sash edosel tdeh pies c gcharaionns nsweedhl .ef and teh oer on RE- the ramp down. The fast loop accomplishes this task by ADC comparing the peak signal-plus-blocker level at the ADC output (which includes the signal and any blockers that pass through MSAATCGAHTCIENE FAST LOOP DETECTORS SISGLNOAWL PLLOUOSP ,B SLIOGNCKALE RL ELVEEVLEL 03683-030 tdheete SrAmWin efisl twerh)e wn itthhi sa lporoopg risa macmtivaabtleed l.e Tvehl e( SSPBBP__lleevveell) d tehfaatu lt Figure 30. AGC Loop Block Diagram Rev. A | Page 23 of 44

AD6650 value is −40 dBFS. When the wideband signal is below the SPB The SDIV for Serial Port 0 and Serial Port 1 can be programmed level, the FD loop is activated. This loop overrides the slow loop via Internal Control Register 0x21. Valid SDIV values are between and has a programmable step size (default 0.094 dB) and a 0 and 7, corresponding to divide ratios between 1 and 8. programmable peak detect period (defaults four samples at Serial Output Frame Timing 1.08 MHz). The SDFS signal transitions high to signal the start of a data UPPER THRESHOLD1 frame. On the next rising edge of SCLK, the port drives the first (OVER LOAD PROTECTION) ~–1dBFS bit of the serial data on the SDO pin. The falling edge of SCLK OPERATIONAL or the subsequent rising edge can then be used by the DSP to RANGE –6dBFS sample the data until the required number of bits is received REQUESTED LEVEL2 (determined by the serial output port word length). If the DSP has the ability to count bits, it can identify when the complete –46dBFS frame is received. LOWER THRESHOLD3 (DEEPFADE PROTECTION) Serial Port Timing Specifications NOTES Figure 32 to Figure 35 indicate the timing required for the 123AAADDDJJJUUUSSSTTTAAABBBLLLEEE LLLEEEVVVEEELLL,,, AWLDOIJTOUHPS PGTRAAOBINGL ER(< AS1M)T, EMHPAY SSBTILZEEER .SETSEIPS ,S IINZTEEAGNRDATAIDOJNU PSETARBIOLDE. PERIOD.03683-031 AD6650 serial port. Figure 31. AGC Thresholds tSCLK SERIAL OUTPUT DATA PORT tSCLKH The AD6650 has two configurable serial output ports (SDO0 SCLK and SDO1). Both ports must be identically configured and are tSCLKL 03683-032 programmed using the same control register. The ports share a Figure 32. SCLK Timing Requirements common SFDS, SCLK, and DR pin for connection to an external ASIC or DSP; therefore, the outputs cannot be CLK programmed independently. tDSCLKH Serial Output Data Format The AD6650 utilizes a twos complement data format with a tSCLKH selectable serial data-word length of 16 bits or 24 bits. The data SCLK is shifted out of the device in MSB-first format. tSCLKL 03683-033 Serial Data Frame Sync Figure 33. SCLK Switching Characteristics (Divide-by-1) The serial data frame sync (SDFS) pin signals the start of the t DSDO serial data frame. As channel data becomes available at the output of the AD6650’s filters, this data is transferred into the SCLK serial data buffer. The internal serial controller initiates the SthDeFreS aorne tthhere nee mxto rdiseisn ign e wdhgeic ohf tthhee fsrearmiael csyloncck c. aInn tbhee AD6650, SDO I15 I14 I13 03683-034 Figure 34. Serial Output Data Switching Characteristics generated, which are described in the SDFS Modes section. Configuring the Serial Ports tDSO SCLK Both serial output ports must function as master serial ports. A serial bus master provides SCLK and SDFS outputs. Serial Port 0 SDFS MINIMUM WIDTH IS ONE SCLK and Serial Port 1 must be programmed as the bus masters by SDFS setting Bit 3 of the serial control register high. STehrei aSCl PLoKr tfr Deqautean Rcya tise d efined by Equation 21. SDO RFISIRINSGT SDCALTAK AISFATVEARI LSADBFLSE G TOHEES F HIRIGSHT IMSB IMSB1 03683-035 Figure 35. Timing for Serial Output Port f f = CLK (21) SCLK SDIV +1 SCLK SCLK is an output on the AD6650. All outputs are switched on where: the rising edge of SCLK. The SDFS pin is sampled on the falling fCLK is the frequency of the master clock of the AD6650 channel. edge of SCLK. This allows the AD6650 to recognize the SDFS in SDIV is the serial division word for the channel. time to initiate a frame on the next SCLK rising edge. The maximum speed of this port is 52 MHz. Rev. A | Page 24 of 44

AD6650 SDO SDO1. In this condition, there are three modes of operation. (There are technically four modes, but Mode 0 and Mode 1 are SDO is the serial data output. Serial output data is shifted on the same). the rising edge of SCLK. On the next SCLK rising edge after an SDFS, the MSB of the I data from the channel is shifted. • Mode 0 and Mode 1 (Address 0x21, Bits[6 :5] = 00; On every subsequent SCLK edge, a new piece of data is shifted Bit[7] = 1): The SDFS is valid for one complete clock cycle out on the SDO pin until the last bit of data is shifted out. The prior to the data shift. This single pulse is valid for Output last bit of data shifted is the LSB of the Q data from the channel. Channel SDO0 and Output Channel SDO1. On the next SDO is three-stated when the serial port is outside its time slot. clock cycle, the AD6650 begins shifting out the digitally This allows the AD6650 to share the SDIN of a DSP with other processed data stream. Depending on the bit precision of AD6650s or other devices. the serial configuration, either 16 bits or 24 bits of I data are shifted out, followed by 16 bits or 24 bits of Q data. SDFS • Mode 2 (Address 0x21, Bits[6:5] = 10; Bit[7] = 1): Because SDFS is the serial data frame sync signal. SDFS is configured as both SDO0 and SDO1 are used, SDFS pulses high one an output. SDFS is sampled on the falling edge of SCLK. When clock cycle prior to I data and also pulses high one clock SBM is sampled high, the chip functions as a serial bus master. cycle prior to Q data for each corresponding input channel. In In this mode, the AD6650 is responsible for generating serial this mode, there are two SFDS pulses per each output channel. control data. Four modes of that operation are set via Channel • Mode 3 (Address 0x21, Bits[6:5] = 11; Bit[7] = 1): The SDFS Address 0x21, Bit 6 to Bit 5. is high while valid bits are being shifted. On SDO0, SDFS Serial Word Length remains high for 16 bits or 24 bits of I data, followed by 16 bits or 24 bits of Q data corresponding to Input Channel A. Bit 4 of Address 0x21 determines the length of the serial word For SDO1, SDFS remains high for 16 bits or 24 bits of I data, (I or Q). If this bit is set to 0, each word is 16 bits wide (16 bits followed by 16 bits or 24 bits of Q data corresponding to for I and 16 bits for Q). If this bit is set to 1, the serial words are Input Channel B. The SDFS bit goes high one complete 24 bits wide. clock cycle before the first bit is shifted out of the AD6650. SDFS Modes As mentioned in the Serial Data Frame Sync section, there are three modes of operation. Setting Bit 7 of Address 0x21 high indicates that Input Channel A data is output on SDO0 and Input Channel B data is output on Rev. A | Page 25 of 44

AD6650 APPLICATION INFORMATION REQUIRED SETTINGS AND START-UP SEQUENCE Overall DC Correction Performance FOR DC CORRECTION With the recommended settings, the dc correction performance On startup, the fine dc correction block may take up to several is approximately −120 dBFS or better for small signals. Once the minutes to converge to a good dc estimate, especially if a large signal is large enough to trip the AGC loop, the dc component signal is present on the input. To improve this convergence also rises; however, this component has been shown to always without run-time trade-offs, use a two-step start-up process. be 40 dBc below the signal of interest. Therefore, the carrier-to- The first step is to configure the fine dc correction block with dc ratio degrades for small signals. For additional details on the the parameters shown in Table 12. The freeze is set so that the dc correction registers, see the associated bit descriptions in the fine dc correction responds after the coarse dc correction has Register Map section. updated. At the same time, the minimum period can be set to a CLOCKING THE AD6650 small value, such as 10. This guarantees a quicker convergence The AD6650 encode signal must be a high quality, low phase because the minimum period is smaller, resulting in a smaller noise source to prevent degradation of performance. The integration period. AD6650 can be clocked with a single-ended signal, but CLK Also, setting the registers as described in Table 12, and must be ac-coupled to ground. For optimum performance, the subsequently programming the AD6650, ensures that the VGA AD6650 must be clocked differentially. The encode signal and mixer are powered down during the power-on calibration should be ac-coupled into the CLK and CLK pins via a to keep signals with large dc content from interfering with the transformer or capacitors. These pins are biased internally and estimation of the dc component from the analog path. require no additional bias. After ~500 ms, the freeze bit (Address 0x0B, Bit 0) can be Figure 36 shows the preferred method for clocking the AD6650. written low. The dc correction then converges and begins The clock source (low jitter) is converted from single-ended to removing the offset. If desired, the minimum period can differential using an RF transformer. The back-to-back Schottky then be set to a larger value. diodes across the secondary transformer limit clock excursions If the VGA and mixer are not disabled during a power-up using the into the AD6650 to approximately 0.8 V p-p differential. This AutoCalibration control register as recommended, approximately helps prevent large voltage swings of the clock from feeding 30 dB of suppression can be achieved, but the user must through to other portions of the AD6650 and limits the noise guarantee that significant content is not present at the IF presented to the encode inputs. frequency that will be translated to dc. If enhanced performance CLOCK T1-4T is desired from the coarse dc correction, an RF switch or other SOURCE CLK 0.1µF device can be used to shut off the input of the AD6650 until the AD6650 correction has been completed. 0.01µF HSMS2812 CLK 03683-036 DIODES Figure 36. Crystal Clock Oscillator—Differential Encode Table 12. DC Correction Register Recommendations Description Channel Address Bit Value AutoCalibration Control Register 0x22 Bit 0 Enabled (1) AutoCalibration Control Register 0x22 Bit 1 Power down DACs at startup (0) AutoCalibration Control Register 0x22 Bit 2 Enabled (1) AutoCalibration Control Register 0x22 Bit 3 Sync ADCs (0) Upper Threshold 0x0B Bit 19 to Bit 13 −48 dBFS Lower Threshold 0x0B Bit 12 to Bit 8 −90 dBFS Minimum Period 0x0B Bit 7 to Bit 3 +10 sample periods Freeze 0x0B Bit 0 Enabled (1) Rev. A | Page 26 of 44

AD6650 Another option is to ac-couple a differential ECL/PECL signal EXTERNAL REFERENCE to the encode input pins as shown in Figure 37. A device that The reference should be connected as shown in Figure 39 to offers excellent jitter performance is the MC100EL16 (or a achieve the results specified in this data sheet. device from the same family) from Motorola. AIN/BIN VT AIN/BIN REFT 0.1µF 0.1µF CLK PEECCLL/ AD6650 RAEMFP CCHHAAANNDNNCEELL AB/ 0.1µF 0.1µF CLK 03683-037 CORE 10µF REFB VT 0.1µF Figure 37. Differential ECL for Encode VREF VREF 0.5V DRIVING THE ANALOG INPUTS 0.1µF 10µF RINT SELECT As with most new high speed, high dynamic range devices, the LOGIC REFGND analog input to the AD6650 is differential. Differential inputs allow much improvement in performance on-chip because signals are processed through attenuation and gain stages. Most of the RINT ihmigphr orevjeemcteionnt ios fa e rveesnu-lot rodf edri fhfaerrmenotinailc asn. Daliofgfe srteangteias lt ihnapt uhtasv aer e 03683-039 Figure 39. Reference Connection also beneficial at the PCB level. First, differential inputs have POWER SUPPLIES high common-mode rejection of stray signals, such as ground and power noise, and good rejection of common-mode signals, Care should be taken when selecting a power source. Linear such as local oscillator feedthrough. supplies are strongly recommended. Switching supplies tend to The AD6650 analog input voltage range is offset from ground have radiated components that may be received by the AD6650. by 1.3 V. The resistor network on the input properly biases the Each of the power supply pins should be decoupled as closely to followers for maximum linearity and range. Therefore, the the package as possible using 0.1 μF chip capacitors. analog source driving the AD6650 should be ac-coupled to the The AD6650 is susceptible to low frequency power supply input pins. The input resistance for the AD6650 is 200 Ω, and interference as shown in Figure 40. This low frequency energy is the input voltage range is 2 V p-p differential. This equates to translated into spurious tones in the output signal. Analog 4 dBm full-scale input power. The recommended method for power supply ripple couples into the LO through the VCO. This driving the analog input of the AD6650 is to use an RF balun. can be observed from the ripple frequency vs. sideband spur C101 C102 level plot (see Figure 40). Note that this plot has the spur level J101 47000pF 47000pF referenced to 1 mV rms supply ripple and is referred to the LO. 5 1 AIN/BIN Thus, this plot shows a transfer function rather than an absolute T101 R101 4 3 C103 68.9Ω value. The spurious level can be extrapolated to any supply 47000pF ripple level from this data using Equation 22. 5 1 AIN/BIN T102 Spur_Lev =Spur_Lev ×20log(SupRipple(mV)) (22) 4 3 03683-038 where: 1mV Figure 38. Balun-Coupled Analog Input Circuit Spur_Lev is the output spurious level relative to the LO. Spur_Lev is the 1 mV referred level from Figure 40 and 1 mV Figure 41. SupRipple (mV) is the RMS ripple on the AVDD power supply. Rev. A | Page 27 of 44

AD6650 –35 DIGITAL OUTPUTS –40 It is recommended that the digital outputs drive a series resistor (for example, 100 Ω). To minimize capacitive loading, the s) –45 m V r number of gates on each output pin should be limited. The m –50 series resistors should be placed as close to the AD6650 as 1 c/ B possible to limit the amount of current that can flow into the EL (d –55 output stage. These switching currents are confined between V LE –60 ground and the DVDD pin. Also, note that excessive capacitive R U loading increases output timing and can invalidate timing P –65 S specifications. ––7705 03683-040 GROUNDING 1 10 100 1000 For optimum performance, it is highly recommended to use a OFFSET FREQUENCY (kHz) split ground between the analog and digital grounds. AGND Figure 40. Output Spurious vs. Power Supply Ripple (AIN = 199 MHz) should be connected to the analog ground of the RF board, and DGND should be connected to the digital ground of the RF board. An additional parameter that strongly impacts the PSRR is the sensitivity to the AVDD voltage level. A plot of spur level versus To minimize the potential for noise coupling, it is highly AVDD is shown below in Figure 41. Note that this plot also has recommended to place multiple ground return traces and vias the spur level referenced to 1mV rms supply ripple and is so that the digital output currents do not flow back toward the referred to the LO. Thus, this plot shows a transfer function analog front end, but instead are routed quickly away from the rather than an absolute value. The spurious level can be AD6650. This can be accomplished by simply placing extrapolated to any supply ripple level from this plot using substantial ground connections directly back to the supply at a Equation 21. point between the analog front end and the digital outputs. –20 Judicious use of ceramic chip capacitors between the power supply and ground planes also helps suppress digital noise. The –23 layout should incorporate enough bulk capacitance to supply –26 s) the peak current requirements during switching periods. m mV r –29 LAYOUT INFORMATION 1 –32 c/ B A multilayer board should be utilized to achieve optimal results. EL (d –35 It is highly recommended to use high quality ceramic chip V –38 LE capacitors to decouple each supply pin to ground directly at the UR –41 device. The pin arrangement of the AD6650 facilitates ease of P S –44 use in the implementation of high frequency, high resolution ––4570 03683-041 dsiedsei gonf tphrea pctaicckeasg. eA flrlo omf tthhee danigailtoagl oinuptuptust fso arr ies oolnat itohne pouprppoossietes . 2.953.003.053.103.153.203.253.303.353.403.453.503.553.60 Care should be taken when routing the digital output traces. To AVDD (V) prevent coupling through the digital outputs into the analog Figure 41. Output Spurious vs. Power Supply Ripple (AIN = 199 MHz) portion of the AD6650, minimal capacitive loading should be The AD6650 has separate digital and analog power supply pins. placed on these outputs. The analog supplies are denoted AVDD, and the digital supply The layout of the encode circuit is equally critical. Any noise pins are denoted DVDD. Although analog and digital supplies received on this circuitry results in corruption in the digitization can be tied together, best performance is achieved when the process and lower overall performance. The encode clock must supplies are separate because the fast digital output swings can be isolated from the digital outputs and the analog inputs. couple switching current back into the analog supplies. Note that AVDD and DVDD must be held between 3.0 V and 3.45 V. Rev. A | Page 28 of 44

AD6650 CHIP SYNCHRONIZATION 3. Write the start holdoff counter(s) (Address 0x14) to the appropriate value (greater than 1 but less than 65,535). The AD6650 is designed to allow synchronization of multiple 4. Program all other registers of the AD6650 that are not AD6650s within a system. The AD6650 is synchronized with already set. either a microprocessor write (Soft_SYNC) or a pulse on the 5. Write the Soft_SYNC bit high (External Memory SYNC pin (Pin_SYNC). The first sync event starts the device, Address 5, Bit 0). and subsequent sync events resynchronize the filters of the 6. When the Soft_SYNC bit goes high, the start holdoff AD6650. By using a start holdoff counter, it is possible to align the counter begins to count down using the AD6650 CLK phase of the AD6650 to other devices. To synchronize the AD6650 signal after the CLK divider. When the start holdoff with external hardware, see the Start with SYNC Pin section. counter reaches a count of 1, the selected channel(s) are Start with Soft_SYNC activated. The AD6650 includes the ability to synchronize channels or Start with SYNC Pin chips under microprocessor control. The start holdoff counter (Address 0x14), in conjunction with the SYNC bit (External The AD6650 has a SYNC pin that can be used to provide Memory Address 5, Bit 0), allows this synchronization. The synchronization between AD6650 devices and external start holdoff counter delays the start and synchronization of a hardware to a resolution of 1 ADC sample cycle. This can be channel(s) by its value (number of AD6650 CLKs). accomplished by providing a 1-CLK-cycle-wide pulse on the SYNC pin when the edge-sensitive bit of the SF1 register is low Use the following method to synchronize the start of a channel (External Memory Address 4, Bit 4), which is useful when an via microprocessor control: FPGA or other external hardware is operating at the CLK rate of 1. Set the appropriate channels to sleep mode. A hard reset to the AD6650. Synchronization can also be accomplished by the AD6650 (RESET taken low) puts both channels into setting the edge-sensitive bit high so that the SYNC input is sleep mode. rising-edge sensitive, which is useful when the external 2. Enable Channel A and/or Channel B (External Memory hardware is operating off a clock that is much slower than the Address 3, Bit 0). AD6650 or is asynchronous to it. Rev. A | Page 29 of 44

AD6650 MICROPORT CONTROL The AD6650 has an 8-bit microprocessor port. The microport ACCESS CONTROL REGISTER (ACR) interface is a multimode interface that allows flexibility when Bit 7 of the ACR register is the auto-increment bit. If this bit is set to dealing with the host processor. 1, the CAR register, described in the Channel Address Register There are two modes of bus operation: Intel® nonmultiplexed (CAR) section, increments in value after every access to the mode (INM) and Motorola nonmultiplexed mode (MNM). The channel. This allows blocks of address space, such as coefficient mode is selected based on the host processor and which mode memory, to be initialized more efficiently. is best suited for that processor. The microport has an 8-bit data Bit 6 of the ACR register is unused and must be written low. bus (D[7:0]), 3-bit address bus (A[2:0]), three control pin lines (CS, DS or RD, and R/W or WR), and one status pin (DTACK Bit 5 to Bit 2 of the ACR register are instruction bits that allow or RDY). The functionality of the control signals and status line multiple AD6650s to receive the same write access. The instruction changes slightly depending on the selected mode. Refer to the bits allow a single or multiple (up to four) AD6650 chip(s) to be timing diagrams in Figure 10 through Figure 13 and the configured simultaneously. There are seven possible instructions descriptions in the Programming Modes, Intel Nonmultiplexed that are defined in Table 14, where x represents disregarded Mode (INM), and Motorola Nonmultiplexed Mode (MNM) values in the digital decoding. sections for details on the operation of each mode. If multiple AD6650 chips are using the same CS line, readback EXTERNAL MEMORY MAP is not valid because of the potential for bus contention. Therefore, if device readback capability is desired, the CS lines should be The external memory map is used to gain access to the channel separated for individual control. To facilitate device debug and address space. The 8-bit data and address buses are used to set verification, the use of separate CS lines for each AD6650 is the eight registers shown in Table 13. These registers are recommended. collectively referred to as the external interface registers because they control all access to the channel address space and global Bit 1 to Bit 0 of the ACR register are address bits that decode which chip functions. The use of each register is described in Table 13. channel is to be accessed. Because the channels of the AD6650 cannot be programmed independently, these bits should be set Table 13. External Memory Map to 0. Addr. (Hex) Mnemonic Bit No. Description CHANNEL ADDRESS REGISTER (CAR) 7 Access Control Register 7 Auto-increment (ACR) The CAR register represents the 8-bit internal address of each 6 Reserved (write low) channel. If the auto-increment bit of the ACR is 1, this value is 5 to 2 Instruction [3:0] incremented after every access to the DR0 register, which in 1 to 0 A[9:8] turn accesses the location pointed to by this address. 6 Channel Address Register 7 to 0 A[7:0] SPECIAL FUNCTION REGISTERS (CAR) 5 Special Function Register 2 6 AGC sync enable The AD6650 has three special function registers, SF0, SF1, and (SF2) SF2, that control synchronizing and enabling of the channels. SF0 5 DC correction controls channel enabling, SF1 controls Pin_SYNC, and SF2 sync enable 4 PN sync enable controls Soft_SYNC. For SF0, Bit 0 and Bit 2 allow Channel A 3 to 1 Reserved and Channel B, respectively, to exit sleep mode by the method 0 Issue Soft_SYNC selected in SF1. Bit 1 and Bit 3 are read-only bits and indicate 4 Special Function Register 1 5 First sync only whether Channel A and Channel B, respectively, are active. A 1 (SF1) indicates that the channel is active, and a 0 indicates that it is 4 Enable edge- sensitivity not active. Bits 4 through Bit 7 are unused. 3 to 1 Reserved 0 Enable Pin_SYNC For SF1, if Bit 0 is set to 1, both channels wait for a pulse to 3 Special Function Register 0 7 to 4 Reserved appear on the SYNC pin before exiting sleep mode; otherwise, (SF0) the channels assume a soft start is desired and wait for the start 3 Status of Channel B holdoff counter to issue a sync. When Bit 5 is set, both channels 2 Enable Channel B ignore all subsequent attempts to resync once they have exited 1 Status of Channel A sleep mode. 0 Enable Channel A 2 Data Register 2 (DR2) 7 to 4 Reserved 3 to 0 D[19:16] 1 Data Register 1 (DR1) 15 to 8 D[15:8] 0 Data Register 0 (DR0) 7 to 0 D[7:0] Rev. A | Page 30 of 44

AD6650 READ/WRITE CHAINING Table 14. Microport Instructions Instruction Description The microport of the AD6650 allows multiple accesses while CS 0xxx All chips obtain access. is held low (CS can be tied permanently low if the microport is 1000 All chips with Chip_ID [1:0] = x0 obtain access.1 not shared with additional devices). The user can access 1001 All chips with Chip_ID [1:0] = x1 obtain access.1 multiple locations by pulsing the WR or RD line and changing 1100 All chips with Chip_ID [1:0] = 00 obtain access.1 the contents of the external 3-bit address bus. Access to the 1101 All chips with Chip_ID [1:0] = 01 obtain access.1 external registers listed in Table 13 is accomplished in one of 1110 All chips with Chip_ID [1:0] = 10 obtain access.1 two modes using the CS, RD, WR, and MODE inputs. The 1111 All chips with Chip_ID [1:0] = 11 obtain access.1 access modes are INM mode and MNM mode. These modes are controlled by the MODE input (MODE = 0 for INM, 1 Bits A[9:8] control which channel is decoded for the access. MODE = 1 for MNM). CS, RD, and WR control the access type For SF2, Bit 0 prompts the startup block to run the start hold- for each mode. off counter from the value programmed in the start holdoff counter control register and to issue a sync when this task is PROGRAMMING MODES complete. Bit 4 to Bit 6 are used to enable syncs to individual The AD6650 can be programmed using several different modes. blocks in the channels. These modes include two microport modes, INM mode and DATA ADDRESS REGISTERS MNM mode. The programming mode is selected by setting the MODE pins. Table 15 identifies how to set the MODE pins to External Addresses [2:0] form Data Register DR2, Data Register select the desired programming mode. DR1, and Data Register DR0, respectively. All internal data- words have widths that are less than or equal to 22 bits. Access Table 15. Programming Modes to DR0 triggers an internal access to the AD6650 based on the MODE [2:0] Description address indicated in ACR and CAR. Therefore, during writes to 000 Microport Intel nonmultiplexed mode the internal registers, DR0 must be written last. At this point, 001 Microport Motorola nonmultiplexed mode data is transferred to the internal memory location indicated in 010 Reserved A[9:0]. Reads are performed in the reverse sequence. Once the 011 Reserved address is set, DR0 must be the first data register read to initiate 100 Reserved an internal access. DR2 is only six bits wide. Data written to the 101 Reserved upper two bits of this register is ignored. Likewise, reading from 110 Reserved this register produces only 6 LSBs. 111 Reserved WRITE SEQUENCING Writing to an internal location is achieved by first writing the Intel Nonmultiplexed Mode (INM) upper two bits of the address into Bit 1 and Bit 0 of the ACR Setting the mode word bits to 000 places the AD6650 in INM (these bits should be set low). Bits[5:2] can be set to select the mode. The access is controlled by the user with the CS, RD (DS), chips for access as indicated above. The CAR is then written and WR (R/W) inputs. The RDY (DTACK) signal is produced with the lower eight bits of the internal address (it does not by the microport to communicate to the user that an access has matter if the CAR is written to before the ACR, as long as both been completed. RDY (DTACK) goes low at the start of the access are written to before the internal access). DR2 and DR1 must be and is released when the internal cycle is complete. See Figure 10 written first because the write to Data Register DR0 triggers the and Figure 11 for INM mode read and write timing. internal access. DR0 must always be the last register written to Motorola Nonmultiplexed Mode (MNM) initiate the internal write. READ SEQUENCING Setting the mode word bits to 001 places the AD6650 in MNM mode. The access type is controlled by the user with the CS, DS Reading from the microport is accomplished in the same (RD), and R/W (WR) inputs. The DTACK (RDY) signal is manner. The internal address is set up the same way as it is for a generated by the microport to signal the user that an access has write. A read from DR0 activates the internal read; therefore, been completed. DTACK (RDY) goes low when an internal access DR0 must be read first to initiate an internal read followed by is complete and returns high after DS (RD) is deasserted. See reads from DR1 and DR2. Figure 12 and Figure 13 for MNM mode read and write timing. Rev. A | Page 31 of 44

AD6650 JTAG BOUNDARY SCAN Bypass (2'b11) The AD6650 supports a subset of the IEEE Standard 1149.1 The bypass instruction allows the IC to remain in normal specification. For details of the standard, see the IEEE Standard functional mode and selects a 1-bit bypass register between TDI Test Access Port and Boundary-Scan Architecture, an IEEE-1149 and TDO. During this instruction, serial data is transferred publication. from TDI to TDO without affecting operation of the IC. The AD6650 has five pins associated with the JTAG interface. Sample/Preload (2'b01) These pins, listed in Table 16, are used to access the on-chip test The sample/preload instruction allows the IC to remain in access port. All input JTAG pins are pull-ups except TCLK, normal functional mode and selects the boundary scan register which is a pull-down. to be connected between TDI and TDO. The boundary scan register can be accessed by a scan operation to take a sample of Table 16. Boundary Scan Test Pins the functional data entering and leaving the IC. Also, test data Mnemonic Description can be preloaded into the boundary-scan register before an TRST Test access port reset extest instruction. TCLK Test clock Extest (2'b00) TMS Test access port mode select TDI Test data input The extest instruction places the IC into an external boundary- TDO Test data output test mode and selects which boundary scan register is connected between TDI and TDO. During this operation, the boundary The AD6650 supports three op codes, listed in Table 17. These scan register is accessed to drive test data off-chip via boundary instructions set the mode of the JTAG interface. outputs and receive test data off-chip from boundary inputs. Table 17. Boundary Scan Op Codes Instruction Op Code Bypass 11 Sample/Preload 01 Extest 00 A boundary scan description language (BSDL) file for this device is available. Contact an Analog Devices sales representative for more information. Rev. A | Page 32 of 44

AD6650 REGISTER MAP Table 18. Memory Map Reg. Bit (Hex) Mnemonic Width Description Additional Information Code Result 0 Clock Divider Control 1 Power-up value is 1’b1. 0 Bypass 1 Divide-by-2 1 PLL Register 0 22 PLL Control Register 0. See Table 19 2 PLL Register 1 22 PLL Control Register 1. See Table 20 3 PLL Register 2 22 PLL Control Register 2. See Table 21 4 PLL Register 3 22 PLL Control Register 3. See Table 22 5 Clamp Control 6 Various VGA control signals. Power-up value is 6’b100011 Code Gain (dB) 5 to 2: Tweak Gain 4 Provides ±1.6 dB of additional gain in VGA in 0 +1.6 dB 0.2 dB steps. 1 +1.4 dB 2 +1.2 dB . . . . 7 +0.2 dB 8 0 dB 9 −0.2 dB . . . . 14 −1.2 dB 15 −1.4 dB Code Result 1: Clamp Disable B 1 Disables clamps at the output of the VGA for 0 Enable clamp Channel B. 1 Disable clamp 0: Clamp Disable A 1 Disables clamps at the output of the VGA for 0 Enable clamp Channel A. 1 Disable clamp 6 Reserved 8 Reserved. Must be written 8’b00000000 7 Reserved 8 Reserved. Must be written 8’b00000000 8 Reserved 8 Reserved. Must be written 8’b00010001 9 Reserved 2 Must be written 0. Power-up value is 2’b00 A Coarse DC Correction 4 Coarse dc correction control registers. Power-up value is 4’b0000 Code Result 3: Cal Now B 1 Calibrate coarse dc correction for the 0 Disabled Channel B. Coarse dc correction occurs 1 Recalibrate automatically at start-up if Bit 0 of the AutoCalibration control register is set high. 2: Cal Now A 1 Calibrate coarse dc correction for the 0 Disabled Channel A. Coarse dc correction occurs 1 Recalibrate automatically at start-up if Bit 0 of the AutoCalibration control register is set high. 1: PN_EN 1 Enables the PN sequence generator to test 0 Disabled the digital block. 1 Enable PN sequence generator Code Result 0: Coarse DCC Enable 1 Enables coarse DCC. This register must be 0 Disabled held high during start-up sequence for 1 DCC enabled coarse dc correction to occur. Rev. A | Page 33 of 44

AD6650 Reg. Bit (Hex) Mnemonic Width Description Additional Information B DC Correction Control 20 Fine DCC control registers. Power-up value is 20’b00000000000000000000 Code Level (dBFS) 19 to 13: Upper 7 Fine DCC upper threshold. No new dc 0 0 dBFS Threshold estimation is made if the signal is above the 1 −0.75 dBFS upper threshold. 2 −1.5 dBFS . . . . 126 −94.5 dBFS 127 −95.25 dBFS 12 to 8: Lower Threshold 5 Fine DCC lower threshold. The maximum 0 0 dBFS range for the lower limit is 0 dBFS to 138.46 dBFS. 1 −6.02 dBFS 2 −12.04 dBFS . . . . 22 −132.44 dBFS 23 −138.46 dBFS Integration Code Time 7 to 3: Minimum Period 5 Fine DCC integration period. 1 21 × T S 2 22 × T S 3 23 × T S . . . . 30 230 × T S 31 231 × T S T = sample S period Code Result 2: Bypass 1 Fine DCC bypass. 0 Update DCC estimate 1 Keep old estimate 1: Interpolate 1 Fine DCC interpolator reduces discontinuity 0 Disabled between the current dc estimate and the 1 Enabled new estimate. 0: Freeze 1 Fine DCC freeze is used to hold the current 0 Disabled dc estimate. 1 Enabled C AGC Control 0 4 AGC Control Settings. Code Result 3: Force VGA Gain 1 Force the VGA gain to a specific value. This 0 Disabled control line overrides the slow loop, fast 1 Enable forced decay loop, and fast attack loop when gain mode enabled. 2: FD_Enable 1 Fast decay loop enable. 0 Disabled 1 Enable fast decay loop Code Result 1: FA_Enable 1 Fast attack loop enable. 0 Disabled 1 Enable fast attack loop 0: Reserved 1 Reserved. N/A Rev. A | Page 34 of 44

AD6650 Reg. Bit (Hex) Mnemonic Width Description Additional Information D AGC Control 1 9 VGA gain (dB) = (0.094) × VGA gain word. Code Gain (dB) 8 to 0: VGA Gain This drives the VGA directly when force VGA 0 0 dB gain = 1. 1 0.094 dB 2 0.188 dB . . . . 382 35.9 dB 383 36.002 dB E AGC Control 2 16 AGC hysteresis and requested level. Code Hysteresis (dB) 15 to 8: Hysteresis 8 Upper hysteresis threshold = requested level 0 0 + hysteresis. 1 ±.094 dB Lower hysteresis threshold = requested level 2 ±.188 dB − hysteresis. . . The gain word does not change if the peak . . measurement falls between the upper and 254 ±23.876 dB lower hysteresis threshold. 255 ±23.97 dB Requested Code Level (dBm) 7 to 0: Requested Level 8 The requested level for the slow loop. The 0 +4 dBm full-scale input into the AD6650 is 1 +3.906 dBm 2 V p-p = 4 dBm. 2 +3.812 dBm . . . . 254 −19.8 dBm 255 −19.97 dBm F AGC Control 3 11 Loop gain = (mantissa/256) × ½exponent. Code Loop Gain Exp 10 to 8: Loop Gain 3 Loop gain exponent (slow loop). 0 20 Exponent 1 21 . . . . 6 26 7 27 7 to 6: Reserved 2 Reserved. N/A Code Mantissa 5 to 0: Loop Gain 6 Loop gain mantissa (slow loop). 0 0 Mantissa 1 1 2 2 . . . . 62 62 63 63 Rev. A | Page 35 of 44

AD6650 Reg. Bit (Hex) Mnemonic Width Description Additional Information 10 AGC Control 4 13 Fast attack and fast decay loop parameters. Code Step size (dB) 12 to 10: FD_Step 3 Fast decay step size. 0 0 dB 1 0.094 dB 2 0.188 dB . . . . 6 0.564 dB 7 0.658 dB Code Threshold 9 to 8: FA_Thresh 2 Fast attack threshold measured at the 0 −6.02 dBFS antialiasing filters. 1 −3.1 dBFS 2 −0.915 dBFS 3 0 dBFS Code Count 7 to 4: FA_Count 4 Fast attack count. The fast attack loop steps 0 1 the gain down by FA_Step for FA_Count 1 2 number of clock cycles. 2 3 . . . . 14 14 15 15 Code Step size (dB) 3 to 0: FA_Step 4 Fast attack step size. 0 0 dB 1 0.094 dB 2 0.188 dB . . . . 14 1.316 dB 15 1.41 dB 11 AGC Control 5 16 Slow loop peak detector period. Samples (f S Code clock cycles) 15 to 8: SPB Peak 8 Signal plus blocker peak detector period for 0 0 Detector Period the slow loop; fS = 26 MHz; fSYM =270.833 kHz; 1 1 SPB peak period = ¼ × (f /f ). SAMP SYM 2 2 . . . . 254 254 255 255 7 to 0: Reserved 8 Reserved. Must be written 8’b00000000 12 Reserved 7 Reserved. Must be written 7’b0000000 13 AGC Control 7 Code Threshold 8 to 0: FD SPB Threshold Fast decay signal plus blocker threshold. 0 0 dBFS 1 −0.094 dBFS 2 −0.188 dBFS . . . . 510 −47.94 dBFS 511 −48.034 dBFS Rev. A | Page 36 of 44

AD6650 Reg. Bit (Hex) Mnemonic Width Description Additional Information Code Count 14 Start Holdoff Counter 16 The power-up sequence is initiated with a 1 1 Soft_SYNC or Pin_SYNC and then the start 2 2 holdoff counter counts down to 1, and the . . chip power-up sequence starts. 0 is an . . invalid value. 65,534 65,534 65,535 65,535 Code Decimation 15 CIC4 Decimation (M − 1) 5 Should be ≥12 because CIC and IIR have 7 8 CIC4 maximum rates of 26 MHz/12. 8 9 9 10 . . . . 30 31 31 32 Code Scale Factor 16 CIC4 Scale (Scale − 12) 4 Controls the attenuation of the data into the 0 12 CIC4 stage in 6 dB increments. This register 1 13 has a range of 12 to 20, which supports decimations from 8 to 32 according to Equation 4. 2 14 . . . . 7 19 8 20 Code Results 17 IIR Control 1 Sync mask. 0 Disabled 1 Enabled Code Decimation 18 RCF Decimation Register 3 Decimation of 1 to 8. 0 1 (MRCF − 1) 1 2 2 3 . . . . 6 7 7 8 Code Phase 19 RCF Decimation Phase 3 Phase from 0 to M − 1. 0 0 RCF (PRCF) 1 1 . . . . 6 6 7 7 Code Offset 1A RCF Coefficient Offset 6 Range is 0 to 48 taps. 0 0 (CORCF) 1 1 2 2 . . . . 46 46 47 47 Rev. A | Page 37 of 44

AD6650 Reg. Bit (Hex) Mnemonic Width Description Additional Information Code Taps 1B RCF Taps (N − 1) 6 1 to 48. 0 1 Taps 1 2 . . . . 46 47 47 48 Code Scale Factor 1C RCF Scale 2 0, −6 dB, −12 dB, and −18 dB gain adjust to 0 −18 dB prevent coefficients from clipping the MAC. 1 −12 dB 2 −6 dB 3 0 dB 1D BIST for A-I 24 16-bit data available, I/DATA_I. 1E BIST for A-Q 24 16-bit data available, Q/DATA_Q. 1F BIST for B-I 24 16-bit data available, I/DATA_I. 20 BIST for B-Q 24 16-bit data available, Q/DATA_Q. 21 Serial Control 9 Power-up value is 9’bxxxxx0xxx for Bit 3 to make it a serial slave. 8: Fine DCC Data to BIST 1 Data is available through the I/Q BIST registers when Bit 8 is high. Code Results 7: B Data Serial Ouput 1 Port B data serial output select. 0 Use SDO0 for Select B data 1 Use SDO1 for B data 6 to 5: I_SDFS Control 2 Serial port control functions. 0 AI pulse 1 AI, BI pulses 2 AI, AQ, BI, BQ pulses 3 High for SDO0 valid 4: SOWL 1 Serial output word length. 0 16-bit words 1 24-bit words 3: SBM 1 Serial bus master. 0 Serial slave 1 Serial bus master 2 to 0: SDIV [2:0] 3 Serial divider. 0 Divide-by-1 . . . . 7 Divide-by-8 22 AutoCalibration Control 4 New calibration sequence control registers. Power-up value is 4’b0000. 3: Reserved 1 Reserved. Must be written 0 2: Reserved 1 Reserved. Must be written 1 Code Results 1: DAC Power-Down 1 Power down VGA DACs during the power-up 0 Power down Disable sequence to calibrate the dc offset. DACs 1 DACs on 0: Enable 1 Autocalibration enable. 0 Disabled 1 Enabled 23 to Reserved 3F 40 to Coefficient Memory Common coefficients for Channel A and 48 × 20 bit RAM 6F Channel B. 70 to Reserved FF Rev. A | Page 38 of 44

AD6650 REGISTER DETAILS Table 19. PLL Register 0: Control Latch CH Address Register Description Comment DB21 to DB0 RSVD Reserved Must be written 00 0000 0111 1100 0100 0000 (MSB ... LSB). Table 20. PLL Register 1: R Counter Latch CH Address Register Description Comment DB21 to DB14 RSVD Reserved Must be written 0001 0100 (DB21 ... DB14). DB13 to DB0 R1 to R14 14-bit reference counter, R Table 21. PLL Register 2: N Counter Latch CH Address Register Description Comment DB21 to DB19 RSVD Reserved Must be written 000. DB18 to DB6 B13 to B1 13-bit B counter B13 to B1 programs the 13-bit B counter. DB5 RSVD Reserved Must be written 0. DB4 to DB0 A5-A1 5-bit A counter A5 to A1 programs the 5-bit counter. The divide range is 0 (00000) to 31 (11111). Table 22. PLL Register 3—Reserved CH Address Register Bit Definitions Comment DB21 to DB0 RSVD Reserved Must be written 11 0001 1000 0000 0000 0000 (MSB ... LSB). 0x00: Clock Divider Control [1] 0x05: Clamp Control [5:0] The clock divider control bit sets the internal clock rate for the This register either enables or disables the clamps on the output AD6650. If this bit is set low and the clock rate is ≤52 MSPS, the of the mixers. These clamps should be enabled. internal divide-by-2 is bypassed. If a faster clock rate is desired, 0x06: Reserved [8:0] the clock divider control bit should be set high. By setting this This register is reserved and must be written 00000000. bit high, the internal divide-by-2 is used. 0x07: Reserved [8:0] 0x01: PLL Control Register 0 [21:0] This register is reserved and must be written 00000000. This register is reserved and must be written 00 0000 0111 1100 0100 0000 (MSB ... LSB). 0x08: Reserved [8:0] 0x02: PLL Control Register 1 [21:0] This register is reserved and must be written 00010001. DB13 to DB0: These bits are used to set the R-counter for the PLL. 0x09: Reserved [1:0] DB21 to DB14: These bits are reserved and must be written This register is reserved and should be written low. 0001 0100. 0x03: PLL Control Register 2 [21:0] DB4 to DB0: This 5-bit register is used to set the value for the A counter in the PLL. DB5: This bit is reserved and must be written to 0. DB18 to DB6: This 13-bit register is used to set the value for the B-counter in the PLL. DB21 to DB19: These bits are reserved and must be written 000. 0x04: PLL Control Register 3 [21:0] This register is reserved and must be written 11 0001 1000 0000 0000 0000 (MSB ... LSB). Rev. A | Page 39 of 44

AD6650 0x0A: Coarse DC Correction Control Register [3:0] the peak detectors in the fine dc correction block ranges off the dc content as well as the signal of interest. Address 0xA is the coarse dc correction control register. It is used to enable the coarse correction with Bit 0 and to initiate Bit 12 to Bit 8 calibrations on Channel A and/or Channel B. Bit 3 and Bit 2 of The lower threshold determines where the minimum integration this register can be used to initiate coarse calibrations when the period is used. When the peak of the input to the fine dc device is running and can be used in conjunction with an correction block is lower than this level, the accumulators external switch if desired. Bit 1 is used to activate the internal average 2Min_period samples at the output rate (1 or 2 samples/symbol). pseudorandom noise generator, which is useful for looking at When the peak of the signal increases above this, the integration the digital filter response and performing the built-in self-test. periods increase by a factor of 4 for every 6 dB that the signal Table 23. Coarse DC Correction Control Functions power increases. Bit No. Description It should be noted that any dc content left after the coarse 3 Calibrate B correction can be seen by the fine dc correction peak detector 2 Calibrate A and causes the integration period to change. For example, if the 1 PN_EN lower threshold is −96 dBFS and the dc content is −78 dBFS, the 0 CDCC enable signal is at least 18 dB larger; therefore, the integration period is at least 64× (that is, 418/6) the minimum period. 0xB: Fine DC Correction Filter [19:0] The lower threshold can be set near the upper threshold to The fine dc correction block is used to provide a good dc provide a constant integration period of 2Min_period if desired. correction for small signals that are under the range of the AGC loop. Address 0xB has four parameters. Bit 7 to Bit 3 This interval is equal to 2Min_period. The minimum period Table 24. Fine DC Correction Filter Functions determines the integration period when the peak signal power Bits Description into the fine dc correction block is less than the lower threshold. 19 to 13 Upper threshold This can be used in combination with the lower threshold to 12 to 8 Lower threshold make sure there is enough integration to estimate the dc for 7 to 3 Minimum period small signals. 2 Bypass 1 Interpolator enable If Min_period is 12, the period of integration for a signal with 0 Freeze power less than or equal to −96.32 dBFS is 4096 samples. For each 6.02 dBFS increase in the signal power, the integration Bit 19 to Bit 13 period quadruples. The Min_period register can be programmed The upper threshold disables the fine dc correction algorithm for from 1 to 31; 0 is not a valid value for this register. large input signals that could potentially contain significant dc Bit 2 content from the modulated data. This should be set below the This is the bypass bit that effectively shuts down the fine dc range of the AGC loop, which is equal to the requested level of correction block. When this bit is 1, no correction is performed. −36 dB. It should also be set above the uncorrected dc level so that the fine DCC is guaranteed to range. Bit 1 The upper threshold should be set low enough so that the dc This bit enables an interpolator that can smooth out the content is not estimated while the loop is ranging because the updated estimate transition by a fixed interpolation by 256. This changing gain distorts the estimate. Setting the upper threshold is a linear interpolator that allows the correction block to gradually lower also decreases effects from dc content in the signal such shift between the old estimate and the new estimate to avoid as dc offset from modulated data with high correlations or transients if there has been significant dc shift. If disabled, the mobiles with LO feedthrough. shift in correction values happens instantaneously, causing a It is equally important not to set the upper threshold too low. discontinuity in the signal; however, if the interpolator is enabled, If the upper threshold is set so low that the desired signal is this shift occurs over 256 samples, preventing any large consistently higher than this threshold, a new dc estimate, which discontinuities. The interpolator should not be enabled if is necessary to compensate for power supply or temperature Min_period is set to less than 8 (a period of 256 samples). Use drifts, will not occur. Therefore, a thorough understanding of of the interpolator is not recommended at this time, and this bit the signal statistics for the application is required. should be set to 0. As a guideline, the upper threshold should be set between Bit 0 −40 dBFS and −70 dBFS. If it is set below −72 dBFS, the When set to 1, this bit freezes the estimate of the dc correction uncorrected dc offset from the analog front end and coarse and resets the peak detector to the smallest possible signal state correction can increase the effective minimum period because (−138 dB peak signal). This way, the dc can be estimated once Rev. A | Page 40 of 44

AD6650 and constantly corrected. This is useful for debugging and for Bit 7 to Bit 0 use when the dc estimate can be performed at discrete These lower eight bits set the requested level for the AGC slow predefined times. loop. Setting the code to 0 sets the requested level to +4 dBm, Even though the upper threshold register can vary between 0 which corresponds to the full-scale input of the AD6650. and 15 and the Min_period register can vary between 1 and 31, Setting the code to 255 sets the requested level to −19.97 dBm. only certain combinations of the two are valid. This is because 0x0F: AGC Control 3 [10:0] the growth is restricted to 34 bits. Equation 23 can be used to Bit 10 to Bit 8 determine if a combination of values is valid. If C < 0, the combination is invalid; otherwise, the combination is valid. This 3-bit register sets the loop gain exponent for the slow loop of the AD6650 AGC. The values can range C = 34 − (2 × (16 − Upper Threshold) + Min_period) (23) from 0 to 7. The equation for the loop gain is noted in the AGC 0x0C: AGC Control 0 [3:0] Loop/Relinearization section. Bit 3 Bit 7 to Bit 6 The force VGA gain control register allows the user to force the These two bits are reserved and should be written low. VGA gain to a specific value. This control line overrides the slow loop, fast decay loop, and fast attack loop when enabled. By setting Bit 5 to Bit 0 this bit low, the force VGA gain control is disabled. By setting This 6-bit register represents the loop gain mantissa for the slow this bit high, the force VGA gain control is enabled. For normal loop of the AD6650 AGC. The values for this register range from 0 operation, this bit should be disabled. to 63. The equation for the loop gain is noted in the AGC Bit 2 Loop/Relinearization section. 0x10: AGC Control 4 [12:0] By setting this bit high, the fast decay loop is enabled; by setting this bit low, the fast decay loop is disabled. It is recommended Bit 12 to Bit 10 that the fast decay loop be enabled for normal operation. For a This 3-bit register is used to set the fast decay step size. The gain description of the fast decay functionality, see the AGC continues to increase until it has reached the fast decay Loop/Relinearization section. threshold or until the maximum gain has been reached. Bit 1 Bit 9 to Bit 8 By setting this bit high, the fast attack loop is enabled; by setting This 2-bit register sets the threshold for the fast attack AGC this bit low, the fast attack loop is disabled. It is recommended loop. When the desired signal reaches this threshold, the gain is that the fast decay loop be enabled for normal operation. For a reduced by the FA_Step for FA_Count number of clock cycles. description of the fast attack functionality, see the AGC Bit 7 to Bit 4 Loop/Relinearization section. The fast attack loop steps the gain down by FA_Step for Bit 0 FA_Count number of clock cycles. This bit is reserved and should be written low. Bit 3 to Bit 0 0x0D: AGC Control 1 [8:0] The FA_Step register determines how large a step to take once If the force VGA bit is enabled in AGC Control Register 0 the fast attack threshold has been reached. This value is (Bit 3 = 1), this register controls the gain setting for the VGA. expressed in decibels. The gain is controlled in 0.094 dB steps with a maximum gain 0x11: AGC Control 5 [15:0] of 36 dB. Code 0 corresponds to 0 dB gain or minimum gain, whereas Code 383 corresponds to 36 dB gain or maximum gain. Bit 15 to Bit 8 0x0E: AGC Control 2 [15:0] This 8-bit register sets the signal plus blocker peak detector period for the AGC slow loop. It can be set from 0 to 255 samples. The AGC Control 2 register is a 16-bit register that sets the amount of hysteresis used in the AGC loop and sets the Bit 7 to Bit 0 requested level for the AGC loop. Reserved and must be written 00000000. Bit 15 to Bit 8 0x12: Reserved [6:0] These upper bits set the hysteresis level in 0.094 dB steps. Code 0 This register is reserved and must be written 0000000. corresponds to 0 dB of hysteresis, and Code 255 corresponds to 0x13: AGC Control 7 [8:0] ±23.97 dB of hysteresis. This 9-bit register is used to set the threshold for the fast decay signal plus blocker. Values can range from 0 dBFS to −48 dBFS. Rev. A | Page 41 of 44

AD6650 The peak detector for this threshold monitors the desired signal 0x1B: RCF Taps Minus One (N − 1) [5:0] TAPS and blocker peaks at the ADC output. The number of taps for the RCF filter minus one is written to 0x14: Start Holdoff Counter [15:0] this register. The start holdoff counter is loaded with the value written to this 0x1C: RCF Scale Register [1:0] address when a sync is initiated. It can be initiated by either a This 2-bit register represents the output scale factor of the RCF. Soft_SYNC or Pin_SYNC. The counter begins decrementing, This register is used to scale the output data between 0 dB and and when it reaches a value of 1, the channel exits sleep mode −18 dB in 6 dB steps. and begins processing data. If this register is written 1, the start 0x1D to 0x20: BIST Register [23:0] occurs immediately when the SYNC comes into the channel. If it is written 0, no SYNC occurs. These four registers allow the complete digital functionality of the I and Q data path in the A and B channels to be tested in the 0x15: CIC4 Decimation Minus One (M − 1) [4:0] CIC4 system. See the User-Configurable Built-In Self-Test (BIST) This register is used to set the decimation in the CIC4 filter. The section for more details. value written to this register is the decimation minus one. The 0x21: Serial Control Register [8:0] value of this register should be 12 or greater because the CIC and IIR have maximum rates of 26 MHz/12. Although this is a This register controls the serial port of the AD6650 and 5-bit register, the decimation is usually limited to between 12 determines the output format. and 32. Decimations higher than 32 require more scaling than Bit 8 the CIC4’s capability. Fine DCC data to BIST. 0x16: CIC4 Scale [3:0] Bit 7 The CIC4 scale factor is used to compensate for the growth of If this bit is enabled (set high), Channel B data is output on the CIC4 filter. See the Fourth-Order Cascaded Integrator Serial Data Output 1 (SDO1). Comb Filter (CIC4) section for details. Bit 6 to Bit 5 0x17: IIR Control Register [1] Address 0x17 is the IIR control register. When this bit is set to 0, Choose the serial data frame sync (SDFS) mode. See the Serial the sync mask is disabled. In this mode, after a SYNC is issued Data Frame Sync section for a full description of each mode. The to the AD6650, the IIR data path is not cleared. If the sync mask following bits select the corresponding mode. is enabled, the bit is set to 1, and the data path is cleared of its Table 25. Serial Port Control Functions contents and starts accumulating new data on the first valid Bits Description clock after a Soft_SYNC or Pin_SYNC is issued. 11 High for SDO0 valid 0x18: RCF Decimation Register Minus One (M − 1) [2:0] RCF 10 AI, AQ, BI, BQ pulses This register is used to set the decimation of the RCF stage. The 01 AI, BI pulses value written is the decimation minus one. This is a 3-bit 00 AI pulse register that allows decimations up to 8. Bit 4 0x19: RCF Decimation Phase (P ) [2:0] RCF By setting this bit low, the output data stream is 16-bit I and 16-bit This register allows any one of the MRCF phases of the filter to Q data-words for both the A and B channels. By setting this bit be used and can be adjusted dynamically. Each time a filter is high, the output data stream is 24-bit I and 24-bit Q data words started, this phase is updated. When a channel is synchronized, for both the A and B chan nels. To fully realize the dynamic range it retains the phase setting selected. This can be used as part of a of the AD6650, it is recommended that the 24-bit mode be used. timing recovery loop with an external processor or can allow Bit 3 multiple RCFs to work together while using a single RCF pair. See the RAM Coefficient Filter section for more details. By setting this bit high, the AD6650 becomes the serial bus master. It is recommended that this bit be enabled (set high). 0x1A: RCF Coefficient Offset (CO ) [5:0] RCF Bit 2 to Bit 0 This register is used to specify which section of the 256-word coefficient memory is used for a filter. It can be used to select This 3-bit register controls the divider on the serial clock among multiple filters that are loaded into memory and (SCLK) on the output of the AD6650. It is possible to divide the referenced by this pointer. This register is shadowed and the SCLK by 8, allowing a flexible interface to a DSP or FPGA. filter pointer is updated every time a new filter is started. This allows the coefficient offset to be written even while a filter is being computed without disturbing operation. The next sample that comes out of the RCF will be with the new filter. Rev. A | Page 42 of 44

AD6650 0x22: Autocalibration Register [3:0] Bit 0 Address 0x22 is the autocalibration register and controls the Enables the autocalibration. This should be set to 1 for automatic coarse dc autocalibration at start-up. the calibration to run automatically. Then the AD6650 waits Bit 3 approximately 20.63 ms after a Soft_SYNC or Pin_SYNC enables the part and then runs a coarse dc calibration. This Reserved. This bit should be set to 0. allows some warm-up time for the analog path to thermally Bit 2 stabilize. Reserved. This bit should be set to 1. 0x23 to 0x3F: Reserved Bit 1 These registers must not be written. Determines whether to power down the VGA and mixer on a 0x40 to 0x6F: Coefficient Memory coarse calibration. This should be set to 0 to allow the state This memory is utilized to store up to forty-eight 20-bit RCF machine to power down the VGA and mixer. If it is known that coefficients shared by Channel A and Channel B. there is no dc input into the part, this can be set to 1 to improve 0x70 to 0xFF: Reserved the correction performance, which allows more flexibility in setting the lower threshold. These registers must not be written. Rev. A | Page 43 of 44

AD6650 OUTLINE DIMENSIONS 12.20 A1 CORNER INDEX AREA 12.00 SQ 11.80 1110 9 8 7 6 5 4 3 2 1 A B BALL A1 C CORNER D 10.00 E BSC SQ F G H 1.00 BSC J K L TOP VIEW BOTTOM VIEW *1.85 DETAIL A *1.31 1.71 DETAIL A 1.21 1.40 1.11 0.50 NOM 0.30 MIN 0.70 0.20 COPLANARITY 0.60 SEATING PLANE 0.50 BALL DIAMETER *CEOXCMEPPLTIAIONNT TWOIT PHA JCEKDAEGCE S HTEAINGDHATR ADNSD M TOH-I1C9K2N-AEBSDS-.1 WITH 082406-A Figure 42. 121-Lead Chip Scale Package Ball Grid Array [CSP_BGA] (BC-121) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range1 Package Description Package Option AD6650ABC −25°C to +85°C 121-Lead Chip Scale Package Ball Grid Array [CSP_BGA] BC-121 AD6650ABCZ2 −25°C to +85°C 121-Lead Chip Scale Package Ball Grid Array [CSP_BGA] BC-121 AD6650BBC −25°C to +85°C 121-Lead Chip Scale Package Ball Grid Array [CSP_BGA] BC-121 AD6650BBCZ2 −25°C to +85°C 121-Lead Chip Scale Package Ball Grid Array [CSP_BGA] BC-121 AD6650/PCB Evaluation Board with AD6650 and Software 1 The AD6650 is guaranteed fully functional from −40°C to +85°C. All ac minimum specifications are guaranteed from −25°C to +85°C, but degrade slightly from −25°C to −40°C. 2 Z = Pb-free part. ©2006–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03683-0-1/07(A) Rev. A | Page 44 of 44