Complete Quad, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC Data Sheet AD5764R FEATURES GENERAL DESCRIPTION Complete quad, 16-bit digital-to-analog converter (DAC) The AD5764R is a quad, 16-bit, serial input, bipolar voltage output Programmable output range: ±10 V, ±10.2564 V, or ±10.5263 V DAC that operates from supply voltages of ±11.4 V to ±16.5 V. ±1 LSB maximum INL error, ±1 LSB maximum DNL error Nominal full-scale output range is ±10 V. The AD5764R provides Low noise: 60 nV/√Hz integrated output amplifiers, reference buffers, and proprietary Settling time: 10 μs maximum power-up/power-down control circuitry. The part also features Integrated reference buffers a digital I/O port, programmed via the serial interface, and an Internal reference: 10 ppm/°C maximum analog temperature sensor. The part incorporates digital offset On-chip die temperature sensor and gain adjust registers per channel. Output control during power-up/brownout The AD5764R is a high performance converter that provides Programmable short-circuit protection guaranteed monotonicity, integral nonlinearity (INL) of ±1 LSB, Simultaneous updating via LDAC low noise, and 10 μs settling time. The AD5764R includes an Asynchronous CLR to zero code on-chip 5 V reference with a reference temperature coefficient Digital offset and gain adjust of 10 ppm/°C maximum. During power-up when the supply Logic output control pins voltages are changing, VOUTx is clamped to 0 V via a low DSP-/microcontroller-compatible serial interface impedance path. Temperature range: −40°C to +85°C iCMOS process technology The AD5764R is based on the iCMOS® technology platform, which is designed for analog systems designers within industrial/ APPLICATIONS instrumentation equipment OEMs who need high performance Industrial automation ICs at higher voltage levels. iCMOS enables the development of Open-loop/closed-loop servo control analog ICs capable of 30 V and operation at ±15 V supplies, while Process control allowing reductions in power consumption and package size, Data acquisition systems coupled with increased ac and dc performance. Automatic test equipment The AD5764R uses a serial interface that operates at clock rates Automotive test and measurement of up to 30 MHz and is compatible with DSP and microcontroller High accuracy instrumentation interface standards. Double buffering allows the simultaneous updating of all DACs. The input coding is programmable to either twos complement or offset binary formats. The asynchronous clear function clears all data registers to either bipolar zero or zero scale, depending on the coding used. The AD5764R is ideal for both closed-loop servo control and open-loop control applications. The AD5764R is available in a 32-lead TQFP and offers guaranteed specifications over the −40°C to +85°C industrial temperature range (see Figure 1 for the functional block diagram). Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2008–2011 Analog Devices, Inc. All rights reserved.

AD5764R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Function Register ....................................................................... 24 Applications ....................................................................................... 1 Data Register ............................................................................... 25 General Description ......................................................................... 1 Coarse Gain Register ................................................................. 25 Revision History ............................................................................... 2 Fine Gain Register ...................................................................... 25 Functional Block Diagram .............................................................. 3 Offset Register ............................................................................ 26 Specifications ..................................................................................... 4 Offset and Gain Adjustment Worked Example ...................... 26 AC Performance Characteristics ................................................ 6 Design Features ............................................................................... 27 Timing Characteristics ................................................................ 7 Analog Output Control ............................................................. 27 Absolute Maximum Ratings .......................................................... 10 Digital Offset and Gain Control ............................................... 27 Thermal Resistance .................................................................... 10 Programmable Short-Circuit Protection ................................ 27 ESD Caution ................................................................................ 10 Digital I/O Port ........................................................................... 27 Pin Configuration and Function Descriptions ........................... 11 Die Temperature Sensor ............................................................ 27 Typical Performance Characteristics ........................................... 13 Local Ground Offset Adjust ...................................................... 27 Terminology .................................................................................... 19 Applications Information .............................................................. 28 Theory of Operation ...................................................................... 21 Typical Operating Circuit ......................................................... 28 DAC Architecture ....................................................................... 21 Layout Guidelines ........................................................................... 30 Reference Buffers ........................................................................ 21 Galvanically Isolated Interface ................................................. 30 Serial Interface ............................................................................ 21 Microprocessor Interfacing ....................................................... 30 Simultaneous Updating via LDAC ........................................... 22 Evaluation Board ........................................................................ 31 Transfer Function ....................................................................... 23 Outline Dimensions ....................................................................... 32 Asynchronous Clear (CLR) ....................................................... 23 Ordering Guide .......................................................................... 32 Registers ........................................................................................... 24 REVISION HISTORY 10/11—Rev. C to Rev. D 2/09—Rev. 0 to Rev. A Changed 50 MHz to 30 MHz ....................................... Throughout Changes to Table 1 Test Conditions/Comments and Changes to t, t, and t Parameters, Table 3 .................................. 7 Added Endnote to Table 1 ................................................................ 4 1 2 3 Added Endnote to Table 2 ................................................................ 6 7/11—Rev. B to Rev. C Added Endnote to Table 3 ................................................................ 7 Changed 30 MHz to 50 MHz Throughout.................................... 1 Changes to t, t, and t Parameters, Table 3 .................................. 7 10/08—Revision 0: Initial Version 1 2 3 8/09—Rev. A to Rev. B Deleted Endnote 1 in Table 1 .......................................................... 4 Deleted Endnote 1 in Table 2 .......................................................... 6 Deleted Endnote 1 and Changes t Parameter in Table 3 ............ 7 6 Changes to Ordering Guide .......................................................... 32 Rev. D | Page 2 of 32

Data Sheet AD5764R FUNCTIONAL BLOCK DIAGRAM PGND AVDD AVSS AVDD AVSS REFOUT REFGND REFAB RSTOUT RSTIN VOLTAGE DVCC MONITOR AD5764R 5V REFERENCE AND DGND REFERENCE BUFFERS CONTROL ISCC 16 16 G1 INPUT DATA SDIN INPUT REG A REG A DAC A VOUTA SHIFT G2 SCLK REGISTER AND GAIN REG A SYNC CONTROL OFFSET REG A AGNDA LOGIC SDO 16 G1 INPUT DATA REG B REG B DAC B VOUTB G2 GAIN REG B OFFSET REG B AGNDB D0 16 G1 INPUT DATA D1 REG C REG C DAC C VOUTC G2 GAIN REG C OFFSET REG C AGNDC BIN/2sCOMP 16 G1 INPUT DATA REG D REG D DAC D VOUTD G2 GAIN REG D CLR AGNDD OFFSET REG D REFERENCE TEMP BUFFERS SENSOR LDAC REFCD TEMP 06064-001 Figure 1. Rev. D | Page 3 of 32

AD5764R Data Sheet SPECIFICATIONS AV = 11.4 V to 16.5 V, AV = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V external; DD SS DV = 2.7 V to 5.25 V, R = 10 kΩ, C = 200 pF. All specifications T to T , unless otherwise noted. CC LOAD L MIN MAX Table 1. Parameter B Grade1 C Grade1 Unit Test Conditions/Comments ACCURACY Outputs unloaded Resolution 16 16 Bits Relative Accuracy (INL) ±2 ±1 LSB max Differential Nonlinearity (DNL) ±1 ±1 LSB max Guaranteed monotonic Bipolar Zero Error ±2 ±2 mV max 25°C; error at other temperatures obtained using bipolar zero tempco ±3 ±3 mV max Bipolar Zero Tempco2 ±2 ±2 ppm FSR/°C max Zero-Scale Error ±2 ±2 mV max 25°C; error at other temperatures obtained using zero-scale tempco ±2.5 ±2.5 mV max Zero-Scale Tempco2 ±2 ±2 ppm FSR/°C max Gain Error ±0.02 ±0.02 % FSR max Gain Tempco2 ±2 ±2 ppm FSR/°C max DC Crosstalk2 0.5 0.5 LSB max REFERENCE INPUT/OUTPUT Reference Input2 Reference Input Voltage 5 5 V nominal ±1% for specified performance DC Input Impedance 1 1 MΩ min Typically 100 MΩ Input Current ±10 ±10 µA max Typically ±30 nA Reference Range 1/7 1/7 V min/V max Reference Output Output Voltage 4.995/5.005 4.995/5.005 V min/V max At 25°C, AV /AV = ±13.5 V DD SS Reference Tempco2 ±10 ±10 ppm/°C max Typically 1.7ppm/°C R 2 1 1 MΩ min LOAD Power Supply Sensitivity2 300 300 µV/V typ Output Noise2 18 18 µV p-p typ 0.1 Hz to 10 Hz Noise Spectral Density2 75 75 nV/√Hz typ At 10 kHz Output Voltage Drift vs. Time2 ±40 ±40 ppm/500 hr typ ±50 ±50 ppm/1000 hr typ Thermal Hysteresis2 70 70 ppm typ First temperature cycle 30 30 ppm typ Subsequent temperature cycles OUTPUT CHARACTERISTICS2 Output Voltage Range3 ±10.5263 ±10.5263 V min/V max AV /AV = ±11.4 V, V = 5 V DD SS REFIN ±14 ±14 V min/V max AV /AV = ±16.5 V, V = 7 V DD SS REFIN Output Voltage Drift vs. Time ±13 ±13 ppm FSR/500 hr typ ±15 ±15 ppm FSR/1000 hr typ Short-Circuit Current 10 10 mA typ R = 6 kΩ, see Figure 31 ISCC Load Current ±1 ±1 mA max For specified performance Capacitive Load Stability R = ∞ 200 200 pF max LOAD R = 10 kΩ 1000 1000 pF max LOAD DC Output Impedance 0.3 0.3 Ω max Rev. D | Page 4 of 32

Data Sheet AD5764R Parameter B Grade1 C Grade1 Unit Test Conditions/Comments DIGITAL INPUTS2 DV = 2.7 V to 5.25 V CC Input High Voltage, V 2.4 2.4 V min IH Input Low Voltage, V 0.8 0.8 V max IL Input Current ±1.2 ±1.2 µA max Per pin Pin Capacitance 10 10 pF max Per pin DIGITAL OUTPUTS (D0, D1, SDO)2 Output Low Voltage 0.4 0.4 V max DV = 5 V ± 5%, sinking 200 µA CC Output High Voltage DV − 1 DV − 1 V min DV = 5 V ± 5%, sourcing 200 µA CC CC CC Output Low Voltage 0.4 0.4 V max DV = 2.7 V to 3.6 V, CC sinking 200 µA Output High Voltage DV − 0.5 DV − 0.5 V min DV = 2.7 V to 3.6 V, CC CC CC sourcing 200 µA High Impedance Leakage Current ±1 ±1 µA max SDO only High Impedance Output Capacitance 5 5 pF typ SDO only DIE TEMPERATURE SENSOR2 Output Voltage at 25°C 1.47 1.47 V typ Die temperature Output Voltage Scale Factor 5 5 mV/°C typ Output Voltage Range 1.175/1.9 1.175/1.9 V min/V max −40°C to +105°C Output Load Current 200 200 µA max Current source only Power-On Time 10 10 ms typ POWER REQUIREMENTS AV /AV 11.4/16.5 11.4/16.5 V min/V max DD SS DV 2.7/5.25 2.7/5.25 V min/V max CC Power Supply Sensitivity2 ∆V /∆ΑV −85 −85 dB typ OUT DD AI 3.55 3.55 mA/channel max Outputs unloaded DD AI 2.8 2.8 mA/channel max Outputs unloaded SS DI 1.2 1.2 mA max V = DV , V = DGND, 750 µA typ CC IH CC IL Power Dissipation 275 275 mW typ ±12 V operation output unloaded 1 Temperature range: −40°C to +85°C; typical at +25°C. Device functionality is guaranteed to +105°C with degraded performance. 2 Guaranteed by design and characterization; not production tested. 3 Output amplifier headroom requirement is 1.4 V minimum. Rev. D | Page 5 of 32

AD5764R Data Sheet AC PERFORMANCE CHARACTERISTICS AV = 11.4 V to 16.5 V, AV = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V external; DD SS DV = 2.7 V to 5.25 V, R = 10 kΩ, C = 200 pF. All specifications T to T , unless otherwise noted. CC LOAD L MIN MAX Table 2. Parameter B Grade C Grade Unit Test Conditions/Comments DYNAMIC PERFORMANCE1 Output Voltage Settling Time 8 8 µs typ Full-scale step to ±1 LSB 10 10 µs max 2 2 µs typ 512 LSB step settling Slew Rate 5 5 V/µs typ Digital-to-Analog Glitch Energy 8 8 nV-sec typ Glitch Impulse Peak Amplitude 25 25 mV max Channel-to-Channel Isolation 80 80 dB typ DAC-to-DAC Crosstalk 8 8 nV-sec typ Digital Crosstalk 2 2 nV-sec typ Digital Feedthrough 2 2 nV-sec typ Effect of input bus activity on DAC outputs Output Noise (0.1 Hz to 10 Hz) 0.1 0.1 LSB p-p typ Output Noise (0.1 Hz to 100 kHz) 45 45 µV rms max 1/f Corner Frequency 1 1 kHz typ Output Noise Spectral Density 60 60 nV/√Hz typ Measured at 10 kHz Complete System Output Noise Spectral Density2 80 80 nV/√Hz typ Measured at 10 kHz 1 Guaranteed by design and characterization; not production tested. 2 Includes noise contributions from integrated reference buffers, a 16-bit DAC, and an output amplifier. Rev. D | Page 6 of 32

Data Sheet AD5764R TIMING CHARACTERISTICS AV = 11.4 V to 16.5 V, AV = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V external; DD SS DV = 2.7 V to 5.25 V, R = 10 kΩ, C = 200 pF. All specifications T to T , unless otherwise noted. CC LOAD L MIN MAX Table 3. Parameter1, 2, 3 Limit at T , T Unit Description MIN MAX t 33 ns min SCLK cycle time 1 t 13 ns min SCLK high time 2 t 13 ns min SCLK low time 3 t 13 ns min SYNC falling edge to SCLK falling edge setup time 4 t 4 13 ns min 24th SCLK falling edge to SYNC rising edge 5 t 90 ns min Minimum SYNC high time 6 t 2 ns min Data setup time 7 t 5 ns min Data hold time 8 t 1.7 µs min SYNC rising edge to LDAC falling edge (all DACs updated) 9 480 ns min SYNC rising edge to LDAC falling edge (single DAC updated) t 10 ns min LDAC pulse width low 10 t 500 ns max LDAC falling edge to DAC output response time 11 t 10 µs max DAC output settling time 12 t 10 ns min CLR pulse width low 13 t 2 µs max CLR pulse activation time 14 t 5, 6 25 ns max SCLK rising edge to SDO valid 15 t 13 ns min SYNC rising edge to SCLK falling edge 16 t 2 µs max SYNC rising edge to DAC output response time (LDAC = 0) 17 t 170 ns min LDAC falling edge to SYNC rising edge 18 1 Guaranteed by design and characterization; not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, and Figure 4. 4 Standalone mode only. 5 Measured with the load circuit of Figure 5. 6 Daisy-chain mode only. Rev. D | Page 7 of 32

AD5764R Data Sheet Timing Diagrams t1 SCLK 1 2 24 t6 t3 t2 t4 t5 SYNC t8 t7 SDIN DB23 DB0 t10 t10 t9 LDAC t18 t12 t11 VOUTx LDAC = 0 t12 t17 VOUTx CLR t13 t14 VOUTx 06064-002 Figure 2. Serial Interface Timing Diagram t1 SCLK 24 48 t6 t3 t2 t5 t16 t4 SYNC t8 t7 SDIN DB23 DB0 DB23 DB0 INPUT WORD FOR DAC N INPUT WORD FOR DAC N – 1 t15 SDO DB23 DB0 UNDEFINED INPUT WORD FOR DAC N t9 t10 LDAC 06064-003 Figure 3. Daisy-Chain Timing Diagram Rev. D | Page 8 of 32

Data Sheet AD5764R SCLK 24 48 SYNC SDIN DB23 DB0 DB23 DB0 INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ SDO DB23 DB0 UNDEFINED SELECCTLEOD CRKEEGDIS OTUETR DATA 06064-004 Figure 4. Readback Timing Diagram 200µA IOL TO OUTPUT VOH (MIN) OR PIN CL VOL (MAX) 50pF 200µA IOH 06064-005 Figure 5. Load Circuit for SDO Timing Diagram Rev. D | Page 9 of 32

AD5764R Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Transient currents of up to Stresses above those listed under Absolute Maximum Ratings A 100 mA do not cause SCR latch-up. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Table 4. other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute AV to AGND, DGND −0.3 V to +17 V DD maximum rating conditions for extended periods may affect AV to AGND, DGND +0.3 V to −17 V SS device reliability. DV to DGND −0.3 V to +7 V CC THERMAL RESISTANCE Digital Inputs to DGND −0.3 V to (DV + 0.3 V) or +7 V, CC whichever is less θ is specified for the worst-case conditions, that is, a device JA Digital Outputs to DGND −0.3 V to DVCC + 0.3 V soldered in a circuit board for surface-mount packages. REFAB, REFCD to AGND, PGND −0.3 V to AV + 0.3 V DD REFOUT to AGND AV to AV Table 5. Thermal Resistance SS DD TEMP AVSS to AVDD Package Type θJA θJC Unit VOUTx to AGND AV to AV 32-Lead TQFP 65 12 °C/W SS DD AGND to DGND −0.3 V to +0.3 V Operating Temperature Range ESD CAUTION Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature (T max) 150°C J Lead Temperature (Soldering) JEDEC industry standard J-STD-020 Rev. D | Page 10 of 32

Data Sheet AD5764R PIN CONFIGURATION AND FUNCTION DESCRIPTIONS P M BIN/2sCO AVDDAVSS TEMP REFGND REFOUT REFCD REFAB 32 31 30 29 28 27 26 25 SYNC 1 24 AGNDA SCLK 2 PIN 1 23 VOUTA SDIN 3 AD5764R 22 VOUTB SDO 4 21 AGNDB TOP VIEW CLR 5 (Not to Scale) 20 AGNDC LDAC 6 19 VOUTC D0 7 18 VOUTD D1 8 17 AGNDD 9 10 11 12 13 14 15 16 T N D C D D S C RSTOU RSTI DGN DVC AVD PGN AVS ISC 06064-006 Figure 6. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 SYNC Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in on the falling edge of SCLK. 2 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This operates at clock speeds of up to 30 MHz. 3 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK. 4 SDO Serial Data Output. This pin is used to clock data from the serial register in daisy-chain or readback mode. 5 CLR Negative Edge Triggered Input.1 Asserting this pin sets the data registers to 0x0000. 6 LDAC Load DAC. This logic input is used to update the data registers and, consequently, the analog outputs. When tied permanently low, the addressed data register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the DAC input register is updated but the output update is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. The LDAC pin must not be left unconnected. 7, 8 D0, D1 Digital I/O Port. D0 and D1 form a digital I/O port. The user can set up these pins as inputs or outputs that are configurable and readable over the serial interface. When configured as inputs, these pins have weak internal pull-ups to DV . When programmed as outputs, D0 and D1 are referenced by DV and DGND. CC CC 9 RSTOUT Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. If desired, it can be used to control other system components. 10 RSTIN Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to this input clamps the DAC outputs to 0 V. In normal operation, RSTIN should be tied to Logic 1. Register values remain unchanged. 11 DGND Digital Ground Pin. 12 DV Digital Supply Pin. Voltage ranges from 2.7 V to 5.25 V. CC 13, 31 AV Positive Analog Supply Pins. Voltage ranges from 11.4 V to 16.5 V. DD 14 PGND Ground Reference Point for Analog Circuitry. 15, 30 AV Negative Analog Supply Pins. Voltage ranges from –11.4 V to –16.5 V. SS 16 ISCC This pin is used in association with an optional external resistor to AGND to program the short-circuit current of the output amplifiers. Refer to the Design Features section for more information. 17 AGNDD Ground Reference Pin for DAC D Output Amplifier. 18 VOUTD Analog Output Voltage of DAC D. Buffered output with a nominal full-scale output range of ±10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load. 19 VOUTC Analog Output Voltage of DAC C. Buffered output with a nominal full-scale output range of ±10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load. 20 AGNDC Ground Reference Pin for DAC C Output Amplifier. 21 AGNDB Ground Reference Pin for DAC B Output Amplifier. Rev. D | Page 11 of 32

AD5764R Data Sheet Pin No. Mnemonic Description 22 VOUTB Analog Output Voltage of DAC B. Buffered output with a nominal full-scale output range of ±10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load. 23 VOUTA Analog Output Voltage of DAC A. Buffered output with a nominal full-scale output range of ±10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load. 24 AGNDA Ground Reference Pin for DAC A Output Amplifier. 25 REFAB External Reference Voltage Input for Channel A and Channel B. The reference input range is 1 V to 7 V, and it programs the full-scale output voltage. V = 5 V for specified performance. REFIN 26 REFCD External Reference Voltage Input for Channel C and Channel D. The reference input range is 1 V to 7 V, and it programs the full-scale output voltage. V = 5 V for specified performance. REFIN 27 REFOUT Reference Output. This is the reference output from the internal voltage reference. The internal reference is 5 V ± 3 mV at 25°C, with a reference temperature coefficient of 10 ppm/°C. 28 REFGND Reference Ground Return for the Reference Generator and Buffers. 29 TEMP This pin provides an output voltage proportional to temperature. The output voltage is 1.47 V typical at 25°C die temperature; variation with temperature is 5 mV/°C. 32 BIN/2sCOMP This pin determines the DAC coding. This pin should be hardwired to either DV or DGND. When hardwired to CC DV , input coding is offset binary (see Table 7). When hardwired to DGND, input coding is twos complement CC (see Table 8). 1 Internal pull-up device on this logic input. Therefore, it can be left floating; and it defaults to a logic high condition. Rev. D | Page 12 of 32

Data Sheet AD5764R TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 TA = 25°C TA = 25°C 0.8 VDD/VSS = ±15V 0.8 VDD/VSS = ±12V VREFIN = 5V VREFIN = 5V 0.6 0.6 0.4 0.4 B) B) R (LS 0.2 R (LS 0.2 RO 0 RO 0 R R NL E –0.2 NL E –0.2 I –0.4 D –0.4 –0.6 –0.6 –0.8 –0.8 –1.00 10,000 20,000 3D0A,0C0 0COD4E0,000 50,000 60,000 06064-007 –1.00 10,000 20,000 3D0A,0C0 0COD4E0,000 50,000 60,000 06064-012 Figure 7. Integral Nonlinearity Error vs. DAC Code, Figure 10. Differential Nonlinearity Error vs. DAC Code, VDD/VSS = ±15 V VDD/VSS = ±12 V 1.0 0.5 TA = 25°C TA = 25°C 0.8 VDD/VSS = ±12V VDD/VSS = ±15V VREFIN = 5V 0.4 VREFIN = 5V 0.6 0.4 0.3 B) B) R (LS 0.2 R (LS 0.2 O 0 O R R L ER –0.2 L ER 0.1 N N I –0.4 I 0 –0.6 –0.1 –0.8 –1.00 10,000 20,000 3D0A,0C0 0COD4E0,000 50,000 60,000 06064-008 –0.2–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 06064-015 Figure 8. Integral Nonlinearity Error vs. DAC Code, Figure 11. Integral Nonlinearity Error vs. Temperature, VDD/VSS = ±12 V VDD/VSS = ±15 V 1.0 0.5 0.8 VTVADR DE=F/ VI2NS5 S=°C =5 V±15V 0.4 TVVADR DE=F/ VI2NS5 S=°C =5 V±12V 0.6 0.4 B) B) 0.3 R (LS 0.2 R (LS RO 0 RO 0.2 R R DNL E ––00..42 INL E 0.1 –0.6 0 –0.8 –1.00 10,000 20,000 3D0A,0C0 0COD4E0,000 50,000 60,000 06064-011 –0.1–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 06064-016 Figure 9. Differential Nonlinearity Error vs. DAC Code, Figure 12. Integral Nonlinearity Error vs. Temperature, VDD/VSS = ±15 V VDD/VSS = ±12 V Rev. D | Page 13 of 32

AD5764R Data Sheet 0.15 0.15 TA = 25°C 0.10 0.10 VREFIN = 5V 0.05 0.05 B) B) S 0 S 0 L L R ( R ( RO–0.05 RO–0.05 R R E E NL –0.10 NL –0.10 D D –0.15 –0.15 –0.20 VTAD D=/ V2S5S°C = ±15V –0.20 VREFIN = 5V –0.25–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 06064-019 –0.2511.4 12.4 SU1P3P.4LY VOLTA14G.4E (V) 15.4 16.4 06064-025 Figure 13. Differential Nonlinearity Error vs. Temperature, Figure 16. Differential Nonlinearity Error vs. Supply Voltage VDD/VSS = ±15 V 0.15 0.8 TA = 25°C 0.10 0.6 0.4 0.05 B) B) 0.2 R (LS 0 R (LS 0 RO–0.05 RO R R –0.2 DNL E–0.10 INL E –0.4 –0.15 –0.6 –0.20 VTAD D=/ V2S5S°C = ±12V –0.8 VREFIN = 5V –0.25–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 06064-020 –1.01 2 RE3FERENCE 4VOLTAGE5 (V) 6 7 06064-027 Figure 14. Differential Nonlinearity Error vs. Temperature, Figure 17. Integral Nonlinearity Error vs. Reference Voltage, VDD/VSS = ±12 V VDD/VSS = ±16.5 V 0.5 0.4 TA = 25°C TA = 25°C 0.4 VREFIN = 5V 0.3 0.2 0.3 B) B) R (LS 0.2 R (LS 0.1 RO RO 0 NL ER 0.1 NL ER –0.1 I D 0 –0.2 –0.1 –0.3 –0.211.4 12.4 SU1P3P.4LY VOLTA14G.4E (V) 15.4 16.4 06064-023 –0.41 2 RE3FERENCE 4VOLTAGE5 (V) 6 7 06064-031 Figure 15. Integral Nonlinearity Error vs. Supply Voltage Figure 18. Differential Nonlinearity Error vs. Reference Voltage, VDD/VSS = ±16.5 V Rev. D | Page 14 of 32

Data Sheet AD5764R 0.6 0.8 TA = 25°C VREFIN = 5V 0.4 VDD/VSS = ±15V 0.2 0.6 V) 0 m R ( 0.4 –0.2 O UE (mV) ––00..64 ERO ERR 0.2 VDD/VSS = ±12V T Z –0.8 LAR 0 O –1.0 P BI –1.2 –0.2 –1.4 –1.61 2 RE3FERENCE 4VOLTAGE5 (V) 6 7 06064-073 –0.4–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 06064-039 Figure 19. Total Unadjusted Error vs. Reference Voltage, Figure 22. Bipolar Zero Error vs. Temperature VDD/VSS = ±16.5 V 14 1.4 TA = 25°C VREFIN = 5V VREFIN = 5V 1.2 13 12 |IDD| V) 1.0 VDD/VSS = ±12V A) m 0.8 T (m OR ( N 11 R 0.6 E R R E CUR AIN 0.4 10 G VDD/VSS = ±15V |ISS| 0.2 9 0 811.4 12.4 13.4VDD/VSS (1V4).4 15.4 16.4 06064-037 –0.2–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 06064-040 Figure 20. IDD/ISS vs. VDD/VSS Figure 23. Gain Error vs. Temperature 0.25 0.0014 VREFIN = 5V VDD/VSS = ±15V TA = 25°C 0.20 0.0013 0.15 5V mV) 0.10 VDD/VSS = ±12V 0.0012 R ( ERRO 0.05 mA)0.0011 CALE –0.050 DI (CC0.0010 S 0.0009 O- R–0.10 ZE 0.0008 –0.15 3V 0.0007 –0.20 –0.25–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 06064-038 0.00060 0.5 1.0 1.5 2.0VLO2G.I5C (V)3.0 3.5 4.0 4.5 5.0 06064-041 Figure 21. Zero-Scale Error vs. Temperature Figure 24. DICC vs. Logic Input Voltage Rev. D | Page 15 of 32

AD5764R Data Sheet 7000 –4 TA = 25°C VREFIN = 5V –6 6000 V) VDD/VSS = ±15V –8 TA (µ 5000 VDD/VSS = ±12V –10 EL 4000 –12 GE D mV) –14 OLTA 3000 V (OUT –16 T V 2000 –18 U UTP 1000 –20 VDD/VSS = ±12V, O –22 VREFIN = 5V, 0 TA = 25°C, –24 0x8000 TO 0x7FFF, 500ns/DIV –1000–10 –5SOURCE/SIN0K CURRENT (5mA) 10 06064-042 –26–2.0–1.5–1.0–0.5 0 0.51.01T.5IM2E.0 (µ2s.)53.03.54.04.55.05.56.0 06064-047 Figure 25. Source and Sink Capability of Output Amplifier with Figure 28. Major Code Transition Glitch Energy, VDD/VSS = ±12 V Positive Full Scale Loaded 10,000 9000 VTAR E=F I2N5 =°C 5V VMVDRIDDEFS/VICNS AS=L =0E V± L1O5VADED µV) 8000 VDD/VSS = ±15V A ( 7000 T EL 6000 AGE D 5000 VDD/VSS = ±12V 4 LT 4000 O T V 3000 U TP 2000 U O 1000 –10000–12 –7 SOURCE/–S2INK CURREN3T (mA) 8 06064-043 CH4 50.0µV M1.00s 50µVC/DHI4V 26µV 06064-048 Figure 26. Source and Sink Capability of Output Amplifier with Figure 29. Peak-to-Peak Noise (100 kHz Bandwidth) Negative Full Scale Loaded VTAD D=/ V2S5S°C = ±15V T VVRDRADEMF/VPINS TS=I M=5 VE±, 1 =T2 AV1 0,=0 µ2s5,°C, VREFIN = 5V LOAD = 200pF||10kΩ 1 2 3 1 CH1 3.00V M1.00µs 1CµHs/1D I V –120mV 06064-044 CCHH13 1100..00VmVBWBWCH2 10.0V MT 1 2090.µ6s0%A CH1 7.80mV 06064-055 Figure 27. Full-Scale Settling Time Figure 30. VOUTx vs. VDD/VSS on Power-Up Rev. D | Page 16 of 32

Data Sheet AD5764R 10 9 VTAD D=/ V2S5S°C = ±15V VTAD D=/ V2S5S°C = ±12V VREFIN = 5V A) 8 m T ( 7 N E RR 6 U T C 5 1 UI RC 4 CI T- 3 R O SH 2 100 20 40 RISC6C0 (kΩ) 80 100 120 06064-050 M1.00s 5AµV C/DHI1V 18mV 06064-053 Figure 31. Short-Circuit Current vs. RISCC Figure 34. REFOUT Output Noise 0.1 Hz to 10 Hz T VTAD D=/ V2S5S°C = ±12V 6 VTAD D=/ V2S5S°C = ±15V V) 5 E ( G A T 1 L 4 O 2 V T U TP 3 U O E NC 2 E R E F RE 1 3 CCHH13 150.0.00VVBBWW CH2 10.0V MT 4 2090.µ6s0%A CH1 7.80mV 06064-054 00 20 40 60LOA80D CU1R0R0EN1T2 (0µA)140 160 180 200 06064-032 Figure 32. REFOUT Turn-On Transient Figure 35. REFOUT Load Regulation 1.9 1VT0ADµ D=F/ V 2CS5AS°C P=,A ±C1I2TVOR ON REFOUT V) 1.8 VTAD D=/ V2S5S°C = ±15V E ( G 1.7 A T L O 1.6 V T PU 1.5 1 UT E O 1.4 R U T 1.3 A R PE 1.2 M E T 1.1 CH1 50.0µV M1.00s 50AµV C/DHI1V 15µV 06064-052 1.0–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 06064-033 Figure 33. REFOUT Output Noise 100 kHz Bandwidth Figure 36. Temperature Output Voltage vs. Temperature Rev. D | Page 17 of 32

AD5764R Data Sheet 5.003 40 20 DEVICES SHOWN MAX: 10ppm/°C TYP: 1.7ppm/°C 35 V)5.002 E ( G 30 A T TPUT VOL55..000001 ATION (%) 2205 U L O U NCE 4.999 POP 15 E ER 10 F RE4.998 5 4.997–40 –20 0 TEM2P0ERATU4R0E(°C)60 80 100 06064-070 0 0.5 1.5 2.5TEM3P.5ERA4T.U5RE 5D.5RIFT6 (.p5pm/7°C.5) 8.5 9.5 06064-072 Figure 37. Reference Output Voltage vs. Temperature Figure 38. Reference Output Temperature Drift (−40°C to +85°C) Rev. D | Page 18 of 32

Data Sheet AD5764R TERMINOLOGY Total Unadjusted Error (TUE) Relative Accuracy or Integral Nonlinearity (INL) A measure of the output error, considering all the various For the DAC, a measure of the maximum deviation, in LSBs, errors. Figure 19 shows a plot of total unadjusted error vs. from a straight line passing through the endpoints of the DAC reference voltage. transfer function. Zero-Scale Error Temperature Coefficient Differential Nonlinearity (DNL) A measure of the change in zero-scale error with a change in The difference between the measured change and the ideal 1 LSB temperature. It is expressed as parts per million of full-scale change between any two adjacent codes. A specified differential range per degree Celsius (ppm FSR/°C). nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic. Gain Error Temperature Coefficient A measure of the change in gain error with changes in tempera- Monotonicity ture. It is expressed as parts per million of full-scale range per A DAC is monotonic if the output either increases or remains degree Celsius (ppm FSR/°C). constant for increasing digital input code. The AD5744R is monotonic over its full operating temperature range. Digital-to-Analog Glitch Energy The impulse injected into the analog output when the input Bipolar Zero Error code in the data register changes state. It is normally specified The deviation of the analog output from the ideal half-scale as the area of the glitch in nanovolt-seconds (nV-sec) and is output of 0 V when the DAC register is loaded with 0x8000 measured when the digital input code is changed by 1 LSB at the (offset binary coding) or 0x0000 (twos complement coding). major carry transition (0x7FFF to 0x8000), as seen in Figure 28. Figure 22 shows a plot of bipolar zero error vs. temperature. Digital Feedthrough Bipolar Zero Temperature Coefficient A measure of the impulse injected into the analog output of the The measure of the change in the bipolar zero error with a DAC from the digital inputs of the DAC, but measured when change in temperature. It is expressed as parts per million of the DAC output is not updated. It is specified in nanovolt-seconds full-scale range per degree Celsius (ppm FSR/°C). (nV-sec) and measured with a full-scale code change on the Full-Scale Error data bus, that is, from all 0s to all 1s, and vice versa. The measure of the output error when full-scale code is loaded Power Supply Sensitivity to the data register. Ideally, the output voltage should be 2 × Indicates how the output of the DAC is affected by changes in V − 1 LSB. Full-scale error is expressed as a percentage of REFIN the power supply voltage. full-scale range (% FSR). DC Crosstalk Negative Full-Scale Error/Zero-Scale Error The dc change in the output level of one DAC in response to a The error in the DAC output voltage when 0x0000 (offset binary change in the output of another DAC. It is measured with a full- coding) or 0x8000 (twos complement coding) is loaded to the scale output change on one DAC while monitoring another data register. Ideally, the output voltage should be −2 × V . REFIN DAC, and is expressed in least significant bits (LSBs). Figure 21 shows a plot of zero-scale error vs. temperature. DAC-to-DAC Crosstalk Output Voltage Settling Time The glitch impulse transferred to the output of one DAC due to The amount of time it takes for the output to settle to a specified a digital code change and subsequent output change of another level for a full-scale input change. DAC. This includes both digital and analog crosstalk. It is Slew Rate measured by loading one of the DACs with a full-scale code A limitation in the rate of change of the output voltage. The change (from all 0s to all 1s, and vice versa) with LDAC low and output slewing speed of a voltage-output DAC is usually limited monitoring the output of another DAC. The energy of the glitch by the slew rate of the amplifier used at its output. Slew rate is is expressed in nanovolt-seconds (nV-sec). measured from 10% to 90% of the output signal and is given in volts per microsecond (V/µs). Channel-to-Channel Isolation The ratio of the amplitude of the signal at the output of one DAC Gain Error to a sine wave on the reference input of another DAC. It is A measure of the span error of the DAC. It is the deviation in measured in decibels (dB). slope of the DAC transfer characteristic from the ideal, expressed as a percentage of the full-scale range (% FSR). Figure 23 shows Reference Temperature Coefficient a plot of gain error vs. temperature. A measure of the change in the reference output voltage with a change in temperature. It is expressed in parts per million per degree Celsius (ppm/°C). Rev. D | Page 19 of 32

AD5764R Data Sheet Digital Crosstalk Thermal Hysteresis A measure of the impulse injected into the analog output of one The change of reference output voltage after the device is cycled DAC from the digital inputs of another DAC but is measured through temperatures from −40°C to +85°C and back to −40°C. when the DAC output is not updated. It is specified in nanovolt- This is a typical value from a sample of parts put through such seconds (nV-sec) and measured with a full-scale code change a cycle. on the data bus; that is, from all 0s to all 1s, and vice versa. Rev. D | Page 20 of 32

Data Sheet AD5764R THEORY OF OPERATION The AD5764R is a quad, 16-bit, serial input, bipolar voltage output SERIAL INTERFACE DAC that operates from supply voltages of ±11.4 V to ±16.5 V and The AD5764R is controlled over a versatile 3-wire serial interface has a buffered output voltage of up to ±10.5263 V. Data is written to that operates at clock rates of up to 30 MHz and is compatible the AD5764R in a 24-bit word format via a 3-wire serial interface. with SPI, QSPI™, MICROWIRE™, and DSP standards. The AD5764R also offers an SDO pin that is available for daisy Input Shift Register chaining or readback. The input shift register is 24 bits wide. Data is loaded into the The AD5764R incorporates a power-on reset circuit that ensures device, MSB first, as a 24-bit word under the control of a serial that the data registers are loaded with 0x0000 at power-up. The clock input, SCLK. The input register consists of a read/write bit, AD5764R features a digital I/O port that can be programmed via a reserved bit that must be set to 0, three register select bits, three the serial interface, an analog die temperature sensor, on-chip DAC address bits, and 16 data bits, as shown in Table 9. The 10 ppm/°C voltage reference, on-chip reference buffers, and per timing diagram for this operation is shown in Figure 2. channel digital gain and offset registers. Upon power-up, the data registers are loaded with zero code DAC ARCHITECTURE (0x0000) and the outputs are clamped to 0 V via a low impedance The DAC architecture of the AD5764R consists of a 16-bit, path. The outputs can be updated with the zero code value by current mode, segmented R-2R DAC. The simplified circuit asserting either LDAC or CLR. The corresponding output voltage diagram for the DAC section is shown in Figure 39. depends on the state of the BIN/2sCOMP pin. If the BIN/2sCOMP VREF R R R pin is tied to DGND, the data coding is twos complement and the outputs update to 0 V. If the BIN/2sCOMP pin is tied to 2R 2R 2R 2R 2R 2R 2R DV , the data coding is offset binary and the outputs update to CC negative full scale. To have the outputs power up with zero code R/8 E15 E14 E1 S11 S10 S0 loaded to the outputs, hold the CLR pin low during power-up. IOUT Standalone Operation VOUTx The serial interface works with both a continuous and noncon- 41 M5 SEBQsU DAELC SOEDGEMDE INNTTSO 12-BIT, R-2R LADDER AGNDx 06064-060 tifin SuYoNusC s iesr ihael lcdl olockw. Afo rc othneti ncouroruesc tS nCuLmK bseoru orcfe c cloacnk b cey ucsleesd. Ionn ly Figure 39. DAC Ladder Structure gated clock mode, a burst clock containing the exact number of The four MSBs of the 16-bit data-word are decoded to drive clock cycles must be used, and SYNC must be taken high after 15 switches, E1 to E15. Each of these switches connects one the final clock to latch the data. The first falling edge of SYNC of the 15 matched resistors to either AGNDx or I . The OUT starts the write cycle. Exactly 24 falling clock edges must be remaining 12 bits of the data-word drive Switch S0 to Switch S11 applied to SCLK before SYNC is brought high again. If SYNC is of the 12-bit R-2R ladder network. brought high before the 24th falling SCLK edge, then the data REFERENCE BUFFERS written is invalid. If more than 24 falling SCLK edges are applied The AD5764R can operate with either an external or an internal before SYNC is brought high, the input data is also invalid. The reference. The reference inputs (REFAB and REFCD) have an input register addressed is updated on the rising edge of SYNC. input range of up to 7 V. This input voltage is then used to provide For another serial transfer to take place, SYNC must be brought a buffered positive and negative reference for the DAC cores. low again. After the end of the serial data transfer, data is The positive reference is given by automatically transferred from the input shift register to the addressed register. +V = 2 × V REF REFIN When the data has been transferred into the chosen register of The negative reference to the DAC cores is given by the addressed DAC, all data registers and outputs can be updated −V = −2 × V REF REFIN by taking LDAC low. These positive and negative reference voltages (along with the gain register values) define the output ranges of the DACs. Rev. D | Page 21 of 32

AD5764R Data Sheet A continuous SCLK source can be used only if SYNC is held 68HC11* AD5764R* low for the correct number of clock cycles. In gated clock mode, MOSI SDIN a burst clock containing the exact number of clock cycles must SCK SCLK be used, and SYNC must be taken high after the final clock to PC7 SYNC latch the data. PC6 LDAC Readback Operation MISO SDO Before a readback operation is initiated, the SDO pin must be SDIN enabled by writing to the function register and clearing the SDO AD5764R* disable bit; this bit is cleared by default. Readback mode is invoked by setting the R/W bit to 1 in the serial input register write. With SCLK R/W set to 1, Bit A2 to Bit A0, in association with Bit REG2 to SYNC Bit REG0, select the register to be read. The remaining data bits in LDAC the write sequence are don’t care. During the next SPI write, the SDO data appearing on the SDO output contains the data from the previously addressed register. For a read of a single register, the SDIN NOP command can be used in clocking out the data from the AD5764R* selected register on SDO. The readback diagram in Figure 4 shows the readback sequence. For example, to read back the SCLK fine gain register of Channel A, implement the following SYNC sequence: LDAC 1. Write 0xA0XXXX to the input shift register. This write SDO *ADDITIONAL PINS OMITTED FOR CLARITY. 06064-061 rceognifsitgeurr oesf tChhea AnnDe5l 7A6 4sRel e fcotre dre. aNdo mteo tdhea tw ailtlh t hthe ed faitnae b gitasi,n Figure 40. Daisy-Chaining the AD5764R DB15 to DB0, are don’t care. Daisy-Chain Operation 2. Follow with a second write: an NOP condition, 0x00XXXX. During this write, the data from the fine gain register is clocked For systems that contain several devices, the SDO pin can be out on the SDO line; that is, data clocked out contains the used to daisy-chain several devices together. This daisy-chain data from the fine gain register in Bit DB5 to Bit DB0. mode can be useful in system diagnostics and in reducing the SIMULTANEOUS UPDATING VIA LDAC number of serial interface lines. The first falling edge of SYNC starts the write cycle. The SCLK is continuously applied to the Depending on the status of both SYNC and LDAC, and after input shift register when SYNC is low. If more than 24 clock data has been transferred into the input register of the DACs, pulses are applied, the data ripples out of the input shift register there are two ways to update the data registers and DAC outputs. and appears on the SDO line. This data is clocked out on the Individual DAC Updating rising edge of SCLK and is valid on the falling edge. By In individual DAC updating mode, LDAC is held low while data connecting the SDO of the first device to the SDIN input of the is being clocked into the input shift register. The addressed DAC next device in the chain, a multidevice interface is constructed. output is updated on the rising edge of SYNC. Each device in the system requires 24 clock pulses. Therefore, Simultaneous Updating of All DACs the total number of clock cycles must equal 24n, where n is the total number of AD5764R devices in the chain. When the serial In simultaneous updating of all DACs mode, LDAC is held high transfer to all devices is complete, SYNC is taken high. This while data is being clocked into the input shift register. All DAC latches the input data in each device in the daisy chain and outputs are updated by taking LDAC low any time after SYNC prevents any further data from being clocked into the input shift has been taken high. The update then occurs on the falling edge register. The serial clock can be a continuous or a gated clock. of LDAC. Rev. D | Page 22 of 32

Data Sheet AD5764R See Figure 41 for a simplified block diagram of the DAC load The output voltage expression for the AD5764R is given by circuitry.  D  OUTPUT VOUT =−2×VREFIN +4×VREFIN65,536 I/V AMPLIFIER REFAB, REFCD 16-BIT VOUTx where: DAC D is the decimal equivalent of the code loaded to the DAC. V is the reference voltage applied at the REFAB and REFIN DATA LDAC REGISTER REFCD pins. ASYNCHRONOUS CLEAR (CLR) INPUT REGISTER CLR is a negative edge triggered clear that allows the outputs to be cleared to either 0 V (twos complement coding) or negative SSSYCDNLICKN INTLEORGFIACCE SDO 06064-062 flouwll fsocra lae m(oinffismetu bmin aamryo ucondt ionf gti)m. Iet ifso rn tehcee sospaerrya ttioo nm taoi nctoaminp CleLteR Figure 41. Simplified Serial Interface of Input Loading Circuitry (see Figure 2). When the CLR signal is returned high, the output for One DAC Channel remains at the cleared value until a new value is programmed. TRANSFER FUNCTION If CLR is at 0 V at power-on, all DAC outputs are updated with Table 7 and Table 8 show the ideal input code to output voltage the clear value. A clear can also be initiated through software by relationship for offset binary data coding and twos complement writing the command of 0x04XXXX. data coding, respectively. Table 7. Ideal Output Voltage to Input Code Relationship—Offset Binary Data Coding Digital Input Analog Output MSB LSB V OUT 1111 1111 1111 1111 +2 V × (32,767/32,768) REFIN 1000 0000 0000 0001 +2 V × (1/32,768) REFIN 1000 0000 0000 0000 0 V 0111 1111 1111 1111 −2 V × (1/32,768) REFIN 0000 0000 0000 0000 −2 V × (32,767/32,768) REFIN Table 8. Ideal Output Voltage to Input Code Relationship—Twos Complement Data Coding Digital Input Analog Output MSB LSB V OUT 0111 1111 1111 1111 +2 V × (32,767/32,768) REFIN 0000 0000 0000 0001 +2 V × (1/32,768) REFIN 0000 0000 0000 0000 0 V 1111 1111 1111 1111 −2 V × (1/32,768) REFIN 1000 0000 0000 0000 −2 V × (32,767/32,768) REFIN Rev. D | Page 23 of 32

AD5764R Data Sheet REGISTERS Table 9. Input Shift Register Format MSB LSB DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1 DB0 R/W 0 REG2 REG1 REG0 A2 A1 A0 Data Table 10. Input Shift Register Bit Function Descriptions Register Bit Description R/W Indicates a read from or a write to the addressed register REG2, REG1, REG0 Used in association with the address bits, determines if a read or write operation is to the data register, offset register, gain registers, or function register REG2 REG1 REG0 Function 0 0 0 Function register 0 1 0 Data register 0 1 1 Coarse gain register 1 0 0 Fine gain register 1 0 1 Offset register A2, A1, A0 Decodes the DAC channels A2 A1 A0 Channel Address 0 0 0 DAC A 0 0 1 DAC B 0 1 0 DAC C 0 1 1 DAC D 1 0 0 All DACs Data Data bits FUNCTION REGISTER The function register is addressed by setting the three REG bits to 000. The values written to the address bits and the data bits determine the function addressed. The functions available via the function register are outlined in Table 11 and Table 12. Table 11. Function Register Options REG2 REG1 REG0 A2 A1 A0 DB15 to DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 NOP, data = don’t care 0 0 0 0 0 1 Don’t care Local ground D1 D1 D0 D0 SDO offset adjust direction value direction value disable 0 0 0 1 0 0 Clear, data = don’t care 0 0 0 1 0 1 Load, data = don’t care Table 12. Explanation of Function Register Options Option Description NOP No operation instruction used in readback operations. Local Ground Set by the user to enable the local ground offset adjust function. Cleared by the user to disable the local ground offset Offset Adjust adjust function (default). See the Design Features section for more information. D0, D1 Set by the user to enable the D0 and D1 pins as outputs. Cleared by the user to enable the D0 and D1 pins as inputs (default). Direction See the Design Features section for more information. D0, D1 Value I/O port status bits. Logic values written to these locations determine the logic outputs on the D0 and D1 pins when configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is active as an input. When enabled as inputs, these bits are don’t cares during a write operation. SDO Disable Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default). Clear Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary mode. Load Addressing this function updates the DAC registers and consequently the analog outputs. Rev. D | Page 24 of 32

Data Sheet AD5764R DATA REGISTER The data register is addressed by setting the three REG bits to 010. The DAC address bits select the DAC channel with which the data transfer takes place (see Table 10). The data bits are positioned in DB15 to DB0, as shown in Table 13. Table 13. Programming the Data Register REG2 REG1 REG0 A2 A1 A0 DB15 to DB0 0 1 0 DAC address 16-bit DAC data COARSE GAIN REGISTER The coarse gain register is addressed by setting the three REG bits to 011. The DAC address bits select the DAC channel with which the data transfer takes place (see Table 10). The coarse gain register is a 2-bit register that allows the user to select the output range of each DAC, as shown in Table 15. Table 14. Programming the Coarse Gain Register REG2 REG1 REG0 A2 A1 A0 DB15 to DB2 DB1 DB0 0 1 1 DAC address Don’t care CG1 CG0 Table 15. Output Range Selection Output Range CG1 CG0 ±10 V (Default) 0 0 ±10.2564 V 0 1 ±10.5263 V 1 0 FINE GAIN REGISTER The fine gain register is addressed by setting the three REG bits to 100. The DAC address bits select the DAC channel with which the data transfer takes place (see Table 10). The AD5764R fine gain register is a 6-bit register that allows the user to adjust the gain of each DAC channel by −32 LSBs to +31 LSBs in 1 LSB steps, as shown in Table 16 and Table 17. The adjustment is made to both the positive full-scale points and the negative full-scale points simultaneously, with each point adjusted by one-half of one step. The fine gain register coding is twos complement. Table 16. Programming the Fine Gain Register REG2 REG1 REG0 A2 A1 A0 DB15 to DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 DAC address Don’t care FG5 FG4 FG3 FG2 FG1 FG0 Table 17. Fine Gain Register Options Gain Adjustment FG5 FG4 FG3 FG2 FG1 FG0 +31 LSBs 0 1 1 1 1 1 +30 LSBs 0 1 1 1 1 0 No Adjustment (Default) 0 0 0 0 0 0 −31 LSBs 1 0 0 0 0 1 −32 LSBs 1 0 0 0 0 0 Rev. D | Page 25 of 32

AD5764R Data Sheet OFFSET REGISTER The offset register is addressed by setting the three REG bits to 101. The DAC address bits select the DAC channel with which the data transfer takes place (see Table 10). The AD5764R offset register is an 8-bit register that allows the user to adjust the offset of each channel by −16 LSBs to +15.875 LSBs in steps of one-eighth LSB, as shown in Table 18 and Table 19. The offset register coding is twos complement. Table 18. Programming the Offset Register REG2 REG1 REG0 A2 A1 A0 DB15 to DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 1 DAC address Don’t care OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0 Table 19. Offset Register Options Offset Adjustment OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0 +15.875 LSBs 0 1 1 1 1 1 1 1 +15.75 LSBs 0 1 1 1 1 1 1 0 No Adjustment (Default) 0 0 0 0 0 0 0 0 −15.875 LSBs 1 0 0 0 0 0 0 1 −16 LSBs 1 0 0 0 0 0 0 0 OFFSET AND GAIN ADJUSTMENT WORKED The required offset register value can be calculated as follows: EXAMPLE 1. Convert the adjustment value to binary: 00010000. Using the information provided in the Offset Register section, 2. Convert this binary value to a negative twos complement the following worked examples demonstrate how the AD5764R number by inverting all bits and adding 1: 11110000. functions can be used to eliminate both offset and gain errors. 3. Program this value, 11110000, to the offset register. Because the AD5764R is factory calibrated, offset and gain errors Note that this twos complement conversion is not necessary in should be negligible. However, errors can be introduced by the the case of a positive offset adjustment. The value to be pro- system within which the AD5764R is operating. For example, grammed to the offset register is simply the binary representation a voltage reference value that is not equal to 5 V introduces of the adjustment value. a gain error. An output range of ±10 V and twos complement Removing Gain Error data coding are assumed. Removing Offset Error The AD5764R can eliminate a gain error at negative full-scale output in the range of −9.77 mV to +9.46 mV with a step size of The AD5764R can eliminate an offset error in the range of one-half of a 16-bit LSB. −4.88 mV to +4.84 mV with a step size of one-eighth of a 16-bit LSB. 1. Calculate the step size of the gain adjustment, using the following equation: 1. Calculate the step size of the offset adjustment, using the following equation: 20 Gain Adjust Step Size = = 152.59 µV 216×2 20 Offset Adjust Step Size = = 38.14 µV 216×8 2. Measure the gain error by programming 0x8000 to the data register and measuring the resulting output voltage. 2. Measure the offset error by programming 0x0000 to the The gain error is the difference between this value and −10 V. data register and measuring the resulting output voltage. For this example, the gain error is −1.2 mV. For this example, the measured value is 614 µV. 3. Determine how many gain adjustment steps this value 3. Determine how many offset adjustment steps this value represents, using the following equation: represents, using the following equation: MeasuredGainValue 1.2mV MeasuredOffsetValue 614µV Number of Steps = = = 8 Steps Number of Steps = = = 16 Steps Gain Step Size 152.59µV OffsetStepSize 38.14µV The gain error measured is negative (in terms of magnitude). The offset error measured is positive; therefore, a negative Therefore, a positive adjustment of eight steps is required. The adjustment of 16 steps is required. The offset register is gain register is six bits wide, and the coding is twos complement. eight bits wide, and the coding is twos complement. The required gain register value can be determined as follows: 1. Convert the adjustment value to binary: 001000. 2. Program this binary number to the gain register. Rev. D | Page 26 of 32

Data Sheet AD5764R DESIGN FEATURES ANALOG OUTPUT CONTROL If the ISCC pin is left unconnected, the short circuit current limit defaults to 5 mA. It should be noted that limiting the In many industrial process control applications, it is vital that short-circuit current to a small value can affect the slew rate of the output voltage be controlled during power-up and during the output when driving into a capacitive load. Therefore, the brownout conditions. When the supply voltages are changing, value of the short-circuit current that is programmed should the VOUTx pins are clamped to 0 V via a low impedance path. take into account the size of the capacitive load being driven. To prevent the output amp from being shorted to 0 V during DIGITAL I/O PORT this time, Transmission Gate G1 is also opened (see Figure 42). The AD5764R contains a 2-bit digital I/O port (D1 and D0). These RSTOUT RSTIN bits can be configured independently as inputs or outputs and can be driven or have their values read back via the serial interface. VOLTAGE MONITOR The I/O port signals are referenced to DV and DGND. When AND CC CONTROL configured as outputs, they can be used as control signals to multiplexers or can be used to control calibration circuitry G1 elsewhere in the system. When configured as inputs, the logic VOUTA signals from limit switches, for example, can be applied to D0 G2 AGNDA 06064-063 aDnIdE D T1E aMndP EcaRnA bTe UreRadE b SaEckN uSsOinRg t he digital interface. Figure 42. Analog Output Control Circuitry The on-chip die temperature sensor provides a voltage output These conditions are maintained until the power supplies stabilize that is linearly proportional to the Celsius temperature scale. and a valid word is written to the data register. G2 then opens, and Its nominal output voltage is 1.47 V at +25°C die temperature, G1 closes. Both transmission gates are also externally controllable varying at 5 mV/°C, giving a typical output range of 1.175 V to by using the reset in (RSTIN) control input. For example, if RSTIN 1.9 V over the full temperature range. Its low output impedance, is driven from a battery supervisor chip, the RSTIN input is driven and linear output simplify interfacing to temperature control low to open G1 and close G2 on power-off or during a brownout. circuitry and analog-to-digital converters (ADCs). The temper- Conversely, the on-chip voltage detector output (RSTOUT) is ature sensor is provided as more of a convenience than as a precise also available to the user to control other parts of the system. feature; it is intended for indicating a die temperature change for The basic transmission gate functionality is shown in Figure 42. recalibration purposes. DIGITAL OFFSET AND GAIN CONTROL LOCAL GROUND OFFSET ADJUST The AD5764R incorporates a digital offset adjust function with The AD5764R incorporates a local ground offset adjust feature a ±16 LSB adjust range and 0.125 LSB resolution. The gain register that, when enabled in the function register, adjusts the DAC allows the user to adjust the AD5764R full-scale output range. outputs for voltage differences between the individual DAC ground The full-scale output can be programmed to achieve full-scale pins and the REFGND pin, ensuring that the DAC output voltages ranges of ±10 V, ±10.25 V, and ±10.5 V. A fine gain trim is also are always referenced to the local DAC ground pin. For example, available. if the AGNDA pin is at +5 mV with respect to the REFGND pin, PROGRAMMABLE SHORT-CIRCUIT PROTECTION and VOUTA is measured with respect to AGNDA, a −5 mV error results, enabling the local ground offset adjust feature to adjust The short-circuit current (I ) of the output amplifiers can be pro- SC VOUTA by +5 mV, thereby eliminating the error. grammed by inserting an external resistor between the ISCC pin and the PGND pin. The programmable range for the current is 500 µA to 10 mA, corresponding to a resistor range of 120 kΩ to 6 kΩ. The resistor value is calculated as follows: 60 R ≈ I SC Rev. D | Page 27 of 32

AD5764R Data Sheet APPLICATIONS INFORMATION TYPICAL OPERATING CIRCUIT Initial accuracy error on the output voltage of an external refer- ence could lead to a full-scale error in the DAC. Therefore, to Figure 43 shows the typical operating circuit for the AD5764R . minimize these errors, a reference with low initial accuracy The only external components needed for this precision 16-bit error specification is preferred. Choosing a reference with an DAC are decoupling capacitors on the supply pins and reference output trim adjustment, such as the ADR425, allows a system inputs, and an optional short-circuit current setting resistor. designer to trim system errors out by setting the reference Because the AD5764R incorporates a voltage reference and voltage to a voltage other than the nominal. The trim adjust- reference buffers, it eliminates the need for an external bipolar ment can also be used at temperature to trim out any error. reference and associated buffers, resulting in an overall savings in both cost and board space. Long-term drift is a measure of how much the reference output voltage drifts over time. A reference with a tight long-term drift In Figure 43, AVDD is connected to +15 V, and AVSS is con- specification ensures that the overall solution remains relatively nected to −15 V, but AV and AV can operate with supplies DD SS stable over its entire lifetime. from ±11.4 V to ±16.5 V. In Figure 43, AGNDx is connected to REFGND. The temperature coefficient of a reference output voltage affects INL, DNL, and TUE. A reference with a tight temperature coeffi- Precision Voltage Reference Selection cient specification should be chosen to reduce the dependence To achieve the optimum performance from the AD5764R over of the DAC output voltage on ambient conditions. its full operating temperature range, an external voltage reference In high accuracy applications, which have a relatively low noise must be used. Care must be taken in the selection of a precision budget, reference output voltage noise must be considered. It is voltage reference. The AD5764R has two reference inputs, important to choose a reference with as low an output noise REFAB and REFCD. The voltages applied to the reference inputs voltage as practical for the system resolution that is required. are used to provide a buffered positive and negative reference Precision voltage references, such as the ADR435 (XFET® design), for the DAC cores. Therefore, any error in the voltage reference produce low output noise in the 0.1 Hz to 10 Hz region. However, is reflected in the outputs of the device. as the circuit bandwidth increases, filtering the output of the There are four possible sources of error to consider when choosing reference may be required to minimize the output noise. a voltage reference for high accuracy applications: initial accuracy, temperature coefficient of the output voltage, long term drift, and output voltage noise. Table 20. Some Precision References Recommended for Use with the AD5764R Initial Accuracy Long-Term Drift Temperature Drift 0.1 Hz to 10 Hz Noise Part No. (mV Maximum) (ppm Typical) (ppm/°C Maximum) (µV p-p Typical) ADR435 ±6 30 3 3.5 ADR425 ±6 50 3 3.4 ADR02 ±5 50 3 10 ADR395 ±6 50 25 5 AD586 ±2.5 15 10 4 Rev. D | Page 28 of 32

Data Sheet AD5764R +15V –15V 10µF 10µF 100nF 100nF TEMP µF 0 1 BIN/2sCOMP 32 31 30 29 28 27 26 25 +5V 2sCOMP AVDDAVSS TEMP REFGND REFOUT REFCD REFAB SYNC 1 SYNC N/ AGNDA 24 SCLK 2 SCLK BI VOUTA 23 VOUTA SDIN 3 SDIN VOUTB 22 VOUTB SDO 4 SDO AD5764R AGNDB 21 5 CLR AGNDC 20 LDAC 6 LDAC VOUTC 19 VOUTC D0 7 D0 VOUTD 18 VOUTD D1 8 D1 T AGNDD 17 RSTOU RSTIN DGND DVCC AVDDPGND AVSS ISCC 9 10 11 12 13 14 15 16 RSTOUT nF nF 0 0 RSTIN 10 10 µF 10µF 0 1 100nF 10µF +5V+15V –15V 06064-064 Figure 43. Typical Operating Circuit Rev. D | Page 29 of 32

AD5764R Data Sheet LAYOUT GUIDELINES In any circuit where accuracy is important, careful considera- angles to each other to reduce the effects of feedthrough on the tion of the power supply and ground return layout helps to board. A microstrip technique is recommended but not always ensure the rated performance. Design the PCB on which the possible with a double-sided board. In this technique, the com- AD5764R is mounted such that the analog and digital sections ponent side of the board is dedicated to the ground plane, and are separated and confined to certain areas of the board. If the the signal traces are placed on the solder side. AD5764R is in a system where multiple devices require an GALVANICALLY ISOLATED INTERFACE AGNDx-to-DGND connection, establish the connection at one In many process control applications, it is necessary to provide point only. Establish the star ground point as close as possible to an isolation barrier between the controller and the unit being the device. The AD5764R should have ample supply bypassing of controlled to protect and isolate the controlling circuitry from 10 µF in parallel with 0.1 µF on each supply located as close to any hazardous common-mode voltages that may occur. Iso- the package as possible, ideally right up against the device. The couplers provide voltage isolation in excess of 2.5 kV. The serial 10 µF capacitors are of the tantalum bead type. The 0.1 µF loading structure of the AD5764R makes it ideal for isolated capacitor should have low effective series resistance (ESR) and low interfaces because the number of interface lines is kept to a mini- effective series inductance (ESI), such as the common ceramic mum. Figure 44 shows a 4-channel isolated interface to the types that provide a low impedance path to ground at high AD5764R using an ADuM1400 iCoupler® product. For more frequencies to handle transient currents due to internal logic information on iCoupler products, refer to www.analog.com. switching. MICROPROCESSOR INTERFACING The power supply lines of the AD5764R should use as large a trace as possible to provide low impedance paths and reduce the effects Microprocessor interfacing to the AD5764R is accomplished via of glitches on the power supply line. Shield fast-switching signals, a serial bus that uses standard protocol that is compatible with such as clocks, with digital ground to avoid radiating noise to other microcontrollers and DSP processors. The communication parts of the board; they should never be run near the reference channel is a 3-wire (minimum) interface consisting of a clock inputs. A ground line routed between the SDIN and SCLK lines signal, a data signal, and a synchronization signal. The AD5764R helps reduce cross talk between them. (A ground line is not requires a 24-bit data-word with data valid on the falling edge required on a multilayer board because it has a separate ground of SCLK. plane; however, it is helpful to separate the lines.) It is essential to For all the interfaces, a DAC output update can be performed minimize noise on the reference inputs because it couples automatically when all the data is clocked in, or it can be done through to the DAC output. Avoid crossover of digital and under the control of LDAC. The contents of the DAC register analog signals. Run traces on opposite sides of the board at right can be read using the readback function. MICROCONTROLLER ADuM1400* VIA VOA SERIAL CLOCK OUT ENCODE DECODE TO SCLK VIB VOB SERIAL DATA OUT ENCODE DECODE TO SDIN VIC VOC SYNC OUT ENCODE DECODE TO SYNC VID VOD CONTROL OUT ENCODE DECODE TO LDAC *ADDITIONAL PINS OMITTED FOR CLARITY. 06064-065 Figure 44. Isolated Interface Rev. D | Page 30 of 32

Data Sheet AD5764R EVALUATION BOARD the USB interface of the PC. Software that allows easy program- ming of the AD5764R is available with the evaluation board. The AD5764R comes with a full evaluation board to help designers The software runs on any PC that has Microsoft® Windows® evaluate the high performance of the part with a minimum of 2000/XP installed. effort. All that is required to run the evaluation board is a power supply and a PC. The AD5764R evaluation kit includes a popu- lated, tested AD5764R PCB. The evaluation board interfaces to Rev. D | Page 31 of 32

AD5764R Data Sheet OUTLINE DIMENSIONS 0.75 1.20 MAX 9.00 BSC SQ 0.60 0.45 32 25 1 24 PIN 1 7.00 TOP VIEW BSC SQ 1.05 0° MIN 0.20 (PINS DOWN) 1.00 0.09 0.95 7° 3.5° 8 17 0.15 SEATING 0° 9 16 0.05 PLANE 0C.O08P LMAANXARITY VIEW A 0.80 0.45 BSC LEAD PITCH 0.37 VIEW A 0.30 ROTATED 90° CCW COMPLIANTTO JEDEC STANDARDS MS-026-ABA 020607-A Figure 45. 32-Lead Thin Plastic Quad Flat Package [TQFP] (SU-32-2) Dimensions shown in millimeters ORDERING GUIDE Temperature Internal Package Package Model1 Function INL Range Reference Description Option AD5764RBSUZ Quad 16-Bit DAC ±2 LSB Max −40°C to +85°C +5 V 32-Lead TQFP SU-32-2 AD5764RBSUZ-REEL7 Quad 16-Bit DAC ±2 LSB Max −40°C to +85°C +5 V 32-Lead TQFP SU-32-2 AD5764RCSUZ Quad 16-Bit DAC ±1 LSB Max −40°C to +85°C +5 V 32-Lead TQFP SU-32-2 AD5764RCSUZ-REEL7 Quad 16-Bit DAC ±1 LSB Max −40°C to +85°C +5 V 32-Lead TQFP SU-32-2 EVAL-AD5764REBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2008–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06064-0-10/11(D) Rev. D | Page 32 of 32

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: EVAL-AD5764REBZ AD5764RCSUZ AD5764RCSUZ-REEL7 AD5764RBSUZ AD5764RBSUZ-REEL7