a 12-Bit Ultrahigh Speed Monolithic D/A Converter AD568 FEATURES FUNCTIONAL BLOCK DIAGRAM Ultrahigh Speed: Current Settling to 1 LSB in 35 ns High Stability Buried Zener Reference on Chip Monotonicity Guaranteed Over Temperature 10.24 mA Full-Scale Output Suitable for Video Applications Integral and Differential Linearity Guaranteed Over Temperature 0.3" “Skinny DIP” Packaging Variable Threshold Allows TTL and CMOS Interface MIL-STD-883 Compliant Versions Available PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD568 is an ultrahigh-speed, 12-bit digital-to-analog con- 1. The ultrafast settling time of the AD568 allows leading edge verter (DAC) settling to 0.025% in 35 ns. The monolithic de- performance in waveform generation, graphics display and vice is fabricated using Analog Devices’ Complementary Bipolar high speed A/D conversion applications. (CB) Process. This is a proprietary process featuring high-speed 2. Pin strapping provides a variety of voltage and current output NPN and PNP devices on the same chip without the use of di- ranges for application versatility. Tight control of the abso- electric isolation or multichip hybrid techniques. The high speed lute output current reduces trim requirements in externally- of the AD568 is maintained by keeping impedance levels low scaled applications. enough to minimize the effects of parasitic circuit capacitances. 3. Matched on-chip resistors can be used for precision scaling in The DAC consists of 16 current sources configured to deliver a high speed A/D conversion circuits. 10.24 mA full-scale current. Multiple matched current sources and thin-film ladder techniques are combined to produce bit 4. The digital inputs are compatible with TTL and +5 V weighting. The DAC’s output is a 10.24 mA full scale (FS) for CMOS logic families. current output applications or a 1.024 V FS unbuffered voltage 5. Skinny DIP (0.3") packaging minimizes board space require- output. Additionally, a 10.24 V FS buffered output may be gen- ments and eases layout considerations. erated using an onboard 1 kW span resistor with an external op amp. Bipolar ranges are accomplished by pin strapping. 6. The AD568 is available in versions compliant with MIL- STD-883. Refer to the Analog Devices Military Products Laser wafer trimming insures full 12-bit linearity. All grades of Databook or current AD568/883B data sheet for detailed the AD568 are guaranteed monotonic over their full operating specifications. temperature range. Furthermore, the output resistance of the DAC is trimmed to 100 W – 1.0%. The gain temperature coeffi- cient of the voltage output is 30 ppm/(cid:176) C max (K). The AD568 is available in three performance grades. The AD568JQ and KQ are available in 24-pin cerdip (0.3") packages and are specified for operation from 0(cid:176) C to +70(cid:176) C. The AD568SQ features operation from –55(cid:176) C to +125(cid:176) C and is also packaged in the hermetic 0.3" cerdip. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703

AD568–SPECIFICATIONS (@ = +25(cid:56)C, V , V = (cid:54)15 V unless otherwise noted) CC EE Model AD568J AD568K AD568S Min Typ Max Min Typ Max Min Typ Max Units RESOLUTION 12 12 12 Bits ACCURACY1 Linearity –1/2 +1/2 –1/4 +1/4 –1/2 +1/2 LSB T to T –3/4 +3/4 –1/2 +1/2 –3/4 +3/4 LSB MIN MAX Differential Nonlinearity –1 +1 –1/2 +1/2 –1 +1 LSB T to T –1 +1 –1 + 1 –1 –1 LSB MIN MAX Monotonicity GUARANTEED OVER RATED SPECIFICATION TEMPERATURE RANGE Unipolar Offset –0.2 +0.2 * * * * % of FSR Bipolar Offset –1.0 +1.0 * * * * % of FSR Bipolar Zero –0.2 +0.2 * * * * % of FSR Gain Error –1.0 +1.0 * * * * % of FSR TEMPERATURE COEFFICIENTS2 Unipolar Offset –5 +5 –3 +3 –5 +5 ppm of FSR/(cid:176)C Bipolar Offset –30 +30 –20 +20 –30 +30 ppm of FSR/(cid:176)C Bipolar Zero –15 +15 • • • • ppm of FSR/(cid:176)C Gain Drift –50 +50 –30 +30 –50 +50 ppm of FSR/(cid:176)C Gain Drift (I ) –150 +150 * * * * ppm of FSR/(cid:176)C OUT DATA INPUTS Logic Levels (T to T ) MIN MAX V 2.0 7.0 * * * * V IH V 0.0 0.8 * * * * V IL Logic Currents (T to T ) MIN MAX I –10 0 +10 * * * * * * m A IH I –0.5 –60 –100 * * * * –100 –200 m A IL V Pin Voltage 1.4 * * V TH CODING BINARY, OFFSET BINARY CURRENT OUTPUT RANGES 0 to 10.24, – 5.12 mA VOLTAGE OUTPUT RANGES 0 to 1.024, – 0.512 V COMPLIANCE VOLTAGE –2 +1.2 * * * * V OUTPUT RESISTANCE Exclusive of R 160 200 240 * * W L Inclusive of R 99 100 101 * * W L SETTLING TIME Current to – 0.025% 35 * * ns to 0.025% of FSR – 0.1% 23 * * ns to 0.1% of FSR Voltage 50 W Load3, 0.512 V p-p, to 0.025% 37 * * ns to 0.025% of FSR to 0.1% 25 * * ns to 0.1% of FSR to 1% 18 * * ns to 1% of FSR 75 W Load3, 0.768 V p-p, to 0.025% 40 * * ns to 0.025% of FSR to 0.1% 25 * * ns to 0.1% of FSR to 1% 20 * * ns to 1% of FSR 100 W (Internal R )3, 1.024 V p-p, L to 0.025% 50 * * ns to 0.025% of FSR to 0.1% 38 * * ns to 0.1% of FSR to 1% 24 * * ns to 1% of FSR Glitch Impulse4 350 * * pV-sec Peak Amplitude 15 * * % of FSR FULL-SCALE TRANSlTlON5 10% to 90% Rise Time 11 * * ns 90% to 10% Fall Time 11 * * ns POWER REQUIREMENTS +13.5 V to +16.5 V 27 32 * * * * mA –13.5 V to –16.5 V –7 –8 * * * * mA Power Dissipation 525 625 * * * * mW PSRR 0.05 * * % of FSR/V TEMPERATURE RANGE Rated Specification2 0 +70 0 +70 –55 +125 (cid:176)C Storage –65 +150 * * * * (cid:176)C NOTES *Same as AD568J. 1Measured in I mode. OUT 2Measured in V mode, unless otherwise specified. See text for further information. OUT 3Total Resistance. Refer to Figure 3, 4At the major carry, driven by HCMOS logic. See text for further explanation. 5Measured in V mode. OUT Specifications shown in boldface are tested on all production units at final electrical test. Specifications subject to change without notice. –2– REV. A

AD568 LSB MSB PIN CONFIGURATION 12 11 10 9 8 7 6 5 4 3 2 1 CURRPENNPT 2X 4X 24 VCC SOURCES BURIED ZENER PNP REFERENCE THCROESNHTOROLDL 13 SWITCHES REFERENCE THRCEOSMHMOOLND 14 BG1RA.AE4NVFPD- THIN-F(I1L0M0 R- -220R0 WLA)DDER IOUT 200W 12229031 CBIL(OROOIUPLAMT)ODML AORRENSISTOR CLOAMDMDOERN 17 DIFFUSE(1D0 R- -220RW L)ADDER IOUT GCEBNUIPERORRLAEATNROTR 1kW 15 1RO0EFVSF SISSEPTTAO N(RIBPO) AD568 16 10V SPAN 18 22 RESISTOR CAONMALMOOGN VEE Figure 1. Functional Block Diagram ABSOLUTE MAXIMUM RATINGS1 V to REFCOM . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +18V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mW CC V to REFCOM . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to –18 V Storage Temperature Range EE REFCOM to LCOM . . . . . . . . . . . . . . . . . +100 mV to –10 V Q (Cerdip) Package . . . . . . . . . . . . . . . . . –65(cid:176) C to +150(cid:176) C ACOM to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . – 100 mV Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175(cid:176) C THCOM to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . – 500 mV Thermal Resistance SPANs to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 12 V q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75(cid:176) C/W JA I to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 5 V q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25(cid:176) C/W BPO JC I to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to V OUT TH Digital Inputs to THCOM . . . . . . . . . . . . . –500 mV to +7.0 V 1Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional Voltage Across Span Resistor . . . . . . . . . . . . . . . . . . . . . . 12 V operation of the device at these or any other conditions above those indicated in the V to THCOM . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +1.4 V TH operational section of this specification is not implied. Exposure to absolute Logic Threshold Control Input Current . . . . . . . . . . . . . 5 mA maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Linearity Voltage Temperature Error Max Gain T.C. Modell Package Option2 Range (cid:56)C @ 25(cid:56)C Max ppm/(cid:56)C AD568JQ 24-Lead Cerdip (Q-24) 0 to +70 – 1/2 – 50 AD568KQ 24-Lead Cerdip (Q-24) 0 to +70 – 1/4 – 30 AD568SQ 24-Lead Cerdip (Q-24) –55 to +125 – 1/2 – 50 NOTES 1For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or current AD568/883B data sheet. 2Q = Cerdip. Definitions LINEARITY ERROR (also called INTEGRAL NONLINEAR- requires that the differential linearity error not exceed 1 LSB in ITY OR INL): Analog Devices defines linearity error as the the negative direction. maximum deviation of the actual analog output from the ideal MONOTONICITY: A DAC is said to be monotonic if the out- output (a straight line drawn from 0 to FS) for any bit combina- put either increases or remains constant as the digital input tion expressed in multiples of 1 LSB. The AD568 is laser increases. trimmed to 1/4 LSB (0.006% of FS) maximum linearity error at UNIPOLAR OFFSET ERROR: The deviation of the analog +25(cid:176) C for the K version and 1/2 LSB for the J and S versions. output from the ideal (0 V or 0 mA) when the inputs are set to DIFFERENTIAL LINEARITY ERROR (also called DIFFER- all 0s is called unipolar offset error. ENTIAL NONLINEARITY or DNL): DNL is the measure of BIPOLAR OFFSET ERROR: The deviation of the analog out- the variation in analog value, normalized to full scale, associated put from the ideal (negative half-scale) when the inputs are set with a 1 LSB change in digital input code. Monotonic behavior to all 0s is called bipolar offset error. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD568 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ESD SENSITIVE DEVICE REV. A –3–

AD568 BIPOLAR ZERO ERROR: The deviation of the analog output their glitch impulse. It is specified as the net area of the glitch in from the ideal half-scale output of 0 V (or 0 mA) for bipolar nV-sec or pA-sec. mode when only the MSB is on (100 . . .00) is called bipolar COMPLIANCE VOLTAGE: The range of allowable voltage at zero error. the output of a current-output DAC which will not degrade the GAIN ERROR: The difference between the ideal and actual accuracy of the output current. output span of FS –1 LSB, expressed in % of FS, or LSB, when SETTLING TIME: The time required for the output to reach all bits are on. and remain within a specified error band about its final value, GLITCH IMPULSE: Asymmetrical switching times in a DAC measured from the digital input transition. give rise to undesired output transients which are quantified by +15V –15V 0.8 0.2µF 0.1µF 1 +15V 24 FERRITE BEADS 0.1µF STACKPOLE 57-1392 2 REFCOM 23 OR LTS0.6 3 –15V 220.1µF AOMR IEDQOUNI VFABL-4E3NBT-101 VO 4 IBPO 21 – OUTPUT 0.4 DINIGPIUTATSL 765 AD56A8CIOORUMLT 211098 AOANUNATALPLOUOGTG R(OEPXTTIONAL) 8 LCOM 17 SUPPLY GROUND ANALOG 9 SPAN16 NC GND PLANE 10 SPAN 15 NC DIGITAL GND PLANE DIGITAL 0 50 100 150 200 250 11 THCOM 14 100pF SUPPLY TIME – ns 12 VTH 13 GROUND Figure 2.Glitch Impulse R1kTWH Connecting the AD568 +5V Figure 3.Unipolar Output Unbuffered 0 V to +1.024 V UNBUFFERED VOLTAGE OUTPUT +15V –15V 0.2µF Unipolar Configuration Figure 3 shows the AD568 configured to provide a unipolar 0 to 0.1µF +1.024 V output range. In this mode, the bipolar offset termi- 1 +15V 24 nal, Pin 21, should be grounded if not used for offset trimming. 0.1µF 2 REFCOM 23 The nominal output impedance of the AD568 with Pin 19 3 –15V 220.1µF grounded has been trimmed to 100 W , – 1%. Other output im- 4 IBPO 21 pedances can be generated with an external resistor, REXT, be- 5 IOUT 20 ANALOG tween Pins 19 and 20. An REXT equalling 300 W will yield a DIGITAL 6 AD568 RL 19 OUTPUT total output resistance of 75 W , while an REXT of 100 W will pro- INPUTS 7 ACOM 18 ANALOG vide 50 W of output resistance. Note that since the full-scale 8 LCOM 17 ANALOG SGURPOPULNYD output current of the DAC remains 10.24 mA, changing the 9 SPAN16 GND PLANE 100pF load impedance changes the unbuffered output voltage accord- 10 SPAN 15 DIGITAL ingly. Settling time and full-scale range characteristics for these 11 THCOM 14 GND PLANE DSUIGPITPALYL load impedances are provided in the specifications table. 12 VTH 13 GROUND Bipolar Configuration Figure 4 shows the connection scheme used to provide a bipolar +5V output voltage range of 1.024 V. The bipolar offset (–0.512 V) occurs when all bits are OFF (00 . . . 00), bipolar zero (0 V) oc- Figure 4.Bipolar Output Unbuffered – 0.512 V curs when the MSB is ON with all other bits OFF (10 . . . 00), and full-scale minus 1 LSB (0.51175 V) is generated when all Figure 4 also demonstrates how the internal span resistor may bits are ON (11 . . . 11). Figure 5 shows an optional bipolar be used to bias the V pin (Pin 13) from a 5 V supply. This mode with a 2.048 V range. The scale factor in this mode will TH eliminates the requirement for an external R in applications not be as accurate as the configuration shown in Figure 4, be- TH that do not require the precision span resistor. cause the laser-trimmed resistor R is not used. L –4– REV. A

AD568 +15V –15V full scale at the DAC output. Note: this may slightly compro- 0.2µF mise the bipolar zero trim. 0.1µF 1 BIT 1 24 1 +15V 24 0.1µF 2 MSB 23 2 REFCOM 23 0.1µF 3 AD568 22 3 –15V 22 4 IBPO 21 VCC 4 IBPO 21 5 IOUT 20 DINIGPIUTATSL 765 AD56A8CIOORUMLT 211098 AONUATPLAOUNTGALOG DINIGPIUTATSL 76 ACORML 1198 20WGAIN 5.1715kWW ZERO 20kW (–AO00NU..55AT11LP22OUV T)GTO 8 LCOM 17 ANALOG SGURPOPULNYD 98 LCOM1167 9 SPAN16 NC GND PLANE VEE 10 15 10 SPAN 15 NC DIGITAL GND PLANE DIGITAL 11 14 1121 THCVOTMH 1134 100pF SGURPOPULNYD 12 BLSITB 12 13 RTH 1kW Figure 7.Bipolar Unbuffered Gain and Zero Adjust BUFFERED VOLTAGE OUTPUT +5V For full-scale outputs of greater than 1 V, some type of external buffer amplifier is required. The AD840 fills this requirement Figure 5.Bipolar Output Unbuffered – 1.024 V perfectly, settling to 0.025% from a 10 V full-scale step in less Optional Gan and Zero Adjustment than 100 ns. The gain and offset are laser trimmed to minimize their effects A 1 kW span resistor has been provided on chip for use as a on circuit performance. However, in some applications, it may feedback resistor in buffered applications. Using R (Pins 15, be desirable to externally reduce these errors further. In those SPAN 16) introduces a 100 mW code-dependent power source onto cases, the following procedures are suggested. the chip which may generate a slight degradation in linearity. UNIPOLAR MODE: (Refer to Figure 6) Maximum linearity performance can be realized by using an ex- Step 1 – Set all bits (BIT 1–BIT 12) to Logic “0” (OFF)—note ternal span resistor. the output voltage. This is the offset error. +15V –15V 0.2µF Step 2 – Set all bits to Logic “1” (ON). Adjust the gain trim re- sistor so that the output voltage is equal to the desired full scale 0.1µF minus 1 LSB plus the offset error measured in step 1. Step 3 – Reset all bits to Logic “0” (OFF). Adjust the offset 1 +15V 24 0.1µF trim resistor for 0 V output. 2 REFCOM 23 3 –15V 220.1µF –VS +VS 1 BIT 1 24 4 IBPO 21 AD840 2 MSB 23 5 IOUT 20 100W ANALOG 3 AD568 22 DIGITAL 6 AD568 RL 19 OUTPUT 4 IBPO 21 INPUTS 7 ACOM 18 5 IOUT 20 GAIN 8 LCOM 17 AGNNADL POLGANE ANALOG DINIGPIUTATSL 76 ACORML 1198 20W 150.101WkW AO(0NU TATOPL OU1.TG024V) 190 SSPPAANN1156 5pF GSRUOPPULNYD OFFSET 8 LCOM 17 11 THCOM 14 100pF DIGITAL 9 16 12 VTH 13 GND PLANE DIGITAL 10 15 1RkTWH GSRUOPPULNYD 11 14 12 BIT 12 13 LSB AMPLIFIER NOISE GAIN: 11 +5V Figure 6.Unbuffered Unipolar Gain and Zero Adjust BIPOLAR MODE (Refer to Figure 7) Figure 8.Unipolar Output Buffered 0 to –10.24V Step 1 – Set bits to offset binary “zero” (10 . . . 00). Adjust the Unipolar Inverting Configuration zero resistor to produce 0 V at the DAC output. This removes Figure 8 shows the connections for producing a – 10.24 V full- the bipolar zero error. scale swing. This configuration uses the AD568 in the current Step 2 – Set all bits to Logic “1” (ON). Adjust gain trim resistor output mode into a summing junction at the inverting input ter- so the output voltage is equal to the desired full-scale minus minal of the external op amp. With the load resistor R L l LSB . grounded, the DAC has an output impedance of 100 W . This Step 3 – (Optional) If precise trimming of the bipolar offset is produces a noise gain of 11 from the noninverting terminal of preferred to trimming of bipolar zero: set all bits to Logic “0” the op amp, and hence, satisfies the stability criterion of the (OFF). Trim the zero resistor to produce the desired negative AD840 (stable at a gain of 10). The addition of a 5 pF compen- REV. A –5–

AD568 sation capacitor across the 1 kW feedback resistor produces opti- Noninverting Configuration mal settling. Lower noise gain can be achieved by connecting R If a positive full-scale output voltage is required, it can be imple- L to I increasing the DAC output impedance to approximately mented using the AD568 in the unbuffered voltage output mode OUT, 200 W , and reducing the noise gain to 6 (illustrated in Figure 9). followed by the AD840 in a noninverting configuration (Figure While the output in this configuration will feature improved 10). The noise gain of this topology is 10, requiring only 5 pF noise performance, it is somewhat less stable and may suffer across the feedback resistor to optimize settling. from ringing. The compensation capacitance should be in- +15V –15V creased to 7 pF to maintain stability at this reduced gain. 0.2µF +15V –15V 0.1µF 0.2µF 0.1µF 1 +15V 24 0.1µF 2 REFCOM 23 1 +15V 24 3 –15V 220.1µF –VS +VS 0.1µF 2 REFCOM 23 4 IBPO 21 AD840 3 –15V 220.1µF –VS +VS 5 IOUT 20 111W ANALOG 4 IBPO 21 AD840 DIGITAL 6 AD568 RL 19 OUTPUT 5 IOUT 20 100W INPUTS 7 ACOM 18 DIGITAL 6 AD568 RL 19 AONUATPLOUTG 8 LCOM 17 AGNNADLOG ANALOG INPUTS 7 ACOM 18 9 SPAN16 PLANE SUPPLY 8 LCOM 17 ANALOG 10 SPAN 15 5pF GROUND GND PLANE ANALOG DIGITAL GND PLANE 190 SSPPAANN1156 5pF GSRUOPPULNYD 1121 THCVOTMH 1134 100pF DIGITAL 11 THCOM 14 100pF DIGITAL R1kTWH GSRUOPPULNYD 12 VTH 13 GND PLANE DIGITAL 1RkTWH GSRUOPPULNYD AMPLIFIER NOISE GAIN: 10 +5V AMPLIFIER NOISE GAIN: 11 Figure 10.Unipolar Output Buffered 0 V to +10.24 V +5V Figure 8.Unipolar Output Buffered 0 to –10.24V Guidelines for Using the AD568 +15V –15V The designer who seeks to combine high speed with high preci- 0.2µF sion faces a challenging design environment. Where tens of milliamperes are involved, fractions of an ohm of misplaced 0.1µF impedance can generate several LSBs of error. Increasing bandwidths make formerly negligible parasitic capacitances and 1 +15V 24 0.1µF inductances significant. As system performance reaches and ex- 2 REFCOM 23 3 –15V 220.1µF –VS +VS ceeds that of the measurement equipment, time-honored test methods may no longer be trustworthy. The DAC’s placement 4 IBPO 21 AD840 on the boundary between the analog and digital domains intro- 5 IOUT 20 200W ANALOG duces additional concerns. Proper RF techniques must be used DIGITAL 6 AD568 RL 19 OUTPUT in board design, device selection, supply bypassing, grounding, INPUTS 7 ACOM 18 and measurement if optimal performance is to be realized. The 8 LCOM 17 AGNNADL POLGANE ANALOG AD568 has been configured to be relatively easy to use, even in 9 SPAN16 7pF GSRUOPPULNYD some of the more treacherous applications. The device charac- 10 SPAN 15 teristics shown in this data sheet are readily achievable if proper 11 THCOM 14 100pF DIGITAL attention is paid to the details. Since a solid understanding of 12 VTH 13 GND PLANE DIGITAL the circuit involved is one of the designer’s best weapons against 1RkTWH GSRUOPPULNYD the difficulties of RF design, the following sections provide illus- trations, explanations, examples, and suggestions to facilitate successful design with the AD568. AMPLIFIER NOISE GAIN: 6 +5V Current Output vs. Voltage Output As indicated in Figures 3 through 10, the AD568 has been Figure 9.Bipolar Output Buffered – 5.12 V designed to operate in several different modes depending on the Bipolar Inverting Configuration external circuit configuration. While these modes may be Figure 9 illustrates the implementation of a +5.12 V to –5.12 V categorized by many different schemes, one of the most impor- bipolar range, achieved by connecting the bipolar offset current, tant distinctions to be made is whether the DAC is to be used to I , to the summing junction of the external amplifier. Note generate an output voltage or an output current. In the current BPO that since the amplifier is providing an inversion, the full-scale output mode, the DAC output (Pin 20) is tied to some type of output voltage is –5.12 V, while the bipolar offset voltage (all summing junction, and the current flowing from the DAC into bits OFF) is +5.12 V at the amplifier output. this summing junction is sensed (e.g., Figures 8 and 9). In this –6– REV. A

AD568 mode, the DAC output scale is insensitive to whether the load The threshold of the digital inputs is set at 1.4 V and does not resistor, R , is shorted (Pin 19 connected to Pin 20), or vary with supply voltage. This is provided by a bandgap refer- L grounded (Pin 19 connected to Pin 18). However, this does ence generator, which requires approximately 3 mA of bias cur- affect the output impedance of the DAC current and may have a rent achieved by tying R to any +V supply where TH L significant impact on the noise gain of the external circuitry. In the voltage output mode, the DAC’s output current flows (cid:230) +(cid:86) (cid:177)(cid:49)(cid:46)(cid:52)(cid:86)(cid:246) (cid:82) =(cid:231) (cid:76) (cid:247) through its own internal impedance (perhaps in parallel with an (cid:84)(cid:72) Ł (cid:51)(cid:109)(cid:65) ł external impedance) to generate a voltage, as in Figures 3, 4, 5, The input lines operate with small input currents to easily and 10. In this case, the DAC output scale is directly dependent achieve interface with unbuffered CMOS logic. The digital in- on the load impedance. The temperature coefficient of the put signals to the DAC should be isolated from the analog out- AD568’s internal reference is trimmed in such a way that the put as much as possible. To minimize undershoot, ringing, and drift of the DAC output in the voltage output mode is centered possible digital feedthrough noise, the interconnect distances to on zero. The current output of the DAC will have an additional the DAC inputs should be kept as short as possible. Termina- drift factor corresponding to the absolute temperature coeffi- tion resistors may improve performance if the digital lines be- cient of the internal thin-film resistors. This additional drift may come too long. The digital input should be free from large be removed by judicious placement of the 1 kW span resistor in glitches and ringing and have maximum 10% to 90% rise and the signal path. For example, in Figures 8 and 9, the current fall times of 5 ns. Figure 12 shows the equivalent digital input flowing from the DAC into the summing junction could suffer circuit of the AD568. from as much as 150 ppm/(cid:176) C of thermal drift. However, since this current flows through the internal span resistor (Pins 15 and 1.28mA +VL 16) which has a temperature coefficient that matches the DAC ladder resistors, this drift factor is compensated and the buffered 125W R(ETXHTERNAL) voltage at the amplifier output will be within specified limits for INPBUITT VTHRESHOLD the voltage output mode. 5pF 58pF 1B.A4VNDGAP DIODE Output Voltage Compliance The AD568 has a typical output compliance range of +1.2 V to TO TO ANALOG TO LADDER THRESHOLD THRESHOLD COMMON IOUT COMMON COMMON –2.0 V (with respect to the LCOM Pin). The current- COMMON steering output stages will be unaffected by changes in the out- Figure 12.Equivalent Digital Input put terminal voltage over that range. However, as shown in Fig- ure 11, there is an equivalent output impedance of 200 W in Due to the high-speed nature of the AD568, it is recommended parallel with 15 pF at the output terminal which produces an that high-speed logic families such as Schottky TTL, high-speed equivalent error current if the voltage deviates from the ladder CMOS, or the new lines of FAST* TTL be used exclusively. common. This is a linear effect which does not change with in- Table I shows how DAC performance can vary depending on put code. Operation beyond the maximum compliance limits the driving logic used. As this table indicates, STTL, HCMOS, may cause either output stage saturation or breakdown resulting and FAST represent the most viable families for driving the in nonlinear performance. The positive compliance limit is not AD568. affected by the positive power supply, but is a function of output current and the logic threshold voltage at V , Pin 13. Table I. DAC Performance vs. Drive Logic1 TH IOUT = 10.24mA x DIG4I0T9A6L IN IOUT = 10.24mA x (1 – D I G 4 I0 T 9 A 6 L I N ) 10-90% SettlDinAgC Time2, 3 Maximum Logic DAC 1% 0.1% 0.025% Glitch4 Glitch COMPLIANCE 10.24mA Family Rise Time2 Impulse Excursion TO VTHRESHOLD TTL 11 ns 18 ns 34 ns 50 ns 2.5 nV-s 240 mV LSTTL 11 ns 28 ns 46 ns 80 ns 950 pV-s 160 mV RLOAD 15pF RLADDER RLADDER 15pF COMPLIANCE TO STTL 9.5 ns 16 ns 33 ns 50 ns 850 pV-s 150 mV (200W ) (200W ) (200W ) LOGIC LOW VALUE HCMOS 11 ns 24 ns 38 ns 50 ns 350 pV-s 115 mV FAST* 12 ns 16 ns 36 ns 42 ns 1.0 nV-s 250 mV RLOAD IOUT CLOAMDDMEORN CAONMALMOOGN N1AOll TvaElSues typical, taken in rest fixture diagrammed in Figure 13. 2Measurements are made for a 1 V full-scale step into 100 W DAC load Figure 11.Equivalent Output resistance. 3Settling time is measured from the time the digit input crosses the threshold Digital Input Considerations voltage (1.4 V) to when the output is within the specified range of its final value. The AD568 uses a standard positive true straight binary code 4The worst case glitch impulse, measured on the major carry DAC full scale for unipolar outputs (all 1s full-scale output), and an offset bi- is 1 V. nary code for bipolar output ranges. In the bipolar mode, with all 0s on the inputs, the output will go to negative full scale; with 111 . . . 11, the output will go to positive full scale less 1 LSB; and with 100 . . 00 (only the MSB on), the output will go to zero. REV. A –7–

AD568 The variations in settling times can be attributed to differences in the rise time and current driving capabilities of the various families. Differences in the glitch impulse are predominantly de- 1.026 pendent upon the variation in data skew. Variations in these specs occur not only between logic families, but also between TS L different gates and latches within the same family. When select- VO – ing a gate to drive the AD568 logic input, pay particular atten- T 1.024 U tion to the propagation delay time specs: tPLH and tPHL. UTP Selecting the smallest delays possible will help to minimize the C O settling time, while selection of gates where tPLH and tPHL are DA closely matched to one another will minimize the glitch impulse 1.022 resulting from data skew. Of the common latches, the 74374 oc- tal flip-flop provides the best performance in this area for many of the logic families mentioned above. 0 20 40 60 80 100 120 TIME – ns *FAST is a registered trademark of Fairchild Camera and Instrumentation Figure 14.Zero to Full-Scale Settling Corporation. Glitch Considerations CLOCK IN +5V In many high-speed DAC applications, glitch performance is a SELECT critical specification. In a conventional DAC architecture such 1A VCC 1B 1V as the AD568 there are two basic glitch mechanisms: data skew 2A741582V and digital feedthrough. A thorough understanding of these 2B 3A 3V sources can help the user to minimize glitch in any application. 3B 4V +15V –15V 4A STROBE DIGITAL FEEDTHROUGH—As with any converter product, 4B GND AD568 a high-speed digital-to-analog converter is forced to exist on the 1 VCC 12 2 REFCOM frontier between the noisy environment of high-speed digital WORD A 1ASELECVTCC 34 IBVPEOE VOUT ltoergfiacc ainngd atrhee psaerntsicituivlaer alyn aalcougt ed womheanin d. eTmhaen pdrso obfl ehmigsh o sfp teheisd in- 1B 1V 5 IOUT (greater than 10 MHz switching times) and high precision (12 2A74158 2B 2V 6 RL bits or more) are combined. No amount of design effort can 3A 3V 7 ACOM perfectly isolate the analog portions of a DAC from the spectral 3B 4V 8 LCOM 4A STROBE 9 RSPAN components of a digital input signal with a 2 ns risetime. Inevi- 4B GND 10 RSPAN tably, once this digital signal is brought onto the chip, some of 12 11 THCON its higher frequency components will find their way to the sensi- WORD B 12 VTH tive analog nodes, producing a digital feedthrough glitch. To SELECT 1A VCC 1k minimize the exposure to this effect, the AD568 has intention- 1B 1V ally omitted the on-board latches that have been included in 22AB741582V +5V many slower DACs. This not only reduces the overall level of 3V 3A digital activity on chip, it also avoids bringing a latch clock pulse 3B 4V 4A STROBE on board, whose opposite edge inevitably produces a substantial 4B GND glitch, even when the DAC is not supposed to be changing codes. Another path for digital noise to find its way onto a con- Figure 13.Test Setup for Glitch Impulse and Settling verter chip is through the reference input pin. The completely Time Measurements internal reference featured in the AD568 eliminates this noise input, providing a greater degree of signal integrity in the analog Settling Time Considerations portions of the chip. As can be seen from Table I and the specifications page, the set- tling time of the AD568 is application dependent. The fastest DATA SKEW—The AD568, like many of its slower predeces- settling is achieved in the current-output mode, since the volt- sors, essentially uses each digital input line to switch a separate, age output mode requires the output capacitance to be charged weighted current to either the output (I ) or some other node OUT to the appropriate voltage. The DAC’s relatively large output (ANALOG COM). If the input bits are not changed simulta- current helps to minimize this effect, but settling-time sensitive neously, or if the different DAC bits switch at different speeds, applications should avoid any unnecessary parasitic capacitance then the DAC output current will momentarily take on some in- at the output node of voltage output configurations. Direct mea- correct value. This effect is particularly troublesome at the surement of the fine scale DAC settling time, even in the voltage “carry points”, where the DAC output is to change by only one output mode, is extremely tricky: analog scope front ends are LSB, but several of the larger current sources must be switched generally incapable of recovering from overdrive quickly enough to realize this change. Data skew can allow the DAC output to to give an accurate settling representation. The plot shown in move a substantial amount towards full scale or zero (depending Figure 14 was obtained using Data Precision’s 640 16-bit sam- upon the direction of the skew) when only a small transition is pling head, which features the quick overdrive recovery charac- desired. Great care was taken in the design and layout of the teristic of sampling approaches combined with high accuracy AD568 to ensure that switching times of the DAC switches are and relatively small thermal tail. symmetrical and that the length of the input data lines are short –8– REV. A

AD568 and well matched. The glitch-sensitive user should be equally 1.4 V, Pin 13 may be directly driven with a voltage source, leav- diligent about minimizing the data skew at the AD568’s inputs, ing Pin 14 tied to the ground plane. As Note 2 in Table III indi- particularly for the 4 or 5 most significant bits. This can be cates, lowering the threshold voltage may reduce output voltage achieved by using the proper logic family and gate to drive the compliance below the specified limits, which may be of concern DAC, and keeping the interconnect lines between the logic out- in an unbuffered voltage output topology. puts and the DAC inputs as short and as well matched as pos- sible, particularly for the most significant bits. The top 6 bits AD568 RB C1: 1000pF CHIP CAPACITOR should be driven from the same latch chip if latches are used. THCOM 14 C1 Glitch Reduction Schemes ANALOG BIT-DESKEWING—Even carefully laid-out boards using the VTH 13 GROUND proper driving logic may suffer from some degree of data-skew RA PLANE induced glitch. One common approach to reducing this effect is to add some appropriate capacitance (usually several pF) to +5V each of the 2 or 3 most significant bits. The exact value of each Figure 16. Positive Threshold Voltage Shift capacitor for a given application should be determined experi- mentally, as it will be dependent on circuit board layout and the Table III shows the glitch reduction achieved by shifting the type of driving logic used. Table II presents a few examples of threshold voltage for HCMOS, STTL, and FAST logic. how the glitch impulse may be reduced through passive Table III. Threshold Shift for Glitch Improvement1 deskewing. Logic Uncompensated Modified Resulting Table II. Bit Delay Glitch Reduction Examples1 Family Gate Glitch Threshold2 Glitch Logic Uncompensated Compensation Compensated HCMOS 74HC158 350 pV-s 1.7 V 150 pV-s Family Gate Glitch Used Glitch STTL 74S158 850 pV-s 1.0 V 200 pV-s FAST 74F158 1000 pV-s 1.3 V 480 pV-s HCMOS 74157 350 pV-s C2 = 5 pF 250 pV-s STTL 74158 850 pV-s R1 = 50 W , 600 pV-s NOTES C1 = 7 pF 1Measurements made on a modified version of the circuit shown in Figure 13, with a 1 V full scale. NOTE 2Use care in any scheme that lowers the threshold voltage since the output volt- 1Measurements were made using a modified version of the fixture shown in age compliance of the DAC is sensitive to this voltage. If the DAC is to be op- Figure 13, with resistors and capacitors placed as shown in Figure 15. Resis- erating in the voltage output mode, it is strongly suggested that the threshold tance and capacitance values were set to zero except as noted. voltage be set at least 200 mV above the output voltage full scale. As Figure 15 indicates, in some cases it may prove useful to Deglitching place a few hundred ohms of series resistance in the input line Some applications may prove so sensitive to glitch impulse that to enhance the delay effect. This approach also helps to reduce reduction of glitch impulse by an order of magnitude or more is some of the digital feedthrough glitch, as the higher frequency required. In order to realize glitch impulses this low, some sort spectral components are being filtered out of the most signifi- of sample-and-hold amplifier (SHA)-based deglitching scheme cant bits’ digital inputs. must be used. R – C BIT DESKEWING SCHEME There are high-speed SHAs available with specifications suffi- R1 cient to deglitch the AD568, however most are hybrid in design 1 BIT 1 (MSB) at costs which can be prohibitive. A high performance, low cost alternative shown in Figure 17 is a discrete SHA utilizing a FROM R2 DRIVING 2 BIT 2 high-speed monolithic op amp and high-speed DMOS FET LOGIC switches. R3 3 BIT 3 This SHA circuit uses the inverting integrator architecture. The AD841 operational amplifier used (300 MHz gain bandwidth AD568 product) is fabricated on the same high-speed process as the 4 BIT 4 AD568. The time constant formed by the 200 W resistor and the 100 pF capacitor determines the acquisition time and also band 5 BIT 5 limits the output signal to eliminate slew induced distortion. A discrete drive circuit is used to achieve the best performance 6 BIT 6 from the SD5000 quad DMOS switch. This switch driving cell is composed of MPS571 RF npn transistors and an MC10124 TTL to ECL translator. Using this technique provides both high speed and highly symmetrical drive signals for the SD5000 Figure 15. R-C Bit Deskewing Scheme switches. The switches are arranged in a single-throw double- THRESHOLD SHIFT—It is also possible to reduce the data pole (SPDT) configuration. The 360 pF “flyback” capacitor is skew by shifting the level of logic voltage threshold, V (Pin switched to the op amp summing junction during the hold mode TH 13). This can be readily accomplished by inserting some resis- to keep switching transients from feeding to the output. The ca- tance between the THRESHOLD COM pin (Pin 14) and pacitor is grounded during sample mode to minimize its effect ground, as in Figure 16. To generate threshold voltages below on acquisition time. REV. A –9–

AD568 Circuit layout for a high speed SHA is almost as critical as the ground for the AD568. The REFERENCE COMMON (and design itself. Figure 17 shows a recommended layout of the Bipolar offset when not used), should also be connected to this deglitching cell for a double sided printed circuit board. The node. layout is very compact with care taken that all critical signal All of the current that flows into the V terminal (Pin 13) from paths are short. TH the resistor tied to the 5 V logic supply (or other convenient 200W 13 12 200W positive supply) flows out the THRESHOLD COMMON (Pin +15V 14). This ground pin should be returned directly to the digital 14 11 ground plane on its own individual line. IN4735 16 9 100pF The +5 V logic supply should be decoupled to the THRESH- 360W 360W OLD COMMON. AD841 4 OUTPUT Because the V pin is connected directly to the DAC switches 10M1C24 249W 249W 6 58 5 10 75W it should be deTcHoupled to the analog output signal common. 169W 510W 169W In order to preserve proper operation of the DAC switches, the 3 4 digital and analog grounds need to eventually be tied together. –5V –15V –5V 500pF 1 This connection between the ground planes should be made –15V within 1/2" of the DAC. 20kW The Use of Ground and Power Planes TO PIN 2 SD5000 If used properly, ground planes can perform a myriad of func- 1.6W 0.39µF tions on high-speed circuit boards: bypassing, shielding, current transport, etc. In mixed signal design, the analog and digital por- tions of the board should be distinct from one another, with the Figure 17.High Performance Deglitcher analog ground plane covering analog signal traces and the digital Grounding Rules ground plane confined to areas covering digital interconnect. The AD568 brings out separate reference, output, and digital The two ground planes should be connected at or near the power grounds. This allows for optimum management of signal DAC. Care should be taken to insure that the ground plane is ground currents for low noise and high-speed-settling perfor- uninterrupted over crucial signal paths. On the digital side, this mance. The separate ground returns are provided to minimize includes the digital input lines running to the DAC and any changes in current flow in the analog signal paths. In this way, clock lines. On the analog side, this incudes the DAC output logic return currents are not summed into the same return path signal as well as the supply feeders. The use of side runs or with the analog signals. planes in the routing of power lines is also recommended. This It is important to understand which supply and signal currents serves the dual function of providing a low series impedance are flowing in which grounds so that they may be returned to power supply to the part as well as providing some ‘‘free’’ ca- the proper power supply in the best possible way. pacitive decoupling to the appropriate ground plane. Figure The majority of the current that flows into the V supply (Pin 18 illustrates many of the points discussed above. If more layers CC 24) flows out (depending on the DAC input code) either the of interconnect are available, even better results are possible. ANALOG COMMON (Pin 18), the LADDER COMMON Using the Right Bypass Capacitors (Pin 17), and/or IOUT (Pin 20). Probably the most important external components associated The current in the LADDER COMMON is configured to be with any high-speed design are the capacitors used to bypass code independent when the output current is being summed the power supplies. Both selection and placement of these ca- into a virtual ground. If I is operated into its own output im- pacitors can be critical and, to a large extent, dependent upon OUT pedance (or in any unbuffered voltage output mode) the current the specifics of the system configurations. The dominant consid- in LADDER COMMON will become partially code dependent. eration in selection of bypass capacitors for the AD568 is mini- mization of series resistance and inductance. Many capacitors The current in the ANALOG COMMON (Pin 18) is an ap- will begin to look inductive at 20 MHz and above, the very fre- proximate complement of the current in I , i.e., zero when OUT quencies we are most interested in bypassing. Ceramic and film- the DAC is at full scale and approximately 10 mA at zero input type capacitors generally feature lower series inductance than code. tantalum or electrolytic types. A few general rules are of univer- A relatively constant current (not code dependent) flows out the sal use when approaching the problem of bypassing: REFERENCE COMMON (Pin 23). Bypass capacitors should be installed on the printed circuit The current flowing out of the V supply (Pin 22) comes from board with the shortest possible leads consistent with reliable EE a combination of reference ground and BIPOLAR OFFSET construction. This helps to minimize series inductance in the (Pin 21). The plus and minus 15 V supplies are decoupled to leads. Chip capacitors are optimal in this respect. the REFERENCE COMMON. Some series inductance between the DAC supply pins and the The ground side of the load resistor R , ANALOG COMMON power supply plane often helps to filter out high-frequency L and LADDER COMMON should be tied together as close to power supply noise. This inductance can be generated using a the package pins as possible. The analog output voltage is then small ferrite bead. referred to this node and thus it becomes the “high quality” –10– REV. A

AD568 High-Speed Interconnect and Routing ANALOG GROUND DIGITAL GROUND CLOCK PLANE It is essential that care be taken in the signal and power ground PLANE +15V circuits to avoid inducing extraneous voltage drops in the signal ground paths. It is suggested that all connections be short and –15V direct, and as physically close to the package as possible, so that the length of any conduction path shared by external compo- nents will be minimized. When runs exceed an inch or so in INPUT OUTPUT length, some type of termination resistor may be required. The WORDS necessity and value of this resistor will be dependent upon the logic family used. For maximum ac performance, the DAC should be mounted di- 5V rectly to the circuit board; sockets should not be used as they in- AD568 troduce unwanted capacitive coupling between adjacent pins of SETTLING/GLITCH 5V EVALUATION BOARD the device. Applications Component Side ANALOG VCC 1 (cid:109)s, 12-BIT SUCCESSIVE APPROXIMATION A/D CONVERTER ANALOG VEE The AD568’s unique combination of high speed and true 12-bit accuracy can be used to construct a 12-bit SAR-type A/D con- verter with a sub-m s conversion time. Figure 19 shows the con- figuration used for this application. A negative analog input voltage is converted into current and brought into a summing junction with the DAC current. This summing junction is bidirectionally clamped with two Schottky diodes to limit its voltage excursion from ground. This voltage is differentially am- ANALOG +5V plified and passed to a high-speed comparator. The comparator output is latched and fed back to the successive approximation register, which is then clocked to generated the next set of codes +5V for the DAC. Foil Side Figure 18.Printed Circuit Board Layout VIN +5V –5V 0 TO –10.24V +15V –15V 0.2µF 2.5k –5V COMPARATOR LT1016 +5V 0.1µF 1k 620 620 1 V+ OUT 8 24VCC Q11 21 1 +15V 24 0.1µF 150 2 +IN OUT 7 122GD0NDSARQQ190 2109 23 REF–C1O5MV 22320.1µF 0.01µF 1kQ3 D3 34 –VIN– GLCNHD 65 23Q11 2504 Q8 18 4 IBPO 21 IN4148 10NC Q717 5 DAC IOUT 20 Q1 Q2 15 NC Q6 16 6 AD568 RL 19 D1 D2 22 NC Q5 9 7 ACOM 18 27k ANALOG 13 CP Q4 8 8 LCOM 17 GND PLANE 1 E Q3 7 9 SPAN16 NC +5V –15V 14 S Q2 6 10 SPAN 15 NC 15kW 3 CC Q1 5 11 THCOM 14 100pF 150kW 11D Q0 4 12 VTH 13 I7N4VHECR0T4ER 1k Q4 150kW PARALLEL DATA Q5 OUT +5V CONVERSION COMPLETE START COMVERT CHIP ENABLE Figure 19.AD568 1 m s Successive Approximation A/D Application REV. A –11–

AD568 Circuit Details AD5539 wideband op amp, a high-speed multiplying DAC can Figure 20 shows an approximate timing budget for the A/D con- be built. verter. If 12 cycles are to be completed in 1 m s, approximately In the application shown in Figure 21, the AD568 is used in a 80 ns is allowed for each cycle. Since the Schottky diodes clamp buffered voltage output mode to generate the input to the the voltage of the summing junction, the DAC settling time ap- AD539’s control channel. The speed of the AD568 allows proaches the current-settling value of 35 ns, and hence uses up oversampling of the control signal waveform voltage, thereby less than half the timing budget. providing increased spectral purity of the amplitude envelope To maintain simplicity, a simple clock is used that runs at a that modulates the analog input channels. constant rate throughout the conversion, with a duty cycle of The AD568 is configured in the unbuffered unipolar output approximately 90%. If absolute speed is worth the additional mode. The internal 200 W load resistor creates the 0-1 V FS complexity, the clock frequency can be increased as the conver- output signal, which is buffered and amplified to a 0-3 V range sion progresses since the DAC must settle from increasingly suitable for the control channel of the AD539. smaller steps. A 500 W input impedance exists at Pin 1, the input channel. To When seeking a cycle time of less than 100 ns, the delays gener- provide a buffer for the 0-1 V output signal from the AD568 ated by the older generation SAR registers become problematic. looking into the impedance and to achieve the full-scale range, Newer, high speed SAR logic chips are becoming available in the AD841, high-speed, fast settling op amp is included. The the classic 2504 pinout that cuts the logic overhead in half. One gain of 3 is achieved with a 2 kW resistor configured in follower example of this is Zyrel’s ZR2504. mode with a 1 kW pot and 500 W resistor. A 20 kW pot with Finding a comparator capable of keeping up with this DAC ar- connections to Pins 3, 4 and 12 is provided for offset trim. rangement is fairly difficult: it must respond to an overdrive of 250 m V (1 LSB) in less than 25 ns. Since no inexpensive com- The AD539 can accept two separate input signals, each with a nominal full-scale voltage range of – 2 V. Each signal can then parator exists with these specs, special arrangements must be be simultaneously controlled by the AD568 signal at the com- made. The LT106 comparator provides relatively quick re- sponse, but requires at least 5 mV of overdrive to maintain this mon input channels, Pins 11 and 14, applied to the AD5539 in speed. A discrete preamplifier may be used to amplify the sum- a subtracting configuration, provide the voltage output signal: ming junction voltage to sufficiently overdrive the comparator. (cid:68) (cid:86) (cid:177)(cid:86) Cblaorcek mtou astv obied eixnetrrcoidseudc ining tchoem lapyaoruatto orf itnhseta pbrieliatym wp/ictho mthpearator (cid:86) (cid:79)(cid:85)(cid:84) =(cid:52)(cid:48)(cid:57)(cid:54)· (cid:89)(cid:49)(cid:50)(cid:86) (cid:89)(cid:50)(cid:40)(cid:48)£ (cid:68)£ (cid:52)(cid:48)(cid:57)(cid:53)(cid:41) preamp’s additional gain. For applications where only a single channel is involved, chan- SAR PREAMP COMPARATOR nel 2, V , is tied to ground. This provides: DELAY DAC SETTLING DELAY DELAY Y2 10ns 35ns 15ns 10ns 10ns (cid:86) = (cid:68) · (cid:86)(cid:89)(cid:49)(cid:40)(cid:48)£ (cid:68)£ (cid:52)(cid:48)(cid:57)(cid:53)(cid:41) (cid:79)(cid:85)(cid:84) (cid:52)(cid:48)(cid:57)(cid:54) (cid:50)(cid:86) CLOCK PULSE Some AD539 circuit details: The control amplifier compensa- tion capacitor for Pin 2, C , must have a minimum value of C 0 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 300 pF to provide circuit stability. For improved bandwidth and feedthrough, the feedthrough capacitor between Pins 1 and 2 START OF START OF NEXT should be 5-20% of C . A Schottky diode at Pin 2 can improve CLOCK CYCLE CLOCK CYCLE C recovery time from small negative values of V . Lead lengths LATCH COMPARATOR X along the path of the high-speed signal from AD568 should be Figure 20.Typical Clock Cycle for a 1 m s SAR A/D kept at a minimum. Converter HIGH-SPEED MULTIPLYING DAC A powerful use for the AD568 is found in multiplying applica- tions, where the DAC controls the amplitude of a high-speed signal. Specifically, using the AD568 as the control voltage input signal for the AD539 60 MHz analog multiplier and –12– REV. A

AD568 +VS 12 20kW +15V –15V 4 6 0.2µF 3 VX AD841 11 1 CONTROL W1 16 0.1µF 5 10 Cff +9V 12 REF+C1O5MV 2234 0.1µF –VS D1 100pF2 HCFOMP Z1 15 5(OO0UPkTTPIOUNTAL) OFFSET 34 –IB15PVO 22210.1µF 1kW 2kW VY1IN 300C0cpF 3 CH1AD568CH114 100k –9+V9V DINIGPIUTATSL 765 AD56A8CIOORUMLT 211098 AONUATPLOUTG 5A00NWALOG +9V 10W 75W 4 I+NVPSUT OUTPUT13 180W 2.7W 0.47µF 8 LCOM 17 ANALOG SGURPOPULNYD 1µF BASE 1 10 VOUT 9 SPAN16 NC GND PLANE 10W 1µF COMMON AD5539N 8 10 SPAN 15 NC DIGITAL –9V 5 –VS 12 14 7 GND PLANE DIGITAL 1121 THCVOTMH 1134 100pF SGURPOPULNYD VY1IN 180W 3 –9V RTH 6 CINHP2UT OUTPCUHT2 11 1kW 75W CF 0.25pF – 7 INPUT Z2 10 1.5pF COMMON +5V 8 OUTPUT W2 9 2G0A0IWN 470W COMMON ADJUST (– 4% RANGE) 2.7W 0.47µF D1: THOMPSON CSFBAR – 10 OR SIMILAR SCHOTTKY DIODE –9V SHORT, DIRECT CONNECTION TO GROUND PLANE. Figure 21.Wideband Digitally Controlled Multiplier OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Pin Cerdip (Suffix Q) REV. A –13–

7 8 7/ – 9 – a 4 1 0 1 C A. S. U. N D I E T N RI P –14–