Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

7 4 V H C May 2007 T 5 74VHCT573A 7 3 tm A Octal D-Type Latch with 3-STATE Outputs O c t a Features General Description l D ■ High speed: t = 7.7ns (Typ.) at T = 25°C The VHCT573A is an advanced high speed CMOS octal - PD A T ■ High Noise Immunity: V = 2.0V, V = 0.8V latch with 3-STATE output fabricated with silicon gate y IH IL p ■ Power Down Protection is provided on all inputs and CMOS technology. It achieves the high speed operation e outputs similar to equivalent Bipolar Schottky TTL while main- L taining the CMOS low power dissipation. This 8-bit a ■ Low Noise: VOLP = 1.6V (Max.) D-type latch is controlled by a Latch Enable input (LE) tc ■ Low Power Dissipation: ICC = 4µA (Max.) @ TA = 25°C and an Output Enable input (OE). When the OE input is h w ■ Pin and function compatible with 74HCT573 HIGH, the eight outputs are in a high impedance state. i t h Protection circuits ensure that 0V to 7V can be applied to 3 the input and output(1) pins without regard to the supply - S voltage. This device can be used to interface 3V to 5V T A systems and two supply systems such as battery back T up. This circuit prevents device destruction due to mis- E matched supply and input voltages. O u Note: t p 1. Outputs in OFF-State u t s Ordering Information Package Order Number Number Package Description 74VHCT573AM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74VHCT573ASJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHCT573AMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Description Pin Names Description D –D Data Inputs 0 7 LE Latch Enable Input OE 3-STATE Output Enable Input O –O 3-STATE Outputs 0 7 ©1997 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHCT573A Rev. 1.3

7 4 Logic Symbol Functional Description V H C IEEE/IEC The VHCT573A contains eight D-type latches with T 3-STATE output buffers. When the Latch Enable (LE) 5 7 input is HIGH, data on the D inputs enters the latches. n 3 In this condition the latches are transparent, i.e., a latch A output will change state each time its D input changes. O When LE is LOW the latches store the information that c was present on the D inputs, a setup time preceding the ta HIGH-to-LOW transition of LE. The 3-STATE buffers are l D controlled by the Output Enable (OE) input. When OE is - T LOW, the buffers are enabled. When OE is HIGH the y p buffers are in the high impedance mode, but, this does e not interfere with entering new data into the latches. L a t c h w i t h 3 Truth Table -S T A Inputs Outputs T E OE LE D On O L H H H u t p L H L L u t L L X O s 0 H X X Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1997 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHCT573A Rev. 1.3 2

7 4 Absolute Maximum Ratings V H Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be C operable above the recommended operating conditions and stressing the parts to these levels is not recommended. T 5 In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. 7 3 The absolute maximum ratings are stress ratings only. A Symbol Parameter Rating O c V Supply Voltage –0.5V to +7.0V t CC a l VIN DC Input Voltage –0.5V to +7.0V D - V DC Output Voltage T OUT y Note 2 –0.5V to V + 0.5V p CC e Note 3 –0.5V to +7.0V L a IIK Input Diode Current –20mA tc I Output Diode Current(4) ±20mA h OK w IOUT DC Output Current ±25mA it h ICC DC VCC/GND Current ±75mA 3 TSTG Storage Temperature –65°C to +150°C -S T T Lead Temperature (Soldering, 10 seconds) 260°C A L T E O u Recommended Operating Conditions(5) tp u The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended t s operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Rating V Supply Voltage 4.5V to +5.5V CC V Input Voltage 0V to +5.5V IN V Output Voltage OUT Note 2 0V to V CC Note 3 0V to 5.5V T Operating Temperature –40°C to +85°C OPR t , t Input Rise and Fall Time, V = 5.0V ± 0.5V 0ns/V ~ 20ns/V r f CC Notes: 2. HIGH or LOW state. I absolute maximum rating must be observed. OUT 3. When outputs are in OFF-State or when V = 0V. CC 4. V < GND, V > V (Outputs Active). OUT OUT CC 5. Unused inputs must be held HIGH or LOW. They may not float. ©1997 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHCT573A Rev. 1.3 3

7 4 DC Electrical Characteristics V H C TA = –40°C T T = 25°C to +85°C 5 A 7 3 Symbol Parameter VCC (V) Conditions Min. Typ. Max. Min. Max. Units A VIH HIGH Level Input 4.5 2.0 2.0 V O Voltage c 5.5 2.0 2.0 t a VIL LOW Level Input 4.5 0.8 0.8 V l D Voltage 5.5 0.8 0.8 -T y VOH HIGH Level Output 4.5 VIN = VIH IOH = –50µA 4.40 4.50 4.40 V p Voltage or VIL I = –8mA 3.94 3.80 e OH L VOL LOW Level Output 4.5 VIN = VIH IOL = 50µA 0.0 0.1 0.1 V atc Voltage or VIL I = 8mA 0.36 0.44 h OL w IOZ 3-STATE Output 5.5 VIN = VIH or VIL, ±0.25 ±2.5 µA it Off-State Current V = V or GND h OUT CC 3 IIN Input Leakage 0–5.5 VIN = 5.5V or GND ±0.1 ±1.0 µA -S Current T A ICC Quiescent Supply 5.5 VIN = VCC or GND 4.0 40.0 µA T Current E O I Maximum I /Input 5.5 V = 3.4V, Other 1.35 1.50 mA CCT CC IN u Inputs = V or GND t CC p u IOFF Output Leakage 0.0 VOUT = 5.5V 0.5 5.0 µA ts Current (Power Down State) Noise Characteristics T = 25°C A Symbol Parameter V (V) Conditions Typ. Limits Units CC V (6) Quiet Output Maximum 5.0 C = 50pF 1.2 1.6 V OLP L Dynamic V OL V (6) Quiet Output Minimum 5.0 C = 50pF –1.2 –1.6 V OLV L Dynamic V OL V (6) Minimum HIGH Level 5.0 C = 50pF 2.0 V IHD L Dynamic Input Voltage V (6) Maximum LOW Level 5.0 C = 50pF 0.8 V ILD L Dynamic Input Voltage Note: 6. Parameter guaranteed by design. ©1997 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHCT573A Rev. 1.3 4

7 4 AC Electrical Characteristics V H C TA = –40°C T T = +25°C to +85°C 5 A 7 3 Symbol Parameter VCC (V) Conditions Min. Typ. Max. Min. Max. Units A tPLH, tPHL Propagation Delay 5.0 ± 0.5 CL = 15pF 7.7 12.3 1.0 13.5 ns O Time (LE to On) CL = 50pF 8.5 13.3 1.0 14.5 cta tPLH, tPHL Propagation Delay 5.0 ± 0.5 CL = 15pF 5.1 8.5 1.0 9.5 ns l D Time (D to On) CL = 50pF 5.9 9.5 1.0 10.5 -T y tPZL, tPZH 3-STATE Output 5.0 ± 0.5 RL = 1kΩ CL = 15pF 6.3 10.9 1.0 12.5 ns p Enable Time C = 50pF 7.1 11.9 1.0 13.5 e L L tPLZ, tPHZ 3-STATE Output 5.0 ± 0.5 RL = 1kΩ CL = 50pF 8.8 11.2 1.0 12.0 ns atc Disable Time h t , t Output to Output 5.0 ± 0.5 (7) 1.0 1.0 ns w OSLH OSHL i Skew th C Input Capacitance V = Open 4 10 10 pF 3 IN CC - S COUT Output Capacitance VCC = 5.0V 6 pF T A CPD Power Dissipation (8) 25 pF T Capacitance E O Notes: u 7. Parameter guaranteed by design. t = |t – t |; t = |t – t | tp OSLH PLH max PLH min OSHL PHL max PHL min u 8. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating ts current consumption without load. Average operating current can be obtained by the equation: I (Opr.) = C • V • f + I / 8 (per F/F). The total C when n pcs. of the Latch operates can be CC PD CC IN CC PD calculated by the equation: C (total) = 14 + 13n. PD AC Operating Requirements T = +25°C T = –40°C to +85°C A A Symbol Parameter V (V) Min. Typ. Max. Min. Max. Units CC t (H) Minimum Pulse Width (LE) 5.0 ± 0.5 6.5 8.5 ns W t Minimum Set-Up Time 5.0 ± 0.5 1.5 1.5 ns S t Minimum Hold Time 5.0 ± 0.5 3.5 3.5 ns H ©1997 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHCT573A Rev. 1.3 5

7 4 Physical Dimensions V H Dimensions are in millimeters unless otherwise noted. C T 5 7 3 A O c t a l D - T y p e L a t c h w i t h 3 - S T A T E O u t p u t s Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B ©1997 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHCT573A Rev. 1.3 6

7 4 Physical Dimensions (Continued) V H Dimensions are in millimeters unless otherwise noted. C T 5 7 3 A O c t a l D - T y p e L a t c h w i t h 3 - S T A T E O u t p u t s Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D ©1997 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHCT573A Rev. 1.3 7

7 4 Physical Dimensions (Continued) V H Dimensions are in millimeters unless otherwise noted. C T 5 7 3 A O c t a l D - T y p e L a t c h w i t h 3 - S T A T E O u t p u t s Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 ©1997 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHCT573A Rev. 1.3 8

7 4 V H C T 5 7 TRADEMARKS 3 A ThefollowingareregisteredandunregisteredtrademarksFairchildSemiconductorownsorisauthorizedtouseandisnotintendedtobean exhaustivelistofallsuchtrademarks. O ACEx® HiSeC™ Power-SPM™ TinyBuck™ ct Acrosstheboard.Aroundtheworld.™ i-Lo™ PowerTrench® TinyLogic® a l ActiveArray™ ImpliedDisconnect™ ProgrammableActiveDroop™ TINYOPTO™ D Bottomless™ IntelliMAX™ QFET® TinyPower™ - T BuilditNow™ ISOPLANAR™ QS™ TinyWire™ y CoolFET™ MICROCOUPLER™ QTOptoelectronics™ TruTranslation™ p CorePLUS™ MicroPak™ QuietSeries™ µSerDes™ e CROSSVOLT™ MICROWIRE™ RapidConfigure™ UHC® La CTL™ Motion-SPM™ RapidConnect™ UniFET™ t c CurrentTransferLogic™ MSX™ ScalarPump™ VCX™ h DOME™ MSXPro™ SMARTSTART™ Wire™ w E2CMOS™ OCX™ SPM® i EcoSPARK® OCXPro™ STEALTH™ th EnSigna™ OPTOLOGIC® SuperFET™ 3 FACTQuietSeries™ OPTOPLANAR® SuperSOT™-3 -S FACT® PACMAN™ SuperSOT™-6 T FAST® PDP-SPM™ SuperSOT™-8 A FASTr™ POP™ SyncFET™ TE FPS™ Power220® TCM™ FRFET® Power247® ThePowerFranchise® O u GlobalOptoisolator™ PowerEdge™ ™ t GTO™ PowerSaver™ TinyBoost™ pu t s DISCLAIMER FAIRCHILDSEMICONDUCTORRESERVESTHERIGHTTOMAKECHANGESWITHOUTFURTHERNOTICETOANYPRODUCTS HEREINTOIMPROVERELIABILITY,FUNCTION,ORDESIGN.FAIRCHILDDOESNOTASSUMEANYLIABILITYARISINGOUTOFTHE APPLICATIONORUSEOFANYPRODUCTORCIRCUITDESCRIBEDHEREIN;NEITHERDOESITCONVEYANYLICENSEUNDERITS PATENTRIGHTS,NORTHERIGHTSOFOTHERS.THESESPECIFICATIONSDONOTEXPANDTHETERMSOFFAIRCHILD’S WORLDWIDETERMSANDCONDITIONS,SPECIFICALLYTHEWARRANTYTHEREIN,WHICHCOVERSTHESEPRODUCTS. LIFESUPPORTPOLICY FAIRCHILD’SPRODUCTSARENOTAUTHORIZEDFORUSEASCRITICALCOMPONENTSINLIFESUPPORTDEVICESOR SYSTEMSWITHOUTTHEEXPRESSWRITTENAPPROVALOFFAIRCHILDSEMICONDUCTORCORPORATION. Asusedherein: 1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support, which, (a) are intended for surgical implant into the bodyor device, or system whose failure to perform can be (b) support or sustain life, and (c) whose failure to perform reasonablyexpectedtocausethefailureofthelifesupport when properly used in accordance with instructions for use deviceorsystem,ortoaffectitssafetyoreffectiveness. provided in the labeling, can be reasonably expected to resultinasignificantinjuryoftheuser. PRODUCTSTATUSDEFINITIONS DefinitionofTerms DatasheetIdentification ProductStatus Definition AdvanceInformation FormativeorInDesign Thisdatasheetcontainsthedesignspecificationsforproduct development.Specificationsmaychangeinanymannerwithoutnotice. Preliminary FirstProduction Thisdatasheetcontainspreliminarydata;supplementarydatawillbe publishedatalaterdate.FairchildSemiconductorreservestherightto makechangesatanytimewithoutnoticetoimprovedesign. NoIdentificationNeeded FullProduction Thisdatasheetcontainsfinalspecifications.FairchildSemiconductor reservestherighttomakechangesatanytimewithoutnoticetoimprove design. Obsolete NotInProduction Thisdatasheetcontainsspecificationsonaproductthathasbeen discontinuedbyFairchildSemiconductor.Thedatasheetisprintedfor referenceinformationonly. Rev.I27 ©1997 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHCT573A Rev. 1.3 9

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: O N Semiconductor: 74VHCT573AMTCX 74VHCT573AM 74VHCT573AMX 74VHCT573ASJX 74VHCT573AMTC