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7 4 February 1994 L Revised May 2005 C X 1 6 3 74LCX16373 7 3 Low Voltage 16-Bit Transparent Latch L o w with 5V Tolerant Inputs and Outputs V o l General Description Features ta g The LCX16373 contains sixteen non-inverting latches with (cid:1) 5V tolerant inputs and outputs e 3tio-SnTsA. TTEh eo udtepvuictse aisn db yist ein cteonndtreodll efodr. bTuhse oflriipe-nfltoepds aappppliecaar- (cid:1) 2.3V–3.6V VCC specifications provided 16 transparent to the data when the Latch Enable (LE) is (cid:1) 5.4 ns tPD max (VCC 3.3V), 20 PA ICC max -B HIGH. When LE is LOW, the data that meets the setup time (cid:1) Power down high impedance inputs and outputs it is latched. Data appears on the bus when the Output (cid:1) Supports live insertion/withdrawal (Note 1) T Ea nhaigbhle i m(OpEe)d aisn LceO Wsta. tWe.hen OE is HIGH, the outputs are in (cid:1) r24 mA output drive (VCC 3.0V) ran (cid:1) Uses proprietary noise/EMI reduction circuitry s The LCX16373 is designed for low voltage (2.5V or 3.3V) p VenCvCir aopnpmliecnatt.ions with capability of interfacing to a 5V signal (cid:1)(cid:1) LEaStDch p-ueprf opremrfaonrmcea:nce exceeds 500 mA are n The LCX16373 is fabricated with an advanced CMOS tech- Human body model ! 2000V t nology to achieve high speed operation while maintaining Machine model ! 200V L CMOS low power dissipation. (cid:1) Also packaged in plastic Fine-Pitch Ball Grid Array at c (FBGA) h Note 1: To ensure the high-impedance state during power up or down, OE w should be tied to VCC through a pull-up resistor: the minimum value or the i resistor is determined by the current-sourcing capability of the driver. th 5 V Ordering Code: T o l Order Number Package Number Package Description e r 74LCX16373G BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide a (Note 2)(Note 3) n t 74LCX16373MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide In (Note 3) p 74LCX16373MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide u t (Note 3) s Note 2: Ordering code “G” indicates Trays. a n Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. d O Logic Symbol u t p u t s © 2005 Fairchild Semiconductor Corporation DS012002 www.fairchildsemi.com

3 7 Connection Diagrams Pin Descriptions 3 6 1 X Pin Assignment for SSOP and TSSOP Pin Names Description C L OEn Output Enable Input (Active LOW) 4 7 LEn Latch Enable Input I0–I15 Inputs O0–O15 Outputs NC No Connect FBGA Pin Assignments 1 2 3 4 5 6 A O0 NC OE1 LE1 NC I0 B O2 O1 NC NC I1 I2 C O4 O3 VCC VCC I3 I4 D O6 O5 GND GND I5 I6 E O8 O7 GND GND I7 I8 F O10 O9 GND GND I9 I10 G O12 O11 VCC VCC I11 I12 H O14 O13 NC NC I13 I14 J O15 NC OE2 LE2 NC I15 Truth Tables Inputs Outputs LE1 OE1 I0–I7 O0–O7 X H X Z H L L L Pin Assignment for FBGA H L H H L L X O0 Inputs Outputs LE2 OE2 I8–I15 O8–O15 X H X Z H L L L H L H H L L X O0 H HIGH Voltage Level L LOW Voltage Level (Top Thru View) X Immaterial Z High Impedance O0 Previous O0 before HIGH-to-LOW transition of Latch Enable www.fairchildsemi.com 2

7 Functional Description 4 L The LCX16373 contains sixteen D-type latches with its I input changes. When LEn is LOW, the latches store CX 3-STATE standard outputs. The device is byte controlled information that was present on the I inputs a setup time 1 with each byte functioning identically, but independent of preceding the HIGH-to-LOW transition of LEn. The 6 the other. Control pins can be shorted together to obtain full 3-STATE standard outputs are controlled by the Output 37 16-bit operation. The following description applies to each Enable (OEn) input. When OEn is LOW, the standard out- 3 byte. When the Latch Enable (LEn) input is HIGH, data on puts are in the 2-state mode. When OEn is HIGH, the stan- the In enters the latches. In this condition the latches are dard outputs are in the high impedance mode but this does transparent, i.e. a latch output will change state each time not interfere with entering new data into the latches. Logic Diagrams Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com

3 7 Absolute Maximum Ratings 3 (Note 4) 6 1 Symbol Parameter Value Conditions Units X C VCC Supply Voltage (cid:16)0.5 to (cid:14)7.0 V 4L VI DC Input Voltage (cid:16)0.5 to (cid:14)7.0 V 7 VO DC Output Voltage (cid:16)0.5 to (cid:14)7.0 Output in 3-STATE V (cid:16)0.5 to VCC (cid:14) 0.5 Output in HIGH or LOW State (Note 5) IIK DC Input Diode Current (cid:16)50 VI (cid:31) GND mA IOK DC Output Diode Current (cid:16)50 VO (cid:31) GND mA (cid:14)50 VO ! VCC IO DC Output Source/Sink Current r50 mA ICC DC Supply Current per Supply Pin r100 mA IGND DC Ground Current per Ground Pin r100 mA TSTG Storage Temperature (cid:16)65 to (cid:14)150 qC Recommended Operating Conditions (Note 6) Symbol Parameter Min Max Units VCC Supply Voltage Operating 2.0 3.6 V Data Retention 1.5 3.6 VI Input Voltage 0 5.5 V VO Output Voltage HIGH or LOW State 0 VCC V 3-STATE 0 5.5 IOH/IOL Output Current VCC 3.0V (cid:16) 3.6V r24 VCC 2.7V (cid:16) 3.0V r12 mA VCC 2.3V (cid:16) 2.7V r8 TA Free-Air Operating Temperature (cid:16)40 85 qC ’t/’V Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V 0 10 ns/V Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom- mended Operating Conditions” table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics VCC TA (cid:16)40qC to (cid:14)85qC Symbol Parameter Conditions Units (V) Min Max VIH HIGH Level Input Voltage 2.3 (cid:16) 2.7 1.7 V 2.7 (cid:16) 3.6 2.0 VIL LOW Level Input Voltage 2.3 (cid:16) 2.7 0.7 V 2.7 (cid:16) 3.6 0.8 VOH HIGH Level Output Voltage IOH (cid:16)100 PA 2.3 (cid:16) 3.6 VCC (cid:16) 0.2 IOH 8 mA 2.3 1.8 IOH (cid:16)12 mA 2.7 2.2 V IOH (cid:16)18 mA 3.0 2.4 IOH (cid:16)24 mA 3.0 2.2 VOL LOW Level Output Voltage IOL 100 PA 2.3 (cid:16) 3.6 0.2 IOL 8 mA 2.3 0.6 IOL 12 mA 2.7 0.4 V IOL 16 mA 3.0 0.4 IOL 24 mA 3.0 0.55 II Input Leakage Current 0 d VI d 5.5V 2.3 (cid:16) 3.6 r5.0 PA IOZ 3-STATE Output Leakage 0 d VO d 5.5V 2.3 (cid:16) 3.6 r5.0 PA VI VIH or VIL IOFF Power-Off Leakage Current VI or VO 5.5V 0 10 PA www.fairchildsemi.com 4

7 DC Electrical Characteristics 4 (Continued) L C X VCC TA (cid:16)40qC to (cid:14)85qC 1 Symbol Parameter Conditions Units 6 (V) Min Max 3 ICC Quiescent Supply Current VI VCC or GND 2.3 (cid:16) 3.6 20 PA 73 3.6V d VI, VO d 5.5V (Note 7) 2.3 (cid:16) 3.6 r20 ’ICC Increase in ICC per Input VIH VCC (cid:16)0.6V 2.3 (cid:16) 3.6 500 PA Note 7: Outputs disabled or 3-STATE only. AC Electrical Characteristics TA (cid:16)40qC to (cid:14)85qC, RL 500: VCC 3.3V r 0.3V VCC 2.7V VCC 2.5V r 0.2V Symbol Parameter Units CL 50 pF CL 50 pF CL 30 pF Min Max Min Max Min Max tPHL Propagation Delay 1.5 5.4 1.5 5.9 1.5 6.5 ns tPLH In to On 1.5 5.4 1.5 5.9 1.5 6.5 tPHL Propagation Delay 1.5 5.5 1.5 6.4 1.5 6.6 ns tPLH LE to On 1.5 5.5 1.5 6.4 1.5 6.6 tPZL Output Enable Time 1.5 6.1 1.5 6.5 1.5 7.9 ns tPZH 1.5 6.1 1.5 6.5 1.5 7.9 tPLZ Output Disable Time 1.5 6.0 1.5 6.3 1.5 7.2 ns tPHZ 1.5 6.0 1.5 6.3 1.5 7.2 tS Setup Time, In to LE 2.5 2.5 3.0 ns tH Hold Time, In to LE 1.5 1.5 2.0 ns tW LE Pulse Width 3.0 3.0 3.5 ns tOSHL Output to Output Skew (Note 8) 1.0 ns tOSLH 1.0 Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Dynamic Switching Characteristics VCC TA 25qC Symbol Parameter Conditions Units (V) Typical VOLP Quiet Output Dynamic Peak VOL CL 50 pF, VIH 3.3V, VIL 0V 3.3 0.8 V CL 30 pF, VIH 2.5V, VIL 0V 2.5 0.6 VOLV Quiet Output Dynamic Valley VOL CL 50 pF, VIH 3.3V, VIL 0V 3.3 (cid:16)0.8 V CL 30 pF, VIH 2.5V, VIL 0V 2.5 (cid:16)0.6 Capacitance Symbol Parameter Conditions Typical Units CIN Input Capacitance VCC Open, VI 0V or VCC 7 pF COUT Output Capacitance VCC 3.3V, VI 0V or VCC 8 pF CPD Power Dissipation Capacitance VCC 3.3V, VI 0V or VCC, f 10 MHz 20 pF 5 www.fairchildsemi.com

3 7 AC LOADING and WAVEFORMS 3 Generic for LCX Family 6 1 X C L 4 7 FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC 3.3 r 0.3V, and 2.7V VCC x 2 at VCC 2.5 r 0.2V tPZH, tPHZ GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic 3-STATE Output Low Enable and trise and tfall Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns) VCC Symbol 3.3V r 0.3V 2.7V 2.5V r 0.2V Vmi 1.5V 1.5V VCC/2 Vmo 1.5V 1.5V VCC/2 Vx VOL (cid:14) 0.3V VOL (cid:14) 0.3V VOL (cid:14) 0.15V Vy VOH (cid:16) 0.3V VOH (cid:16) 0.3V VOH (cid:16) 0.15V www.fairchildsemi.com 6

7 Schematic Diagram 4 Generic for LCX Family L C X 1 6 3 7 3 7 www.fairchildsemi.com

3 7 Physical Dimensions 3 inches (millimeters) unless otherwise noted 6 1 X C L 4 7 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A www.fairchildsemi.com 8

7 Physical Dimensions 4 inches (millimeters) unless otherwise noted (Continued) L C X 1 6 3 7 3 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 9 www.fairchildsemi.com

s ut Physical Dimensions inches (millimeters) unless otherwise noted (Continued) p t u O d n a s t u p n I t n a r e l o T V 5 h t i w h c t a L t n e r a p s n a r T t i B - 6 1 e g a t l o V w o L 3 7 3 6 1 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide X Package Number MTD48 C L 4 7 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea- body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support to perform when properly used in accordance with device or system, or to affect its safety or effectiveness. instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the www.fairchildsemi.com user. www.fairchildsemi.com 10

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: O N Semiconductor: 74LCX16373MEAX 74LCX16373MTDX 74LCX16373MEA 74LCX16373MTD