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7 4 L C X December 2013 0 7 — L 74LCX07 o w Low Voltage Hex Buffer with Open Drain Outputs V o l t a Features General Description g e ■ 5V tolerant inputs The LCX07 contains six buffers. The inputs tolerate volt- H e ■ 2.3V to 5.5V V specifications provided ages up to 7V allowing the interface of 5V systems to 3V x ■ 2.9ns t max.C (CV = 3.3V), 10µA I max. systems. B PD CC CC u ■ Power down high impedance inputs and outputs The outputs of the LCX07 are open drain and can be f f ■■ +Im2p4lmemA eonuttsp uptr odprirvieet a(VryC nCo =is 3e./0EVM)I reduction circuitry caocntivnee cHteIGd Ht ow iroeth AeNr Do poer na cdtirvaei nL OoWutp wuitrse OtoR imfupnlcetmionesn.t er w i ■ Latch-up performance exceeds JEDEC 78 conditions The 74LCX07 is fabricated with advanced CMOS tech- th ■ ESD performance: nology to achieve high speed operation while maintain- O ing CMOS low power dissipation. p – Human body model > 2000V e n – Machine model > 200V D ■ Leadless DQFN package r a i n O u Ordering Information t p u Package t s Order Number Number Package Description 74LCX07M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LCX07SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LCX07BQX(1) MLP14A 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm 74LCX07MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Note: 1. DQFN package available in Tape and Reel only. Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX07 Rev. 1.11.1

7 4 Connection Diagram Logic Symbol L C X Pin Assignments for SOIC, SOP, and TSSOP IEEE/IEC 0 7 — L o w V o l t a g e H e x B u f f e r Pad Assignments for DQFN w i t h O p e n D r a i n O u t p u t s (Top Through View) (Bottom View) Pin Description Pin Names Description A Inputs n O Outputs n DAP No Connect Note: DAP (Die Attach Pad) ©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX07 Rev. 1.11.1 2

7 4 Absolute Maximum Ratings L C Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be X 0 operable above the recommended operating conditions and stressing the parts to these levels is not recommended. 7 In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. — The absolute maximum ratings are stress ratings only. L o Symbol Parameter Rating w V Supply Voltage –0.5V to +7.0V V CC o VI DC Input Voltage –0.5V to +7.0V lta V DC Output Voltage, Output in HIGH or LOW State(2) –0.5V to +7.0V g O e I DC Input Diode Current, V < GND –50mA H IK I e I DC Output Diode Current x OK V < GND –50mA B O u V > V +50mA ff O CC e r I DC Output Current ±50mA O w ICC DC Supply Current per Supply Pin ±100mA ith IGND DC Ground Current per Ground Pin ±100mA O p TSTG Storage Temperature –65°C to +150°C e n Note: D 2. I Absolute Maximum Rating must be observed. r O a i n O Recommended Operating Conditions(3) u t p The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended u operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not t s recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Min. Max. Units V Supply Voltage CC Operating 2.0 5.5 V Data Retention 1.5 5.5 V Input Voltage 0 5.5 V I V Output Voltage 0 5.5 V O I Output Current OL V = 4.5V–5.5V +32 mA CC V = 3.0V–3.6V +24 CC V = 2.7V–3.0V +12 CC V = 2.3V–2.7V +8 CC T Free-Air Operating Temperature –40 85 °C A ∆t / ∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V 0 10 ns / V Note: 3. Unused inputs must be held HIGH or LOW. They may not float. ©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX07 Rev. 1.11.1 3

7 4 DC Electrical Characteristics L C X TA = –40°C to +85°C 0 7 Symbol Parameter VCC (V) Conditions Min. Max. Units — VIH HIGH Level Input Voltage 2.3–2.7 1.7 V L o 2.7–3.6 2.0 w 4.5–5.5 0.7 x V V CC o l V LOW Level Input Voltage 2.3–2.7 0.7 V t IL a g 2.7–3.6 0.8 e 4.5–5.5 0.3 x V H CC e V LOW Level Output Voltage 2.3–5.5 I = 100µA 0.2 V x OL OL B 2.3 IOL = 8mA 0.6 u f 2.7 IOL = 12mA 0.4 fe r 3.0 IOL = 16mA 0.4 w 3.0 I = 24mA 0.55 it OL h 4.5 I = 32mA 0.55 O OL p II Input Leakage Current 2.3–5.5 0 ≤ VI ≤ 5.5V ±5.0 µA e n I Power-Off Leakage Current 0 V or V = 5.5V 10 µA OFF I O D ICC Quiescent Supply Current 2.3–5.5 VI = VCC or GND 10 µA ra i 2.3–5.5 3.6V ≤ V ≤ 5.5V ±10 n I O ∆ICC Increase in ICC per Input 2.3–3.6 VIH = VCC – 0.6V 500 µA u t 4.5–5.5 1 mA p u IOHZ Off State Current 2–5.5 VO = 5.5V 10 µA ts AC Electrical Characteristics T = –40°C to +85°C, R = 500Ω A L V = 5.0V ± 0.5V, V = 3.3V ± 0.3V, V = 2.7V, V = 2.5V ± 0.2V, CC CC CC CC C = 50pF C = 50pF C = 50pF C = 30pF L L L L Symbol Parameter Min. Max. Min. Max. Min Max Min Max Units t , t Propagation 0.5 3.0 0.8 3.7 1.0 4.4 0.8 3.8 ns PZL PLZ Delay Time ©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX07 Rev. 1.11.1 4

7 4 Dynamic Switching Characteristics L C X TA = 25°C 0 7 Symbol Parameter VCC (V) Conditions Typical Unit — VOLP Quiet Output Dynamic Peak VOL 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V 0.9 V L o 2.5 CL = 30pF, VIH = 2.5V, VIL = 0V 0.7 w V Quiet Output Dynamic Valley V 3.3 C = 50pF, V = 3.3V, V = 0V –0.8 V V OLV OL L IH IL o 2.5 C = 30pF, V = 2.5V, V = 0V –0.6 lt L IH IL a g e H e Capacitance x B Symbol Parameter Conditions Typical Units u f f CIN Input Capacitance VCC = Open, VI = 0V or VCC 7 pF er C Output Capacitance V = 3.3V, V = 0V or V 8 pF w OUT CC I CC i t C Power Dissipation Capacitance V = 3.3V, V = 0V or V , f = 10MHz 25 pF h PD CC I CC O p e n D r a i n O u t p u t s ©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX07 Rev. 1.11.1 5

7 4 AC Loading and Waveforms L C X 0 7 — L o w V o l t a g e H e x Test Switch B u V x 2 at V = 5.0 ± 0.5V f CC CC f e t , t 6V at V = 3.3 ± 0.3V r PZL PLZ CC w VCC x 2 at VCC = 2.5 ± 0.2V it h Figure 1. AC Test Circuit (C includes probe and jig capacitance) O L p e n D r a i n O u t p u t s 3-STATE Output Low Enable and t and t rise fall Disable Times for Logic V CC Symbol 5.0V ± 0.5V 3.3V ± 0.3V 2.7V 2.5V ± 0.2V V V / 2 1.5V 1.5V V / 2 mi CC CC V V / 2 1.5V 1.5V V / 2 mo CC CC V V + 0.3V V + 0.3V V + 0.3V V + 0.15V x OL OL OL OL V V – 0.3V V – 0.3V V – 0.3V V – 0.15V y OH OH OH OH Figure 2. Waveforms (Input Pulse Characteristics; f =1MHz, t = t = 3ns) r f ©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX07 Rev. 1.11.1 6

7 4 Tape and Reel Specification L C X Tape Format for DQFN 0 7 Package Designator Tape Section Number of Cavities Cavity Status Cover Tape Status — BQX Leader (Start End) 125 (Typ.) Empty Sealed L o Carrier 3000 Filled Sealed w Trailer (Hub End) 75 (Typ.) Empty Sealed V o l t Tape Dimensions inches (millimeters) a g e H e x B u f f e r w i t h O p e n D r a i n O u t p u t s Reel Dimensions inches (millimeters) Tape Size A B C D N W1 W2 12mm 13.0 (330.0) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) 0.488 (12.4) 0.724 (18.4) ©1999 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX07 Rev. 1.11.1 7

0.65 (cid:24)(cid:17)(cid:19)(cid:19)(cid:147)(cid:19)(cid:17)(cid:20)(cid:19) A 0.43TYP 14 8 B 6.4 (cid:23)(cid:17)(cid:23)(cid:19)(cid:147)(cid:19)(cid:17)(cid:20)(cid:19) 6.10 3.2 1.65 1 7 0.2 C B A PIN1IDENT TOPVIEW ALLLEADTIPS 0.45 RECOMMENDEDLANDPATTERN 1.2MAX SEEDETAILA +0.15 0.90 -0.10 0.20 (cid:19)(cid:17)(cid:20)(cid:19)(cid:147)(cid:19)(cid:17)(cid:19)(cid:24) 0.09 ALLLEADTIPS 0.30 0.19 C 0.1 C 0.65 0.13 A B C (cid:20)(cid:21)(cid:17)(cid:19)(cid:19)(cid:131)(cid:3)(cid:55)(cid:50)(cid:51)(cid:3)(cid:9)(cid:3)(cid:37)(cid:50)(cid:55)(cid:55)(cid:50)(cid:48) FRONTVIEW 0.09MIN NOTES: GAGEPLANE A.CONFORMSTOJEDECREGISTRATIONMO-153, VARIATIONAB,REFNOTE6 B.DIMENSIONSAREINMILLIMETERS. 0.25 0.09MIN C.DIMENSIONSAREEXCLUSIVEOFBURRS, (cid:19)(cid:131)(cid:16)(cid:3)(cid:27)(cid:131) (cid:19)(cid:17)(cid:25)(cid:147)(cid:19)(cid:17)(cid:20) MOLDFLASH,ANDTIEBAREXTRUSIONS SEATINGPLANE 1.00 D.DIMENSIONINGANDTOLERANCESPERANSI DETAILA Y14.5M,2009. E.LANDPATTERNSTANDARD:SOP65P640X110-14M. F.DRAWINGFILENAME:MKT-MTC14rev7.

None

8.75 A 8.50 7.62 14 0.65 8 14 8 B 4.00 6.00 5.60 3.80 1.70 1 7 PIN #1 1.27 0.51 1 7 IDENT. 1.27 0.35 (0.33) 0.25 M C B A LAND PATTERN RECOMMENDATION TOP VIEW 1.75 MAX A C 0.25 0.19 1.50 0.10 C 0.25 1.25 0.10 SIDE VIEW FRONT VIEW NOTES: A. CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C B. ALL DIMENSIONS ARE IN MILLIMETERS 0.50 0.25 x 45 C. DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS R0.10 GAGE D. LAND PATTERN STANDARD: PLANE SOIC127P600X145-14M R0.10 E. CONFORMS TO ASME Y14.5M, 2009 0.36 D. DRAWING FILENAME: MKT-M14Arev14 8° 0° 0.90 0.50 SEATING PLANE (1.04) DETAIL A SCALE 16 : 1

4.00MAX 2.20MAX B 3.00 1.40MAX 0.05 C A 2X 1.00 MAX 1.70 2.50 0.50TYP MAX 3.50 MAX (0.90) 0.05 C PIN1QUADRANT TOPVIEW 2X 0.50TYP 0.24TYP (cid:19)(cid:17)(cid:27)(cid:19)(cid:147)(cid:19)(cid:17)(cid:19)(cid:24) 0.10 C RECOMMENDEDLANDPATTERN (cid:19)(cid:17)(cid:21)(cid:19)(cid:147)(cid:19)(cid:17)(cid:19)(cid:24) 0.08 C (cid:19)(cid:17)(cid:19)(cid:21)(cid:24)(cid:147)(cid:19)(cid:17)(cid:19)(cid:21)(cid:24) SIDEVIEW C SEATING PLANE (cid:22)(cid:17)(cid:19)(cid:19)(cid:147)(cid:19)(cid:17)(cid:19)(cid:24) (cid:20)(cid:17)(cid:25)(cid:24)(cid:147)(cid:19)(cid:17)(cid:19)(cid:24) (cid:19)(cid:17)(cid:22)(cid:26)(cid:19)(cid:147)(cid:19)(cid:17)(cid:19)(cid:24) (14X) A.CONFORMSTOJEDECREGISTRATION PIN1IDENT MO-241,VARIATIONAA B.DIMENSIONSAREINMILLIMETERS. C.DIMENSIONSANDTOLERANCESPER ASMEY14.5M,2009. 0.50 (cid:20)(cid:17)(cid:20)(cid:24)(cid:147)(cid:19)(cid:17)(cid:19)(cid:24) D.LANDPATTERNRECOMMENDATIONIS (cid:21)(cid:17)(cid:24)(cid:19)(cid:147)(cid:19)(cid:17)(cid:19)(cid:24) EXISTINGINDUSTRYLANDPATTERN. E.DRAWINGFILENAME:MKT-MLP14Arev2. 0.50 (cid:19)(cid:17)(cid:21)(cid:24)(cid:147)(cid:19)(cid:17)(cid:19)(cid:24) (14X) 2.00 0.10 C A B 0.05 C BOTTOMVIEW

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