74HC2G86; 74HCT2G86 Dual 2-input EXCLUSIVE-OR gate Rev. 5 — 18 December 2018 Product data sheet 1. General description The 74HC2G86; 74HCT2G86 is a dual 2-input EXCLUSIVE-OR gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits • Wide supply voltage range from 2.0 V to 6.0 V • Input levels: • For 74HC2G86: CMOS level • For 74HCT2G86: TTL level • Symmetrical output impedance • High noise immunity • Low power dissipation • Balanced propagation delays • ESD protection: • HBM JESD22-A114E exceeds 2000 V • MM JESD22-A115-A exceeds 200 V • Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC2G86DP -40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads; SOT505-2 body width 3 mm; lead length 0.5 mm 74HC2G86DC -40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; SOT765-1 8 leads; body width 2.3 mm 74HCT2G86DC 4. Marking Table 2. Marking code Type number Marking code[1] 74HC2G86DP H86 74HC2G86DC H86 74HCT2G86DC T86 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

Nexperia 74HC2G86; 74HCT2G86 Dual 2-input EXCLUSIVE-OR gate 5. Functional diagram = 1 1A 1Y 1B 2A 2Y = 1 2B 001aah760 001aah761 Fig. 1. Logic symbol Fig. 2. IEC logic symbol B Y A mna040 Fig. 3. Logic diagram (one gate) 6. Pinning information 6.1. Pinning 74HC2G86 74HCT2G86 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A 001aak026 Fig. 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 6.2. Pin description Table 3. Pin description Symbol Pin Description 1A, 2A 1, 5 data input 1B, 2B 2, 6 data input GND 4 ground (0 V) 1Y, 2Y 7, 3 data output V 8 supply voltage CC 74HC_HCT2G86 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 5 — 18 December 2018 2 / 11

Nexperia 74HC2G86; 74HCT2G86 Dual 2-input EXCLUSIVE-OR gate 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level. Input Output nA nB nY L L L L H H H L H H H L 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V supply voltage -0.5 +7.0 V CC I input clamping current V < -0.5 V or V > V + 0.5 V [1] - ±20 mA IK I I CC I output clamping current V < -0.5 V or V > V + 0.5 V [1] - ±20 mA OK O O CC I output current V = -0.5 V to (V + 0.5 V) [1] - 25 mA O O CC I supply current [1] - 50 mA CC I ground current [1] -50 - mA GND T storage temperature -65 +150 °C stg P dynamic power dissipation T = -40 °C to +125 °C [2] - 300 mW D amb [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74HC2G86 74HCT2G86 Unit Min Typ Max Min Typ Max V supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V CC V input voltage 0 - V 0 - V V I CC CC V output voltage 0 - V 0 - V V O CC CC T ambient temperature -40 +25 +125 -40 +25 +125 °C amb Δt/ΔV input transition rise and V = 2.0 V - - 625 - - - ns/V CC fall rate V = 4.5 V - 1.67 139 - 1.67 139 ns/V CC V = 6.0 V - - 83 - - - ns/V CC 74HC_HCT2G86 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 5 — 18 December 2018 3 / 11

Nexperia 74HC2G86; 74HCT2G86 Dual 2-input EXCLUSIVE-OR gate 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max 74HC2G86 V HIGH-level V = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V IH CC input voltage V = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V CC V = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V CC V LOW-level V = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V IL CC input voltage V = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V CC V = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V CC V HIGH-level V = V or V OH I IH IL output voltage I = -20 μA; V = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V O CC I = -20 μA; V = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V O CC I = -20 μA; V = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V O CC I = -4.0 mA; V = 4.5 V 4.18 4.32 - 4.13 - 3.7 - V O CC I = -5.2 mA; V = 6.0 V 5.68 5.81 - 5.63 - 5.2 - V O CC V LOW-level V = V or V OL I IH IL output voltage I = 20 μA; V = 2.0 V - 0 0.1 - 0.1 - 0.1 V O CC I = 20 μA; V = 4.5 V - 0 0.1 - 0.1 - 0.1 V O CC I = 20 μA; V = 6.0 V - 0 0.1 - 0.1 - 0.1 V O CC I = 4.0 mA; V = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V O CC I = 5.2 mA; V = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V O CC I input leakage V = V or GND; V = 6.0 V - - ±0.1 - ±1.0 - ±1.0 μA I I CC CC current I supply current V = V or GND; I = 0 A; - - 1.0 - 10 - 20 μA CC I CC O V = 6.0 V CC C input - 1.5 - - - - - pF I capacitance 74HCT2G86 V HIGH-level V = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V IH CC input voltage V LOW-level V = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V IL CC input voltage V HIGH-level V = V or V ; V = 4.5 V OH I IH IL CC output voltage I = -20 μA 4.4 4.5 - 4.4 - 4.4 - V O I = -4.0 mA 4.18 4.32 - 4.13 - 3.7 - V O V LOW-level V = V or V ; V = 4.5 V OL I IH IL CC output voltage I = 20 μA - 0 0.1 - 0.1 - 0.1 V O I = 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V O I input leakage V = V or GND; V = 5.5 V - - ±0.1 - ±1.0 - ±1.0 μA I I CC CC current I supply current V = V or GND; I = 0 A; - - 1.0 - 10 - 20 μA CC I CC O V = 5.5 V CC 74HC_HCT2G86 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 5 — 18 December 2018 4 / 11

Nexperia 74HC2G86; 74HCT2G86 Dual 2-input EXCLUSIVE-OR gate Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max ΔI additional per input; - - 300 - 375 - 410 μA CC supply current V = 4.5 V to 5.5 V; CC V = V - 2.1 V; I = 0 A I CC O C input - 1.5 - - - - - pF I capacitance 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit, see Fig. 6. Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max 74HC2G86 t propagation nA, nB to nY; see Fig. 5 [1] pd delay V = 2.0 V - 34 120 - 150 - 180 ns CC V = 4.5 V - 11 20 - 25 - 36 ns CC V = 6.0 V - 9.0 17 - 21 - 30 ns CC t transition nY; see Fig. 5 [2] t time V = 2.0 V - 18 75 - 95 - 110 ns CC V = 4.5 V - 6 15 - 19 - 22 ns CC V = 6.0 V 5 13 - 16 - 20 ns CC C power per buffer; [3] - 10 - - - - - pF PD dissipation C = 50 pF; f = 1 MHz; L i capacitance V = GND to V I CC 74HCT2G86 t propagation nA, nB to nY; see Fig. 5 [1] pd delay V = 4.5 V - 11 19 - 23 - 48 ns CC t transition nY; see Fig. 5 [2] t time V = 4.5 V - 6 15 - 19 - 22 ns CC C power per buffer; [3] - 9 - - - - - pF PD dissipation C = 50 pF; f = 1 MHz; L i capacitance V = GND to V - 1.5 V I CC [1] tpd is the same as tPLH and tPHL. [2] tt is the same as tTLH and tTHL. [3] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD x VCC2 x fi x N + Σ(CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL x VCC2 x fo) = sum of the outputs. 74HC_HCT2G86 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 5 — 18 December 2018 5 / 11

Nexperia 74HC2G86; 74HCT2G86 Dual 2-input EXCLUSIVE-OR gate 11.1. Waveforms and test circuit VI nA, nB input VM GND tPHL tPLH VOH VY nY output VM VX VOL tTHL tTLH 001aak020 Measurement points are given in Table 9. V and V are typical output voltage levels that occur with the output load. OL OH Fig. 5. Propagation delay data input (nA, nB) to data output (nY) and transition time output (nY) Table 9. Measurement points Type Input Output V V V V M M X Y 74HC2G86 0.5V 0.5V 0.1V 0.9V CC CC CC CC 74HCT2G86 1.3 V 1.3 V 0.1V 0.9V CC CC tW VI 90 % negative pulse VM VM 10 % 0 V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0 V tW VCC VCC VI VO RL S1 G DUT open RT CL 001aad983 Test data is given in Table 10. Definitions for test circuit: R = Termination resistance should be equal to output impedance Z of the pulse generator; T o C = Load capacitance including jig and probe capacitance; R = Load resistance and S1 = Test selection switch. L L Fig. 6. Test circuit for measuring switching times Table 10. Test data Type Input Load S1 position V t, t C R t , t I r f L L PHL PLH 74HC2G86 GND to V ≤ 6 ns 50 pF 1 kΩ open CC 74HCT2G86 GND to 3 V ≤ 6 ns 50 pF 1 kΩ open 74HC_HCT2G86 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 5 — 18 December 2018 6 / 11

Nexperia 74HC2G86; 74HCT2G86 Dual 2-input EXCLUSIVE-OR gate 12. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 D E A X c y HE v M A Z 8 5 A A2 A1 (A3) pin 1 index θ Lp L 1 4 detail X e w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax . A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ 0.15 0.95 0.38 0.18 3.1 3.1 4.1 0.47 0.70 8° mm 1.1 0.25 0.65 0.5 0.2 0.13 0.1 0.00 0.75 0.22 0.08 2.9 2.9 3.9 0.33 0.35 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION SOT505-2 - - - 02-01-16 Fig. 7. Package outline SOT505-2 (TSSOP8) 74HC_HCT2G86 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 5 — 18 December 2018 7 / 11

Nexperia 74HC2G86; 74HCT2G86 Dual 2-input EXCLUSIVE-OR gate VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E A X c y HE v A Z 8 5 Q A2 A pin 1 index A1 (A3) θ Lp 1 4 detail X L e w bp 0 5 mm scale Dimensions (mm are the original dimensions) A Unit max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ max 0.15 0.85 0.27 0.23 2.1 2.4 3.2 0.40 0.21 0.4 8° mm nom 1 0.12 0.5 0.4 0.2 0.08 0.1 min 0.00 0.60 0.17 0.08 1.9 2.2 3.0 0.15 0.19 0.1 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. sot765-1_po Outline References European Issue date version IEC JEDEC JEITA projection 07-06-02 SOT765-1 MO-187 16-05-31 Fig. 8. Package outline SOT765-1 (VSSOP8) 74HC_HCT2G86 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 5 — 18 December 2018 8 / 11

Nexperia 74HC2G86; 74HCT2G86 Dual 2-input EXCLUSIVE-OR gate 13. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT2G86 v.5 20181218 Product data sheet - 74HC_HCT2G86 v.4 Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. • Type numbers 74HCT2G86DP, 74HC2G86GD and 74HCT2G86GD removed. 74HC_HCT2G86 v.4 20140314 Product data sheet - 74HC_HCT2G86 v.3 Modifications: • For type numbers 74HC2G86GD and 74HCT2G86GD XSON8U has changed to XSON8. 74HC_HCT2G86 v.3 20090507 Product data sheet - 74HC_HCT2G86 v.2 74HC_HCT2G86 v.2 20030728 Product specification - 74HC_HCT2G86 v.1 74HC_HCT2G86 v.1 20020717 Product specification - - 74HC_HCT2G86 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 5 — 18 December 2018 9 / 11

Nexperia 74HC2G86; 74HCT2G86 Dual 2-input EXCLUSIVE-OR gate injury, death or severe property or environmental damage. Nexperia and its 15. Legal information suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Quick reference data — The Quick reference data is an extract of the Data sheet status product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status Product Definition Applications — Applications that are described herein for any of these [1][2] status [3] products are for illustrative purposes only. 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Nexperia 74HC2G86; 74HCT2G86 Dual 2-input EXCLUSIVE-OR gate Contents 1. General description......................................................1 2. Features and benefits..................................................1 3. Ordering information....................................................1 4. Marking..........................................................................1 5. Functional diagram.......................................................2 6. Pinning information......................................................2 6.1. Pinning.........................................................................2 6.2. Pin description.............................................................2 7. Functional description.................................................3 8. Limiting values.............................................................3 9. Recommended operating conditions..........................3 10. Static characteristics..................................................4 11. Dynamic characteristics.............................................5 11.1. Waveforms and test circuit........................................6 12. Package outline..........................................................7 13. Abbreviations..............................................................9 14. Revision history..........................................................9 15. Legal information......................................................10 © Nexperia B.V. 2018. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 18 December 2018 74HC_HCT2G86 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 5 — 18 December 2018 11 / 11