25AA512 512 Kbit SPI Bus Serial EEPROM Device Selection Table Part Number VCC Range Page Size Temp. Ranges Packages 25AA512 1.8-5.5V 128 Byte I P, SN, SM, MF Features: Description: • 20 MHz max. Clock Speed The Microchip Technology Inc. 25AA512 is a 512 Kbit • Byte and Page-level Write Operations: serial EEPROM memory with byte-level and page-level - 128-byte page serial EEPROM functions. It also features Page, Sector - 5 ms max. and Chip erase functions typically associated with - No page or sector erase required Flash-based products. These functions are not required • Low-Power CMOS Technology: for byte or page write operations. The memory is - Max. Write Current: 5 mA at 5.5V, 20 MHz accessed via a simple Serial Peripheral Interface (SPI) - Read Current: 10 mA at 5.5V, 20 MHz compatible serial bus. The bus signals required are a - Standby Current: 1A at 2.5V (Deep power- clock input (SCK) plus separate data in (SI) and data out down) (SO) lines. Access to the device is controlled by a Chip • Electronic Signature for Device ID Select (CS) input. • Self-Timed Erase and Write cycles: Communication to the device can be paused via the - Page Erase (5 ms, typical) hold pin (HOLD). While the device is paused, transi- - Sector Erase (10 ms/sector, typical) tions on its inputs will be ignored, with the exception of - Bulk Erase (10 ms, typical) Chip Select, allowing the host to service higher priority • Sector Write Protection (16K byte/sector): interrupts. - Protect none, 1/4, 1/2 or all of array The 25AA512 is available in standard packages includ- • Built-In Write Protection: ing 8-lead PDIP, SOIC, and advanced 8-lead DFN - Power-on/off data protection circuitry package. All packages are Pb-free and RoHS - Write enable latch compliant. - Write-protect pin • High Reliability: Package Types (not to scale) - Endurance: 1 Million erase/write cycles - Data Retention: >200 years - ESD Protection: 4000V DFN PDIP/SOIC/SOIJ (MF) (P, SN, SM) • Temperature Ranges Supported: • P- bI-nfdreues tarinadl (RI)o:H-4S0 C°Co mtop +lia8n5t°C SCOS 21 A512 78 HVCOCLD SCOS 12 512 87 HVCOCLD Pin Function Table VWSPS 43 25A 56 SSCI K VWSPS 34 25AA 65 SSCI K Name Function CS Chip Select Input SO Serial Data Output WP Write-Protect VSS Ground SI Serial Data Input SCK Serial Clock Input HOLD Hold Input VCC Supply Voltage  2010 Microchip Technology Inc. DS22021F-page 1

25AA512 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS.........................................................................................................-0.6V to VCC +1.0V Storage temperature.................................................................................................................................-65°C to 150°C Ambient temperature under bias...............................................................................................................-40°C to 125°C ESD protection on all pins..........................................................................................................................................4kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Industrial (I)*: TA = 0°C to +85°C VCC = 1.8V to 5.5V DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 2.0V to 5.5V *Limited industrial temp range. Param. Sym. Characteristic Min. Max. Units Test Conditions No. D001 VIH1 High-level input .7 VCC VCC +1 V voltage D002 VIL1 Low-level input -0.3 0.3 VCC V VCC2.7V D003 VIL2 voltage -0.3 0.2 VCC V VCC < 2.7V D004 VOL Low-level output — 0.4 V IOL = 2.1mA D005 VOL voltage — 0.2 V IOL = 1.0mA, VCC < 2.5V D006 VOH High-level output VCC -0.2 — V IOH = -400A voltage D007 ILI Input leakage current — ±1 A CS = VCC, VIN = VSS TO VCC D008 ILO Output leakage — ±1 A CS = VCC, VOUT = VSS TO VCC current D009 CINT Internal capacitance — 7 pF TA = 25°C, CLK = 1.0MHz, (all inputs and VCC = 5.0V (Note) outputs) D010 ICC Read — 10 mA VCC = 5.5V; FCLK = 20.0MHz; — SO = Open Operating current 5 mA VCC = 2.5V; FCLK = 10.0MHz; SO = Open D011 ICC Write — 7 mA VCC = 5.5V — 5 mA VCC = 2.5V D012 ICCS — 10 A CS = VCC = 5.5V, Inputs tied to VCC or Standby current — VSS, 85°C D13 ICCSPD Deep power-down — 1 A CS = VCC = 2.5V, Inputs tied to VCC or current VSS, 85°C Note: This parameter is periodically sampled and not 100% tested. DS22021F-page 2  2010 Microchip Technology Inc.

25AA512 TABLE 1-2: AC CHARACTERISTICS Industrial (I)*: TA = 0°C to +85°C VCC = 1.8V to 5.5V AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 2.0V to 5.5V *Limited industrial temp range. Param. Sym. Characteristic Min. Max. Units Conditions No. 1 FCLK Clock frequency — 20 MHz 4.5 VCC 5.5 — 10 MHz 2.5 VCC 5.5 — 2 MHz 1.8  VCC <2.5 at 0°C to +85°C 2.0  VCC <2.5 at -40°C to +85°C 2 TCSS CS setup time 25 — ns 4.5 VCC 5.5 50 — ns 2.5 VCC 5.5 250 — ns 1.8  VCC <2.5 at 0°C to +85°C 2.0  VCC <2.5 at -40°C to +85°C 3 TCSH CS hold time 50 — ns 4.5 VCC 5.5 100 — ns 2.5 VCC 5.5 500 — ns 1.8  VCC <2.5 at 0°C to +85°C 2.0  VCC <2.5 at -40°C to +85°C (Note3) 4 TCSD CS disable time 50 — ns — 5 Tsu Data setup time 5 — ns 4.5 VCC 5.5 10 — ns 2.5 VCC 5.5 50 — ns 1.8  VCC <2.5 at 0°C to +85°C 2.0  VCC <2.5 at -40°C to +85°C 6 THD Data hold time 10 — ns 4.5 VCC 5.5 20 — ns 2.5 VCC 5.5 100 — ns 1.8  VCC <2.5 at 0°C to +85°C 2.0  VCC <2.5 at -40°C to +85°C 7 TR CLK rise time — 20 ns (Note1) 8 TF CLK fall time — 20 ns (Note1) 9 THI Clock high time 25 — ns 4.5 VCC 5.5 50 — ns 2.5 VCC 5.5 250 — ns 1.8  VCC <2.5 at 0°C to +85°C 2.0  VCC <2.5 at -40°C to +85°C 10 TLO Clock low time 25 — ns 4.5 VCC 5.5 50 — ns 2.5 VCC 5.5 250 ns 1.8  VCC <2.5 at 0°C to +85°C 2.0  VCC <2.5 at -40°C to +85°C 11 TCLD Clock delay time 50 — ns — 12 TCLE Clock enable time 50 — ns — 13 TV Output valid from clock — 25 ns 4.5 VCC 5.5 low — 50 ns 2.8 VCC 5.5 — 250 ns 1.8  VCC <2.5 at 0°C to +85°C 2.0  VCC <2.5 at -40°C to +85°C 14 THO Output hold time 0 — ns (Note1) Note1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but established by characterization and qualification. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. 3: Includes THI time.  2010 Microchip Technology Inc. DS22021F-page 3

25AA512 TABLE 1-2: AC CHARACTERISTICS (CONTINUED) Industrial (I)*: TA = 0°C to +85°C VCC = 1.8V to 5.5V AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 2.0V to 5.5V *Limited industrial temp range. Param. Sym. Characteristic Min. Max. Units Conditions No. 15 TDIS Output disable time — 25 ns 4.5 VCC 5.5 — 50 ns 2.5 VCC 5.5 — 250 ns 1.8  VCC <2.5 at 0°C to +85°C 2.0  VCC <2.5 at -40°C to +85°C (Note1) 16 THS HOLD setup time 10 — ns 4.5 VCC 5.5 20 — ns 2.5 VCC 5.5 100 — ns 1.8  VCC <2.5 at 0°C to +85°C 2.0  VCC <2.5 at -40°C to +85°C 17 THH HOLD hold time 10 — ns 4.5 VCC 5.5 20 — ns 2.5 VCC 5.5 100 — ns 1.8  VCC <2.5 at 0°C to +85°C 2.0  VCC <2.5 at -40°C to +85°C 18 THZ HOLD low to output 15 — ns 4.5 VCC 5.5 High-Z 30 — ns 2.5 VCC 5.5 150 — ns 1.8  VCC <2.5 at 0°C to +85°C 2.0  VCC <2.5 at -40°C to +85°C (Note1) 19 THV HOLD high to output 15 — ns 4.5 VCC 5.5 valid 30 — ns 2.5 VCC 5.5 150 — ns 1.8  VCC <2.5 at 0°C to +85°C 2.0  VCC <2.5 at -40°C to +85°C 20 TREL CS High to Standby — 100 s VCC = 1.8V to 5.5V mode 21 TPD CS High to Deep power- — 100 s VCC = 1.8V to 5.5V down 22 TCE Chip erase cycle time — 10 ms VCC = 1.8V to 5.5V 23 TSE Sector erase cycle time — 10 ms VCC = 1.8V to 5.5V 24 TWC Internal write cycle time — 5 ms Byte or Page mode and Page Erase 25 — Endurance 1M — E/W Page mode, 25°C, 5.5V (Note2) Cycles Note1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but established by characterization and qualification. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. 3: Includes THI time. DS22021F-page 4  2010 Microchip Technology Inc.

25AA512 TABLE 1-3: AC TEST CONDITIONS AC Waveform: VLO = 0.2V — VHI = VCC - 0.2V (Note1) VHI = 4.0V (Note2) CL = 30 pF — Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC Note 1: For VCC  4.0V 2: For VCC > 4.0V FIGURE 1-1: HOLD TIMING CS 16 17 16 17 16 17 16 17 SCK 18 19 18 19 High-Impedance High-Impedance SO n + 1 n n n - 1 n - 2 Don’t Care Don’t Care 5 SI n + 1 n n n - 1 n - 2 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 12 2 11 7 Mode 1,1 8 3 SCK Mode 0,0 5 6 SI MSB in LSB in High-Impedance SO  2010 Microchip Technology Inc. DS22021F-page 5

25AA512 FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 10 3 Mode 1,1 SCK Mode 0,0 13 15 14 SO MSB out LSB out Don’t Care SI DS22021F-page 6  2010 Microchip Technology Inc.

25AA512 2.0 FUNCTIONAL DESCRIPTION 2.1 Principles of Operation BLOCK DIAGRAM The 25AA512 is a 65,536 byte Serial EEPROM STATUS HV Generator designed to interface directly with the Serial Periph- Register eral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC® microcontrollers. It may also interface with microcon- trollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to EEPROM match the SPI protocol. I/O Control MCeomntororyl X Array Logic The 25AA512 contains an 8-bit instruction register. The Logic Dec device is accessed via the SI pin, with data being Page Latches clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. SI Table2-1 contains a list of the possible instruction SO Y Decoder bytes and format for device operation. All instructions, CS addresses, and data are transferred MSB first, LSB SCK last. Sense Amp. HOLD Data (SI) is sampled on the first rising edge of SCK R/W Control WP after CS goes low. If the clock line is shared with other VCC peripheral devices on the SPI bus, the user can assert VSS the HOLD input and place the 25AA512 in ‘HOLD’ mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. TABLE 2-1: INSTRUCTION SET Instruction Name Instruction Format Description READ 0000 0011 Read data from memory array beginning at selected address WRITE 0000 0010 Write data to memory array beginning at selected address WREN 0000 0110 Set the write enable latch (enable write operations) WRDI 0000 0100 Reset the write enable latch (disable write operations) RDSR 0000 0101 Read STATUS register WRSR 0000 0001 Write STATUS register PE 0100 0010 Page Erase – erase one page in memory array SE 1101 1000 Sector Erase – erase one sector in memory array CE 1100 0111 Chip Erase – erase all sectors in memory array RDID 1010 1011 Release from Deep power-down and read electronic signature DPD 1011 1001 Deep Power-Down mode  2010 Microchip Technology Inc. DS22021F-page 7

25AA512 Read Sequence provide clock pulses. The internal Address Pointer is automatically incremented to the next higher address The device is selected by pulling CS low. The 8-bit after each byte of data is shifted out. When the highest READ instruction is transmitted to the 25AA512 fol- address is reached (FFFFh), the address counter rolls lowed by the 16-bit address. After the correct READ over to address 0000h allowing the read cycle to be instruction and address are sent, the data stored in the continued indefinitely. The READ instruction is memory at the selected address is shifted out on the terminated by raising the CS pin (Figure2-1). SO pin. The data stored in the memory at the next address can be read sequentially by continuing to FIGURE 2-1: READ SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction 16-bit Address SI 0 0 0 0 0 0 1 1 15 14 13 12 2 1 0 Data Out High-Impedance SO 7 6 5 4 3 2 1 0 DS22021F-page 8  2010 Microchip Technology Inc.

25AA512 2.2 Write Sequence Note: Page write operations are limited to writing bytes within a single physical page, Prior to any attempt to write data to the 25AA512, the regardless of the number of bytes write enable latch must be set by issuing the WREN actually being written. Physical page instruction (Figure2-4). This is done by setting CS low boundaries start at addresses that are and then clocking out the proper instruction into the integer multiples of the page buffer size (or 25AA512. After all eight bits of the instruction are trans- ‘page size’), and end at addresses that are mitted, the CS must be brought high to set the write integer multiples of page size – 1. If a enable latch. If the write operation is initiated immedi- Page Write command attempts to write ately after the WREN instruction without CS being across a physical page boundary, the brought high, the data will not be written to the array result is that the data wraps around to the because the write enable latch will not have been beginning of the current page (overwriting properly set. data previously stored there), instead of A write sequence includes an automatic, self timed being written to the next page as might be erase cycle. It is not required to erase any portion of the expected. It is therefore necessary for the memory prior to issuing a WRITE instruction. application software to prevent page write Once the write enable latch is set, the user may operations that would attempt to cross a proceed by setting the CS low, issuing a WRITE instruc- page boundary. tion, followed by the 16-bit address, and then the data For the data to be actually written to the array, the CS to be written. Up to 128 bytes of data can be sent to the must be brought high after the Least Significant bit (D0) device before a write cycle is necessary. The only of the nth data byte has been clocked in. If CS is restriction is that all of the bytes must reside in the brought high at any other time, the write operation will same page. not be completed. Refer to Figure2-2 and Figure2-3 for more detailed illustrations on the byte write Note: When doing a write of less than 128 bytes sequence and the page write sequence, respectively. the data in the rest of the page is refreshed While the write is in progress, the STATUS register may along with the data bytes being written. be read to check the status of the WPEN, WIP, WEL, This will force the entire page to endure a BP1 and BP0 bits (Figure2-6). A read attempt of a write cycle, for this reason endurance is memory array location will not be possible during a specified per page. write cycle. When the write cycle is completed, the write enable latch is reset. FIGURE 2-2: BYTE WRITE SEQUENCE CS Twc 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction 16-bit Address Data Byte SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0 High-Impedance SO  2010 Microchip Technology Inc. DS22021F-page 9

25AA512 FIGURE 2-3: PAGE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction 16-bit Address Data Byte 1 SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0 CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 Data Byte 3 Data Byte n (128 max) SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 DS22021F-page 10  2010 Microchip Technology Inc.

25AA512 2.3 Write Enable (WREN) and Write • Power-up Disable (WRDI) • WRDI instruction successfully executed • WRSR instruction successfully executed The 25AA512 contains a write enable latch. See • WRITE instruction successfully executed Table2-4 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be • PE instruction successfully executed completed internally. The WREN instruction will set the • SE instruction successfully executed latch, and the WRDI will reset the latch. • CE instruction successfully executed The following is a list of conditions under which the write enable latch will be reset: FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 1 0 High-Impedance SO FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 10 0 High-Impedance SO  2010 Microchip Technology Inc. DS22021F-page 11

25AA512 2.4 Read Status Register Instruction The Write Enable Latch (WEL) bit indicates the status (RDSR) of the write enable latch and is read-only. When set to a ‘1’, the latch allows writes to the array, when set to a The Read Status Register instruction (RDSR) provides ‘0’, the latch prohibits writes to the array. The state of access to the STATUS register. The STATUS register this bit can always be updated via the WREN or WRDI may be read at any time, even during a write cycle. The commands regardless of the state of write protection STATUS register is formatted as follows: on the STATUS register. These commands are shown in Figure2-4 and Figure2-5. TABLE 2-2: STATUS REGISTER The Block Protection (BP0 and BP1) bits indicate 7 6 5 4 3 2 1 0 which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction. These W/R – – – W/R W/R R R bits are nonvolatile, and are shown in Table2-3. WPEN X X X BP1 BP0 WEL WIP See Figure2-6 for the RDSR timing sequence. W/R = writable/readable. R = read-only. The Write-In-Process (WIP) bit indicates whether the 25AA512 is busy with a write operation. When set to a ‘1’, a write is in progress, when set to a ‘0’, no write is in progress. This bit is read-only. FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction SI 0 0 0 0 0 1 0 1 Data from STATUS Register High-Impedance SO 7 6 5 4 3 2 1 0 DS22021F-page 12  2010 Microchip Technology Inc.

25AA512 2.5 Write Status Register Instruction The Write-Protect Enable (WPEN) bit is a nonvolatile (WRSR) bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable The Write Status Register instruction (WRSR) allows the (WPEN) bit in the STATUS register control the user to write to the nonvolatile bits in the STATUS programmable hardware write-protect feature. Hard- register as shown in Table2-2. The user is able to ware write protection is enabled when WP pin is low select one of four levels of protection for the array by and the WPEN bit is high. Hardware write protection is writing to the appropriate bits in the STATUS register. disabled when either the WP pin is high or the WPEN The array is divided up into four segments. The user bit is low. When the chip is hardware write-protected, has the ability to write-protect none, one, two or all four only writes to nonvolatile bits in the STATUS register of the segments of the array. The partitioning is are disabled. See Table2-4 for a matrix of functionality controlled as shown in Table2-3. on the WPEN bit. See Figure2-7 for the WRSR timing sequence. TABLE 2-3: ARRAY PROTECTION Array Addresses Array Addresses BP1 BP0 Write-Protected Unprotected 0 0 none All (Sectors 0, 1, 2 & 3) (0000h-FFFFh) 0 1 Upper 1/4 (Sector 3) Lower 3/4 (Sectors 0, 1 & 2) (C000h-FFFFh) (0000h-BFFFh) 1 0 Upper 1/2 (Sectors 2 & 3) Lower 1/2 (Sectors 0 & 1) (8000h-FFFFh) (0000h-7FFFh) 1 1 All (Sectors 0, 1, 2 & 3) none (0000h-FFFFh) FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction Data to STATUS Register SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 High-Impedance SO  2010 Microchip Technology Inc. DS22021F-page 13

25AA512 2.6 Data Protection 2.7 Power-On State The following protection has been implemented to The 25AA512 powers on in the following state: prevent inadvertent writes to the array: • The device is in low-power Standby mode • The write enable latch is reset on power-up (CS=1) • A write enable instruction must be issued to set • The write enable latch is reset the write enable latch • SO is in high-impedance state • After a byte write, page write or STATUS register • A high-to-low-level transition on CS is required to write, the write enable latch is reset enter active state • CS must be set high after the proper number of clock cycles to start an internal write cycle • Access to the array during an internal write cycle is ignored and programming is continued TABLE 2-4: WRITE-PROTECT FUNCTIONALITY MATRIX WEL WPEN WP Protected Blocks Unprotected Blocks STATUS Register (SR bit 1) (SR bit 7) (pin 3) 0 x x Protected Protected Protected 1 0 x Protected Writable Writable 1 1 0 (low) Protected Writable Protected 1 1 1 (high) Protected Writable Writable x = don’t care DS22021F-page 14  2010 Microchip Technology Inc.

25AA512 2.8 PAGE ERASE The PAGE ERASE instruction will erase all bits (FFh) CS must then be driven high after the last bit of the inside the given page. A Write Enable (WREN) instruc- address or the PAGE ERASE will not execute. Once tion must be given prior to attempting a PAGE ERASE. the CS is driven high the self-timed PAGE ERASE This is done by setting CS low and then clocking out cycle is started. The WIP bit in the STATUS register the proper instruction into the 25AA512. After all eight can be read to determine when the PAGE ERASE cycle bits of the instruction are transmitted, the CS must be is complete. brought high to set the write enable latch. If a PAGE ERASE instruction is given to an address The PAGE ERASE instruction is entered by driving CS that has been protected by the Block Protect bits (BP0, low, followed by the instruction code (Figure2-8) and BP1) then the sequence will be aborted and no erase two address bytes. Any address inside the page to be will occur. erased is a valid address. FIGURE 2-8: PAGE ERASE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 SCK Instruction 16-bit Address SI 1 1 0 1 1 0 0 0 15 14 13 12 2 1 0 High-Impedance SO  2010 Microchip Technology Inc. DS22021F-page 15

25AA512 2.9 SECTOR ERASE The SECTOR ERASE instruction will erase all bits CS must then be driven high after the last bit of the (FFh) inside the given sector. A Write Enable (WREN) address or the SECTOR ERASE will not execute. Once instruction must be given prior to attempting a SECTOR the CS is driven high the self-timed SECTOR ERASE ERASE. This is done by setting CS low and then clock- cycle is started. The WIP bit in the STATUS register ing out the proper instruction into the 25AA512. After can be read to determine when the SECTOR ERASE all eight bits of the instruction are transmitted, the CS cycle is complete. must be brought high to set the write enable latch. If a SECTOR ERASE instruction is given to an address The SECTOR ERASE instruction is entered by driving that has been protected by the Block Protect bits (BP0, CS low, followed by the instruction code (Figure2-9) BP1) then the sequence will be aborted and no erase and two address bytes. Any address inside the sector will occur. to be erased is a valid address. See Table2-3 for Sector Addressing. FIGURE 2-9: SECTOR ERASE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 SCK Instruction 16-bit Address SI 0 1 0 0 0 0 1 0 15 14 13 12 2 1 0 High-Impedance SO DS22021F-page 16  2010 Microchip Technology Inc.

25AA512 2.10 CHIP ERASE The CHIP ERASE instruction will erase all bits (FFh) in The CS pin must be driven high after the eighth bit of the array. A Write Enable (WREN) instruction must be the instruction code has been given or the CHIP given prior to executing a CHIP ERASE. This is done ERASE instruction will not be executed. Once the CS by setting CS low and then clocking out the proper pin is driven high the self-timed CHIP ERASE instruc- instruction into the 25AA512. After all eight bits of the tion begins. While the device is executing the CHIP instruction are transmitted, the CS must be brought ERASE instruction the WIP bit in the STATUS register high to set the write enable latch. can be read to determine when the CHIP ERASE instruction is complete. The CHIP ERASE instruction is entered by driving the CS low, followed by the instruction code (Figure2-10) The CHIP ERASE instruction is ignored if either of the onto the SI line. Block Protect bits (BP0, BP1) are not 0, meaning ¼, ½, or all of the array is protected. FIGURE 2-10: CHIP ERASE SEQUENCE CS 0 1 2 3 4 5 6 7 SCK SI 1 1 0 0 0 1 1 1 High-Impedance SO  2010 Microchip Technology Inc. DS22021F-page 17

25AA512 2.11 DEEP POWER-DOWN MODE Deep Power-Down mode of the 25AA512 is its lowest All instructions given during Deep Power-Down mode power consumption state. The device will not respond are ignored except the Read Electronic Signature to any of the Read or Write commands while in Deep command (RDID). The RDID command will release Power-Down mode, and therefore it can be used as an the device from Deep power-down and outputs the additional software write protection feature. electronic signature on the SO pin, and then returns the device to Standby mode after delay (T ) The Deep Power-Down mode is entered by driving CS REL low, followed by the instruction code (Figure2-11) onto Deep Power-Down mode automatically releases at the SI line, followed by driving CS high. device power-down. Once power is restored to the device it will power-up in the Standby mode. If the CS pin is not driven high after the eighth bit of the instruction code has been given, the device will not execute Deep power-down. Once the CS line is driven high there is a delay (T ) before the current settles to DP its lowest consumption. FIGURE 2-11: DEEP POWER-DOWN SEQUENCE CS 0 1 2 3 4 5 6 7 SCK SI 1 0 1 1 1 0 0 1 High-Impedance SO DS22021F-page 18  2010 Microchip Technology Inc.

25AA512 2.12 RELEASE FROM DEEP Release from Deep Power-Down mode and Read POWER-DOWN AND READ Electronic Signature is entered by driving CS low, followed by the RDID instruction code (Figure2-12) ELECTRONIC SIGNATURE and then a dummy address of 16 bits (A15-A0). After Once the device has entered Deep Power-Down the last bit of the dummy address is clock in, the 8-bit mode all instructions are ignored except the Release Electronic Signature is clocked out on the SO pin. from Deep Power-down and Read Electronic Signa- After the signature has been read out at least once, ture command. This command can also be used when the sequence can be terminated by driving CS high. the device is not in Deep power-down to read the The device will then return to Standby mode and will electronic signature out on the SO pin unless another wait to be selected so it can be given new instructions. command is being executed such as Erase, Program If additional clock cycles are sent after the electronic or Write Status Register. signature has been read once, it will continue to output the signature on the SO line until the sequence is terminated. FIGURE 2-12: RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction 16-bit Address SI 1 0 1 0 1 0 1 1 15 14 13 12 2 1 0 Electronic Signature Out High-Impedance SO 7 6 5 4 3 2 1 0 0 0 1 0 1 0 0 1 Manufacturer’s ID = 0x29 Driving CS high after the 8-bit RDID command but before the Electronic Signature has been transmitted will still ensure the device will be taken out of Deep Power-Down mode. However, there is a delay T that occurs before the device REL returns to Standby mode (I ), as shown in Figure2-13. CCS FIGURE 2-13: RELEASE FROM DEEP POWER-DOWN CS 0 1 2 3 4 5 6 7 TREL SCK Instruction SI 1 0 1 0 1 0 1 1 High-Impedance SO  2010 Microchip Technology Inc. DS22021F-page 19

25AA512 3.0 PIN DESCRIPTIONS The WP pin function is blocked when the WPEN bit in the STATUS register is low. This allows the user to The descriptions of the pins are listed in Table3-1. install the 25AA512 in a system with WP pin grounded and still be able to write to the STATUS register. The TABLE 3-1: PIN FUNCTION TABLE WP pin functions will be enabled when the WPEN bit is set high. Name Pin Number Function 3.4 Serial Input (SI) CS 1 Chip Select Input SO 2 Serial Data Output The SI pin is used to transfer data into the device. It receives instructions, addresses and data. Data is WP 3 Write-Protect Pin latched on the rising edge of the serial clock. VSS 4 Ground 3.5 Serial Clock (SCK) SI 5 Serial Data Input SCK 6 Serial Clock Input The SCK is used to synchronize the communication between a master and the 25AA512. Instructions, HOLD 7 Hold Input addresses or data present on the SI pin are latched on VCC 8 Supply Voltage the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input. 3.1 Chip Select (CS) 3.6 Hold (HOLD) A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. The HOLD pin is used to suspend transmission to the However, a programming cycle which is already 25AA512 while in the middle of a serial sequence with- initiated or in progress will be completed, regardless of out having to re-transmit the entire sequence over the CS input signal. If CS is brought high during a again. It must be held high any time this function is not program cycle, the device will go into Standby mode as being used. Once the device is selected and a serial soon as the programming cycle is complete. When the sequence is underway, the HOLD pin may be pulled device is deselected, SO goes to the high-impedance low to pause further serial communication without state, allowing multiple parts to share the same SPI resetting the serial sequence. bus. A low-to-high transition on CS after a valid write The HOLD pin should be brought low while SCK is low, sequence initiates an internal write cycle. After power- otherwise the HOLD function will not be invoked until up, a low level on CS is required prior to any sequence the next SCK high-to-low transition. The 25AA512 must being initiated. remain selected during this sequence. The SI and SCK levels are “don’t cares” during the time the device is 3.2 Serial Output (SO) paused and any transitions on these pins will be The SO pin is used to transfer data out of the 25AA512. ignored. To resume serial communication, HOLD During a read cycle, data is shifted out on this pin after should be brought high while the SCK pin is low, other- the falling edge of the serial clock. wise serial communication will not be resumed until the next SCK high-to-low transition. 3.3 Write-Protect (WP) The SO line will tri-state immediately upon a high-to- low transition of the HOLD pin, and will begin outputting This pin is used in conjunction with the WPEN bit in the again immediately upon a subsequent low-to-high STATUS register to prohibit writes to the nonvolatile transition of the HOLD pin, independent of the state of bits in the STATUS register. When WP is low and SCK. WPEN is high, writing to the nonvolatile bits in the STATUS register is disabled. All other operations function normally. When WP is high, all functions, including writes to the nonvolatile bits in the STATUS register, operate normally. If the WPEN bit is set, WP low during a STATUS register write sequence will disable writing to the STATUS register. If an internal write cycle has already begun, WP going low will have no effect on the write. DS22021F-page 20  2010 Microchip Technology Inc.

25AA512 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 8-Lead DFN Example: XXXXXXX 25AA512 T/XXXXX I/MF e3 YYWW 0728 NNN 1L7 8-Lead PDIP Example: XXXXXXXX 25AA512 T/XXXNNN I/P e 3 1L7 YYWW 0728 8-Lead SOIC Example: XXXXXXXT 25AA512I XXXXYYWW SN e 3 0728 NNN 1L7 8-Lead SOIJ Example: XXXXXXXX 25AA512 T/XXXXXX I/SMe3 YYWWNNN 07281L7 Legend: XX...X Part number or part number code T Temperature (I) Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code (2 characters for small packages) e3 Pb-free JEDEC designator for Matte Tin (Sn) Note: For very small packages with no room for the Pb-free JEDEC designator e 3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010 Microchip Technology Inc. DS22021F-page 21

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25AA512 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)%&(cid:3)(cid:4)(cid:13)&(cid:5)(cid:8)(cid:23)(cid:9)(cid:25)(cid:8)(cid:26)(cid:8)’(((cid:8)(cid:30)(cid:13)(cid:10)(cid:8)(cid:31)(cid:20)(cid:7) (cid:8)!(cid:9)(cid:15)%(cid:9)# (cid:19)(cid:20)(cid:12)(cid:5)$ 3(cid:22)(cid:21)(cid:14)&(cid:23)(cid:13)(cid:14)’(cid:22)!&(cid:14)(cid:20)"(cid:21)(cid:21)(cid:13)(cid:25)&(cid:14)(cid:10)(cid:11)(cid:20)+(cid:11)(cid:12)(cid:13)(cid:14)#(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12)!((cid:14)(cid:10)(cid:26)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:31)(cid:11)(cid:20)+(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)%(cid:19)(cid:20)(cid:11)&(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:23)&&(cid:10)244***(cid:29)’(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)’4(cid:10)(cid:11)(cid:20)+(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) N NOTE1 E1 1 2 3 D E A A2 L A1 c e eB b1 b 5(cid:25)(cid:19)&! (cid:28)71;-(cid:3) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:14)6(cid:19)’(cid:19)&! (cid:18)(cid:28)7 78(cid:18) (cid:18)(cid:7)9 7"’)(cid:13)(cid:21)(cid:14)(cid:22)%(cid:14)(cid:31)(cid:19)(cid:25)! 7 : (cid:31)(cid:19)&(cid:20)(cid:23) (cid:13) (cid:29)(cid:30)(cid:4)(cid:4)(cid:14)0(cid:3)1 (cid:24)(cid:22)(cid:10)(cid:14)&(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)&(cid:19)(cid:25)(cid:12)(cid:14)(cid:31)(cid:26)(cid:11)(cid:25)(cid:13) (cid:7) > > (cid:29)(cid:16)(cid:30)(cid:4) (cid:18)(cid:22)(cid:26)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:20)+(cid:11)(cid:12)(cid:13)(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)+(cid:25)(cid:13)!! (cid:7)(cid:16) (cid:29)(cid:30)(cid:30)/ (cid:29)(cid:30),(cid:4) (cid:29)(cid:30)(cid:6)/ 0(cid:11)!(cid:13)(cid:14)&(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)&(cid:19)(cid:25)(cid:12)(cid:14)(cid:31)(cid:26)(cid:11)(cid:25)(cid:13) (cid:7)(cid:30) (cid:29)(cid:4)(cid:30)/ > > (cid:3)(cid:23)(cid:22)"(cid:26)#(cid:13)(cid:21)(cid:14)&(cid:22)(cid:14)(cid:3)(cid:23)(cid:22)"(cid:26)#(cid:13)(cid:21)(cid:14)<(cid:19)#&(cid:23) - (cid:29)(cid:16)(cid:6)(cid:4) (cid:29),(cid:30)(cid:4) (cid:29),(cid:16)/ (cid:18)(cid:22)(cid:26)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:20)+(cid:11)(cid:12)(cid:13)(cid:14)<(cid:19)#&(cid:23) -(cid:30) (cid:29)(cid:16)(cid:5)(cid:4) (cid:29)(cid:16)/(cid:4) (cid:29)(cid:16):(cid:4) 8 (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)6(cid:13)(cid:25)(cid:12)&(cid:23) (cid:2) (cid:29),(cid:5): (cid:29),(cid:15)/ (cid:29)(cid:5)(cid:4)(cid:4) (cid:24)(cid:19)(cid:10)(cid:14)&(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)&(cid:19)(cid:25)(cid:12)(cid:14)(cid:31)(cid:26)(cid:11)(cid:25)(cid:13) 6 (cid:29)(cid:30)(cid:30)/ (cid:29)(cid:30),(cid:4) (cid:29)(cid:30)/(cid:4) 6(cid:13)(cid:11)#(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)+(cid:25)(cid:13)!! (cid:20) (cid:29)(cid:4)(cid:4): (cid:29)(cid:4)(cid:30)(cid:4) (cid:29)(cid:4)(cid:30)/ 5(cid:10)(cid:10)(cid:13)(cid:21)(cid:14)6(cid:13)(cid:11)#(cid:14)<(cid:19)#&(cid:23) )(cid:30) (cid:29)(cid:4)(cid:5)(cid:4) (cid:29)(cid:4)(cid:15)(cid:4) (cid:29)(cid:4)(cid:17)(cid:4) 6(cid:22)*(cid:13)(cid:21)(cid:14)6(cid:13)(cid:11)#(cid:14)<(cid:19)#&(cid:23) ) (cid:29)(cid:4)(cid:30)(cid:5) (cid:29)(cid:4)(cid:30): (cid:29)(cid:4)(cid:16)(cid:16) 8 (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)(cid:8)(cid:22)*(cid:14)(cid:3)(cid:10)(cid:11)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:14)? (cid:13)0 > > (cid:29)(cid:5),(cid:4) (cid:19)(cid:20)(cid:12)(cid:5)(cid:11)$ (cid:30)(cid:29) (cid:31)(cid:19)(cid:25)(cid:14)(cid:30)(cid:14) (cid:19)!"(cid:11)(cid:26)(cid:14)(cid:19)(cid:25)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:21)(cid:13)(cid:14)’(cid:11)(cid:27)(cid:14) (cid:11)(cid:21)(cid:27)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)*(cid:19)&(cid:23)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:23)(cid:11)&(cid:20)(cid:23)(cid:13)#(cid:14)(cid:11)(cid:21)(cid:13)(cid:11)(cid:29) (cid:16)(cid:29) ?(cid:14)(cid:3)(cid:19)(cid:12)(cid:25)(cid:19)%(cid:19)(cid:20)(cid:11)(cid:25)&(cid:14)1(cid:23)(cid:11)(cid:21)(cid:11)(cid:20)&(cid:13)(cid:21)(cid:19)!&(cid:19)(cid:20)(cid:29) ,(cid:29) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)!(cid:14)(cid:2)(cid:14)(cid:11)(cid:25)#(cid:14)-(cid:30)(cid:14)#(cid:22)(cid:14)(cid:25)(cid:22)&(cid:14)(cid:19)(cid:25)(cid:20)(cid:26)"#(cid:13)(cid:14)’(cid:22)(cid:26)#(cid:14)%(cid:26)(cid:11)!(cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)&(cid:21)"!(cid:19)(cid:22)(cid:25)!(cid:29)(cid:14)(cid:18)(cid:22)(cid:26)#(cid:14)%(cid:26)(cid:11)!(cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)&(cid:21)"!(cid:19)(cid:22)(cid:25)!(cid:14)!(cid:23)(cid:11)(cid:26)(cid:26)(cid:14)(cid:25)(cid:22)&(cid:14)(cid:13)$(cid:20)(cid:13)(cid:13)#(cid:14)(cid:29)(cid:4)(cid:30)(cid:4)@(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)!(cid:19)#(cid:13)(cid:29) (cid:5)(cid:29) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:19)(cid:25)(cid:12)(cid:14)(cid:11)(cid:25)#(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)(cid:7)(cid:3)(cid:18)-(cid:14).(cid:30)(cid:5)(cid:29)/(cid:18)(cid:29) 0(cid:3)12(cid:14)0(cid:11)!(cid:19)(cid:20)(cid:14)(cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:29)(cid:14)(cid:24)(cid:23)(cid:13)(cid:22)(cid:21)(cid:13)&(cid:19)(cid:20)(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)(cid:13)$(cid:11)(cid:20)&(cid:14) (cid:11)(cid:26)"(cid:13)(cid:14)!(cid:23)(cid:22)*(cid:25)(cid:14)*(cid:19)&(cid:23)(cid:22)"&(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)!(cid:29) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:24)(cid:13)(cid:20)(cid:23)(cid:25)(cid:22)(cid:26)(cid:22)(cid:12)(cid:27)(cid:2)(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12)1(cid:4)(cid:5)(cid:9)(cid:4)(cid:30):0 DS22021F-page 24  2010 Microchip Technology Inc.

25AA512 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)"(cid:30)(cid:6)(cid:10)(cid:10)(cid:8))(cid:16)(cid:12)(cid:10)(cid:13)&(cid:5)(cid:8)(cid:23)"(cid:19)(cid:25)(cid:8)(cid:26)(cid:8)(cid:19)(cid:6)**(cid:20)+(cid:18)(cid:8)’,-((cid:8)(cid:30)(cid:30)(cid:8)(cid:31)(cid:20)(cid:7) (cid:8)!")%.# (cid:19)(cid:20)(cid:12)(cid:5)$ 3(cid:22)(cid:21)(cid:14)&(cid:23)(cid:13)(cid:14)’(cid:22)!&(cid:14)(cid:20)"(cid:21)(cid:21)(cid:13)(cid:25)&(cid:14)(cid:10)(cid:11)(cid:20)+(cid:11)(cid:12)(cid:13)(cid:14)#(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12)!((cid:14)(cid:10)(cid:26)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:31)(cid:11)(cid:20)+(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)%(cid:19)(cid:20)(cid:11)&(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:23)&&(cid:10)244***(cid:29)’(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)’4(cid:10)(cid:11)(cid:20)+(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) D e N E E1 NOTE1 1 2 3 α b h h c A A2 φ A1 L L1 β 5(cid:25)(cid:19)&! (cid:18)(cid:28)66(cid:28)(cid:18)-(cid:24)-(cid:8)(cid:3) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:14)6(cid:19)’(cid:19)&! (cid:18)(cid:28)7 78(cid:18) (cid:18)(cid:7)9 7"’)(cid:13)(cid:21)(cid:14)(cid:22)%(cid:14)(cid:31)(cid:19)(cid:25)! 7 : (cid:31)(cid:19)&(cid:20)(cid:23) (cid:13) (cid:30)(cid:29)(cid:16)(cid:17)(cid:14)0(cid:3)1 8 (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14);(cid:13)(cid:19)(cid:12)(cid:23)& (cid:7) > > (cid:30)(cid:29)(cid:17)/ (cid:18)(cid:22)(cid:26)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:20)+(cid:11)(cid:12)(cid:13)(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)+(cid:25)(cid:13)!! (cid:7)(cid:16) (cid:30)(cid:29)(cid:16)/ > > (cid:3)&(cid:11)(cid:25)#(cid:22)%%(cid:14)(cid:14)? (cid:7)(cid:30) (cid:4)(cid:29)(cid:30)(cid:4) > (cid:4)(cid:29)(cid:16)/ 8 (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)<(cid:19)#&(cid:23) - (cid:15)(cid:29)(cid:4)(cid:4)(cid:14)0(cid:3)1 (cid:18)(cid:22)(cid:26)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:20)+(cid:11)(cid:12)(cid:13)(cid:14)<(cid:19)#&(cid:23) -(cid:30) ,(cid:29)(cid:6)(cid:4)(cid:14)0(cid:3)1 8 (cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)6(cid:13)(cid:25)(cid:12)&(cid:23) (cid:2) (cid:5)(cid:29)(cid:6)(cid:4)(cid:14)0(cid:3)1 1(cid:23)(cid:11)’%(cid:13)(cid:21)(cid:14)A(cid:22)(cid:10)&(cid:19)(cid:22)(cid:25)(cid:11)(cid:26)B (cid:23) (cid:4)(cid:29)(cid:16)/ > (cid:4)(cid:29)/(cid:4) 3(cid:22)(cid:22)&(cid:14)6(cid:13)(cid:25)(cid:12)&(cid:23) 6 (cid:4)(cid:29)(cid:5)(cid:4) > (cid:30)(cid:29)(cid:16)(cid:17) 3(cid:22)(cid:22)&(cid:10)(cid:21)(cid:19)(cid:25)& 6(cid:30) (cid:30)(cid:29)(cid:4)(cid:5)(cid:14)(cid:8)-3 3(cid:22)(cid:22)&(cid:14)(cid:7)(cid:25)(cid:12)(cid:26)(cid:13) (cid:3) (cid:4)C > :C 6(cid:13)(cid:11)#(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)+(cid:25)(cid:13)!! (cid:20) (cid:4)(cid:29)(cid:30)(cid:17) > (cid:4)(cid:29)(cid:16)/ 6(cid:13)(cid:11)#(cid:14)<(cid:19)#&(cid:23) ) (cid:4)(cid:29),(cid:30) > (cid:4)(cid:29)/(cid:30) (cid:18)(cid:22)(cid:26)#(cid:14)(cid:2)(cid:21)(cid:11)%&(cid:14)(cid:7)(cid:25)(cid:12)(cid:26)(cid:13)(cid:14)(cid:24)(cid:22)(cid:10) (cid:4) /C > (cid:30)/C (cid:18)(cid:22)(cid:26)#(cid:14)(cid:2)(cid:21)(cid:11)%&(cid:14)(cid:7)(cid:25)(cid:12)(cid:26)(cid:13)(cid:14)0(cid:22)&&(cid:22)’ (cid:5) /C > (cid:30)/C (cid:19)(cid:20)(cid:12)(cid:5)(cid:11)$ (cid:30)(cid:29) (cid:31)(cid:19)(cid:25)(cid:14)(cid:30)(cid:14) (cid:19)!"(cid:11)(cid:26)(cid:14)(cid:19)(cid:25)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:21)(cid:13)(cid:14)’(cid:11)(cid:27)(cid:14) (cid:11)(cid:21)(cid:27)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)*(cid:19)&(cid:23)(cid:19)(cid:25)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:23)(cid:11)&(cid:20)(cid:23)(cid:13)#(cid:14)(cid:11)(cid:21)(cid:13)(cid:11)(cid:29) (cid:16)(cid:29) ?(cid:14)(cid:3)(cid:19)(cid:12)(cid:25)(cid:19)%(cid:19)(cid:20)(cid:11)(cid:25)&(cid:14)1(cid:23)(cid:11)(cid:21)(cid:11)(cid:20)&(cid:13)(cid:21)(cid:19)!&(cid:19)(cid:20)(cid:29) ,(cid:29) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)!(cid:14)(cid:2)(cid:14)(cid:11)(cid:25)#(cid:14)-(cid:30)(cid:14)#(cid:22)(cid:14)(cid:25)(cid:22)&(cid:14)(cid:19)(cid:25)(cid:20)(cid:26)"#(cid:13)(cid:14)’(cid:22)(cid:26)#(cid:14)%(cid:26)(cid:11)!(cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)&(cid:21)"!(cid:19)(cid:22)(cid:25)!(cid:29)(cid:14)(cid:18)(cid:22)(cid:26)#(cid:14)%(cid:26)(cid:11)!(cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)&(cid:21)"!(cid:19)(cid:22)(cid:25)!(cid:14)!(cid:23)(cid:11)(cid:26)(cid:26)(cid:14)(cid:25)(cid:22)&(cid:14)(cid:13)$(cid:20)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:29)(cid:30)/(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)!(cid:19)#(cid:13)(cid:29) (cid:5)(cid:29) (cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:19)(cid:25)(cid:12)(cid:14)(cid:11)(cid:25)#(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)(cid:7)(cid:3)(cid:18)-(cid:14).(cid:30)(cid:5)(cid:29)/(cid:18)(cid:29) 0(cid:3)12 0(cid:11)!(cid:19)(cid:20)(cid:14)(cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)(cid:29)(cid:14)(cid:24)(cid:23)(cid:13)(cid:22)(cid:21)(cid:13)&(cid:19)(cid:20)(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)(cid:13)$(cid:11)(cid:20)&(cid:14) (cid:11)(cid:26)"(cid:13)(cid:14)!(cid:23)(cid:22)*(cid:25)(cid:14)*(cid:19)&(cid:23)(cid:22)"&(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)!(cid:29) (cid:8)-32 (cid:8)(cid:13)%(cid:13)(cid:21)(cid:13)(cid:25)(cid:20)(cid:13)(cid:14)(cid:2)(cid:19)’(cid:13)(cid:25)!(cid:19)(cid:22)(cid:25)((cid:14)"!"(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)*(cid:19)&(cid:23)(cid:22)"&(cid:14)&(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)((cid:14)%(cid:22)(cid:21)(cid:14)(cid:19)(cid:25)%(cid:22)(cid:21)’(cid:11)&(cid:19)(cid:22)(cid:25)(cid:14)(cid:10)"(cid:21)(cid:10)(cid:22)!(cid:13)!(cid:14)(cid:22)(cid:25)(cid:26)(cid:27)(cid:29) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:24)(cid:13)(cid:20)(cid:23)(cid:25)(cid:22)(cid:26)(cid:22)(cid:12)(cid:27)(cid:2)(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12)1(cid:4)(cid:5)(cid:9)(cid:4)/(cid:17)0  2010 Microchip Technology Inc. DS22021F-page 25

25AA512 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)"(cid:30)(cid:6)(cid:10)(cid:10)(cid:8))(cid:16)(cid:12)(cid:10)(cid:13)&(cid:5)(cid:8)(cid:23)"(cid:19)(cid:25)(cid:8)(cid:26)(cid:8)(cid:19)(cid:6)**(cid:20)+(cid:18)(cid:8)’,-((cid:8)(cid:30)(cid:30)(cid:8)(cid:31)(cid:20)(cid:7) (cid:8)!")%.# (cid:19)(cid:20)(cid:12)(cid:5)$ 3(cid:22)(cid:21)(cid:14)&(cid:23)(cid:13)(cid:14)’(cid:22)!&(cid:14)(cid:20)"(cid:21)(cid:21)(cid:13)(cid:25)&(cid:14)(cid:10)(cid:11)(cid:20)+(cid:11)(cid:12)(cid:13)(cid:14)#(cid:21)(cid:11)*(cid:19)(cid:25)(cid:12)!((cid:14)(cid:10)(cid:26)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:31)(cid:11)(cid:20)+(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)%(cid:19)(cid:20)(cid:11)&(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:23)&&(cid:10)244***(cid:29)’(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)’4(cid:10)(cid:11)(cid:20)+(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) DS22021F-page 26  2010 Microchip Technology Inc.

25AA512 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010 Microchip Technology Inc. DS22021F-page 27

25AA512 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22021F-page 28  2010 Microchip Technology Inc.

25AA512 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010 Microchip Technology Inc. DS22021F-page 29

25AA512 APPENDIX A: REVISION HISTORY Revision A Original release. Revision B (06/2007) Revised Device Selection Table; Revised Features section; Revised Table 1-1 DC Characteristics; Revised Table 1-2 AC Characteristics; Replaced Pack- age Drawings (Rev. AP); Revised Package Marking (SOIC, SOIJ); Revised Product ID section. Revision C (10/2007) Removed 25LC512 part number; New data sheet created for 25LC512 (DS22065); Revised Tables; Updates throughout. Revision D (03/2008) Revise Figures 2-11 and 2-12; Revise title to Figure 2-13; Update Package Drawings. Revision E (5/2008) Modified parameter D006 in Table 1-1; Revised Package Marking Information; Replaced Package Drawings; Revised Product ID section. Revision F (05/10) Revised Table 1-2, Param. No. 25 Conditions; Revised Section 2.2, added note; Added SOIC Land Pattern and updated SOIJ package drawings. DS22021F-page 30  2010 Microchip Technology Inc.

25AA512 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. Preliminary  2010 Microchip Technology Inc. DS22021F-page 31

25AA512 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: 25AA512 Literature Number: DS22021F Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS22021F-page 32  2010 Microchip Technology Inc.

25AA512 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X – X /XX Examples: Device Tape & Reel Temp Range Package a) 25AA512-I/SN = 512 Kbit, 1.8V Serial EEPROM, Industrial temp., SOIC package b) 25AA512T-I/SM = 512 Kbit, 1.8V Serial EEPROM, Industrial temp., Tape & Reel, SOIJ package Device: 25AA512 512 Kbit, 1.8V, 128-Byte Page SPI Serial EEPROM c) 25AA512T-I/MF = 512 Kbit, 1.8V Serial Tape & Reel: Blank = Standard packaging (tube) EEPROM, Industrial temp., Tape & Reel, DFN T = Tape & Reel package Temperature I = -40C to+85C Range: Package: MF = Micro Lead Frame (6 x 5 mm body), 8-lead P = Plastic DIP (300 mil body), 8-lead SN = Plastic SOIC (3.90 mm body), 8-lead SM = Plastic SOIJ (5.28 mm body), 8-lead  2010 Microchip Technology Inc. DS22021F-page 33

25AA512 NOTES: DS22021F-page 34  2010 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-225-0 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2010 Microchip Technology Inc. DS22021F-page 35

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: 25AA512-I/MF 25AA512-I/P 25AA512-I/SM 25AA512-I/SN 25AA512T-I/MF 25AA512T-I/SM 25AA512T-I/SN