25AA02UID 2K SPI Bus Serial EEPROM with Unique 32-Bit Serial Number Device Selection Table Part Number VCC Range Page Size Temp. Ranges Packages Unique ID Length 25AA02UID 1.8-5.5V 16 Bytes I SN, OT 32-Bit Features: Description: • Preprogrammed 32-Bit Serial Number: The Microchip Technology Inc. 25AA02UID is a 2 Kbit - Unique across all UID-family EEPROMs Serial Electrically Erasable Programmable Read-Only Memory (EEPROM) with a preprogrammed, 32-bit - Scalable to 48-bit, 64-bit, 128-bit, 256-bit, unique ID. The memory is accessed via a simple Serial and other lengths Peripheral Interface (SPI) compatible serial bus. The • 10 MHz max. Clock Frequency bus signals required are a clock input (SCK) plus sep- • Low-Power CMOS Technology: arate data in (SI) and data out (SO) lines. Access to the - Max. write current: 5 mA at 5.5V device is controlled through a Chip Select (CS) input. - Read current: 5 mA at 5.5V, 10 MHz Communication to the device can be paused via the - Standby current: 1 A at 2.5V hold pin (HOLD). While the device is paused, transi- • 256 x 8-Bit Organization tions on its inputs will be ignored, with the exception of • Write Page mode (up to 16 bytes) Chip Select, allowing the host to service higher priority interrupts. • Sequential Read • Self-Timed Erase and Write Cycles (5 ms max.) The 25AA02UID is available in the standard 8-lead SOIC and 6-lead SOT-23 packages. • Block Write Protection: - Protect none, 1/4, 1/2 or all of array Pin Function Table • Built-in Write Protection: Name Function - Power-on/off data protection circuitry - Write enable latch CS Chip Select Input - Write-protect pin SO Serial Data Output • High Reliability: WP Write-Protect - Endurance: 1,000,000 erase/write cycles VSS Ground - Data retention: >200 years SI Serial Data Input - ESD protection: >4000V • Temperature Ranges Supported: SCK Serial Clock Input - Industrial (I): -40C to +85C HOLD Hold Input • RoHS Compliant VCC Supply Voltage Package Types (not to scale) SOT-23 SOIC (OT) (SN) CS 1 8 VCC SCK 1 6 VDD SO 2 7 HOLD VSS 2 5 CS WP 3 6 SCK SI 3 4 SO VSS 4 5 SI  2013 Microchip Technology Inc. DS20005205A-page 1

25AA02UID 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS.........................................................................................................-0.6V to VCC +1.0V Storage temperature.................................................................................................................................-65°C to 150°C Ambient temperature under bias.................................................................................................................-40°C to 85°C ESD protection on all pins..........................................................................................................................................4kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V Param. Sym. Characteristic Min. Max. Units Test Conditions No. D001 VIH1 High-level Input 0.7 VCC VCC +1 V voltage D002 VIL1 Low-level Input -0.3 0.3 VCC V VCC2.7V (Note 1) Voltage D003 VIL2 -0.3 0.2 VCC V VCC < 2.7V (Note 1) D004 VOL Low-level Output — 0.4 V IOL = 2.1mA D005 VOL Voltage — 0.2 V IOL = 1.0mA, VCC < 2.5V D006 VOH High-level Output VCC -0.5 — V IOH = -400A Voltage D007 ILI Input Leakage — ±1 A CS = VCC, VIN = VSS or VCC Current D008 ILO Output Leakage — ±1 A CS = VCC, VOUT = VSS or VCC Current D009 CINT Internal Capacitance — 7 pF TA = 25°C, CLK = 1.0MHz, (all inputs and VCC = 5.0V (Note 1) outputs) D010 ICC Read — 5 mA VCC = 5.5V; FCLK = 10.0MHz; SO = Open Operating Current — 2.5 mA VCC = 2.5V; FCLK = 5.0MHz; SO = Open D011 ICC Write — 5 mA VCC = 5.5V — 3 mA VCC = 2.5V D012 ICCS Standby Current — 1 A CS = VCC = 2.5V, Inputs tied to VCC or VSS, TA = +85°C Note: This parameter is periodically sampled and not 100% tested. DS20005205A-page 2  2013 Microchip Technology Inc.

25AA02UID TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V Param. Sym. Characteristic Min. Max. Units Test Conditions No. 1 FCLK Clock Frequency — 10 MHz 4.5V VCC  5.5V — 5 MHz 2.5V VCC  4.5V — 3 MHz 1.8V VCC  2.5V 2 TCSS CS Setup Time 50 — ns 4.5V VCC  5.5V 100 — ns 2.5V VCC  4.5V 150 — ns 1.8V VCC  2.5V 3 TCSH CS Hold Time 100 — ns 4.5V VCC  5.5V 200 — ns 2.5V VCC  4.5V 250 — ns 1.8V VCC  2.5V 4 TCSD CS Disable Time 50 — ns — 5 Tsu Data Setup Time 10 — ns 4.5V VCC  5.5V 20 — ns 2.5V VCC  4.5V 30 — ns 1.8V VCC  2.5V 6 THD Data Hold Time 20 — ns 4.5V VCC  5.5V 40 — ns 2.5V VCC  4.5V 50 — ns 1.8V VCC  2.5V 7 TR CLK Rise Time — 100 ns (Note1) 8 TF CLK Fall Time — 100 ns (Note1) 9 THI Clock High Time 50 — ns 4.5V VCC  5.5V 100 — ns 2.5V VCC  4.5V 150 — ns 1.8V VCC  2.5V 10 TLO Clock Low Time 50 — ns 4.5V VCC  5.5V 100 — ns 2.5V VCC  4.5V 150 — ns 1.8V VCC  2.5V 11 TCLD Clock Delay Time 50 — ns — 12 TCLE Clock Enable Time 50 — ns — 13 TV Output Valid from Clock — 50 ns 4.5V VCC  5.5V Low — 100 ns 2.5V VCC  4.5V — 160 ns 1.8V VCC  2.5V 14 THO Output Hold Time 0 — ns (Note1) 15 TDIS Output Disable Time — 40 ns 4.5V VCC  5.5V (Note1) — 80 ns 2.5V VCC  4.5V (Note1) — 160 ns 1.8V VCC  2.5V (Note1) 16 THS HOLD Setup Time 20 — ns 4.5V VCC  5.5V 40 — ns 2.5V VCC  4.5V 80 — ns 1.8V VCC  2.5V Note1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.Microchip.com. 3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete.  2013 Microchip Technology Inc. DS20005205A-page 3

25AA02UID TABLE 1-2: AC CHARACTERISTICS (CONTINUED) AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V Param. Sym. Characteristic Min. Max. Units Test Conditions No. 17 THH HOLD Hold Time 20 — ns 4.5V VCC  5.5V 40 — ns 2.5V VCC  4.5V 80 — ns 1.8V VCC  2.5V 18 THZ HOLD Low to Output 30 — ns 4.5V VCC  5.5V (Note1) High-Z 60 — ns 2.5V VCC  4.5V (Note1) 160 — ns 1.8V VCC  2.5V (Note1) 19 THV HOLD High to Output 30 — ns 4.5V VCC  5.5V Valid 60 — ns 2.5V VCC  4.5V 160 — ns 1.8V VCC  2.5V 20 TWC Internal Write Cycle Time — 5 ms (Note 3) (byte or page) 21 — Endurance 1M — E/W 25°C, VCC = 5.5V (Note 2) Cycles Note1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.Microchip.com. 3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. TABLE 1-3: AC TEST CONDITIONS AC Waveform: VLO = 0.2V — VHI = VCC - 0.2V (Note 1) VHI = 4.0V (Note 2) CL = 100 pF — Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC Note1: For VCC  4.0V. 2: For VCC  4.0V. DS20005205A-page 4  2013 Microchip Technology Inc.

25AA02UID FIGURE 1-1: HOLD TIMING CS 17 17 16 16 SCK 18 19 High-Impedance SO n + 2 n + 1 n n n - 1 Don’t Care 5 SI n + 2 n + 1 n n n - 1 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 12 2 11 7 Mode 1,1 8 3 SCK Mode 0,0 5 6 SI MSB in LSB in High-Impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 10 3 Mode 1,1 SCK Mode 0,0 13 15 14 SO MSB out ISB out Don’t Care SI  2013 Microchip Technology Inc. DS20005205A-page 5

25AA02UID 2.0 FUNCTIONAL DESCRIPTION After setting the write enable latch, the user may proceed by driving CS low, issuing a WRITE instruction, followed by the remainder of the address, and then the 2.1 Principles of Operation data to be written. Up to 16 bytes of data can be sent to The 25AA02UID is a 256-byte Serial EEPROM the device before a write cycle is necessary. The only designed to interface directly with the Serial Peripheral restriction is that all of the bytes must reside in the Interface (SPI) port of many of today’s popular same page. Additionally, a page address begins with microcontroller families, including Microchip’s PIC® XXXX 0000 and ends with XXXX 1111. If the internal microcontrollers. It may also interface with microcon- address counter reaches XXXX 1111 and clock signals trollers that do not have a built-in SPI port by using continue to be applied to the chip, the address counter discrete I/O lines programmed properly in software to will roll back to the first address of the page and over- match the SPI protocol. write any data that previously existed in those locations. The 25AA02UID contains an 8-bit instruction register. The device is accessed via the SI pin, with data being Note: Page write operations are limited to clocked in on the rising edge of SCK. The CS pin must writing bytes within a single physical page, be low and the HOLD pin must be high for the entire regardless of the number of bytes operation. actually being written. Physical page Table2-1 contains a list of the possible instruction boundaries start at addresses that are bytes and format for device operation. All instructions, integer multiples of the page buffer size addresses, and data are transferred MSb first, LSb last. (or ‘page size’) and, end at addresses that are integer multiples of page size – 1. If a Data (SI) is sampled on the first rising edge of SCK page Write command attempts to write after CS goes low. If the clock line is shared with other across a physical page boundary, the peripheral devices on the SPI bus, the user can assert result is that the data wraps around to the the HOLD input and place the 25AA02UID in ‘HOLD’ beginning of the current page (overwriting mode. After releasing the HOLD pin, operation will data previously stored there), instead of resume from the point when the HOLD was asserted. being written to the next page as might be expected. It is therefore necessary for the 2.2 Read Sequence application software to prevent page write operations that would attempt to cross a The device is selected by pulling CS low. The 8-bit page boundary. READ instruction is transmitted to the 25AA02UID followed by an 8-bit address. See Figure 2-1 for more For the data to be actually written to the array, the CS details. must be brought high after the Least Significant bit (D0) After the correct READ instruction and address are sent, of the nth data byte has been clocked in. If CS is driven high at any other time, the write operation will not be the data stored in the memory at the selected address is shifted out on the SO pin. Data stored in the memory completed. Refer to Figure2-2 and Figure2-3 for more detailed illustrations on the byte write sequence and at the next address can be read sequentially by the page write sequence, respectively. While the write continuing to provide clock pulses to the slave. The is in progress, the STATUS register may be read to internal Address Pointer automatically increments to check the status of the WIP, WEL, BP1 and BP0 bits the next higher address after each byte of data is shifted out. When the highest address is reached (Figure2-6). Attempting to read a memory array location will not be possible during a write cycle. Polling (FFh), the address counter rolls over to address 00h, allowing the read cycle to be continued indefinitely. The the WIP bit in the STATUS register is recommended in read operation is terminated by raising the CS pin order to determine if a write cycle is in progress. When (Figure2-1). the write cycle is completed, the write enable latch is reset. 2.3 Write Sequence Prior to any attempt to write data to the 25AA02UID, the write enable latch must be set by issuing the WREN instruction (Figure2-4). This is done by setting CS low and then clocking out the proper instruction into the 25AA02UID. After all eight bits of the instruction are transmitted, CS must be driven high to set the write enable latch. If the write operation is initiated immedi- ately after the WREN instruction without CS driven high, data will not be written to the array since the write enable latch was not properly set. DS20005205A-page 6  2013 Microchip Technology Inc.

25AA02UID BLOCK DIAGRAM STATUS HV Generator Register EEPROM I/O Control Memory X Array Control Logic Logic Dec Page Latches SI SO Y Decoder CS SCK Sense Amp. HOLD R/W Control WP VCC VSS TABLE 2-1: INSTRUCTION SET Instruction Name Instruction Format Description READ 0000 x011 Read data from memory array beginning at selected address WRITE 0000 x010 Write data to memory array beginning at selected address WRDI 0000 x100 Reset the write enable latch (disable write operations) WREN 0000 x110 Set the write enable latch (enable write operations) RDSR 0000 x101 Read STATUS register WRSR 0000 x001 Write STATUS register x = don’t care FIGURE 2-1: READ SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK Instruction Address Byte SI 0 0 0 0 0 0 1 1 A7 A6 A5 A4 A3 A2 A1 A0 Data Out High-Impedance SO 7 6 5 4 3 2 1 0  2013 Microchip Technology Inc. DS20005205A-page 7

25AA02UID FIGURE 2-2: BYTE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Twc SCK Instruction Address Byte Data Byte SI 0 0 0 0 0 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0 7 6 5 4 3 2 1 0 High-Impedance SO FIGURE 2-3: PAGE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK Instruction Address Byte Data Byte 1 SI 0 0 0 0 0 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0 7 6 5 4 3 2 1 0 CS 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCK Data Byte 2 Data Byte 3 Data Byte n (16 max) SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 DS20005205A-page 8  2013 Microchip Technology Inc.

25AA02UID 2.4 Write Enable (WREN) and Write The following is a list of conditions under which the Disable (WRDI) write enable latch will be reset: • Power-up The 25AA02UID contains a write enable latch. See • WRDI instruction successfully executed Table2-4 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be • WRSR instruction successfully executed completed internally. The WREN instruction will set the • WRITE instruction successfully executed latch, and the WRDI will reset the latch. • WP pin is brought low FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 1 0 High-Impedance SO FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 0 0 High-Impedance SO  2013 Microchip Technology Inc. DS20005205A-page 9

25AA02UID 2.5 Read Status Register Instruction The Write Enable Latch (WEL) bit indicates the status (RDSR) of the write enable latch and is read-only. When set to a ‘1’, the latch allows writes to the array, when set to a The Read Status Register instruction (RDSR) provides ‘0’, the latch prohibits writes to the array. The state of access to the STATUS register. See Figure2-6 for the this bit can always be updated via the WREN or WRDI RDSR timing sequence. The STATUS register may be commands regardless of the state of write protection read at any time, even during a write cycle. The on the STATUS register. These commands are shown STATUS register is formatted as follows: in Figure2-4 and Figure2-5. The Block Protection (BP0 and BP1) bits indicate TABLE 2-2: STATUS REGISTER which blocks are currently write-protected. These bits 7 6 5 4 3 2 1 0 are set by the user issuing the WRSR instruction, which is shown in Figure 2-7. These bits are nonvolatile and – – – – W/R W/R R R are described in more detail in Table2-3. X X X X BP1 BP0 WEL WIP W/R = writable/readable. R = read-only. The Write-In-Process (WIP) bit indicates whether the 25AA02UID is busy with a write operation. When set to a ‘1’, a write is in progress, when set to a ‘0’, no write is in progress. This bit is read-only. FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction SI 0 0 0 0 0 1 0 1 Data from STATUS register High-Impedance SO 7 6 5 4 3 2 1 0 DS20005205A-page 10  2013 Microchip Technology Inc.

25AA02UID 2.6 Write Status Register Instruction TABLE 2-3: ARRAY PROTECTION (WRSR) Array Addresses BP1 BP0 Write-Protected The Write Status Register instruction (WRSR) allows the user to write to the nonvolatile bits in the STATUS 0 0 none register, as shown in Table2-2. See Figure2-7 for the 0 1 upper 1/4 WRSR timing sequence. Four levels of protection for (C0h-FFh) the array are selectable by writing to the appropriate bits in the STATUS register. The user has the ability to 1 0 upper 1/2 write-protect none, one, two, or all four of the (80h-FFh) segments of the array as shown in Table2-3. 1 1 all (00h-FFh) FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction Data to STATUS register SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 High-Impedance SO  2013 Microchip Technology Inc. DS20005205A-page 11

25AA02UID 2.7 Data Protection 2.8 Power-On State The following protection has been implemented to The 25AA02UID powers on in the following state: prevent inadvertent writes to the array: • The device is in low-power Standby mode • The write enable latch is reset on power-up (CS=1) • A write enable instruction must be issued to set • The write enable latch is reset the write enable latch • SO is in high-impedance state • After a byte write, page write or STATUS register • A high-to-low-level transition on CS is required to write, the write enable latch is reset enter active state • CS must be set high after the proper number of clock cycles to start an internal write cycle • Access to the array during an internal write cycle is ignored and programming is continued TABLE 2-4: WRITE-PROTECT FUNCTIONALITY MATRIX WP WEL Protected Blocks Unprotected Blocks STATUS Register (pin 3) (SR bit 1) 0 (low) x Protected Protected Protected 1 (high) 0 Protected Protected Protected 1 (high) 1 Protected Writable Writable x = don’t care DS20005205A-page 12  2013 Microchip Technology Inc.

25AA02UID 3.0 PREPROGRAMMED UNIQUE 3.1 Manufacturer and Device Codes 32-BIT SERIAL NUMBER In addition to the serial number, a manufacturer code is stored at location 0xFA and a device identifier is stored The 25AA02UID is programmed at the factory with a at 0xFB. The manufacturer code is fixed as 0x29. For unique 32-bit serial number stored in the upper 1/4 of the 25AA02UID, the device identifier is 0x51. The ‘5’ the array and write-protected through the STATUS indicates the SPI family and the ‘1’ indicates a 2 Kbit register. The remaining 1,536 bits are available for memory density. application use. Note: The 32-bit serial number is unique across 3.2 Factory-Programmed Write all Microchip UID-family serial EEPROM Protection devices. In order to help guard against accidental corruption of FIGURE 3-1: MEMORY ORGANIZATION the serial number, the BP1 and BP0 bits of the STATUS register are programmed at the factory to ‘0’ and ‘1’, 00h respectively, as shown in the following table: 7 6 5 4 3 2 1 0 Standard EEPROM X X X X BP1 BP0 WEL WIP — — — — 0 1 — — C0h This protects the upper 1/4 of the array (0xC0 to 0xFF) Write-Protected from write operations. This array block can be utilized Serial Number Block FFh for writing by clearing the BP bits with a Write Status Register (WRSR) instruction. Note that if this is per- The 4-byte serial number is stored in array locations formed, care must be taken to prevent overwriting the 0xFC through 0xFF, as shown in Figure3-2. serial number. FIGURE 3-2: SERIAL NUMBER PHYSICAL MEMORY MAP EXAMPLE Manufacturer Device Description 32-bit Serial Number Code Code Data 29h 51h 12h 34h 56h 78h Type Fixed Serialized Array FAh FBh FCh FDh FEh FFh Address 3.3 Extending the 32-bit Serial TABLE 3-1: EXTENDED READ EXAMPLES Number Serial Number Start Address End Address Length For applications that require serial numbers larger than 32 bits, additional data bytes can be used to pad the 0xFC 0xFF 32 bits provided serial number to meet the required length. 0xFA 0xFF 48 bits Any data byte values can be used for padding as the 0xF8 0xFF 64 bits 32-bit serial number ensures the extended serial number remains unique. 0xF0 0xFF 128 bits The padding can be performed in two ways. The first 0xE0 0xFF 256 bits method is to pad the data in software by combining the 32-bit serial number from the 25AA02UID with fixed data. The second method is to extend the number of bytes read from the 25AA02UID to meet the required length. Table3-1 shows example address ranges and their corresponding serial number lengths.  2013 Microchip Technology Inc. DS20005205A-page 13

25AA02UID 4.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table4-1. 4.5 Serial Clock (SCK) The SCK is used to synchronize the communication TABLE 4-1: PIN FUNCTION TABLE between a master and the 25AA02UID. Instructions, Name SOIC SOT-23 Function addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO CS 1 5 Chip Select Input pin is updated after the falling edge of the clock input. SO 2 4 Serial Data Output WP 3 — Write-Protect Pin 4.6 Hold (HOLD) VSS 4 2 Ground The HOLD pin is used to suspend transmission to the SI 5 3 Serial Data Input 25AA02UID while in the middle of a serial sequence SCK 6 1 Serial Clock Input without having to retransmit the entire sequence again. HOLD 7 — Hold Input It must be held high any time this function is not being used. Once the device is selected and a serial VCC 8 6 Supply Voltage sequence is underway, the HOLD pin may be pulled 4.1 Chip Select (CS) low to pause further serial communication without resetting the serial sequence. The HOLD pin must be A low level on this pin selects the device. A high level brought low while SCK is low, otherwise the HOLD deselects the device and forces it into Standby mode. function will not be invoked until the next SCK high-to- However, a programming cycle which is already low transition. The 25AA02UID must remain selected initiated or in progress will be completed, regardless of during this sequence. The SI, SCK and SO pins are in the CS input signal. If CS is brought high during a a high-impedance state during the time the device is program cycle, the device will go into Standby mode as paused and transitions on these pins will be ignored. To soon as the programming cycle is complete. When the resume serial communication, HOLD must be brought device is deselected, SO goes to the high-impedance high while the SCK pin is low, otherwise serial state, allowing multiple parts to share the same SPI communication will not resume. Lowering the HOLD bus. A low-to-high transition on CS after a valid write line at any time will tri-state the SO line. sequence initiates an internal write cycle. After power- up, a low level on CS is required prior to any sequence being initiated. 4.2 Serial Output (SO) The SO pin is used to transfer data out of the 25AA02UID. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock. 4.3 Write-Protect (WP) The WP pin is a hardware write-protect input pin. When it is low, all writes to the array or STATUS reg- ister are disabled, but any other operations function normally. When WP is high, all functions, including nonvolatile writes operate normally. At any time, when WP is low, the write enable Reset latch will be reset and programming will be inhibited. However, if a write cycle is already in progress, WP going low will not change or disable the write cycle. See Table 2-4 for the Write-Protect Functionality Matrix. 4.4 Serial Input (SI) The SI pin is used to transfer data into the device. It receives instructions, addresses and data. Data is latched on the rising edge of the serial clock. DS20005205A-page 14  2013 Microchip Technology Inc.

25AA02UID 5.0 PACKAGING INFORMATION 5.1 Package Marking Information 8-Lead SOIC Example: XXXXXXXT 25A2UIDI XXXXYYWW SN e 3 1327 NNN 1L7 6-Lead SOT-23 Example: XXXXY AAAD3 WWNNN 271L7 1st Line Marking Code Part Number SOIC SOT-23 I Temp. I Temp. 25AA02UID 25A2UIDT AAADY Legend: XX...X Part number or part number code T Temperature (I, E) Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code (2 characters for small packages) e3 Pb-free JEDEC designator for Matte Tin (Sn) Note: For very small packages with no room for the Pb-free JEDEC designator e 3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. *Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.  2013 Microchip Technology Inc. DS20005205A-page 15

25AA02UID Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20005205A-page 16  2013 Microchip Technology Inc.

25AA02UID Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2013 Microchip Technology Inc. DS20005205A-page 17

25AA02UID (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:15)(cid:21)(cid:22)(cid:8)(cid:23)(cid:8)(cid:21)(cid:6)(cid:24)(cid:24)(cid:25)(cid:26)(cid:27)(cid:8)(cid:28)(cid:29)(cid:30)(cid:31)(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"(cid:15)(cid:17)#$% (cid:21)(cid:25)(cid:12)(cid:5)& (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)!(cid:10)"(cid:31)(cid:2)(cid:8)#(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)%(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)"’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7))(cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)%(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12)*++&&&(cid:20)!(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)!+(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS20005205A-page 18  2013 Microchip Technology Inc.

25AA02UID ’(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)((cid:24)(cid:6)(cid:19)(cid:11)(cid:13)(cid:11)(cid:12)(cid:25)(cid:24)(cid:8)(cid:20)(cid:17)((cid:22)(cid:8)"(cid:15)(cid:17)((cid:3))(cid:28)% (cid:21)(cid:25)(cid:12)(cid:5)& (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)!(cid:10)"(cid:31)(cid:2)(cid:8)#(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)%(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)"’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7))(cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)%(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12)*++&&&(cid:20)!(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)!+(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) b N 4 E E1 PIN1IDBY LASERMARK 1 2 3 e e1 D A A2 c φ L A1 L1 >(cid:15)(cid:7)(cid:31)" (cid:6)(cid:19)??(cid:19)(cid:6)6(cid:13)6(cid:26)(cid:22) (cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:2)?(cid:7)!(cid:7)(cid:31)" (cid:6)(cid:19)@ @A(cid:6) (cid:6)(cid:25)E @#!G(cid:14)(cid:9)(cid:2)(cid:10))(cid:2)((cid:7)(cid:15)" @ H ((cid:7)(cid:31)(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)(cid:24)(cid:29)(cid:2);(cid:22)< A#(cid:31)"(cid:7)%(cid:14)(cid:2)?(cid:14)(cid:28)%(cid:2)((cid:7)(cid:31)(cid:8)(cid:11) (cid:14)3 3(cid:20)(cid:24)(cid:4)(cid:2);(cid:22)< A=(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)J(cid:14)(cid:7)(cid:17)(cid:11)(cid:31) (cid:25) (cid:4)(cid:20)(cid:24)(cid:4) K 3(cid:20)(cid:23)(cid:29) (cid:6)(cid:10)(cid:16)%(cid:14)%(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)$(cid:15)(cid:14)"" (cid:25)(cid:3) (cid:4)(cid:20)L(cid:24) K 3(cid:20)1(cid:4) (cid:22)(cid:31)(cid:28)(cid:15)%(cid:10))) (cid:25)3 (cid:4)(cid:20)(cid:4)(cid:4) K (cid:4)(cid:20)3(cid:29) A=(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)N(cid:7)%(cid:31)(cid:11) 6 (cid:3)(cid:20)(cid:3)(cid:4) K 1(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)%(cid:14)%(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)N(cid:7)%(cid:31)(cid:11) 63 3(cid:20)1(cid:4) K 3(cid:20)L(cid:4) A=(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)?(cid:14)(cid:15)(cid:17)(cid:31)(cid:11) (cid:21) (cid:3)(cid:20)(cid:5)(cid:4) K 1(cid:20)3(cid:4) (cid:30)(cid:10)(cid:10)(cid:31)(cid:2)?(cid:14)(cid:15)(cid:17)(cid:31)(cid:11) ? (cid:4)(cid:20)3(cid:4) K (cid:4)(cid:20)H(cid:4) (cid:30)(cid:10)(cid:10)(cid:31)(cid:12)(cid:9)(cid:7)(cid:15)(cid:31) ?3 (cid:4)(cid:20)1(cid:29) K (cid:4)(cid:20)L(cid:4) (cid:30)(cid:10)(cid:10)(cid:31)(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)O K 1(cid:4)O ?(cid:14)(cid:28)%(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)$(cid:15)(cid:14)"" (cid:8) (cid:4)(cid:20)(cid:4)L K (cid:4)(cid:20)(cid:3)H ?(cid:14)(cid:28)%(cid:2)N(cid:7)%(cid:31)(cid:11) G (cid:4)(cid:20)(cid:3)(cid:4) K (cid:4)(cid:20)(cid:29)3 (cid:21)(cid:25)(cid:12)(cid:5)(cid:11)& 3(cid:20) (cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)"(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)%(cid:2)63(cid:2)%(cid:10)(cid:2)(cid:15)(cid:10)(cid:31)(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)#%(cid:14)(cid:2)!(cid:10)(cid:16)%(cid:2))(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)(cid:31)(cid:9)#"(cid:7)(cid:10)(cid:15)"(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)%(cid:2))(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)(cid:31)(cid:9)#"(cid:7)(cid:10)(cid:15)"(cid:2)"(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)(cid:31)(cid:2)(cid:14)7(cid:8)(cid:14)(cid:14)%(cid:2)(cid:4)(cid:20)3(cid:3)(cid:5)(cid:2)!!(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)"(cid:7)%(cid:14)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)%(cid:2)(cid:31)(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)6(cid:2)83(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) ;(cid:22)<* ;(cid:28)"(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)(cid:31)(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)7(cid:28)(cid:8)(cid:31)(cid:2)=(cid:28)(cid:16)#(cid:14)(cid:2)"(cid:11)(cid:10)&(cid:15)(cid:2)&(cid:7)(cid:31)(cid:11)(cid:10)#(cid:31)(cid:2)(cid:31)(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)"(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)<(cid:4)(cid:23)(cid:27)(cid:4)(cid:3)L;  2013 Microchip Technology Inc. DS20005205A-page 19

25AA02UID Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20005205A-page 20  2013 Microchip Technology Inc.

25AA02UID APPENDIX A: REVISION HISTORY Revision A (05/2013) Initial release.  2013 Microchip Technology Inc. DS20005205A-page 21

25AA02UID NOTES: DS20005205A-page 22  2013 Microchip Technology Inc.

25AA02UID THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.  2013 Microchip Technology Inc. DS20005205A-page 23

25AA02UID READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: 25AA02UID Literature Number: DS20005205A Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS20005205A-page 24  2013 Microchip Technology Inc.

25AA02UID PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X – X /XX Examples: Device Tape & Reel Temperature Package a) 25AA02UID-I/SN = 2k-bit, 16-byte page, 1.8V Serial EEPROM with 32-bit serial number, Industrial temp., SOIC package b) 25AA02UIDT-I/SN = 2k-bit, 16-byte page, 1.8V Serial EEPROM with 32-bit serial number, Device: 25AA02UID = 2k-Bit, 1.8V, 16-Byte Page, SPI Serial EEPROM Industrial temp., Tape & Reel, SOIC package with 32-bit Serial Number c) 25AA02UIDT-I/OT = 2k-bit, 16-byte page, 1.8V Serial EEPROM with 32-bit serial number, Industrial temp., Tape & Reel, SOT-23 package Tape & Reel: Blank = Standard packaging T = Tape & Reel Temperature I = -40C to+85C Range: Package: SN = Plastic SOIC (3.90 mm body), 8-lead OT = SOT-23, 6-lead (Tape and Reel only)  2013 Microchip Technology Inc. DS20005205A-page 25

25AA02UID NOTES: DS20005205A-page 26  2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620772294 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2013 Microchip Technology Inc. DS20005205A-page 27

Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Asia Pacific Office India - Bangalore Austria - Wels 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-3090-4444 Tel: 43-7242-2244-39 Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-3090-4123 Fax: 43-7242-2244-393 Tel: 480-792-7200 Harbour City, Kowloon India - New Delhi Denmark - Copenhagen Fax: 480-792-7277 Hong Kong Tel: 91-11-4160-8631 Tel: 45-4450-2828 Technical Support: Tel: 852-2401-1200 Fax: 91-11-4160-8632 Fax: 45-4485-2829 http://www.microchip.com/ support Fax: 852-2401-3431 India - Pune France - Paris Web Address: Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20 www.microchip.com Tel: 61-2-9868-6733 Fax: 91-20-2566-1513 Fax: 33-1-69-30-90-79 Atlanta Fax: 61-2-9868-6755 Japan - Osaka Germany - Munich Duluth, GA China - Beijing Tel: 81-6-6152-7160 Tel: 49-89-627-144-0 Tel: 86-10-8569-7000 Fax: 49-89-627-144-44 Tel: 678-957-9614 Fax: 81-6-6152-9310 Fax: 678-957-1455 Fax: 86-10-8528-2104 Japan - Tokyo Italy - Milan China - Chengdu Tel: 39-0331-742611 Boston Tel: 81-3-6880- 3770 Tel: 86-28-8665-5511 Fax: 39-0331-466781 Westborough, MA Fax: 81-3-6880-3771 Tel: 774-760-0087 Fax: 86-28-8665-7889 Korea - Daegu Netherlands - Drunen Fax: 774-760-0088 China - Chongqing Tel: 82-53-744-4301 Tel: 31-416-690399 Chicago Tel: 86-23-8980-9588 Fax: 82-53-744-4302 Fax: 31-416-690340 Itasca, IL Fax: 86-23-8980-9500 Korea - Seoul Spain - Madrid Tel: 630-285-0071 China - Hangzhou Tel: 82-2-554-7200 Tel: 34-91-708-08-90 Fax: 630-285-0075 Tel: 86-571-2819-3187 Fax: 82-2-558-5932 or Fax: 34-91-708-08-91 Cleveland Fax: 86-571-2819-3189 82-2-558-5934 UK - Wokingham Independence, OH China - Hong Kong SAR Malaysia - Kuala Lumpur Tel: 44-118-921-5869 Tel: 216-447-0464 Tel: 852-2943-5100 Tel: 60-3-6201-9857 Fax: 44-118-921-5820 Fax: 216-447-0643 Fax: 852-2401-3431 Fax: 60-3-6201-9859 Dallas China - Nanjing Malaysia - Penang Addison, TX Tel: 86-25-8473-2460 Tel: 60-4-227-8870 Tel: 972-818-7423 Fax: 86-25-8473-2470 Fax: 60-4-227-4068 Fax: 972-818-2924 China - Qingdao Philippines - Manila Detroit Tel: 86-532-8502-7355 Tel: 63-2-634-9065 Farmington Hills, MI Fax: 86-532-8502-7205 Fax: 63-2-634-9069 Tel: 248-538-2250 Fax: 248-538-2260 China - Shanghai Singapore Tel: 86-21-5407-5533 Tel: 65-6334-8870 Indianapolis Fax: 86-21-5407-5066 Fax: 65-6334-8850 Noblesville, IN Tel: 317-773-8323 China - Shenyang Taiwan - Hsin Chu Fax: 317-773-5453 Tel: 86-24-2334-2829 Tel: 886-3-5778-366 Fax: 86-24-2334-2393 Fax: 886-3-5770-955 Los Angeles Mission Viejo, CA China - Shenzhen Taiwan - Kaohsiung Tel: 949-462-9523 Tel: 86-755-8864-2200 Tel: 886-7-213-7828 Fax: 949-462-9608 Fax: 86-755-8203-1760 Fax: 886-7-330-9305 Santa Clara China - Wuhan Taiwan - Taipei Santa Clara, CA Tel: 86-27-5980-5300 Tel: 886-2-2508-8600 Tel: 408-961-6444 Fax: 86-27-5980-5118 Fax: 886-2-2508-0102 Fax: 408-961-6445 China - Xian Thailand - Bangkok Toronto Tel: 86-29-8833-7252 Tel: 66-2-694-1351 Mississauga, Ontario, Fax: 86-29-8833-7256 Fax: 66-2-694-1350 Canada China - Xiamen Tel: 905-673-0699 Tel: 86-592-2388138 Fax: 905-673-6509 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 11/29/12 Fax: 86-756-3210049 DS20005205A-page 28  2013 Microchip Technology Inc.