23A1024/23LC1024 1Mbit SPI Serial SRAM with SDI and SQI Interface Device Selection Table Part Dual I/O Quad I/O Max Clock VCC Range Packages Number (SDI) (SQI) Frequency 23A1024 1.7-2.2V Yes Yes 20 MHz SN, ST, P 23LC1024 2.5-5.5V Yes Yes 20 MHz SN, ST, P Features: Description: • SPI-Compatible Bus Interface: The Microchip Technology Inc. 23A1024/23LC1024 - 20 MHz Clock rate are 1 Mbit Serial SRAM devices. The memory is accessed via a simple Serial Peripheral Interface (SPI) - SPI/SDI/SQI mode compatible serial bus. The bus signals required are a • Low-Power CMOS Technology: clock input (SCK) plus separate data in (SI) and data - Read Current: 3 mA at 5.5V, 20 MHz out (SO) lines. Access to the device is controlled - Standby Current: 4 A at +85°C through a Chip Select (CS) input. Additionally, SDI • Unlimited Read and Write Cycles (Serial Dual Interface) and SQI (Serial Quad Interface) • Zero Write Time is supported if your application needs faster data rates. • 128K x 8-bit Organization: This device also supports unlimited reads and writes to - 32-byte page the memory array. • Byte, Page and Sequential mode for Reads and The 23A1024/23LC1024 is available in standard Writes packages including 8-lead SOIC, PDIP and advanced • High Reliability 8-lead TSSOP. • Temperature Range Supported: Package Types (not to scale) - Industrial (I): -40C to +85C • Pb-Free and RoHS Compliant, Halogen Free • 8 Lead SOIC, TSSOP and PDIP Packages Pin Function Table SOIC/TSSOP/PDIP Name Function CS 1 8 Vcc CS Chip Select Input SO/SIO1 2 7 HOLD/SIO3 SO/SIO1 Serial Output/SDI/SQI Pin SIO2 3 6 SCK SIO2 SQI Pin Vss 4 5 SI/SIO0 Vss Ground SI/SIO0 Serial Input/SDI/SQI Pin SCK Serial Clock HOLD/SIO3 Hold/SQI Pin Vcc Power Supply Preliminary  2011 Microchip Technology Inc. DS25142A-page 1

23A1024/23LC1024 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS.........................................................................................................-0.3V to VCC +0.3V Storage temperature...............................................................................................................................-65°C to +150°C Ambient temperature under bias...............................................................................................................-40°C to +85°C † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C Param. Sym. Characteristic Min. Typ(1) Max. Units Test Conditions No. D001 VCC Supply voltage 1.7 — 2.2 V 23A1024 2.5 5.5 23LC1024 D002 VIH High-level input .7 VCC — VCC +0.3 V voltage D003 VIL Low-level input -0.3 — 0.2xVCC V 23A1024 voltage 0.10xVCC 23LC1024 D004 VOL Low-level output — — 0.2 V IOL = 1mA voltage D005 VOH High-level output VCC -0.5 — — V IOH = -400A voltage D006 ILI Input leakage — — ±1 A CS = VCC, VIN = VSS OR VCC current D007 ILO Output leakage — — ±1 A CS = VCC, VOUT = VSS OR VCC current D008 ICC Read Operating current — 1 10 mA FCLK = 20MHz; SO = O, 2.2V — 3 10 mA FCLK = 20MHz; SO = O, 5.5V D009 ICCS Standby current — 1 4 A CS = VCC = 2.2V, Inputs tied to VCC or VSS — 4 10 A CS = VCC = 5.5V, Inputs tied to VCC or VSS D010 CINT Input capacitance 7 pF VCC = 0V, f = 1 MHz, Ta = 25°C (Note1) D011 VDR RAM data retention — 1.0 — V voltage (2) Note 1: This parameter is periodically sampled and not 100% tested. Typical measurements taken at room temperature (25°C). 2: This is the limit to which VDD can be lowered without losing RAM data. This parameter is periodically sampled and not 100% tested. Preliminary DS25142A-page 2  2011 Microchip Technology Inc.

23A1024/23LC1024 TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C Param. Sym. Characteristic Min. Max. Units Test Conditions No. 1 FCLK Clock frequency — 20 MHz 2 TCSS CS setup time 25 — ns 3 TCSH CS hold time 50 — ns 4 TCSD CS disable time 25 — ns 5 Tsu Data setup time 10 — ns 6 THD Data hold time 10 — ns 7 TR CLK rise time — 20 ns Note1 8 TF CLK fall time — 20 ns Note1 9 THI Clock high time 25 — ns 10 TLO Clock low time 25 — ns 11 TCLD Clock delay time 25 — ns 12 TV Output valid from clock low — 25 ns 13 THO Output hold time 0 — ns Note1 14 TDIS Output disable time — 20 ns 15 THS HOLD setup time 10 — ns — 16 THH HOLD hold time 10 — ns — 17 THZ HOLD low to output High-Z 10 — ns — 18 THV HOLD high to output valid — 50 ns — Note 1: This parameter is periodically sampled and not 100% tested. TABLE 1-3: AC TEST CONDITIONS AC Waveform: Input pulse level 0.1 VCC to 0.9 VCC Input rise/fall time 5 ns Operating temperature -40°C to +85°C CL = 30 pF — Timing Measurement Reference Level: Input 0.5 VCC Output 0.5 VCC Preliminary  2011 Microchip Technology Inc. DS25142A-page 3

23A1024/23LC1024 FIGURE 1-1: HOLD TIMING CS 16 16 15 15 SCK 17 18 High-Impedance SO n + 2 n + 1 n n n - 1 Don’t Care 5 SI n + 2 n + 1 n n n - 1 HOLD FIGURE 1-2: SERIAL INPUT TIMING (SPI MODE) 4 CS 2 11 7 8 3 SCK 5 6 SI MSB in LSB in High-Impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING (SPI MODE) CS 9 10 3 SCK 12 14 13 SO MSB out LSB out Don’t Care SI Preliminary DS25142A-page 4  2011 Microchip Technology Inc.

23A1024/23LC1024 2.0 FUNCTIONAL DESCRIPTION After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. 2.1 Principles of Operation If operating in Sequential mode, the data stored in the The 23A1024/23LC1024 is an 1 Mbit Serial SRAM memory at the next address can be read sequentially designed to interface directly with the Serial Peripheral by continuing to provide clock pulses. The internal Interface (SPI) port of many of today’s popular Address Pointer is automatically incremented to the microcontroller families, including Microchip’s PIC® next higher address after each byte of data is shifted microcontrollers. It may also interface with microcon- out. When the highest address is reached (1FFFFh), trollers that do not have a built-in SPI port by using the address counter rolls over to address 00000h, discrete I/O lines programmed properly in firmware to allowing the read cycle to be continued indefinitely. match the SPI protocol. In addition, the 23A1024/ The read operation is terminated by raising the CS 23LC1024 is also capable of operating in SDI/SQI high pin. speed SPI mode. The 23A1024/23LC1024 contains an 8-bit instruction 2.4 Write Sequence register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The Prior to any attempt to write data to the 23A1024/ CS pin must be low for the entire operation. 23LC1024, the device must be selected by bringing CS low. Table2-1 contains a list of the possible instruction bytes and format for device operation. All instructions, Once the device is selected, the Write command can addresses and data are transferred MSB first, LSB last. be started by issuing a WRITE instruction, followed by the 24-bit address, with the first seven MSB’s of the address being a “don’t care” bit, and then the data to be 2.2 Modes of Operation written. A write is terminated by the CS being brought The 23X1024 has three modes of operation that are high. selected by setting bits 7 and 6 in the MODE register. If operating in Page mode, after the initial data byte is The modes of operation are Byte, Page and Burst. shifted in, additional bytes can be shifted into the Byte Operation – is selected when bits 7 and 6 in the device. The Address Pointer is automatically MODE register are set to 00. In this mode, the read/ incremented. This operation can continue for the entire write operations are limited to only one byte. The page (32 bytes) before data will start to be overwritten. Command followed by the 24-bit address is clocked into If operating in Sequential mode, after the initial data the device and the data to/from the device is transferred byte is shifted in, additional bytes can be clocked into on the next eight clocks (Figure2-1, Figure2-2). the device. The internal Address Pointer is automati- Page Operation – is selected when bits 7 and 6 in the cally incremented. When the Address Pointer reaches MODE register are set to 10. The 23X1024 has 4096 the highest address (1FFFFh), the address counter pages of 32 bytes. In this mode, the read and write oper- rolls over to (00000h). This allows the operation to ations are limited to within the addressed page (the continue indefinitely, however, previous data will be address is automatically incremented internally). If the overwritten. data being read or written reaches the page boundary, then the internal address counter will increment to the start of the page (Figure2-3, Figure2-4). Sequential Operation – is selected when bits 7 and 6 in the MODE register are set to 01. Sequential opera- tion allows the entire array to be written to and read from. The internal address counter is automatically incremented and page boundaries are ignored. When the internal address counter reaches the end of the array, the address counter will roll over to 0x00000 (Figure2-5, Figure2-6). 2.3 Read Sequence The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 23A1024/ 23LC1024 followed by the 24-bit address, with the first seven MSB’s of the address being a “don’t care” bit. Preliminary  2011 Microchip Technology Inc. DS25142A-page 5

23A1024/23LC1024 TABLE 2-1: INSTRUCTION SET Hex Instruction Name Instruction Format Description Code READ 0000 0011 0x03 Read data from memory array beginning at selected address WRITE 0000 0010 0x02 Write data to memory array beginning at selected address EDIO 0011 1011 0x3B Enter Dual I/O access EQIO 0011 1000 0x38 Enter Quad I/O access RSTIO 1111 1111 0xFF Reset Dual and Quad I/O access RDMR 0000 0101 0x05 Read Mode Register WRMR 0000 0001 0x01 Write Mode Register FIGURE 2-1: BYTE READ SEQUENCE (SPI MODE) CS 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction 24-bit Address SI 0 0 0 0 0 0 1 1 23 22 21 20 2 1 0 Data Out High-Impedance SO 7 6 5 4 3 2 1 0 FIGURE 2-2: BYTE WRITE SEQUENCE (SPI MODE) CS 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction 24-bit Address Data Byte SI 0 0 0 0 0 0 1 0 23 22 21 20 2 1 0 7 6 5 4 3 2 1 0 High-Impedance SO Preliminary DS25142A-page 6  2011 Microchip Technology Inc.

23A1024/23LC1024 FIGURE 2-3: PAGE READ SEQUENCE (SPI MODE) CS 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction 24-bit Address SI 0 0 0 0 0 0 1 1 23 22 21 20 2 1 0 Page X, Word Y Page X, Word Y High Impedance SO 7 6 5 4 3 2 1 0 CS 40 41 42 43 44 45 46 47 SCK SI Page X, Word Y+1 Page X, Word 31 Page X, Word 0 SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 FIGURE 2-4: PAGE WRITE SEQUENCE (SPI MODE) CS 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction 24-bit Address Page X, Word Y SI 0 0 0 0 0 0 1 0 23 22 21 20 2 1 0 7 6 5 4 3 2 1 0 Page X, Word Y CS 40 41 42 43 44 45 46 47 SCK Page X, Word Y+1 Page X, Word 31 Page X, Word 0 SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Preliminary  2011 Microchip Technology Inc. DS25142A-page 7

23A1024/23LC1024 FIGURE 2-5: SEQUENTIAL READ SEQUENCE (SPI MODE) CS 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction 24-bit Address SI 0 0 0 0 0 0 1 1 23 22 21 20 2 1 0 Page X, Word Y SO 7 6 5 4 3 2 1 0 CS SCK SI Page X, Word 31 Page X+1, Word 0 Page X+1, Word 1 SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CS SCK SI Page X+1, Word 31 Page X+n, Word 1 Page X+n, Word 31 SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Preliminary DS25142A-page 8  2011 Microchip Technology Inc.

23A1024/23LC1024 FIGURE 2-6: SEQUENTIAL WRITE SEQUENCE (SPI MODE) CS 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction 24-bit Address Data Byte 1 SI 0 0 0 0 0 0 1 0 23 22 21 20 2 1 0 7 6 5 4 3 2 1 0 CS 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCK Data Byte 2 Data Byte 3 Data Byte n SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Preliminary  2011 Microchip Technology Inc. DS25142A-page 9

23A1024/23LC1024 2.5 Read Mode Register Instruction The mode bits indicate the operating mode of the (RDMR) SRAM. The possible modes of operation are: 0 0 = Byte mode The Read Mode Register instruction (RDMR) provides access to the MODE register. The MODE register may 1 0 = Page mode be read at any time. The MODE register is formatted as 0 1 = Sequential mode (default operation) follows: 1 1 = Reserved TABLE 2-2: MODE REGISTER Bits 0 through 5 are reserved and should always be set to ‘0’. 7 6 5 4 3 2 1 0 See Figure2-7 for the RDMR timing sequence. W/R W/R – – – – – – MODE MODE 0 0 0 0 0 0 W/R = writable/readable FIGURE 2-7: READ MODE REGISTER TIMING SEQUENCE (RDMR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction SI 0 0 0 0 0 1 0 1 Data from MODE Register High-Impedance SO 7 6 5 4 3 2 1 0 Preliminary DS25142A-page 10  2011 Microchip Technology Inc.

23A1024/23LC1024 2.6 Write Mode Register Instruction (WRMR) The Write Mode Register instruction (WRMR) allows the user to write to the bits in the MODE register as shown in Table2-2. This allows for setting of the Device operating mode. Several of the bits in the MODE register must be cleared to ‘0’. See Figure2-8 for the WRMR timing sequence. FIGURE 2-8: WRITE MODE REGISTER TIMING SEQUENCE (WRMR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction Data to MODE Register SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 High-Impedance SO 2.7 Power-On State The 23A1024/23LC1024 powers on in the following state: • The device is in low-power Standby mode (CS=1) • A high-to-low-level transition on CS is required to enter active state Preliminary  2011 Microchip Technology Inc. DS25142A-page 11

23A1024/23LC1024 3.0 PIN DESCRIPTIONS 3.6 Serial Clock (SCK) The descriptions of the pins are listed in Table3-1. The SCK is used to synchronize the communication between a master and the 23A1024/23LC1024. TABLE 3-1: PIN FUNCTION TABLE Instructions, addresses or data present on the SI pin are latched on the rising edge of the clock input, while SOIC/ data on the SO pin is updated after the falling edge of Name PDIP Function the clock input. TSSOP 3.7 Hold Function (HOLD) CS 1 Chip Select Input SO/SIO1 2 Serial Data Output/SDI/SQI The HOLD pin is used to suspend transmission to the Pin 23A1024/23LC1024 while in the middle of a serial SIO2 3 SQI Pin sequence without having to re-transmit the entire sequence over again. It must be held high any time VSS 4 Ground this function is not being used. Once the device is SI/SIO0 5 Serial Data Input/SDI/SQI Pin selected and a serial sequence is underway, the SCK 6 Serial Clock Input HOLD pin may be pulled low to pause further serial HOLD/SIO3 7 Hold/SQI Pin communication without resetting the serial sequence. VCC 8 Power Supply The HOLD pin should be brought low while SCK is 3.1 Chip Select (CS) low, otherwise the HOLD function will not be invoked until the next SCK high-to-low transition. The A low level on this pin selects the device. A high level 23A1024/23LC1024 must remain selected during this deselects the device and forces it into Standby mode. When the device is deselected, SO goes to the high- sequence. The SI and SCK levels are “don’t cares” impedance state, allowing multiple parts to share the during the time the device is paused and any same SPI bus. After power-up, a low level on CS is transitions on these pins will be ignored. To resume required, prior to any sequence being initiated. serial communication, HOLD should be brought high while the SCK pin is low, otherwise serial 3.2 Serial Output (SO) communication will not be resumed until the next SCK The SO pin is used to transfer data out of the 23A1024/ high-to-low transition. 23LC1024. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock. The SO line will tri-state immediately upon a high-to low transition of the HOLD pin, and will begin 3.3 Serial Input (SI) outputting again immediately upon a subsequent low- The SI pin is used to transfer data into the device. It to-high transition of the HOLD pin, independent of the receives instructions, addresses, and data. Data is state of SCK. latched on the rising edge of the serial clock. Hold functionality is not available when operating in 3.4 Serial Dual Interface Pins(SIO0, SQI mode. SIO1) The SIO0 and SIO1 pins are used for SDI mode of operation. Functionality of these I/O pins is shared with SO and SI. 3.5 Serial Quad Interface Pins (SIO0 – SIO3) The SIO0 through SIO3 pins are used for SQI mode of operation. Because of the shared functionality of these pins the HOLD feature is not available when using SQI mode. Preliminary DS25142A-page 12  2011 Microchip Technology Inc.

23A1024/23LC1024 3.8 SPI/SDI and SQI Pin Designations SPI Mode: CS 1 8 Vcc SO 2 7 HOLD NC 3 6 SCK Vss 4 5 SI SDI Mode: CS 1 8 Vcc SIO1 2 7 HOLD NC 3 6 SCK Vss 4 5 SIO0 SQI Mode: CS 1 8 Vcc SIO1 2 7 SIO3 SIO2 3 6 SCK Vss 4 5 SIO0 Note: Pin 3 should not be left floating when not using SQI Operation. Preliminary  2011 Microchip Technology Inc. DS25142A-page 13

23A1024/23LC1024 4.0 DUAL AND QUAD SERIAL 4.1 Dual Interface Mode MODE The 23A1024/23LC1024 supports Serial Dual Input (SDI) mode of operation. To enter SDI mode the EDIO The 23A1024/23LC1024 also supports SDI (Serial command must be clocked in (Figure4-1). It should be Dual) and SQI (Serial Quad) mode of operation when noted that if the MCU resets before the SRAM, the user used with compatible master devices. As a convention will need to determine the serial mode of operation of for SDI mode of operation, two bits are entered per the SRAM and reset it accordingly. Byte read and write clock using the SIO0 and SIO1 pins. Bits are clocked sequence in SDI mode is shown in Figure4-2 and MSB first. Figure4-3. For SQI mode of operation, four bits of data are entered per clock, or one nibble per clock. The nibbles are clocked MSB first. FIGURE 4-1: ENTER SDI MODE (EDIO) FROM SPI MODE CS 0 1 2 3 4 5 6 7 SCK SI 0 0 1 1 1 0 1 1 High Impedance SO 4.2 Quad Interface Mode In addition to the Serial Dual interface (SDI) mode of operation Serial Quad Interface (SQI) is also supported. In this mode the HOLD functionality is not available. To enter SQI mode the EQIO command must be clocked in (Figure4-4). Preliminary DS25142A-page 14  2011 Microchip Technology Inc.

23A1024/23LC1024 FIGURE 4-2: BYTE READ MODE SDI CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK SIO0 0 0 0 1 22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0 Instruction 24-Bit Address Dummy Byte Data Out SIO1 0 0 0 1 23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1 Note: Page and Sequential mode are similar in that additional bytes can be clocked out before CS is brought high. Note: The first byte read after the address will be a dummy byte. FIGURE 4-3: BYTE WRITE MODE SDI CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SCK SIO0 0 0 0 0 22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0 Instruction 24-Bit Address Data In SIO1 0 0 0 1 23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1 Note: Page and Sequential mode are similar in that additional bytes can be clocked in before CS is brought high. Preliminary  2011 Microchip Technology Inc. DS25142A-page 15

23A1024/23LC1024 FIGURE 4-4: ENTER SQI MODE (EQIO) FROM SPI MODE CS 0 1 2 3 4 5 6 7 SCK SI 0 0 1 1 1 0 0 0 High Impedance SO 4.3 Exit SDI or SQI Mode To exit from SDI mode, the RSTIO command must be issued. The command must be entered in the current device configuration, either SDI or SQI, see Figure4-7 and Figure4-8. FIGURE 4-5: BYTE READ MODE SQII CS 0 1 2 3 4 5 6 7 8 9 10 11 SCK SIO0 0 1 20 16 12 8 4 0 4 0 SIO1 0 1 21 17 13 9 5 1 5 1 SIO2 0 0 22 18 14 10 6 2 6 2 SIO3 0 0 23 19 15 11 7 3 7 3 Instruction 24-Bit Address Dummy Byte Data Out Note: Page and Sequential mode is similar in that additional bytes can be clocked out before CS is brought high. Note: The first byte read after the address will be a dummy byte. Preliminary DS25142A-page 16  2011 Microchip Technology Inc.

23A1024/23LC1024 FIGURE 4-6: BYTE WRITE MODE SQI CS 0 1 2 3 4 5 6 7 8 9 SCK SIO0 0 0 20 16 12 8 4 0 4 0 SIO1 0 1 21 17 13 9 5 1 5 1 0 0 22 18 14 10 6 2 6 2 SIO2 0 0 23 19 15 11 7 3 7 3 SIO3 Instruction 24-Bit Address Data In Note: Page and Sequential mode are similar in that additional bytes can be clocked out before CS is brought high. FIGURE 4-7: RESET SDI MODE (RSTIO) – FROM SDI MODE CS 0 1 2 3 SCK SIO0 1 1 1 1 1 1 1 1 SIO1 Preliminary  2011 Microchip Technology Inc. DS25142A-page 17

23A1024/23LC1024 FIGURE 4-8: RESET SDI/SQI MODE (RSTIO) – FROM SQI MODE CS 0 1 SCK 1 1 SIO0 1 1 SIO1 SIO2 1 1 SIO3 1 1 Preliminary DS25142A-page 18  2011 Microchip Technology Inc.

23A1024/23LC1024 5.0 PACKAGING INFORMATION 5.1 Package Marking Information 8-Lead PDIP (300 mil) Example XXXXXXXX 23A1024 XXXXXNNN I/P e 3 1L7 YYWW 0528 8-Lead SOIC (3.90 mm) Example: XXXXXXXT 23A1024I XXXXYYWW SN e 3 0528 NNN 1L7 8-Lead TSSOP Example: XXXX 3ABI TYWW I837 NNN 1L7 Legend: XX...X Part number or part number code T Temperature (I, E) Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code (2 characters for small packages) e3 Pb-free JEDEC designator for Matte Tin (Sn) Note: For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Preliminary  2011 Microchip Technology Inc. DS25142A-page 19

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(cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 < (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:30)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:24)(cid:29) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)-(cid:3)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)(cid:29)(cid:4) (cid:20)(cid:3)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:20)-(cid:23)< (cid:20)-?(cid:29) (cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)?(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2(cid:2)1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:30)<1 Preliminary DS25142A-page 20  2011 Microchip Technology Inc.

23A1024/23LC1024 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Preliminary  2011 Microchip Technology Inc. DS25142A-page 21

23A1024/23LC1024 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Preliminary DS25142A-page 22  2011 Microchip Technology Inc.

23A1024/23LC1024 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19) (cid:30)(cid:20)(cid:8)(cid:21)(cid:8)(cid:30)(cid:6)""(cid:26)#$(cid:8)(cid:22)%&(cid:23)(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28) !(cid:17)’(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) Preliminary  2011 Microchip Technology Inc. DS25142A-page 23

23A1024/23LC1024 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)()(cid:13)(cid:18)(cid:8) )"(cid:13)(cid:18)*(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19) ((cid:20)(cid:8)(cid:21)(cid:8)+%+(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)( !(cid:9)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 b e c φ A A2 A1 L1 L 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 < (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:4)(cid:20)<(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:30)(cid:20)(cid:4)(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = (cid:4)(cid:20)(cid:30)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . ?(cid:20)(cid:23)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:23)(cid:20)-(cid:4) (cid:23)(cid:20)(cid:23)(cid:4) (cid:23)(cid:20)(cid:29)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:3)(cid:20)(cid:24)(cid:4) -(cid:20)(cid:4)(cid:4) -(cid:20)(cid:30)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:29) (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)(cid:5)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:4)(cid:4)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)R = <R 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:4) 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:30)(cid:24) = (cid:4)(cid:20)-(cid:4) (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:30)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)<?1 Preliminary DS25142A-page 24  2011 Microchip Technology Inc.

23A1024/23LC1024 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Preliminary  2011 Microchip Technology Inc. DS25142A-page 25

23A1024/23LC1024 APPENDIX A: REVISION HISTORY Revision A (July 2012) Initial release. Preliminary DS25142A-page 26  2011 Microchip Technology Inc.

23A1024/23LC1024 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. Preliminary  2012 Microchip Technology Inc. DS25142A-page 27

23A1024/23LC1024 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: 23A1024/23LC1024 Literature Number: DS25142A Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? Preliminary DS25142A-page 28  2012 Microchip Technology Inc.

23A1024/23LC1024 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Not all possible ordering options are shown below.. PART NO. X – X /XX Examples: Device Tape & Reel Temp Range Package a) 23A1024-I/ST = 1 Mbit, 1.7 - 2.2V Serial SRAM, Industrial temp., TSSOP package b) 23LC1024-I/SN = 1 Mbit, 2.5-5.5V Serial SRAM, Industrial temp., Tape & Reel, SOIC package Device: 23A1024 = 1 Mbit, 1.7 - 2.2V, SPI Serial SRAM 23LC1024 = 1 Mbit, 2.5 - 5.5V, SPI Serial SRAM c) 23LC1024-I/P = 1 Mbit, 2.5-5.5V Serial SRAM, Industrial temp., PDIP package Tape & Reel: Blank = Standard packaging (tube) T = Tape & Reel Temperature I = -40C to+85C Range: Package: SN = Plastic SOIC (3.90 mm body), 8-lead ST = Plastic TSSOP (4.4 mm body), 8-lead P = Plastic PDIP (300 mil body), 8-lead Preliminary  2012 Microchip Technology Inc. DS25142A-page 29

23A1024/23LC1024 NOTES: Preliminary DS25142A-page 30  2012 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, chipKIT, devices in life support and/or safety applications is entirely at chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, hold harmless Microchip from any and all damages, claims, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, suits, or expenses resulting from such use. No licenses are Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, conveyed, implicitly or otherwise, under any Microchip MPLINK, mTouch, Omniscient Code Generation, PICC, intellectual property rights. PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620764589 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary  2012 Microchip Technology Inc. DS25142A-page 31

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: 23A1024-I/P 23A1024-I/SN 23LC1024-I/SN 23A1024-I/ST 23LC1024-I/ST 23LC1024-I/P 23LC1024T-I/ST 23LC1024T-I/SN