XRA1405 16-BIT SPI GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS SEPTEMBER 2011 REV. 1.0.0 GENERAL DESCRIPTION FEATURES The XRA1405 is an 16-bit GPIO expander with an • 1.65V to 3.6V operating voltage SPI interface. After power-up, the XRA1405 has • 16 General Purpose I/Os (GPIOs) internal 100K ohm pull-up resistors on each I/O pin that can be individually enabled. • Integrated Level Shifters In addition, the GPIOs on the XRA1405 can • 5V tolerant inputs individually be controlled and configured. As outputs, • Maximum stand-by current of 1uA at +1.8V the GPIOs can be outputs that are high, low or in three-state mode. The three-state mode feature is • SPI bus interface useful for applications where the power is removed ■ SPI Clock Frequency up to 26MHz from the remote devices, but they may still be • Individually programmable inputs connected to the GPIO expander. ■ Internal pull-up resistors As inputs, the internal pull-up resistors can be enabled or disabled and the input polarity can be ■ Polarity inversion inverted. The interrupt can be programmed for ■ Individual interrupt enable different behaviors. The interrupts can be ■ Rising edge and/or Falling edge interrupt programmed to generate an interrupt on the rising ■ Input filter edge, falling edge or on both edges. The interrupt can be cleared if the input changes back to its original • Individually programmable outputs state or by reading the current state of the inputs. ■ Output Level Control The XRA1405 is available in 24-pin QFN and 24-pin ■ Output Three-State Control TSSOP packages. • Open-drain active low interrupt output • 3kV HBM ESD protection per JESD22-A114F • 200mA latch-up performance per JESD78B APPLICATIONS • Personal Digital Assistants (PDA) • Cellular Phones/Data Devices • Battery-Operated Devices • Global Positioning System (GPS) • Bluetooth Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

XRA1405 16-BIT SPI GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS REV. 1.0.0 FIGURE 1. XRA1405 BLOCK DIAGRAM (1.65V – 3.6V) VCCP VCC (1.65V – 3.6V) P0 P1 P2 P3 GPIOs P4 P5 CS# P6 P7 SCL SI SPI Bus CGoPnItOrol IntLeegvraetle d SO Interface Registers Shifters P8 P9 IRQ# P10 P11 GPIOs P12 P13 P14 P15 GND ORDERING INFORMATION NUMBER OF OPERATING TEMPERATURE PART NUMBER PACKAGE DEVICE STATUS GPIOS RANGE XRA1405IL24-F QFN-24 16 -40°C to +85°C Active XRA1405IL24TR-F QFN-24 16 -40°C to +85°C Active XRA1405IG24-F TSSOP-24 16 -40°C to +85°C Active XRA1405IG24TR-F TSSOP-24 16 -40°C to +85°C Active NOTE: TR = Tape and Reel, F = Green / RoHS FIGURE 2. PIN OUT ASSIGNMENTS IRQ# 1 24 VCCP SI VCC IRQ# VCCP SO SCL VCSCI 32 2223 SSOCL 24 23 22 21 20 19 P0 4 21 CS# P0 1 18 CS# P1 2 17 P15 P1 5 20 P15 P2 3 XRA1405 16 P14 P2 6 XRA1405 19 P14 24-Pin QFN 24-Pin P3 4 15 P13 P3 7 TSSOP 18 P13 P4 5 14 P12 P4 8 17 P12 P5 6 13 P11 7 8 9 10 11 12 P5 9 16 P11 P6 P7 GND P8 P9 P10 P6 10 15 P10 P7 11 14 P9 GND 12 13 P8 2

XRA1405 REV. 1.0.0 16-BIT SPI GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS PIN DESCRIPTIONS Pin Description QFN-24 TSSOP-24 NAME TYPE DESCRIPTION PIN# PIN# SPI INTERFACE SO 20 23 O SPI serial data output. SCL 19 22 I SPI bus serial input clock. IRQ# 22 1 OD Interrupt output (open-drain, active LOW). CS# 18 16 I SPI bus chip select. SI 24 3 I SPI serial data input. GPIOs P0 1 4 I/O General purpose I/Os P0-P7. All GPIOs are configured as inputs upon power- P1 2 5 I/O up or after a reset. P2 3 6 I/O P3 4 7 I/O P4 5 8 I/O P5 6 9 I/O P6 7 10 I/O P7 8 11 I/O P8 10 13 I/O General purpose I/O P8-P15. All GPIOs are configured as inputs upon power- P9 11 14 I/O up or after a reset. P10 12 15 I/O P11 13 16 I/O P12 14 17 I/O P13 15 18 I/O P14 16 19 I/O P15 17 20 I/O ANCILLARY SIGNALS VCCP 21 24 1.65V to 3.6V VCC supply voltage for GPIOs. VCC 23 2 Pwr 1.65V to 3.6V VCC supply voltage for SPI bus interface. GND 9 12 Pwr Power supply common, ground. GND Center - Pwr The exposed pad at the bottom surface of the package is designed for thermal Pad performance. Use of a center pad on the PCB is strongly recommended for ther- mal conductivity as well as to provide mechanical stability of the package on the PCB. The center pad is recommended to be solder masked defined with open- ing size less than or equal to the exposed thermal pad on the package bottom to prevent solder bridging to the outer leads of the device. Thermal vias must be connected to GND plane as the thermal pad of package is at GND potential. Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain. 3

XRA1405 16-BIT SPI GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS REV. 1.0.0 1.0 FUNCTIONAL DESCRIPTIONS 1.1 SPI bus Interface The SPI interface consists of four lines: serial clock (SCL), chip select (CS#), slave output (SO) and slave input (SI). The serial clock, slave output and slave input can be as fast as 26 MHz. To access the device in the SPI mode, the CS# signal is asserted by the SPI master, then the SPI master starts toggling the SCL signal with the appropriate transaction information. The first bit sent by the SPI master includes whether it is a read or write transaction and the register being accessed. See Table 1 below. TABLE 1: SPI COMMAND BYTE FORMAT BIT FUNCTION 7 Read/Write# Logic 1 = Read Logic 0 = Write 6:1 Command Byte 0 Reserved FIGURE 3. SPI WRITE SCL SI 0 0 0 A3 A2 A1 A0 X D7 D6 D5 D4 D3 D2 D1 D0 FIGURE 4. SPI READ SCL SI 1 0 0 A3 A2 A1 A0 X SO D7 D6 D5 D4 D3 D2 D1 D0 After the last read or write transaction, the SPI master will set the SCL signal back to its idle state (LOW). 4

XRA1405 REV. 1.0.0 16-BIT SPI GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS 1.1.1 SPI Command Byte An SPI command byte is sent by the SPI master following the slave address. The command byte indicates the address offset of the register that will be accessed. Table 2 below lists the command bytes for each register. TABLE 2: COMMAND BYTE (REGISTER ADDRESS) COMMAND BYTE REGISTER NAME DESCRIPTION READ/WRITE DEFAULT VALUES 0x00 GSR1 - GPIO State for P0-P7 Read-Only 0xXX 0x01 GSR2 - GPIO State for P8-P15 Read-Only 0xXX 0x02 OCR1 - Output Control for P0-P7 Read/Write 0xFF 0x03 OCR2 - Output Control for P8-P15 Read/Write 0xFF 0x04 PIR1 - Input Polarity Inversion for P0-P7 Read/Write 0x00 0x05 PIR2 - Input Polarity Inversion for P8-P15 Read/Write 0x00 0x06 GCR1 - GPIO Configuration for P0-P7 Read/Write 0xFF 0x07 GCR2 - GPIO Configuration for P8-P15 Read/Write 0xFF 0x08 PUR1 - Input Internal Pull-up Resistor Enable/Disable for P0-P7 Read/Write 0x00 0x09 PUR2 - Input Internal Pull-up Resistor Enable/Disable for P8-P15 Read/Write 0x00 0x0A IER1 - Input Interrupt Enable for P0-P7 Read/Write 0x00 0x0B IER2 - Input Interrupt Enable for P8-P15 Read/Write 0x00 0x0C TSCR1 - Output Three-State Control for P0-P7 Read/Write 0x00 0x0D TSCR2 - Output Three-State Control for P8-P15 Read/Write 0x00 0x0E ISR1 - Input Interrupt Status for P0-P7 Read 0x00 0x0F ISR2 - Input Interrupt Status for P8-P15 Read 0x00 0x10 REIR1 - Input Rising Edge Interrupt Enable for P0-P7 Read/Write 0x00 0x11 REIR2 - Input Rising Edge Interrupt Enable for P8-P15 Read/Write 0x00 0x12 FEIR1 - Input Falling Edge Interrupt Enable for P0-P7 Read/Write 0x00 0x13 FEIR2 - Input Falling Edge Interrupt Enable for P8-P15 Read/Write 0x00 0x14 IFR1 - Input Filter Enable/Disable for P0-P7 Read/Write 0xFF 0x15 IFR2 - Input Filter Enable/Disable for P8-P15 Read/Write 0xFF 5

XRA1405 16-BIT SPI GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS REV. 1.0.0 1.2 Interrupts The table below summarizes the interrupt behavior of the different register settings for the XRA1405. TABLE 3: INTERRUPT GENERATION AND CLEARING GCR IER REIR FEIR IFR INTERRUPT GENERATED BY: INTERRUPT CLEARED BY: BIT BIT BIT BIT BIT 1 0 X X X No interrupts enabled (default) N/A 0 A rising or falling edge on the input Reading the GSR register or if the input changes back to its previous state (state of 1 1 0 0 1 A rising or falling edge on the input and input during last read to GSR) remains in the new state for more than 1075ns 0 A rising edge on the input Reading the GSR register 1 1 1 0 1 A rising edge on the input and remains high for more than 1075ns 0 A falling edge on the input Reading the GSR register 1 1 0 1 1 A falling edge on the input and remains low for more than 1075ns 0 A rising or falling edge on the input Reading the GSR register 1 1 1 1 1 A rising or falling edge on the input and remains in the new state for more than 1075ns 0 x x x x No interrupts in output mode N/A 6

XRA1405 REV. 1.0.0 16-BIT SPI GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS 2.0 REGISTER DESCRIPTION 2.1 GPIO State Register 1 (GSR1) - Read-Only The status of P7 - P0 can be read via this register. A read will show the current state of these pins (or the inverted state of these pins if enabled via the PIR Register). Reading this register will clear an input interrupt (see Table 3 for complete details). Reading this register will also return the last value written to the OCR register for any pins that are configured as outputs (ie. this is not the same as the state of the actual output pin since the output pin can be in three-state mode). A write to this register has no effect. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0. 2.2 GPIO State Register 2 (GSR2) - Read-Only The status of P15 - P8 can be read via this register. A read will show the current state of these pins (or the inverted state of these pins if enabled via the PIR Register). Reading this register will clear an input interrupt (see Table 3 for complete details). Reading this register will also return the last value written to the OCR register for any pins that are configured as outputs (ie. this is not the same as the state of the actual output pin since the output pin can be in three-state mode). A write to this register has no effect. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8. 2.3 Output Control Register 1 (OCR1) - Read/Write When P7 - P0 are defined as outputs, they can be controlled by writing to this register. Reading this register will return the last value written to it, however, this value may not be the actual state of the output pin since these pins can be in three-state mode. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0. 2.4 Output Control Register 2 (OCR2) - Read/Write When P15 - P8 are defined as outputs, they can be controlled by writing to this register. Reading this register will return the last value written to it, however, this value may not be the actual state of the output pin since these pins can be in three-state mode. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8. 2.5 Input Polarity Inversion Register 1 (PIR1) - Read/Write When P7 - P0 are defined as inputs, this register inverts the polarity of the input value read from the Input Port Register. If the corresponding bit in this register is set to ’1’, the value of this bit in the GSR Register will be the inverted value of the input pin. If the corresponding bit in this register is set to ’0’, the value of this bit in the GSR Register will be the actual value of the input pin. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0. 2.6 Input Polarity Inversion Register 2 (PIR2) - Read/Write When P15 - P8 are defined as inputs, this register inverts the polarity of the input value read from the Input Port Register. If the corresponding bit in this register is set to ’1’, the value of this bit in the GSR Register will be the inverted value of the input pin. If the corresponding bit in this register is set to ’0’, the value of this bit in the GSR Register will be the actual value of the input pin. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8. 2.7 GPIO Configuration Register 1 (GCR1) - Read/Write This register configures the GPIOs as inputs or outputs. After power-up and reset, the GPIOs are inputs. Setting these bits to ’0’ will enable the GPIOs as outputs. Setting these bits to ’1’ will enable the GPIOs as inputs. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0. 2.8 GPIO Configuration Register 2 (GCR2) - Read/Write This register configures the GPIOs as inputs or outputs. After power-up and reset, the GPIOs are inputs. Setting these bits to ’0’ will enable the GPIOs as outputs. Setting these bits to ’1’ will enable the GPIOs as inputs. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8. 7

XRA1405 16-BIT SPI GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS REV. 1.0.0 2.9 Input Internal Pull-up Enable/Disable Register 1 (PUR1) - Read/Write This register enables/disables the internal pull-up resistors for an input. Writing a ’1’ to these bits will enable the internal pull-up resistors. Writing a ’0’ to these bits will disable the internal pull-up resistors. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0. 2.10 Input Internal Pull-up Enable/Disable Register 2 (PUR2) - Read/Write This register enables/disables the internal pull-up resistors for an input. Writing a ’1’ to these bits will enable the internal pull-up resistors. Writing a ’0’ to these bits will disable the internal pull-up resistors. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8. 2.11 Input Interrupt Enable Register 1 (IER1) - Read/Write This register enables/disables the interrupts for an input. After power-up and reset, the interrupts are disabled. Writing a ’1’ to these bits will enable the interrupt for the corresponding input pins. See Table 3 for complete details of the interrupt behavior for various register settings. No interrupts are generated for outputs when GCR bit is 0. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0. 2.12 Input Interrupt Enable Register 2 (IER2) - Read/Write This register enables/disables the interrupts for an input. After power-up and reset, the interrupts are disabled. Writing a ’1’ to these bits will enable the interrupt for the corresponding input pins. See Table 3 for complete details of the interrupt behavior for various register settings. No interrupts are generated for outputs when GCR bit is 0. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8. 2.13 Output Three-State Control Register 1 (TSCR1) - Read/Write This register can enable/disable the three-state mode of an output. Writing a ’1’ to these bits will enable the three-state mode for the corresponding output pins. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0. 2.14 Output Three-State Control Register 2 (TSCR2) - Read/Write This register can enable/disable the three-state mode of an output. Writing a ’1’ to these bits will enable the three-state mode for the corresponding output pins. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8. 2.15 Input Interrupt Status Register 1 (ISR1) - Read-Only This register reports the input pins that have generated an interrupt. See Table 3 for complete details of the interrupt behavior for various register settings. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0. 2.16 Input Interrupt Status Register 2 (ISR2) - Read-Only This register reports the input pins that have generated an interrupt. See Table 3 for complete details of the interrupt behavior for various register settings. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8. 8

XRA1405 REV. 1.0.0 16-BIT SPI GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS 2.17 Input Rising Edge Interrupt Enable Register 1 (REIR1) - Read/Write Writing a ’1’ to these bits will enable the corresponding input to generate an interrupt on the rising edge. See Table 3 for complete details of the interrupt behavior for various register settings. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0. 2.18 Input Rising Edge Interrupt Enable Register 2 (REIR2) - Read/Write Writing a ’1’ to these bits will enable the corresponding input to generate an interrupt on the rising edge. See Table 3 for complete details of the interrupt behavior for various register settings. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8. 2.19 Input Falling Edge Interrupt Enable Register 1 (FEIR1) - Read/Write Writing a ’1’ to these bits will enable the corresponding input to generate an interrupt on the falling edge. Writing a ’1’ to these bits will make that input generate an interrupt on the rising edge only. See Table 3 for complete details of the interrupt behavior for various register settings. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0. 2.20 Input Falling Edge Interrupt Enable Register 2 (FEIR2) - Read/Write Writing a ’1’ to these bits will enable the corresponding input to generate an interrupt on the falling edge. Writing a ’1’ to these bits will make that input generate an interrupt on the rising edge only. See Table 3 for complete details of the interrupt behavior for various register settings. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8. 2.21 Input Filter Enable Register 1 (IFR1) - Read/Write By default, the input filters are enabled (IFR = 0xFF). When the input filters are enabled, any pulse that is greater than 1075ns will generate an interrupt (if enabled). Pulses that are less than 225ns will be filtered and will not generate an interrupt. Pulses in between this range may or may not generate an interrupt. Writing a ’0’ to these bits will disable the input filter for the corresponding inputs. With the input filters disabled, any change on the inputs will generate an interrupt (if enabled). See Table 3 for complete details of the interrupt behavior for various register settings. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0. 2.22 Input Filter Enable Register 2 (IFR2) - Read/Write By default, the input filters are enabled (IFR = 0xFF). When the input filters are enabled, any pulse that is greater than 1075ns will generate an interrupt (if enabled). Pulses that are less than 225ns will be filtered and will not generate an interrupt. Pulses in between this range may or may not generate an interrupt. Writing a ’0’ to these bits will disable the input filter for the corresponding inputs. With the input filters disabled, any change on the inputs will generate an interrupt (if enabled). See Table 3 for complete details of the interrupt behavior for various register settings. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8. 9

XRA1405 16-BIT SPI GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS REV. 1.0.0 ABSOLUTE MAXIMUM RATINGS Power supply voltage 3.6 Volts Supply current 160 mA Ground current 200 mA External current limit of each GPIO 25 mA Total current limit for GPIO[15:8] and GPIO[7:0] 100 mA Total current limit for GPIO[15:0] 200 mA Total supply current sourced by all GPIOs 160 mA Operating Temperature -40o to +85oC Storage Temperature -65o to +150oC Power Dissipation 200 mW TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) Thermal Resistance (24-QFN) theta-ja = 38oC/W, theta-jc = 26oC/W Thermal Resistance (24-TSSOP) theta-ja = 84oC/W, theta-jc = 16oC/W 10

XRA1405 REV. 1.0.0 16-BIT SPI GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS UNLESS OTHERWISE NOTED: TA = -40O TO +85OC, VCC IS 1.65V TO 3.6V LIMITS LIMITS LIMITS SYMBOL PARAMETER 1.8V ± 10% 2.5V ± 10% 3.3V ± 10% UNITS CONDITIONS MIN MAX MIN MAX MIN MAX V Input Low Voltage -0.3 0.2 -0.3 0.5 -0.3 0.8 V Note 1 IL V Input High Voltage 1.4 5.5 1.8 5.5 2.0 5.5 V Note 1 IH V Output Low Voltage 0.4 V I = 6 mA OL OL 0.4 V I = 4 mA OL 0.4 V I = 1.5 mA OL Note 2 & Note 4 V Output Low Voltage 0.5 0.5 0.5 V I = 8 mA OL OL Note 3 V Output High Voltage 2.0 V I = -4 mA OH OL 1.8 V I = -2 mA OL 1.4 V I = -0.2 mA OL Note 2 V Output High Voltage 2.6 V I = -8 mA OH OH 1.8 V I = -8 mA OH 1.2 V I = -8 mA OH Note 3 I Input Low Leakage Current ±10 ±10 ±10 uA IL I Input High Leakage Current ±10 ±10 ±10 uA IH C Input Pin Capacitance 5 5 5 pF IN I Power Supply Current 0.5 1.0 2.0 mA Test 1 CC I Power Supply Current 0.6 1.2 2.4 mA Test 2 CC I Standby Current 1 2 5 uA Test 3 CCS RGPIO GPIO pull-up resistance 60 140 60 140 60 140 kΩ 100kΩ ± 40% NOTE: The Vcc comes from VCCP pin for the GPIOs and the VCC pin for the other signals; NOTES: 1. For SPI input signals (SI, SCL) & GPIOs, A0, A1 and A2 signals; 2. For SPI output signal SO; 3. For GPIOs; 4. For IRQ# signal; Test 1: SCL frequency is 10 MHz with internal pull-ups disabled. All GPIOs are configured as inputs. All inputs are steady at VCC or GND. Outputs are floating or in the tri-state mode. Test 2: SCL frequency is 10 MHz with internal pull-ups enabled. All GPIOs are configured as inputs. All inputs are steady at VCC or GND. Outputs are floating or in the tri-state mode. 11

XRA1405 16-BIT SPI GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS REV. 1.0.0 Test 3: All inputs are steady at VCC or GND to minimize standby current. If internal pull-up is enabled, input voltage level should be the same as VCC. SCL and SI are at GND. CS# is at VCC. All GPIOs are configured as inputs. Outputs are left floating or in tri-state mode. AC ELECTRICAL CHARACTERISTICS - SPI-BUS TIMING SPECIFICATIONS Unless otherwise noted: TA=-40o to +85oC, Vcc=1.65V - 3.6V LIMITS LIMITS LIMITS SYMBOL PARAMETER 1.8V ± 10% 2.5V ± 10% 3.3V ± 10% UNIT CONDITIONS MIN MAX MIN MAX MIN MAX f Operating frequency 15 26 26 MHz SCL T CS# to SCL setup time 20 20 20 ns CSS T CS# to SCL hold time 20 20 20 ns CSH T SCL fall to SO valid time 100 100 100 ns C = 30 pF DO L T SI to SCL setup time 20 20 20 ns DS T SI to SCL hold time 20 20 20 ns DH T SCL period 66 38 38 ns T + T CP CH CL T SCL HIGH time 30 15 15 ns CH T SCL LOW time 30 15 15 ns CL T CS# HIGH pulse width 30 30 30 ns CSW T SPI input pin interrupt clear 200 200 200 ns D13 NOTE: The Vcc comes from the VCC pin. 12

XRA1405 REV. 1.0.0 16-BIT SPI GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS FIGURE 5. SPI-BUS TIMING CS# ... TCSH TCSS TCL TCH TCSH TCSW SCLK ... TDH TDS SI ... TDO TTR ... SO FIGURE 6. READ INPUT PORT TO CLEAR GPIO INT CS# SCL SI 1 0 0 A3 A2 A1 A0 X SO D7 D6 D5 D4 D3 D2 D1 D0 TD13 INT# 13

XRA1405 16-BIT SPI GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS REV. 1.0.0 PACKAGE DIMENSIONS (24 PIN QFN - 4 X 4 X 0.9 mm) θ Note: the actual center pad is metallic and the size (D2) is device-dependent with a typical tolerance of 0.3mm Note: The control dimension is in millimeter. INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A - 0.039 - 1.00 A1 0.000 0.002 0.00 0.05 A3 0.006 0.010 0.15 0.25 θ 0 14o 0 14o D 0.154 0.161 3.90 4.10 D2 0.087 0.102 2.20 2.60 b 0.007 0.012 0.18 0.30 e 0.020 BSC 0.50 BSC L 0.012 0.020 0.30 0.50 k 0.008 - 0.20 - 14

XRA1405 REV. 1.0.0 16-BIT SPI GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS PACKAGE DIMENSIONS (24 PIN TSSOP - 4.4 mm) Note: The control dimension is in millimeter. INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.031 0.047 0.80 1.20 A1 0.002 0.006 0.05 0.15 A2 0.031 0.041 0.80 1.05 b 0.007 0.012 0.19 0.30 C 0.004 0.008 0.09 0.2 D 0.303 0.311 7.70 7.90 E 0.240 0.264 6.10 6.70 E1 0.169 0.177 4.30 4.50 e 0.0256 BSC 0.65 BSC L 0.018 0.030 0.45 0.75 α 0° 8° 0° 8° 15

XRA1405 16-BIT SPI GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS REV. 1.0.0 REVISION HISTORY DATE REVISION DESCRIPTION September 2011 1.0.0 Final Datasheet. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2011 EXAR Corporation Datasheet September 2011. Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 16