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  • 型号: VNS1NV04DPTR-E
  • 制造商: STMicroelectronics
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VNS1NV04DPTR-E产品简介:

ICGOO电子元器件商城为您提供VNS1NV04DPTR-E由STMicroelectronics设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 VNS1NV04DPTR-E价格参考¥6.21-¥6.21。STMicroelectronicsVNS1NV04DPTR-E封装/规格:PMIC - 配电开关,负载驱动器, 。您可以下载VNS1NV04DPTR-E参考资料、Datasheet数据手册功能说明书,资料中有VNS1NV04DPTR-E 详细功能的应用电路图电压和使用方法及教程。

产品参数 图文手册 常见问题
参数 数值
产品目录

集成电路 (IC)半导体

描述

MOSFET N-CH 40V 1.7A 8SOIC门驱动器 OMNIFET POWER MOSFET 40V 1.7 A

产品分类

PMIC - MOSFET,电桥驱动器 - 内部开关电源管理 IC

Id-ContinuousDrainCurrent

30 uA

品牌

STMicroelectronics

产品手册

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产品图片

rohs

符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求

产品系列

门驱动器,STMicroelectronics VNS1NV04DPTR-EOMNIFET II™, VIPower™

数据手册

点击此处下载产品Datasheet

产品型号

VNS1NV04DPTR-E

Pd-PowerDissipation

4 W

Qg-GateCharge

5 nC

RdsOn-Drain-SourceResistance

250 mOhms

Vds-Drain-SourceBreakdownVoltage

45 V

上升时间

500 ns

下降时间

600 ns

产品

MOSFET Gate Drivers

产品培训模块

http://www.digikey.cn/PTM/IndividualPTM.page?site=cn&lang=zhs&ptm=26261

产品种类

门驱动器

供应商器件封装

8-SO

其它名称

497-11722-6

其它有关文件

http://www.st.com/web/catalog/sense_power/FM1965/CL1969/SC1038/PF250596?referrer=70071840

包装

Digi-Reel®

商标

STMicroelectronics

安装类型

表面贴装

安装风格

SMD/SMT

导通电阻

250 毫欧

封装

Reel

封装/外壳

8-SOIC(0.154",3.90mm 宽)

封装/箱体

SO-8

工作温度

-40°C ~ 150°C

工厂包装数量

2500

标准包装

1

正向跨导-最小值

2 S

电压-电源

-

电流-峰值输出

3.5A

电流-输出/通道

1.7A

电源电流

150 uA

类型

Power MOSFET

系列

VNS1NV04DP-E

输入类型

非反相

输出数

2

输出电流

- 3 A

配置

Single

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PDF Datasheet 数据手册内容提取

VNS1NV04DP-E OMNIFET II fully autoprotected Power MOSFET Features M ax On-state resistance(1) R 250m DS(ON) Current limitation (typ)(1) I 1.7A LIMH Drain-Source clamp voltage(1) V 40V CLAMP 1. Per each device. SO-8 • Linear current limitation • Thermal shutdown Description • Short circuit protection The VNS1NV04DP-E is a device formed by two • Integrated clamp monolithic OMNIFET II chips housed in a • Low current drawn from input pin standard SO-8 package. The OMNIFET II are • Diagnostic feedback through input pin designed in STMicroelectronics VIPower™ M0-3 technology: they are intended for replacement of • ESD protection standard Power MOSFETs from DC up to 50KHz • Direct access to the gate of the power mosfet applications. Built in thermal shutdown, linear (analog driving) current limitation and overvoltage clamp protects • Compatible with standard power mosfet the chip in harsh environments. • In compliance with the 2002/95/EC european Fault feedback can be detected by monitoring the directive voltage at the input pin. Table 1. Device summary Order codes Package Tube Tape and reel SO-8 VNS1NV04DP-E VNS1NV04DPTR-E September 2013 Doc ID 17344 Rev 3 1/24 www.st.com 1

Contents VNS1NV04DP-E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 Overvoltage clamp protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 Linear current limiter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 Overtemperature and short circuit protection . . . . . . . . . . . . . . . . . . . . . . 16 3.4 Status feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2 SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3 SO-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/24 Doc ID 17344 Rev 3

VNS1NV04DP-E List of tables List of tables Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. Off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. On. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 6. Dynamic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 7. Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 8. Source Drain diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 9. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 10. Thermal parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 11. SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Doc ID 17344 Rev 3 3/24

List of figures VNS1NV04DP-E List of figures Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. Switching time test circuit for resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5. Test circuit for diode recovery times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 6. Unclamped inductive load test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 7. Input charge test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 8. Unclamped inductive waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 9. Source-drain diode forward characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 10. Static drain-source on resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 11. Derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 12. Static drain-source on resistance vs input voltage (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 13. Static drain-source on resistance vs input voltage (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 14. Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 15. Static drain-source on resistance vs id. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 16. Transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 17. Turn-on current slope (part1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 18. Turn-on current slope (part2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 19. Input voltage vs input charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 20. Turn-off drain source voltage slope (part1/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 21. Turn-off drain-source voltage slope (part2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 22. Capacitance variations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 23. Switching time resistive load (part1/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 24. Switching time resistive load (part2/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 25. Output characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 26. Normalized on resistance vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 27. Normalized input threshold voltage vs temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 28. Normalized current limit vs junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 29. Step response current limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 30. SO-8 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 31. Rthj-amb vs PCB copper area in open box free air condition. . . . . . . . . . . . . . . . . . . . . . . 17 Figure 32. SO-8 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 33. Thermal fitting model of a double channel HSD in SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 34. SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 35. SO-8 tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 36. SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4/24 Doc ID 17344 Rev 3

VNS1NV04DP-E Block diagram and pin description 1 Block diagram and pin description Figure 1. Block diagram DRAIN1 DRAIN2 OVERVOLTAGE OVERVOLTAGE CLAMP CLAMP INPUT1 GATE GATE INPUT2 CONTROL CONTROL LINEAR LINEAR TEMPOEVREARTURE CLUIMRRITEENRT CLUIMRRITEENRT TEMPOEVREARTURE SOURCE1 SOURCE2 Figure 2. Configuration diagram (top view) SOURCE 1 1 8 DRAIN 1 INPUT 1 DRAIN 1 SOURCE 2 DRAIN 2 INPUT 2 4 5 DRAIN 2 Doc ID 17344 Rev 3 5/24

Electrical specifications VNS1NV04DP-E 2 Electrical specifications Figure 3. Current and voltage conventions IIN1 RIN1 ID1 INPUT 1 DRAIN 1 VIN1 IIN2 RIN2 ID2 VDS1 INPUT 2 DRAIN 2 VIN2 SOURCE 1 SOURCE 2 VDS1 2.1 Absolute maximum ratings Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to Absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE program and other relevant quality document. T able 2. Absolute maximum ratings Symbol Parameter Value Unit V Drain-source voltage (V =0V) Internally clamped V DSn INn V Input voltage Internally clamped V INn I Input current +/-20 mA INn R Minimum input series impedance 330  IN MINn I Drain current Internally limited A Dn I Reverse DC output current -3 A Rn V Electrostatic discharge (R=1.5K, C=100pF) 4000 V ESD1 Electrostatic discharge on output pins only V 16500 V ESD2 (R=330, C=150pF) P Total dissipation at T =25°C 4 W tot c T Operating junction temperature Internally limited °C j T Case operating temperature Internally limited °C c T Storage temperature -55 to 150 °C stg 6/24 Doc ID 17344 Rev 3

VNS1NV04DP-E Electrical specifications 2.2 Thermal data T able 3. Thermal data Symbol Parameter Max. value Unit R Thermal resistance junction-lead (per channel) 30 °C/W thj-lead R Thermal resistance junction-ambient See Figure31 °C/W thj-amb 2.3 Electrical characteristics T able 4. Off(1) Symbol Parameter Test conditions Min. Typ. Max. Unit Drain-source clamp V V =0V; I =0.5A 40 45 55 V CLAMP voltage IN D Drain-source clamp V V =0V; I =2mA 36 V CLTH threshold voltage IN D Input threshold V V =V ; I =1mA 0.5 2.5 V INTH voltage DS IN D Supply current from I V =0V; V =5V 100 150 µA ISS input pin DS IN V Input-source clamp IIN=1mA 6 6.8 8 V INCL voltage I =-1mA -1.0 -0.3 V IN Zero input voltage V =13V; V =0V; T =25°C 30 µA I drain current DS IN j DSS V = 25V; V =0V 75 µA (V =0V) DS IN IN 1. -40°C<T <150°C, unless otherwise specified. j T able 5. On(1) Symbol Parameter Test conditions Min. Typ. Max. Unit R Static drain-source on VIN=5V; ID=0.5A; Tj= 25°C 250 m DS(on) resistance V =5V; I =0.5A 500 m IN D 1. -40°C<T <150°C, unless otherwise specified. j T able 6. Dynamic(1) Symbol Parameter Test conditions Min. Typ. Max. Unit Forward g (1) V =13V; I =0.5A 2 S fs transconductance DD D C Output capacitance V =13V; f=1MHz; V =0V 90 pF OSS DS IN 1. T = 25°C, unless otherwise specified. j Doc ID 17344 Rev 3 7/24

Electrical specifications VNS1NV04DP-E T able 7. Switching(1) Symbol Parameter Test conditions Min. Typ. Max. Unit t Turn-on delay time 70 200 ns d(on) V =15V; I =0.5A; t Rise time DD D 170 500 ns r V =5V; R =R =330 gen gen IN MIN t Turn-off delay time 350 1000 ns d(off) (see Figure4) t Fall time 200 600 ns f t Turn-on delay time 0.25 1 µs d(on) V =15V; I =0.5A t Rise time DD D 1.3 4 µs r V =5V; R =2.2K gen gen t Turn-off delay time 1.8 5.5 µs d(off) (see Figure4) t Fall time 1.2 4 µs f V =15V; I =1.5A (dI/dt) Turn-on current slope DD D 5 A/µs on V =5V; R =R =330 gen gen IN MIN V =12V; I =0.5A; V =5V Q Total input charge DD D IN 5 nC i I =2.13mA (see Figure7) gen 1. T = 25°C, unless otherwise specified. j T able 8. Source Drain diode(1) Symbol Parameter Test conditions Min. Typ. Max. Unit V (2) Forward on voltage I =0.5A; V =0V - 0.8 - V SD SD IN t Reverse recovery time - 205 - ns rr I =0.5A; dI/dt=6A/µs SD Q Reverse recovery charge V =30V; L=200µH - 100 - nC rr DD (see Figure5) I Reverse recovery current - 0.75 - A RRM 1. T = 25°C, unless otherwise specified. j 2. Pulsed: pulse duration = 300µs, duty cycle 1.5%. T able 9. Protections(1) Symbol Parameter Test conditions Min. Typ. Max. Unit I Drain current limit V =5V; V =13V 1.7 3.5 A lim IN DS Step response current t V =5V; V =13V 2 µs dlim limit IN DS Overtemperature T 150 175 200 °C jsh shutdown T Overtemperature reset 135 °C jrs I Fault sink current V =5V; V =13V; T =T 10 15 20 mA gf IN DS j jsh Starting T =25°C; V =24V j DD Single pulse V =5V R =R =330 E IN gen INMIN 55 mJ as avalanche energy L=50mH (see Figure6 and Figure8) 1. -40°C < T < 150°C, unless otherwise specified. j 8/24 Doc ID 17344 Rev 3

VNS1NV04DP-E Electrical specifications Figure 4. Switching time test circuit for resistive load VD Rgen Vgen I D 90% tr 10% tf t V td(on) td(off) gen t Figure 5. Test circuit for diode recovery times A A D I FAST L=100uH OMNIFET DIODE S B B 330 D V R DD gen I OMNIFET V gen S 8.5  Doc ID 17344 Rev 3 9/24

Electrical specifications VNS1NV04DP-E Figure 6. Unclamped inductive load test circuits R GEN V IN P W Figure 7. Input charge test circuit V GEN IN ND8003 10/24 Doc ID 17344 Rev 3

VNS1NV04DP-E Electrical specifications Figure 8. Unclamped inductive waveforms Doc ID 17344 Rev 3 11/24

Electrical specifications VNS1NV04DP-E 2.4 Electrical characteristics curves Figure 9. Source-drain diode forward Figure 10. Static drain-source on characteristics resistance Vsd (mV) Rds(on) (ohms) 1000 4.5 Tj=-40ºC 4 950 Vin=2.5V 3.5 Vin=0V 900 3 2.5 850 2 800 1.5 Tj=25ºC 1 750 Tj=150ºC 0.5 700 0 0 2 4 6 8 10 12 14 0 0.05 0.1 0.15 0.2 0.25 0.3 Id (A) Id(A) Figure 11. Derating curve Figure 12. Static drain-source on resistance vs input voltage (part 1/2) Rds(on) (mohms) 500 450 Id=0.5A 400 Tj=150ºC 350 300 250 200 Tj=25ºC 150 Tj=-40ºC 100 50 0 3 3.5 4 4.5 5 5.5 6 6.5 7 Vin(V) Figure 13. Static drain-source on Figure 14. Transconductance resistance vs input voltage (part 2/2) Rds(on) (mohms) 500 Gfs (S) Tj=150ºC 6 450 5.5 400 Id=1.5A 5 Vds=13V Tj=-40ºC 350 Id=1A 4.5 Tj=25ºC 300 4 Tj=150ºC 250 Tj=25ºC 3.5 3 200 Id=1.5A 2.5 Tj=-40ºC Id=1A 150 2 Id=1.5A 100 Id=1A 1.5 50 1 0.5 0 3 3.5 4 4.5 5 5.5 6 6.5 0 Vin(V) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 Id(A) 12/24 Doc ID 17344 Rev 3

VNS1NV04DP-E Electrical specifications Figure 15. Static drain-source on Figure 16. Transfer characteristics resistance vs id Rds(on) (mohms) Idon(A) 500 2.25 Vin=3.5V 450 Tj=25ºC 2 400 Tj=150ºC Vds=13.5V Vin=5V 1.75 350 1.5 300 1.25 250 Vin=3.5V 1 Tj=150ºC 200 Tj=25ºC Tj=-40ºC Vin=5V 0.75 Vin=3.5V 150 Tj=-40ºC 0.5 Vin=5V 100 0.25 50 0 0 1.5 2 2.5 3 3.5 4 4.5 5 1.75 2.25 2.75 3.25 3.75 4.25 4.75 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 Vin(V) Id(A) Figure 17. Turn-on current slope Figure 18. Turn-on current slope (part1/2) (part2/2) di/dt(A/us) di/dt(A/us) 1.4 6 1.2 5 Vin=3.5V Vin=5V Vdd=15V 4 VIdd=d1=.155AV 1 Id=1.5A 0.8 3 0.6 2 0.4 1 0.2 0 0 500 1000 1500 2000 2500 0 500 1000 1500 2000 2500 Rg(ohm) Rg(ohm) Figure 19. Input voltage vs input charge Figure 20. Turn-off drain source voltage slope (part1/2) Vin (V) dv/dt(V/us) 6 350 5 300 Vds=12V Vin=5V Id=0.5A 250 Vdd=15V 4 Id=0.5A 200 3 150 2 100 1 50 0 0 0 1 2 3 4 5 6 0 500 1000 1500 2000 2500 Qg (nC) Rg(ohm) Doc ID 17344 Rev 3 13/24

Electrical specifications VNS1NV04DP-E Figure 21. Turn-off drain-source voltage Figure 22. Capacitance variations slope (part2/2) dv/dt(V/us) C(pF) 350 225 300 200 f=1MHz Vin=3.5V Vin=0V 250 Vdd=15V 175 Id=0.5A 200 150 150 125 100 100 50 75 0 50 0 500 1000 1500 2000 2500 0 5 10 15 20 25 30 35 Rg(ohm) Vds(V) Figure 23. Switching time resistive load Figure 24. Switching time resistive load (part1/2) (part2/2) t(us) t(ns) 2 550 500 1.75 td(off) tr Vdd=15V Vdd=15V 450 Id=0.5A 1.5 Id=0.5A Rg=330ohm 400 Vin=5V tr 1.25 350 td(off) tf 300 1 250 tf 0.75 200 0.5 150 td(on) 100 td(on) 0.25 50 0 0 0 250 500 750 1000 1250 1500 1750 20002250 2500 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 Rg(ohm) Vin(V) Figure 25. Output characteristics Figure 26. Normalized on resistance vs temperature ID(A) Rds(on) (mOhm) 2.25 2.4 2.2 Vin=5.5V 2 2 Vin=4.5V Vin=5V Vin=3.5V Id=0.5A 1.8 1.75 1.6 1.5 1.4 1.2 1.25 1 0.8 1 0.6 0.4 0.75 Vin=3V 0.2 0 0.5 0 1 2 3 4 5 6 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 150 175 VDS(V) Tc (ºC) 14/24 Doc ID 17344 Rev 3

VNS1NV04DP-E Electrical specifications Figure 27. Normalized input threshold Figure 28. Normalized current limit vs voltage vs temperature junction temperature Vinth (V) Ilim (A) 2 5 1.8 4.5 Vds=Vin Vin=5V 1.6 4 Id=1mA Vds=13V 1.4 3.5 1.2 3 1 2.5 0.8 2 0.6 1.5 0.4 1 0.2 0.5 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (ºC) Tc (ºC) Figure 29. Step response current limit Tdlim(us) 2.4 2.3 Vin=5V Rg=330ohm 2.2 2.1 2 1.9 5 10 15 20 25 30 35 Vdd(V) Doc ID 17344 Rev 3 15/24

Protection features VNS1NV04DP-E 3 Protection features During normal operation, the INPUT pin is electrically connected to the gate of the internal power MOSFET through a low impedance path. The device then behaves like a standard power MOSFET and can be used as a switch from DC up to 50KHz. The only difference from the user’s standpoint is that a small DC current I (typ. 100µA) flows into the INPUT pin in order to supply the internal circuitry. ISS The device integrates: 3.1 Overvoltage clamp protection Internally set at 45V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads. 3.2 Linear current limiter circuit Limits the drain current I to I whatever the INPUT pin voltage. When the current limiter is D lim active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold T jsh. 3.3 Overtemperature and short circuit protection These are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Overtemperature cutout occurs in the range 150 to 190 °C, a typical value being 170 °C. The device is automatically restarted when the chip temperature falls of about 15°C below shutdown temperature. 3.4 Status feedback In the case of an overtemperature fault condition (T > T ), the device tries to sink a j jsh diagnostic current I through the INPUT pin in order to indicate fault condition. If driven from gf a low impedance source, this current may be used in order to warn the control circuit of a device shutdown. If the drive impedance is high enough so that the INPUT pin driver is not able to supply the current I , the INPUT pin will fall to 0V. This will not however affect the gf device operation: no requirement is put on the current capability of the INPUT pin driver except to be able to supply the normal operation drive current I . ISS Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL Logic circuit. 16/24 Doc ID 17344 Rev 3

VNS1NV04DP-E Package and PCB thermal data 4 Package and PCB thermal data 4.1 SO-8 thermal data Figure 30. SO-8 PC board Note: Layout condition of R and Z measurements (PCB FR4 area=58mm x 58mm, PCB th th thickness=2mm, Cu thickness=35µm, Copper areas: from minimum pad lay-out to 0.8cm2). Figure 31. R vs PCB copper area in open box free air condition thj-amb RTH _amb (°C/W) J 115 110 105 100 95 90 85 80 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 PCB Cu heatsink area (cm^2) - (refer to PCB layout) Doc ID 17344 Rev 3 17/24

Package and PCB thermal data VNS1NV04DP-E Figure 32. SO-8 thermal impedance junction ambient single pulse ZTH (°C/W) 1000 0.07cm2 100 0.15 cm2 0.3 cm2 0.6 cm2 10 1 0,1 0,0001 0,001 0,01 0,1 1 10 100 1000 Time (s) Equation 1: pulse calculation formula Z = R +Z 1– TH TH THtp where  = t /T P Figure 33. Thermal fitting model of a double channel HSD in SO-8 18/24 Doc ID 17344 Rev 3

VNS1NV04DP-E Package and PCB thermal data T able 10. Thermal parameters Area/island (cm2) 0.07 0.15 0.3 0.6 R1 = R7 (°C/W) 0.02 R2 = R8 (°C/W) 2 R3 = R9 (°C/W) 11 R4 = R10 (°C/W) 30 R5 = R11 (°C/W) 25 R6 = R12 (°C/W) 100 87.5 74.2 62.6 R13 = R14 (°C/W) 250 C1=C2=C7=C8 (W.s/°C) 0.0005 C3 = C9 (W.s/°C) 0.02 C4 = C10 (W.s/°C) 0.035 C5 = C11 (W.s/°C) 0.2 C6 = C12 (W.s/°C) 0.4 0.51 0.65 0.95 Doc ID 17344 Rev 3 19/24

Package and packing information VNS1NV04DP-E 5 Package and packing information ® 5.1 ECOPACK packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 5.2 SO-8package information Figure 34. SO-8 package dimensions 20/24 Doc ID 17344 Rev 3

VNS1NV04DP-E Package and packing information T able 11. SO-8 mechanical data Millimeters Symbol Min. Typ. Max. A 1.75 A1 0.10 0.25 A2 1.25 b 0.28 0.48 c 0.17 0.23 D(1) 4.80 4.90 5.00 E 5.80 6.00 6.20 E1(2) 3.80 3.90 4.00 e 1.27 h 0.25 0.50 L 0.40 1.27 L1 1.04 k 0° 8° ccc 0.10 1. Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm in total (both side). 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. Doc ID 17344 Rev 3 21/24

Package and packing information VNS1NV04DP-E 5.3 SO-8 packing information Figure 35. SO-8 tube shipment (no suffix) B C Base Q.ty 100 Bulk Q.ty 2000 Tube length (± 0.5) 532 A A 3.2 B 6 C (± 0.1) 0.6 All dimensions are in mm. Figure 36. SO-8 tape and reel shipment (suffix “TR”) REEL DIMENSIONS Base Q.ty 2500 Bulk Q.ty 2500 A (max) 330 B (min) 1.5 C (± 0.2) 13 F 20.2 G (+ 2 / -0) 12.4 N (min) 60 T (max) 18.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width W 12 Tape Hole Spacing P0 (± 0.1) 4 Component Spacing P 8 Hole Diameter D (± 0.1/-0) 1.5 Hole Diameter D1 (min) 1.5 Hole Position F (± 0.05) 5.5 Compartment Depth K (max) 4.5 Hole Spacing P1 (± 0.1) 2 All dimensions are in mm. End Start Top No components Components No components cover tape 500mm min Empty components pockets 500mm min saled with cover tape. User direction of feed 22/24 Doc ID 17344 Rev 3

VNS1NV04DP-E Revision history 6 Revision history T able 12. Document revision history Date Revision Changes 09-Jun-2008 1 Initial release. Changed template. 02-Apr-2010 2 Updated Table17: Turn-on current slope (part1/2). 20-Sep-2013 3 Updated Disclaimer. Doc ID 17344 Rev 3 23/24

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