Product Sample & Technical Tools & Support & Folder Buy Documents Software Community UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 UCC28950 Green Phase-Shifted Full-Bridge Controller With Synchronous Rectification 1 Features 3 Description • EnhancedWideRangeResonantZeroVoltage The UCC28950 enhanced phase-shifted controller 1 builds upon Texas Instrument’s industry standard Switching(ZVS)Capability UCx895 phase-shifted controller family with • DirectSynchronousRectifier(SR)Control enhancements that offer best in class efficiency in • Light-LoadEfficiencyManagementIncluding today’s high performance power systems. The – BurstModeOperation UCC28950 implements advanced control of the full- bridge along with active control of the synchronous – DiscontinuousConductionMode(DCM), rectifieroutputstage. DynamicSROnandOffControlwith ProgrammableThreshold The primary-side signals allow programmable delays to ensure ZVS operation over wide-load current and – ProgrammableAdaptiveDelay input voltage range, while the load current naturally • AverageorPeakCurrentModeControlWith tunes the secondary-side synchronous rectifiers ProgrammableSlopeCompensationandVoltage switching delays, maximizing overall system ModeControl efficiency. • NaturallyHandlesPre-BiasedStartUpWithDCM The UCC28950 also offers multiple light-load Mode management features including burst mode and • ClosedLoopSoftStartandEnableFunction dynamic SR on/off control when transitioning in and out of Discontinuous Current Mode (DCM) operation, • ProgrammableSwitchingFrequencyupto1MHz ensuring ZVS operation is extended down to much withBi-DirectionalSynchronization lighterloads. • (±3%)Cycle-by-CycleCurrentLimitProtection In addition, the UCC28950 includes support for WithHiccupModeSupport current or voltage mode control. Programmable • 150-µAStart-UpCurrent switching frequency up to 1 MHz and a wide set of • V UndervoltageLockout protection features including cycle-by-cycle current DD • WideTemperatureRange–40°Cto+125°C limit, UVLO and thermal shutdown. A 90-degree phase-shifted interleaved synchronized operation can 2 Applications beeasilyarrangedbetweentwoconverters. TheUCC28950isavailableinTSSOP-24package. • Phase-ShiftedFull-BridgeConverters • Datacom,Telecom,andWirelessBase-Station DeviceInformation(1) Power PARTNUMBER PACKAGE BODYSIZE(NOM) • Server,PowerSupplies UCC28950 TSSOP(24) 7.80mmx4.40mm • IndustrialPowerSystems (1) For all available packages, see the orderable addendum at • High-DensityPowerArchitectures theendofthedatasheet. • SolarInverters,andElectricVehicles UCC28950TypicalApplication + CT V-IN CIN R1 CREF R2 1 VREFUCC28950GND 24 CVDD VDD VBIASRLF2 2 EA+ VDD 23 R3 C1 3 EA- OUTA 22 A VDD VDD VSENSE R6 R4 C3 C2 R5 4 COMP OUTB 21 B A QA T1 QC C CSS 5 SS/EN OUTC 20 C ENABLE RAB 6 DELAB OUTD 19 D RCD 7 DELCD OUTE 18 E VDD VDD REF 8 DELEF OUTF 17 F B QB LOUT QD D RT RTMIN 9 TMIN SYNC 16 SYNCRAHI VOUT VREF 10 RT CS 15 + RSUM 11 RSUM ADEL 14 UCC27324 UCC27324 VREF RDCMHI 12 DCM ADELEF 13 RAEFHI E QE QF F COUT RA - R7 DA RCS RDCM RLF1 CLF RAEF VSENSE 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com Table of Contents 1 Features.................................................................. 1 7.3 FeatureDescription.................................................17 2 Applications........................................................... 1 7.4 DeviceFunctionalModes........................................34 3 Description............................................................. 1 8 ApplicationandImplementation........................ 35 4 RevisionHistory..................................................... 2 8.1 ApplicationInformation............................................35 8.2 TypicalApplication..................................................38 5 PinConfigurationandFunctions......................... 4 9 PowerSupplyRecommendations...................... 66 6 Specifications......................................................... 5 10 Layout................................................................... 66 6.1 AbsoluteMaximumRatings......................................5 6.2 ESDRatings..............................................................5 10.1 LayoutGuidelines.................................................66 6.3 RecommendedOperatingConditions.......................5 10.2 LayoutExample....................................................67 6.4 ThermalInformation..................................................6 11 DeviceandDocumentationSupport................. 68 6.5 ElectricalCharacteristics...........................................6 11.1 DeviceSupport......................................................68 6.6 TimingRequirements................................................8 11.2 DocumentationSupport........................................68 6.7 DissipationRatings...................................................8 11.3 CommunityResources..........................................68 6.8 TypicalCharacteristics............................................11 11.4 Trademarks...........................................................68 7 DetailedDescription............................................ 15 11.5 ElectrostaticDischargeCaution............................68 7.1 Overview.................................................................15 11.6 Glossary................................................................68 7.2 FunctionalBlockDiagram.......................................16 12 Mechanical,Packaging,andOrderable Information........................................................... 68 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionC(November2015)toRevisionD Page • ChangedPinFunctionstabletobealphabetized. ................................................................................................................. 4 • AddedtexttoUCC28950StartupTimingDiagramnote,"Narrowerpulsewidths(lessthan50%dutycycle)maybe observedinthefirstOUTDpulseofaburst.Theusermustdesignthebootstrapcapacitorchargingcircuitofthe gatedriverdevicesothatthefirstOUTCpulseistransmittedtotheMOSFETgateinallcases.Transformerbased gatedrivercircuitsarenotaffected.Thisbehaviorisdescribedinmoredetailintheapplicationnote,GateDriver DesignConsiderations".......................................................................................................................................................... 9 ChangesfromRevisionB(October2011)toRevisionC Page • AddedPinConfigurationandFunctionssection,HandlingRatingtable,FeatureDescriptionsection,Device FunctionalModes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layout section,DeviceandDocumentationSupportsection,andMechanical,Packaging,andOrderableInformation section ................................................................................................................................................................................... 1 • MovedStandardTemperatureRangefromESDtabletoAbsoluteMaximumRatingstable ............................................... 5 • ChangedFigure6StartupCurrentvaluefrommAtoµA..................................................................................................... 11 • ChangedFigure11NominalSwitchingFrequencyvaluefromHztokHz........................................................................... 12 • ChangedFigure12MaximumSwitchingFrequencyvaluefromHztokHz. ....................................................................... 12 • UpdatedAdaptiveDelaysection.......................................................................................................................................... 19 • ChangedvaluesinEquation3 ............................................................................................................................................ 19 • ChangedvaluesinEquation4 ............................................................................................................................................ 19 • ChangedlineinFigure34tostopatR =10kΩandTMIN=800ns.............................................................................. 23 TMIN • ChangedcontentinSlopeCompensation(R )section.................................................................................................... 25 SUM • AddedT settingtoFigure39............................................................................................................................................ 27 MIN • UpdatedSynchronization(SYNC)section............................................................................................................................ 31 • ChangedDetailedDesignProcedureintheTypicalApplicationsection............................................................................. 39 • DeletedV vs.Q forQEandQFFETsgraphfromSelectFETsQEandQFsection........................................................ 48 g g • AddedDaughterBoardSchematic. ..................................................................................................................................... 62 2 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 • AddedPowerStageSchematic. .......................................................................................................................................... 63 ChangesfromRevisionA(July2010)toRevisionB Page • AddedNaturallyHandlesPre-BiasedStartUpwithDCMModebullet.................................................................................. 1 • AddedDatacom,Telecom,andWirelessBase-StationPower.............................................................................................. 1 • ChangedServer,TelecomPowerSuppliesbullettoServer,PowerSupplies....................................................................... 1 ChangesfromOriginal(March2010)toRevisionA Page • ChangedUCC28950TypicalApplicationDiagram................................................................................................................. 1 • ChangedConverterswitchingfrequencyfrom1400kHzto1000kHz................................................................................... 5 • ChangedFunctionalBlockDiagram..................................................................................................................................... 16 • AddedFigure30................................................................................................................................................................... 20 • ChangedEquation................................................................................................................................................................ 21 • AddedTypicalApplicationDiagram...................................................................................................................................... 21 • AddedalwaysdeliverevennumberofPowercyclestoPowertransformer........................................................................ 23 • Deleteddelivereitheroneortwopowerdeliverycyclepulses.IfcontrollerdeliversapowerdeliverycycleforOUTB andOUTC,thenitstops.IfitstartsdeliveringtoOUTAandOUTD,thenitcontinueswithanotherpowerdelivery cycletoOUTBandOUTC,andthenitstops....................................................................................................................... 23 Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com 5 Pin Configuration and Functions PWPackage 24-PinTSSOP TopView UCC28950 1 VREF GND 24 2 EA+ VDD 23 3 EA- OUTA 22 4 COMP OUTB 21 5 SS/EN OUTC 20 6 DELAB OUTD 19 7 DELCD OUTE 18 8 DELEF OUTF 17 9 TMIN SYNC 16 10 RT CS 15 11 RSUM ADEL 14 12 DCM ADELEF 13 PinFunctions PIN I/O DESCRIPTION NO. NAME Dead-timeprogrammingfortheprimaryswitchesoverCSvoltagerange,T and 14 ADEL I ABSET T . CDSET Delay-timeprogrammingbetweenprimarysideandsecondarysideswitches,T 13 ADELEF I AFSET andT . BESET 4 COMP I/O ErroramplifieroutputandinputtothePWMcomparator. 15 CS I Currentsenseforcycle-by-cycleover-currentprotectionandadaptivedelayfunctions. 12 DCM I DCMthresholdsetting. 6 DELAB I Dead-timedelayprogrammingbetweenOUTAandOUTB. 7 DELCD I Dead-timedelayprogrammingbetweenOUTCandOUTD. 8 DELEF I Delay-timeprogrammingbetweenOUTAtoOUTF,andOUTBtoOUTE. 2 EA+ I Erroramplifiernon-invertinginput. 3 EA– I Erroramplifierinvertinginput. 24 GND — Ground.Allsignalsarereferencedtothisnode. 22 OUTA O 0.2-Asink/sourceprimaryswitchingoutput. 21 OUTB O 0.2-Asink/sourceprimaryswitchingoutput. 20 OUTC O 0.2-Asink/sourceprimaryswitchingoutput. 19 OUTD O 0.2-Asink/sourceprimaryswitchingoutput. 18 OUTE O 0.2-Asink/sourcesynchronousswitchingoutput. 11 RSUM I Slopecompensationprogramming.Voltagemodeorpeakcurrentmodesetting. 10 RT I Oscillatorfrequencyset.Masterorslavemodesetting. 5 SS/EN I Soft-startprogramming,deviceenableandhiccupmodeprotectioncircuit. 16 SYNC I/O SynchronizationoutfromMastercontrollertoinputofslavecontroller. 17 OUTF O 0.2-Asink/sourcesynchronousswitchingoutput. 9 TMIN I Minimumdutycycleprogramminginburstmode. 23 VDD I Biassupplyinput. 1 VREF O 5-V,±1.5%,20-mAreferencevoltageoutput. 4 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1)(2) MIN MAX UNIT Inputsupplyvoltage,V (3) –0.4 20 V DD OUTA,OUTB,OUTC,OUTD,OUTE,OUTF –0.4 VDD+0.4 V InputvoltageonDELAB,DELCD,DELEF,SS/EN,DCM,TMIN,RT,SYNC,RSUM,EA+,EA-, –0.4 VREF+0.4 V COMP,CS,ADEL,ADELEF OutputvoltageonVREF –0.4 5.6 V Continuoustotalpowerdissipation SeeDissipationRatings Operatingvirtualjunctiontemperature,T –40 +150 °C J Operatingambienttemperature,T –40 +125 °C A Leadtemperature(soldering,10sec.) +300 °C Storagetemperature,T –65 +150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Thesedevicesaresensitivetoelectrostaticdischarge;followproperdevicehandlingprocedures. (3) AllvoltagesarewithrespecttoGNDunlessotherwisenoted.Currentsarepositiveinto,negativeoutofthespecifiedterminal.See PackagingSectionofthedatasheetforthermallimitationsandconsiderationsofpackages. 6.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) 2000 V V(ESD) Electrostaticdischarge Chargeddevicemodel(CDM),perJEDECspecificationJESD22- C101(2) 500 V (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT Supplyvoltagerange,V 8 12 17 V DD Operatingjunctiontemperaturerange –40 125 °C Converterswitchingfrequencysettingrange,F 50 1000 kHz SW(nom) ProgrammabledelayrangebetweenOUTA,OUTBandOUTC,OUTDsetby resistorsDELABandDELCDandparameterK (1) 30 1000 ns A ProgrammabledelayrangebetweenOUTA,OUTFandOUTB,OUTEsetby resistorDELEF,andparameterK (1) 30 1400 ns EF ProgrammableDCMrangeaspercentageofvoltageatCS(1) 5% 30% ProgrammableT range 100 800 ns MIN (1) Verifiedduringcharacterizationonly. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com 6.4 Thermal Information UCC28950 THERMALMETRIC(1) PW(TSSOP) UNIT 24PINS R Junction-to-ambientthermalresistance 93.3 °C/W θJA R Junction-to-case(top)thermalresistance 24.2 °C/W θJC(top) R Junction-to-boardthermalresistance 47.9 °C/W θJB ψ Junction-to-topcharacterizationparameter 0.7 °C/W JT ψ Junction-to-boardcharacterizationparameter 47.4 °C/W JB R Junction-to-case(bottom)thermalresistance n/a °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. 6.5 Electrical Characteristics V =12V,T =T =–40°Cto+125°C,C =1µF,C =1µF,R =22.6kΩ,R =22.6kΩ,R =13.3kΩ,R =124 DD A J VDD REF AB CD EF SUM kΩ,R =88.7kΩ,R =59kΩconnectedbetweenRTpinand5-VvoltagesupplytosetF =100kHz(F =200kHz) TMIN T SW OSC (unlessotherwisenoted).AllcomponentdesignationsarefromFigure48. PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT UNDERVOLTAGELOCKOUT(UVLO) UVLO_RTH Startthreshold 6.75 7.3 7.9 V Minimumoperatingvoltage UVLO_FTH 6.15 6.7 7.2 V afterstart UVLO_HYST Hysteresis 0.53 0.6 0.75 V SUPPLYCURRENTS I Startupcurrent V is5.2V 150 270 µA DD(off) DD I Operatingsupplycurrent 5 10 mA DD VREFOUTPUTVOLTAGE V VREFtotaloutputrange 0≤IR≤20mA;V =from8Vto17V 4.925 5 5.075 V REF DD ISCC Shortcircuitcurrent VREF=0V –53 –23 mA SWITCHINGFREQUENCY(½OFINTERNALOSCILLATORFREQUENCYF ) OSC F Totalrange 92 100 108 kHz SW(nom) D Maximumdutycycle 95% 97% MAX SYNCHRONIZATION R =59kΩbetweenRTandGND;Inputpulses PH Totalrange T 85 90 95 °PH SYNC 200kHz,D=0.5atSYNC R =59kΩbetweenRTand5V;–40°C≤T ≤ F Totalrange T J 180 200 220 kHz SYNC +125°C T Pulsewidth 2.2 2.5 2.8 µs PW (1) TypicalvaluesforT =25°C A 6 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 Electrical Characteristics (continued) V =12V,T =T =–40°Cto+125°C,C =1µF,C =1µF,R =22.6kΩ,R =22.6kΩ,R =13.3kΩ,R =124 DD A J VDD REF AB CD EF SUM kΩ,R =88.7kΩ,R =59kΩconnectedbetweenRTpinand5-VvoltagesupplytosetF =100kHz(F =200kHz) TMIN T SW OSC (unlessotherwisenoted).AllcomponentdesignationsarefromFigure48. PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT ERRORAMPLIFIER V rangeensuresparameters,thefunctionality Commonmodeinput ICM V ensuredfor3.6V<V <VREF+0.4V,and 0.5 3.6 V ICM voltagerange ICM –0.4V<V <0.5V ICM V Offsetvoltage –7 7 mV IO I Inputbiascurrent –1 1 µA BIAS EA High-leveloutputvoltage (EA+)–(EA–)=500mV,I =–0.5mA 3.9 4.25 V HIGH EAOUT EA Low-leveloutputvoltage (EA+)–(EA–)=–500mV,I =0.5mA 0.25 0.35 V LOW EAOUT Erroramplifiersource I –8 –3.75 –0.5 mA SOURCE current I Erroramplifiersinkcurrent 2.7 4.6 5.75 mA SINK I Open-loopdcgain 100 dB VOL GBW Unitygainbandwidth(2) 3 MHz CYCLE-BY-CYCLECURRENTLIMIT CSpincycle-by-cycle V 1.94 2 2.06 V CS_LIM threshold INTERNALHICCUPMODESETTINGS Dischargecurrenttoset I cycle-by-cyclecurrentlimit CS=2.5V,VSS=4V 15 20 25 µA DS duration V HiccupOFFTimethreshold 3.2 3.6 4.2 V HCC Dischargecurrenttoset I 1.90 2.55 3.2 µA HCC HiccupModeOFFTime SOFTSTART/ENABLE I Chargecurrent V =0V 20 25 30 µA SS SS Shutdown/restart/reset V 0.25 0.50 0.70 V SS_STD threshold V Pullupthreshold 3.3 3.7 4.3 V SS_PU V Clampvoltage 4.20 4.65 4.95 V SS_CL LIGHT-LOADEFFICIENCYCIRCUIT V =0.4V,SweepCSconfirmthereare DCMthreshold,T=25°C DCM 0.37 0.39 0.41 V OUTEandOUTFpulses DCMthreshold,T=0°Cto V =0.4V,SweepCS,confirmthereare VDCM +85°C (3) ODUCTMEandOUTFpulses 0.364 0.390 0.416 V DCMthreshold,T=–40°C V =0.4V,SweepCS,confirmthereare to+125°C (3) ODUCTMEandOUTFpulses 0.35 0.39 0.43 V I DCMSourcingCurrent CS<DCMthreshold 14 20 26 µA DCM_SRC OUTPUTSOUTA,OUTB,OUTC,OUTD,OUTE,OUTF I Sink/Sourcepeakcurrent(3) 0.2 A SINK/SRC R Outputsourceresistance I =20mA 10 20 35 Ω SRC OUT R Outputsinkresistance I =20mA 5 10 30 Ω SINK OUT THERMALSHUTDOWN Risingthreshold(3) 160 °C Fallingthreshold(3) 140 °C Hysteresis 20 °C (2) Verifiedduringcharacterizationonly. (3) Verifiedduringcharacterizationonly. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com 6.6 Timing Requirements MIN NOM MAX UNIT CYCLE-BY-CYCLECURRENTLIMIT PropagationdelayfromCStoOUTCandOUTDoutputs T 100 ns CS InputpulsebetweenCSandGNDfromzeroto2.5V PROGRAMMABLEDELAYTIMESETACCURACYANDRANGE(1)(2)(3)(4)(5) ShortdelaytimesetaccuracybetweenOUTAandOUTB T 32 45 56 ns ABSET1 CS=ADEL=ADELEF=1.8V LongdelaytimesetaccuracybetweenOUTAandOUTB T 216 270 325 ns ABSET2 CS=ADEL=ADELEF=0.2V ShortdelaytimesetaccuracybetweenOUTCandOUTD T 32 45 56 ns CDSET1 CS=ADEL=ADELEF=1.8V LongdelaytimesetaccuracybetweenOUTCandOUTD T 216 270 325 ns CDSET2 CS=ADEL=ADELEF=0.2V ShortdelaytimesetaccuracybetweenfallingOUTA,OUTF T 22 35 48 ns AFSET1 CS=ADEL=ADELEF=0.2V LongdelaytimesetaccuracybetweenfallingOUTA,OUTF T 190 240 290 ns AFSET2 CS=ADEL=ADELEF=1.8V ShortdelaytimesetaccuracybetweenfallingOUTB,OUTE T 22 35 48 ns BESET1 CS=ADEL=ADELEF=0.2V LongdelaytimesetaccuracybetweenfallingOUTB,OUTE T 190 240 290 ns BESET2 CS=ADEL=ADELEF=1.8V PulsematchingbetweenOUTArise,OUTDfallandOUTBrise, ΔT OUTCfall –50 0 50 ns ADBC CS=ADEL=ADELEF=1.8V,COMP=2V HalfcyclematchingbetweenOUTArise,OUTBriseandOUTBrise, ΔT OUTArise –50 0 50 ns ABBA CS=ADEL=ADELEF=1.8V,COMP=2V PulsematchingbetweenOUTEfall,OUTEriseandOUTFfall,OUTF ΔT rise –60 0 60 ns EEFF CS=ADEL=ADELEF=0.2V,COMP=2V PulsematchingbetweenOUTEfall,OUTFriseandOUTFfall,OUTE ΔT rise –60 0 60 ns EFFE CS=ADEL=ADELEF=0.2V,COMP=2V LIGHT-LOADEFFICIENCYCIRCUIT T Totalrange,R =88.7kΩ 425 525 625 ns MIN TMIN OUTPUTSOUTA,OUTB,OUTC,OUTD,OUTE,OUTF T Risetime,C =100pF 9 25 ns R LOAD T Falltime,C =100pF 7 25 ns F LOAD (1) SeeFigure28fortimingdiagramandT ,T ,T ,T definitions. ABSET1 ABSET2 CDSET1 CDSET2 (2) SeeFigure31fortimingdiagramandT ,T ,T ,T definitions. AFSET1 AFSET2 BESET1 BESET2 (3) PairofoutputsOUTC,OUTEandOUTD,OUTFalwaysgoinghighsimultaneously. (4) OutputsAorBareneverallowedtogohighifbothoutputsOUTEandOUTFarehigh. (5) Alldelaysettingsaremeasuredrelativeto50%ofpulseamplitude. 6.7 Dissipation Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted) PACKAGE DERATINGFACTOR POWERRATING ABOVET =25°C T <25°C T =70°C T =85°C A A A A PW 10.7mW/°C 1.07W 0.59W 0.429W 8 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 VDD 7.3-Vrise,6.7-Vfall VDD_GOOD VREF 4.8-Vrise,4.6-Vfall VREF_GOOD SS>0.5V,thenreleaseCOMP,DCM,CS,OutputsA,B,C,D,EandF CLK TMIN TMIN Add0.85VoffsettoRAMP COMP NoPWMpulsesshorterthanTMIN PWM TMIN 2V exceptduringcycle-by-cyclecurrentlimit P-P RAMP PWM A B C D E F BurstModeatthebeginningof startupuntilPWM>T pulses MIN Nooutputdelayshown,COMP-to-RAMPoffsetnotincluded. ThereisnopulseonOUTEduringburstmodeatstartup.TwofallingedgePWMpulsesarerequiredbeforeenabling thesynchronousrectifieroutputs.Narrowerpulsewidths(lessthan50%dutycycle)maybeobservedinthefirst OUTDpulseofaburst.Theusermustdesignthebootstrapcapacitorchargingcircuitofthegatedriverdevicesothat thefirstOUTCpulseistransmittedtotheMOSFETgateinallcases.Transformerbasedgatedrivercircuitsarenot affected.Thisbehaviorisdescribedinmoredetailintheapplicationnote,GateDriverDesignConsiderations. Figure1. UCC28950StartupTimingDiagram Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com VDD 7.3V rise, 6.7V fall VDD faiElevde raynthdi nVgD Dis_ sGhOuOtdDo wgones low, VDD_GOOD VREF 4.8V rise, 4.6V fall VREF_GOOD TMIN CLK TMIN Add 0.85V offset to RAMP COMP RAMP 2Vp-p PWM No PWM pulses shorter than TMIN except during cycle-by-cycle current limit A B C D E F Nooutputdelayshown,COMP-to-RAMPoffsetnotincluded. Figure2. UCC28950SteadyState/ShutdownTimingDiagram 10 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 6.8 Typical Characteristics 7.6 640 -V mV UnderVoltageLockoutThresholds 67677.....80624 UVLO_FTH UVLO_RTH UnderVoltageLockoutHysteresis- 666610230000 UVLO_HYST UVLO- 6.4 UVLO- 590 6.2 580 -40 25 125 -40 25 125 T -Temperature-°C T -Temperature-°C J J Figure3.UVLOThresholdsvsTemperature Figure4.UVLOHysteresisvsTemperature 3.9 250 A m 3.8 - 200 peratingSupplyCurrent 33..67 I - Startup Current - APDD 150 O 100 I-DD 3.5 3.4 50 -40 25 125 -40 25 125 TJ-Temperature-°C TJ - Temperature - (cid:176)C Figure5.SupplyCurrentvsTemperature Figure6.StartupCurrentvsTemperature 5.010 5.001 5.005 ILOAD=10µA 4.999 VREF_10mA_12VDD V V n- V-VoltageReference-REF 4454....990998095500 ILOAD=1mAILOAD=20mAILOAD=10mA V-LineVoltageRegulatioREF 4444....999999995173 VREF_10mVAR_EF1_01V0DDmA_8VDD 4.980 4.989 4.975 4.987 -40 25 125 4.985-40 25 125 T -Temperature-°C T -Temperature-°C J J Figure7.VoltageReference(VDD=12V)vsTemperature Figure8.LineVoltageRegulation(I =10mA)vs LOAD Temperature Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com Typical Characteristics (continued) 38.5 95.4 95.2 38.0 % 95.0 nt-mA 37.5 Cycle- 94.8 ShortCircuitCurre 333667...050 D-MaximumDutyMAX99994444....2460 35.5 93.8 35.0 93.6 -40 25 125 -40 25 125 T -Temperature-°C T -Temperature-°C J J Figure9.ShortCircuitCurrentvsTemperature Figure10.MaximumDutyCyclevsTemperature 95.4 1079 F - Nominal Switching Frequency - kHzSW(nom) 999544...060 F - Maximum Switching Frequency - kHzSW(max) 111000531999 93.6 999 -40 25 125 -40 25 125 TJ - Temperature - (cid:176)C TJ - Temperature - (cid:176)C Figure11.NominalSwitchingFrequencyvsTemperature Figure12.MaximumSwitchingFrequencyvsTemperature 0.00 125 -0.05 120 mV -0.10 dB oltage- -0.15 plifier- 115 OFFSETv --00..2250 VIO=500mV ErrorAm 111005 ErrorAmplifier ---000...334500 VIO=3.6V VIO=2.5V AVOL-Voltage 19050 90 -0.45 -0.50 85 -40 25 125 -40 25 125 T -Temperature-°C T -Temperature-°C J J Figure13.ErrorAmplifierOffsetVoltagevsTemperature Figure14.VoltageErrorAmplifier(OpenLoopGain)vs Temperature 12 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 Typical Characteristics (continued) 26.0 0.60 V - d µA 25.5 Threshol 0.55 I-ChargeCurrent–SS 2254..05 hutdown/Restart/Reset 000...445500 S 24.0 V-SS(std)0.35 23.5 0.30 -40 25 125 -40 25 125 T -Temperature-°C T -Temperature-°C J J Figure15.I ChargeCurrentvsTemperature Figure16.Shutdown/Restart/ResetThresholdvs SS Temperature 3.715 4.692 4.690 4.688 V - SS Pullup Threshold - VSS(pu) 333...777001500 V - SS Clamp Voltage - VSS(CL) 4444....666688882064 4.678 4.676 3.695 4.674 -40 25 125 -40 25 125 TJ - Temperature - (cid:176)C TJ - Temperature - (cid:176)C Figure17.SSPull-UpThresholdvsTemperature Figure18.SSClampVoltagevsTemperature 1.996 110 -V ns V-CurrentSenseCycle-By-CycleLimitCS(lim) 11111.....999999899808426 T-CurrentSensePropagationDelay-CS(prop) 11190008741 1.984 95 -40 25 125 -40 25 125 T -Temperature-°C T -Temperature-°C J J Figure19.CurrentSenseCycle-by-CycleLimitvs Figure20.CurrentSensePropagationDelayvsTemperature Temperature Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com Typical Characteristics (continued) 17.5 17.5 Ω R Ω R – SINK_OUTF – SINK_OUTE nce 15.5 RSINK_OUTD nce 15.5 RSINK_OUTC Resista RSINK_OUTA Resista RSINK_OUTB nk 13.5 nk 13.5 Si Si uts uts p p ut 11.5 ut 11.5 O O - - RSINK 9.5 RSINK 9.5 7.5 7.5 -40 25 125 -40 25 125 T -Temperature-°C T -Temperature-°C J J Figure21.OutputsSinkResistancevsTemperature Figure22.OutputsSinkResistancevsTemperature 25 25 ΩResistance– 23 RRRSSSRRRCCC___OOOUUUTTTACF ΩResistance– 23 RRRSSSRRRCCC___OOOUUUTTTBDE Source 21 Source 21 Outputs 19 Outputs 19 -RSRC 17 -RSRC 17 15 15 -40 25 125 -40 25 125 TJ-Temperature-°C TJ-Temperature-°C Figure23.OutputsSourceResistancevsTemperature Figure24.OutputsSourceResistancevsTemperature 50 280 TCDSET2 TCDSET1 270 Delay-ns 45 TABSET1 Delay-ns 260 TABSET2 me me DeadTi 40 DeadTi 250 T-OFFTIME 35 TAFSET1 T-OFFTIME 240 TAFSET2 TBESET2 230 TBESET1 30 220 -40 25 125 -40 25 125 TJ- Temperature - °C TJ-Temperature-°C Figure25.DeadTimeDelayvsTemperature Figure26.DeadTimeDelayvsTemperature 14 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 Typical Characteristics (continued) 0.405 0.400 0.395 V M Threshold - 00..339805 DC 0.380 0.380 0.375 -40 25 125 TJ - Temperature - (cid:176)C Figure27.DCMThresholdvsTemperature 7 Detailed Description 7.1 Overview The UCC28950 device combines all the functions necessary to control a phase-shifted full bridge power stage in a 24-pin TSSOP package. The device includes two Synchronous-Rectifier (SR), gate-drive outputs as well as the outputs needed to drive all four switches in the full-bridge circuit. The dead times between the upper and lower switches in the full bridge may be set using the DELAB and DELCD inputs. Further, this dead time may be dynamically adjusted according to the load level using the ADEL pin. This allows the user to optimize the dead timefortheirparticularpowercircuitandtoachieveZVSovertheentireoperatingrange.Inasimilarmanner,the dead times between the full bridge switches and the secondary SRs may be optimized using the DELEF input. This dead time may also be dynamically adjusted according to the load, using the ADELEF input to the controller.ADCM(DiscontinuousConductionMode)optiondisablestheSRsatausersettablelightloadinorder to improve power circuit efficiency. The device enters a light-load-burst mode if the feedback loop demands a conductiontimelessthanausersettablelevel(TMIN). At higher-power levels, two or more UCC28950 devices may be easily synchronized in a Master/Slave configuration. A SS/EN input may be used to set the length of the soft start process and to turn the controller on and off. The controller may be configured for Voltage mode or Current mode control. Cycle-by-cycle current limiting is provided in Voltage mode and Peak Current mode. The switching frequency may be set over a wide rangemakingthisdevicesuitedtobothIGBTandMOSFETbaseddesigns. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com 7.2 Functional Block Diagram ADEL 14 V DD UVLO Thermal VDD 22 OUTA COMP Shutdown VDD 23 EN Reference Programmable + Generator 6 DELAB V DelayAB ON/OFF DD + 7.3VRise - 6.7VFall VREF 1 5VLDO 21 OUTB COMP 4 PWM 20 OUTC EA- 3 COMP + + EA+ 2 + Programmable 7 DELCD DelayCD LogicBlock Lower"+"Input CLK isDominant 19 OUTD RT 10 Oscillator RAMP 2.8V 13 ADELEF 0.8V Ramp RSUM 11 Summing 18 OUTE CS + CS 15 Cycle-by-Cycle I Programmable LIM 8 DELEF Synchronization DelayEF Block + CS - 2V Light-Load SoftStartandEnable 17 OUTF EfficiencyBlock with0.55VThreshold 16 24 12 9 5 SYNC GND DCM TMIN SS/EN 16 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 7.3 Feature Description 7.3.1 Start-UpProtectionLogic BeforetheUCC28950controllerwillstartup,thefollowingconditionsmustbemet: • VDDvoltageexceedsrisingUVLOthreshold7.3-Vtypical. • The5-Vreferencevoltageisavailable. • Junctiontemperatureisbelowthethermalshutdownthresholdof140°C. • Thevoltageonthesoft-startcapacitorisnotbelow0.55-Vtypical. If all those conditions are met, an internal enable signal EN is generated that initiates the soft start process. The duty cycle during the soft start is defined by the voltage at the SS pin, and cannot be lower than the duty cycle setbyTMIN,orbycycle-by-cyclecurrentlimitcircuitdependingonloadconditions. 7.3.2 VoltageReference(VREF) The accurate (±1.5%) 5-V reference voltage regulator with a short circuit protection circuit supplies internal circuitry and provides up to 20-mA external output current. Place a low ESR and ESL, preferably ceramic decoupling capacitor C in 1-µF to 2.2-µF range from this pin to GND as close to the related pins as possible REF for best performance. The only condition where the reference regulator is shut down internally is during under voltagelockout. 7.3.3 ErrorAmplifier(EA+,EA–,COMP) The error amplifier has two uncommitted inputs, EA+ and EA-, with a 3-MHz unity gain bandwidth, which allows flexibility in closing the feedback loop. The EA+ is a non-inverting input, the EA– is an inverting input and the COMP is the output of the error amplifier. The input voltage common mode range, where the parameters of the error amplifier are guaranteed, is from 0.5 V to 3.6 V. The output of the error amplifier is connected internally to the non-inverting input of the PWM comparator. The range of the error amplifier output of 0.25 V to 4.25 V far exceeds the PWM comparator input ramp-signal range, which is from 0.8 V to 2.8 V. The soft-start signal serves as an additional non-inverting input of the error amplifier. The lower of the two non-inverting inputs of the error amplifier is the dominant input and sets the duty cycle where the output signal of the error amplifier is compared withtheinternalrampattheinputsofthePWMcomparator. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com Feature Description (continued) 7.3.4 SoftStartandEnable(SS/EN) Thesoft-startpinSS/ENisamulti-functionpinusedforthefollowingoperations: • Closed loop soft start with the gradual duty cycle increase from the minimum set by TMIN up to the steady statedutycyclerequiredbytheregulatedoutputvoltage. • Settinghiccupmodeconditionsduringcycle-by-cycleovercurrentlimit. • On/offcontrolfortheconverter. During soft start, one of the voltages at the SS/EN or EA+ pins, whichever is lower (SS/EN – 0.55 V) or EA+ voltage(seeBlockDiagram),setsthereferencevoltageforaclosedfeedbackloop.BothSS/ENandEA+signals are non-inverting inputs of the error amplifier with the COMP pin being its output. Thus the soft start always goes under the closed feedback loop and the voltage at COMP pin sets the duty cycle. The duty cycle defined by the COMP pin voltage can not be shorter than TMIN pulse width set by the user. However, if the shortest duty cycle is set by the cycle-by-cycle current limit circuit, then it becomes dominant over the duty cycle defined by the COMPpinvoltageorbytheTMINblock. The soft-start duration is defined by an external capacitor C , connected between the SS/EN pin and ground, SS and the internal charge current that has a typical value of 25 µA. Pulling the soft-start pin externally below 0.55 V shuts down the controller. The release of the soft-start pin enables the controller to start, and if there is no current limit condition, the duty cycle applied to the output inductor gradually increases until it reaches the steady state duty cycle defined by the regulated output voltage of the converter. This happens when the voltage at the SS/EN pin reaches and then exceeds by 0.55 V, the voltage at the EA+ pin. Thus for the given soft-start time T ,theC valuecanbedefinedbyEquation1orEquation2: SS SS T ´25mA C = SS SS(master) (0.55+EA+) (1) T C = SS SS(slave) æ 20.6 ö 825k´Lnç ÷ è20.6 – 0.55 – EA+ø (2) For example, in Equation 1, if the soft-start time T is selected to be 10 ms, and the EA+ pin is 2.5 V, then the SS soft-startcapacitorC isequalto82nF. SS NOTE If the converter is configured in Slave Mode, place an 825-kΩ resistor from SS pin to ground. 7.3.5 Light-LoadPowerSavingFeatures The UCC28950 offers four different light-load management techniques for improving the efficiency of a power converteroverawideloadcurrentrange. 1. AdaptiveDelay, (a) ADEL, which sets and optimizes the dead-time control for the primary switches over a wide load current range. (b) ADELEF, which sets and optimizes the delay-time control between the primary side switches and the secondarysideswitches. 2. TMIN,setstheminimumpulsewidthaslongasthepartisnotincurrentlimitmode. 3. Dynamic synchronous rectifier on/off control in DCM Mode, For increased efficiency at light loads. The DCM Mode starts when the voltage at CS pin is lower than the threshold set by the user. In DCM Mode, the synchronousoutputdrivesignalsOUTEandOUTFarebroughtdownlow. 4. Burst Mode, for maximum efficiency at very light loads or no load. Burst Mode has an even number of PWM TMIN pulses followed by off time. Transition to the Burst Mode is defined by the TMIN duration set by the user. 18 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 Feature Description (continued) 7.3.6 AdaptiveDelay,(DelaybetweenOUTAandOUTB,OUTCandOUTD(DELAB,DELCD,ADEL)) The resistor R from the DELAB pin, DELAB to GND, along with the resistor divider R from CS pin to ADEL AB AHI pin and R from ADEL pin to GND sets the delay T between one of outputs OUTA or OUTB going low and A ABSET the other output going high Figure 28. The total resistance of this resistor divider should be in the range between 10kΩand20kΩ T T ABSET2 ABSET2 TCDSET2 TCDSET2 OUTA (OUTC) T T ABSET1 ABSET1 T T CDSET1 CDSET1 OUTB (OUTD) Figure28. DelayDefinitionsBetweenOUTAandOUTB,OUTCandOUTD This delay gradually increases as a function of the CS signal from T , which is measured at V = 1.8 V, to ABSET1 CS T , which is measured at the V = 0.2 V. This approach ensures there will be no shoot-through current ABSET2 CS during the high-side and low-side MOSFET switching and optimizes the delay for acheiving ZVS condition over a wide load current range. The ratio between the longest and shortest delays is set by the resistor divider R and AHI R . The max ratio is achieved by tying the CS and ADEL pins together. If ADEL is connected to GND, then the A delay is fixed, defined only by the resistor R from DELAB to GND. The delay T and T settings and AB CDSET1 CDSET2 their behaviour for outputs OUTC and OUTD are very similar to the one described for OUTA and OUTB. The difference is that resistor R connected between DELCD pin and GND sets the delay T . The ratio between CD CDSET thelongestandshortestdelaysissetbytheresistordividerR andR . AHI A ThedelaytimeT isdefinedbythefollowingEquation3. ABSET æ 5 ´R ö T =ç AB ÷ns ABSET 0.26V+CS ´K ´1.3 è ø A (3) ThesameequationisusedtodefinethedelaytimeT inanotherlegexceptR isreplacedbyR . CDSET AB CD æ 5 ´R ö T =ç CD ÷ns CDSET 0.26V+CS ´K ´1.3 è ø A (4) In these equations R and R are in kΩ and CS, the voltage at pin CS, is in volts and K is a numerical AB CD A coefficient in the range from 0 to 1. The delay time T and T are in ns, and is measured at the IC pins. ABSET CDSET These equations are empirical and they are approximated from measured data. Thus, there is no unit agreement in the equations. As an example, assume R = 15 kΩ, CS = 1 V and K = 0.5. Then the T will be AB A ABSET approximately90ns.InbothEquation3 andEquation4,K isthesameandisdefinedas: A R K = A A R +R A AHI (5) K setshowthedelayvarieswiththeCSpinvoltageasshowninFigure29andFigure30. A Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com Feature Description (continued) ItisrecommendedtostartbysettingK =0andsetT andT relativelylargeusingequationsorplotsin A ABSET CDSET this data sheet to avoid hard switching or even shoot through current. The delay between outputs A, B and C, D set by resistors R and R accordingly. Program the optimal delays at light load first. Then by changing K set AB CS A the optimal delay for the outputs A, B at maximum current. K for outputs C, D is the same as for A,D. Usually A outputsC,DalwayshaveZVSifsufficientdelayisprovided. NOTE TheallowedresistorrangeonDELABandDELCD,R andR is13kΩ to90kΩ. AB CD R and R define the portion of voltage at pin CS applied to the pin ADEL (See Figure 48). K defines how A AHI A significantly the delay time depends on CS voltage. K varies from 0, where ADEL pin is shorted to ground (R = A A 0) and the delay does not depend on CS voltage, to 1, where ADEL is tied to CS (R = 0). Setting K , R and AHI A AB R provides the ability to maintain optimal ZVS conditions of primary switches over load current because the CD voltage at CS pin includes the load current reflected to the primary side through the current sensing circuit. The plotsinFigure29andFigure30showthedelaytimesettingsasafunctionofCSvoltageandK fortwodifferent A conditions:R =R =13kΩ(Figure29)andR =R =90kΩ(Figure30). AB CD AB CD 350 2000 KA = 0 KA = 0 KA = 0.1 1800 KA = 0.1 300 KA = 0.25 KA = 0.25 KA = 0.5 KA = 0.5 KA = 0.75 1600 KA = 0.75 ns KA = 1 ns KA = 1 y - 250 y - 1400 a a el el me D 200 me D 1200 Ti Ti - ET - ET 1000 S 150 S CD CD 800 T T , T , T BSE 100 BSE 600 A A T T 400 50 200 0 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.5 1 1.5 2 CS Voltage - V CS Voltage - V G001 G001 Figure29.DelayTimeSetT andT Figure30.DelaytimesetT andT ABSET CDSET ABSET CDSET (OverCSvoltagevariationandselectedK forR and (OverCSvoltagevariationandselectedK forR and A AB A AB R equal13kΩ) R equal90kΩ) CD CD 20 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 Feature Description (continued) 7.3.7 AdaptiveDelay(DelaybetweenOUTAandOUTF,OUTBandOUTE(DELEF,ADELEF)) The resistor R from the DELEF pin to GND along with the resistor divider R from CS pin to ADELEF pin EF AEFHI and R from ADELEF pin to GND sets equal delays T and T between outputs OUTA or OUTB going AEF AFSET BESET low and related output OUTF or OUTE going low Figure 31. The total resistance of this resistor divider should be intherangebetween10kΩ and20kΩ. OUTA (OUTB) OUTD (OUTC) T AFSET1 T BESET1 OUTF (OUTE) T AFSET2 T BESET2 Figure31. DelayDefinitionsBetweenOUTAandOUTF,OUTBandOUTE These delays gradually increase as function of the CS signal from T , which is measured at V = 0.2 V, to AFSET1 CS T , which is measured at V = 1.8 V. This is opposite to the DELAB and DELCD behavior and this delay is AFSET2 CS longest (T ) when the signal at CS pin is maximized and shortest (T ) when the CS signal is AFSET2 AFSET1 minimized. This approach will reduce the synchronous rectifier MOSFET body diode conduction time over a wide load current range thus improving efficiency . The ratio between the longest and shortest delays is set by the resistor divider R and R . If CS and ADELEF are tied, the ratio is maximized. If ADELEF is connected to AEFHI AEF GND,thenthedelayisfixed,definedonlybyresistorR fromDELEFtoGND. EF ThedelaytimeT isdefinedbythefollowingEquation6.Equation6alsodefinesthedelaytimeT . AFSET BESET ææ 5´R ö ö T =çç EF ÷ns+4ns÷ AFSET ç 2.65V-CS´K ´1.32 ÷ èè ø ø EF (6) In this equation R is in kΩ, the CS, which is the voltage at pin CS, is in volts and K is a numerical gain factor EF EF of CS voltage from 0 to 1. The delay time T is in ns, and is measured at the IC pins. This equation is an AFSET empirical approximation of measured data, thus, there is no unit agreement in it. As an example, assume R = EF 15kΩ,CS=1VandK =0.5.ThentheT isgoingtobe41.7ns.K isdefinedas: EF AFSET EF R K = AEF EF R +R AEF AEF(hi) (7) R and R define the portion of voltage at pin CS applied to the pin ADELEF (See Figure 48). K defines AEF AEFHI EF how significantly the delay time depends on CS voltage. K varies from 0, where ADELEF pin is shorted to EF ground(R =0)andthedelaydoesnotdependonCSvoltage,to1,whereADELEFistiedtoCS(R =0). AEF AEFHI NOTE TheallowedresistorrangeonDELEF,R is13kΩto90kΩ. EF Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com Feature Description (continued) The plots in Figure 32 and Figure 33 show delay time settings as function of CS voltage and K for two different EF conditions:R =13kΩ(Figure32)andR =90kΩ(Figure33) EF EF 350 2000 1800 300 1600 y - ns 250 KA = 0.00 y - ns 1400 KA = 0.0 me Dela 200 KKAA == 00..2550 me Dela 1200 KKAA == 00..45 T, T - TiAFSETBESET 110500 KKKAAA === 001...790500 T, T - TiAFSETBESET 1068000000 KKKAAA === 001...890 400 50 200 5 5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 CS Voltage - V CS Voltage - V Figure32.DelayTimeT andT Figure33.DelayTimeT andT AFSET BESET AFSET BESET (OverCSVoltageandSelectedK forR equal13kΩ) (OverCSVoltageandSelectedK forR equal90kΩ) EF EF EF EF 22 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 Feature Description (continued) 7.3.8 MinimumPulse(TMIN) The resistor R from the TMIN pin to GND sets a fixed minimum pulse width. This pulse is applied to the TMIN transformer and enables ZVS at light load. If the output PWM pulse demanded by the feedback loop is shorter than TMIN, then the controller proceeds to burst mode operation where an even number of TMIN pulses are followed by the off time dictated by the feedback loop. The proper selection of the TMIN duration is dictated by the time it takes to raise sufficient magnetizing current in the power transformer to maintain ZVS. The TMIN pulse is measured from the rising edge of OUTA to the falling edge of OUTD – or from the rising edge of OUTB tothefallingedgeofOUTC.TheminimumpulseTMINisthendefinedbyEquation8. TMIN=(5.92´R )ns TMIN (8) Where TMIN is in ns and R is in kΩ The pulse width measured at the transformer will be modified (usually TMIN increased) by various propagation and response time delays in the power circuit. Because of the propagation andresponsetimedelaysinthepowercircuit,selectingthecorrectTMINsettingwillbeaniterativeprocess. NOTE TheminimumallowedresistoronTMIN,R is10kΩ. TMIN TherelatedplotisshowninFigure34. 800 700 600 500 ns) N ( 400 MI T 300 200 100 0 0 20 40 60 80 100 120 140 RTMIN (k:) D001 Figure34. MinimumTimeTMIN OverSettingResistorR TMIN ThevalueofminimumdutycycleDMINisdeterminedbyEquation9. DMIN=(TMIN´F ´10-4)% SW(osc) (9) Here,F isoscillatorfrequencyinkHz,TMINistheminimumpulseinnsandDMINisinpercent. SW(osc) 7.3.9 BurstMode If the converter is commanding a duty cycle lower than TMIN, then the controller will go into Burst Mode. The controller will always deliver an even number of Power cycles to the Power transformer. The controller always stops its bursts with an OUTB and an OUTC power delivery cycle. If the controller is still demanding a duty cycle less than TMIN, then the controller goes into shut down mode. Then it waits until the converter is demanding a duty cycle equal or higher than TMIN before the controller puts out TMIN or a PWM duty cycle as dictated by COMPvoltagepin. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com Feature Description (continued) 7.3.10 SwitchingFrequencySetting Connecting an external resistor R between the RT pin and VREF pins sets the fixed frequency operation and T configures the controller as a master providing synchronization output pulses at SYNC pin with 0.5 duty cycle and frequency equal to the internal oscillator. To set the converter in slave mode, connect the external resistor R between the RT pin to GND and place an 825-kΩ resistor from the SS pin to GND in parallel with the SS_EN T capacitor. This configures the controller as a slave. The slave controller operates with 90° phase shift relative to themasterconverteriftheirSYNCpinsaretiedtogether.Theswitchingfrequencyoftheconverterisequaltothe frequency of output pulses. The following Equation 10 defines the nominal switching frequency of the converter configured as a master (resistor R between the RT pin and VREF). On the UCC28950 there is an internal clock T oscillatorfrequencywhichistwiceasthatofthecontroller'soutputfrequency. æ ö ç ÷ ç 2.5´103 ÷ F = kHz SW(nom) çæ R kWö÷ çç T +1´ ÷÷ ç ÷ èèV -2.5V V øø REF (10) In this equation R is in kΩ, VREF is in volts and F is in kHz. This is also an empirical approximation and T SW(nom) thus, there is no unit agreement. Assume for example, VREF = 5 V, R = 65 kΩ. Then the switching frequency T F isgoingtobe92.6kHz. SW(nom) Equation 11 defines the nominal switching frequency of converter if the converter configured as a slave and the resistorR isconnectedbetweentheRTpinandGND. T æ ö ç ÷ ç 2.5´103 ÷ F = kHz SW(nom) çæ R kWö÷ çç T +1´ ÷÷ èè2.5V V øø (11) In this equation the R is in kΩ, and F is in kHz. Notice that for VREF = 5 V, Equation 10 and Equation 11 T SW(nom) yieldthesameresults. The plot in Figure 35 shows how F depends on the resistor R value when the VREF = 5 V. As it is seen SW(nom) T from Equation 10 and Equation 11, the switching frequency F is set to the same value for either master or SW(nom) slaveconfigurationprovidedthesameresistorvalueR isused. T 1000 900 z H 800 k - cy 700 n e u q 600 e Fr ng 500 hi witc 400 S - 300 m) W(no 200 FS 100 0 5 15 25 35 45 55 65 75 85 95 105115125 R -Resistor- kΩ T Figure35. ConverterSwitchingFrequencyF OverresistorR Value SW(nom) T 24 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 Feature Description (continued) 7.3.11 SlopeCompensation(R ) SUM Slope compensation is needed to prevent a sub-harmonic oscillation in a controller operating in peak current mode(PCM)controlorduringcycle-by-cyclecurrentlimitatdutycyclesabove50%(somepublicationssuggestit mayhappenatD<50%).SlopecompensationintheUCC28950addsanadditionalrampsignaltotheCSsignal andisapplied: • TothePWMcomparatorinthecaseofpeakcurrentmodecontrol. • Totheinputofthecycle-by-cyclecomparator. At low duty cycles and light loads the slope compensation ramp reduces the noise sensitivity of Peak Current Modecontrol. Placing a resistor from the R pin to ground allows the controller to operate in PCM control. Connecting a SUM resistor from R to VREF switches the controller to voltage mode control (VMC) with the internal PWM ramp. SUM In VMC the resistor at R provides CS signal slope compensation for operation in cycle-by-cycle current limit. SUM That is, in VMC, the slope compensation is applied only to the cycle-by-cycle comparator while in PCM the slope compensation is applied to both the PWM and cycle-by-cycle current limit comparators. The operation logic of theslopecompensationcircuitisshowninFigure36. COMP 4 + + Oscillator 0.85 V VREF VCM CLK PCM Ramp VMC Generator RAMP RSUM Cycle-by-Cycle ILIM Two Direction Ramp CS_SLOPECOMP 11 Current Sense Summing + + CS 15 2 V - Mode Select GND PCM 7 GND Figure36. TheOperationLogicofSlopeCompensationCircuit Too much slope compensation reduces the benefits of PCM control. In the case of cycle-by-cycle current limit, the average current limit becomes lower and this might reduce the start-up capability into large output capacitances. The optimum compensation ramp varies, depending on duty cycle, L and L . A good starting point in OUT MAG selectingtheamountofslopecompensationistosettheslopecompensationramptobehalftheinductorcurrent ramp downslope (inductor current ramp during the off time). The inductor current ramp downslope – as seen at theCSpininput,andneglectingtheeffectsofanyfilteringattheCSpin,willbe: V R m = OUT S 0 L a1´ CT OUT RAT (12) Where, V is the converter’s output voltage of the converter, L is the output inductor value, a1 is the OUT OUT transformerturnsratio(Np/Ns),CT isthecurrenttransformerratio(Ip/Is,typically100:1).SelectionofL ,a1 RAT OUT and CT are described elsewhere in this document. The total slope compensation is 0.5 m . Part of this ramp RAT 0 will be due to magnetizing current in the transformer, the rest is added by an appropriately chosen resistor from RSUMtoground. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com Feature Description (continued) The slope of the additional ramp, me, added to the CS signal by placing a resistor from RSUM to ground is definedbyEquation13. æ 2.5 ö V me =ç ÷ 0.5´R ms è SUM ø (13) If the resistor from the RSUM pin is connected to the VREF pin, then the controller operates in voltage mode control, still having the slope compensation ramp added to the CS signal used for cycle-by-cycle current limit. In thiscasetheslopeisdefinedbyEquation14. æ(V -2.5V)ö V me =ç REF ÷ 0.5´R ms è ø SUM (14) In Equation 13and Equation 14, VREF is in volts, R is in kΩ and me is in V/μs. These are empirically derived SUM equations without units agreement. As an example, substituting VREF = 5V and R = 40 kΩ, yields the result SUM 0.125 V/μs. The related plot of me as a function of R is shown in Figure 37, Because VREF = 5V, the plots SUM generatedfromEquation13andEquation14coincide. 0.50 0.45 0.40 0.35 s 0.30 µ V/ - 0.25 e p Slo 0.20 0.15 0.10 0.05 0 5 20 40 60 80 100 120 140 160 180 200 R -Resistor-kΩ sum Figure37. SlopeoftheAddedRampOverResistorR SUM NOTE TherecommendedresistorrangeforR is10kΩto1MΩ. SUM 26 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 Feature Description (continued) 7.3.12 DynamicSRON/OFFControl(DCMMode) The voltage at the DCM pin provided by the resistor divider R between VREF pin and DCM, and R from DCMHI DCM DCMpintoGND,setsthepercentageof2-VcurrentlimitthresholdfortheCurrentSensepin,(CS).IftheCSpin voltage falls below the DCM pin threshold voltage, then the controller initiates the light load power saving mode, and shuts down the synchronous rectifiers, OUTE and OUTF. If the CS pin voltage is higher than the DCM pin threshold voltage, then the controller runs in CCM mode. Connecting the DCM pin to VREF makes the controller run in DCM mode and shuts both Outputs OUTE and OUTF. Shorting the DCM pin to GND disables the DCM featureandthecontrollerrunsinCCMmodeunderallconditions. VREF 1 20mA R DCM(hi) R = 77 kW PWM CS DCM_COMP 15 2-Cycle + Counter R = 77 kW DCM 0 = DCM 12 1 = CCM R C = 6.5 pF DCM C = 6.5 pF Other Blocks Figure38. DCMFunctionalBlock Moving into DCM Mode 0.8 VS(max) 0.6 VS(min) % e - ycl 0.4 C y ut D TMIN Setting 0.2 Burst Mode Area 0 0 1 2 3 4 5 6 7 8 9 10 Load Current - A Figure39. DutyCycleChangeOverLoadCurrentChange Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com Feature Description (continued) Anominal20-µAswitchedcurrentsourceisusedtocreatehysteresis.Thecurrentsourceisactiveonlywhenthe system is in DCM Mode. Otherwise, it is inactive and does not affect the node voltage. Therefore, when in the DCM region, the DCM threshold is the voltage divider plus ΔV explained in Equation 15. When in the CCM region, the threshold is the voltage set by the resistor divider. When the CS pin reaches the threshold set on the DCM pin, the system waits to see two consecutive falling edge PWM cycles before switching from CCM to DCM and vice-versa. The magnitude of the hysteresis is a function of the external resistor divider impedance. The hysteresiscanbecalculatedusingthefollowingEquation15: R ´R DV =2´10-5 DCMHI DCM R +R DCMHI DCM (15) PWM DCMThreshold +Hysteresis CS E F Figure40. MovingfromDCMtoCCMMode PWM DCMThreshold +Hysteresis CS E F Figure41. MovingfromCCMtoDCMMode DCM must be used in order to prevent reverse current in the output inductor which could cause the synchronous FETStofail. The controller must switch to DCM mode at a level where the output inductor current is positive. If the output inductor current is negative when the controller switches to DCM mode then the synchronous FETs will see a largeV spikeandmayfail. DS 28 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 Feature Description (continued) 7.3.13 CurrentSensing(CS) The signal from the current sense pin is used for cycle-by-cycle current limit, peak-current mode control, light- load efficiency management and setting the delay time for outputs OUTA, OUTB, OUTC, OUTD and delay time for outputs OUTE, OUTF. Connect the current sense resistor R between CS and GND. Depending on layout, CS to prevent a potential electrical noise interference, it is recommended to put a small R-C filter between the R CS resistorandtheCSpin. 7.3.14 Cycle-by-CycleCurrentLimitCurrentProtectionandHiccupMode The cycle-by-cycle current limit provides peak current limiting on the primary side of the converter when the load currentexceedsitspredeterminedthreshold.Forpeakcurrentmodecontrol,acertainleadingedgeblankingtime is needed to prevent the controller from false tripping due to switching noise. An internal 30-ns filter at the CS input is provided. The total propagation delay TCS from CS pin to outputs is 100 ns. An external RC filter is still needed if the power stage requires more blanking time. The 2.0-V ±3% cycle-by-cycle current limit threshold is optimized for efficient current transformer based sensing. The duration when a converter operates at cycle-by- cycle current limit depends on the value of soft-start capacitor and how severe the overcurrent condition is. This isachievedbytheinternaldischargecurrentI Equation16andEquation17atSSpin. DS I =(-25´(1-D)+5)mA DS(master) (16) I =(-25´(1-D))mA DS(slave) (17) The soft-start capacitor value also determines the so called hiccup mode off-time duration. The behavior of the converter during different modes of operation, along with related soft start capacitor charge/discharge currents areshowninFigure42. Cycle-by-CycleI LIM SSPin(V) Normal SoftStart Operation . OFFTimeBeforeRestart SSClampVoltage 4.65 25mA 3.70 SoftRestart PullUpThreshold 3.60 FastPullUp by1kWSwitch IDS=(-25x(1-D)+5)mA I =2.5mA HCC OutputEnable I =25mA 0.55 SS Threshold 0.00 OutputPulses(D) Figure42. TimingDiagramofSoft-StartVoltageV SS Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com Feature Description (continued) The largest discharge current of 20 µA is when the duty cycle is close to zero. This current sets the shortest operationtimeduringthecycle-by-cyclecurrentlimitwhichisdefinedas: C ´(4.65V-3.7V) T = SS CL(on_master) 20mA (18) C ´(4.65V-3.7V) T = SS CL(on_slave) 25mA (19) Thus,ifthesoft-startcapacitorC =100nFisselected,thentheT timewillbe5ms. SS CL(on) To calculate the hiccup off time T before the restart, the following Equation 20 or Equation 21 needs to be CL(off) used: C ´(3.6V -0.55V) T = SS CL(off_master) 2.5mA (20) C ´(3.6V-0.55V) T = SS CL(off_slave) 4.9mA (21) With the same soft start capacitor value 100 nF, the off time before the restart is going to be 122 ms. Notice, that if the overcurrent condition happens before the soft start capacitor voltage reaches the 3.7-V threshold during startup,thecontrollerlimitsthecurrentbutthesoftstartcapacitorcontinuestobecharged.Assoonasthe3.7-V threshold is reached, the soft-start voltage is quickly pulled up to the 4.65-V threshold by an internal 1-kΩ R DS(on) switch and the cycle-by-cycle current limit duration timing starts by discharging the soft start capacitor. Depending on specific design requirements, the user can override this default behavior by applying external charge or discharge currents to the soft start capacitor. The whole cycle-by-cycle current limit and hiccup operation is shown in Figure 42. In this example the cycle-by-cycle current limit lasts about 5 ms followed by 122 msofofftime. Similarly to the overcurrent condition, the hiccup mode with the restart can be overridden by the user if a pullup resistor is connected between the SS and VREF pins. If the pullup current provided by the resistor exceeds 2.5 µA,thenthecontrollerremainsinthelatchoffmode.Inthiscase,anexternalsoft-startcapacitorvalueshouldbe calculated with the additional pull-up current taken into account. The latch off mode can be reset externally if the soft-startcapacitorisforciblydischargedbelow0.55VortheV voltageisloweredbelowtheUVLOthreshold. DD 30 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 Feature Description (continued) 7.3.15 Synchronization(SYNC) The UCC28950 allows flexible configuration of converters operating in synchronized mode by connecting all SYNC pins together and by configuration of the controllers as master and/or slaves. The controller configured as master (resistor between RT and VREF) provides synchronization pulses at the SYNC pin with the frequency equal to 2X the converter frequency F and 0.5 duty cycle. The controller configured as a slave (resistor SW(nom) between RT and GND and 825-kΩ resistor between SS_EN pin to GND) does not generate the synchronization pulses. The Slave controller synchronizes its own clock to the falling edge of the synchronization signal thus operating90° phaseshiftedversusthemasterconverter’sfrequencyF . SW(nom) The output inductor in a full bridge converter sees a switching frequency which is twice that seen by the transformer. In the case of the UCC28950 this means that the output inductor operates at 2 x F . This SW(nom) means that the 90° phase shift between master and slave controllers gives a 180° phase shift between the currents in the output inductors and hence maximum ripple cancellation. For more information about synchronizing more than two UCC28950 devices, see Synchronizing Three or More UCC28950 Phase-Shifted, Full-BridgeControllers,SLUA609. If the synchronization feature is not used then the SYNC pin may be left floating, but connecting the SYNC pin to GNDviaa10-kΩresistorwillreducenoisepickupandswitchingfrequencyjitter. • If any converter is configured as a slave, the SYNC frequency must be greater than or equal to 1.8 times the converterfrequency. • Slaveconverterdoesnotstartuntilatleastonesynchronizationpulsehasbeenreceived. • If any or all converters are configured as slaves, then each converter operates at its own frequency without synchronization after receiving at least one synchronization pulse. Thus, If there is an interruption of synchronization pulses at the slave converter, then the controller uses its own internal clock pulses to maintainoperationbasedontheR valuethatisconnectedtoGNDintheslaveconverter. T • Inmastermode,SYNCpulsesstartafterSSpinpassesitsenablethresholdwhichis0.55V. • SlavestartsgeneratingSS/ENvoltageeventhoughsynchronizationpulseshavenotbeenreceived. • It is recommended that the SS on the master controller starts before the SS on the slave controller; therefore SS/EN pin on master converter must reach its enable threshold voltage before SS/EN on the slave converter starts for proper operation. On the same note, it’s recommended that T resistors on both master and slave MIN aresetatthesamevalue. CLK SYNC_OUT A B Figure43. SYNC_OUT(MasterMode)TimingDiagram SYNC_IN CLK A B Figure44. SYNC_IN(SlaveMode)TimingDiagram Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com Feature Description (continued) 7.3.16 Outputs(OUTA,OUTB,OUTC,OUTD,OUTE,OUTF) • AllMOSFETcontroloutputshave0.2-Adrivecapability. • The control outputs are configured as P-MOS and N-MOS totem poles with typical R 20 Ω and 10 Ω DS(on) accordingly. • Thecontroloutputsarecapableofcharging100-pFcapacitorwithin12nsanddischargewithin8ns. • TheamplitudeofoutputcontrolpulsesisequaltoV . DD • ControloutputsaredesignedtobeusedwithexternalgateMOSFET/IGBTdrivers. • Thedesignisoptimizedtopreventthelatchupofoutputsandverifiedbyextensivetests. The UCC28950 device has outputs OUTA, OUTB driving the active leg, initiating the duty cycle leg of power MOSFETs in a phase-shifted full bridge power stage, and outputs OUTC, OUTD driving the passive leg, completing the duty cycle leg, as it is shown in the typical timing diagram in Figure 46. Outputs OUTE and OUTF are optimized to drive the synchronous rectifier MOSFETs (Figure 48). These outputs have 200-mA peak-current capabilities and are designed to drive relatively small capacitive loads like inputs of external MOSFET or IGBT drivers. Recommended load capacitance should not exceed 100 pF. The amplitude of the output signal is equal totheV voltage. DD 7.3.17 SupplyVoltage(VDD) Connect this pin to a bias supply in the range from 8 V to 17 V. Place high quality, low ESR and ESL, at least 1- µF ceramic bypass capacitor C from this pin to GND. It is recommended to use a 10-Ω resistor in series from VDD thebiassupplytotheVDDpintoformanRCfilterwiththeC capacitor. VDD 7.3.18 Ground(GND) All signals are referenced to this node. It is recommended to have a separate quiet analog plane connected in one place to the power plane. The analog plane connects the components related to the pins VREF, EA+, EA-, COMP, SS/EN, DELAB, DELCD, DELEF, TMIN, RT, RSUM. The power plane connects the components related to the pins DCM, ADELEF, ADEL, CS, SYNC, OUTF, OUTE, OUTD, OUTC, OUTB, OUTA, and VDD. An exampleoflayoutandgroundplanesconnectionisshowninFigure45. 32 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 Feature Description (continued) UCC28950 C C REF VDD R1 R2 1 VREF GND 24 2 EA+ VDD 23 VDD C1 R3 3 EA- OUTA 22 A R4 R5 V SENSE 4 COMP OUTB 21 B C3 R6 C2 C 5 SS/EN OUTC 20 C SS ENABLE R 6 DELAB OUTD 19 D AB Power Plane R 7 DELCD OUTE 18 E CD Analog Plane R 8 DELEF OUTF 17 F EF R 9 TMIN SYNC 16 SYNC T(min) R 10 RT CS 15 T R R A(hi) SUM 11 RSUM ADEL 14 R A R DCM(hi) VREF 12 DCM ADELEF 13 R AEF(hi) CurrentSense R AEF R7 R R CS DCM Figure45. LayoutRecommendationforAnalogandPowerPlanes Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com 7.4 Device Functional Modes TheUCC28950hasanumberofoperationalmodes.ThesemodesaredescribedindetailinFeatureDescription. • Current mode(1). The UCC28950 device will operate in current mode control if the RSUM pin is connected to GNDthrougharesistor(R ).Theresistorsetstheamountofslopecompensation. SUM • Voltage mode(1). The UCC28950 device will operate in voltage mode control if the RSUM pin is connected to VREF through a resistor (R ). The resistor value is chosen to give the correct amount of slope SUM compensationforoperationincurrentlimitmode(cycle-by-cyclecurrentlimit). • DCM mode. The UCC28950 device enters DCM mode if the signal at the CS pin falls below the level set by the resistor at the DCM pin. The SR drives (OUTE and OUTF) are turned off and secondary rectification is throughthebodydiodesoftheSRs. • Burst mode. The UCC28950 device enters burst mode if the pulse width demanded by the feedback signal fallsbelowthewidthsetbytheresistorattheTMINpin. • Master mode. This is the default operation mode of the UCC28950 device and is the mode used if there is only one UCC28950 device in the system. Connect the timing resistor (R ) from the RT pin to VREF. In a T systemwithmorethanoneUCC28950,onewillbeconfiguredasthemasterandtheothersasslaves(1). • Slave mode. The slave controller will operate with a 90° phase shift relative to the Master (providing their SYNC pins are tied together). Connect the timing resistor (R ) from the RT pin to GND and connect an 825 T kΩresistorfromtheSS/ENpintoGND(1). • Synchronized mode. If a UC28950 is configured as a slave then its SYNC pin is used as an input. The slave will synchronize its internal oscillator at 90° to the signal at its SYNC pin. App note slua609 discusses how multipleSlavecontrollersmaybesynchronizedtoasinglemasteroscillator. • Hiccup mode. This mode provides overload protection to the power circuit. The UCC28950 device stops switching after a certain time in current limit. It starts again (soft start) after a delay time. The user can control thetimespentincurrentlimitbeforeswitchingisstoppedandthedelaytimebeforethesoftstarthappens. • Current-limit mode. The UCC28950 device will provide cycle-by-cycle current limiting if the signal at the CS pinreaches2V. • Latch-off mode. Connect a resistor between the SS pin and VREF. The UCC28950 will then latch off if the controllerentersCurrentLimitmode. (1) (1) Currentmodecontrolandvoltagemodecontrolaremutuallyexclusiveasaremasterandslavemodes. 34 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The high efficiency of a phase-shifted full-bridge DC/DC converter using the UCC28950 is achieved by using synchronousrectification,acontrolalgorithmprovidingZVSconditionovertheentireloadcurrentrange,accurate adaptive timing of the control signals between primary and secondary FETs and special operating modes at light load. A simplified electrical diagram of this converter is shown in Figure 48. The controller device is located on the secondary side of converter, although it could be located on primary side as well. The location on secondary sideallowseasypowersystemlevelcommunicationandbetterhandlingofsometransientconditionsthatrequire fast direct control of the synchronous rectifier MOSFETs. The power stage includes primary side MOSFETs, QA, QB, QC, QD and secondary side synchronous rectifier MOSFETs, QE and QF. For example, for the 12-V output converters in server power supplies use of the center-tapped rectifier scheme with L-C output filter is a popular choice. To maintain high efficiency at different output power conditions, the converter operates in synchronous rectification mode at mid and high output power levels, transitioning to diode rectifier mode at light load and then into burst mode as the output power becomes even lower. All these transitions are based on current sensing on theprimarysideusingacurrentsensetransformerinthisspecificcase. The major waveforms of the phase-shifted converter during normal operation are shown in Figure 46. The upper six waveforms in Figure 46 show the output drive signals of the controller. In normal mode, the outputs OUTE and OUTF overlap during the part of the switching cycle when both rectifier MOSFETs are conducting and the windings of the power transformer are shorted. Current, I , is the current flowing through the primary winding of PR the power transformer. The bottom four waveforms show the drain-source voltages of rectifier MOSFETs, V DS_QE andV ,thevoltageattheoutputinductor,VL ,andthecurrentthroughtheoutputinductor,IL .Proper DS_QF OUT OUT timing between the primary switches and synchronous rectifier MOSFETs is critical to achieve highest efficiency and reliable operation in this mode. The controller device adjusts the turn OFF timing of the rectifier MOSFETs as a function of load current to ensure minimum conduction time and reverse recovery losses of their internal bodydiodes. ZVS is an important feature of relatively high input voltage converters in reducing switching losses associated with the internal parasitic capacitances of power switches and transformers. The controller ensures ZVS conditions over the entire load current range by adjusting the delay time between the primary MOSFETs switching in the same leg in accordance to the load variation. The controller also limits the minimum ON-time pulse applied to the power transformer at light load, allowing the storage of sufficient energy in the inductive componentsofthepowerstagefortheZVStransition. As the load current reduces from full load down to the no-load condition, the controller selects the most efficient power saving mode by moving from the normal operation mode to the discontinuous-current diode-rectification mode and, eventually, at very light-load and at no-load condition, to the burst mode. These modes and related outputsignals,OUTE,OUTF,drivingtherectifierMOSFETs,areshowninFigure47. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com Application Information (continued) TABSET2 TSW(nom) OUTA TABSET1 TSW(osc) TCDSET2 OUTB OUTC TCDSET1 OUTD IPR VOUTx(1-D) /D VLOUT VOUT ILOUT IOUT Figure46. MajorWaveformsofPhase-ShiftedConverter 36 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 Application Information (continued) OUTE (CCMMode) OUTF (CCMMode) OUTEandOUTFaredisabledifV <V OUTE CS DCM OUTEandOUTFaredisabledifV <V OUTF CS DCM BurstModeatlightloadwithT maintainingZVS MIN (Thetimescaleisdifferentversusabovediagram) Transformer Winding Magnetizing Current Figure47. MajorWaveformsDuringTransitionsBetweenDifferentOperatingModes It is necessary to prevent the reverse current flow through the synchronous rectifier MOSFETs and output inductor at light load, during parallel operation and at some transient conditions. Such reverse current results in circulating of some extra energy between the input voltage source and the load and, therefore, causes increased losses and reduced efficiency. Another negative effect of such reverse current is the loss of ZVS condition. The suggested control algorithm prevents reverse current flow, still maintaining most of the benefits of synchronous rectification by switching off the drive signals of rectifier MOSFETs in a predetermined way. At some pre- determined load current threshold, the controller disables outputs OUTE and OUTF by bringing them down to zero. Synchronous rectification using MOSFETs requires some electrical energy to drive the MOSFETs. There is a condition below some light-load threshold when the MOSFET drive related losses exceed the saving provided by the synchronous rectification. At such light load, it is best to disable the drive circuit and use the internal body diodes of rectifier MOSFETs, or external diodes in parallel with the MOSFETs, for more efficient rectification. In most practical cases, the drive circuit needs to be disabled close to DCM mode. This mode of operation is called discontinuous-currentdiode-rectificationmode. At very light-load and no-load condition, the duty cycle, demanded by the closed-feedback-loop control circuit for output voltage regulation, can be very low. This could lead to the loss of ZVS condition and increased switching losses. To avoid the loss of ZVS, the control circuit limits the minimum ON-time pulse applied to the power transformerusingresistorfromTMINpintoGND.Therefore,theonlywaytomaintainregulationatverylightload and at no-load condition is to skip some pulses. The controller skips pulses in a controllable manner to avoid saturation of the power transformer. Such operation is called burst mode. In Burst Mode there are always an even number of pulses applied to the power transformer before the skipping off time. Thus, the flux in the core of thepowertransformeralwaysstartsfromthesamepointduringthestartofeveryburstofpulses. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com 8.2 Typical Application A typical application for the UCC28950 device is a controller for a phase-shifted full-bridge converter that convertsa390-V inputtoaregulated12-Voutputusingsynchronousrectifierstoachievehighefficiency. DC + CT VIN CIN R1 CREF R2 VREF UCC28950 VBIAS - 1 VREF GND 24 CVDD VDD RLF2 2 EA+ VDD 23 R3 C1 3 EA- OUTA 22 A VDD VDD VSENSE R6 R4 C3 C2 R5 4 COMP OUTB 21 B A QA DB T1 QC C CSS 5 SS/EN OUTC 20 C LS ENABLE RAB 6 DELAB OUTD 19 D DC RCD 7 DELCD OUTE 18 E VDD VDD REF 8 DELEF OUTF 17 F B QB LOUT QD D RTMIN 9 TMIN SYNC 16 SYNC RT VOUT VREF RSUM 1101 RRSTUM ADCESL 1154 RAHI VREF UCC27324 UCC27324 + VREF RDCMHI 12 DCM ADELEF 13 E QE QF F COUT RAEFHI - R7 DA RCS RDCM RLF1 CLF RAEF RA VSENSE Figure48. UCC28950TypicalApplication 8.2.1 DesignRequirements Table1liststherequirementsforthisapplication. Table1.UCC28950TypicalApplicationDesignRequirements PARAMETER TESTCONDITIONS MIN TYP MAX UNIT INPUTCHARACTERISTICS V DCinputvoltagerange 370 390 410 V IN I Maximuminputcurrent V =370V to410V 2 A IN(max) IN DC DC OUTPUTCHARACTERISTICS V Outputvoltage V =370V to410V 11.4 12 12.6 V OUT IN DC DC I Outputcurrent V =370V to410V 50 A OUT IN DC DC Outputvoltagetransient 90%loadstep 600 mV P Continuousoutputpower V =370V to410V 600 W OUT IN DC DC Loadregulation V =370V to410V ,I =5Ato50A 140 mV IN DC DC OUT Lineregulation V =370V to410V ,I =5Ato50A 140 mV IN DC DC OUT Outputripplevoltage V =370V to410V ,I =5Ato50A 200 mV IN DC DC OUT SYSTEM F SwitchingFrequency 100 kHz SW Full-loadefficiency V =370V to410V ,P =500W 93% 94% IN DC DC OUT 38 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 8.2.2 DetailedDesignProcedure In high-power server applications to meet high-efficiency and green standards some power-supply designers have found it easier to use a phase-shifted, full-bridge converter. This is because the phase-shifted, full-bridge converter can obtain zero-voltage switching on the primary side of the converter, reducing switching losses, and EMIandincreasingoverallefficiency. This is a review of the design of a 600-W, phase-shifted, full-bridge converter for one of these power systems using TI's UCC28950 device, which is based on typical values. In a production design, the values may need to be modified for worst-case conditions. TI has provided a MathCAD Design Tool and an Excel Design Tool to support the system designer. Both tools can be accessed in the Tools and Software tab of the UCC28950 productfolderonTI.com,orcanbedownloadedthroughthefollowinglinks:MathCADDesignTool,ExcelDesign Tool. NOTE F refers to the switching frequency applied to the power transformer. The output SW inductorexperiencesaswitchingfrequencywhichis2xF . SW 8.2.2.1 PowerLossBudget Tomeettheefficiencygoalapowerlossbudgetneedstobeset. æ1-hö P =P ´ » 45.2W BUDGET OUT ç ÷ è h ø (22) 8.2.2.2 PreliminaryTransformerCalculations(T1) Transformerturnsratio(a1): N a1= P N S (23) EstimatedFETvoltagedrop(V ): RDSON V =0.3V RDSON (24) Select transformer turns based on 70% duty cycle (D ) at minimum specified input voltage. This will give some MAX roomfordropoutifaPFCfrontendisused. N a1= P N S (25) (V -2´V )´D a1= INMIN RDSON MAX »21 V +V OUT RDSON (26) Turnsratioroundedtothenearestwholeturn. a1=21 (27) Calculatedtypicaldutycycle(D )basedonaverageinputvoltage. TYP (V +V )´a1 D = OUT RDSON »0.66 TYP (V -2´V ) IN RDSON (28) Outputinductorpeak-to-peakripplecurrentissetto20%oftheoutputcurrent. P ´0.2 DI = OUT =10A LOUT V OUT (29) Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com Care must be taken in selecting the correct amount of magnetizing inductance (L ). The following equations MAG calculate the minimum magnetizing inductance of the primary of the transformer (T1) to ensure the converter operates in current-mode control. As L reduces, the increasing magnetizing current becomes an increasing MAG proportion of the signal at the CS pin. If the magnetizing current increases enough it can swamp out the current sense signal across R and the converter will operate increasingly as if it were in voltage mode control rather CS thancurrentmode. V ´(1-D ) L ³ IN TYP »2.78mH MAG DI ´0.5 LOUT ´2´F a1 SW (30) Figure 49 shows T1 primary current (I ) and synchronous rectifiers QE (I ) and QF (I ) currents with PRIMARY QE QF respect to the synchronous rectifier gate drive currents. Note that I and I are the same as the secondary QE QF windingcurrentsofT1.VariableDisthedutycycleoftheconverter. IPP IPRIMARY IMP2 IMP2»IPP-DILOUT/(2´a1) IMP 0A D On QEg Off On QFg Off IQE 0A IQF IPS IMS2 IMS IMS2»IPS-DILOUT/2 0A DILOUT/2 Figure49. T1PrimaryandQEandQFFETCurrents 40 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 CalculateT1secondaryRMScurrent(I ): SRMS P DI I = OUT + LOUT »55A PS V 2 OUT (31) P DI I = OUT - LOUT » 45A MS V 2 OUT (32) ΔI I =I - LOUT »50A MS2 PS 2 (33) SecondaryRMScurrent(I )whenenergyisbeingdeliveredtothesecondary: SRMS1 æD öé (I -I )2ù I = MAX êI ´I + PS MS ú »29.6A SRMS1 ç 2 ÷ PS MS 3 è øê ú ë û (34) Secondary RMS current (I ) when current is circulating through the transformer when QE and QF are both SRMS2 on. æ1-D öé (I -I )2ù I = MAX êI ´I + PS MS2 ú »20.3A SRMS2 ç 2 ÷ PS MS2 3 è øê ú ë û (35) Secondary RMS current (I ) caused by the negative current in the opposing winding during freewheeling SRMS3 period,pleaserefertoFigure49. DI æ1-D ö I = LOUT MAX »1.1A ç ÷ SRMS3 2 è 2´3 ø (36) TotalsecondaryRMScurrent(I ): SRMS I = I 2 +I 2 +I 2 »36.0A SRMS SRMS1 SRMS2 SRMS3 (37) CalculateT1PrimaryRMSCurrent(I ): PRMS V ´D DI = INMIN MAX »0.47A LMAG L ´2´F MAG SW (38) æ P DI ö 1 I =ç OUT + LOUT ÷ +DI »3.3A PP V ´h 2 a1 LMAG è OUT ø (39) æ P DI ö 1 I =ç OUT - LOUT ÷ +DI »2.8A MP V ´h 2 a1 LMAG è OUT ø (40) IPRMS1= (DMAX)éêIPP´IMP +(IPP -IMP)2ùú »2.5A ê 3 ú ë û (41) æDI ö 1 I =I - LOUT »3.0A ç ÷ MP2 PP è 2 øa1 (42) Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com T1PrimaryRMS(I )currentwhenenergyisbeingdeliveredtothesecondary. PRMS1 IPRMS1= (DMAX)éêIPP´IMP +(IPP -IMP)2ùú »2.5A ê 3 ú ë û (43) T1PrimaryRMS(I )currentwhentheconverterisfreewheeling. PRMS2 é (I -I )2ù I = (1-D )êI ´I + PP MP2 ú »1.7A PRMS2 MAX PP MP2 3 ê ú ë û (44) TotalT1primaryRMScurrent(I ): PRMS I = I 2 +I 2 »3.1A PRMS PRMS1 PRMS2 (45) ForthisdesignaVitec™transformerwasselectedpartnumber75PR8107thathadthefollowingspecifications. a1=21 (46) L =2.8mH MAG (47) MeasureleakageinductanceonthePrimary: L = 4mH LK (48) TransformerPrimaryDCresistance: DCR =0.215W P (49) TransformerSecondaryDCresistance: DCR =0.58W S (50) Estimatedtransformercorelosses(P )aretwicethecopperloss. T1 NOTE Thisisjustanestimateandthetotallossesmayvarybasedonmagneticdesign. P »2´(I 2´DCR +2´I 2´DCR )»7.0W T1 PRMS P SRMS S (51) Calculateremainingpowerbudget: P =P -P »38.1W BUDGET BUDGET T1 (52) 42 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 8.2.2.3 QA,QB,QC,QDFETSelection Inthisdesigntomeetefficiencyandvoltagerequirements20A,650V,CoolMOSFETsfromInfineonarechosen forQA..QD. FETdraintosourceonresistance: R =0.220W ds(on)QA (53) FETSpecifiedC : OSS C =780pF OSS_QA_SPEC (54) Voltageacrossdrain-to-source(V )whereC wasmeasured,datasheetparameter: dsQA OSS V =25V dsQA (55) CalculateaverageC [2]: oss V C =C dsQA »193pF OSS_QA_AVG OSS_QA_SPEC V INMAX (56) QAFETgatecharge: QA =15nC g (57) VoltageappliedtoFETgatetoactivateFET: V =12V g (58) CalculateQAlosses(P )basedonR andgatecharge(QA ): QA ds(on)QA g P I 2 uR (cid:14)2uQA uV uf |2.1W QA PRMS DS(on)QA g g SW (59) Recalculatepowerbudget: P =P -4´P »29.7W BUDGET BUDGET QA (60) Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com 8.2.2.4 SelectingL S Calculatingthevalueoftheshiminductor(L )isbasedontheamountofenergyrequiredtoachievezerovoltage S switching. This inductor needs to able to deplete the energy from the parasitic capacitance at the switch node. The following equation selects L to achieve ZVS at 100% load down to 50% load based on the primary FET’s S averagetotalC attheswitchnode. OSS NOTE The actual parasitic capacitance at the switched node may differ from the estimate and L S mayhavetobeadjustedaccordingly. V 2 ( ) L ³ 2´C INMAX -L »26mH S OSS_QA_AVG 2 LK æI DI ö PP - LOUT ç ÷ è 2 2´a1ø (61) For this design a 26-µH Vitec inductor was chosen for L , part number 60PR964. The shim inductor had the S followingspecifications. L =26mH S (62) L DCResistance: S DCR =27mW LS (63) EstimateL powerloss(P )andreadjustremainingpowerbudget: S LS P =2´I 2´DCR »0.5W LS PRMS LS (64) P =P -P »29.2W BUDGET BUDGET LS (65) 8.2.2.5 SelectingDiodesD andD B C There is a potential for high voltage ringing on the secondary rectifiers, caused by the difference in current between the transformer and the shim inductor when the transformer comes out of freewheeling. Diodes D and B D provide a path for this current and prevent any ringing by clamping the transformer primary to the primary C side power rails. Normally these diodes do not dissipate much power but they should be sized to carry the full primarycurrent.Theworsecasepowerdissipatedinthesediodesis: P =0.5´L ´I2 ´F S PRMS SW (66) The diodes should be ultra-fast types and rated for the input voltage of the converter – V (410 VDC in this IN case). AMURS360partissuitableatthispowerlevel. 44 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 8.2.2.6 OutputInductorSelection(L ) OUT InductorL isdesignedfor20%inductorripplecurrent(∆I ): OUT LOUT P ´0.2 600W´0.2 DI = OUT = »10A LOUT V 12V OUT (67) V u(1(cid:16)D ) L OUT TYP |2PH OUT ’I u2uf LOUT SW (68) CalculateoutputinductorRMScurrent(I ): LOUT_RMS æP ö2 æDI ö2 I = ç OUT ÷ +ç LOUT ÷ =50.3A LOUT_RMS èV ø è 3 ø OUT (69) A 2-µH inductor from Vitec Electronics Corporation, part number 75PR8108, is suitable for this design. The inductorhasthefollowingspecifications. L =2mH OUT (70) OutputinductorDCresistance: DCR =750mW LOUT (71) Estimate output inductor losses (P ) and recalculate power budget. Note P is an estimate of inductor LOUT LOUT losses that is twice the copper loss. Note this may vary based on magnetic manufactures. It is advisable to doublecheckthemagneticlosswiththemagneticmanufacture. P =2´I 2´DCR »3.8W LOUT LOUT_RMS LOUT (72) P =P -P »25.4W BUDGET BUDGET LOUT (73) Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 45 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com 8.2.2.7 OutputCapacitance(C ) OUT Theoutputcapacitorisselectedbasedonholdupandtransient(V )loadrequirements. TRAN TimeittakesL tochange90%ofitsfullloadcurrent: OUT L ´P ´0.9 OUT OUT V t = OUT =7.5ms HU V OUT (74) During load transients most of the current will immediately go through the capacitors equivalent series resistance (ESR ). The following equations are used to select ESR and C based on a 90% load step in current. COUT COUT OUT The ESR is selected for 90% of the allowable transient voltage (V ), while the output capacitance (C ) is TRAN OUT selectedfor10%ofV . TRAN V ´0.9 ESR £ TRAN =12mW COUT P ´0.9 OUT V OUT (75) P ´0.9´t OUT HU V C ³ OUT »5.6mF OUT V ´0.1 TRAN (76) Beforeselectingtheoutputcapacitor,theoutputcapacitorRMScurrent(I )mustbecalculated. COUT_RMS DI I = LOUT »5.8A COUT_RMS 3 (77) To meet the design requirements five 1500-µF, aluminum electrolytic capacitors are chosen for the design from UnitedChemi-Con™,partnumberEKY-160ELL152MJ30S.ThesecapacitorshaveanESRof31mΩ. Numberofoutputcapacitors: n=5 (78) Totaloutputcapacitance: C =1500mF´n»7500mF OUT (79) EffectiveoutputcapacitanceESR: 31mW ESR = =6.2mW COUT n (80) Calculateoutputcapacitorloss(P ): COUT P =I 2´ESR »0.21W COUT COUT_RMS COUT (81) RecalculateremainingPowerBudget: P =P -P »25.2W BUDGET BUDGET COUT (82) 46 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 8.2.2.8 SelectFETsQEandQF SelectingFETsforadesignisaniterativeprocess.Tomeetthepowerrequirementsofthisdesign,weselect75- V,120-AFETs,fromFairchild,partnumberFDP032N08.TheseFETshavethefollowingcharacteristics. QE =152nC g (83) R =3.2mW ds(on)QE (84) Calculate average FET C (C ) based on the data sheet parameters for C (C ), and drain OSS OSS_QE_AVG OSS OSS_SPEC to source voltage where C was measured (V ), and the maximum drain to source voltage in the OSS_SPEC ds_spec design(V )thatwillbeappliedtotheFETintheapplication. dsQE VoltageacrossFETQEandQFwhentheyareoff: V V = INMAX »19.5V dsQE a1 (85) VoltagewhereFETC isspecifiedandtestedintheFETdatasheet: OSS V =25V ds_spec (86) SpecifiedoutputcapacitancefromFETdatasheet: C =1810pF OSS_SPEC (87) AverageQEandQFC [2]: OSS V C =C dsQE »1.6nF OSS_QE_AVG OSS_SPEC V ds_spec (88) QEandQFRMScurrent: I =I =36.0A QE_RMS SRMS (89) Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 47 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com To estimate FET switching loss the V vs. Q curve from the FET data sheet needs to be studied. First the gate g g charge at the beginning of the miller plateau needs to be determined (QE ) and the gate charge at the MILLER_MIN endofthemillerplateau(QE )forthegivenV . MILLER_MAX DS Maximumgatechargeattheendofthemillerplateau: QE »100nC MILLER_MAX (90) Minimumgatechargeatthebeginningofthemillerplateau: QE »52nC MILLER_MIN (91) NOTE The FETs in this design are driven with a UCC27324 Gate Driver IC, setup to drive 4-A (I )ofgatedrivecurrent. P I » 4A P (92) EstimatedFETV riseandfalltime: ds 100nC-52nC 48nC t » t = = »24ns r f I 4A P 2 2 (93) EstimateQEandQFFETLosses(P ): QE P P I 2uR (cid:14) OUT uV (cid:11)t (cid:14)t (cid:12)f (cid:14)2uC uV 2f (cid:14)2uQ uV f QE QE_RMS ds(on)QE V dsQE r f SW OSS_QE_AVG dsQE SW gQE gQESW OUT (94) P »9.3W QE (95) Recalculatethepowerbudget. P =P -2´P »6.5W BUDGET BUDGET QE (96) 48 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 8.2.2.9 InputCapacitance(C ) IN The input voltage in this design is 390 V , which is generally fed by the output of a PFC boost pre-regulator. DC Theinputcapacitanceisgenerallyselectedbasedonholdupandripplerequirements. NOTE ThedelaytimeneededtoachieveZVScanactasadutycycleclamp(D ). CLAMP Calculatetankfrequency: 1 f = R 2p L ´(2´C ) S OSS_QA_AVG (97) Estimateddelaytime: 2 t = »314ns DELAY f ´4 R (98) Effectivedutycycleclamp(D ): CLAMP § 1 • D ¤ (cid:16)t ‚u2uf 94% CLAMP '2uf DELAY„ SW SW (99) V istheminimuminputvoltagewheretheconvertercanstillmaintainoutputregulation.Theconverter’sinput DROP voltage would only drop down this low during a brownout or line-drop condition if this converter was following a PFCpre-regulator. æ2´D ´V +a1´(V +V )ö V =ç CLAMP RDSON OUT RDSON ÷ =276.2V DROP è D ø CLAMP (100) C wascalculatedbasedononelinecycleofholdup: IN 1 2´P ´ OUT 60Hz C ³ »364mF IN (V 2 -V 2) IN DROP (101) CalculatehighfrequencyinputcapacitorRMScurrent(I ). CINRMS 2 æ P ö I = I 2 -ç OUT ÷ =1.8A CINRMS PRMS1 V ´a1 è ø INMIN (102) To meet the input capacitance and RMS current requirements for this design a 330-µF capacitor was chosen fromPanasonicpartnumberEETHC2W331EA. C =330mF IN (103) Thiscapacitorhasahighfrequency(ESR )of150mΩ,measuredwithanimpedanceanalyzerat200kHz. CIN ESR =0.150W CIN (104) EstimateC powerdissipation(P ): IN CIN P =I 2´ESR =0.5W CIN CINRMS CIN (105) Recalculateremainingpowerbudget: P =P -P »6.0W BUDGET BUDGET CIN (106) There is roughly 6.0 W left in the power budget left for the current sensing network, and biasing the control deviceandallresistorssupportingthecontroldevice. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 49 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com 8.2.2.10 CurrentSenseNetwork(CT,R ,R7,D ) CS A TheCTchosenforthisdesignhasaturnsratio(CT )of100:1 RAT I CT = P =100 RAT I S (107) Calculatenominalpeakcurrent(I )atV : P1 INMIN Peakprimarycurrent: æ P DI ö 1 V ´D I =ç OUT + LOUT ÷ + INMIN MAX »3.3A P1 V ´h 2 a1 L ´2´F è OUT ø MAG SW (108) TheCSpinvoltagewherepeakcurrentlimitwilltrip. V =2V P (109) Calculatecurrentsenseresistor(R )andleave300mVforslopecompensation.Includea1.1factorformargin: CS V -0.3V R = P » 47W CS I P1 ´1.1 CT RAT (110) SelectastandardresistorforR : CS R = 47W CS (111) EstimatepowerlossforR : CS 2 æ I ö P =ç PRMS1 ÷ ´R »0.03W RCS CT CS è ø RAT (112) Calculatemaximumreversevoltage(V )onD : DA A D V = V CLAMP »29.8V DA P1-D CLAMP (113) EstimateD powerloss(P ): A DA P ´0.6V P = OUT »0.01W DA V ´h´CT INMIN RAT (114) CalculateresetresistorR7: ResistorR7isusedtoresetthecurrentsensetransformerCT. R7 =100´R = 4.7kW CS (115) 50 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 Resistor R and capacitor C form a low pass filter for the current sense signal (Pin 15). For this design we LF1 LF chose the following values. This filter has a low frequency pole (f ) at 482 kHz. This should work for most LFP applicationsbutmaybeadjustedtosuitindividuallayoutsandEMIpresentinthedesign. R =1kW LF1 (116) C =330pF LF (117) 1 f = = 482kHz LFP 2pf´R ´C LF1 LF (118) The UCC28950 VREF output (Pin 1) needs a high frequency bypass capacitor to filter out high frequency noise. Thispinneedsatleast1µFofhighfrequencybypasscapacitance(C ). REF C =1mF REF (119) The voltage amplifier reference voltage (Pin 2, EA +) can be set with a voltage divider (R1, R2), for this design example, the error amplifier reference voltage (V1) will be set to 2.5 V. Select a standard resistor value for R1 andthencalculateresistorvalueR2. UCC28950referencevoltage: V =5V REF (120) Setvoltageamplifierreferencevoltage: V1=2.5V (121) R1= 2.37kW (122) R1´(V -V1) R2= REF = 2.37kW V1 (123) VoltagedividerformedbyresistorR3andR4arechosentosettheDCoutputvoltage(V )atPin3(EA-). OUT SelectastandardresistorforR3: R3 = 2.37kW (124) CalculateR4: R3´(V -V1) R4 = OUT »9kW V1 (125) ThenchooseastandardresistorforR4: R3´(V -V1) R4 = OUT »9.09kW V1 (126) Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 51 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com 8.2.2.10.1 VoltageLoopCompensationRecommendation Forbestresultsinthevoltageloop,TIrecommendsusingaType2orType3compensationnetwork(Figure50). A Type 2 compensation network does not require passive components C and R . Type 1 compensation is not Z2 Z2 versatile enough for a phase shifted full bridge. When evaluating the COMP for best results, TI recommends placinga1-kΩresistorbetweenthesocpeprobeandtheCOMPpinoftheUCC28950. V V OUT REF EA+ + C R EA- Z2 I 1 k: R D C R Z1 R Z2 R Z1 C P1 R When evaluating COMP, for best results put a 1-k: resistor between COMP and probe. Figure50. Type3CompensationEvaluation Compensating the feedback loop can be accomplished by properly selecting the feedback components (R5, C1 and C2). These components are placed as close as possible to pin 3 and 4 of the UCC28950. A Type 2 compensationnetworkisdesignedinthisexample. Calculateloadimpedanceat10%load(R ): LOAD V 2 R = OUT =2.4W LOAD P ´0.1 OUT (127) Approximationofcontroltooutputtransferfunction(G (f))asafunctionoffrequency: CO DV R æ1+2pj´f´ESR ´C ö 1 G (f)» OUT =a1´CT ´ LOAD ´ç COUT OUT ÷´ RAT CO DV R è 1+2pj´f´R ´C ø S(f) æ S(f) ö2 C CS LOAD OUT 1+ +ç ÷ 2p´f è2p´f ø PP PP (128) DoublepolefrequencyofG (f): CO F f » SW =50kHz PP 2 (129) Angularvelocity: S(f)=2p´j´f (130) 52 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 Compensate the voltage loop with type 2 feedback network. The following transfer function is the compensation gainasafunctionoffrequency(G (f)). C DV 2pj´f´R5´C2+1 G (f)= C = C DV æ2pj´f´C2´C1´R5 ö OUT 2pj´f´(C2+C1)R4 +1 ç ÷ è C2+C1 ø (131) Calculate voltage loop feedback resistor (R5) based on crossing the voltage loop (f ) over at a 10th of the double C polefrequency(f ). PP f f = PP =5kHz C 10 (132) R4 R5 = » 27.9kW æf ö G PP ç ÷ COè10ø (133) SelectastandardresistorforR5. R5 » 27.4kW (134) Calculatethefeedbackcapacitor(C2)togiveaddedphaseatcrossover. 1 C2= »5.8nF f 2´p´R5´ C 5 (135) Selectastandardcapacitancevalueforthedesign. C2=5.6nF (136) Putapoleattwotimesf . C 1 C1= »580pF 2´p´R5´f ´2 C (137) Selectastandardcapacitancevalueforthedesign. C1=560pF (138) Loopgainasafunctionoffrequency(T (f))indB. V ( ) T dB(f)=20log G (f)´G (f) V C CO (139) Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 53 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com Plot theoretical loop gain and phase to graphically check for loop stability (Figure 51). The theoretical loop gain crossesoveratroughly3.7kHzwithaphasemarginofgreaterthan90degrees. 80 180 60 135 40 90 s e 20 45 e B gr d e Gain in -200 -045 ase in D h P -40 -90 TvdB(f) -60 -135 &Tv(f) -80 -180 100 1000 10000 100000 Frequency in Hz Figure51. LoopGainandPhasevsFrequency NOTE TI recommends checking your loop stability of your final design with transient testing and/oranetworkanalyzerandadjustthecompensation(G (f))feedbackasnecessary. C V ´(1-D ) L ³ IN TYP » 2.78mH MAG DI ´0.5 LOUT ´2´F a1 SW where • LoopGain(T dB(f)),LoopPhase(ΦT (f)) (140) V V 54 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 To limit over shoot during power up the UCC28950 has a soft-start function (SS, Pin 5) which in this application wassetforasoftstarttimeof15ms(t ). SS t =15ms ss (141) t ´25mA C = SS »123nF SS V1+0.55 (142) Selectastandardcapacitorforthedesign. C =150nF SS (143) This application note presents a fixed delay approach to achieving ZVS from 100% load down to 50% load. Adaptive delays can be generated by connecting the ADEL and ADELEF pins to the CS pin as shown in Figure52. UCC28950 R AHI CS 15 ADEL 14 R AEFHI ADELEF 13 R A R AEF Figure52. UCC28950AdaptiveDelays Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 55 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com When the converter is operating below 50% load the converter will be operating in valley switching. In order to achieve zero voltage switching on switch node of QB , the turn-on (t ) delays of FETs QA and QB need to d ABSET be initially set based on the interaction of L and the theoretical switch node capacitance. The following S equationsareusedtosett initially. ABSET EquateshiminductancetotwotimesC capacitance: OSS 1 2p´f L = R S 2p´f ´(2´C ) R OSS_QA_AVG (144) Calculatetankfrequency: 1 f = R 2p L ´(2´C ) S OSS_QA_AVG (145) Setinitialt delaytimeandadjustasnecessary. ABSET NOTE The 2.25 factor of the t equation was derived from empirical test data and may vary ABSET basedonindividualdesigndifferences. 2.25 t = »346ns ABSET f ´4 R (146) The resistor divider formed by R and R programs the t , t delay range of the UCC28950. Select a A AHI ABSET CDSET standardresistorvalueforR . AHI NOTE t canbeprogrammedbetween30nsto1000ns. ABSET R =8.25kW AHI (147) The voltage at the ADEL input of the UCC28950 (V ) needs to be set with R based on the following ADEL A conditions. Ift >155nssetV =0.2V,t canbeprogrammedbetween155nsand1000ns: ABSET ADEL ABSET Ift ≤155nssetV =1.8V,t canbeprogrammedbetween29nsand155ns: ABSET ADEL ABSET 56 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 BasedonV selection,calculateR : ADEL A R ´V R = AHI ADEL »344W A 5V-V ADEL (148) SelectthecloseststandardresistorvalueforR : A R =348W A (149) RecalculateV basedonresistordividerselection: ADEL 5V´R V = A =0.202V ADEL R +R AHI A (150) ResistorR programst : AB ABSET T R = ABSET ´(0.26+CS´K ´1.3)»30.6kW AB 5 A (151) Selectastandardresistorvalueforthedesign: R =30.1kW AB (152) NOTE Once you have a prototype up and running it is recommended you fine tune t at light ABSET load to the peak and valley of the resonance between L and the switch node S capacitance.Inthisdesignthedelaywassetat10%load.PleaserefertoFigure53. Set t at resonant tank Peak and Valley ABSET t = t - t t = t - t ABSET 1 0 ABSET 4 3 QB d QA g Miller Plateau t = t - t MILLER 2 1 QBg Miller Plateau t = t - t MILLER 5 4 t0 t1 t2 t3 t4 t5 Figure53. t toAchieveValleySwitchingatLightLoads ABSET Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 57 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com The QC and QD turnon delays (t ) should be initially set for the same delay as the QA and QB turn on CDSET delays (Pin 6). The following equations program the QC and QD turn-on delays (t ) by properly selecting CDSET resistorR (Pin7). DELCD t = t ABSET CDSET (153) ResistorR programst : CD CDSET T R = CDSET ´(0.26+CS´K ´1.3)»30.6kW CD 5 A (154) Selectastandardresistorforthedesign: R =30.1kW CD (155) NOTE Once you have a prototype up and running it is recommended to fine tune t at light CDSET load. In this design the CD node was set to valley switch at roughly 10% load. Please refer to Figure 54. Obtaining ZVS at lighter loads with switch node QD is easier due to d the reflected output current present in the primary of the transformer at FET QD and QC turnoff/on. This is because there was more peak current available to energize L before S thistransition,comparedtotheQAandQBturnoff/on. Set t at resonant tank Peak and Valley CDSET t = t - t t = t - t CDSET 1 0 CDSET 4 3 QD d QC g Miller Plateau t = t - t MILLER 2 1 QDg Miller Plateau t = t - t MILLER 5 4 t t t t t t 0 1 2 3 4 5 Figure54. t toAchieveValleySwitchingatLightLoads CDSET 58 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 There is a programmable delay for the turnoff of FET QF after FET QA turnoff (t ) and the turnoff of FET QE AFSET after FET QB turnoff (t ). A good place to set these delays is 50% of t . This will ensure that the BESET ABSET appropriate synchronous rectifier turns off before the AB ZVS transition. If this delay is too large it will cause OUTEandOUTFnottooverlapcorrectlyanditwillcreateexcessbodydiodeconductiononFETsQEandQF. t = t = t ´0.5 AFSET BESET ABSET (156) The resistor divider formed by R and R programs the t and t delay range of the UCC28950. AEF AEFHI AFSET BESET SelectastandardresistorvalueforR . AEFHI NOTE t andt canbeprogrammedbetween32nsto1100ns. EFSET BESET R =8.25kW AEFHI (157) The voltage at the ADELEF pin of the UCC28950 (V ) needs to be set with R based on the following ADELEF AEF conditions. Ift <170nssetV =0.2V,t canbeprogrammedbetween32nsand170ns: AFSET ADEL ABSET Ift >or=170nssetV =1.7V,t canbeprogrammedbetween170nsand1100ns: ABSET ADEL ABSET BasedonV selection,calculateR : ADELEF AEF R ´V R = AEFHI ADELEF » 4.25kW AEF 5V-V ADELEF (158) SelectthecloseststandardresistorvalueforR : AEF R = 4.22kW AEF (159) RecalculateV basedonresistordividerselection: ADELEF 5V´R V = AEF =1.692V ADELEF R +R AEFHI AEF (160) Thefollowingequationwasusedtoprogramt andt byproperlyselectingresistorR . AFSET BESET EF (t ´0.5-4ns) (2.65V-V ´1.32)´103 1 R = AFSET ´ ADELEF ´ »14.1kW EF ns 5 1A (161) Astandardresistorwaschosenforthedesign. R =14kW EF (162) Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 59 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com Resistor R programs the minimum on time (t ) that the UCC28950 (Pin 9) can demand before entering TMIN MIN burst mode. If the UCC28950 controller tries to demand a duty cycle on time of less than t the power supply MIN willgointoburstmodeoperation.Forthisdesignwesettheminimumontimeto75ns. t =75ns MIN (163) TheminimumontimeissetbyselectingR withthefollowingequation. TMIN t R = MIN »12.7kW TMIN 5.92 (164) Astandardresistorvalueisthenchosenforthedesign. R =13kW TMIN (165) AresistorfromtheRTpintogroundsetstheconverterswitchingfrequency. æ WHz ö 2.5´106 ç V W÷ RT =ç F - V÷´(VREF -2.5V)´2.5´103 »60kW ç SW ÷ è 2 ø (166) Selectastandardresistorforthedesign. R =61.9kW T (167) The UCC28950 provides slope compensation. The amount of slope compensation is set by the resistor R . As SUM suggested earlier, we set the slope compensation ramp to be half the inductor current ramp downslope (inductor current ramp during the off time), reflected through the main transformer and current sensing networks as explainedearlierinSlopeCompensation(R ). SUM Therequiredslopecompensationrampis V uR 12u47 mV me 0.5u OUT CS 0.5u 67 L ua1uCT 2u10(cid:16)6 u21u100 Ps OUT RAT (168) The magnetizing current of the power transformer provides part of the compensating ramp and is calculated from Equation169. m = VINMAX ´RCS = 400´47 »7mV MAG LMAG ´CTRAT 2.76x10-3´100 ms (169) Therequiredcompensatingrampis mV mV mSUM =me- mMAG =(67-7) ms =60 ms (170) The value for the resistor, R , may be found from the graph in Figure 37 or calculated from rearranged SUM versions of Equation 12 or Equation 13 depending on whether the controller is operating in Current or Voltage Control Mode. In this case we are using Current Mode Control and Equation 12 is rearranged and evaluated as follows 2.5 2.5 R = = »82kW SUM 0.5´m 0.5´60x10-3 SUM (171) 60 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 Check that the 300mV we allowed for the slope compensation ramp when choosing R in Equation 110 is CS sufficient. mV 60 ´0.7 m ´D ms DV = SUM MAX = =210mV SLOPE-COMP 2´F 2´100kHz SW (172) ToincreaseefficiencyatlighterloadstheUCC28950isprogrammed(Pin12,DCM)underlightloadconditionsto disable the synchronous FETs on the secondary side of the converter (Q and Q ). This threshold is E F programmed with resistor divider formed by R and R . This DCM threshold needs to be set at a level DCMHI DCM before the inductor current goes discontinuous. The following equation sets the level at which the synchronous rectifiersaredisabledatroughly15%loadcurrent. æP ´0.15 DI ö ç OUT + LOUT ÷´R V 2 CS è ø V = OUT =0.29V RCS a1´CT RAT (173) SelectastandardresistorvalueforR . DCM R =1kW DCM (174) CalculateresistorvalueR . DCMHI R (V -V ) R = DCM REF RCS »16.3kW DCMHI V RCS (175) Selectastandardresistorvalueforthisdesign R =16.9kW DCMHI (176) NOTE It is recommended to use an RCD clamp to protect the output synchronous FETs from overvoltageduetoswitchnoderinging. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 61 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com Figure55. DaughterBoardSchematic 62 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 + + + + + + + Figure56. PowerStageSchematic Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 63 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com 8.2.3 ApplicationCurves Valley Switching QBd QDd Valley Switching QBg QDg QB = off QB = on QD = off QD = on 0V 0V QA= on QA/QB = off QC = on QC = off tABSET tD Sbligefhotr De eMlailyle arf Ptelra tteauABSET tCDSET tD Slbigehfot rDee Mlaiyll earf tPelra tteauCDSET V =390V V =390V IN IN I =5A I =5A OUT OUT Figure57.FullBridgeGateDrives Figure58.FullBridgeGateDrives andPrimarySwitchNodes(QB andQD ) andPrimarySwitchNodes(QD QD ) d d g d QBd Valley Switching QDd QBg ZVS QDg QB = off QB = on QD = off 0V QD = on 0V 0V QA= on QA/QB = off QC = on QC = off tABSET tD Slbigehfot rDee Mlaiyll earf tPelra tteauABSET tCDSET tD Slbigehfot rDee Mlaiyll earf tPelra tteauCDSET VIN=390V VIN=390V IOUT=10A IOUT=10A Figure59.Full-BridgeGateDrives Figure60.Full-BridgeGateDrives andSwitchNodes(QBgQBd) andSwitchNodes(QDgQDd) NOTE Switch node QB is valley switching and node QD has achieved ZVS. Please refer to d d Figure 59 and Figure 60. It is not uncommon for switch node QD to obtain ZVS before d QB . This is because during the QD switch node voltage transition, the reflected output d d current provides immediate energy for the LC tank at the switch node. Where at the QB d switch node transition the primary has been shorted out by the high side or low side FETs in the H bridge. This transition is dependent on the energy stored in L and L to provide S LK energyfortheLCtankatswitchnodeQB makingittakelongertoachieveZVS. d 64 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 QBd ZVSAchieved QDd ZVS QDg QBg QB = off QB = on QD = off QD = on 0V 0V QA= on QC = on QA/QB = off QC= off tABSET tCDSET VIN=390V VIN=390V IOUT=25A IOUT=25A Figure61.Full-BridgeGateDrives Figure62.Full-BridgeGateDrives andSwitchNodes(QBgQBd) andSwitchNodes(QDgQDd) NOTE When the converter is running at 25 A, both switch nodes are operating into zero voltage switching (ZVS). It is also worth mentioning that there is no evidence of the gate miller plateau during gate driver switching. This is because the voltage across the drains and sourcesofFETsQAthroughQDhavealreadytransitionedbefore. QBd ZVS QDd ZVS QDg QBg QB = off QB = on QD = off QD = on 0V 0V QA= on QA/QB = off QC = on QC = off tABSET tCDSET VIN=390V VIN=390V IOUT=50A IOUT=50A Figure63.Full-BridgeGateDrives Figure64.Full-BridgeGateDrives andSwitchNodes(QBgQBd) andSwitchNodes(QDgQDd) NOTE ZVSmaintainedfrom50%to100%outputpower. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 65 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com 9 Power Supply Recommendations The UCC28950 device should be operated from a V rail within the limits given in the Recommended Operating DD Conditions section of this datasheet. To avoid the possibility that the device might stop switching, V must not DD be allowed to fall into the UVLO_FTH range. In order to minimize power dissipation in the device, V should not DD be unnecessarily high. Keeping V at 12 V is a good compromise between these competing constraints. The DD gate drive outputs from the UCC28950 device deliver large-current pulses into their loads. This indicates the need for a low-ESR decoupling capacitor to be connected as directly as possible between the V and GND DD terminals. TI recommends ceramic capacitors with stable dielectric characteristics over temperature, such as X7R. Avoid capacitorswhichhavealargedropincapacitancewithappliedDCvoltagebias.Forexample,useapartthathas a low-voltage co-efficient of capacitance. The recommended decoupling capacitance is 1 μF, X7R, with at least a 25-Vratingwitha0.1-µFNPOcapacitorinparallel. 10 Layout 10.1 Layout Guidelines Inordertoincreasethereliabilityandrobustnessofthedesign,TIrecommendsthefollowinglayoutguidelines. • VREF pin. Decouple this pin to GND with a good quality ceramic capacitor. A 1-uF, X7R, 25V capacitor is recommended.KeepVREFPCBtracksasfarawayaspossiblefromsourcesofswitchingnoise. • EA+ pin. This is the non-inverting input to the error amplifier. It is a high impedance pin and is susceptible to noisepickup.Keeptracksfromthispinasshortaspossible. • EA– pin.Thisistheinvertinginputtotheerroramplifier.Itisahighimpedancepinandissusceptibletonoise pickup.Keeptracksfromthispinasshortaspossible. • COMP pin. The error amplifier compensation network is normally connected to this pin. Keep tracks from this pinasshortaspossible. • SS/EN pin. Keep tracks from this pin as short as possible. If the Enable signal is coming from a remote source then avoid running it close to any source of high dv/dt (MOSFET Drain connections for example) and addasimpleRCfilterattheSS/ENpin. • DELAB, DELCD, DELEF, TMIN, RT, R , DCM, ADELEF and ADEL pins. The components connected to SUM these pins are used to set important operating parameters. Keep these components close to the IC and provideshort,lowimpedancereturnconnectionstotheGNDpin. • CS pin. This connection is arguably the most important single connection in the entire PSU system. Avoid running the CS signal traces near to sources of high dv/dt. Provide a simple RC filter as close to the pin as possibletohelpfilteroutleadingedgenoisespikeswhichwilloccuratthebeginningofeachswitchingcycle. • SYNC pin. This pin is essentially a digital I/O port. If it is unused, then it may be left open circuit or tied to ground via a 1-kΩ resistor. If Synchronisation is used, then route the incoming Synchronisation signal as far awayfromnoisesensitiveinputpinsaspossible. • OUTA, OUTB, OUTC, OUTD, OUTE and OUTF pins. These are the gate drive output pins and will have a highdv/dtrateassociatedwiththeirrisingandfallingedges.Keepthetracksfromthesepinsasfarawayfrom noise sensitive input pins as possible. Ensure that the return currents from these outputs do not cause voltage changes in the analog ground connections to noise sensitive input pins. Follow the layout recommendationforAnalogandPowergroundPlanesinFigure45. • VDD pin. This pin must be decoupled to GND using ceramic capacitors as detailed in the 'Power Supply Recommendations'section.KeepthiscapacitorasclosetotheVDDandGNDpinsaspossible. • GND pin. This pin provides the ground reference to the controller. Use a Ground Plane to minimize the impedanceofthegroundconnectionandtoreducenoisepickup. 66 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

UCC28950 www.ti.com SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 10.2 Layout Example VREF pin decoupled to GND (C1), close to the device R28 VDD decoupling as close to the R6 Top Side device as possible. (C6, C5) C8 R2 R7 C1 C6 C5 R15 R9 U1 C3 C4 R5 R1 OUTA through OUTE signals routed as far as possible from signal pins. (pins 17 through 22) R12 R11 R16 R13 R24 C7 R14 R27 RC filter close to CS pin. R17 (C7, R27, pin 15) R25 R28 R26 R22 R23 Short tracks at EA+, EA-, COMP, SS/EN, DELAB, DELCD, TMIN, RT, RSUM, DCM, ADELEF, and ADEL pins. (pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14) Figure65. UCC28950LayoutExample(TopSide) Bottom Side R29 C2 J1 R3 R4 R20 R8 R10 Figure66. UCC28950LayoutExample(BottomSide) Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 67 ProductFolderLinks:UCC28950

UCC28950 SLUSA16D–MARCH2010–REVISEDNOVEMBER2016 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-PartyProductsDisclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONEORINCOMBINATIONWITHANYTIPRODUCTORSERVICE. 11.1.2 DevelopmentSupport FortheMathCADDesignTool,seeSLUC210. FortheExcelDesignTool,seeSLUC222. 11.2 Documentation Support 11.2.1 RelatedDocumentation SynchronizingThreeorMoreUCC28950Phase-Shifted,Full-BridgeControllers,SLUA609. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.4 Trademarks E2EisatrademarkofTexasInstruments. UnitedChemi-ConisatrademarkofUnitedChemi-Con. VitecisatrademarkofVitecElectronicsCorporation. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 68 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC28950

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCC28950PW ACTIVE TSSOP PW 24 60 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 UCC28950 & no Sb/Br) UCC28950PWR ACTIVE TSSOP PW 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 UCC28950 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 OTHER QUALIFIED VERSIONS OF UCC28950 : •Automotive: UCC28950-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UCC28950PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UCC28950PWR TSSOP PW 24 2000 350.0 350.0 43.0 PackMaterials-Page2

PACKAGE OUTLINE PW0024A TSSOP - 1.2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 22X 0.65 24 1 2X 7.9 7.15 7.7 NOTE 3 12 13 0.30 24X B 4.5 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 0.25 GAGE PLANE 0.15 0.05 (0.15) TYP SEE DETAIL A 0.75 0 -8 0.50 DETA 20AIL A TYPICAL 4220208/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 24X (1.5) SYMM (R0.05) TYP 1 24X (0.45) 24 22X (0.65) SYMM 12 13 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220208/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 24X (1.5) SYMM (R0.05) TYP 1 24X (0.45) 24 22X (0.65) SYMM 12 13 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220208/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated