TPS767D301-Q1, TPS767D318-Q1, TPS767D325-Q1 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS SGLS231A − FEBRUARY 2004 − JUNE 2008 (cid:2) Qualified for Automotive Applications PWP PACKAGE (cid:2) (TOP VIEW) Dual Output Voltages for Split-Supply Applications NC 1 28 1RESET (cid:2) Output Current Range of 0 mA to 1.0 A Per NC 2 27 NC Regulator 1GND 3 26 NC (cid:2) 3.3-V/2.5-V, 3.3-V/1.8-V, and 3.3-V/Adjustable 1EN 4 25 1FB/NC Output 1IN 5 24 1OUT (cid:2) 1IN 6 23 1OUT Fast-Transient Response NC 7 22 2RESET (cid:2) 2% Tolerance Over Load and Temperature NC 8 21 NC (cid:2) Dropout Voltage Typically 350 mV at 1 A 2GND 9 20 NC (cid:2) Ultra Low 85 μA Typical Quiescent Current 2EN 10 19 NC 2IN 11 18 2OUT (cid:2) 1 μA Quiescent Current During Shutdown 2IN 12 17 2OUT (cid:2) Dual Open Drain Power-On Reset With NC 13 16 NC 200-ms Delay for Each Regulator NC 14 15 NC (cid:2) 28-Pin PowerPAD™ TSSOP Package (cid:2) NC − No internal connection Thermal Shutdown Protection for Each Regulator description The TPS767D3xx family of dual voltage regulators offers fast transient response, low dropout voltages and dual outputs in a compact package and incorporating stability with 10-μF low ESR output capacitors. The TPS767D3xx family of dual voltage regulators is designed primarily for DSP applications. These devices can be used in any mixed-output voltage application, with each regulator supporting up to 1 A. Dual active-low reset signals allow resetting of core-logic and I/O separately. (cid:2)(cid:3) AVAILABLE OPTIONS REGULATOR 1 REGULATOR 2 TSSOP TJ VO (V) VO (V) (PWP) Adj (1.5 − 5.5 V) 3.3 V TPS767D301QPWPRQ1 −4400°CC ttoo 112255°CC 1.8 V 3.3 V TPS767D318QPWPRQ1 2.5 V 3.3 V TPS767D325QPWPRQ1 †For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. The TPS767D301 is adjustable using an external resistor divider (see application information). The PWP packages are taped and reeled as indicated by the R suffix on the device type (e.g., TPS767D301QPWPRQ1). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2008 Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

TPS767D301-Q1, TPS767D318-Q1, TPS767D325-Q1 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS SGLS231A − FEBRUARY 2004 − JUNE 2008 DROPOUT VOLTAGE vs LOAD TRANSIENT RESPONSE FREE-AIR TEMPERATURE 100 103 V nm VO = 3.3 V ange iage − 50 CTAL == 12050° CμF 102 IO = 1 A Cholt 0 V − Out V − m Vp e Δ Out −50 oltag 101 V A −100 ut − po IO = 10 mA nt 1 ro 100 e D rr − Cu O put 0.5 VD 10−1 I − OutO 0 10−2 VCOO == 31.03 μVF IO = 0 0 20 40 60 80 100 120 140 160 180 200 −60 −40 −20 0 20 40 60 80 100 120 140 t − Time − μs TA − Free-Air Temperature − °C description (continued) Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 350 mV at an output current of 1 A for the TPS767D325) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 85 μA over the full range of output current, 0 mA to 1 A). These two key specifications yield a significant improvement in operating life for battery-powered systems. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to 1 μA at T = 25°C. J The RESET output of the TPS767D3xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS767D3xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. The TPS767D3xx is offered in 1.8-V, 2.5-V, and 3.3-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS767D3xx family is available in 28 pin PWP TSSOP package. They operate over a junction temperature range of −40°C to 125°C. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS767D301-Q1, TPS767D318-Q1, TPS767D325-Q1 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS SGLS231A − FEBRUARY 2004 − JUNE 2008 TPS767D3xx 5 28 RESET VI IN RESET 6 IN 250 kΩ 24 C1 OUT VO 0.15 0 μ VF 4 EN OUT 23 + CO 10 μF GND 3 Figure 1. Typical Application Circuit (Fixed Versions) for Single Channel POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

TPS767D301-Q1, TPS767D318-Q1, TPS767D325-Q1 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS SGLS231A − FEBRUARY 2004 − JUNE 2008 functional block diagram—adjustable version (for each LDO) IN EN RESET _ + OUT + _ 200 ms Delay R1 Vref = 1.1834 V R2 GND functional block diagram—fixed-voltage version (for each LDO) IN EN RESET _ + OUT + 200 ms Delay R1 _ Vref = 1.1834 V FB/NC R2 GND External to the device 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS767D301-Q1, TPS767D318-Q1, TPS767D325-Q1 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS SGLS231A − FEBRUARY 2004 − JUNE 2008 Terminal Functions TERMINAL II//OO DDEESSCCRRIIPPTTIIOONN NAME NO. 1GND 3 Regulator #1 ground 1EN 4 I Regulator #1 enable 1IN 5, 6 I Regulator #1 input supply voltage 2GND 9 Regulator #2 ground 2EN 10 I Regulator #2 enable 2IN 11, 12 I Regulator #2 input supply voltage 2OUT 17, 18 O Regulator #2 output voltage 2RESET 22 O Regulator #2 reset signal 1OUT 23, 24 O Regulator #1 output voltage 1FB/NC 25 I Regulator #1 output voltage feedback for adjustable and no connect for fixed output 1RESET 28 O Regulator #1 reset signal NC 1, 2, 7, 8, No connection 13−16, 19, 20, 21, 26, 27 timing diagram VI Vres† Vres t VO VIT+‡ VIT+‡ Threshold Voltage Less than 5% of the output voltage VIT− VIT− t RESET Output 200 ms 200 ms Delay Delay ÎÎ ÎÎ OutputÎÎ ÎÎ Output Undefined Undefined ÎÎ ÎÎ ÎÎ ÎÎt †Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. ‡VIT −Trip voltage is typically 5% lower than the output voltage (95%VO) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

TPS767D301-Q1, TPS767D318-Q1, TPS767D325-Q1 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS SGLS231A − FEBRUARY 2004 − JUNE 2008 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Input voltage range‡, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 13.5 V I Input voltage range, V (1IN, 2IN, EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.3 V I I Output voltage, V (1OUT, 2OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V O Output voltage, V (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V O Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See dissipation rating tables Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C J Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡All voltage values are with respect to network terminal ground. DISSIPATIÁON ÁRATÁINGÁ TABÁLEÁ PACKAGE AIR FLOW TA ≤ 25°C ÁDEÁRATÁINGÁ FAÁCTOÁR TA = 70°C TA = 85°C ÁÁÁÁÁÁÁ(ÁCFMÁ) ÁÁPÁOWEÁR RÁATIÁNG ÁÁÁAÁÁBOÁÁVE TÁÁA = ÁÁ25°CÁÁÁÁPOWÁERÁ RAÁTINGÁÁPÁOWÁER ÁRATÁINGÁ 0 3.58 W 35.8 mW/°C 1.97 W 1.43 W ÁÁÁÁPPÁÁWWPPÁÁ§§ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 250 5.07 W 50.7 mW/°C 2.79 W 2.03 W ÁÁÁÁÁ ÁÁÁÁÁÁ This parameter is measured with the recommended copper heat sink pattern on a 4−layer PCB, 1 oz. copper on 4−in x 4−in ground layer. For more information, refer to TI technical brief literature number SLMA002. recommended operating conditions MIN MAX UNIT Input voltage, VI¶ (1IN, 2IN) 2.7 10 V Output current for each LDO, IO (Note 1) 0 1.0 A Output voltage range, VO (1OUT, 2OUT) 1.5 5.5 V Operating virtual junction temperature, TJ −40 125 °C ¶To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load). NOTE 1: Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the device operate under conditions beyond those specified in this table for extended periods of time. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS767D301-Q1, TPS767D318-Q1, TPS767D325-Q1 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS SGLS231A − FEBRUARY 2004 − JUNE 2008 electrical characteristics, Vi = VO(nom) + 1 V, IO = 1 mA, EN = 0, CO = 10 μF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AAddjjuussttaabbllee 1110..55 μ VVA ≤≤ < VV IOOO <≤≤ 155 ..A55 VV,, TTJJ == −254°0C°C to 125°C 0.98VO VO 1.02VO 11.88 VV OOuuppuutt 2210..88 μ VVA << < VV IOII << < 11 100 AVV,, TTJJ == −254°0C°C to 125°C 1.764 1.8 1.836 VV OOuuttppuutt vvoollttaaggee ((VVO)) ((sseeee NNoottee 22)) 22.55 VV OOuuttppuutt 3310..55 μ VVA << < VV IOII << < 11 100 AVV,, TTJJ == −254°0C°C to 125°C 2.45 2.5 2.55 33.33 VV OOuuttppuutt 4410..33 μ VVA << < VV IOII << < 11 100 AVV,, TTJJ == −254°0C°C to 125°C 3.234 3.3 3.366 VV Quiescent current (GND current) for each LDO 10 μA < IO < 1 A, TJ = 25°C 85 ((sseeee NNoottee 22)) μAA IO = 1 A, TJ = −40°C to 125°C 125 Output voltage line regulation for each LDO (ΔVO/VO) (see Notes 2 and 3) VO + 1 V < VI ≤ 10 V, TJ = 25°C 0.01 %/V Output noise voltage BW = 200 Hz to 100 kHz, VO = 1.8 V, 55 μVrms IC = 1 A, CO = 10 μF, TJ = 25°C Output current limit for each LDO VO = 0 V 1.7 2 A Thermal shutdown juction temperature 150 °C 2.7 < VI < 10V, EN = VI, 1 μA TJ = 25°C, SSttaannddbbyy ccuurrrreenntt ffoorr eeaacchh LLDDOO 2.7 < VI < 10V, EN = VI, 10 μA TJ = −40°C to 125°C FB input current Adjustable FB = 1.5 V 2 nA High level enable input voltage 2.0 V Low level enable input voltage 0.8 V Power supply ripple rejection (see Note 2) f = 1 KHz, TJ = 25°C, CO = 10 μF 60 dB Minimum input voltage for valid RESET IO(RESET) = 300 μA 1.1 V Trip threshold voltage VO decreasing 92 98 %VO Hysteresis voltage Measured at VO 0.5 %VO RReesseett Output low voltage VI = 2.7 V, IO(RESET) = 1 mA 0.15 0.4 V Leakage current V(RESET) = 7 V 1 μA RESET time-out delay 200 mA NOTES: 2. Minimum IN operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. maximum IN voltage 10V. 3. If VO ≤ 1.8 V, VImin = 2.7 V, and VImax = 10 V: (cid:3) (cid:5) V V (cid:7)2.7V LineReg.(mV) (cid:2) (cid:3)%(cid:4)V(cid:5) (cid:6) O Imax (cid:6)1000 100 If VO ≥ 2.5 V, VImin = Vo + 1 V, and VImax = 10 V: (cid:3) (cid:3) (cid:5)(cid:5) V V (cid:7) V (cid:8)1V O Imax O LineReg.(mV) (cid:2) (cid:3)%(cid:4)V(cid:5) (cid:6) (cid:6)1000 100 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

TPS767D301-Q1, TPS767D318-Q1, TPS767D325-Q1 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS SGLS231A − FEBRUARY 2004 − JUNE 2008 electrical characteristics, Vi = VO(nom) + 1 V, IO = 1 mA, EN = 0, CO = 10 μF (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EN = 0 V −1 0 1 IInnppuutt ccuurrrreenntt ((EENN)) μAA EN = VI −1 1 Load regulation 3 mV TJ = 25°C 350 DDrrooppoouutt vvoollttaaggee ((sseeee NNoottee 44)) VVO = 33.33 VV, IIO = 11 AA TJ = −40°C to 125°C 575 mmVV NOTE 4: IN voltage equals Vo(Typ) − 100mV; Adjustable output voltage set to 3.3V nominal with external resistor divider. 1.8V, and 2.5V dropout voltage is limited by input voltage range limitations. TYPICAL CHARACTERISTICS Table of Graphs FIGURE vs Output current 2, 3, 4 OOuuttppuutt vvoollttaaggee vs Free-air temperature 5, 6, 7 Ground current vs Free-air temperature 8, 9 Power supply ripple rejection vs Frequency 10 Output spectral noise density vs Frequency 11 Output impedance vs Frequency 12 Dropout voltage vs Free-air temperature 13 Line transient response 14, 16 Load transient response 15, 17 Output voltage vs Time 18 Dropout voltage vs Input voltage 19 vs Output current, TA = 25°C 21 vs Output current, TJ = 125°C 22 EEqquuiivvaalleenntt sseerriieess rreessiissttaannccee ((EESSRR)) vs Output Current, TA = 25°C 23 vs Output current, TJ = 125°C 24 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS767D301-Q1, TPS767D318-Q1, TPS767D325-Q1 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS SGLS231A − FEBRUARY 2004 − JUNE 2008 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs OUTPUT CURRENT OUTPUT CURRENT 1.7965 3.2835 3.2830 VVTAOI = == 4 23.53.3° VC V 1.7960 VVTAOI = == 2 21.58.8°VC V V V3.2825 − e − age 1.7955 ag3.2820 olt Volt ut V put 3.2815 utp 1.7950 Out − O − O3.2810 VO V 1.7945 3.2805 1.7940 3.2800 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 IO − Output Current − A IO − Output Current − A Figure 2 Figure 3 OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs OUTPUT CURRENT FREE-AIR TEMPERATURE 2.4960 3.32 VO = 2.5 V VO = 3.3 V 2.4955 VI = 3.5 V VI = 4.3 V TA = 25°C 3.31 2.4950 V V 3.30 Output Voltage − 222...444999434550 Output Voltage − 33..2298 IO = 1 A IO = 1 mA − − O O 3.27 V 2.4930 V 3.26 2.4925 2.4920 3.25 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 −60 −40 −20 0 20 40 60 80 100 120 140 IO − Output Current − A TA − Free-Air Temperature − °C Figure 4 Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

TPS767D301-Q1, TPS767D318-Q1, TPS767D325-Q1 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS SGLS231A − FEBRUARY 2004 − JUNE 2008 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 1.815 2.515 VO = 1.8 V VO = 2.5 V VI = 2.8 V 2.510 VI = 3.5 V 1.810 V V 2.505 − 1.805 − e e g g a a 2.500 Volt 1.800 IO = 1 A Volt IO = 1 A ut ut p p 2.495 Out IO = 1 mA Out − O1.795 − O2.490 IO = 1 mA V V 1.790 2.485 1.785 2.480 −60 −40 −20 0 20 40 60 80 100 120 140 −60 −40 −20 0 20 40 60 80 100 120 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 6 Figure 7 GROUND CURRENT GROUND CURRENT vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 92 96 90 VVOI = = 4 3.3.3 V V 94 VVOI = = 2 1.8.8 V V 88 92 IO = 1 mA 90 86 A A μnt − 84 μnt − 88 e e 86 rr 82 rr IO = 500 mA u u d C 80 IO = 1 mA d C 84 n n ou IO = 1 A ou 82 Gr 78 Gr 80 IO = 500 mA 76 78 74 76 IO = 1 A 72 74 −60 −40 −20 0 20 40 60 80 100 120 140 −60 −40 −20 0 20 40 60 80 100 120 140 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 8 Figure 9 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS767D301-Q1, TPS767D318-Q1, TPS767D325-Q1 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS SGLS231A − FEBRUARY 2004 − JUNE 2008 TYPICAL CHARACTERISTICS POWER SUPPLY RIPPLE REJECTION OUTPUT SPECTRAL NOISE DENSITY vs vs FREQUENCY FREQUENCY 90 10−5 Rejection − dB 768000 VIVCTOAOIO == === 41 231. 53A.03° VC μVF ensity −V/Hz 10−6 IO = 7 mAVCTAIO = == 4 21.530° VCμF e D pl 50 e p s Ri oi upply 4300 ctral N IO = 1 A S e wer 20 ut Sp 10−7 o p RR − P 10 − Out PS 0 Vn 10−8 −10 10 100 1k 10k 100k 1M 102 103 104 105 f − Frequency − Hz f − Frequency − Hz Figure 10 Figure 11 OUTPUT IMPEDANCE DROPOUT VOLTAGE vs vs FREQUENCY FREE-AIR TEMPERATURE 0 103 VI = 4.3 V CTAO == 2150° CμF IO = 1 A 102 V Ωpedance − IO = 1 mA Voltage − m 101 m 10−1 ut put I opo 100 IO = 10 mA ut Dr O − − O o D Z IO = 1 A V 10−1 VO = 3.3 V IO = 0 CO = 10 μF 10−2 10−2 101 102 103 104 105 106 −60 −40 −20 0 20 40 60 80 100 120 140 f − Frequency − kHz TA − Free-Air Temperature − °C Figure 12 Figure 13 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

TPS767D301-Q1, TPS767D318-Q1, TPS767D325-Q1 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS SGLS231A − FEBRUARY 2004 − JUNE 2008 TYPICAL CHARACTERISTICS LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE 100 nput Voltage − V 3.8 − Change inOut Voltage − mV 500 VVCTAOIL = === 2 211.850.8 °0VC VμF − I 2.8 ΔVutp −50 VI VO = 1.8 V O IL = 10 mA −100 CL = 10 μF A nmV 20 TA = 25°C nt − 1 − Change iOut Voltage − −200 Output Curre 0.05 ΔVOutp I − O 0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200 t − Time − μs t − Time − μs Figure 14 Figure 15 LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE 100 − V VO = 3.3 V nmV VO = 3.3 V oltage TCAL == 2150° μCF ange iage − 50 TCAL == 12050° CμF nput V 5.3 − ChOut Volt 0 − I ΔVutp −50 VI O 4.3 −100 A V − nm 10 nt 1 Change ioltage − 0 ut Curre 0.5 − Out V −10 Outp 0 ΔVOutp I − O 0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200 t − Time − μs t − Time − μs Figure 16 Figure 17 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS767D301-Q1, TPS767D318-Q1, TPS767D325-Q1 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS SGLS231A − FEBRUARY 2004 − JUNE 2008 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE DROPOUT VOLTAGE vs vs TIME (AT STARTUP) INPUT VOLTAGE 4 900 V − IO = 1A ge 3 800 a ut Volt 2 mV 700 p − ut e 600 O 1 g − O olta 500 V V 0 pout 400 TA = 25°C TA = 125°C o r V D − − 300 e O s D ul V 200 e P TA = −40°C abl 0 100 n E 0 0 20 40 60 80 100 120 140 160 180 200 2.5 3 3.5 4 4.5 5 t − Time − μs VI − Input Voltage − V Figure 18 Figure 19 To Load VI IN OUT + EN CO RL GND ESR Figure 20. Test Circuit for Typical Regions of Stability (Figures 21 through 24) (fixed output options) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

TPS767D301-Q1, TPS767D318-Q1, TPS767D325-Q1 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS SGLS231A − FEBRUARY 2004 − JUNE 2008 TYPICAL CHARACTERISTICS TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE† EQUIVALENT SERIES RESISTANCE† vs vs OUTPUT CURRENT OUTPUT CURRENT 10 10 Ω Ω Region of Instability − Region of Instability − e e c c n n a a st st esi 1 esi 1 R R es VO = 3.3 V es uivalent Seri 0.1 CVTAIo = == 4 24.5.37° VCμF Region of Stability uivalent Seri 0.1 VCVTJOIo = === 4 143.23..735 V °μVCF Region of Stability q q E E − − R R S S E E Region of Instability Region of Instability 0.01 0.01 0 200 400 600 800 1000 0 200 400 600 800 1000 IO − Output Current − mA IO − Output Current − mA Figure 21 Figure 22 TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE† EQUIVALENT SERIES RESISTANCE† vs vs OUTPUT CURRENT OUTPUT CURRENT 10 10 Ω Region of Instability − Region of Instability Ω nce e − a c Resist 1 sistan 1 Equivalent Series 0.1 VVCTAOIo = === 4 223.523.3° μVC VF Region of Stability uivalent Series Re 0.1 VCVTJOIo = === 4 123.232.35 Vμ °VCF Region of Stability R − − Eq ES R Region of Instability ES Region of Instability 0.01 0.01 0 200 400 600 800 1000 0 200 400 600 800 1000 IO − Output Current − mA IO − Output Current − mA Figure 23 Figure 24 †Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS767D301-Q1, TPS767D318-Q1, TPS767D325-Q1 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS SGLS231A − FEBRUARY 2004 − JUNE 2008 APPLICATION INFORMATION The features of the TPS767D3xx family (low-dropout voltage, ultra low quiescent current, power-saving shutdown mode, and a supply-voltage supervisor) and the power-dissipation properties of the TSSOP PowerPAD package have enabled the integration of the dual LDO regulator with high output current for use in DSP and other multiple voltage applications. Figure 25 shows a typical dual-voltage DSP application. R1 R2 100 kΩ 100 kΩ U1 TPS767D325 PG 1 28 NC 1RESET 2 27 NC NC RESET to DSP 3 26 1GND NC 4 25 VC549 1EN 1FB/NC DSP 5 V 5 24 1IN 1OUT 6 23 2.5 V C0 1IN 1OUT CVDD 1 μF 7 22 (Core NC 2RESET 8 21 D1 Supply) NC NC 9 20 C3 2GND NC 10 19 33 μF + 8 2EN NC 4 1 11 18 4 D3 2IN 2OUT L 12 17 D DL5817 2IN 2OUT 13 16 NC NC 14 15 D2 NC NC 3.3 V C1 DVDD 1 μF (I/O Supply) C2 33 μF GND GND Figure 25. Dual-Voltage DSP Application DSP power requirements include very high transient currents that must be considered in the initial design. This design uses higher-valued output capacitors to handle the large transient currents. device operation The TPS767D3xx features very low quiescent current, which remain virtually constant even with varying loads. Conventional LDO regulators use a pnp pass element, the base current of which is directly proportional to the load current through the regulator (I = I /β). Close examination of the data sheets reveals that these devices B C are typically specified under near no-load conditions; actual operating currents are much higher as evidenced by typical quiescent current versus load current curves. The TPS767D3xx uses a PMOS transistor to pass current; because the gate of the PMOS is voltage driven, operating current is low and invariable over the full load range. The TPS767D3xx specifications reflect actual performance under load condition. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

TPS767D301-Q1, TPS767D318-Q1, TPS767D325-Q1 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS SGLS231A − FEBRUARY 2004 − JUNE 2008 device operation (continued) Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into dropout. The resulting drop in β forces an increase in I to maintain the load. During power up, this translates B to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems, it means rapid battery discharge when the voltage decays below the minimum required for regulation. The TPS767D3xx quiescent current remains low even when the regulator drops out, eliminating both problems. The TPS767D3xx family also features a shutdown mode that places the output in the high-impedance state (essentially equal to the feedback-divider resistance) and reduces quiescent current to under 2 μA. If the shutdown feature is not used, EN should be tied to ground. Response to an enable transition is quick; regulated output voltage is typically reestablished in 120 μs. minimum load requirements The TPS767D3xx family is stable even at zero load; no minimum load is required for operation. FB - pin connection (adjustable version only) The FB pin is an input pin to sense the output voltage and close the loop for the adjustable option. The output voltage is sensed through a resistor divider network as is shown in Figure 27 to close the loop. Normally, this connection should be as short as possible; however, the connection can be made near a critical circuit to improve performance at that point. Internally, FB connects to a high-impedance wide-bandwidth amplifier and noise pickup feeds through to the regulator output. Routing the FB connection to minimize/avoid noise pickup is essential. In fixed output options this pin is a no connect. external capacitor requirements An input capacitor is not required; however, a ceramic bypass capacitor (0.047 pF to 0.1 μF) improves load transient response and noise rejection when the TPS767D3xx is located more than a few inches from the power supply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load transients with fast rise times are anticipated. Like all low dropout regulators, the TPS767D3xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance value is 10 μF and the ESR (equivalent series resistance) must be between 60 mΩ and 1.5 Ω. Capacitor values 10 μF or larger are acceptable, provided the ESR is less than 1.5 Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements described previously. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS767D301-Q1, TPS767D318-Q1, TPS767D325-Q1 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS SGLS231A − FEBRUARY 2004 − JUNE 2008 external capacitor requirements (continued) When necessary to achieve low height requirements along with high output current and/or high ceramic load capacitance, several higher ESR capacitors can be used in parallel to meet the previous guidelines. TPS767D3xx 5 28 RESET VI IN RESET 6 IN 250 kΩ 24 C1 OUT VO 0.15 0 μ VF 4 EN OUT 23 + CO 10 μF GND 3 Figure 26. Typical Application Circuit (Fixed Versions) for Single Channel programming the TPS767D301 adjustable LDO regulator The output voltage of the TPS767D301 adjustable regulator is programmed using an external resistor divider as shown in Figure 27. The output voltage is calculated using: (cid:3) (cid:5) V (cid:2)V (cid:6) 1(cid:8)R1 (1) O ref R2 where: V = 1.1834 V typ (the internal reference voltage) ref Resistors R1 and R2 should be chosen for approximately 50-μA divider current. Lower value resistors can be used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage currents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 30.1kΩ to set the divider current at 50 μA and then calculate R1 using: (cid:3) (cid:5) V R1(cid:2) O (cid:7)1 (cid:6)R2 (2) V ref OUTPUT VOLTAGE TPS767D301 PROGRAMMING GUIDE OUTPUT R1 R2 UNIT VI IN RESET RESET Output VOLTAGE 0.1 μF 2.5 V 33.2 30.1 kΩ 250 kΩ >2.7 V 3.3 V 53.6 30.1 kΩ EN OUT VO 3.6 V 61.9 30.1 kΩ <0.5V + R1 CO 4 75V 90.8 30.1 kΩ FB / NC 10 μF GND R2 Figure 27. TPS767D301 Adjustable LDO Regulator Programming POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

TPS767D301-Q1, TPS767D318-Q1, TPS767D325-Q1 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS SGLS231A − FEBRUARY 2004 − JUNE 2008 Reset indicator The TPS767D3xx features a RESET output that can be used to monitor the status of the regulator. The internal comparator monitors the output voltage: when the output drops to 95% (typical) of its regulated value, the RESET output transistor turns on, taking the signal low. The open-drain output requires a pullup resistor. If not used, it can be left floating. RESET can be used to drive power-on reset circuitry or as a low-battery indicator. regulator protection The TPS767D3xx PMOS-pass transistor has a built-in back-gate diode that safely conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The TPS767D3xx also features internal current limiting and thermal protection. During normal operation, the TPS767D3xx limits output current to approximately 1.7 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130°C(typ), regulator operation resumes. power dissipation and junction temperature Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, P , and the actual dissipation, P , which must be less than D(max) D or equal to P . D(max) The maximum-power-dissipation limit is determined using the following equation: T max(cid:7)T P (cid:2) J A D(max) R(cid:2)JA where: TJmax is the maximum allowable junction temperature RθJA is the thermal resistance junction-to-ambient for the package, i.e., 27.9°C/W for the 28-terminal PWP with no airflow. TA is the ambient temperature. The regulator dissipation is calculated using: (cid:3) (cid:5) P (cid:2) V (cid:7)V (cid:6)I D I O O Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the thermal protection circuit. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS767D301QPWPRQ1 ACTIVE HTSSOP PWP 28 2000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 767D301Q1 & no Sb/Br) TPS767D318QPWPRQ1 ACTIVE HTSSOP PWP 28 2000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 767D318Q1 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 OTHER QUALIFIED VERSIONS OF TPS767D3-Q1 : •Catalog: TPS767D3 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 5-Jul-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS767D301QPWPRQ1 HTSSOP PWP 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 TPS767D318QPWPRQ1 HTSSOP PWP 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 5-Jul-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS767D301QPWPRQ1 HTSSOP PWP 28 2000 350.0 350.0 43.0 TPS767D318QPWPRQ1 HTSSOP PWP 28 2000 350.0 350.0 43.0 PackMaterials-Page2

GENERIC PACKAGE VIEW PWP 28 PowerPADTM TSSOP - 1.2 mm max height 4.4 x 9.7, 0.65 mm pitch SMALL OUTLINE PACKAGE Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224765/A www.ti.com

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